WO2024032628A1 - 印制电路板以及制备方法 - Google Patents

印制电路板以及制备方法 Download PDF

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Publication number
WO2024032628A1
WO2024032628A1 PCT/CN2023/111810 CN2023111810W WO2024032628A1 WO 2024032628 A1 WO2024032628 A1 WO 2024032628A1 CN 2023111810 W CN2023111810 W CN 2023111810W WO 2024032628 A1 WO2024032628 A1 WO 2024032628A1
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WO
WIPO (PCT)
Prior art keywords
coaxial
hole
printed circuit
circuit board
large hole
Prior art date
Application number
PCT/CN2023/111810
Other languages
English (en)
French (fr)
Inventor
刘昊
桂来来
杨海云
Original Assignee
生益电子股份有限公司
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Filing date
Publication date
Application filed by 生益电子股份有限公司 filed Critical 生益电子股份有限公司
Publication of WO2024032628A1 publication Critical patent/WO2024032628A1/zh

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections

Definitions

  • the embodiments of the present application relate to the technical field of printed circuit boards, and in particular, to a printed circuit board and a preparation method.
  • Coaxial via technology can achieve true signal impedance continuity, provide excellent ground (GND) return, and effectively reduce crosstalk between vias and between vias and traces.
  • the coaxial hole process is a pre-research for 5G high-frequency solutions. The purpose is to imitate the coaxial line design to obtain better waveguide characteristics.
  • the coaxial hole of the circuit board is used in the radio frequency coaxial cable.
  • the transmission loop consists of the inner conductor and the insulating medium. It consists of three parts: and outer conductor. These three parts are concentric, that is, they have a common central axis, so the accuracy of the coaxial hole position is required to be high.
  • the coaxial hole design method is to drill a large coaxial hole in the daughter board. After the large coaxial hole passes through the resin plug hole, a small coaxial hole is drilled in the middle of the large coaxial hole that passes through the resin plug hole. Usually the large coaxial hole is It is not in the same layer as the coaxial holes, and the hole diameters are very different. The number of spacing layers is N (N ⁇ 1).
  • the requirements for some electrical properties and performance indicators of coaxial holes are not clear.
  • the only determinable indicator is the alignment of coaxial holes, which is required to be ⁇ 2mil.
  • the main method is the slice confirmation method. Although this method can quantify the alignment data, sampling measurement will cause the substrate to be scrapped. Therefore, consider using a method that does not require slice confirmation and measures directly with tools. Use this method to confirm the alignment of the coaxial holes.
  • Embodiments of the present application provide a printed circuit board and a preparation method to simplify the detection process of the coaxial hole alignment of the printed circuit board and reduce the detection cost.
  • a printed circuit board includes an inner layer and an outer layer, and further includes:
  • the inner layer of the printed circuit board includes at least one group of coaxial metallized via holes, wherein each group of coaxial metallized via holes includes coaxial large holes and coaxial small holes, and the coaxial large holes and the coaxial small holes are Insulating materials are arranged between coaxial small holes.
  • the conductive layer of the coaxial large holes includes a coaxial large hole layer.
  • the conductive layer of the coaxial small holes includes including a coaxial small hole layer, the coaxial large hole layer includes a coaxial large hole opening conductive layer and a coaxial large hole inner conductive layer, the coaxial small hole layer includes a coaxial small hole opening conductive layer and The conductive layer inside the coaxial small hole; in a group of coaxial metallized vias, the coaxial large hole conductive layer is located on a different layer than the coaxial small hole conductive layer located on the same layer of the printed circuit board. ;
  • the printed circuit board also includes a coaxial large hole conductive structure and a coaxial small hole conductive structure.
  • the coaxial large hole conductive structure is connected to the coaxial large hole conductive layer.
  • the coaxial small hole is conductive.
  • the structure is connected to the coaxial small hole conductive layer, and the conduction status of the coaxial large hole conductive structure and the coaxial small hole conductive structure is related to the alignment of the coaxial metallized via hole, Wherein, the alignment of the coaxial metalized via holes includes the deviation amount and/or the offset direction of the coaxial small holes.
  • the printed circuit board further includes a coaxial large hole connection pad, a connection through hole and a connection blind hole;
  • the coaxial large hole connection pad and the coaxial large hole opening conductive layer are located on the same layer, located outside the coaxial large hole and connected to the conductive layer of the coaxial large hole opening;
  • the connection through hole covers the coaxial large hole connection pad in the orthographic projection of the printed circuit board In at least part of the orthographic projection of the printed circuit board;
  • the hole bottom pad connecting the blind hole and the coaxial small hole opening conductive layer are located on the same layer, and the hole bottom pad connecting the blind hole is on
  • the front projection of the printed circuit board at least covers the front projection of the area inside the conductive layer ring in the coaxial large hole on the printed circuit board, and is insulated from the connection through hole;
  • the outer layer of the printed circuit board includes a coaxial small hole test pad and a coaxial large hole test pad.
  • the coaxial large hole test pad covers at least part of the opening of the connection through hole, and the The coaxial small hole test pad covers at least part of the opening of the connecting blind hole;
  • the coaxial large hole connection pad, the connection through hole and the coaxial large hole test pad constitute the coaxial large hole conductive structure;
  • the connection blind hole and the coaxial small hole test pad constitute the coaxial large hole test pad.
  • the conduction condition of the coaxial large hole test pad and the coaxial small hole test pad is related to the alignment of the coaxial metallized via hole, wherein the alignment of the coaxial metallized via hole Accuracy includes the deviation amount and/or deviation direction of the coaxial holes.
  • n groups of coaxial metallized vias are included, wherein the value of n includes an integer greater than or equal to 1;
  • the apertures of the n coaxial small holes include: first aperture, second aperture...nth aperture;
  • the aperture differences between the n coaxial small holes and the coaxial large holes include: first aperture difference, second aperture difference...nth aperture difference, where the first aperture difference>the second aperture difference>... >nth aperture difference;
  • the aperture diameter of the coaxial small hole in the i-th group of coaxial metallized via holes is the i-th aperture
  • the aperture difference between the coaxial small hole of the i-th aperture and the coaxial large hole is the i-th aperture difference
  • the i Values include greater than or equal to 1, and an integer less than or equal to n.
  • the conductive layer in the coaxial large hole includes at least two sector-shaped rings provided with insulation;
  • the coaxial large-hole connection pads include at least two insulated sector-shaped connection pads.
  • the sector-shaped connection pads are arranged around the sector-shaped ring, and the sector-shaped connection pads are connected to the sector-shaped ring in a one-to-one correspondence. ;
  • connection through holes include at least two, and the front projection of the connection through holes on the printed circuit board covers at least part of the front projection of the sector-shaped connection pad on the printed circuit board;
  • the coaxial large hole test pads include at least two, and the coaxial large hole test pads cover at least part of the opening of the connection through hole in one-to-one correspondence.
  • the coaxial small holes in the coaxial small hole conductive layer and the coaxial large hole conductive layer located on the same side of the printed circuit board, the coaxial small holes
  • the number of spacing layers between the orifice conductive layer and the outer layer is smaller than the number of spacing layers between the coaxial large hole aperture conductive layer and the outer layer.
  • a method for preparing a printed circuit board including:
  • At least one coaxial large hole is formed on the inner layer of the printed circuit board, wherein the coaxial large hole is a metallized via hole, and the conductive layer of the coaxial large hole includes a coaxial large hole layer.
  • the macroporous layer includes two coaxial macropore conductive layers and a coaxial macropore inner conductive layer;
  • the side of the coaxial large hole conductive layer facing away from the printed circuit board is laminated to reach the coaxial small hole conductive layer;
  • the structure after lamination forms at least one coaxial small hole, wherein the coaxial small hole is a metallized via hole, the conductive layer of the coaxial small hole includes a coaxial small hole layer, and the coaxial small hole
  • the layer includes a coaxial small hole opening conductive layer and a coaxial small hole inner conductive layer; in a group of coaxial metallized via holes, the coaxial large hole opening conductive layer is located on the same layer as the printed circuit board.
  • Coaxial pinhole layers are located in different layers;
  • It also includes forming a coaxial large hole conductive structure and a coaxial small hole conductive structure, the coaxial large hole conductive structure is connected to the coaxial large hole conductive layer, and the coaxial small hole conductive structure is connected to the coaxial small hole conductive structure.
  • the axial small hole orifice conductive layer is connected, the conduction condition of the coaxial large hole conductive structure and the coaxial small hole conductive structure is related to the alignment of the coaxial metallized via hole, wherein the coaxial large hole conductive structure and the coaxial small hole conductive structure are related to the alignment of the coaxial metallized via hole.
  • the alignment of the shaft metallized vias includes the offset amount and/or offset direction of the coaxial holes.
  • the coaxial large hole conductive structure includes coaxial large hole connection pads, connection through holes and coaxial large hole test pads;
  • the coaxial small hole conductive structure includes connection blind holes and coaxial small holes test pad;
  • a coaxial large hole connection pad is formed, wherein the coaxial large hole connection pad and the coaxial large hole hole are The mouth conductive layer is located on the same layer, located outside the coaxial large hole and connected to the coaxial large hole hole conductive layer;
  • the coaxial large holes are plugged with insulating materials
  • the structure after lamination forms at least one coaxial small hole, wherein the coaxial small hole is a metallized via hole, the conductive layer of the coaxial small hole includes a coaxial small hole layer, and the coaxial small hole
  • the layer includes a coaxial small hole opening conductive layer and a coaxial small hole inner conductive layer; in a group of coaxial metallized via holes, the coaxial large hole opening conductive layer is located on the same layer as the printed circuit board.
  • Coaxial pinhole layers are located in different layers;
  • the laminated structure forms at least one coaxial small hole, it also includes:
  • a bottom pad connecting the blind hole is formed, wherein the bottom pad connecting the blind hole and the coaxial small hole opening conductive layer are located on the same layer, and the bottom pad connecting the blind hole is on the
  • the orthographic projection of the printed circuit board at least covers the orthographic projection of the area within the conductive layer ring in the coaxial large hole on the printed circuit board;
  • connection through holes and blind connection holes cover the front projection of the printed circuit board.
  • the coaxial large hole connection pad is at least part of the front projection of the printed circuit board, and the hole bottom pad of the connection blind hole is insulated from the connection through hole;
  • a coaxial small hole test pad and a coaxial large hole test pad are formed on the outer layer of the printed circuit board, wherein the coaxial large hole test pad covers at least part of the opening of the connection through hole.
  • the conduction status of the coaxial large hole test pad and the coaxial small hole test pad is related to the alignment of the coaxial metallized via hole, wherein the coaxial metallized via hole Alignment includes the amount and/or direction of deviation of the coaxial holes.
  • the structure after lamination forms at least one coaxial hole, including:
  • Drill n coaxial holes with different diameters in the laminated structure
  • the apertures of the n coaxial holes include: a first aperture, a second aperture...the nth aperture, and the value of n includes an integer greater than or equal to 1;
  • the n coaxial holes are
  • the aperture difference of the coaxial large hole includes: the first aperture difference, the second aperture difference...the nth aperture difference, where the first aperture difference>the second aperture difference>...>nth aperture difference; the i-th group
  • the aperture diameter of the coaxial small hole in the coaxial metallized via hole is the i-th aperture
  • the aperture difference between the coaxial small hole of the i-th aperture and the coaxial large hole is the i-th aperture difference
  • the value of i includes An integer greater than or equal to 1 and less than or equal to n.
  • form at least one coaxial large hole on the inner layer of the printed circuit board including:
  • the coaxial large holes are formed into metallized vias through copper plating and electroplating processes, wherein the conductive layer of the coaxial large holes includes a coaxial large hole layer, and the coaxial large hole layer includes two coaxial large holes. Orifice conductive layer and the same Conductive layer inside the large hole of the shaft;
  • a plugging device is inserted into the coaxial large hole, wherein the plugging device includes an inner hard bracket and a flexible outer layer, and the cross section of the inner hard bracket includes a solid portion and a portion distributed in the At least two fan-shaped connecting parts on the edge of the solid part, with a hollow area provided between the fan-shaped connecting parts;
  • wet etching is performed on the conductive layer in the coaxial large hole to form at least two coaxial large holes with insulated sector-shaped rings;
  • Forming the coaxial large hole connection pad includes:
  • connection through-holes cover the locations of the sector-shaped connection pads one by one in the orthographic projection of the printed circuit board.
  • the disk is at least partially in the orthographic projection of the printed circuit board.
  • the side of the coaxial large hole conductive layer facing away from the printed circuit board is laminated to the coaxial small hole conductive layer, including:
  • At least one layer is laminated on the side of the coaxial large hole conductive layer facing away from the printed circuit board to reach the coaxial small hole conductive layer.
  • the coaxial large hole conductive structure serves as the first electrical signal extraction structure of the coaxial large hole; the coaxial small hole conductive structure serves as the second electrical signal extraction structure of the coaxial small hole.
  • Figure 1 is a schematic structural diagram of a printed circuit board provided according to an embodiment of the present application.
  • Figure 2 is a schematic structural diagram of another printed circuit board provided according to an embodiment of the present application.
  • Figure 3 is a schematic structural diagram of yet another printed circuit board provided according to an embodiment of the present application.
  • Figure 4 is a top view of the three sets of coaxial metallized vias in Figure 3;
  • Figure 5 is a perspective view of the three sets of coaxial metallized vias in Figure 3;
  • Figure 6 is a top view of the three sets of coaxial metallized vias and coaxial large hole connection pads in Figure 5;
  • Figure 7 is a three-dimensional expanded view of the three groups of coaxial metallized vias in Figure 5;
  • Figure 8 is a top view of the coaxial small hole test pad and the coaxial large hole test pad
  • Figure 9 is a flow chart of a method for preparing a printed circuit board according to an embodiment of the present application.
  • Figure 10 is a schematic structural diagram corresponding to each step of a printed circuit board preparation method provided according to an embodiment of the present application.
  • Figure 11 is a schematic structural diagram corresponding to each step of another printed circuit board preparation method provided according to an embodiment of the present application.
  • Figure 12 is a schematic structural diagram corresponding to each step of another printed circuit board preparation method provided according to an embodiment of the present application.
  • Figure 13 is a schematic structural diagram corresponding to each step of another printed circuit board preparation method provided according to an embodiment of the present application.
  • Figure 14 is a schematic structural diagram corresponding to each step of another printed circuit board preparation method provided according to an embodiment of the present application.
  • Figure 15 is a schematic structural diagram corresponding to each step of another printed circuit board preparation method provided according to an embodiment of the present application.
  • Figure 16 is a flow chart of another method for preparing a printed circuit board according to an embodiment of the present application.
  • Figure 17 is a flow chart of yet another printed circuit board preparation method provided according to an embodiment of the present application.
  • Figure 18 is a structural diagram of each step of another printed circuit board preparation method provided according to an embodiment of the present application.
  • Figure 19 is a structural diagram of each step of another printed circuit board preparation method provided according to an embodiment of the present application.
  • Figure 20 is a structural diagram of each step of another printed circuit board preparation method provided according to an embodiment of the present application.
  • Figure 21 is a structural diagram of each step of another printed circuit board preparation method provided according to an embodiment of the present application.
  • Figure 22 is a structural diagram of each step of another printed circuit board preparation method provided according to an embodiment of the present application.
  • Figure 23 is a structural diagram of each step of another printed circuit board preparation method provided according to an embodiment of the present application.
  • Figure 24 is a structural diagram of each step of another printed circuit board preparation method provided according to an embodiment of the present application.
  • Figure 25 is a structural diagram of each step of another printed circuit board preparation method provided according to an embodiment of the present application.
  • Figure 26 is a schematic flow chart of a method for testing the coaxial hole alignment of a printed circuit board according to an embodiment of the present application
  • Figure 27 is a schematic flow chart of another method for testing the coaxial hole alignment of a printed circuit board according to an embodiment of the present application.
  • FIG. 28 is a schematic flow chart of yet another method for testing the coaxial hole alignment of a printed circuit board according to an embodiment of the present application.
  • An embodiment of the present application provides a printed circuit board.
  • the printed circuit board includes: the inner layer of the printed circuit board includes at least one group of coaxial metallized via holes, wherein each group of coaxial metallized via holes includes coaxial large holes and coaxial small holes, and the coaxial large holes An insulating material is provided between the coaxial small holes.
  • the conductive layer of the coaxial large holes includes a coaxial large hole layer.
  • the conductive layer of the coaxial small holes includes a coaxial small hole layer.
  • the coaxial large hole layer includes the coaxial large holes.
  • the hole conductive layer and the coaxial large hole inner conductive layer includes the coaxial small hole hole entrance conductive layer and the coaxial small hole inner conductive layer; in a group of coaxial metallized vias, the coaxial In the large-hole conductive layer, the coaxial small-hole conductive layer located on the same layer of the printed circuit board is located on a different layer; the printed circuit board also includes a coaxial large-hole conductive structure and a coaxial small-hole conductive structure.
  • the large hole conductive structure is connected to the coaxial large hole conductive layer
  • the coaxial small hole conductive structure is connected to the coaxial small hole conductive layer
  • the alignment degree of the coaxial metallized via hole is related, wherein the alignment degree of the coaxial metallized via hole includes the deviation amount and/or offset direction of the coaxial small hole.
  • the coaxial large hole conductive structure serves as the first electrical signal extraction structure of the coaxial large hole; the coaxial small hole conductive structure serves as the second electrical signal extraction structure of the coaxial small hole.
  • the printed circuit board also includes a coaxial large hole connection pad, a connection through hole, and a connection blind hole; the coaxial large hole connection pad and the coaxial large hole conductive layer are located on the same layer, and are located on the coaxial large hole.
  • the outside of the hole is connected to the conductive layer of the coaxial large hole opening; the orthographic projection of the connecting through hole on the printed circuit board covers at least part of the orthographic projection of the coaxial large hole connecting pad on the printed circuit board; the blind hole is connected The bottom pad of the hole is located on the same layer as the conductive layer of the coaxial small hole opening.
  • the orthographic projection of the bottom pad of the hole connected to the blind hole on the printed circuit board at least covers the area within the ring of the conductive layer in the coaxial large hole in the printed circuit.
  • the coaxial large hole connection pad, the connection through hole and the coaxial large hole test pad form a coaxial large hole conductive structure; the connection of the blind hole and the coaxial small hole test pad forms a coaxial small hole conductive structure.
  • the conduction status of the coaxial large hole test pad and the coaxial small hole test pad is related to the alignment of the coaxial metallized via hole.
  • the alignment of the coaxial metallized via hole includes the coaxial small hole. Amount and/or direction of offset.
  • FIG. 1 is a schematic structural diagram of a printed circuit board according to an embodiment of the present application.
  • Figure 2 is a schematic structural diagram of another printed circuit board according to an embodiment of the present application.
  • the inner layer of the printed circuit board includes three sets of coaxial metallized vias.
  • Three coaxial large holes M0, one coaxial large hole M0 and one coaxial small hole constitute a set of coaxial metalized vias.
  • the coaxial small holes include the first coaxial small hole m1 and the second coaxial small hole m2. and the third coaxial hole m3.
  • the conductive layer of the coaxial large hole M0 includes the coaxial large hole layer
  • the conductive layer of the coaxial small hole includes the coaxial small hole layer
  • the coaxial large hole layer includes the coaxial large hole orifice conductive layer Ls and the coaxial large hole hole.
  • the inner conductive layer L01 and the coaxial pinhole layer include the coaxial pinhole opening conductive layer Ls-q and the coaxial pinhole inner conductive layer L02, where the value of q includes an integer greater than or equal to 1.
  • An insulating material such as a resin material, is disposed between the large coaxial hole M0 and the small coaxial hole.
  • the printed circuit board also includes a coaxial large hole connecting pad 11, a connecting through hole 12 and a blind connecting hole 13; the coaxial large hole connecting pad 11, the connecting through hole 12 and the coaxial large hole test pad 15 form a coaxial Large hole conductive structure; connecting the blind hole 13 and the coaxial small hole test pad 16 forms a coaxial small hole conductive structure.
  • the coaxial large hole connection pad 11 and the coaxial large hole orifice conductive layer Ls are located on the same layer and are connected to the coaxial large hole orifice conductive layer Ls; the connection through hole 12 covers the coaxial axis in the orthographic projection of the printed circuit board
  • the large hole connecting pad 11 is in the orthographic projection of the printed circuit board;
  • the hole bottom pad 14 connecting the blind hole 13 is located on the same layer as the coaxial small hole opening conductive layer Ls-q, and is connected to the hole bottom of the blind hole 13
  • the orthographic projection of the pad 14 on the printed circuit board covers the orthographic projection of the area within the conductive layer L01 ring in the coaxial large hole on the printed circuit board, and is insulated from the connection through hole 12 .
  • the outer layer of the printed circuit board includes a coaxial small hole test pad 16 and a coaxial large hole test pad 15.
  • the coaxial large hole test pad 15 covers the opening connecting the through hole 12, and the coaxial small hole test pad 15 16 covers the orifice connecting the blind hole 13.
  • the conduction condition of the coaxial large hole test pad 15 and the coaxial small hole test pad 16 is related to the alignment of the coaxial metallized via hole, where the coaxial metallization
  • the alignment of the vias includes the deviation amount and/or offset direction of the coaxial holes.
  • the first coaxial small hole m1 is not in contact with the coaxial large hole M0.
  • the relative coaxial large hole M0 is an open circuit connection.
  • the second coaxial small hole m2 is not in contact with the coaxial large hole M0, and the second coaxial small hole m2 is disconnected from the coaxial large hole M0.
  • the third coaxial small hole m3 is not in contact with the coaxial large hole M0, and the third coaxial small hole m3 is disconnected from the coaxial large hole M0.
  • the first coaxial small hole m1 is in contact with the coaxial large hole M0, and the first coaxial small hole m1 is connected in a short circuit with respect to the coaxial large hole M0.
  • the second small coaxial hole m2 is in contact with the large coaxial hole M0, and the second small coaxial hole m2 is connected in a short circuit with respect to the large coaxial hole M0.
  • the third coaxial small hole m3 is in contact with the coaxial large hole M0, and the third coaxial small hole m3 is connected in a short circuit with respect to the coaxial large hole M0.
  • the coaxial large hole connecting pad 11 and the coaxial large hole orifice conductive layer Ls are located on the same layer and are connected to the coaxial large hole orifice conductive layer Ls.
  • the connection through hole 12 is in the orthographic projection of the printed circuit board.
  • the coaxial large hole connection pad 11 is covered in the front projection part of the printed circuit board, the coaxial large hole test pad 15 covers the opening of the connection through hole 12 , the coaxial large hole connection pad 11 and the connection through hole 12
  • the coaxial large hole layer of the coaxial large hole M0 and the coaxial large hole test pad 15 can form a path.
  • the hole bottom pad 14 connected to the blind hole 13 is located on the same layer as the coaxial small hole opening conductive layer Ls-q.
  • the orthographic projection of the hole bottom pad 14 connected to the blind hole 13 on the printed circuit board at least covers the coaxial large hole.
  • the area within the ring of the conductive layer L01 in the hole is the orthographic projection of the printed circuit board and is insulated from the connecting through hole 12.
  • the coaxial small hole test pad 16 covers the opening of the blind hole 13 and is connected to the bottom of the blind hole 13.
  • the bonding pad 14 and the connecting blind hole 13 serve as the second electrical signal extraction structure of the coaxial hole layer, and the coaxial hole and the coaxial hole test pad 16 can form a path.
  • the coaxial large hole connection pad 11 is located outside the coaxial large hole M0, and the connection through hole 12 covers at least the front projection of the coaxial large hole connection pad 11 on the printed circuit board. part, the connection through hole 12 and the connection blind hole 13 are insulated. Therefore, if the coaxial large hole test pad 15 and the coaxial small hole test pad 16 are connected, there must be a connection between the coaxial small hole and the coaxial large hole. Only when the hole M0 comes into contact will the coaxial large hole test pad 15 and the coaxial small hole test pad 16 form a path and form a short circuit connection.
  • the coaxial large hole connecting pad and the connecting through hole are used as the first electrical signal extraction structure of the coaxial large hole, and the coaxial large hole and the coaxial large hole test pad can be formed into a path; connection The bottom pad of the blind hole and the connecting blind hole serve as the second electrical signal extraction structure of the coaxial hole, and the coaxial hole and the coaxial hole test pad can form a path.
  • the coaxial large hole connecting pad is located outside the coaxial large hole, and the orthographic projection of the connecting through hole on the printed circuit board covers at least part of the orthographic projection of the coaxial large hole connecting pad on the printed circuit board, and the connecting through hole Insulation is provided between the hole and the connecting blind hole.
  • the printed circuit board provided in this embodiment determines the deviation of the coaxial small hole by detecting the continuity of the coaxial large hole test pad and the coaxial small hole test pad.
  • the amount and/or offset direction eliminates the need to detect the alignment of the coaxial metal vias in the inner layer through a slicing process, achieving non-destructive testing, simplifying the testing process, and thereby saving testing costs.
  • the printed circuit board includes n groups of coaxial metallized vias, where the value of n includes an integer greater than or equal to 1;
  • the apertures of the n coaxial holes include: a first aperture, a second aperture ...nth aperture;
  • the aperture difference between the n coaxial small holes and the coaxial large holes includes: the first aperture difference, the second aperture difference...the nth aperture difference, where the first aperture difference > the second aperture difference > «>The nth hole diameter difference;
  • the hole diameter of the coaxial small hole in the i-th group of coaxial metallized via holes is the i-th hole diameter, and the hole diameter difference between the coaxial small hole of the i-th hole diameter and the coaxial large hole is the i-th hole diameter Difference
  • the value of i includes integers greater than or equal to 1 and less than or equal to n.
  • Figure 3 is a schematic structural diagram of yet another printed circuit board provided according to an embodiment of the present application.
  • Figure 4 is a top view of three sets of coaxial metallized vias in Figure 3.
  • the aperture of the first coaxial small hole m1 is the first aperture d1
  • the aperture of the second coaxial small hole m2 is the second aperture d2
  • the aperture diameter of the third coaxial small hole m3 is the third aperture d3.
  • the difference between the aperture diameter of the first coaxial small hole m1 and the coaxial large hole M0 is the first aperture difference ⁇ d1
  • the difference between the aperture diameter of the second coaxial small hole m2 and the coaxial large hole M0 is the second aperture difference ⁇ d2
  • the difference between the aperture diameter of the third coaxial small hole m3 and the aperture diameter of the coaxial large hole M0 is the third aperture difference ⁇ d3.
  • the hole test pad 15 and the coaxial small hole test pad 16 do not form a path and are disconnected.
  • the third coaxial small hole m3 has a deviation in a certain offset direction relative to the coaxial large hole M0.
  • the third coaxial small hole m3 is in contact with the coaxial large hole M0, and the coaxial large hole test pad 15 is in contact with the coaxial small hole M0.
  • Hole test pad 16 forms a via and is a short circuit connection.
  • the aperture of the fourth coaxial small hole m4 is the fourth aperture d4, and the fourth coaxial small hole m4 and The aperture difference of the coaxial large hole M0 is the fourth aperture difference ⁇ d4.
  • the aperture difference of the fourth coaxial small hole m4 and the coaxial large hole M0 is greater than the aperture difference of the third coaxial small hole m3 relative to the coaxial large hole M0.
  • the offset of the fourth coaxial small hole m4 and the coaxial large hole M0 makes the two in contact, the coaxial small hole test pad 16 of the fourth coaxial small hole m4 and the coaxial large hole of the coaxial large hole M0
  • the test pad 15 forms a via and is a short-circuit connection.
  • the hole diameter difference between the third coaxial small hole m3 and the coaxial large hole M0 is the deviation of the coaxial small hole.
  • the above-mentioned printed circuit board can quickly and accurately obtain the deviation of the coaxial holes in the coaxial metallized via holes.
  • the conductive layer in the coaxial large hole hole includes at least two insulated sector-shaped rings;
  • the coaxial large-hole connection pad includes at least two insulating sector-shaped connection pads, and the sector-shaped connection pads are arranged around the sector ring, And the sector-shaped connection pads are connected to the sector-shaped ring in a one-to-one correspondence;
  • the connection through-holes include at least two, and the connection through-holes in the orthographic projection of the printed circuit board cover one-to-one areas located in the orthographic projection of the sector-shaped connection pad in the printed circuit board.
  • At least part of the coaxial large hole test pads includes at least two coaxial large hole test pads, and the coaxial large hole test pads cover at least part of the opening of the connecting through hole in one-to-one correspondence.
  • Figure 5 is a perspective view of three sets of coaxial metallized vias in Figure 3.
  • Figure 6 is a top view of the three sets of coaxial metallized vias in Figure 5.
  • FIG. 7 is a three-dimensional expanded view of the three groups of coaxial metallized vias in FIG. 5 .
  • Figure 8 is a top view of the coaxial small hole test pad and the coaxial large hole test pad. Among them, two connecting through holes are shown on the periphery of each group of coaxial metallized via holes in FIG. 7 .
  • the conductive layer L01 in the coaxial large hole includes eight insulated sector rings, namely the first sector ring A, the second sector ring B, the third sector ring C, and the fourth sector ring. D.
  • the fifth sector ring E, the sixth sector ring F, the seventh sector ring G and the eighth sector ring H; the coaxial large hole connection pad 11 includes 8 insulated sector connection pads, each of which is the first sector ring.
  • the sector-shaped connection pads are arranged around the sector ring, and the sector connection pads are connected to the sector ring in a one-to-one correspondence; the connection through holes 12 include eight, and the connection through holes 12 are on the printed circuit board.
  • the coaxial large hole test pads in Figure 8 include 8 coaxial large hole test pads, which are the first coaxial large hole test pad 150a, the second coaxial large hole test pad 150b, and the first coaxial large hole test pad 150b.
  • the coaxial large hole test pad is electrically connected to the connection through hole 12 in a one-to-one correspondence.
  • the coaxial small The hole and the coaxial large hole M0 are not in contact yet, and any coaxial large hole test pad and the coaxial small hole test pad 16 do not form a path, and are open circuit connections.
  • the third coaxial small hole m3 has a deviation relative to the coaxial large hole M0 in the offset direction in which the axis center of the coaxial metallized via hole points to the eighth sector ring H.
  • the third coaxial small hole m3 and the coaxial large hole M0 The eighth sector ring H is in contact, and the connection through hole 12 passing through the eighth sector connection pad 110h is electrically connected to the corresponding eighth coaxial large hole test pad 150h, thereby making the eighth coaxial large hole test pad 150h electrically connected.
  • the pad 150h and the coaxial hole test pad 16 form a path and are connected in a short circuit. In the above example, it can be determined that the direction of the eighth coaxial large hole test pad 150h relative to the coaxial small hole is the offset direction of the coaxial small hole.
  • each group of coaxial metallized vias there are coaxial small hole opening conductive layers and coaxial large hole opening conductive layers located on the same side of the printed circuit board, and coaxial small hole opening conductive layers
  • the number of spacer layers between the conductive layer and the outer layer is smaller than the number of spacer layers between the conductive layer and the outer layer.
  • the number of spacing layers between the coaxial small hole conductive layer Ls-q and the outer layer is smaller than the spacing between the coaxial large hole conductive layer Ls-q and the outer layer.
  • the number of layers makes the coaxial small hole conductive layer Ls-q closer to the outer layer than the coaxial large hole conductive layer Ls, which can realize the connection between the bottom pad 14 of the blind hole 13 and the coaxial small hole.
  • the conductive layer Ls-q is located on the same layer, covers the opening of the coaxial small hole, and is equal to the inner diameter of the coaxial large hole M0, the connecting through hole 12 and the connecting blind hole 13 are insulated.
  • the alignment of the coaxial metallized vias can be determined by detecting the continuity of the coaxial large hole test pad 15 and the coaxial small hole test pad 16, without the need to detect the inner layer of coaxial metal through a slicing process.
  • the alignment of the vias enables non-destructive testing, simplifies the testing process, and thus saves testing costs.
  • An embodiment of the present application also provides a method for manufacturing a printed circuit board.
  • the preparation method includes:
  • the coaxial large hole is a metallized via hole
  • the conductive layer of the coaxial large hole includes a coaxial large hole layer
  • the coaxial large hole layer includes Two coaxial large hole conductive layers and a coaxial large hole inner conductive layer;
  • the structure after lamination forms at least one coaxial hole, wherein the coaxial hole is a metalized via, the conductive layer of the coaxial hole includes a coaxial hole layer, and the coaxial hole layer includes a coaxial hole.
  • S140 also includes forming a coaxial large hole conductive structure and a coaxial small hole conductive structure, the coaxial large hole conductive structure is connected to the coaxial large hole orifice conductive layer, and the coaxial small hole conductive structure is conductive to the coaxial small hole orifice.
  • Layer connection, the conduction status of the coaxial large hole conductive structure and the coaxial small hole conductive structure is related to the alignment of the coaxial metallized vias, where the alignment of the coaxial metallized vias includes the coaxial small holes amount of deviation and/or direction of offset.
  • the coaxial large hole conductive structure serves as the first electrical signal extraction structure of the coaxial large hole; the coaxial small hole conductive structure serves as the second electrical signal extraction structure of the coaxial small hole.
  • FIG. 9 is a flow chart of a method for manufacturing a printed circuit board according to an embodiment of the present application.
  • the preparation method of the printed circuit board includes:
  • the conductive layer of the coaxial large hole includes a coaxial large hole layer
  • the coaxial large hole layer includes There are two coaxial large hole conductive layers and a coaxial large hole inner conductive layer.
  • three coaxial large holes M0 are formed on the inner layer of the printed circuit board.
  • the coaxial large holes M0 are metallized vias.
  • the conductive layer of the coaxial large holes M0 includes a coaxial large hole layer.
  • the axial macropore layer includes two coaxial macropore conductive layers Ls and a coaxial macropore inner conductive layer L01.
  • a coaxial large hole connection pad 11 is formed, in which the coaxial large hole connection pad 11 and the coaxial large hole conductive layer Ls are located on the same layer, located outside the coaxial large hole M0 and with the coaxial large hole M0.
  • the large hole opening conductive layer Ls is connected.
  • the coaxial large hole connection pad 11 serves as the electrical signal extraction structure of the coaxial large hole M0.
  • the coaxial large hole M0 is plugged with insulating material.
  • An insulating material such as a resin material, is disposed between the large coaxial hole M0 and the small coaxial hole.
  • the side of the coaxial large hole orifice conductive layer Ls away from the printed circuit board is laminated to the coaxial small hole orifice conductive layer Ls-q, so that the coaxial large hole orifice conductive layer Ls and The coaxial orifice conductive layer Ls-q is located in different layers.
  • the value of q includes integers greater than or equal to 1.
  • each group of coaxial metallized vias of S140 the side of the coaxial large hole conductive layer facing away from the printed circuit board is laminated to reach the coaxial small hole conductive layer, including:
  • At least one layer is laminated on the side of the coaxial large hole orifice conductive layer Ls facing away from the printed circuit board to reach the coaxial small hole orifice conductive layer Ls-q.
  • the number of spacing layers between the conductive layer Ls-q and the outer layer of the coaxial small hole is smaller than that of the coaxial large hole.
  • the number of spacing layers between the conductive layer Ls and the outer layer makes the coaxial small hole orifice conductive layer Ls-q closer to the outer layer than the coaxial large hole orifice conductive layer Ls, allowing bottom welding of the hole connected to the blind hole 13
  • the pad 14 is located on the same layer as the conductive layer Ls-q of the coaxial small hole.
  • the orthographic projection of the hole bottom pad 14 connected to the blind hole 13 on the printed circuit board at least covers the inner ring area of the conductive layer L01 in the coaxial large hole.
  • the conductivity of the coaxial large hole test pad and the coaxial small hole test pad can be detected to determine the coaxial metallized via hole.
  • Alignment There is no need to use the slicing process to detect the alignment of the coaxial metal vias in the inner layer, which enables non-destructive testing, simplifies the testing process, and thus saves testing costs.
  • the structure after lamination forms at least one coaxial small hole, where the coaxial small hole is a metallized via hole, where the coaxial small hole is a metallized via hole, and the conductive layer of the coaxial small hole includes a coaxial
  • the small hole layer and the coaxial small hole layer include the coaxial small hole opening conductive layer and the coaxial small hole inner conductive layer; in a set of coaxial metallized vias, there are two coaxial large holes corresponding to the coaxial large holes.
  • the coaxial hole layer located on the same layer of the printed circuit board is located in a different layer.
  • the coaxial small hole is a metallized via hole
  • the coaxial large hole M0 is arranged around the coaxial small hole.
  • the inner layer of the printed circuit board includes three sets of coaxial metallized vias.
  • a coaxial large hole M0 and a coaxial small hole constitute a set of coaxial metallized via holes.
  • the coaxial small hole includes a first coaxial small hole m1, a second coaxial small hole m2 and a third coaxial small hole m3. .
  • the bottom pad 14 connected to the blind hole is located on the same layer as the conductive layer Ls-q of the coaxial small hole opening.
  • the orthographic projection of the bottom pad 14 connected to the blind hole 13 on the printed circuit board covers at least the same layer.
  • the inner ring area of the conductive layer L01 in the large hole of the shaft is in the orthographic projection of the printed circuit board and is insulated from the connecting through hole 12 .
  • the hole bottom pad 14 connected to the blind hole serves as an electrical signal extraction structure for the first coaxial hole m1, the second coaxial hole m2, and the third coaxial hole m3.
  • connection through hole 12 and a connection blind hole 13 are formed in the printed circuit, wherein the connection through hole 12 covers the coaxial large hole connection pad 11 in the front projection of the printed circuit board. At least part of the projection, the hole bottom pad 14 connecting the blind hole 13 is insulated from the connecting through hole 12, so that the connecting through hole 12 can pass through The coaxial large hole connection pad 11 is electrically connected to the coaxial large hole M0.
  • a coaxial small hole test pad 16 and a coaxial large hole test pad 15 are formed on the outer layer of the printed circuit board.
  • the coaxial large hole connecting pad 11 and the coaxial large hole orifice conductive layer Ls are located on the same layer and are connected to the coaxial large hole orifice conductive layer Ls.
  • the through hole 12 covers the coaxial axis in the orthographic projection of the printed circuit board.
  • the large hole connection pad 11 is in the orthographic projection part of the printed circuit board.
  • the coaxial large hole test pad 15 covers the opening of the connection through hole 12.
  • the coaxial large hole connection pad 11 and the connection through hole 12 serve as coaxial
  • the first electrical signal extraction structure of the large hole M0 can form a path through the coaxial large hole M0 and the coaxial large hole test pad 15 .
  • the bottom pad 14 connected to the blind hole 13 is located on the same layer as the coaxial small hole opening conductive layer Ls-q.
  • the bottom pad 14 connected to the blind hole 13 covers the coaxial large hole in the orthographic projection of the printed circuit board.
  • the area within the ring of the inner conductive layer L01 is in the orthographic projection of the printed circuit board and is insulated from the connecting through hole 12.
  • the coaxial small hole test pad 16 covers the opening of the blind hole 13, and the bottom of the hole connecting the blind hole 13 is soldered
  • the disk 14 and the connecting blind hole 13 serve as the second electrical signal extraction structure of the coaxial hole, and the coaxial hole and the coaxial hole test pad 16 can form a path.
  • the coaxial large hole connection pad 11 is located outside the coaxial large hole M0, and the connection through hole 12 covers at least the front projection of the coaxial large hole connection pad 15 on the printed circuit board. part, and the connection through hole 12 and the connection blind hole 13 are insulated.
  • the coaxial large hole test pad 15 and the coaxial small hole test pad 16 are connected, the coaxial small hole must be in contact with the coaxial large hole M0, which will cause the coaxial large hole test pad 15 and the coaxial small hole test pad 16 to be connected.
  • the coaxial eyelet test pad 16 forms a via, forming a short circuit connection.
  • the coaxial large hole connecting pad and the connecting through hole are used as the first electrical signal extraction structure of the coaxial large hole, and the coaxial large hole and the coaxial large hole test pad can be formed into a path; connection The bottom pad of the blind hole and the connecting blind hole serve as the second electrical signal extraction structure of the coaxial hole, and the coaxial hole and the coaxial hole test pad can form a path.
  • the coaxial large hole connecting pad is located outside the coaxial large hole, and the orthographic projection of the connecting through hole on the printed circuit board covers at least part of the orthographic projection of the coaxial large hole connecting pad on the printed circuit board, and the connecting through hole Insulation is provided between the hole and the connecting blind hole.
  • the printed circuit board provided in this embodiment determines the deviation amount and/or offset direction of the coaxial small hole by detecting the continuity of the coaxial large hole test pad and the coaxial small hole test pad without passing the test pad.
  • the slicing process detects the alignment of the coaxial metal vias in the inner layer, achieving non-destructive testing, simplifying the testing process, and thus saving testing costs.
  • Figure 16 is a flow chart of another method for manufacturing a printed circuit board according to an embodiment of the present application. The difference between Figure 16 and Figure 9 is that S150 in Figure 9 is further limited. Specifically, referring to Figure 16, the preparation method of the printed circuit board includes the following steps:
  • Drill n coaxial holes with different diameters in the laminated structure.
  • the apertures of the n coaxial small holes include: the first aperture, the second aperture...the nth aperture, and the value of n includes an integer greater than or equal to 1; the apertures of the n coaxial small holes and the coaxial large holes
  • the differences include: the first aperture difference, the second aperture difference...the nth aperture difference, where the first aperture difference>the second aperture difference>...>nth aperture difference; the i-th group of coaxial metallized vias
  • the aperture of the coaxial small hole is the i-th aperture, and the aperture difference between the coaxial small hole of the i-th aperture and the coaxial large hole is the i-th aperture difference.
  • the value of i includes an integer greater than or equal to 1 and less than or equal to n. .
  • the aperture of the first coaxial small hole m1 is the first aperture d1
  • the aperture of the second coaxial small hole m2 is the second aperture d2
  • the aperture diameter of the third coaxial small hole m3 is the third aperture d3.
  • the difference between the aperture diameter of the first coaxial small hole m1 and the coaxial large hole M0 is the first aperture difference ⁇ d1
  • the difference between the aperture diameter of the second coaxial small hole m2 and the coaxial large hole M0 is the second aperture difference ⁇ d2
  • the difference between the aperture diameter of the third coaxial small hole m3 and the aperture diameter of the coaxial large hole M0 is the third aperture difference ⁇ d3.
  • the hole test pad 15 and the coaxial small hole test pad 16 do not form a path and are disconnected.
  • the third coaxial small hole m3 has a deviation in a certain offset direction relative to the coaxial large hole M0.
  • the third coaxial small hole m3 is in contact with the coaxial large hole M0, and the coaxial large hole test pad 15 is in contact with the coaxial small hole M0.
  • Hole test pad 16 forms a via, which is Short circuit connection.
  • the aperture of the fourth coaxial small hole m4 is the fourth aperture d4, and the fourth coaxial small hole m4 and The aperture difference of the coaxial large hole M0 is the fourth aperture difference ⁇ d4.
  • the aperture difference of the fourth coaxial small hole m4 and the coaxial large hole M0 is greater than the aperture difference of the third coaxial small hole m3 relative to the coaxial large hole M0.
  • the offset of the fourth coaxial small hole m4 and the coaxial large hole M0 makes the two in contact, the coaxial small hole test pad 16 of the fourth coaxial small hole m4 and the coaxial large hole of the coaxial large hole M0
  • the test pad 15 forms a via and is a short-circuit connection.
  • the hole diameter difference between the third coaxial small hole m3 and the coaxial large hole M0 is the deviation of the coaxial small hole.
  • coaxial small holes with different apertures are set, and the coaxial small hole test pad and the coaxial large hole test pad are connected.
  • the difference in diameter between the coaxial small hole with the smallest diameter and the coaxial large hole is the deviation of the coaxial small hole.
  • the above-mentioned printed circuit board can quickly and accurately obtain the deviation of the coaxial holes in the coaxial metallized via holes.
  • FIG 17 is a flow chart of yet another printed circuit board manufacturing method provided according to an embodiment of the present application.
  • S110 and S120 and S210 and S220 are further limited.
  • the preparation method of the printed circuit board includes the following steps:
  • At least one coaxial large hole M0 is drilled in the conductive layer Ls of the coaxial large hole opening of the printed circuit board.
  • the coaxial large holes are formed into metallized vias through copper plating and electroplating processes.
  • the conductive layer of the coaxial large holes includes a coaxial large hole layer, and the coaxial large hole layer includes two coaxial large hole orifice conductive layers. and the conductive layer inside the coaxial large hole.
  • the coaxial large holes are formed into metallized vias through copper plating and electroplating processes.
  • the conductive layer of the coaxial large hole M0 includes a coaxial large hole layer, and the coaxial large hole layer includes two coaxial large hole holes.
  • the plug-hole device includes an inner hard bracket and a flexible outer layer.
  • the cross-section of the inner hard bracket includes a solid part and at least two holes distributed on the edge of the solid part.
  • the plug hole device 200 is inserted into the coaxial large hole M0.
  • the plug hole device 200 includes an inner hard bracket 201 and a flexible outer layer 202.
  • the cross section of the inner hard bracket 201 includes a solid portion 201a and at least two fan-shaped connections distributed on the edge of the solid portion 201a. portions 201b, and hollow areas 203 are provided between the sector-shaped connecting portions 201b.
  • the plugging device 200 is a cylinder, the length of which is equal to the depth of the coaxial large hole M0, and the diameter of the plugging device 200 is the same as the inner diameter of the coaxial large hole M0.
  • the plug hole device 200 is a M-shaped cylindrical plug hole device.
  • the inner hard bracket 201 needs to have a relatively hard texture to provide support, facilitate insertion into the hole, and be able to freely control the insertion depth. Its material needs to be acid and alkali resistant, non-conductive, non-absorbent, and non-compatible with electroplating solutions. For reaction, hard materials such as polytetrafluoroethylene can be used.
  • the material of the flexible outer layer 202 needs to be soft, deformable, resistant to acid and alkali corrosion, and not react with the potion. It is used to completely fill the gap between the plugging device and the hole wall to prevent the potion from entering the material.
  • the flexible outer layer 202 may be made of soft material such as PVC.
  • wet etching is performed on the conductive layer L01 in the coaxial large hole to form at least two coaxial large holes M0 with insulated sector-shaped rings.
  • the copper in the area of the hole wall of the coaxial large hole M0 that is not blocked by the plug hole device 200 (the hollow area 203) is etched away, and the copper in the blocked area is retained.
  • the hole wall is divided vertically into 8 partially metallized areas. The 8 areas can distinguish up, down, left, right, and 8 directions along a 45° angle.
  • the coaxial large hole M0 includes eight insulated sector rings, namely the first sector ring A, the second sector ring B, the third sector ring C, the fourth sector ring D, and the fifth sector ring. Ring E, sixth sector ring F, seventh sector ring G and eighth sector ring H.
  • the connecting through holes include at least two, and the connecting through holes are printed on
  • the front projection of the printed circuit board covers at least part of the front projection of the sector-shaped connection pads on the printed circuit board.
  • the first area surface copper 301 of the layer where the coaxial large hole conductive layer Ls is located is etched.
  • the second area surface copper 300 is not etched.
  • the dotted line area is covered by the dry film, so the dotted line area
  • at least two insulating sector-shaped connection pads can be formed on the surface copper, wherein the sector-shaped connection pads are arranged around the sector-shaped ring, and the sector-shaped connection pads are connected to the sector-shaped ring in a one-to-one correspondence.
  • the coaxial large hole connection pad 11 includes eight insulated fan-shaped connection pads, which are the first fan-shaped connection pad 110a, the second fan-shaped connection pad 110b, the third fan-shaped connection pad 110c, and the third fan-shaped connection pad 110c.
  • the third coaxial small hole m3 has a deviation relative to the coaxial large hole M0 in the offset direction in which the axis center of the coaxial metallized via hole points to the eighth sector ring H.
  • the third coaxial small hole m3 and the coaxial large hole M0 The eighth sector ring H is in contact, and the connection through hole 12 passing through the eighth sector connection pad 110h is electrically connected to the corresponding eighth coaxial large hole test pad 150h, thereby making the eighth coaxial large hole test pad 150h electrically connected.
  • the pad 150h and the coaxial hole test pad 16 form a path and are connected in a short circuit. In the above example, it can be determined that the direction of the eighth coaxial large hole test pad 150h relative to the coaxial small hole is the offset direction of the coaxial small hole.
  • the structure after lamination forms at least one coaxial small hole, where the coaxial small hole is a metallized via hole, where the coaxial small hole is a metallized via hole, and the conductive layer of the coaxial small hole includes a coaxial
  • the small hole layer and the coaxial small hole layer include the coaxial small hole opening conductive layer and the coaxial small hole inner conductive layer; in a set of coaxial metallized vias, there are two coaxial large holes corresponding to the coaxial large holes.
  • the coaxial hole layer located on the same layer of the printed circuit board is located in a different layer.
  • implementation steps and beneficial effects of S380 can refer to the implementation steps of S150. and beneficial effects execution.
  • a first coaxial small hole m1 is formed in the coaxial small hole layer Ls-q.
  • the first coaxial small hole m1 is a metallized via hole, and the coaxial large hole M0 is arranged around the first coaxial small hole m1.
  • a hole bottom pad 14 connecting the blind hole is formed on the coaxial small hole opening layer Ls-q.
  • the hole bottom pad 14 connecting the blind hole and the coaxial small hole opening conductive layer Ls-q are located at On the same layer, the orthographic projection of the hole bottom pad 14 connecting the blind hole 13 on the printed circuit board at least covers the orthographic projection of the area inside the conductive layer L01 ring in the coaxial large hole on the printed circuit board, and is connected with the connecting through hole 12
  • the hole bottom pad 14 is insulated and connected to the blind hole as the electrical signal extraction structure of the first coaxial small hole m1.
  • connection through holes cover the coaxial large hole connection solder in the orthographic projection of the printed circuit board.
  • the pad is at least part of the front projection of the printed circuit board, and the hole bottom pad of the connecting blind hole is insulated from the connecting through hole.
  • connection through holes 12 and connection blind holes 13 are formed in the printed circuit.
  • 8 connection through holes 12 are located in a one-to-one correspondence within the orthographic projection of the sector-shaped connection pads on the printed circuit board, so that the connection through holes 12 connect to the pads 11 through the coaxial large holes.
  • coaxial small hole test pad Form a coaxial small hole test pad and at least two coaxial large hole test pads on the outer layer of the printed circuit board.
  • the coaxial large hole test pads cover the openings of the connecting through holes one by one.
  • the coaxial small hole test pad covers at least part of the orifice connecting the blind via, the continuity of the coaxial large hole test pad and the coaxial small hole test pad and the alignment of the coaxial metallized via Degree-related, wherein the alignment of the coaxial metallized vias includes the deviation amount and/or offset direction of the coaxial holes.
  • a coaxial small hole test pad 16 and a coaxial large hole test pad 15 are formed on the outer layer of the printed circuit board.
  • the number of coaxial large hole test pads 15 is eight, and the coaxial large hole test pads 15 are electrically connected to the connection through holes 12 in one-to-one correspondence.
  • the coaxial large hole M0 includes 8 insulated sector rings, namely the first sector ring A, the second sector ring B, the third sector ring C, the fourth sector ring D, the fifth sector ring E, sixth Sector ring F, seventh sector ring G and eighth sector ring H;
  • the coaxial large hole connection pad 11 includes 8 insulated sector connection pads, which are the first sector connection pad 110a, the second sector connection pad 110a and the second sector connection pad 110a.
  • connection through-holes 12 include 8, and the connection through-holes 12 are located in the sector-shaped connection pads in a one-to-one correspondence on the orthographic projection of the printed circuit board.
  • the disk is within the orthographic projection of the printed circuit board.
  • the coaxial large hole test pads in Figure 8 include 8 coaxial large hole test pads, which are the first coaxial large hole test pad 150a, the second coaxial large hole test pad 150b, and the first coaxial large hole test pad 150b.
  • the coaxial large hole test pad is electrically connected to the connection through hole 12 in a one-to-one correspondence.
  • the conduction status of the coaxial small hole test pad and each coaxial large hole test pad in each group of coaxial metallized via holes is obtained; the coaxial small hole test pad is In each set of coaxial metallized vias in which the hole test pad and the coaxial large hole test pad are connected, the orientation of the coaxial large hole test pad relative to the coaxial small hole pad is the offset of the coaxial small hole. Shift position.
  • the embodiment of the present application also provides a schematic flow chart of a method for testing the coaxial hole alignment of a printed circuit board.
  • S410 Determine the alignment of the coaxial metallized vias based on the conduction conditions of the coaxial large hole conductive structure and the coaxial small hole conductive structure, where the alignment of the coaxial metallized vias includes the alignment of the coaxial small holes. Amount and/or direction of offset.
  • the coaxial large hole conductive structure serves as the first electrical signal extraction structure of the coaxial large hole; the coaxial small hole conductive structure serves as the second electrical signal extraction structure of the coaxial small hole.
  • FIG. 26 is a schematic flowchart of a method for testing the coaxial hole alignment of a printed circuit board according to an embodiment of the present application.
  • the test method for the coaxial hole alignment of this printed circuit board includes the following steps:
  • S420 Determine the alignment of the coaxial metallized vias based on the conduction conditions of the coaxial large hole test pads and the coaxial small hole test pads in each group of coaxial metallized vias, where the coaxial metallized vias
  • the alignment of the vias includes the deviation amount and/or offset direction of the coaxial holes.
  • the coaxial large hole connection pad 11 and the coaxial large hole conductive layer Ls are located on the same layer, and are connected to the coaxial large hole conductive layer Ls, connecting the through holes 12
  • the coaxial large hole connection pad 11 is covered in the orthographic projection of the printed circuit board, and the coaxial large hole test pad 15 covers the orifice of the connection through hole 12, the coaxial large hole
  • the connection pad 11 and the connection through hole 12 serve as the first electrical signal extraction structure of the coaxial large hole layer of the coaxial large hole M0, and the coaxial large hole layer of the coaxial large hole M0 and the coaxial large hole test pad can be 15 constitute the passage.
  • the hole bottom pad 14 connected to the blind hole 13 is located on the same layer as the coaxial small hole opening conductive layer Ls-q.
  • the orthographic projection of the hole bottom pad 14 connected to the blind hole 13 on the printed circuit board at least covers the coaxial large hole.
  • the area within the ring of the conductive layer L01 in the hole is the orthographic projection of the printed circuit board and is insulated from the connecting through hole 12.
  • the coaxial small hole test pad 16 covers the opening of the blind hole 13 and is connected to the bottom of the blind hole 13.
  • the bonding pad 14 and the connecting blind hole 13 serve as the second electrical signal extraction structure of the coaxial hole layer, and the coaxial hole and the coaxial hole test pad 16 can form a path.
  • the coaxial large hole connection pad 11 is located outside the coaxial large hole M0, and the connection through hole 12 covers at least the front projection of the coaxial large hole connection pad 11 on the printed circuit board. part, the connection through hole 12 and the connection blind hole 13 are insulated. Therefore, if the coaxial large hole test pad 15 and the coaxial small hole test pad 16 are connected, there must be a connection between the coaxial small hole and the coaxial large hole. Only when the hole M0 comes into contact will the coaxial large hole test pad 15 and the coaxial small hole test pad 16 form a path and form a short circuit connection.
  • the coaxial large hole connecting pad and the connecting through hole are used as the first electrical signal extraction structure of the coaxial large hole, and the coaxial large hole and the coaxial large hole test pad can be formed into a path; connection The bottom pad of the blind hole and the connecting blind hole serve as the second electrical signal extraction structure of the coaxial hole, and the coaxial hole and the coaxial hole test pad can form a path.
  • the coaxial large hole connecting pad is located outside the coaxial large hole, and the orthographic projection of the connecting through hole on the printed circuit board covers at least part of the orthographic projection of the coaxial large hole connecting pad on the printed circuit board, and the connecting through hole
  • the hole and the connecting blind hole are insulated, so that the connecting through hole and the connecting blind hole are insulated. Only when the coaxial small hole and the coaxial large hole are in contact will the coaxial large hole test pad and the coaxial small hole test pad form a path and form a short circuit connection. Therefore, the printed circuit board provided in this embodiment determines the deviation amount and/or offset direction of the coaxial small hole by detecting the continuity of the coaxial large hole test pad and the coaxial small hole test pad without passing the test pad. The slicing process detects the alignment of the coaxial metal vias in the inner layer, achieving non-destructive testing, simplifying the testing process, and thus saving testing costs.
  • Figure 27 is the coaxial hole alignment of another printed circuit board provided according to an embodiment of the present application. Flow chart of the test method. Figure 27 further defines S420 in Figure 26. Referring to Figure 27, the test method for the coaxial hole alignment of the printed circuit board includes the following steps:
  • coaxial small hole test pad and coaxial large hole test pad are connected to each set of coaxial metallized via holes.
  • the difference in aperture between the coaxial small hole with the smallest aperture and the coaxial large hole is the coaxial small hole. amount of deviation.
  • the aperture of the first coaxial small hole m1 is the first aperture d1
  • the aperture of the second coaxial small hole m2 is the second aperture d2.
  • the aperture diameter of the third coaxial small hole m3 is the third aperture d3.
  • the difference between the aperture diameter of the first coaxial small hole m1 and the coaxial large hole M0 is the first aperture difference ⁇ d1
  • the difference between the aperture diameter of the second coaxial small hole m2 and the coaxial large hole M0 is the second aperture difference ⁇ d2
  • the difference between the aperture diameter of the third coaxial small hole m3 and the aperture diameter of the coaxial large hole M0 is the third aperture difference ⁇ d3.
  • the hole test pad 15 and the coaxial small hole test pad 16 do not form a path and are disconnected.
  • the third coaxial small hole m3 has a deviation in a certain offset direction relative to the coaxial large hole M0.
  • the third coaxial small hole m3 is in contact with the coaxial large hole M0, and the coaxial large hole test pad 15 is in contact with the coaxial small hole M0.
  • Hole test pad 16 forms a via and is a short circuit connection.
  • the aperture of the fourth coaxial small hole m4 is the fourth aperture d4, and the fourth coaxial small hole m4 and The aperture difference of the coaxial large hole M0 is the fourth aperture difference ⁇ d4.
  • the aperture difference of the fourth coaxial small hole m4 and the coaxial large hole M0 is greater than the aperture difference of the third coaxial small hole m3 relative to the coaxial large hole M0.
  • the offset of the fourth coaxial small hole m4 and the coaxial large hole M0 makes the two in contact, the coaxial small hole test pad 16 of the fourth coaxial small hole m4 and the coaxial large hole of the coaxial large hole M0
  • the test pad 15 forms a via and is a short-circuit connection.
  • the hole diameter difference between the third coaxial small hole m3 and the coaxial large hole M0 is the deviation of the coaxial small hole.
  • the above-mentioned printed circuit board can quickly and accurately obtain the deviation of the coaxial holes in the coaxial metallized via holes.
  • FIG. 28 is a schematic flow chart of yet another method for testing the coaxial hole alignment of a printed circuit board according to an embodiment of the present application.
  • Figure 28 further performs S410 and S420 in Figure 26 limited.
  • the test method for the coaxial hole alignment of the printed circuit board includes the following steps:
  • the coaxial large hole test pad where the coaxial small hole test pad is connected is relatively the same.
  • the position of the axis hole pad is the offset position of the coaxial hole.
  • the coaxial large hole M0 includes eight insulated sector rings, namely the first sector ring A, the second sector ring B, the third sector ring C, and the fourth sector ring D. , the fifth sector ring E, the sixth sector ring F, the seventh sector ring G and the eighth sector ring H;
  • the coaxial large hole connection pad 11 includes 8 insulated sector connection pads, respectively the first sector connection Bonding pad 110a, second sector connection pad 110b, third sector connection pad 110c, fourth sector connection pad 110d, fifth sector connection pad 110e, sixth sector connection pad 110f, seventh sector connection pad 110g and the eighth sector connection pad 110h, the sector connection pads are arranged around the sector ring, and the sector connection pads are connected to the sector ring in one-to-one correspondence;
  • the connection through holes 12 include 8, and the connection through holes 12 are on the printed circuit board.
  • the coaxial large hole test pads in Figure 8 include 8 coaxial large hole test pads, which are the first coaxial large hole test pad 150a, the second coaxial large hole test pad 150b, and the first coaxial large hole test pad 150b.
  • the coaxial large hole test pad is electrically connected to the connection through hole 12 in a one-to-one correspondence.
  • the coaxial small The hole and the coaxial large hole M0 are not in contact yet, and any coaxial large hole test pad and the coaxial small hole test pad 16 do not form a path, and are open circuit connections.
  • the third coaxial small hole m3 has a deviation relative to the coaxial large hole M0 in the offset direction in which the axis center of the coaxial metallized via hole points to the eighth sector ring H.
  • the third coaxial small hole m3 and the coaxial large hole M0 The eighth sector ring H is in contact, and the connection through hole 12 passing through the eighth sector connection pad 110h is electrically connected to the corresponding eighth coaxial large hole test pad 150h, thereby making the eighth coaxial large hole test pad 150h electrically connected.
  • the pad 150h and the coaxial hole test pad 16 form a path and are connected in a short circuit. In the above example, it can be determined that the direction of the eighth coaxial large hole test pad 150h relative to the coaxial small hole is the offset direction of the coaxial small hole.
  • the conduction status of the coaxial small hole test pad and each coaxial large hole test pad in each group of coaxial metallized via holes is obtained; the coaxial small hole test pad is In each set of coaxial metallized vias where the hole test pad and the coaxial large hole test pad are connected, the coaxial large hole test pad that is connected to the coaxial small hole pad is relative to the coaxial small hole pad.
  • the orientation is the offset orientation of the coaxial hole. above The printed circuit board can quickly and accurately obtain the offset position of the coaxial hole in the coaxial metallized via hole.

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Abstract

一种印制电路板以及制备方法。印制电路板的内层包括至少一组同轴金属化过孔，其中，每组同轴金属化过孔包括同轴大孔（M0）和同轴小孔（m1, m2, m3），同轴大孔（M0）和同轴小孔（m1, m2, m3）之间设置有绝缘材料；一组同轴金属化过孔中，同轴大孔（M0）孔口导电层中与其位于印制电路板同层的同轴小孔（m1, m2, m3）孔口导电层位于不同层；印制电路板还包括同轴大孔导电结构和同轴小孔导电结构同轴大孔导电结构与同轴小孔导电结构的导通情况和同轴金属化过孔的对准度相关，其中，同轴金属化过孔的对准度包括同轴小孔（m1, m2, m3）的偏差量和/或偏移方向，实现了无损检测，简化了印制电路板同轴孔对准度的检测流程，降低了检测成本。

Description

印制电路板以及制备方法
本申请要求在2022年08月09日提交中国专利局、申请号为202210949032.0的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及印制电路板技术领域，尤其涉及一种印制电路板以及制备方法。
背景技术
同轴通孔技术可以实现真正的信号阻抗连续性，提供优异的地线(GND)回路，并且有效地降低通孔之间的串扰以及通孔与迹线之间的串扰。同轴孔工艺是对于5G高频段解决方案的预研，目的是仿照同轴线设计得到更好的波导特性，线路板同轴孔运用在射频同轴电缆中，传输回路由内导体、绝缘介质和外导体三部分组成。这三部分是同心的、即有共同的中心轴，所以同轴孔孔位精度要求较高。
同轴孔设计方式为，在子板钻出同轴大孔，同轴大孔通过树脂塞孔后，在经过树脂塞孔的同轴大孔中间钻出同轴小孔，通常同轴大孔与同轴小孔不在同一层，且孔径大小差异大，间隔层数为N(N≥1)。
针对同轴孔的一些电性能及性能指标的要求并不明确，仅可确定的指标为同轴孔对准度，要求为±2mil。针对同轴孔对准度的测量，主要方法是切片确认的方法，这种方法虽然可以量化对准度数据，但是取样测量会造成基板报废，因此考虑采用一种不用切片确认，直接通过工具测量的方法进行确认同轴孔的对准度。
发明内容
本申请实施例提供了一种印制电路板以及制备方法，以简化印制电路板同轴孔对准度的检测流程，降低检测成本。
根据本申请的一方面，提供了一种印制电路板，所述印制电路板包括内层和外层，还包括：
所述印制电路板的内层包括至少一组同轴金属化过孔，其中，每组同轴金属化过孔包括同轴大孔和同轴小孔，所述同轴大孔和所述同轴小孔之间设置有绝缘材料，所述同轴大孔的导电层包括同轴大孔层，所述同轴小孔的导电层包 括同轴小孔层，所述同轴大孔层包括同轴大孔孔口导电层和同轴大孔孔内导电层，所述同轴小孔层包括同轴小孔孔口导电层和同轴小孔孔内导电层；一组同轴金属化过孔中，同轴大孔孔口导电层中与其位于所述印制电路板同层的同轴小孔孔口导电层位于不同层；
所述印制电路板还包括同轴大孔导电结构和同轴小孔导电结构，所述同轴大孔导电结构与所述同轴大孔孔口导电层连接，所述同轴小孔导电结构与所述同轴小孔孔口导电层连接，所述同轴大孔导电结构与所述同轴小孔导电结构的导通情况和所述同轴金属化过孔的对准度相关，其中，所述同轴金属化过孔的对准度包括所述同轴小孔的偏差量和/或偏移方向。
可选地，所述印制电路板还包括同轴大孔连接焊盘、连接通孔和连接盲孔；所述同轴大孔连接焊盘和所述同轴大孔孔口导电层位于同层，位于所述同轴大孔的外侧且与所述同轴大孔孔口导电层连接；所述连接通孔在所述印制电路板的正投影覆盖所述同轴大孔连接焊盘在所述印制电路板的正投影的至少部分；所述连接盲孔的孔底焊盘与所述同轴小孔孔口导电层位于同层，所述连接盲孔的孔底焊盘在所述印制电路板的正投影至少覆盖所述同轴大孔孔内导电层环内区域在所述印制电路板的正投影，且与所述连接通孔绝缘设置；
所述印制电路板的外层包括同轴小孔测试焊盘和同轴大孔测试焊盘，所述同轴大孔测试焊盘覆盖所述连接通孔的孔口的至少部分，所述同轴小孔测试焊盘覆盖所述连接盲孔的孔口的至少部分；
所述同轴大孔连接焊盘、所述连接通孔和所述同轴大孔测试焊盘构成所述同轴大孔导电结构；所述连接盲孔和同轴小孔测试焊盘构成所述同轴小孔导电结构；
所述同轴大孔测试焊盘和所述同轴小孔测试焊盘的导通情况和所述同轴金属化过孔的对准度相关，其中，所述同轴金属化过孔的对准度包括所述同轴小孔的偏差量和/或偏移方向。
可选地，包括n组同轴金属化过孔，其中，所述n的取值包括大于或等于1的整数；
n个所述同轴小孔的孔径包括：第一孔径、第二孔径……第n孔径；
n个所述同轴小孔与所述同轴大孔的孔径差异包括：第一孔径差异、第二孔径差异……第n孔径差异，其中，第一孔径差异＞第二孔径差异＞……＞第n孔径差异；
第i组同轴金属化过孔中的同轴小孔的孔径为第i孔径，第i孔径的同轴小孔与所述同轴大孔的孔径差异为第i孔径差异，所述i的取值包括大于或等于1， 且小于或等于n的整数。
可选地，所述同轴大孔孔内导电层包括至少两个绝缘设置的扇形环；
所述同轴大孔连接焊盘包括至少两个绝缘设置的扇形连接焊盘，所述扇形连接焊盘环绕所述扇形环设置，且所述扇形连接焊盘与所述扇形环一一对应连接；
所述连接通孔包括至少两个，所述连接通孔在所述印制电路板的正投影一一覆盖位于所述扇形连接焊盘在所述印制电路板的正投影的至少部分；
所述同轴大孔测试焊盘包括至少两个，所述同轴大孔测试焊盘一一对应覆盖所述连接通孔的孔口的至少部分。
可选地，每组同轴金属化过孔中，位于所述印制电路板同侧的同轴小孔孔口导电层和同轴大孔孔口导电层中，所述同轴小孔孔口导电层和所述外层的间隔层数小于所述同轴大孔孔口导电层和所述外层的间隔层数。
根据本申请的另一方面，提供了一种印制电路板的制备方法，包括：
在印制电路板的内层形成至少一个同轴大孔，其中，所述同轴大孔为金属化过孔，所述同轴大孔的导电层包括同轴大孔层，所述同轴大孔层包括两同轴大孔孔口导电层和同轴大孔孔内导电层；
对同轴大孔孔口导电层背离印制电路板的一侧进行层压后到达同轴小孔孔口导电层；
在层压之后的结构形成至少一个同轴小孔，其中，所述同轴小孔为金属化过孔，所述同轴小孔的导电层包括同轴小孔层，所述同轴小孔层包括同轴小孔孔口导电层和同轴小孔孔内导电层；一组同轴金属化过孔中，同轴大孔孔口导电层中与其位于所述印制电路板同层的同轴小孔层位于不同层；
还包括形成同轴大孔导电结构和同轴小孔导电结构，所述同轴大孔导电结构与所述同轴大孔孔口导电层连接，所述同轴小孔导电结构与所述同轴小孔孔口导电层连接，所述同轴大孔导电结构与所述同轴小孔导电结构的导通情况和所述同轴金属化过孔的对准度相关，其中，所述同轴金属化过孔的对准度包括所述同轴小孔的偏差量和/或偏移方向。
可选地，所述同轴大孔导电结构包括同轴大孔连接焊盘、连接通孔和同轴大孔测试焊盘；所述同轴小孔导电结构包括连接盲孔和同轴小孔测试焊盘；
在对同轴大孔孔口导电层背离印制电路板的一侧进行层压后到达同轴小孔孔口导电层之前，还包括：
形成同轴大孔连接焊盘，其中，所述同轴大孔连接焊盘和所述同轴大孔孔 口导电层位于同层，位于所述同轴大孔的外侧且与所述同轴大孔孔口导电层连接；
对所述同轴大孔进行绝缘材料塞孔处理；
在层压之后的结构形成至少一个同轴小孔，其中，所述同轴小孔为金属化过孔，所述同轴小孔的导电层包括同轴小孔层，所述同轴小孔层包括同轴小孔孔口导电层和同轴小孔孔内导电层；一组同轴金属化过孔中，同轴大孔孔口导电层中与其位于所述印制电路板同层的同轴小孔层位于不同层；
在层压之后的结构形成至少一个同轴小孔之后，还包括：
形成连接盲孔的孔底焊盘，其中，所述连接盲孔的孔底焊盘与所述同轴小孔孔口导电层位于同层，所述连接盲孔的孔底焊盘在所述印制电路板的正投影至少覆盖所述同轴大孔孔内导电层环内区域在所述印制电路板的正投影；
将所述印制电路板的内层和外层压合，在所述印制电路中形成连接通孔和连接盲孔，其中，所述连接通孔在所述印制电路板的正投影覆盖所述同轴大孔连接焊盘在所述印制电路板的正投影的至少部分，所述连接盲孔的孔底焊盘与所述连接通孔绝缘设置；
在所述印制电路板的外层形成同轴小孔测试焊盘和同轴大孔测试焊盘，其中，所述同轴大孔测试焊盘覆盖所述连接通孔的孔口的至少部分，所述同轴大孔测试焊盘与所述同轴小孔测试焊盘的导通情况和所述同轴金属化过孔的对准度相关，其中，所述同轴金属化过孔的对准度包括所述同轴小孔的偏差量和/或偏移方向。
可选地，在层压之后的结构形成至少一个同轴小孔，包括：
在层压之后的结构钻出n个孔径不同的同轴小孔；
其中，n个所述同轴小孔的孔径包括：第一孔径、第二孔径……第n孔径，所述n的取值包括大于或等于1的整数；n个所述同轴小孔与所述同轴大孔的孔径差异包括：第一孔径差异、第二孔径差异……第n孔径差异，其中，第一孔径差异＞第二孔径差异＞……＞第n孔径差异；第i组同轴金属化过孔中的同轴小孔的孔径为第i孔径，第i孔径的同轴小孔与所述同轴大孔的孔径差异为第i孔径差异，所述i的取值包括大于或等于1，且小于或等于n的整数。
可选地，在印制电路板的内层形成至少一个同轴大孔，包括：
在印制电路板的内层钻出至少一个同轴大孔；
通过沉铜和电镀工艺将所述同轴大孔形成金属化过孔，其中，所述同轴大孔的导电层包括同轴大孔层，所述同轴大孔层包括两同轴大孔孔口导电层和同 轴大孔孔内导电层；
在所述同轴大孔中塞入塞孔器件，其中，所述塞孔器件包括内层硬质支架和柔性外层，所述内层硬质支架的横截面包括实心部和分布在所述实心部边缘的至少两个扇形连接部，所述扇形连接部之间设置有镂空区域；
以所述塞孔器件作为掩膜版，对所述同轴大孔孔内导电层进行湿法腐蚀，以形成至少两个绝缘设置的扇形环的同轴大孔；
形成同轴大孔连接焊盘包括：
对所述同轴大孔孔口导电层所在层的面铜进行刻蚀处理，以形成至少两个绝缘设置的扇形连接焊盘，其中，所述扇形连接焊盘环绕所述扇形环设置，且所述扇形连接焊盘与所述扇形环一一对应连接，所述连接通孔包括至少两个，所述连接通孔在所述印制电路板的正投影一一覆盖位于所述扇形连接焊盘在所述印制电路板的正投影的至少部分。
可选地，每组同轴金属化过孔中，对同轴大孔孔口导电层背离印制电路板的一侧进行层压后到达同轴小孔孔口导电层，包括：
对同轴大孔孔口导电层背离印制电路板的一侧层压至少一层到达同轴小孔孔口导电层。
本实施例提供的技术方案，同轴大孔导电结构作为同轴大孔的第一电信号引出结构；同轴小孔导电结构作为同轴小孔的第二电信号引出结构。通过检测同轴大孔导电结构和同轴小孔导电结构的导通情况，确定同轴小孔的偏差量和/或偏移方向，无需通过切片工艺检测内层的同轴化金属过孔的对准度，实现了无损检测，简化了检测流程，进而节省了检测成本。
附图说明
图1是根据本申请实施例提供的一种印制电路板的结构示意图；
图2是根据本申请实施例提供的另一种印制电路板的结构示意图；
图3是根据本申请实施例提供的又一种印制电路板的结构示意图；
图4是图3中3组同轴金属化过孔的俯视图；
图5是图3中3组同轴金属化过孔的立体图；
图6是图5中3组同轴金属化过孔以及同轴大孔连接焊盘的俯视图；
图7是图5中3组同轴金属化过孔的立体展开图；
图8是同轴小孔测试焊盘和同轴大孔测试焊盘的俯视图；
图9是根据本申请实施例提供的一种印制电路板的制备方法的流程图；
图10是根据本申请实施例提供的一种印制电路板的制备方法各步骤对应的结构示意图；
图11是根据本申请实施例提供的另一种印制电路板的制备方法各步骤对应的结构示意图；
图12是根据本申请实施例提供的又一种印制电路板的制备方法各步骤对应的结构示意图；
图13是根据本申请实施例提供的又一种印制电路板的制备方法各步骤对应的结构示意图；
图14是根据本申请实施例提供的又一种印制电路板的制备方法各步骤对应的结构示意图；
图15是根据本申请实施例提供的又一种印制电路板的制备方法各步骤对应的结构示意图；
图16是根据本申请实施例提供的另一种印制电路板的制备方法的流程图；
图17是根据本申请实施例提供的又一种印制电路板的制备方法的流程图；
图18是根据本申请实施例提供的又一种印制电路板的制备方法各步骤的结构图；
图19是根据本申请实施例提供的又一种印制电路板的制备方法各步骤的结构图；
图20是根据本申请实施例提供的又一种印制电路板的制备方法各步骤的结构图；
图21是根据本申请实施例提供的又一种印制电路板的制备方法各步骤的结构图；
图22是根据本申请实施例提供的又一种印制电路板的制备方法各步骤的结构图；
图23是根据本申请实施例提供的又一种印制电路板的制备方法各步骤的结构图；
图24是根据本申请实施例提供的又一种印制电路板的制备方法各步骤的结构图；
图25是根据本申请实施例提供的又一种印制电路板的制备方法各步骤的结构图；
图26是根据本申请实施例还提供的一种印制电路板的同轴孔对准度的测试方法的流程示意图；
图27是根据本申请实施例还提供的另一种印制电路板的同轴孔对准度的测试方法的流程示意图；
图28是根据本申请实施例还提供的又一种印制电路板的同轴孔对准度的测试方法的流程示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，所描述的实施例仅仅是本申请一部分的实施例。
需要说明的是，本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
本申请实施例提供了一种印制电路板。该印制电路板包括：印制电路板的内层包括至少一组同轴金属化过孔，其中，每组同轴金属化过孔包括同轴大孔和同轴小孔，同轴大孔和同轴小孔之间设置有绝缘材料，同轴大孔的导电层包括同轴大孔层，同轴小孔的导电层包括同轴小孔层，同轴大孔层包括同轴大孔孔口导电层和同轴大孔孔内导电层，同轴小孔层包括同轴小孔孔口导电层和同轴小孔孔内导电层；一组同轴金属化过孔中，同轴大孔孔口导电层中与其位于印制电路板同层的同轴小孔孔口导电层位于不同层；印制电路板还包括同轴大孔导电结构和同轴小孔导电结构，同轴大孔导电结构与同轴大孔孔口导电层连接，同轴小孔导电结构与同轴小孔孔口导电层连接，同轴大孔导电结构与同轴小孔导电结构的导通情况和同轴金属化过孔的对准度相关，其中，同轴金属化过孔的对准度包括同轴小孔的偏差量和/或偏移方向。
本实施例提供的技术方案，同轴大孔导电结构作为同轴大孔的第一电信号引出结构；同轴小孔导电结构作为同轴小孔的第二电信号引出结构。通过检测同轴大孔导电结构和同轴小孔导电结构的导通情况，确定同轴小孔的偏差量和/或偏移方向，无需通过切片工艺检测内层的同轴化金属过孔的对准度，实现了无损检测，简化了检测流程，进而节省了检测成本。
可选地，印制电路板还包括同轴大孔连接焊盘、连接通孔和连接盲孔；同轴大孔连接焊盘和同轴大孔孔口导电层位于同层，位于同轴大孔的外侧且与同轴大孔孔口导电层连接；连接通孔在印制电路板的正投影覆盖同轴大孔连接焊盘在印制电路板的正投影的至少部分；连接盲孔的孔底焊盘与同轴小孔孔口导电层位于同层，连接盲孔的孔底焊盘在印制电路板的正投影至少覆盖同轴大孔孔内导电层环内区域在印制电路板的正投影，且与连接通孔绝缘设置；印制电路板的外层包括同轴小孔测试焊盘和同轴大孔测试焊盘，同轴大孔测试焊盘覆盖连接通孔的孔口的至少部分，同轴小孔测试焊盘覆盖连接盲孔的孔口的至少部分。同轴大孔连接焊盘、连接通孔和同轴大孔测试焊盘构成同轴大孔导电结构；连接盲孔和同轴小孔测试焊盘构成同轴小孔导电结构。同轴大孔测试焊盘和同轴小孔测试焊盘的导通情况和同轴金属化过孔的对准度相关，其中，同轴金属化过孔的对准度包括同轴小孔的偏差量和/或偏移方向。
图1是根据本申请实施例提供的一种印制电路板的结构示意图。图2是根据本申请实施例提供的另一种印制电路板的结构示意图。示例性的，参见图1和图2，印制电路板的内层包括3组同轴金属化过孔。3个同轴大孔M0，一个同轴大孔M0和一个同轴小孔构成一组同轴金属化过孔，同轴小孔包括第一同轴小孔m1、第二同轴小孔m2和第三同轴小孔m3。同轴大孔M0的导电层包括同轴大孔层，同轴小孔的导电层包括同轴小孔层，同轴大孔层包括同轴大孔孔口导电层Ls和同轴大孔孔内导电层L01，同轴小孔层包括同轴小孔孔口导电层Ls-q和同轴小孔孔内导电层L02，其中q的取值包括大于或等于1的整数。同轴大孔M0和同轴小孔之间设置有绝缘材料例如是树脂材料。印制电路板还包括同轴大孔连接焊盘11、连接通孔12和连接盲孔13；同轴大孔连接焊盘11、连接通孔12和同轴大孔测试焊盘15构成同轴大孔导电结构；连接盲孔13和同轴小孔测试焊盘16构成同轴小孔导电结构。同轴大孔连接焊盘11和同轴大孔孔口导电层Ls位于同层，且与同轴大孔孔口导电层Ls连接；连接通孔12在印制电路板的正投影覆盖同轴大孔连接焊盘11在印制电路板的正投影的部分；连接盲孔13的孔底焊盘14与同轴小孔孔口导电层Ls-q位于同层，连接盲孔13的孔底焊盘14在印制电路板的正投影覆盖同轴大孔孔内导电层L01环内区域在印制电路板的正投影，且与连接通孔12绝缘设置。印制电路板的外层包括同轴小孔测试焊盘16和同轴大孔测试焊盘15，同轴大孔测试焊盘15覆盖连接通孔12的孔口，同轴小孔测试焊盘16覆盖连接盲孔13的孔口，同轴大孔测试焊盘15和同轴小孔测试焊盘16的导通情况与同轴金属化过孔的对准度相关，其中，同轴金属化过孔的对准度包括同轴小孔的偏差量和/或偏移方向。
图1中，第一同轴小孔m1没有和同轴大孔M0接触，第一同轴小孔m1 相对同轴大孔M0是断路连接。第二同轴小孔m2没有和同轴大孔M0接触，第二同轴小孔m2相对同轴大孔M0是断路连接。第三同轴小孔m3没有和同轴大孔M0接触，第三同轴小孔m3相对同轴大孔M0是断路连接。
图2中，第一同轴小孔m1和同轴大孔M0接触，第一同轴小孔m1相对同轴大孔M0是短路连接。第二同轴小孔m2和同轴大孔M0接触，第二同轴小孔m2相对同轴大孔M0是短路连接。第三同轴小孔m3和同轴大孔M0接触，第三同轴小孔m3相对同轴大孔M0是短路连接。
具体的，同轴大孔连接焊盘11和同轴大孔孔口导电层Ls位于同层，且与同轴大孔孔口导电层Ls连接，连接通孔12在印制电路板的正投影覆盖同轴大孔连接焊盘11在印制电路板的正投影的部分，同轴大孔测试焊盘15覆盖连接通孔12的孔口，同轴大孔连接焊盘11和连接通孔12作为同轴大孔M0的同轴大孔层的第一电信号引出结构，可以将同轴大孔M0的同轴大孔层和同轴大孔测试焊盘15组成通路。
连接盲孔13的孔底焊盘14与同轴小孔孔口导电层Ls-q位于同层，连接盲孔13的孔底焊盘14在印制电路板的正投影至少覆盖同轴大孔孔内导电层L01环内区域在印制电路板的正投影，且与连接通孔12绝缘设置，同轴小孔测试焊盘16覆盖连接盲孔13的孔口，连接盲孔13的孔底焊盘14和连接盲孔13作为同轴小孔的同轴小孔层的第二电信号引出结构，可以将同轴小孔和同轴小孔测试焊盘16组成通路。
同时，同轴大孔连接焊盘11位于同轴大孔M0的外侧，连接通孔12在印制电路板的正投影覆盖同轴大孔连接焊盘11在印制电路板的正投影的至少部分，连接通孔12和连接盲孔13之间绝缘设置，因此，如果同轴大孔测试焊盘15和同轴小孔测试焊盘16导通时，必然是同轴小孔和同轴大孔M0接触，才会导致同轴大孔测试焊盘15和同轴小孔测试焊盘16构成通路，形成短路连接。
本实施例提供的技术方案，同轴大孔连接焊盘和连接通孔作为同轴大孔的第一电信号引出结构，可以将同轴大孔和同轴大孔测试焊盘组成通路；连接盲孔的孔底焊盘和连接盲孔作为同轴小孔的第二电信号引出结构，可以将同轴小孔和同轴小孔测试焊盘组成通路。同时，同轴大孔连接焊盘位于同轴大孔的外侧，连接通孔在印制电路板的正投影覆盖同轴大孔连接焊盘在印制电路板的正投影的至少部分，连接通孔和连接盲孔之间绝缘设置。只有在同轴小孔和同轴大孔接触的情况下，才会导致同轴大孔测试焊盘和同轴小孔测试焊盘构成通路，形成短路连接。因此本实施例提供的印制电路板，通过检测同轴大孔测试焊盘和同轴小孔测试焊盘的导通情况，确定同轴小孔的偏差 量和/或偏移方向，无需通过切片工艺检测内层的同轴化金属过孔的对准度，实现了无损检测，简化了检测流程，进而节省了检测成本。
可选地，该印制电路板包括n组同轴金属化过孔，其中，n的取值包括大于或等于1的整数；n个同轴小孔的孔径包括：第一孔径、第二孔径……第n孔径；n个同轴小孔与同轴大孔的孔径差异包括：第一孔径差异、第二孔径差异……第n孔径差异，其中，第一孔径差异＞第二孔径差异＞……＞第n孔径差异；第i组同轴金属化过孔中的同轴小孔的孔径为第i孔径，第i孔径的同轴小孔与同轴大孔的孔径差异为第i孔径差异，i的取值包括大于或等于1，且小于或等于n的整数。
图3是根据本申请实施例提供的又一种印制电路板的结构示意图。图4是图3中3组同轴金属化过孔的俯视图。示例性的，参见图3和图4，3组同轴金属化过孔，第一同轴小孔m1的孔径为第一孔径d1，第二同轴小孔m2的孔径为第二孔径d2，第三同轴小孔m3的孔径为第三孔径d3。第一同轴小孔m1的孔径和同轴大孔M0的孔径差异为第一孔径差异△d1，第二同轴小孔m2的孔径和同轴大孔M0的孔径差异为第二孔径差异△d2，第三同轴小孔m3的孔径和同轴大孔M0的孔径差异为第三孔径差异△d3。第一孔径差异＞第二孔径差异＞第三孔径差异。
第一同轴小孔m1和第二同轴小孔m2相对同轴大孔M0虽然在某一偏移方向存在偏差量，但是同轴小孔和同轴大孔M0还没有接触，同轴大孔测试焊盘15和同轴小孔测试焊盘16没有构成通路，是断路连接。第三同轴小孔m3相对同轴大孔M0在某一偏移方向存在偏差量，第三同轴小孔m3和同轴大孔M0接触，同轴大孔测试焊盘15和同轴小孔测试焊盘16构成通路，是短路连接。需要说明的是，可以毫无疑义推出，在其他实施例中，如果设置第四同轴小孔m4，第四同轴小孔m4的孔径为第四孔径d4，第四同轴小孔m4和同轴大孔M0的孔径差异为第四孔径差异△d4，第四同轴小孔m4和同轴大孔M0的孔径差异大于第三同轴小孔m3相对同轴大孔M0孔径差异，因此，第四同轴小孔m4和同轴大孔M0的偏移量使得两者接触，第四同轴小孔m4的同轴小孔测试焊盘16和同轴大孔M0的同轴大孔测试焊盘15构成通路，是短路连接。在上述示例中，第三同轴小孔m3和同轴大孔M0的孔径差异为同轴小孔的偏差量。
具体的，在多组同轴金属化过孔中，通过设置不同孔径的同轴小孔，在同轴小孔测试焊盘和同轴大孔测试焊盘导通的各组同轴金属化过孔中，孔径最小的同轴小孔和同轴大孔的孔径差异为同轴小孔的偏差量。上述印制电路板可以快速且准确得到同轴金属化过孔中，同轴小孔的偏差量。
可选地，同轴大孔孔内导电层包括至少两个绝缘设置的扇形环；同轴大孔连接焊盘包括至少两个绝缘设置的扇形连接焊盘，扇形连接焊盘环绕扇形环设置，且扇形连接焊盘与扇形环一一对应连接；连接通孔包括至少两个，连接通孔在印制电路板的正投影一一对应覆盖位于扇形连接焊盘在印制电路板的正投影的至少部分；同轴大孔测试焊盘包括至少两个，同轴大孔测试焊盘一一对应覆盖连接通孔的孔口的至少部分。
图5是图3中3组同轴金属化过孔的立体图。图6是图5中3组同轴金属化过孔的俯视图。图7是图5中3组同轴金属化过孔的立体展开图。图8是同轴小孔测试焊盘和同轴大孔测试焊盘的俯视图。其中，图7中每一组同轴金属化过孔外围示出了两个连接通孔。示例性的，参见图6，同轴大孔孔内导电层L01包括8个绝缘设置的扇形环，分别是第一扇形环A、第二扇形环B、第三扇形环C、第四扇形环D、第五扇形环E、第六扇形环F、第七扇形环G和第八扇形环H；同轴大孔连接焊盘11包括8个绝缘设置的扇形连接焊盘，分别是第一扇形连接焊盘110a、第二扇形连接焊盘110b、第三扇形连接焊盘110c、第四扇形连接焊盘110d、第五扇形连接焊盘110e、第六扇形连接焊盘110f、第七扇形连接焊盘110g和第八扇形连接焊盘110h，扇形连接焊盘环绕扇形环设置，且扇形连接焊盘与扇形环一一对应连接；连接通孔12包括8个，连接通孔12在印制电路板的正投影一一对应覆盖位于扇形连接焊盘在印制电路板的部分。示例性的，图8中同轴大孔测试焊盘包括8个同轴大孔测试焊盘，分别是第一同轴大孔测试焊盘150a、第二同轴大孔测试焊盘150b、第三同轴大孔测试焊盘150c、第四同轴大孔测试焊盘150d、第五同轴大孔测试焊盘150e、第六同轴大孔测试焊盘150f、第七同轴大孔测试焊盘150和第八同轴大孔测试焊盘150h。同轴大孔测试焊盘与连接通孔12一一对应电连接。
其中，第一同轴小孔m1和第二同轴小孔m2相对同轴大孔M0虽然在同轴金属化过孔的轴心指向扇形环H的偏移方向存在偏差量，但是同轴小孔和同轴大孔M0还没有接触，任何一个同轴大孔测试焊盘和同轴小孔测试焊盘16都没有构成通路，是断路连接。第三同轴小孔m3相对同轴大孔M0在同轴金属化过孔的轴心指向第八扇形环H的偏移方向存在偏差量，第三同轴小孔m3和同轴大孔M0的第八扇形环H接触，穿过第八扇形连接焊盘110h的连接通孔12和与之对应的第八同轴大孔测试焊盘150h电连接，进而使得第八同轴大孔测试焊盘150h和同轴小孔测试焊盘16构成通路，是短路连接。上述示例中可以确定第八同轴大孔测试焊盘150h相对同轴小孔的方向为同轴小孔的偏移方向。
具体的，在多组同轴金属化过孔中，获取各组同轴金属化过孔中，同轴 小孔测试焊盘和每一个同轴大孔测试焊盘的导通情况；同轴小孔测试焊盘和同轴大孔测试焊盘导通的各组同轴金属化过孔中，与同轴小孔焊盘导通的同轴大孔测试焊盘相对同轴小孔焊盘的方位为所述同轴小孔的偏移方位。上述印制电路板可以快速且准确得到同轴金属化过孔中，同轴小孔的偏移方位。
可选地，每组同轴金属化过孔中，位于印制电路板同侧的同轴小孔孔口导电层和同轴大孔孔口导电层中，同轴小孔孔口导电层中和外层的间隔层数小于同轴大孔孔口导电层和外层的间隔层数。
示例性的，参见图1-图3以及图5-图7，同轴小孔孔口导电层Ls-q和外层的间隔层数小于同轴大孔孔口导电层Ls和外层的间隔层数，使得同轴小孔孔口导电层Ls-q相比同轴大孔孔口导电层Ls更靠近外层，可以实现在连接盲孔13的孔底焊盘14与同轴小孔孔口导电层Ls-q位于同层，覆盖同轴小孔的孔口，且与同轴大孔M0的内径相等的情况下，连接通孔12和连接盲孔13绝缘设置，只有在同轴小孔和同轴大孔M0接触的情况下，才会导致同轴大孔测试焊盘15和同轴小孔测试焊盘16构成通路，形成短路连接。进而可以通过检测同轴大孔测试焊盘15和同轴小孔测试焊盘16的导通情况，确定同轴金属化过孔的对准度，无需通过切片工艺检测内层的同轴化金属过孔的对准度，实现了无损检测，简化了检测流程，进而节省了检测成本。
本申请实施例还提供了一种印制电路板的制备方法。该制备方法包括：
S110、在印制电路板的内层形成至少一个同轴大孔，其中，同轴大孔为金属化过孔，同轴大孔的导电层包括同轴大孔层，同轴大孔层包括两同轴大孔孔口导电层和同轴大孔孔内导电层；
S120、对同轴大孔孔口导电层背离印制电路板的一侧进行层压后到达同轴小孔孔口导电层；
S130、在层压之后的结构形成至少一个同轴小孔，其中，同轴小孔为金属化过孔，同轴小孔的导电层包括同轴小孔层，同轴小孔层包括同轴小孔孔口导电层和同轴小孔孔内导电层；一组同轴金属化过孔中，同轴大孔孔口导电层中与其位于印制电路板同层的同轴小孔层位于不同层；
S140、还包括形成同轴大孔导电结构和同轴小孔导电结构，同轴大孔导电结构与同轴大孔孔口导电层连接，同轴小孔导电结构与同轴小孔孔口导电层连接，同轴大孔导电结构与同轴小孔导电结构的导通情况和同轴金属化过孔的对准度相关，其中，同轴金属化过孔的对准度包括同轴小孔的偏差量和/或偏移方向。
本实施例提供的技术方案，同轴大孔导电结构作为同轴大孔的第一电信号引出结构；同轴小孔导电结构作为同轴小孔的第二电信号引出结构。通过检测同轴大孔导电结构和同轴小孔导电结构的导通情况，确定同轴小孔的偏差量和/或偏移方向，无需通过切片工艺检测内层的同轴化金属过孔的对准度，实现了无损检测，简化了检测流程，进而节省了检测成本。
图9是根据本申请实施例提供的一种印制电路板的制备方法的流程图。参见图9，该印制电路板的制备方法包括：
S110、在印制电路板的内层形成至少一个同轴大孔，其中，同轴大孔为金属化过孔，同轴大孔的导电层包括同轴大孔层，同轴大孔层包括两同轴大孔孔口导电层和同轴大孔孔内导电层。
参见图10，在印制电路板的内层形成三个同轴大孔M0，其中，同轴大孔M0为金属化过孔，同轴大孔M0的导电层包括同轴大孔层，同轴大孔层包括两同轴大孔孔口导电层Ls和同轴大孔孔内导电层L01。
S120、形成同轴大孔连接焊盘，其中，同轴大孔连接焊盘和同轴大孔孔口导电层位于同层，位于同轴大孔的外侧且与同轴大孔孔口导电层连接。
参见图11，形成同轴大孔连接焊盘11，其中，同轴大孔连接焊盘11和同轴大孔孔口导电层Ls位于同层，位于同轴大孔M0的外侧且与同轴大孔孔口导电层Ls连接。同轴大孔连接焊盘11作为同轴大孔M0的电信号引出结构。
S130、对同轴大孔进行绝缘材料塞孔处理。
参见图11，对同轴大孔M0进行绝缘材料塞孔处理。使得同轴大孔M0和同轴小孔之间设置有绝缘材料例如是树脂材料。
S140、对同轴大孔孔口导电层背离印制电路板的一侧进行层压后到达同轴小孔孔口导电层。
参见图12，对同轴大孔孔口导电层Ls背离印制电路板的一侧经过层压后到达同轴小孔孔口导电层Ls-q，使得同轴大孔孔口导电层Ls和同轴小孔孔口导电层Ls-q位于不同层。其中q的取值包括大于或等于1的整数。
可选地，S140的每组同轴金属化过孔中，对同轴大孔孔口导电层背离印制电路板的一侧进行层压后到达同轴小孔孔口导电层包括：
对同轴大孔孔口导电层Ls背离印制电路板的一侧层压至少一层到达同轴小孔孔口导电层Ls-q。
具体的，同轴小孔孔口导电层Ls-q和外层的间隔层数小于同轴大孔孔口 导电层Ls和外层的间隔层数，使得同轴小孔孔口导电层Ls-q相比同轴大孔孔口导电层Ls更靠近外层，可以实现在连接盲孔13的孔底焊盘14与同轴小孔孔口导电层Ls-q位于同层，连接盲孔13的孔底焊盘14在印制电路板的正投影至少覆盖同轴大孔孔内导电层L01环内区域在印制电路板的正投影，且与连接通孔12绝缘设置，进而可以通过检测同轴大孔测试焊盘和同轴小孔测试焊盘的导通情况，确定同轴金属化过孔的对准度，无需通过切片工艺检测内层的同轴化金属过孔的对准度，实现了无损检测，简化了检测流程，进而节省了检测成本。
S150、在层压之后的结构形成至少一个同轴小孔，其中，同轴小孔为金属化过孔，其中，同轴小孔为金属化过孔，同轴小孔的导电层包括同轴小孔层，同轴小孔层包括同轴小孔孔口导电层和同轴小孔孔内导电层；一组同轴金属化过孔中，同轴大孔对应的两同轴大孔孔口导电层中与其位于印制电路板同层的同轴小孔层位于不同层。
参见图13，在同轴小孔孔口导电层Ls-q形成三个同轴小孔。其中，同轴小孔为金属化过孔，同轴大孔M0环绕同轴小孔设置。使得印制电路板的内层包括3组同轴金属化过孔。一个同轴大孔M0和一个同轴小孔构成一组同轴金属化过孔，同轴小孔包括第一同轴小孔m1、第二同轴小孔m2和第三同轴小孔m3。
S160、形成连接盲孔的孔底焊盘，其中，连接盲孔的孔底焊盘与同轴小孔孔口导电层位于同层，连接盲孔的孔底焊盘在印制电路板的正投影至少覆盖同轴大孔孔内导电层环内区域在印制电路板的正投影。
参见图13，连接盲孔的孔底焊盘14与同轴小孔孔口导电层Ls-q位于同层，连接盲孔13的孔底焊盘14在印制电路板的正投影至少覆盖同轴大孔孔内导电层L01环内区域在印制电路板的正投影，且与连接通孔12绝缘设置。连接盲孔的孔底焊盘14作为第一同轴小孔m1、第二同轴小孔m2和第三同轴小孔m3的电信号引出结构。
S170、将印制电路板的内层和外层压合，在印制电路中形成连接通孔和连接盲孔，其中，连接通孔在印制电路板的正投影覆盖同轴大孔连接焊盘在印制电路板的正投影的至少部分，所述连接盲孔的孔底焊盘与所述连接通孔绝缘设置。
参见图14，通过压合工艺将印制电路板的内层和外层压合。参见图15，在印制电路中形成连接通孔12和连接盲孔13，其中，连接通孔12在印制电路板的正投影覆盖同轴大孔连接焊盘11在印制电路板的正投影的至少部分，连接盲孔13的孔底焊盘14与连接通孔12绝缘设置，使得连接通孔12通过 同轴大孔连接焊盘11与同轴大孔M0电连接。
S180、在印制电路板的外层形成同轴小孔测试焊盘和同轴大孔测试焊盘，其中，同轴大孔测试焊盘覆盖连接通孔的孔口的至少部分，同轴小孔测试焊盘覆盖连接盲孔的孔口的至少部分，同轴大孔测试焊盘和同轴小孔测试焊盘的导通情况和同轴金属化过孔的对准度相关，其中，同轴金属化过孔的对准度包括同轴小孔的偏差量和/或偏移方向。
参见图1，在印制电路板的外层形成同轴小孔测试焊盘16和同轴大孔测试焊盘15。同轴大孔连接焊盘11和同轴大孔孔口导电层Ls位于同层，且与同轴大孔孔口导电层Ls连接，接通孔12在印制电路板的正投影覆盖同轴大孔连接焊盘11在印制电路板的正投影的部分，同轴大孔测试焊盘15覆盖连接通孔12的孔口，同轴大孔连接焊盘11和连接通孔12作为同轴大孔M0的第一电信号引出结构，可以将同轴大孔M0和同轴大孔测试焊盘15组成通路。连接盲孔13的孔底焊盘14与同轴小孔孔口导电层Ls-q位于同层，连接盲孔13的孔底焊盘14在印制电路板的正投影覆盖同轴大孔孔内导电层L01环内区域在印制电路板的正投影，且与连接通孔12绝缘设置，同轴小孔测试焊盘16覆盖连接盲孔13的孔口，连接盲孔13的孔底焊盘14和连接盲孔13作为同轴小孔的第二电信号引出结构，可以将同轴小孔和同轴小孔测试焊盘16组成通路。同时，同轴大孔连接焊盘11位于同轴大孔M0的外侧，连接通孔12在印制电路板的正投影覆盖同轴大孔连接焊盘15在印制电路板的正投影的至少部分，且连接通孔12和连接盲孔13之间绝缘设置。因此，如果同轴大孔测试焊盘15和同轴小孔测试焊盘16导通时，必然是同轴小孔和同轴大孔M0接触，才会导致同轴大孔测试焊盘15和同轴小孔测试焊盘16构成通路，形成短路连接。
本实施例提供的技术方案，同轴大孔连接焊盘和连接通孔作为同轴大孔的第一电信号引出结构，可以将同轴大孔和同轴大孔测试焊盘组成通路；连接盲孔的孔底焊盘和连接盲孔作为同轴小孔的第二电信号引出结构，可以将同轴小孔和同轴小孔测试焊盘组成通路。同时，同轴大孔连接焊盘位于同轴大孔的外侧，连接通孔在印制电路板的正投影覆盖同轴大孔连接焊盘在印制电路板的正投影的至少部分，连接通孔和连接盲孔之间绝缘设置。只有在同轴小孔和同轴大孔接触的情况下，才会导致同轴大孔测试焊盘和同轴小孔测试焊盘构成通路，形成短路连接。因此本实施例提供的印制电路板，通过检测同轴大孔测试焊盘和同轴小孔测试焊盘的导通情况，确定同轴小孔的偏差量和/或偏移方向，无需通过切片工艺检测内层的同轴化金属过孔的对准度，实现了无损检测，简化了检测流程，进而节省了检测成本。
需要说明的是，图2和图3示出的印制电路板的制备方法与图1的制备方法相同。只是在S150时，同轴小孔的孔径、偏移量和偏移方向有所不同。
图16是根据本申请实施例提供的另一种印制电路板的制备方法的流程图。图16与图9有所区别的是，进一步对图9中的S150进行了限定。具体的，参见图16，该印制电路板的制备方法包括如下步骤：
S210、在印制电路板的内层形成至少一个同轴大孔，其中，同轴大孔为金属化过孔，同轴大孔的导电层包括同轴大孔层，同轴大孔层包括两同轴大孔孔口导电层和同轴大孔孔内导电层。
S220、形成同轴大孔连接焊盘，其中，同轴大孔连接焊盘和同轴大孔孔口导电层位于同层，位于同轴大孔的外侧且与同轴大孔孔口导电层连接。
S230、对同轴大孔进行绝缘材料塞孔处理。
S240、对同轴大孔孔口导电层背离印制电路板的一侧进行层压后到达同轴小孔孔口导电层。
需要说明的是，S210-S240的实施步骤和有益效果可以参照S110-S140的实施步骤和有益效果执行。
S250、在层压之后的结构钻出n个孔径不同的同轴小孔。
其中，n个同轴小孔的孔径包括：第一孔径、第二孔径……第n孔径，n的取值包括大于或等于1的整数；n个同轴小孔与同轴大孔的孔径差异包括：第一孔径差异、第二孔径差异……第n孔径差异，其中，第一孔径差异＞第二孔径差异＞……＞第n孔径差异；第i组同轴金属化过孔中的同轴小孔的孔径为第i孔径，第i孔径的同轴小孔与同轴大孔的孔径差异为第i孔径差异，i的取值包括大于或等于1，且小于或等于n的整数。
示例性的，参见图3和图4，3组同轴金属化过孔，第一同轴小孔m1的孔径为第一孔径d1，第二同轴小孔m2的孔径为第二孔径d2，第三同轴小孔m3的孔径为第三孔径d3。第一同轴小孔m1的孔径和同轴大孔M0的孔径差异为第一孔径差异△d1，第二同轴小孔m2的孔径和同轴大孔M0的孔径差异为第二孔径差异△d2，第三同轴小孔m3的孔径和同轴大孔M0的孔径差异为第三孔径差异△d3。第一孔径差异＞第二孔径差异＞第三孔径差异。
第一同轴小孔m1和第二同轴小孔m2相对同轴大孔M0虽然在某一偏移方向存在偏差量，但是同轴小孔和同轴大孔M0还没有接触，同轴大孔测试焊盘15和同轴小孔测试焊盘16没有构成通路，是断路连接。第三同轴小孔m3相对同轴大孔M0在某一偏移方向存在偏差量，第三同轴小孔m3和同轴大孔M0接触，同轴大孔测试焊盘15和同轴小孔测试焊盘16构成通路，是 短路连接。需要说明的是，可以毫无疑义推出，在其他实施例中，如果设置第四同轴小孔m4，第四同轴小孔m4的孔径为第四孔径d4，第四同轴小孔m4和同轴大孔M0的孔径差异为第四孔径差异△d4，第四同轴小孔m4和同轴大孔M0的孔径差异大于第三同轴小孔m3相对同轴大孔M0孔径差异，因此，第四同轴小孔m4和同轴大孔M0的偏移量使得两者接触，第四同轴小孔m4的同轴小孔测试焊盘16和同轴大孔M0的同轴大孔测试焊盘15构成通路，是短路连接。在上述示例中，第三同轴小孔m3和同轴大孔M0的孔径差异为同轴小孔的偏差量。
S260、形成连接盲孔的孔底焊盘，其中，连接盲孔的孔底焊盘与同轴小孔孔口导电层位于同层，连接盲孔的孔底焊盘在印制电路板的正投影至少覆盖同轴大孔孔内导电层环内区域在印制电路板的正投影。
S270、将印制电路板的内层和外层压合，在印制电路中形成连接通孔和连接盲孔，其中，连接通孔在印制电路板的正投影覆盖同轴大孔连接焊盘在印制电路板的正投影的至少部分，所述连接盲孔的孔底焊盘与所述连接通孔绝缘设置。
S280、在印制电路板的外层形成同轴小孔测试焊盘和同轴大孔测试焊盘，其中，同轴大孔测试焊盘覆盖连接通孔的孔口的至少部分，同轴小孔测试焊盘覆盖连接盲孔的孔口的至少部分，同轴大孔测试焊盘和同轴小孔测试焊盘的导通情况和同轴金属化过孔的对准度相关，其中，同轴金属化过孔的对准度包括同轴小孔的偏差量和/或偏移方向。
需要说明的是，S260-S280的实施步骤和有益效果可以参照S160-S180的实施步骤和有益效果执行。
具体的，在上述技术方案的基础上，在多组同轴金属化过孔中，通过设置不同孔径的同轴小孔，在同轴小孔测试焊盘和同轴大孔测试焊盘导通的各组同轴金属化过孔中，孔径最小的同轴小孔和同轴大孔的孔径差异为同轴小孔的偏差量。上述印制电路板可以快速且准确得到同轴金属化过孔中，同轴小孔的偏差量。
图17是根据本申请实施例提供的又一种印制电路板的制备方法的流程图。在上述技术方案的基础上，对于S110和S120以及S210和S220进了进一步限定。参见图17，该印制电路板的制备方法包括如下步骤：
S310、在印制电路板的内层钻出至少一个同轴大孔。
参见图10，在印制电路板的同轴大孔孔口导电层Ls钻出至少一个同轴大孔M0。
S320、通过沉铜和电镀工艺将同轴大孔形成金属化过孔，其中，同轴大孔的导电层包括同轴大孔层，同轴大孔层包括两同轴大孔孔口导电层和同轴大孔孔内导电层。
参见图10，通过沉铜和电镀工艺将同轴大孔形成金属化过孔，其中，同轴大孔M0的导电层包括同轴大孔层，同轴大孔层包括两同轴大孔孔口导电层Ls和同轴大孔孔内导电层L01。
S330、在同轴大孔中塞入塞孔器件，其中，塞孔器件包括内层硬质支架和柔性外层，内层硬质支架的横截面包括实心部和分布在实心部边缘的至少两个扇形连接部，扇形连接部之间设置有镂空区域。
参见图18，在同轴大孔M0中塞入塞孔器件200。参见图19和图20，塞孔器件200包括内层硬质支架201和柔性外层202，内层硬质支架201的横截面包括实心部201a和分布在实心部201a边缘的至少两个扇形连接部201b，扇形连接部201b之间设置有镂空区域203。示例性的，塞孔器件200是圆柱体，其长度与同轴大孔M0的深度相等，塞孔器件200的直径与同轴大孔M0的内径相同。示例性的，图19和图20中，塞孔器件200是米字型圆柱体塞孔器件。内层硬质支架201需要有较硬的质地，起支撑作用，方便塞入孔中，且能够自由控制塞入深度，其材质需耐酸碱、不导电、不吸收药水、不与电镀药水发生反应，可采用聚四氟乙烯等硬性材料。柔性外层202的材料需质地软，可形变，耐酸碱腐蚀且不与药水反应，用于完全填充塞孔器件与孔壁的间隙，避免药水进入材料。柔性外层202例如可采用PVC等软性材质。
S340、以塞孔器件作为掩膜版，对同轴大孔孔内导电层进行湿法腐蚀，以形成至少两个绝缘设置的扇形环的同轴大孔。
参见图18，以塞孔器件200作为掩膜版，对同轴大孔内导电层L01进行湿法腐蚀，以形成至少两个绝缘设置的扇形环的同轴大孔M0。其中，同轴大孔M0孔壁内未被塞孔器件200挡住的区域(镂空区域203)的铜被蚀刻掉，挡住区域的铜被保留。这样同轴大孔M0蚀刻后孔壁就被竖向分割为8块局部金属化的区域，8块区域即可区别上下左右以及沿45°角的8个方向。图21和图22中，同轴大孔M0包括8个绝缘设置的扇形环，分别是第一扇形环A、第二扇形环B、第三扇形环C、第四扇形环D、第五扇形环E、第六扇形环F、第七扇形环G和第八扇形环H。
S350、对同轴大孔孔口导电层所在层的面铜进行刻蚀处理，以形成至少两个绝缘设置的扇形连接焊盘，其中，扇形连接焊盘环绕扇形环设置，且扇形连接焊盘与扇形环一一对应连接，连接通孔包括至少两个，连接通孔在印 制电路板的正投影一一覆盖位于扇形连接焊盘在印制电路板的正投影的至少部分。
参见图18，对同轴大孔孔口导电层Ls所在层的第一区域面铜301进行刻蚀处理，第二区域面铜300没有被蚀刻，虚线区域由于被干膜所覆盖，所以虚线区域的面铜在去除干膜后可以形成至少两个绝缘设置的扇形连接焊盘，其中，扇形连接焊盘环绕扇形环设置，且扇形连接焊盘与扇形环一一对应连接。图21中，同轴大孔连接焊盘11包括8个绝缘设置的扇形连接焊盘，分别是第一扇形连接焊盘110a、第二扇形连接焊盘110b、第三扇形连接焊盘110c、第四扇形连接焊盘110d、第五扇形连接焊盘110e、第六扇形连接焊盘110f、第七扇形连接焊盘110g和第八扇形连接焊盘110h。
参见图5，第一同轴小孔m1和第二同轴小孔m2相对同轴大孔M0虽然在同轴金属化过孔的轴心指向扇形环H的偏移方向存在偏差量，但是同轴小孔和同轴大孔M0还没有接触，任何一个同轴大孔测试焊盘和同轴小孔测试焊盘16都没有构成通路，是断路连接。第三同轴小孔m3相对同轴大孔M0在同轴金属化过孔的轴心指向第八扇形环H的偏移方向存在偏差量，第三同轴小孔m3和同轴大孔M0的第八扇形环H接触，穿过第八扇形连接焊盘110h的连接通孔12和与之对应的第八同轴大孔测试焊盘150h电连接，进而使得第八同轴大孔测试焊盘150h和同轴小孔测试焊盘16构成通路，是短路连接。上述示例中可以确定第八同轴大孔测试焊盘150h相对同轴小孔的方向为同轴小孔的偏移方向。
S360、对同轴大孔进行绝缘材料塞孔处理。
需要说明的是，S360的实施步骤和有益效果可以参照S130的实施步骤和有益效果执行。
S370、对同轴大孔孔口导电层背离印制电路板的一侧进行层压后到达同轴小孔孔口导电层。
需要说明的是，S370的实施步骤和有益效果可以参照S140的实施步骤和有益效果执行。
S380、在层压之后的结构形成至少一个同轴小孔，其中，同轴小孔为金属化过孔，其中，同轴小孔为金属化过孔，同轴小孔的导电层包括同轴小孔层，同轴小孔层包括同轴小孔孔口导电层和同轴小孔孔内导电层；一组同轴金属化过孔中，同轴大孔对应的两同轴大孔孔口导电层中与其位于印制电路板同层的同轴小孔层位于不同层。
需要说明的是，S380的实施步骤和有益效果可以参照S150的实施步骤 和有益效果执行。
示例性的，参见图23，在同轴小孔层Ls-q形成了第一同轴小孔m1。第一同轴小孔m1为金属化过孔，同轴大孔M0环绕第一同轴小孔m1设置。
S390、形成连接盲孔的孔底焊盘，其中，连接盲孔的孔底焊盘与同轴小孔孔口导电层位于同层，连接盲孔的孔底焊盘在印制电路板的正投影至少覆盖同轴大孔孔内导电层环内区域在印制电路板的正投影。
需要说明的是，S390的实施步骤和有益效果可以参照S160的实施步骤和有益效果执行。
参见图23，在同轴小孔孔口层Ls-q形成连接盲孔的孔底焊盘14，其中，连接盲孔的孔底焊盘14与同轴小孔孔口导电层Ls-q位于同层，连接盲孔13的孔底焊盘14在印制电路板的正投影至少覆盖同轴大孔孔内导电层L01环内区域在印制电路板的正投影，且与连接通孔12绝缘设置，连接盲孔的孔底焊盘14作为第一同轴小孔m1的电信号引出结构。
S391、将印制电路板的内层和外层压合，在印制电路中形成连接通孔和连接盲孔，其中，连接通孔在印制电路板的正投影覆盖同轴大孔连接焊盘在印制电路板的正投影的至少部分，所述连接盲孔的孔底焊盘与所述连接通孔绝缘设置。
需要说明的是，S391的实施步骤和有益效果可以参照S170的实施步骤和有益效果执行。
参见图24和图25，通过压合工艺将印制电路板的内层和外层压合。在印制电路中形成连接通孔12和连接盲孔13。其中，8个连接通孔12在印制电路板的正投影一一对应位于扇形连接焊盘在印制电路板的正投影之内，使得连接通孔12通过同轴大孔连接焊盘11与同轴大孔M0电连接。
S392、在印制电路板的外层形成同轴小孔测试焊盘和至少两个同轴大孔测试焊盘，其中，同轴大孔测试焊盘一一对应覆盖连接通孔的孔口的至少部分，同轴小孔测试焊盘覆盖连接盲孔的孔口的至少部分，同轴大孔测试焊盘和同轴小孔测试焊盘的导通情况和同轴金属化过孔的对准度相关，其中，同轴金属化过孔的对准度包括同轴小孔的偏差量和/或偏移方向。
参见图25，在印制电路板的外层形成同轴小孔测试焊盘16和同轴大孔测试焊盘15。同轴大孔测试焊盘15的数量为8个，同轴大孔测试焊盘15与连接通孔12一一对应电连接。
参见图5，同轴大孔M0包括8个绝缘设置的扇形环，分别是第一扇形环A、第二扇形环B、第三扇形环C、第四扇形环D、第五扇形环E、第六 扇形环F、第七扇形环G和第八扇形环H；同轴大孔连接焊盘11包括8个绝缘设置的扇形连接焊盘，分别是第一扇形连接焊盘110a、第二扇形连接焊盘110b、第三扇形连接焊盘110c、第四扇形连接焊盘110d、第五扇形连接焊盘110e、第六扇形连接焊盘110f、第七扇形连接焊盘110g和第八扇形连接焊盘110h，扇形连接焊盘环绕扇形环设置，且扇形连接焊盘与扇形环一一对应连接；连接通孔12包括8个，连接通孔12在印制电路板的正投影一一对应位于扇形连接焊盘在印制电路板的正投影之内。示例性的，图8中同轴大孔测试焊盘包括8个同轴大孔测试焊盘，分别是第一同轴大孔测试焊盘150a、第二同轴大孔测试焊盘150b、第三同轴大孔测试焊盘150c、第四同轴大孔测试焊盘150d、第五同轴大孔测试焊盘150e、第六同轴大孔测试焊盘150f、第七同轴大孔测试焊盘150和第八同轴大孔测试焊盘150h。同轴大孔测试焊盘与连接通孔12一一对应电连接。
具体的，在多组同轴金属化过孔中，获取各组同轴金属化过孔中，同轴小孔测试焊盘和每一个同轴大孔测试焊盘的导通情况；同轴小孔测试焊盘和同轴大孔测试焊盘导通的各组同轴金属化过孔中，同轴大孔测试焊盘相对同轴小孔焊盘的方位为所述同轴小孔的偏移方位。
本申请实施例还提供了印制电路板的同轴孔对准度的测试方法的流程示意图。
S410、获取同轴大孔导电结构和同轴小孔导电结构的导通情况。
S410、根据同轴大孔导电结构和同轴小孔导电结构的导通情况确定同轴金属化过孔的对准度，其中，同轴金属化过孔的对准度包括同轴小孔的偏差量和/或偏移方向。
本实施例提供的技术方案，同轴大孔导电结构作为同轴大孔的第一电信号引出结构；同轴小孔导电结构作为同轴小孔的第二电信号引出结构。通过检测同轴大孔导电结构和同轴小孔导电结构的导通情况，确定同轴小孔的偏差量和/或偏移方向，无需通过切片工艺检测内层的同轴化金属过孔的对准度，实现了无损检测，简化了检测流程，进而节省了检测成本。
图26是根据本申请实施例还提供的一种印制电路板的同轴孔对准度的测试方法的流程示意图。参见图26，该种印制电路板的同轴孔对准度的测试方法包括如下步骤：
S410、获取各组同轴金属化过孔中同轴大孔测试焊盘和同轴小孔测试焊盘的导通情况。
S420、根据各组同轴金属化过孔中同轴大孔测试焊盘和同轴小孔测试焊盘的导通情况，确定同轴金属化过孔的对准度，其中，同轴金属化过孔的对准度包括同轴小孔的偏差量和/或偏移方向。
针对图1-图3的印制电路板，同轴大孔连接焊盘11和同轴大孔孔口导电层Ls位于同层，且与同轴大孔孔口导电层Ls连接，连接通孔12在印制电路板的正投影覆盖同轴大孔连接焊盘11在印制电路板的正投影的部分，同轴大孔测试焊盘15覆盖连接通孔12的孔口，同轴大孔连接焊盘11和连接通孔12作为同轴大孔M0的同轴大孔层的第一电信号引出结构，可以将同轴大孔M0的同轴大孔层和同轴大孔测试焊盘15组成通路。
连接盲孔13的孔底焊盘14与同轴小孔孔口导电层Ls-q位于同层，连接盲孔13的孔底焊盘14在印制电路板的正投影至少覆盖同轴大孔孔内导电层L01环内区域在印制电路板的正投影，且与连接通孔12绝缘设置，同轴小孔测试焊盘16覆盖连接盲孔13的孔口，连接盲孔13的孔底焊盘14和连接盲孔13作为同轴小孔的同轴小孔层的第二电信号引出结构，可以将同轴小孔和同轴小孔测试焊盘16组成通路。
同时，同轴大孔连接焊盘11位于同轴大孔M0的外侧，连接通孔12在印制电路板的正投影覆盖同轴大孔连接焊盘11在印制电路板的正投影的至少部分，连接通孔12和连接盲孔13之间绝缘设置，因此，如果同轴大孔测试焊盘15和同轴小孔测试焊盘16导通时，必然是同轴小孔和同轴大孔M0接触，才会导致同轴大孔测试焊盘15和同轴小孔测试焊盘16构成通路，形成短路连接。
本实施例提供的技术方案，同轴大孔连接焊盘和连接通孔作为同轴大孔的第一电信号引出结构，可以将同轴大孔和同轴大孔测试焊盘组成通路；连接盲孔的孔底焊盘和连接盲孔作为同轴小孔的第二电信号引出结构，可以将同轴小孔和同轴小孔测试焊盘组成通路。同时，同轴大孔连接焊盘位于同轴大孔的外侧，连接通孔在印制电路板的正投影覆盖同轴大孔连接焊盘在印制电路板的正投影的至少部分，连接通孔和连接盲孔之间绝缘设置，使得连接通孔和连接盲孔之间绝缘设置。只有在同轴小孔和同轴大孔接触的情况下，才会导致同轴大孔测试焊盘和同轴小孔测试焊盘构成通路，形成短路连接。因此本实施例提供的印制电路板，通过检测同轴大孔测试焊盘和同轴小孔测试焊盘的导通情况，确定同轴小孔的偏差量和/或偏移方向，无需通过切片工艺检测内层的同轴化金属过孔的对准度，实现了无损检测，简化了检测流程，进而节省了检测成本。
图27是根据本申请实施例还提供的另一种印制电路板的同轴孔对准度 的测试方法的流程示意图。图27对于图26中的S420进行了进一步限定。参见图27，该印制电路板的同轴孔对准度的测试方法包括如下步骤：
S510、获取各组同轴金属化过孔中同轴大孔测试焊盘和同轴小孔测试焊盘的导通情况。
S520、同轴小孔测试焊盘和同轴大孔测试焊盘导通的各组同轴金属化过孔中，孔径最小的同轴小孔和同轴大孔的孔径差异为同轴小孔的偏差量。
针对图3示出的印制电路板，包括3组同轴金属化过孔，第一同轴小孔m1的孔径为第一孔径d1，第二同轴小孔m2的孔径为第二孔径d2，第三同轴小孔m3的孔径为第三孔径d3。第一同轴小孔m1的孔径和同轴大孔M0的孔径差异为第一孔径差异△d1，第二同轴小孔m2的孔径和同轴大孔M0的孔径差异为第二孔径差异△d2，第三同轴小孔m3的孔径和同轴大孔M0的孔径差异为第三孔径差异△d3。第一孔径差异＞第二孔径差异＞第三孔径差异。
第一同轴小孔m1和第二同轴小孔m2相对同轴大孔M0虽然在某一偏移方向存在偏差量，但是同轴小孔和同轴大孔M0还没有接触，同轴大孔测试焊盘15和同轴小孔测试焊盘16没有构成通路，是断路连接。第三同轴小孔m3相对同轴大孔M0在某一偏移方向存在偏差量，第三同轴小孔m3和同轴大孔M0接触，同轴大孔测试焊盘15和同轴小孔测试焊盘16构成通路，是短路连接。需要说明的是，可以毫无疑义推出，在其他实施例中，如果设置第四同轴小孔m4，第四同轴小孔m4的孔径为第四孔径d4，第四同轴小孔m4和同轴大孔M0的孔径差异为第四孔径差异△d4，第四同轴小孔m4和同轴大孔M0的孔径差异大于第三同轴小孔m3相对同轴大孔M0孔径差异，因此，第四同轴小孔m4和同轴大孔M0的偏移量使得两者接触，第四同轴小孔m4的同轴小孔测试焊盘16和同轴大孔M0的同轴大孔测试焊盘15构成通路，是短路连接。在上述示例中，第三同轴小孔m3和同轴大孔M0的孔径差异为同轴小孔的偏差量。
具体的，在多组同轴金属化过孔中，通过设置不同孔径的同轴小孔，在同轴小孔测试焊盘和同轴大孔测试焊盘导通的各组同轴金属化过孔中，孔径最小的同轴小孔和同轴大孔的孔径差异为同轴小孔的偏差量。上述印制电路板可以快速且准确得到同轴金属化过孔中，同轴小孔的偏差量。
图28是根据本申请实施例还提供的又一种印制电路板的同轴孔对准度的测试方法的流程示意图。图28对于图26中的S410和S420进行了进一步 限定。参见图28，该印制电路板的同轴孔对准度的测试方法包括如下步骤：
S610、获取各组同轴金属化过孔中，同轴小孔测试焊盘和每一个同轴大孔测试焊盘的导通情况；
S620、同轴小孔测试焊盘和同轴大孔测试焊盘导通的各组同轴金属化过孔中，与同轴小孔测试焊盘导通的同轴大孔测试焊盘相对同轴小孔焊盘的方位为同轴小孔的偏移方位。
针对图5示出的印制电路板，同轴大孔M0包括8个绝缘设置的扇形环，分别是第一扇形环A、第二扇形环B、第三扇形环C、第四扇形环D、第五扇形环E、第六扇形环F、第七扇形环G和第八扇形环H；同轴大孔连接焊盘11包括8个绝缘设置的扇形连接焊盘，分别是第一扇形连接焊盘110a、第二扇形连接焊盘110b、第三扇形连接焊盘110c、第四扇形连接焊盘110d、第五扇形连接焊盘110e、第六扇形连接焊盘110f、第七扇形连接焊盘110g和第八扇形连接焊盘110h，扇形连接焊盘环绕扇形环设置，且扇形连接焊盘与扇形环一一对应连接；连接通孔12包括8个，连接通孔12在印制电路板的正投影一一对应位于扇形连接焊盘在印制电路板的正投影之内。示例性的，图8中同轴大孔测试焊盘包括8个同轴大孔测试焊盘，分别是第一同轴大孔测试焊盘150a、第二同轴大孔测试焊盘150b、第三同轴大孔测试焊盘150c、第四同轴大孔测试焊盘150d、第五同轴大孔测试焊盘150e、第六同轴大孔测试焊盘150f、第七同轴大孔测试焊盘150和第八同轴大孔测试焊盘150h。同轴大孔测试焊盘与连接通孔12一一对应电连接。
其中，第一同轴小孔m1和第二同轴小孔m2相对同轴大孔M0虽然在同轴金属化过孔的轴心指向扇形环H的偏移方向存在偏差量，但是同轴小孔和同轴大孔M0还没有接触，任何一个同轴大孔测试焊盘和同轴小孔测试焊盘16都没有构成通路，是断路连接。第三同轴小孔m3相对同轴大孔M0在同轴金属化过孔的轴心指向第八扇形环H的偏移方向存在偏差量，第三同轴小孔m3和同轴大孔M0的第八扇形环H接触，穿过第八扇形连接焊盘110h的连接通孔12和与之对应的第八同轴大孔测试焊盘150h电连接，进而使得第八同轴大孔测试焊盘150h和同轴小孔测试焊盘16构成通路，是短路连接。上述示例中可以确定第八同轴大孔测试焊盘150h相对同轴小孔的方向为同轴小孔的偏移方向。
具体的，在多组同轴金属化过孔中，获取各组同轴金属化过孔中，同轴小孔测试焊盘和每一个同轴大孔测试焊盘的导通情况；同轴小孔测试焊盘和同轴大孔测试焊盘导通的各组同轴金属化过孔中，与同轴小孔焊盘导通的同轴大孔测试焊盘相对同轴小孔焊盘的方位为所述同轴小孔的偏移方位。上述 印制电路板可以快速且准确得到同轴金属化过孔中，同轴小孔的偏移方位。
应该理解，可以使用上面所示的各种形式的流程，重新排序、增加或删除步骤。例如，本申请中记载的各步骤可以并行地执行也可以顺序地执行也可以不同的次序执行，只要能够实现本申请的技术方案所期望的结果，本文在此不进行限制。

Claims (10)

  1. 一种印制电路板，所述印制电路板包括内层和外层，其中，所述印制电路板的内层包括至少一组同轴金属化过孔，其中，每组同轴金属化过孔包括同轴大孔和同轴小孔，所述同轴大孔和所述同轴小孔之间设置有绝缘材料，所述同轴大孔的导电层包括同轴大孔层，所述同轴小孔的导电层包括同轴小孔层，所述同轴大孔层包括同轴大孔孔口导电层和同轴大孔孔内导电层，所述同轴小孔层包括同轴小孔孔口导电层和同轴小孔孔内导电层；一组同轴金属化过孔中，同轴大孔孔口导电层中与其位于所述印制电路板同层的同轴小孔孔口导电层位于不同层；
    所述印制电路板还包括同轴大孔导电结构和同轴小孔导电结构，所述同轴大孔导电结构与所述同轴大孔孔口导电层连接，所述同轴小孔导电结构与所述同轴小孔孔口导电层连接，所述同轴大孔导电结构与所述同轴小孔导电结构的导通情况和所述同轴金属化过孔的对准度相关，其中，所述同轴金属化过孔的对准度包括所述同轴小孔的偏差量和/或偏移方向。
  2. 根据权利要求1所述的印制电路板，还包括同轴大孔连接焊盘、连接通孔和连接盲孔；所述同轴大孔连接焊盘和所述同轴大孔孔口导电层位于同层，位于所述同轴大孔的外侧且与所述同轴大孔孔口导电层连接；所述连接通孔在所述印制电路板的正投影覆盖所述同轴大孔连接焊盘在所述印制电路板的正投影的至少部分；所述连接盲孔的孔底焊盘与所述同轴小孔孔口导电层位于同层，所述连接盲孔的孔底焊盘在所述印制电路板的正投影至少覆盖所述同轴大孔孔内导电层环内区域在所述印制电路板的正投影，且与所述连接通孔绝缘设置；
    所述印制电路板的外层包括同轴小孔测试焊盘和同轴大孔测试焊盘，所述同轴大孔测试焊盘覆盖所述连接通孔的孔口的至少部分，所述同轴小孔测试焊盘覆盖所述连接盲孔的孔口的至少部分；
    所述同轴大孔连接焊盘、所述连接通孔和所述同轴大孔测试焊盘构成所述同轴大孔导电结构；所述连接盲孔和同轴小孔测试焊盘构成所述同轴小孔导电结构；
    所述同轴大孔测试焊盘与所述同轴小孔测试焊盘的导通情况和所述同轴金属化过孔的对准度相关，其中，所述同轴金属化过孔的对准度包括所述同轴小孔的偏差量和/或偏移方向。
  3. 根据权利要求1所述的印制电路板，还包括n组同轴金属化过孔，其中，所述n的取值包括大于或等于1的整数；
    n个所述同轴小孔的孔径包括：第一孔径、第二孔径……第n孔径；
    n个所述同轴小孔与所述同轴大孔的孔径差异包括：第一孔径差异、第二孔 径差异……第n孔径差异，其中，第一孔径差异＞第二孔径差异＞……＞第n孔径差异；
    第i组同轴金属化过孔中的同轴小孔的孔径为第i孔径，第i孔径的同轴小孔与所述同轴大孔的孔径差异为第i孔径差异，所述i的取值包括大于或等于1，且小于或等于n的整数。
  4. 根据权利要求2所述的印制电路板，其中，所述同轴大孔孔内导电层包括至少两个绝缘设置的扇形环；
    所述同轴大孔连接焊盘包括至少两个绝缘设置的扇形连接焊盘，所述扇形连接焊盘环绕所述扇形环设置，且所述扇形连接焊盘与所述扇形环一一对应连接；
    所述连接通孔包括至少两个，所述连接通孔在所述印制电路板的正投影一一覆盖位于所述扇形连接焊盘在所述印制电路板的正投影的至少部分；
    所述同轴大孔测试焊盘包括至少两个，所述同轴大孔测试焊盘一一对应覆盖所述连接通孔的孔口的至少部分。
  5. 根据权利要求1所述的印制电路板，其中，每组同轴金属化过孔中，位于所述印制电路板同侧的同轴小孔孔口导电层和同轴大孔孔口导电层中，所述同轴小孔孔口导电层和所述外层的间隔层数小于所述同轴大孔孔口导电层和所述外层的间隔层数。
  6. 一种印制电路板的制备方法，包括：
    在印制电路板的内层形成至少一个同轴大孔，其中，所述同轴大孔为金属化过孔，所述同轴大孔的导电层包括同轴大孔层，所述同轴大孔层包括两同轴大孔孔口导电层和同轴大孔孔内导电层；
    对同轴大孔孔口导电层背离印制电路板的一侧进行层压后到达同轴小孔孔口导电层；
    在层压之后的结构形成至少一个同轴小孔，其中，所述同轴小孔为金属化过孔，所述同轴小孔的导电层包括同轴小孔层，所述同轴小孔层包括同轴小孔孔口导电层和同轴小孔孔内导电层；一组同轴金属化过孔中，同轴大孔孔口导电层中与其位于所述印制电路板同层的同轴小孔层位于不同层；
    还包括形成同轴大孔导电结构和同轴小孔导电结构，所述同轴大孔导电结构与所述同轴大孔孔口导电层连接，所述同轴小孔导电结构与所述同轴小孔孔口导电层连接，所述同轴大孔导电结构与所述同轴小孔导电结构的导通情况和所述同轴金属化过孔的对准度相关，其中，所述同轴金属化过孔的对准度包括 所述同轴小孔的偏差量和/或偏移方向。
  7. 根据权利要求6所述的印制电路板的制备方法，其中，所述同轴大孔导电结构包括同轴大孔连接焊盘、连接通孔和同轴大孔测试焊盘；所述同轴小孔导电结构包括连接盲孔和同轴小孔测试焊盘；
    在对同轴大孔孔口导电层背离印制电路板的一侧进行层压后到达同轴小孔孔口导电层之前，还包括：
    形成同轴大孔连接焊盘，其中，所述同轴大孔连接焊盘和所述同轴大孔孔口导电层位于同层，位于所述同轴大孔的外侧且与所述同轴大孔孔口导电层连接；
    对所述同轴大孔进行绝缘材料塞孔处理；
    在层压之后的结构形成至少一个同轴小孔，其中，所述同轴小孔为金属化过孔，所述同轴小孔的导电层包括同轴小孔层，所述同轴小孔层包括同轴小孔孔口导电层和同轴小孔孔内导电层；一组同轴金属化过孔中，同轴大孔孔口导电层中与其位于所述印制电路板同层的同轴小孔层位于不同层；
    在层压之后的结构形成至少一个同轴小孔之后还包括：
    形成连接盲孔的孔底焊盘，其中，所述连接盲孔的孔底焊盘与所述同轴小孔孔口导电层位于同层，所述连接盲孔的孔底焊盘在所述印制电路板的正投影至少覆盖所述同轴大孔孔内导电层环内区域在所述印制电路板的正投影；
    将所述印制电路板的内层和外层压合，在所述印制电路中形成连接通孔和连接盲孔，其中，所述连接通孔在所述印制电路板的正投影覆盖所述同轴大孔连接焊盘在所述印制电路板的正投影的至少部分，所述连接盲孔的孔底焊盘与所述连接通孔绝缘设置；
    在所述印制电路板的外层形成同轴小孔测试焊盘和同轴大孔测试焊盘，其中，所述同轴大孔测试焊盘覆盖所述连接通孔的孔口的至少部分，所述同轴大孔测试焊盘与所述同轴小孔测试焊盘的导通情况和所述同轴金属化过孔的对准度相关，其中，所述同轴金属化过孔的对准度包括所述同轴小孔的偏差量和/或偏移方向。
  8. 根据权利要求6所述的印制电路板的制备方法，其中，在层压之后的结构形成至少一个同轴小孔，包括：
    在层压之后的结构钻出n个孔径不同的同轴小孔；
    其中，n个所述同轴小孔的孔径包括：第一孔径、第二孔径……第n孔径，所述n的取值包括大于或等于1的整数；n个所述同轴小孔与所述同轴大孔的孔 径差异包括：第一孔径差异、第二孔径差异……第n孔径差异，其中，第一孔径差异＞第二孔径差异＞……＞第n孔径差异；第i组同轴金属化过孔中的同轴小孔的孔径为第i孔径，第i孔径的同轴小孔与所述同轴大孔的孔径差异为第i孔径差异，所述i的取值包括大于或等于1，且小于或等于n的整数。
  9. 根据权利要求6所述的印制电路板的制备方法，其中，在印制电路板的内层形成至少一个同轴大孔，包括：
    在印制电路板的内层钻出至少一个同轴大孔；
    通过沉铜和电镀工艺将所述同轴大孔形成金属化过孔，其中，所述同轴大孔的导电层包括同轴大孔层，所述同轴大孔层包括两同轴大孔孔口导电层和同轴大孔孔内导电层；
    在所述同轴大孔中塞入塞孔器件，其中，所述塞孔器件包括内层硬质支架和柔性外层，所述内层硬质支架的横截面包括实心部和分布在所述实心部边缘的至少两个扇形连接部，所述扇形连接部之间设置有镂空区域；
    以所述塞孔器件作为掩膜版，对所述同轴大孔孔内导电层进行湿法腐蚀，以形成至少两个绝缘设置的扇形环的同轴大孔；
    形成同轴大孔连接焊盘包括：
    对所述同轴大孔孔口导电层所在层的面铜进行刻蚀处理，以形成至少两个绝缘设置的扇形连接焊盘，其中，所述扇形连接焊盘环绕所述扇形环设置，且所述扇形连接焊盘与所述扇形环一一对应连接，所述连接通孔包括至少两个，所述连接通孔在所述印制电路板的正投影一一覆盖位于所述扇形连接焊盘在所述印制电路板的正投影的至少部分。
  10. 根据权利要求6所述的印制电路板的制备方法，其中，每组同轴金属化过孔中，对同轴大孔孔口导电层背离印制电路板的一侧进行层压后到达同轴小孔孔口导电层包括：
    对同轴大孔孔口导电层背离印制电路板的一侧层压至少一层到达同轴小孔孔口导电层。
PCT/CN2023/111810 2022-08-09 2023-08-08 印制电路板以及制备方法 WO2024032628A1 (zh)

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