WO2024031944A1 - 驱动可调谐激光器的自动锁相恒流源电路及方法 - Google Patents

驱动可调谐激光器的自动锁相恒流源电路及方法 Download PDF

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Publication number
WO2024031944A1
WO2024031944A1 PCT/CN2023/075038 CN2023075038W WO2024031944A1 WO 2024031944 A1 WO2024031944 A1 WO 2024031944A1 CN 2023075038 W CN2023075038 W CN 2023075038W WO 2024031944 A1 WO2024031944 A1 WO 2024031944A1
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voltage
phase
current source
constant current
input
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PCT/CN2023/075038
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English (en)
French (fr)
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姜明顺
魏钧涛
张法业
张雷
王晓龙
隋青美
贾磊
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山东大学
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Publication of WO2024031944A1 publication Critical patent/WO2024031944A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters

Definitions

  • the present invention relates to the technical field of constant current sources, and in particular to an automatic phase-locked constant current source circuit and method for driving a tunable laser.
  • Fiber Bragg Grating is a wavelength-modulated optical fiber sensor, referred to as fiber grating.
  • the wavelength of fiber grating reflects the measured information, so its wavelength needs to be accurately demodulated.
  • Commonly used fiber grating demodulation methods include edge filter method, tunable filter method, tunable laser method, etc.
  • the fiber grating wavelength demodulation method based on tunable laser has the advantages of fast demodulation speed, high stability and low cost. Low-level advantages have become a research hotspot in recent years.
  • Tunable lasers need to be driven by a high-precision current source.
  • the driving current range is generally 0 ⁇ 30mA.
  • the commonly used precision current driving method is a current output digital-to-analog conversion chip (DAC).
  • the output current range is generally 0 ⁇ 20mA and cannot be covered.
  • the driving current range of the laser is tunable. Therefore, a voltage output DAC combined with a voltage-controlled constant current source circuit is often used to realize laser driving. Among them, the voltage output DAC technology solution is mature, and the voltage-controlled constant current source circuit is the key to realizing laser driving.
  • phase lag of the output current of the voltage-controlled constant current source will cause the system demodulation speed to decrease
  • the present invention proposes an automatic phase-locked constant current source circuit and method for driving a tunable laser.
  • the phase-locked loop is used to realize the automatic locking of the output current to the input voltage, ensuring that the output current of the voltage-controlled constant current source is the same as the input voltage.
  • the frequency is in phase, which eliminates the phase difference between the output current lagging the input voltage and greatly improves the demodulation speed of the high-speed fiber grating demodulator.
  • an automatic phase-locked constant current source circuit for driving a tunable laser including a sequential phase lag circuit, a phase-locked loop, an adder and a voltage-controlled constant current source.
  • the output end of the voltage-controlled constant current source and a high-pass filter Connection, the high-pass filter is connected to the phase-locked loop;
  • the phase lag circuit can phase-lag the input voltage and input it into the phase-locked loop.
  • the phase-locked loop multiplies the phase lag voltage and the feedback voltage to obtain the superimposed voltage. It filters and oscillates the superimposed voltage and then inputs it into the adder.
  • the device adds the oscillation voltage and the DC bias voltage and then inputs it into the voltage-controlled constant current source.
  • the output voltage of the voltage-controlled constant current source enters the high-pass filter for high-pass filtering and then inputs the feedback voltage into the phase-locked loop.
  • a control method for an automatic phase-locked constant current source circuit that drives a tunable laser including:
  • the phase lag circuit lags the phase of the input voltage and then inputs it into the phase-locked loop;
  • the phase-locked loop multiplies the phase lag voltage and the feedback voltage to obtain the superimposed voltage, filters and oscillates the superimposed voltage and then inputs it into the adder;
  • the adder adds the oscillation voltage and the DC bias voltage and then inputs them into the voltage-controlled constant current source;
  • the feedback voltage is input into the phase-locked loop.
  • the present invention uses a phase-locked loop to automatically lock the output current to the input voltage, ensuring that the output current and the input voltage are in the same frequency and phase, eliminating the phase difference between the output current and the input voltage, and greatly improving the performance of the high-speed fiber grating demodulator.
  • the demodulation speed solves the problem of slow demodulation speed when the traditional constant current source drives the tunable laser.
  • the low-pass filter in the phase-locked loop of the present invention adopts a program-controlled low-pass filter, which can set different cutoff frequencies for different input voltage signals, thereby improving the adaptability of the automatic phase-locked constant current source proposed by the present invention.
  • Figure 1 is a circuit diagram of an example of a traditional voltage-controlled constant current source
  • Figure 2 is a circuit diagram of the second example of a traditional voltage-controlled constant current source
  • Figure 3 is a waveform diagram of Example 1 of a traditional voltage-controlled constant current source when the input signal is 1MHz;
  • Figure 4 shows the cursor data of Example 1 of a traditional voltage-controlled constant current source when the input signal is 1MHz;
  • Figure 5 is a waveform diagram of Example 1 of a traditional voltage-controlled constant current source when the input signal is 10MHz;
  • Figure 6 shows the cursor data of Example 1 of a traditional voltage-controlled constant current source when the input signal is 10MHz;
  • Figure 7 is the waveform diagram of Example 2 of a traditional voltage-controlled constant current source when the input signal is 5MHz;
  • Figure 8 shows the cursor data of Example 2 of the traditional voltage-controlled constant current source when the input signal is 5MHz
  • Figure 9 is the waveform diagram of Example 2 of a traditional voltage-controlled constant current source when the input signal is 10MHz;
  • Figure 10 shows the cursor data of Example 2 of the traditional voltage-controlled constant current source when the input signal is 10MHz
  • Figure 11 is a system block diagram of the automatic phase locking constant current source circuit disclosed in Embodiment 1;
  • Figure 12 is a first simulation circuit diagram of the automatic phase-locked constant current source circuit disclosed in Embodiment 1;
  • Figure 13 is a first example of the automatic phase-locked constant current source circuit disclosed in Embodiment 1. Waveform graph;
  • Figure 14 is a first example of the automatic phase-locked constant current source circuit disclosed in Embodiment 1. and Waveform graph;
  • Figure 15 is the first cursor data of the automatic phase locking constant current source circuit disclosed in Embodiment 1;
  • Figure 16 is a second simulation circuit diagram of the automatic phase-locking constant current source circuit disclosed in Embodiment 1;
  • Figure 17 is a second example of the automatic phase-locked constant current source circuit disclosed in Embodiment 1. Waveform graph;
  • Figure 18 is a second example of the automatic phase-locked constant current source circuit disclosed in Embodiment 1. and Waveform graph;
  • FIG. 19 shows the second cursor data of the automatic phase-locking constant current source circuit disclosed in Embodiment 1.
  • the output current signal will phase lag as the frequency of the input voltage signal increases.
  • the current at the collector of transistor Q 1 is the output current I o .
  • the output current acts solely on the resistor R 1 and the voltage is the positive feedback voltage U fp .
  • the output current acts alone on the resistor.
  • the voltage of R 2 is the negative feedback voltage U fn .
  • R 1 , R 2 , R 3 , R 4 , R 5 , R 6 and R 7 are all the resistance values of the resistors in Figure 1.
  • the oscilloscope waveform is shown in Figure 3.
  • Channel A is the input voltage waveform
  • channel B is the output current waveform.
  • the oscilloscope waveform is as shown in Figure 5.
  • the output current lags behind the input voltage by 6.2092ns.
  • the signal period is 100ns, so the phase of the output current lags 22.3531°.
  • R 1 and R 2 in the circuit form a series current negative feedback.
  • the current at the collector of transistor Q 1 is the output current I o , and the voltage of the output current acting alone on R 1 is negative.
  • Feedback voltage U fn find the negative feedback coefficient F n of the circuit as:
  • the transconductance gain A iuf of the circuit is:
  • the input voltage frequency is set to 5MHz. Use software simulation to open the graphical instrument.
  • the oscilloscope waveform is shown in Figure 7.
  • Channel A is the input voltage waveform and channel B is the output current waveform.
  • the oscilloscope waveform is shown in Figure 9.
  • this embodiment proposes an automatic phase-locked constant current source circuit for driving the tunable laser, as shown in Figure 11, including the following steps: Connected phase lag circuit, phase locked loop, adder and voltage controlled constant current source, voltage controlled constant current The output end of the source used to connect to the load is also connected to the high-pass filter, and the high-pass filter is connected to the phase-locked loop;
  • the phase lag circuit can phase-lag the input voltage and input it into the phase-locked loop.
  • the phase-locked loop multiplies the phase lag voltage and the feedback voltage to obtain the superimposed voltage. It filters and oscillates the superimposed voltage and then inputs it into the adder.
  • the device adds the oscillation voltage and the DC bias voltage and then inputs it into the voltage-controlled constant current source.
  • the output voltage of the voltage-controlled constant current source enters the high-pass filter for high-pass filtering and then inputs the feedback voltage into the phase-locked loop.
  • the main control module is connected to the voltage output module, and the voltage output module is connected to the phase lag circuit to provide input voltage for the phase lag circuit.
  • the phase-locked loop includes a phase detector, a loop filter and a voltage-controlled oscillator connected in sequence; the phase lag circuit and the high-pass filter are all connected to the phase detector.
  • the phase detector includes a multiplier and a low-pass filter connected in sequence; the phase lag circuit and the high-pass filter are both connected to the multiplier.
  • the low-pass filter adopts a program-controlled low-pass filter, and the program-controlled low-pass filter is connected to the main control module.
  • the phase lag circuit adopts a 90° phase lag circuit.
  • the 90° phase lag circuit can lag the input voltage phase by 90° and is composed of two RC low-pass filters connected in series.
  • the voltage output module uses a voltage output DAC.
  • the adder adds the oscillation voltage and the DC bias voltage to raise the voltage signal above the horizontal axis.
  • the output current of the voltage-controlled constant current source is at the same frequency and in phase with the feedback voltage of the high-pass filter input phase-locked loop; the feedback voltage of the high-pass filter input phase-locked loop is at the same frequency and in phase with the input voltage.
  • the main control module first sends a digital signal to the voltage output DAC, and the DAC outputs a high-frequency analog voltage signal.
  • U i is the input voltage signal, that is, the voltage signal output by the voltage output DAC; ⁇ i is the input voltage signal.
  • the frequency of pressure signal U i , t is time.
  • phase detector in the phase locked loop After the phase detector in the phase locked loop, first with the feedback voltage Doing multiplication is affected by the phase detection characteristics of the phase detector.
  • the phase of will lead The phase is 90°, expressed as:
  • U f is the feedback voltage signal, that is, the voltage signal output by the high-pass filter;
  • ⁇ o is the output voltage signal Frequency of.
  • the deviation is in within the range, and phase deviation between and Positively related. Because The frequency of the low-pass filter is different, and the bandwidth of the low-pass filter also needs to be changed accordingly. Therefore, the bandwidth of the low-pass filter needs to be program-controlled. Select a program-controlled low-pass filter, and connect the program-controlled low-pass filter to the main control module. Through the main control module, The control module controls the cutoff frequency of the programmable low-pass filter. After passing through the loop filter, the high-frequency components are filtered out to obtain a small ripple DC signal that can be used by the voltage controlled oscillator.
  • phase lag voltage with the input phase locked loop Same frequency. again The phase is ahead of The phase of is 90°, then and Same frequency and same phase.
  • Voltage controlled oscillator based on Oscillation output frequency and Positively correlated voltage signals after addition
  • the adder is also connected to the adder with a DC bias U ref , and the adder is Adding a DC bias U ref to raise the voltage signal above the horizontal axis, we get Ensure that the direction of current flowing through the load is constant.
  • the output current is obtained
  • the voltage across the load R L is the output voltage Since the load is purely resistive, the output current and output voltage Same frequency and same phase.
  • the DC component is filtered out and the AC signal is obtained.
  • the simulation circuit diagram is shown in Figure 12.
  • the main control module and voltage output DAC are replaced by the signal source that comes with the software, with a 90° phase lag.
  • the circuit uses two RC low-pass filters in series, consisting of R 1 , C 1 , R 2 , and C 2 .
  • the value of RC is adjusted so that the cutoff frequency is equal to the input signal frequency.
  • One RC low-pass filter can make the input signal phase lag by 45 °, the two paths can lag 90°.
  • the phase-locked loop uses the integrated phase-locked loop PLL_VIRTUAL that comes with the software.
  • the adder consists of operational amplifier U 1 and peripheral resistors.
  • the voltage-controlled constant current source uses the circuit shown in Figure 1, which is composed of operational amplifier U 2 , transistor Q 1 and peripheral capacitors and resistors.
  • the high pass filter consists of C 4 and R 14 . Since the input of the phase detector is the phase difference between the two signals, the amplitude of the signal only affects the proportional coefficient of the output signal of the phase detector, so the feedback voltage signal It only needs to be combined with the output voltage signal of the voltage-controlled constant current source Just keep the same frequency and phase. The amplitude of Exactly the same. Therefore, from the perspective of convenient circuit design, the high-pass filter is led from the upper end of R 12 .
  • Input voltage Set the frequency to 10MHz and observe the oscilloscope XSC2.
  • the displayed waveform is After the feedback adjustment of the phase-locked loop, it can be observed that Gradually approaches 0, as shown in Figure 13.
  • Channel A of the oscilloscope is the voltage output DAC output voltage.
  • waveform, channel B is the output current waveform. when approaches 0, the input voltage is observed and output current The waveform is shown in Figure 14.
  • the voltage-controlled constant current source shown in Figure 2 is used to build a simulation circuit diagram of the automatic phase-locked constant current source circuit disclosed in this embodiment.
  • the input voltage Set the frequency to 10MHz and observe the oscilloscope XSC2.
  • the displayed waveform is After the feedback adjustment of the phase-locked loop, it can be observed that Gradually approaches 0, as shown in Figure 17.
  • Channel A of the oscilloscope is the input voltage. waveform, channel B is the output current waveform. when approaches 0, the input voltage is observed and output current The waveform is shown in Figure 18.
  • the automatic phase-locked constant current source circuit for driving the tunable laser disclosed in this embodiment is verified.
  • the phase-locked loop is used to realize the output current.
  • the phase difference greatly improves the demodulation speed of high-speed fiber grating demodulator. It solves the problem of slow demodulation speed when the traditional constant current source drives the tunable laser.
  • the constant current source circuit disclosed in this embodiment eliminates the output current lags the input voltage When a high-frequency voltage signal is input, the output current of the constant current source circuit can be measured synchronously to determine whether the expected current is output, which effectively improves the demodulation accuracy of the high-speed fiber grating demodulator. It solves the problem of low demodulation accuracy when a traditional constant current source drives a tunable laser.
  • the low-pass filter of the phase detector in the phase-locked loop uses a program-controlled low-pass filter, and the program-controlled low-pass filter is connected to the main control module to set different cutoff frequencies for different input voltage signals to improve adaptability.
  • a control method for an automatic phase-locked constant current source circuit that drives a tunable laser includes:
  • the phase lag circuit lags the phase of the input voltage and then inputs it into the phase-locked loop;
  • the phase-locked loop multiplies the phase lag voltage and the feedback voltage to obtain the superimposed voltage, filters and oscillates the superimposed voltage and then inputs it into the adder;
  • the adder adds the oscillation voltage and the DC bias voltage and then inputs them into the voltage-controlled constant current source;
  • the feedback voltage is input into the phase-locked loop.

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Abstract

本发明公开的驱动可调谐激光器的自动锁相恒流源电路及方法，包括依次连接的相位滞后电路、锁相环、加法器和压控恒流源，压控恒流源的输出端与高通滤波器连接，高通滤波器与锁相环连接；将输入电压输入相位滞后电路中，相位滞后电路能够将输入电压进行相位滞后后，输入锁相环中，锁相环将相位滞后电压和反馈电压做乘法，获得叠加电压，并对叠加电压进行滤波和振荡后输入加法器中，加法器将振荡电压和直流偏置电压相加后输入压控恒流源中，压控恒流源的输出电压进入高通滤波器进行高通滤波后向锁相环中输入反馈电压。实现了输出电流自动锁定输入电压，保证压控恒流源输出电流与输入电压同频同相，消除了输出电流滞后于输入电压的相位差。

Description

驱动可调谐激光器的自动锁相恒流源电路及方法
本发明要求于2022年8月10日提交中国专利局、申请号为202210956456.X、发明名称为“驱动可调谐激光器的自动锁相恒流源电路及方法”的中国专利申请的优先权，其全部内容通过引用结合在本发明中。
技术领域
本发明涉及恒流源技术领域，尤其涉及驱动可调谐激光器的自动锁相恒流源电路及方法。
背景技术
本部分的陈述仅仅是提供了与本发明相关的背景技术信息，不必然构成在先技术。
光纤布拉格光栅(Fiber Bragg Grating,FBG)是一种波长调制型光纤传感器，简称光纤光栅，光纤光栅的波长反映了被测量的信息，因此需要对其波长进行精确解调。常用的光纤光栅进行解调方法有边缘滤波器法、可调滤波器法、可调谐激光器法等，其中，基于可调谐激光器的光纤光栅波长解调方法具有解调速度快、稳定性高、成本低等优点，近年来成为研究热点。可调谐激光器需使用高精度电流源驱动，驱动电流范围一般是0～30mA，常用的精密电流驱动方式为电流输出型数模转换芯片(DAC)，然而输出电流范围一般为0～20mA，无法覆盖可调谐激光器的驱动电流范围，因此，多使用电压输出型DAC配合压控恒流源电路的方案来实现激光器驱动。其中，电压输出型DAC技术方案成熟，压控恒流源电路为实现激光器驱动的关键。
传统的压控恒流源，如图1、图2所示，输出电流信号会随着输入电压信号频 率的升高而发生相位滞后，输入电压频率越高，输出电流滞后于输入电压的相位越大。具有以下缺点：
(1)对于高速光纤光栅解调仪，压控恒流源输出电流的相位滞后会导致系统解调速度降低；
(2)因为滞后相位难以确定，所以输入高频电压信号时，很难测得压控恒流源是否输出了期望的电流，导致系统解调精度降低。
发明内容
本发明为了解决上述问题，提出了驱动可调谐激光器的自动锁相恒流源电路及方法，利用锁相环，实现了输出电流自动锁定输入电压，保证压控恒流源输出电流与输入电压同频同相，消除了输出电流滞后于输入电压的相位差，极大地提升了高速光纤光栅解调仪的解调速度。
为实现上述目的，本发明采用如下技术方案：
第一方面，提出了驱动可调谐激光器的自动锁相恒流源电路，包括依次相位滞后电路、锁相环、加法器和压控恒流源，压控恒流源的输出端与高通滤波器连接，高通滤波器与锁相环连接；
相位滞后电路能够将输入电压进行相位滞后后，输入锁相环中，锁相环将相位滞后电压和反馈电压做乘法，获得叠加电压，并对叠加电压进行滤波和振荡后输入加法器中，加法器将振荡电压和直流偏置电压相加后输入压控恒流源中，压控恒流源的输出电压进入高通滤波器进行高通滤波后向锁相环中输入反馈电压。
第二方面，提出了驱动可调谐激光器的自动锁相恒流源电路的控制方法，包括：
向相位滞后电路中输入输入电压；
相位滞后电路将输入电压相位滞后后输入锁相环中；
锁相环将相位滞后电压和反馈电压做乘法，获得叠加电压，并对叠加电压进行滤波和振荡后输入加法器中；
加法器将振荡电压和直流偏置电压相加后输入压控恒流源中；
压控恒流源的输出电压进入高通滤波器进行滤波后，向锁相环中输入反馈电压。
与现有技术相比，本发明的有益效果为：
1、本发明利用锁相环实现了输出电流自动锁定输入电压，保证输出电流与输入电压同频同相，消除了输出电流滞后于输入电压的相位差，极大地提升了高速光纤光栅解调仪的解调速度，解决了传统恒流源驱动可调谐激光器时，解调速度慢的问题。
2、本发明锁相环中的低通滤波器采用程控低通滤波器，能够针对不同的输入电压信号设置不同的截止频率，提高本发明提出的自动锁相恒流源的适应性。
本发明附加方面的优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本发明的实践了解到。
附图说明
构成本申请的一部分的说明书附图用来提供对本申请的进一步理解，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。
图1为传统压控恒流源示例一电路图；
图2为传统压控恒流源示例二电路图；
图3为输入信号为1MHz时传统压控恒流源示例一的波形图；
图4为输入信号为1MHz时传统压控恒流源示例一的光标数据；
图5为输入信号为10MHz时传统压控恒流源示例一的波形图；
图6为输入信号为10MHz时传统压控恒流源示例一的光标数据；
图7为输入信号为5MHz时传统压控恒流源示例二的波形图；
图8为输入信号为5MHz时传统压控恒流源示例二的光标数据；
图9为输入信号为10MHz时传统压控恒流源示例二的波形图；
图10为输入信号为10MHz时传统压控恒流源示例二的光标数据；
图11为实施例1公开的自动锁相恒流源电路的系统框图；
图12为搭建的实施例1公开自动锁相恒流源电路的第一仿真电路图；
图13为实施例1公开自动锁相恒流源电路的第一波形图；
图14为实施例1公开自动锁相恒流源电路的第一和波形图；
图15为实施例1公开自动锁相恒流源电路的第一光标数据；
图16为搭建的实施例1公开自动锁相恒流源电路的第二仿真电路图；
图17为实施例1公开自动锁相恒流源电路的第二波形图；
图18为实施例1公开自动锁相恒流源电路的第二和波形图；
图19为实施例1公开自动锁相恒流源电路的第二光标数据。
具体实施方式
下面结合附图与实施例对本发明作进一步说明。
应该指出，以下详细说明都是例示性的，旨在对本申请提供进一步的说明。除非另有指明，本文使用的所有技术和科学术语具有与本申请所属技术领域的普通技术人员通常理解的相同含义。
需要注意的是，这里所使用的术语仅是为了描述具体实施方式，而非意图限制根据本申请的示例性实施方式。如在这里所使用的，除非上下文另外明确指出，否则单数形式也意图包括复数形式，此外，还应当理解的是，当在本说明书中使用术语“包含”和/或“包括”时，其指明存在特征、步骤、操作、器件、组件和/或它们的组合。
实施例1
传统的压控恒流源，如图1的示例一和图2的示例二所示，输出电流信号会随着输入电压信号频率的升高而发生相位滞后，输入电压频率越高，输出电流滞后于输入电压的相位越大。
图1中所示的传统压控恒流源，记三极管Q1集电极的电流为输出电流Io，输出电流单独作用于电阻R1的电压为正反馈电压Ufp，输出电流单独作用于电阻R2的电压为负反馈电压Ufn。求出电路的正反馈系数Fp为：
求出电路的负反馈系数Fn为
其中，R1、R2、R3、R4、R5、R6、R7均为图1中电阻的阻值。
调整阻值使得Fn>Fp，保证电路工作于负反馈状态，利用“虚短”和“虚断”求出电路的跨导增益Aiuf为：
输入电压频率设置为1MHz，利用软件仿真，打开图示仪，示波器波形如图3所示。A通道为输入电压波形，B通道为输出电流波形。显示光标，利用软件的“前往下一个Y轴最大值”功能，将光标1自动定位到A通道的最大值，光标2定位到B通道的最大值。
查看光标定位到的数据，如图4所示，此时输出电流滞后于输入电压9.0150ns，此时信号周期为1000ns，因此输出电流的相位滞后了3.2454°。
调整输入电压频率，设置为10MHz，打开图示仪，示波器波形如图5所示。查看光标定位到的数据，如图6所示，此时输出电流滞后于输入电压6.2092ns，此时信号周期为100ns，因此输出电流的相位滞后了22.3531°。
图2所示的传统压控恒流源，电路中R1和R2构成串联电流负反馈，记三极管Q1集电极的电流为输出电流Io，输出电流单独作用于R1的电压为负反馈电压Ufn，求出电路的负反馈系数Fn为：
由深度负反馈理论得到电路的跨导增益Aiuf为：
输入电压频率设置为5MHz，利用软件仿真，打开图示仪，示波器波形如图7所示，A通道为输入电压波形，B通道为输出电流波形。
查看光标定位到的数据，如图8所示，此时输出电流滞后于输入电压2.0145ns，此时信号周期为200ns，因此输出电流的相位滞后了3.6261°。
调整输入电压频率，设置为10MHz，打开图示仪，示波器波形如图9所示。查看光标定位到的数据，如图10所示，此时输出电流滞后于输入电压3.1942ns，此时信号周期为100ns，因此输出电流的相位滞后了11.4991°。
可知，通过对图1和图2所示的传统的压控恒流源分析可知，传统的压控恒流源输出电流信号会随着输入电压信号频率的升高而发生相位滞后，输入电压频率越高，输出电流滞后于输入电压的相位越大。
本实施例为了实现输出电流与输入电压同频同相，消除输出电流滞后于输入电压的相位差的问题，提出了驱动可调谐激光器的自动锁相恒流源电路，如图11所示，包括依次连接的相位滞后电路、锁相环、加法器和压控恒流源，压控恒流 源用于与负载连接的输出端还与高通滤波器连接，高通滤波器与锁相环连接；
相位滞后电路能够将输入电压进行相位滞后后，输入锁相环中，锁相环将相位滞后电压和反馈电压做乘法，获得叠加电压，并对叠加电压进行滤波和振荡后输入加法器中，加法器将振荡电压和直流偏置电压相加后输入压控恒流源中，压控恒流源的输出电压进入高通滤波器进行高通滤波后向锁相环中输入反馈电压。
还包括主控模块和电压输出模块，主控模块与电压输出模块连接，电压输出模块与相位滞后电路连接，为相位滞后电路提供输入电压。
其中，锁相环包括依次连接的鉴相器、环路滤波器和压控振荡器；相位滞后电路、高通滤波器均与鉴相器连接。
鉴相器包括依次连接的乘法器和低通滤波器；相位滞后电路、高通滤波器均与乘法器连接。
优选的，低通滤波器采用程控低通滤波器，程控低通滤波器与主控模块连接。
相位滞后电路采用90°相位滞后电路，90°相位滞后电路能够将输入电压相位滞后90°，由两路RC低通滤波器串联而成。
电压输出模块采用电压输出型DAC。
加法器将振荡电压和直流偏置电压相加后，能够将电压信号抬升至横轴上方。
压控恒流源输出电流与高通滤波器输入锁相环的反馈电压同频同相；高通滤波器输入锁相环的反馈电压与输入电压同频同相。
对本实施例公开的驱动可调谐激光器的自动锁相恒流源电路进行详细说明。
主控模块首先发出数字信号至电压输出型DAC，DAC对应输出高频的模拟电压信号为90°相位滞后电路的输入电压，具体为：
其中，Ui为输入电压信号，即电压输出型DAC输出的电压信号；ωi为输入电 压信号Ui的频率，t为时间。
首先经过90°相位滞后电路，使相位滞后90°得到表示为：
其中，是90°相位滞后电路的输出电压信号。
经过锁相环中的鉴相器，首先与反馈电压做乘法，受到鉴相器的鉴相特性影响，的相位会超前的相位90°，表示为：
其中，Uf为反馈电压信号，即高通滤波器输出的电压信号；ωo为输出电压信号的频率。
得到二者的差频信号以及和频信号叠加的信号表示为：
再经过程控低通滤波器，滤除中的和频信号，留下差频信号，即得表示为：
偏差在范围内，与之间的相位偏差和呈正相关。因为的频率不同，低通滤波器的带宽也需要做出相应的变化，所以低通滤波器的带宽需要程控，选用程控低通滤波器，并且将程控低通滤波器和主控模块连接，通过主控模块控制程控低通滤波器的截止频率。经过环路滤波器，滤除其中的高频成分，得到压控振荡器可使用的小纹波直流信号由于锁相环负反馈的调控，经过反馈迭代，当相位偏差趋近于0时，趋近于0，环路滤波器的输出电压趋近于0，得到的反馈电压与输入锁相环的相位滞后后电压同频。又有的相位超前于的相位90°，则和同频同相。
压控振荡器根据振荡输出频率与呈正相关的电压信号经过加法 器，加法器中还通入了直流偏置Uref，加法器在上加入直流偏置Uref，把电压信号抬升到横轴上方，得到确保流经负载的电流方向恒定。经过压控恒流源，得到输出电流负载RL两端的电压即输出电压由于负载是纯阻性负载，因此输出电流和输出电压同频同相。经过高通滤波器，滤除其中的直流分量，得到交流信号反馈给锁相环，因为高通滤波器的截止频率远低于输出电压的频率，所以不会改变输出电压的相位，因此输出电流和反馈电压同频同相，从而最终实现了输出电流和输入相位滞后电路的输入电压同频同相。
使用仿真软件，搭建本实施例公开的自动锁相恒流源电路的仿真电路，仿真电路图如图12所示，主控模块和电压输出型DAC用软件自带的信号源代替，90°相位滞后电路使用两路RC低通滤波器串联，由R1、C1、R2、C2组成，调配RC的数值使得截止频率等于输入信号频率，一路RC低通滤波器可使输入信号相位滞后45°，两路即可滞后90°。锁相环使用软件自带的集成锁相环PLL_VIRTUAL。加法器由运算放大器U1以及外围电阻组成。压控恒流源使用图1给出的电路，由运算放大器U2、三极管Q1以及外围电容电阻组成。高通滤波器由C4和R14组成。由于鉴相器的输入是两信号的相位差，信号的幅值只影响鉴相器输出信号的比例系数，因此反馈电压信号只需和压控恒流源的输出电压信号保持同频同相即可，的幅值不必和完全相同。故从方便电路设计的角度，高通滤波器从R12上端引出。
输入电压频率设置为10MHz，观察示波器XSC2，显示的波形即为经过锁相环的反馈调节后，可以观察到逐渐趋近于0，如图13所示。观察示波器XSC1，示波器A通道为电压输出型DAC输出电压的波形，B通道为输出电流的波形。当趋近于0时，观察到输入电压和输出电流的波形如图14所示。
查看光标定位到的数据，如图15所示，此时输入电压于198.8270μs取到最大值，同样输出电流也于198.8270μs取到最大值。由于示波器的采样周期是0.1ns， 因此输入电压与输出电流之间的时间差小于0.1ns，因此相位差小于0.36°。
采用图2所示的压控恒流源搭建本实施例公开的自动锁相恒流源电路的仿真电路图，如图16所示，输入电压频率设置为10MHz，观察示波器XSC2，显示的波形即为经过锁相环的反馈调节后，可以观察到逐渐趋近于0，如图17所示。
观察示波器XSC1，示波器A通道为输入电压的波形，B通道为输出电流的波形。当趋近于0时，观察到输入电压和输出电流的波形如图18所示。查看光标定位到的数据，如图19所示，此时输入电压于218.5157μs取到最大值，同样输出电流也于218.5157μs取到最大值。由于示波器的采样周期是0.1ns，因此输入电压与输出电流之间的时间差小于0.1ns，因此相位差小于0.36°。
通过搭建两种仿真电路，进行仿真分析，验证了本实施例公开的驱动可调谐激光器的自动锁相恒流源电路，利用锁相环，实现了输出电流自动锁定输入电压保证输出电流与输入电压同频同相，消除了输出电流滞后于输入电压的相位差，极大地提升了高速光纤光栅解调仪的解调速度。解决了传统恒流源驱动可调谐激光器时，解调速度慢的问题。
由于本实施例公开的恒流源电路消除了输出电流滞后于输入电压的相位差，当输入高频电压信号时，能够通过同步测得恒流源电路的输出电流来判断是否输出了期望电流，有效地提高了高速光纤光栅解调仪的解调精度。解决了传统恒流源驱动可调谐激光器时，解调精度低的问题。
锁相环中鉴相器的低通滤波器使用程控低通滤波器，且程控低通滤波器与主控模块连接，从而针对不同的输入电压信号设置不同的截止频率，提高适应性。
实施例2
在该实施例中，提出了驱动可调谐激光器的自动锁相恒流源电路的控制方法， 包括：
向相位滞后电路中输入输入电压；
相位滞后电路将输入电压相位滞后后输入锁相环中；
锁相环将相位滞后电压和反馈电压做乘法，获得叠加电压，并对叠加电压进行滤波和振荡后输入加法器中；
加法器将振荡电压和直流偏置电压相加后输入压控恒流源中；
压控恒流源的输出电压进入高通滤波器进行滤波后，向锁相环中输入反馈电压。
最后应当说明的是：以上实施例仅用以说明本发明的技术方案而非对其限制，尽管参照上述实施例对本发明进行了详细的说明，所属领域的普通技术人员应当理解：依然可以对本发明的具体实施方式进行修改或者等同替换，而未脱离本发明精神和范围的任何修改或者等同替换，其均应涵盖在本发明的权利要求保护范围之内。

Claims (10)

  1. 驱动可调谐激光器的自动锁相恒流源电路，其特征在于，包括依次连接的相位滞后电路、锁相环、加法器和压控恒流源，压控恒流源的输出端与高通滤波器连接，高通滤波器与锁相环连接；
    将输入电压输入相位滞后电路中，相位滞后电路能够将输入电压进行相位滞后后，输入锁相环中，锁相环将相位滞后电压和反馈电压做乘法，获得叠加电压，并对叠加电压进行滤波和振荡后输入加法器中，加法器将振荡电压和直流偏置电压相加后输入压控恒流源中，压控恒流源的输出电压进入高通滤波器进行高通滤波后向锁相环中输入反馈电压。
  2. 如权利要求1所述的驱动可调谐激光器的自动锁相恒流源电路，其特征在于，还包括电压输出模块，电压输出模块连接，电压输出模块与相位滞后电路连接，为相位滞后电路提供输入电压。
  3. 如权利要求2所述的驱动可调谐激光器的自动锁相恒流源电路，其特征在于，还包括主控模块，主控模块与电压输出模块连接。
  4. 如权利要求3所述的驱动可调谐激光器的自动锁相恒流源电路，其特征在于，锁相环包括依次连接的鉴相器、环路滤波器和压控振荡器；相位滞后电路、高通滤波器均与鉴相器连接。
  5. 如权利要求4所述的驱动可调谐激光器的自动锁相恒流源电路，其特征在于，鉴相器包括依次连接的乘法器和低通滤波器；相位滞后电路、高通滤波器均与乘法器连接。
  6. 如权利要求5所述的驱动可调谐激光器的自动锁相恒流源电路，其特征在于，低通滤波器采用程控低通滤波器，程控低通滤波器与主控模块连接。
  7. 如权利要求1所述的驱动可调谐激光器的自动锁相恒流源电路，其特征在于，相位滞后电路采用90°相位滞后电路，90°相位滞后电路能够将输入电压相 位滞后90°。
  8. 如权利要求1所述的驱动可调谐激光器的自动锁相恒流源电路，其特征在于，加法器将振荡电压和输入的直流偏置电压相加后，将电压信号抬升至横轴上方。
  9. 如权利要求1所述的驱动可调谐激光器的自动锁相恒流源电路，其特征在于，压控恒流源输出电流与高通滤波器输入锁相环的反馈电压同频同相；高通滤波器输入锁相环的反馈电压与输入电压同频同相。
  10. 驱动可调谐激光器的自动锁相恒流源电路的控制方法，其特征在于，包括：
    向相位滞后电路中输入输入电压；
    相位滞后电路将输入电压相位滞后后输入锁相环中；
    锁相环将相位滞后电压和反馈电压做乘法，获得叠加电压，并对叠加电压进行滤波和振荡后输入加法器中；
    加法器将振荡电压和直流偏置电压相加后输入压控恒流源中；
    压控恒流源的输出电压进入高通滤波器进行滤波后，向锁相环中输入反馈电压。
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