WO2023184575A1 - 用于锁相环的环路滤波器以及锁相环 - Google Patents

用于锁相环的环路滤波器以及锁相环 Download PDF

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WO2023184575A1
WO2023184575A1 PCT/CN2022/086574 CN2022086574W WO2023184575A1 WO 2023184575 A1 WO2023184575 A1 WO 2023184575A1 CN 2022086574 W CN2022086574 W CN 2022086574W WO 2023184575 A1 WO2023184575 A1 WO 2023184575A1
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loop filter
capacitor
resistor
loop
phase
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PCT/CN2022/086574
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English (en)
French (fr)
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张宁
李闻界
管逸
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上海韬润半导体有限公司
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Publication of WO2023184575A1 publication Critical patent/WO2023184575A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop

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  • the invention relates to the field of electronic circuits, and in particular to a loop filter for a phase-locked loop and a phase-locked loop.
  • Phase Locked Loop is a typical feedback control circuit that uses an externally input reference frequency signal to control the frequency and phase of the oscillation signal inside the loop to achieve automatic tracking of the output signal frequency to the input signal frequency.
  • Charge pump phase-locked loops are widely used in electronic circuits.
  • the charge pump phase-locked loop in the existing technology can include a phase frequency detector (Phase Frequency Detector, PFD), a charge pump (Charge Pump, CP), a ring Loop Filter (LF), Voltage ontrolled Oscillator (VCO) and frequency divider (Divider), and form a loop.
  • PFD phase frequency detector
  • CP Charge Pump
  • CP Charge Pump
  • LF ring Loop Filter
  • VCO Voltage ontrolled Oscillator
  • Divider frequency divider
  • the input end of the frequency-phase detector inputs a reference frequency signal, and the frequency divider is suitable for dividing the phase-locked signal. And transmit the obtained feedback signal to the frequency and phase detector.
  • the phase frequency detector (PFD) and charge pump (CP) convert the phase difference between the reference clock and the feedback clock into a periodic current, which is then converted into a control voltage through the loop filter to regulate the oscillation of the voltage-controlled oscillator. frequency, which in turn changes phase.
  • the loop filter is arranged between the charge pump and the voltage controlled oscillator, and is suitable for converting the output current of the charge pump into the tuning voltage of the voltage controlled oscillator, thereby controlling the output frequency of the voltage controlled oscillator.
  • the loop filter needs to provide a lower zero point to achieve loop stability of the phase locked loop.
  • a smaller resistor and a larger capacitor are usually used to achieve the zero point.
  • larger capacitors increase chip area and cost, and using larger resistors so that the capacitors can be smaller increases the noise introduced by the resistors.
  • the present invention aims to provide a phase-locked loop filter capable of reducing resistance noise while reducing capacitance.
  • a loop filter for a phase-locked loop includes a first resistor, a first capacitor and a second capacitor, wherein the first resistor and the first capacitor are connected to the input end and the ground end of the loop filter. , the second capacitor is connected between the output terminal of the loop filter and the ground terminal.
  • the loop filter also includes a bridge circuit, which is connected between the input end and the output end of the loop filter and is used to divide the input signal of the loop filter.
  • the bridge circuit is used to divide the input signal of the loop filter when the input of the loop filter is the first frequency, and to divide the input signal of the loop filter when the input of the loop filter is the second frequency.
  • a DC bias is provided from the input to the output, wherein the second frequency is lower than the first frequency.
  • the bridge circuit includes a second resistor and a third capacitor, wherein: a first end of the second resistor is connected to the input end of the loop filter, and a second end of the second resistor is connected to the output end of the loop filter. ; The first terminal of the third capacitor is connected to the input terminal of the loop filter, and the second terminal of the third capacitor is connected to the output terminal of the loop filter.
  • the second resistor adopts any one of a passive resistor, an active MOS tube resistor and the equivalent resistance of a level converter;
  • the third capacitor adopts any one of a passive capacitor and an active MOS tube capacitor. A sort of.
  • the resistance value of the second resistor is configured such that the noise bandwidth of the second resistor is lower than the loop bandwidth of the loop filter.
  • the resistance value of the second resistor is greater than the resistance value of the first resistor.
  • the capacitance values of the second capacitor and the third capacitor are both smaller than the capacitance value of the first capacitor.
  • the resistance value of the second resistor ranges from 1 to 500 k ⁇ .
  • the capacitance value of the third capacitor ranges from 5-200pF.
  • phase-locked loop which includes any one of the aforementioned loop filters.
  • the loop filter for a phase-locked loop of the present invention by adding a bridge circuit based on the second-order loop filter of the prior art, the resistance of the loop filter has room for further increase, and The noise of the resistor can be reduced, so that the original capacitance of the loop filter can be reduced. Therefore, the loop filter of the present invention can reduce the chip area and simultaneously reduce the resistance noise of the loop.
  • FIG. 1 shows a schematic diagram of the circuit structure of a second-order loop filter 100 in the prior art
  • Figure 2 shows a schematic diagram of the circuit structure of a loop filter 200 according to some embodiments of the present invention
  • 3A-3B show a schematic diagram of the circuit structure of the loop filter 300 according to other embodiments of the present invention.
  • Figure 4 shows a noise spectrum comparison of a phase-locked loop including a loop filter according to an embodiment of the present invention and a phase-locked loop including an existing second-order loop filter;
  • Figure 5 shows a comparison of the transfer functions of the two phase locked loops shown in Figure 4.
  • Words such as “having” and “comprising” mean that in addition to having units (modules) and steps that are directly and explicitly stated in the description and claims, the technical solution of the present invention does not exclude having units (modules) and steps that are not directly or explicitly stated. The situation of other units (modules) and steps expressed.
  • Figure 1 shows a schematic circuit structure diagram of a conventional second-order loop filter 100.
  • the existing second-order loop filter 100 can be composed of a first resistor 110, a first capacitor 120, and a second capacitor 130 (assuming the resistance/capacitance values are R 1 and C respectively 1 , C 2 ), wherein the first resistor 110 and the first capacitor 120 are connected between the input terminal and the ground terminal of the loop filter 100, and the second capacitor 130 is connected between the output terminal and the ground terminal of the loop filter 100. between.
  • the loop filter receives the input signal I in and outputs the signal V out .
  • the transimpedance transfer function Z f of the second-order loop filter can generally be expressed as:
  • the loop filter has a low-pass filtering function when the input is high frequency.
  • the value R 1 of the first resistor 110 is generally small, which makes the corresponding capacitance value C 1 of the first capacitor 120 often have a smaller value. high. Therefore, the first capacitor 120 will occupy a larger chip area.
  • the resistance value of the first resistor of the loop filter is set to 1k ⁇ , in order to achieve a lower zero point of about 160kHz, the capacitance value of the first capacitor of the loop filter will be as high as 1nF, which greatly increases chip area and design cost.
  • FIG. 2 is a schematic circuit structure diagram of a loop filter 200 for a phase-locked loop according to some embodiments of the present invention.
  • the first resistor 210, the first capacitor 220, and the second capacitor 230 in Figure 2 respectively correspond to the first resistor 110, the first capacitor 120, and the second capacitor 130 described above with respect to Figure 1 .
  • the loop filter 200 shown in FIG. 2 adds a bridge circuit 240 .
  • the bridge circuit 240 is connected between the input terminal and the output terminal of the loop filter 200 and is configured to divide the input signal input to the loop filter circuit in FIG. 2 .
  • a device for signal voltage division may be arranged in the bridge circuit 240, which device can be approximately the same as the original third voltage under appropriate conditions (eg, when the frequency of the input signal is higher).
  • Two capacitors 230 are connected in series to divide the input signal.
  • the bridge circuit 240 is equivalent to proportionally reducing the equivalent transresistance between the input and the output (from the first resistor 210 to the first resistor 210 times the (the voltage division coefficient of the bridge circuit 240 and the second capacitor 230), the resistance value of the first resistor 210 can be increased by a certain multiple.
  • the series connected bridge circuit 240 causes the square value of the noise transfer function of the first resistor 210 to also introduce a fraction corresponding to the voltage division coefficient.
  • Square the square of the fraction makes the square of the voltage noise contributed by the first resistor 210 seen from the output end not increase as the resistance value of the first resistor 210 increases, but can attenuate a certain amount due to the introduction of the fraction. Voltage noise squared.
  • the bridge circuit 240 may also be configured to divide the input signal from the loop filter 200 when the input of the loop filter 200 is the first frequency, and when the input of the loop filter 200 is the second frequency.
  • the circuit of loop filter 200 is DC biased and the second frequency is lower than the first frequency).
  • the bridge circuit can be further designed to produce a voltage dividing effect when the input frequency is high, and to pass the low-frequency input when the input frequency is low, so that the loop filter circuit exhibits low-pass filtering characteristics.
  • the present invention does not limit the range of the first frequency and the second frequency, and a reasonable range can be set according to the specific practical application of the loop filter or phase-locked loop.
  • the bridge circuit may be composed of a capacitive device and a resistive device connected in parallel.
  • FIG. 3A shows a schematic circuit structure diagram of a loop filter 300 according to some embodiments, which uses parallel passive resistors and passive capacitors to form a bridge circuit.
  • the first resistor 310, the first capacitor 320, and the second capacitor 330 in FIG. 3A respectively correspond to the first resistor 110, the first capacitor 120, and the second capacitor 130 described above with respect to FIG. 1 .
  • the bridge circuit is composed of a second resistor 340 and a third capacitor 350 connected in parallel (assume the resistance value/capacitance value is R 2 and C 3 respectively).
  • the two ends of the second resistor 340 and the third capacitor 350 are respectively are respectively connected to the input terminal and the output terminal of the loop filter 300.
  • the transimpedance transfer function Z f of the loop filter 300 can be expressed as:
  • the resistance value R 2 of the second resistor 340 is greater than the resistance value R 1 of the first resistor 310 .
  • the larger resistance value R 2 makes the circuit through the second resistor 340 more similar to an open circuit when the input signal frequency becomes higher, which makes the third capacitor 350 and the second capacitor 330 more similar to a series connection, which is more beneficial to the third capacitor 350 and the second capacitor 330 .
  • Capacitor 350 plays the role of voltage divider.
  • the capacitance value R 2 of the second resistor 340 may range from 1 to 500 k ⁇ .
  • the capacitance value C 2 of the second capacitor 330 and the capacitance value C 3 of the third capacitor 350 are both smaller than the capacitance value C 1 of the first capacitor 320 .
  • the larger capacitance value C 1 and the smaller capacitance value C 3 make the first capacitor 320 more similar to a short circuit when the input signal frequency becomes higher, which also makes the third capacitor 350 and the second capacitor 330 more similar to a series connection. , which is more conducive for the third capacitor 350 to play a voltage dividing role.
  • the capacitance value of the third capacitor 350 may range from 5 to 200 pF.
  • the newly introduced zero point f z2 due to the addition of the second resistor 340 and the third capacitor 350 is approximately equal to the newly introduced pole f s2 , which approximately forms a zero-pole pair.
  • Their effects on the gain can almost cancel each other out, and are basically not the same. It will have an impact on the phase margin of the loop.
  • the first capacitor 310 can be equivalent due to the larger capacitance value.
  • the second resistor 340 may be equivalent to an open circuit due to its large resistance value.
  • the circuit structure of the loop filter 300 may be equivalent to that shown in FIG. 3B . It can be seen from Figure 3B that the circuit structure of the loop filter 300 at this time is equivalent to a series connection of the second capacitor 330 and the third capacitor 350, so the third capacitor 350 can divide the voltage of the series circuit.
  • the first resistor 310 of the loop filter 300 can also be increased by a corresponding multiple relative to the first resistor of the existing second-order loop filter, while the transimpedance to the output end remains unchanged.
  • the capacitance value of the first capacitor 320 can be reduced in a proportion corresponding to the increase in the resistance value of the first resistor 310 to maintain the zero and pole points of the original loop. Basically unchanged.
  • the increase of the first resistor 310 will not cause an increase in the square of its noise voltage, but will reduce the noise transmission to a certain extent. Specifically, due to the presence of capacitive voltage division, the square of the output noise voltage of the resistor is also multiplied by the square of a fraction corresponding to this ratio.
  • the resistor noise of R1 can be expressed by the square of its resistor noise as follows:
  • the resistance value R 2 of the second resistor 340 may be preferably configured such that the noise bandwidth of the second resistor 340 is lower than the loop bandwidth of the loop filter 300 . Since the introduced second resistor 340 will also contribute some resistance noise to the loop filter, if a larger second resistor 340 is set, in addition to making it close to an open circuit when a high-frequency input signal is input, its noise bandwidth will also be average. is lower (or even much lower) than the loop bandwidth of the loop filter, so most of the resistor noise caused by the second resistor 340 will be filtered out in the loop filter circuit.
  • the parallel capacitive devices and resistive devices used to form the bridge circuit of the present invention are not limited to passive devices, but may also be composed of active devices connected in parallel.
  • the resistive device can also be an active MOS tube resistor
  • the third capacitor can also be an active MOS tube capacitor.
  • the resistor device can be replaced with a level converter, and the equivalent resistance value of the level converter is equal to the original resistor device. This can provide an equivalent resistance while adding a level conversion function.
  • the capacitive device and the resistive device are in the form of active devices or passive devices, they can be equivalent to the form of the loop filter 300 described above with respect to FIG. 3, for example, active MOS
  • the equivalent resistance value of the tube resistor or level converter is R 2
  • the equivalent capacitance value of the active MOS tube capacitor is C 3 .
  • FIG 4 shows an output noise spectrum curve of a phase-locked loop including a loop filter according to an embodiment of the present invention and an output noise spectrum curve of a phase-locked loop including an existing second-order loop filter.
  • This noise spectrum originates from the noise of all components in the phase-locked loop (such as charge pumps, loop filters, voltage-controlled oscillators, etc.).
  • the abscissa is the frequency of nonlinearity
  • the ordinate is the square root of the noise voltage
  • the noise spectrum curve of line b almost coincides with line a when the input frequency is low, and then line b rises slightly in the band. For example, it rises at the M5 and M6 points at the input frequency of about 60kHz. About 2dB. As the input frequency continues to increase, line b crosses line a at point M4 where the input frequency is approximately 166kHz. Then, when the input frequency is greater than 166kHz, the noise spectrum curve of line b is always lower than line a, and is always about 2dB lower than the curve a in most frequency ranges greater than 166kHz.
  • the loop filter of the present invention reduces the overall noise spectrum of the phase-locked loop by approximately 2.04dB. Therefore, the embodiment of the loop filter of the present invention shown in Figure 5 reduces the noise voltage over a substantial portion of the bandwidth (eg, a bandwidth greater than 166 kHz).
  • FIG. 5 shows a comparison of phase-locked loop gain transfer functions corresponding to two types of loop filters respectively including two types of loop filters according to the embodiment of FIG. 4 .
  • the loop gain transfer function curves of the two loop filters are relatively similar, and the phase margins are relatively close.
  • the loop bandwidths of the two loop filters basically overlap in the higher frequency range (for example, when the abscissa in Figure 5 is 599.415kHz, the loop gains of line a and line b are already very close, and when Almost equal in most frequency ranges greater than 599.415kHz), and the phase margin is between 60° and 70°, indicating that the loop filter of the present invention has a certain stability as the existing second-order loop filter.
  • the present invention also includes a phase locked loop including any of the loop filters of the present invention as previously described.
  • the loop filter design of the present invention further reduces the capacitance value C 1 of the first capacitor while reducing resistor noise by introducing a bridge circuit, and the loop bandwidth and phase margin remain basically unchanged.
  • the reduction in capacitance value allows for smaller area capacitor designs, further reducing chip area.

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Abstract

一种用于锁相环的环路滤波器(300)以及锁相环，该环路滤波器（300）包括第一电阻（310）、第一电容（320）和第二电容（330）。第一电阻（310）和第一电容（320）连接在环路滤波器（300）的输入端和接地端之间，第二电容（330）连接在环路滤波器（300）的输出端和接地端之间。环路滤波器（300）还包括桥接电路，桥接电路连接在环路滤波器（300）的输入端和输出端之间，用于对环路滤波器（300）的输入信号进行分压。

Description

用于锁相环的环路滤波器以及锁相环 技术领域
本发明涉及电子电路领域，特别是涉及一种用于锁相环的环路滤波器以及锁相环。
背景技术
锁相环(Phase Locked Loop，PLL)是一种典型的反馈控制电路，利用外部输入的参考频率信号控制环路内部振荡信号的频率和相位，实现输出信号频率对输入信号频率的自动跟踪。电子电路中广泛采用电荷泵锁相环，现有技术中的电荷泵锁相环可以包括顺次串联的鉴频鉴相器(Phase Frequency Detector，PFD)、电荷泵(Charge Pump，CP)、环路滤波器(Loop Filter，LF)、压控振荡器(Voltage ontrolled Oscillator，VCO)和分频器(Divider)，并形成环路。其中，压控振荡器的输出端作为电荷泵锁相环的输出端并输出锁相信号，鉴频鉴相器的输入端输入有参考频率信号，分频器适于对锁相信号进行分频并将得到的反馈信号传输至鉴频鉴相器。鉴频鉴相器(PFD)和电荷泵(CP)会将参考时钟和反馈时钟之间的相位差异转化为周期性电流，然后经过环路滤波器转为控制电压，调节压控振荡器的振荡频率，继而改变相位。环路滤波器设置于电荷泵和压控振荡器之间，适于将电荷泵的输出电流转换为压控振荡器的调谐电压，从而控制压控振荡器的输出频率。
环路滤波器需要提供一个较低的零点，以实现锁相环的环路稳定。现有技术中，为了降低环路电阻引入的噪声，通常实现该零点所使用的电阻较小而电容较大。然而，较大的电容增加了芯片面积和成本，而若使用更大的电阻以使电容可以更小，则又会增大电阻引入的噪声。
发明内容
鉴于上述问题，本发明旨在提供一种能够在减小电容的同时降低电阻噪声的锁相环环路滤波器。
本发明的一方面的用于锁相环的环路滤波器，包括第一电阻、第一电容和第二电容，其中第一电阻和第一电容连接在环路滤波器的输入端和接地端之间，第二电容连接在环路滤波器的输出端和接地端之间。环路滤波器还包括桥接电路，桥接电路连接在环路滤波器的输入端和输出端之间，用于对环路滤波器的输入信号进行分压。
可选地，桥接电路用于在环路滤波器的输入为第一频率时对环路滤波器的输入信号进行分压，在环路滤波器的输入为第二频率时为环路滤波器的输入端到输出端提供直流偏置，其中，第二频率低于第一频率。
可选地，桥接电路包括第二电阻和第三电容，其中：第二电阻的第一端连接到环路滤波器的输入端，第二电阻的第二端连接到环路滤波器的输出端；第三电容的第一端连接到环路滤波器的输入端，第三电容的第二端连接到环路滤波器的输出端。
可选地，第二电阻采用无源电阻器、有源MOS管电阻器和电平转换器的等效电阻中的任一种；第三电容采用无源电容器和有源MOS管电容器中的任一种。
可选地，第二电阻的电阻值配置成使得第二电阻的噪声带宽低于环路滤波器的环路带宽。
可选地，第二电阻的电阻值大于第一电阻的电阻值。
可选地，第二电容和第三电容的电容值均小于第一电容的电容值。
可选地，第二电阻的电阻值范围为1-500kΩ。
可选地，第三电容的电容值范围为5-200pF。
本发明的另一方面的锁相环，其包含如前述环路滤波器中的任一种环路滤波器。
如上，根据本发明的用于锁相环的环路滤波器，通过在现有技术的二阶环路滤波器基础上增加桥接电路，使得环路滤波器的电阻具有进一步增大的空间，且能够降低该电阻的噪声，从而使得环路滤波器原有电容能具有减小的空间。由此，本发明的环路滤波器能够实现芯片面积的减小，同时降低环路的电阻噪声。
附图说明
图1示出了现有技术的二阶环路滤波器100的电路结构的示意图；
图2示出了根据本发明的某些实施例的环路滤波器200的电路结构的示意图；
图3A-3B示出了根据本发明的另一些实施例的环路滤波器300的电路结构的示意图；
图4示出了包含根据本发明的某一实施例的环路滤波器的锁相环与包含现有二阶环路滤波器的锁相环的噪声频谱对比；
图5示出了图4中所示的两种锁相环的传递函数对比。
具体实施方式
下面介绍的是本发明的多个实施例中的一些，旨在提供对本发明的基本了解。并不旨在确认本发明的关键或决定性的要素或限定所要保护的范围。
出于简洁和说明性目的，本文主要参考其示范实施例来描述本发明的原理。但是，本领域技术人员将容易地认识到，相同的原理可等效地应用于所有类型的环路滤波器电路和锁相环并且可以在其中实施这些相同的原理，以及任何此类变化不背离本专利申请的真实精神和范围。
而且，在下文描述中，参考了附图，这些附图图示特定的示范实施例。在不背离本发明的精神和范围的前提下可以对这些实施例进行电、机械、逻辑和结构上的更改。此外，虽然本发明的特征是结合若干实施/实施例的仅其中之一来公开的，但是如针对任何给定或可识别的功能可能是期望和/或有利的，可以将此特征与其他实施/实施例的一个或多个其他特征进行组合。因此，下文描述不应视为在限制意义上的，并且本发明的范围由所附权利要求及其等效物来定义。
诸如“具备”和“包括”之类的用语表示除了具有在说明书和权利要求书中有直接和明确表述的单元(模块)和步骤以外，本发明的技术方案也不排除具有未被直接或明确表述的其它单元(模块)和步骤的情形。
图1示出了现有的二阶环路滤波器100的电路结构示意图。
具体而言，如图1所示，现有的二阶环路滤波器100可以由第一电阻110和第一电容120、第二电容130组成(设电阻值/电容值分别为R 1、C 1、C 2)，其中第一电阻110和第一电容120连接在环路滤波器100的输入端和接地端之间，第二电容130连接在环路滤波器100的输出端和接地端之间。环路滤波器接收输入信号I in并输出信号V out。通过推导，该二阶环路滤波器的跨阻传递函数Z f一般可以表示为：
Figure PCTCN2022086574-appb-000001
其中，s＝jω，ω为输入信号频率。
令式(1)的分母为0，则第一电阻110和第一电容120、第二电容130适于产生2个极点，其对应的频率f为：
f＝0
Figure PCTCN2022086574-appb-000002
以及，令式(1)的分子为0，则产生1个零点，其对应的频率f为：
Figure PCTCN2022086574-appb-000003
为了环路的稳定性，通常需要较低的零点，以使得环路滤波器在输入为高频时具有低通滤波的功能。其中，由于第一电容120对应的是一个低频零点，为了降低电阻噪声，第一电阻110的取值R 1一般较小，这使得对应的第一电容120的电容值C 1的取值往往较高。因此，第一电容120会占用较大的芯片面积。举例来说，在一些高性能应用中，若设置环路滤波器的第一电阻的电阻值为1kΩ，则为了实现约160kHz的较低零点，环路滤波器的第一电容的电容值会高达1nF，这极大地增加了芯片面积和设计成本。
图2是根据本发明的某些实施例的用于锁相环的环路滤波器200的电路结构示意图。其中，图2中的第一电阻210和第一电容220、第二电容230分别对应于上述关于图1描述的第一电阻110和第一电容120、第二电容130。相比于图1的现有二阶环路滤波器，图2中示出的环路滤波器200增加了桥接电路240。桥接电路240连接在环路滤波器200的输入端和输出端之间，并配置成对输入图2中的环路滤波器电路的输入信号进行分压。
具体而言，桥接电路240中可以布置用于信号分压的器件(例如，无源电容器)，该器件能在适当条件下(例如，输入信号的频率较高时)近似成与原有的第二电容230串联，从而能对输入信号进行分压。相比于现有二阶环路滤波器电路，该桥接电路240相当于成比例地减小了输入和输出之间的等效跨阻(由第一电阻210减小为第一电阻210乘以桥接电路240和第二电容230的分压系数)，第一电阻210得以能够再增加一定的倍数的电阻值。而由于桥接电路240的引入，虽然允许第一电阻210增大某个比例，但串联的桥接电路240使得第一电阻210的噪声传递函数平方值也要引入一个 与该分压系数对应的分数的平方，该分数的平方使从输出端看到的由第一电阻210贡献的电压噪声平方不会随第一电阻210的电阻值增大而增大，反而由于该分数的引入能够衰减一定量的电压噪声平方。
优选地，桥接电路240还可以配置成在环路滤波器200的输入为第一频率时对从环路滤波器200的输入信号进行分压，在环路滤波器200的输入为第二频率时对环路滤波器200的电路进行直流偏置，并且第二频率低于所述第一频率)。具体而言，桥接电路可以进一步设计为在输入频率较高时产生分压作用，而在输入频率较低时又能使该低频输入通过，使得该环路滤波器电路发挥低通滤波的特性。本发明对第一频率和第二频率的范围并不做限定，其能够根据环路滤波器或锁相环的具体实践应用而设置合理范围。
在一些实施例中，桥接电路可以由并联的电容器件和电阻器件构成。例如，图3A示出了根据一些实施例的环路滤波器300的电路结构示意图，其使用并联的无源电阻器和无源电容器组成桥接电路。其中，图3A中的第一电阻310和第一电容320、第二电容330分别对应于上述关于图1描述的第一电阻110和第一电容120、第二电容130。如图3A所示，桥接电路由并联的第二电阻340和第三电容350组成(设电阻值/电容值分别为R 2和C 3)，第二电阻340和第三电容350各自的两端都分别接入到环路滤波器300的输入端和输出端。经推导，该环路滤波器300的跨阻传递函数Z f可以表示为：
Figure PCTCN2022086574-appb-000004
其中，s＝jω，ω为输入信号频率。
在一些实施例中，第二电阻340的电阻值R 2大于第一电阻310的电阻值R 1。较大的电阻值R 2使得在输入信号频率变高时，通过第二电阻340的电路更近似于断路，这使得第三电容350与第二电 容330更近似于串联连接，从而更利于第三电容350发挥分压作用。优选地，第二电阻340的电容值R 2范围可以是1-500kΩ。
在一些实施例中，第二电容330的电容值C 2和所述第三电容350的电容值C 3均小于第一电容320的电容值C 1。较大的电容值C 1和较小的电容值C 3使得在输入信号频率变高时，第一电容320更近似于短路，这同样使得第三电容350与第二电容330更近似于串联连接，从而更利于第三电容350发挥分压作用。优选地，第三电容350的电容值范围可以是5-200pF。
令式(2)中分子为0，由于C 1的电容值较大，R 2的电阻值较大，则环路滤波器300适于产生2个零点，其对应的频率f为：
Figure PCTCN2022086574-appb-000005
Figure PCTCN2022086574-appb-000006
以及，令式(2)中分母为0，则产生3个极点，其对应的频率f为：
f s1＝0
Figure PCTCN2022086574-appb-000007
Figure PCTCN2022086574-appb-000008
其中，由新增第二电阻340和第三电容350而新引入的零点f z2约等于新引入的极点f s2，近似于组成一个零点极点对，其对增益的影响几乎可以相互抵消，基本不会对环路的相位裕度产生影响。
当在环路滤波器300的输入端的输入信号频率升高时，若设置较大的第三电容350电容值和较大的第二电阻340电阻值，第一电容310由于电容值较大可相当于短路，第二电阻340由于电阻值较大而可相当于断路，此时环路滤波器300的电路结构可以等效为图3B。由图3B可以看到，此时环路滤波器300的电路结构相当于是 对第二电容330和第三电容350进行了串联，所以第三电容350能够对该串联电路进行分压。那么，环路滤波器300的第一电阻310也可以相对于现有的二阶环路滤波器的第一电阻而言增加相应的倍数，而到输出端的跨阻仍维持不变。在此基础上，由于第一电阻310可以增大，则第一电容320的电容值可以以对应于第一电阻310的电阻值增大的比例来减小，以维持原有环路的零极点基本不变。
在环路滤波器300的电阻噪声的传递方面，第一电阻310的增大并不会引起其噪声电压平方的增大，反而会在一定程度上减小噪声传递。具体而言，由于电容分压的存在，电阻的输出噪声电压平方也要乘以一个与该比例对应的分数的平方。R1的电阻噪声可以由其电阻噪声的平方表示如下：
Figure PCTCN2022086574-appb-000009
其中，k＝1.37*10 -23J/K为玻尔兹曼常数，T为绝对温度。由式(3)可以看到，由于有与第一电阻增大的比例对应的分数的平方
Figure PCTCN2022086574-appb-000010
的存在，即使增大第一电阻310的电阻值R 1，
Figure PCTCN2022086574-appb-000011
也会减小。例如，假设第二电容330和第三电容350的电容值相等(即C 2＝C 3)，第一电阻310的电阻值R 1增大为原来的2倍，由于k和T维持不变，则由式(3)的计算可以得到
Figure PCTCN2022086574-appb-000012
仍会相比第一电阻310的电阻值R 1增大前减小2倍，这相当于3dB的噪声衰减。
由此还可以看出，若
Figure PCTCN2022086574-appb-000013
比值更小(例如C 2＞C 3)，则第一电阻310的电阻噪声衰减会更大。所以，可以进一步根据实际应用中对电阻噪声衰减的需要来确定C 2和C 3的具体比值大小。
此外，可以优选地将第二电阻340的电阻值R 2配置成使得第二电阻340的噪声带宽低于环路滤波器300的环路带宽。由于引入的第二电阻340同样会贡献一些环路滤波器的电阻噪声，如果设置较 大的第二电阻340，除了能够使其在高频输入信号时近似于断路之外，其噪声带宽还一般低于(甚至远低于)环路滤波器的环路带宽，所以由第二电阻340引起的电阻噪声的大部分将会在环路滤波器电路中被滤除。
在一些实施例中，本发明所述的组成桥接电路所使用的并联的电容器件和电阻器件并不限于无源器件，而是也可以由有源器件并联组成。例如，电阻器件也可以采用有源MOS管电阻器，而第三电容还可采用有源MOS管电容器。再例如，电阻器件还可以替换为电平转换器，并使得电平转换器的等效电阻值相当于原电阻器件，这可以在提供等效电阻的同时加入电平转换的功能。而无论电容器件和电阻器件采用的是有源器件还是无源器件的形式，其皆可等效为如前所述的关于图3所描述的环路滤波器300的形式，例如，有源MOS管电阻器或电平转换器的等效电阻值为R 2，而有源MOS管电容器的等效电容值为C 3。
图4示出了包含根据本发明的一个实施例的环路滤波器的锁相环的输出噪声频谱曲线与包含现有二阶环路滤波器的锁相环的输出噪声频谱曲线。该噪声频谱来源于锁相环中所有器件(例如电荷泵、环路滤波器、压控振荡器等)的噪声。其中，横坐标为非线性的频率，纵坐标为噪声电压的平方根，a线代表包含现有二阶环路滤波器(各器件参数：R 1＝2kΩ、C 1＝1nF、C 2＝40pF)的锁相环的输出噪声频谱曲线，b线代表包含根据本发明的一个实施例的环路滤波器(各器件参数：R 1＝4kΩ、C 1＝500pF、C 2＝40pF、R 2＝160kΩ、C 3＝40pF)的锁相环的输出噪声频谱曲线，而两种锁相环的其他器件参数取值保持一致。
由图4可知，b线的噪声频谱曲线在输入频率较低时与a线几乎重合，然后b线在带内略有抬升，例如，在输入频率约为60kHz处的M5、M6点处提升了约2dB。随着输入频率继续升高，在输入频率约为166kHz的M4点处b线与a线交叉。而后，在输入频率 大于166kHz时，b线的噪声频谱曲线始终低于a线，且在大于166kHz的大部分频率范围内总是比a曲线低2dB左右。例如，在图4中的输入频率为1MHz的A、B点处，本发明的环路滤波器使得锁相环总体噪声频谱下降了约2.04dB。因此，图5中示出的本发明的环路滤波器的实施例在绝大部分带宽内(例如大于166kHz的带宽内)降低了噪声电压。
图5示出了分别包含根据图4的实施例的两种环路滤波器的两种环路滤波器对应的锁相环增益传递函数对比。由图5可知，两种环路滤波器的环路增益传递函数曲线较为相似，且相位裕度较为接近。其中，两种环路滤波器的环路带宽在较高的频率范围内基本重合(例如，在图5中横坐标为599.415kHz时，a线和b线的环路增益已经非常接近，而在大于599.415kHz的大部分频率范围内几乎相等)，且相位裕度处于60°到70°之间，说明本发明的环路滤波器与现有二阶环路滤波器一样具备一定的稳定性。
在另一方面，本发明还包括锁相环，其包含如前所述的本发明的任一种环路滤波器。
综上所述，本发明所述的环路滤波器设计通过引入桥接电路而使得在降低电阻噪声的同时进一步降低第一电容的电容值C 1，且环路带宽和相位裕度基本不变。电容值的降低允许面积更小的电容设计，从而进一步减小了芯片的面积。
以上主要说明了本发明的环路滤波器和锁相环。尽管只对其中一些本发明的具体实施方式进行了描述，但是本领域普通技术人员应当了解，本发明可以在不偏离其主旨与范围内以许多其他的形式实施。因此，所展示的例子与实施方式被视为示意性的而非限制性的，在不脱离如所附各权利要求所定义的本发明精神及范围的情况下，本发明可能涵盖各种的修改与替换。

Claims (10)

  1. 一种用于锁相环的环路滤波器，包括第一电阻、第一电容和第二电容，其中所述第一电阻和所述第一电容连接在所述环路滤波器的输入端和接地端之间，所述第二电容连接在所述环路滤波器的输出端和接地端之间，其特征在于，所述环路滤波器还包括：
    桥接电路，所述桥接电路连接在所述环路滤波器的输入端和输出端之间，用于对所述环路滤波器的输入信号进行分压。
  2. 根据权利要求1所述的环路滤波器，其特征在于，所述桥接电路用于在所述环路滤波器的输入为第一频率时对所述环路滤波器的输入信号进行分压，在所述环路滤波器的输入为第二频率时为所述环路滤波器的输入端到输出端提供直流偏置，其中，所述第二频率低于所述第一频率。
  3. 根据权利要求1或2所述的环路滤波器，其特征在于，所述桥接电路包括第二电阻和第三电容，其中：
    所述第二电阻的第一端连接到所述环路滤波器的输入端，所述第二电阻的第二端连接到所述环路滤波器的输出端；
    所述第三电容的第一端连接到所述环路滤波器的输入端，所述第三电容的第二端连接到所述环路滤波器的输出端。
  4. 根据权利要求3所述的环路滤波器，其特征在于：
    所述第二电阻采用无源电阻器、有源MOS管电阻器和电平转换器的等效电阻中的任一种；
    所述第三电容采用无源电容器和有源MOS管电容器中的任一种。
  5. 根据权利要求3所述的环路滤波器，其特征在于，所述第二电阻的电阻值配置成使得所述第二电阻的噪声带宽低于所述环路滤波器的环路带宽。
  6. 根据权利要求3所述的环路滤波器，其特征在于，所述第二电阻的电阻值大于所述第一电阻的电阻值。
  7. 根据权利要求3所述的环路滤波器，其特征在于，所述第二电容和所述第三电容的电容值均小于所述第一电容的电容值。
  8. 根据权利要求3所述的环路滤波器，其特征在于，所述第二电阻的电阻值范围为1-500kΩ。
  9. 根据权利要求3所述的环路滤波器，其特征在于，所述第三电容的电容值范围为5-200pF。
  10. 一种锁相环，其特征在于，所述锁相环包含如权利要求1-9中的任一项所述的环路滤波器。
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