WO2024031756A1 - 薄膜晶体管及电子器件 - Google Patents

薄膜晶体管及电子器件 Download PDF

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Publication number
WO2024031756A1
WO2024031756A1 PCT/CN2022/115992 CN2022115992W WO2024031756A1 WO 2024031756 A1 WO2024031756 A1 WO 2024031756A1 CN 2022115992 W CN2022115992 W CN 2022115992W WO 2024031756 A1 WO2024031756 A1 WO 2024031756A1
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Prior art keywords
active pattern
crystalline active
contact
channel
groove
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PCT/CN2022/115992
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English (en)
French (fr)
Inventor
艾飞
宋德伟
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武汉华星光电技术有限公司
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Publication of WO2024031756A1 publication Critical patent/WO2024031756A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present application relates to the field of display technology, and in particular to a thin film transistor and an electronic device.
  • Integrate integrated chip (Integrated Chip) on glass substrate can greatly improve the integration of display panels and reduce the manufacturing cost of display panels.
  • SOG System On Glass
  • the purpose of this application is to provide a thin film transistor and an electronic device that are beneficial to improving the mobility of the thin film transistor.
  • a thin film transistor the thin film transistor includes:
  • Crystalline active pattern the crystalline active pattern includes:
  • At least one groove is located on at least one of the two contact portions and extends in the thickness direction of the crystalline active pattern
  • the source electrode and the drain electrode are respectively connected to the two contact parts;
  • An insulation layer the insulation layer is in contact with the channel.
  • the crystalline active pattern further includes two transition portions, one of the transition portions is connected between one of the contact portions and the channel, and the insulation layer is also connected to two transition portions.
  • the transition portion contacts.
  • the crystalline active pattern includes grains having a size greater than or equal to 300 nanometers.
  • the refractive index of the thermal insulation layer is n
  • the thickness of the thermal insulation layer is d
  • the n, the d and the wavelength ⁇ of the laser satisfy the following formula:
  • 2d ⁇ n k ⁇ , where k is an integer greater than or equal to 1, and the wavelength ⁇ of the laser is greater than or equal to 180 nanometers and less than or equal to 420 nanometers.
  • the thickness of the thermal insulation layer is greater than or equal to 100 angstroms and less than or equal to 1000 angstroms.
  • the depth of the groove is less than or equal to the thickness of the crystalline active pattern, and the groove is located at a position of at least one of the contacts close to the channel.
  • the depth of the groove is less than the thickness of the crystalline active pattern, and the groove on one of the contact portions completely overlaps the contact portion.
  • the thin film transistor further includes:
  • the gate is arranged corresponding to the channel
  • a gate insulating layer located between the gate electrode and the crystalline active pattern
  • An interlayer insulating layer located between the crystalline active pattern and the source electrode and the drain electrode;
  • Two contact holes at least penetrate the interlayer insulating layer, and the source electrode and the drain electrode are respectively connected to the two contact portions through the two contact holes.
  • the gate electrode is located between the crystalline active pattern and the source electrode and the drain electrode, and the interlayer insulating layer is located between the gate electrode, the source electrode and the drain electrode. between drains;
  • the two contact holes also penetrate the gate insulation layer, at least one of the two contact holes overlaps the groove, and the aperture of the contact hole is larger than the opening size of the groove.
  • An electronic device includes the thin film transistor described in any of the above embodiments.
  • the present application provides a thin film transistor and an electronic device.
  • a groove on at least one of the two contact parts of the crystallized active pattern it is beneficial to form a seed crystal at the groove during crystallization to form the crystallized active pattern.
  • the crystal direction grows close to the channel before crystallization, and the heat preservation layer is used to slow down the heat dissipation in the channel before crystallization, so that large-sized grains are formed in the channel, and the grain boundaries in the channel of the crystallized active pattern are reduced, thereby improving the film Transistor mobility.
  • Figure 1 is a schematic plan view of an array substrate according to an embodiment of the present application.
  • Figure 2 is a schematic cross-sectional view along the tangent line A-A of the array substrate shown in Figure 1;
  • Figure 3 is a schematic cross-sectional view along line B-B of the array substrate shown in Figure 1;
  • Figure 4 is a schematic cross-sectional view of an array substrate according to another embodiment of the present application.
  • Figure 5 is a schematic plan view of the crystalline active pattern in Figure 4.
  • Figure 6 is a schematic cross-sectional view of an array substrate according to another embodiment of the present application.
  • FIGS. 7A-7J are schematic diagrams of the process of manufacturing an array substrate according to an embodiment of the present application.
  • FIG. 8 is a schematic cross-sectional view of an electronic device according to an embodiment of the present application.
  • Figure 1 is a schematic plan view of an array substrate according to an embodiment of the present application.
  • Figure 2 is a schematic cross-sectional view along line A-A of the array substrate shown in Figure 1.
  • Figure 3 is a schematic view along the line A-A of the array substrate shown in Figure 1. Schematic cross-section along the B-B tangent line of the substrate.
  • the array substrate 100 includes a substrate 10 and a plurality of thin film transistors 11 arranged in an array on the substrate 10 .
  • the substrate 10 is an insulating substrate, such as a glass substrate, but is not limited thereto.
  • the substrate 10 may also be a flexible substrate.
  • the thin film transistor 11 is a low-temperature polysilicon thin film transistor, but is not limited thereto.
  • the thin film transistor 11 may also be a crystalline metal oxide thin film transistor.
  • the array substrate 100 further includes a light-shielding pattern 12 and a buffer layer 13 .
  • the light shielding pattern 12 is located between the thin film transistor 11 and the substrate 10
  • the buffer layer 13 is located between the light shielding pattern 12 and the thin film transistor 11 .
  • the light-shielding pattern 12 is disposed on the substrate 10 in a flat state.
  • the light-shielding pattern 12 is made of at least one of metal and black organic materials.
  • the buffer layer 13 covers the light-shielding pattern 12 and the substrate 10 .
  • the preparation material of the buffer layer 13 includes at least one of silicon nitride and silicon oxide.
  • the thickness of the buffer layer 13 is greater than or equal to 2500 angstroms and less than or equal to 3500 angstroms, such as 2500 angstroms, 2800 angstroms, 3000 angstroms or 3500 angstroms.
  • the thin film transistor 11 includes a crystalline active pattern 111, a gate electrode 112, a source electrode 1161, a drain electrode 1162, a gate insulating layer 113, an interlayer insulating layer 114 and a thermal insulation layer 115.
  • the crystalline active pattern 111 is a low-temperature polysilicon active pattern, but is not limited thereto.
  • the crystalline active pattern 111 may also be a crystalline metal oxide active pattern.
  • the thickness of the crystalline active pattern 111 is greater than or equal to 300 angstroms and less than or equal to 600 angstroms, such as 350 angstroms, 380 angstroms, 400 angstroms, 420 angstroms, 450 angstroms, 480 angstroms, 500 angstroms or 600 angstroms.
  • the crystalline active pattern 111 is disposed on the buffer layer 13 .
  • the crystalline active pattern 111 includes a channel 1111 , two contact portions 1112 and two transition portions 1113 . In a direction intersecting the thickness direction of the crystalline active pattern 111 , two contact portions 1112 are connected to opposite sides of the channel 1111 , and a transition portion 1113 is connected between one contact portion 1112 and the channel 1111 .
  • two contact portions 1112 are respectively connected to opposite sides of the channel 1111 , and a transition portion 1113 is connected between one contact portion 1112 and the channel 1111 .
  • the channel 1111 and the two transition portions 1113 overlap with the light-shielding pattern 12 , so that the light-shielding pattern 12 plays a role in blocking light incident on the channel 1111 and the two transition portions 1113 .
  • the channel 1111 is not doped with ions
  • the two contact portions 1112 and the two transition portions 1113 are doped with ions
  • the ion doping concentration of the two transition portions 1113 is lower than that of the two contact portions 1112 impurity concentration.
  • the crystalline active pattern 111 further includes at least one groove 111 a located on at least one of the two contact portions 1112 , and the at least one groove 111 a is located on a side of the contact portion 1112 away from the substrate 10 On the other side, at least one groove 111a extends in the thickness direction of the crystalline active pattern 111, and the depth of the at least one groove 111a is less than or equal to the thickness of the crystalline active pattern 111.
  • At least one groove 111a can be provided on one contact portion 1112 or on two contact portions 1112 .
  • One, two or more grooves 111a may be provided on each contact portion 1112 .
  • the depth of the groove 111 a may be equal to the thickness of the crystalline active pattern 111 , or the depth of the groove 111 a may be smaller than the thickness of the crystalline active pattern 111 .
  • At least one groove 111a is located at a position of at least one contact portion 1112 close to the channel 1111.
  • at least one groove 111a is located at a partial position of the contact portion 1112, and at least one groove 111a is provided close to the transition portion 1113 .
  • the design of the grooves of the crystalline active pattern in the embodiment of the present application makes the crystalline active pattern before crystallization have a mutation point. This mutation point is more likely to form a seed crystal, thereby making the grooves crystallize to form the crystalline active pattern. During the process, it plays a role in grain positioning.
  • the groove is set close to the transition part, which is conducive to the growth of the seed crystal laterally to the transition part and channel before crystallization.
  • a groove 111 a is located at a position where a contact portion 1112 is close to the channel 1111 , and the depth of the groove 111 a is equal to the thickness of the crystalline active pattern 111 , that is, the groove 111 a is close to the channel. 1111 set of through holes.
  • the orthographic projection of a groove 111a on the substrate 10 is located within the orthographic projection of a contact portion 1112 on the substrate 10, and the area of the orthographic projection of a groove 111a on the substrate 10 is smaller than that of a contact portion 1112 on the substrate 10. In the orthographic projection area, the groove 111a does not break the contact portion 1112 into two divided parts.
  • Figure 4 is a schematic cross-sectional view of an array substrate according to another embodiment of the present application
  • Figure 5 is a schematic plan view of the crystalline active pattern in Figure 4.
  • the two grooves 111a are respectively located at the positions of the two contact portions 1112 close to the channel 1111.
  • the two grooves 111a are symmetrically arranged on opposite sides of the channel 1111, and the depth of the two grooves 111a is smaller than the crystalline active pattern 111. thickness of.
  • the shape of the cross section of the groove 111a along the thickness direction of the crystalline active pattern 111 may be a rectangle, a trapezoid, or other shapes.
  • the shape of the cross section of the groove 111a in a direction perpendicular to the thickness of the crystalline active pattern 111 may be rectangular, circular, or other shapes.
  • the thermal insulation layer 115 plays a thermal insulation role to reduce the heat dissipation rate.
  • the insulation layer 115 is in contact with the channel 1111 .
  • the thermal insulation layer 115 is located on the surface of the crystalline active pattern 111 away from the substrate 10 , but is not limited thereto.
  • the thermal insulation layer 115 can also be located between the crystalline active pattern 111 and the buffer layer 13 and close to the surface of the substrate 10 with the crystalline active pattern 111 . touch.
  • the thickness of the insulation layer 115 is greater than or equal to 100 angstroms and less than or equal to 1000 angstroms, such as 200 angstroms, 300 angstroms, 400 angstroms, 600 angstroms, 800 angstroms or 1000 angstroms.
  • the insulation layer 115 is made of materials including but not limited to silicon oxide.
  • the thermal insulation layer 115 is in contact with the channel 1111 and the two transition portions 1113, and the thermal insulation layer 115 is not in contact with the two contact portions 1112 to reduce the heat dissipation rate of the channel 1111 before crystallization and the two transition portions 1113 after laser annealing. This is beneficial to the formation of large-sized grains in the channel 1111 and the two transition portions 1113 .
  • the insulation layer insulates the channel before crystallization and the two transition parts.
  • the groove to be formed in the amorphous active pattern is The heat dissipation of the channel and the two transition parts slows down, and the seed crystal generated at the groove grows laterally along the part of the amorphous active pattern where the channel and the two transition parts are to be formed, thereby making the channel and the two transition parts Large-sized grains are formed in the transition section.
  • the refractive index of the thermal insulation layer 115 is n
  • the thickness of the thermal insulation layer 115 is d
  • the wavelength of the laser is ⁇ .
  • the wavelength ⁇ of the laser may be 305 nanometers to 310 nanometers.
  • the laser is a laser with a wavelength ⁇ of 308 nanometers emitted by a XeCl excimer laser. It can be understood that the wavelength ⁇ of the laser can be 185 nanometers to 200 nanometers.
  • the laser can also be a laser with a wavelength of 193 nanometers emitted by an ArF excimer laser; alternatively, the wavelength ⁇ of the light can be 230 nanometers to 250 nanometers.
  • the laser can also be a laser with a wavelength of 248 nanometers emitted by a KrF excimer laser.
  • the refractive index of the thermal insulation layer 115 is 1.6.
  • the value of k can be 2, 3, 4, 5 or 6.
  • the amorphous active pattern under the insulation layer obtains more laser energy, and larger-sized grains tend to be formed in the amorphous active pattern under the insulation layer.
  • the channels and the two transition parts are formed Larger grain sizes are conducive to improving the mobility of thin film transistors, which in turn facilitates the integration of integrated chips on insulating substrates.
  • the crystalline active pattern 111 includes crystal grains with a size greater than or equal to 300 nanometers, such as 320 nanometers, 330 nanometers, 345 nanometers, 350 nanometers, 360nm, 370nm, 380nm, 390nm or 400nm grains.
  • the gate electrode 112 is located on the side of the insulation layer 115 away from the substrate 10 .
  • the thin film transistor 11 is a top-gate thin film transistor. It can be understood that the gate electrode 112 may also be located between the crystalline active pattern 111 and the buffer layer 13. In other words, the thin film transistor 11 is a bottom gate thin film transistor.
  • the gate 112 is arranged corresponding to the channel 1111.
  • the gate 112 is made of a material including, but not limited to, at least one of molybdenum, aluminum, titanium, copper, and silver.
  • the gate insulating layer 113 is disposed between the gate 112 and the thermal insulation layer 115 .
  • the preparation material of the gate insulating layer 113 includes but is not limited to at least one of silicon nitride and silicon oxide.
  • the thickness of the gate insulating layer 113 is greater than or equal to 500 angstroms and less than or equal to 1500 angstroms, such as 800 angstroms, 1000 angstroms, 1200 angstroms, 1300 angstroms or 1500 angstroms.
  • the gate electrode 112 is located between the crystalline active pattern 111 and the source electrode 1161 and the drain electrode 1162.
  • the source electrode 1161 and the drain electrode 1162 are arranged in the same layer.
  • the source electrode 1161 and the drain electrode 1162 are respectively connected with the two contact portions. 1112 connection.
  • the source electrode 1161 and the drain electrode 1162 are made of materials including, but not limited to, at least one of molybdenum, aluminum, titanium, copper, and silver.
  • the interlayer insulating layer 114 is located between the crystalline active pattern 111 and the source electrode 1161 and the drain electrode 1162 , and the interlayer insulating layer 114 is located between the gate electrode 112 and the source electrode 1161 and the drain electrode 1162 .
  • the interlayer insulating layer 114 is made of a material including, but not limited to, at least one of silicon nitride and silicon oxide.
  • the thickness of the interlayer insulating layer 114 is greater than or equal to 5000 angstroms and less than or equal to 6500 angstroms, such as 5200 angstroms, 5400 angstroms, 5500 angstroms, 5600 angstroms or 5800 angstroms.
  • the array substrate 100 further includes two contact holes 100a.
  • the two contact holes 100a are respectively provided corresponding to the two contact portions 1112.
  • the two contact holes 100a penetrate the interlayer insulating layer 114 and the gate insulating layer 113.
  • the source The electrode 1161 is in contact with one contact portion 1112 through one contact hole 100a, and the drain electrode 1162 is in contact with the other contact portion 1112 through the other contact hole 100a.
  • the two contact holes 100 a only need to penetrate the interlayer insulating layer 114 .
  • At least one of the two contact holes 100a overlaps with at least one groove 111a.
  • one contact hole 100a overlaps one groove 111a, and one of the source electrode 1161 and the drain electrode 1162 passes through one contact hole 100a and the groove 111a.
  • the contact portion 1112 contacts the surface away from the substrate 10 .
  • the two contact holes 100a can also overlap the two grooves 111a in a one-to-one correspondence, and the source 1161 passes through one contact hole 100a.
  • a ring contact is formed between one groove 111a and one contact portion 1112, and the drain electrode 1162 forms a ring contact between another contact hole 100a and another groove 111a and another contact portion 1112.
  • the aperture R of the contact hole 100a is larger than the opening size L of the groove 111a, so that the gate insulation layer located in the groove 111a can be etched away during the formation of the contact hole 100a. , realizing communication between the contact hole 100a and the groove 111a, and thereby realizing the connection between one of the source electrode 1161 and the drain electrode 1162 and one contact portion 1112.
  • neither of the two contact holes 100a may overlap with the groove 111a.
  • the groove 111a is located at part of the contact portion 1112.
  • the source electrode 1161 and the drain electrode 1162 are indented with the contact portion 1112 through the two contact holes 100a.
  • the portion outside the groove 111a is in contact.
  • FIG. 6 is a schematic cross-sectional view of an array substrate according to another embodiment of the present application.
  • the array substrate of this embodiment is basically similar to the array substrate shown in FIG. 4 , and the similarities will not be repeated.
  • the differences include that the depth of the groove 111 a is smaller than the thickness of the crystalline active pattern 111 , and the groove on one contact portion 1112 111a completely overlaps the contact portion 1112.
  • a step is formed between at least one contact portion 1112 and the transition portion 1113.
  • the orthographic projection of a groove 111a on the substrate 10 completely coincides with the orthographic projection of a contact portion 1112 on the substrate 10.
  • the area of the orthographic projection of a groove 111a on the substrate 10 is the same as that of a contact portion 1112 on the substrate 10.
  • the area of the orthogonal projection of the contact portion 1112 on the substrate 10 is the same. Therefore, the groove 111 a is formed by thinning the contact portion 1112 in the thickness direction of the crystalline active pattern 111 .
  • this application also provides a method for manufacturing an array substrate.
  • the method for manufacturing an array substrate includes the following steps:
  • a first patterning process is used to pattern the light-shielding metal layer to obtain a light-shielding pattern 12 located on the substrate 10 , and a buffer layer 13 covering the light-shielding pattern 12 and the substrate 10 is formed.
  • an entire amorphous silicon semiconductor layer 14 and an entire thermal insulation film 115a are formed on the buffer layer 13, and a second patterning process is used to pattern the thermal insulation film 115a. Insulation layer 115; then use a third patterning process to pattern the amorphous silicon semiconductor layer 14 to obtain an amorphous silicon semiconductor pattern 141.
  • the amorphous silicon semiconductor pattern 141 has a channel area 141a, two contact areas 141b and two The transition region 141c and the two contact regions 141b are respectively located on opposite sides of the channel region 141a in a direction perpendicular to the thickness of the amorphous silicon semiconductor pattern 141.
  • a transition region 141c is connected between the channel region 141a and a contact region 141b.
  • the thermal insulation layer 115 overlaps with the two transition regions 141c and the channel region 141a of the amorphous silicon semiconductor pattern 141
  • the light-shielding pattern 12 overlaps with the two transition regions 141c and the channel region 141a of the amorphous silicon semiconductor pattern 141.
  • the silicon semiconductor pattern 141 includes a groove 111 a located at a part of a contact region 141 b and close to the transition region 141 c. The depth of the groove 111 a is equal to the thickness of the amorphous silicon semiconductor pattern 141 .
  • the amorphous silicon semiconductor pattern 141 is annealed using laser L with a wavelength ⁇ of 308 nanometers emitted by a XeCl excimer laser to obtain a polycrystalline silicon semiconductor pattern 142 .
  • the seed crystal 1411 is easily formed at the groove 111a.
  • the amorphous silicon semiconductor pattern 141 located in the two transition areas 141c and the channel area 141a dissipates heat slowly under the action of the insulation layer 115, and the seed crystal 1411 is easily formed in the groove 111a.
  • 1411 grows laterally toward the transition region 141c and the channel region 141a, making it easy to form large-sized grains in the transition region 141c and the channel region 141a.
  • the refractive index n of the thermal insulation layer 115, the thickness d of the thermal insulation layer 115, and the wavelength ⁇ of the laser satisfy the formula 2d During the annealing and crystallization process of the semiconductor pattern 141, it plays an anti-reflective effect on the laser. More laser light passes through the insulation layer 115. The amorphous silicon semiconductor pattern 141 below the insulation layer 115 obtains more laser energy. The amorphous silicon semiconductor pattern 141 below the insulation layer 115 obtains more laser energy. Larger-sized crystal grains tend to be formed in the silicon semiconductor pattern 141, and correspondingly, larger-sized crystal grains are further formed in the transition region 141c and the channel region 141a.
  • a heavy ion doping process is used to process the two contact areas 141b of the polysilicon semiconductor pattern 142 to obtain a heavily doped polysilicon semiconductor pattern 143.
  • the heavily doped polysilicon semiconductor pattern 143 includes two contact areas 141b located at the two contact areas 141b. Contact portion 1112.
  • a gate insulating layer 113 covering the heavily doped polysilicon semiconductor pattern 143 and the buffer layer 13 is formed, and the gate metal layer is patterned through a fourth patterning process on the gate insulating layer 113 .
  • the gate electrode 112 is obtained.
  • the gate electrode 112 is arranged corresponding to the channel region 141a.
  • the gate electrode 112 is used as a mask and the two transition regions 141c are processed using a light ion doping process to obtain a crystalline active pattern 111.
  • the crystalline active pattern 111 It includes a channel 1111 located in the channel region 141a and a transition portion 1113 located in two transition regions 141c. A transition portion 1113 is connected between a contact portion 1112 and the channel 1111.
  • an interlayer insulating layer 114 covering the gate electrode 112 and the gate insulating layer 113 is formed, and the fifth patterning process is used to pattern the interlayer insulating layer 114 and the gate insulating layer 113 to obtain two
  • the two contact holes 100a are each provided corresponding to the two contact portions 1112, and one of the two contact holes 100a is connected to the groove 111a.
  • a source and drain electrode metal layer is formed on the surface of the interlayer insulating layer 114 away from the gate insulating layer 113, in the two contact holes 100a and the groove 111a.
  • the sixth patterning process is used to pattern the source and drain electrode metal layers.
  • the layer is patterned to obtain a source electrode 1161 and a drain electrode 1162.
  • the source electrode 1161 forms an annular contact with a contact portion 1112 through a contact hole 100a and a groove 111a.
  • the drain electrode 1162 forms an annular contact with another contact portion 1112 through another contact hole 100a. touch.
  • the manufacturing method of the array substrate according to the embodiment of the present application provides a groove through at least one of the two contact areas of the amorphous silicon semiconductor pattern, which is beneficial to the process of crystallizing the amorphous silicon semiconductor pattern to form a crystalline active pattern at the groove.
  • the seed crystal is formed, and the seed crystal grows towards the transition zone and the channel zone, and cooperates with the insulation layer to make the amorphous silicon semiconductor pattern in the transition zone and the channel zone dissipate heat slowly, so that large-sized grains are formed in the transition zone and the channel zone. Grain boundaries in the channels of the crystalline active pattern are reduced, thereby increasing the mobility of the thin film transistor.
  • the electronic device 200 is a display panel.
  • the electronic device 200 can be a liquid crystal display panel, an organic light-emitting diode display panel, a quantum dot light-emitting diode display panel, a sub-millimeter light-emitting diode display panel, or a micron light-emitting diode display. At least one of the panels.
  • FIG. 8 it is a schematic cross-sectional view of an electronic device according to an embodiment of the present application.
  • the electronic device 200 includes an array substrate 100, a color filter substrate 300, and a liquid crystal layer (not shown) between the array substrate 100 and the color filter substrate 300.
  • the array substrate 100 is basically similar to the array substrate 100 shown in FIGS. 1 and 2 above. , the similarities will not be repeated. The differences include that the array substrate 100 also includes a planarization layer 15 , a common electrode 16 , a passivation layer 17 and a pixel electrode 18 .
  • the planarization layer 15 covers the interlayer insulating layer 114, the source electrode 1161 and the drain electrode 1162, the common electrode 16 is provided on the planarization layer 15, the passivation layer 17 covers the common electrode 16 and the planarization layer 15, and the pixel electrode 18 is provided On the passivation layer 17 , the pixel electrode 18 is connected to the drain electrode 1162 through a via hole penetrating the passivation layer 17 and the planarization layer 15 .
  • grooves are provided on at least one of the two contact portions of the crystallized active pattern, which is conducive to the formation of seed crystals at the grooves during the crystallization process to form the crystallized active pattern, and the seed crystals move closer to the crystallized Before the channel growth, the heat preservation layer is used to slow down the heat dissipation of the channel before crystallization, so that large-sized grains are formed in the channel, reducing the grain boundaries in the channel of the crystallized active pattern, thereby improving the mobility of the thin film transistor. It is beneficial to realize the integration of integrated chips on the insulating substrate of electronic devices and reduce the cost of electronic devices.

Abstract

本申请提供一种薄膜晶体管及电子器件，薄膜晶体管包括：结晶有源图案，包括：沟道；两个接触部，在与结晶有源图案的厚度方向相交的方向上，两个接触部连接于沟道的相对两侧；以及凹槽，位于两个接触部中的至少一个上，在结晶有源图案的厚度方向上延伸；源极和漏极，分别与两个接触部连接；以及保温层，保温层与沟道接触。

Description

薄膜晶体管及电子器件 技术领域
本申请涉及显示技术领域，尤其涉及一种薄膜晶体管及电子器件。
 背景技术
将集成芯片（Integrated Chip）集成在玻璃基板上（System On Glass, SOG）可以极大地提高显示面板的集成度，降低显示面板的制造成本。然而，实现集成芯片集成在玻璃基板上需要提高薄膜晶体管的迁移率。
因此，如何提高薄膜晶体管的迁移率是需要解决的技术问题。
 技术问题
本申请的目的在于提供一种薄膜晶体管及电子器件，有利于提高薄膜晶体管的迁移率。
 技术解决方案
一种薄膜晶体管，所述薄膜晶体管包括：
结晶有源图案，所述结晶有源图案包括：
沟道；
两个接触部，在与所述结晶有源图案的厚度方向相交的方向上，两个所述接触部连接于所述沟道的相对两侧；以及
至少一个凹槽，位于两个所述接触部中的至少一个上，且在所述结晶有源图案的厚度方向上延伸；
源极和漏极，分别与两个所述接触部连接；以及
保温层，所述保温层与所述沟道接触。
在一些实施例的薄膜晶体管中，所述结晶有源图案还包括两个过渡部，一个所述过渡部连接于一个所述接触部与所述沟道之间，所述保温层还与两个所述过渡部接触。
在一些实施例的薄膜晶体管中，所述结晶有源图案包括尺寸大于或等于300纳米的晶粒。
在一些实施例的薄膜晶体管中，所述保温层的折射率为n，所述保温层的厚度为d，所述n、所述d以及激光的波长λ满足如下公式：
2d×n=k×λ，其中，所述k为大于或等于1的整数，所述激光的波长λ大于或等于180纳米且小于或等于420纳米。
在一些实施例的薄膜晶体管中，所述保温层的厚度大于或等于100埃且小于或等于1000埃。
在一些实施例的薄膜晶体管中，所述凹槽的深度小于或等于所述结晶有源图案的厚度，所述凹槽位于至少一个所述接触部靠近所述沟道的位置。
在一些实施例的薄膜晶体管中，所述凹槽的深度小于所述结晶有源图案的厚度，一个所述接触部上的所述凹槽与所述接触部完全重叠。
在一些实施例的薄膜晶体管中，所述薄膜晶体管还包括：
栅极，对应所述沟道设置；
栅极绝缘层，位于所述栅极与所述结晶有源图案之间；
层间绝缘层，位于所述结晶有源图案与所述源极和所述漏极之间；
两个接触孔，至少贯穿所述层间绝缘层，所述源极和所述漏极分别通过两个所述接触孔与两个所述接触部连接。
在一些实施例的薄膜晶体管中，所述栅极位于所述结晶有源图案与所述源极和漏极之间，所述层间绝缘层位于所述栅极与所述源极和所述漏极之间；
两个所述接触孔还贯穿所述栅极绝缘层，两个所述接触孔中的至少一者与所述凹槽重叠，所述接触孔的孔径大于所述凹槽的开口尺寸。
一种电子器件，所述电子器件包括上述任一实施例所述的薄膜晶体管。
 有益效果
本申请提供一种薄膜晶体管及电子器件，通过结晶有源图案的两个接触部的至少一者上设置凹槽，有利于在结晶以形成结晶有源图案过程中凹槽处形成籽晶，籽晶向靠近晶化前的沟道生长，配合保温层使晶化前的沟道散热较慢，以使沟道中形成大尺寸晶粒，减少结晶有源图案的沟道中的晶界，进而提高薄膜晶体管的迁移率。
 附图说明
图1为本申请一实施例阵列基板的平面示意图；
图2为沿图1所示阵列基板A-A切线的截面示意图；
图3为沿图1所示阵列基板B-B切线的截面示意图；
图4为本申请另一实施例阵列基板的截面示意图；
图5为图4中结晶有源图案的平面示意图；
图6为本申请又一实施例阵列基板的截面示意图；
图7A-图7J为制造本申请一实施例阵列基板的过程示意图；
图8为本申请一实施例电子器件的截面示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1、图2以及图3，图1为本申请一实施例阵列基板的平面示意图，图2为沿图1所示阵列基板A-A切线的截面示意图，图3为沿图1所示阵列基板B-B切线的截面示意图。
在本实施例中，阵列基板100包括基板10和设置于基板10上的多个阵列排布的薄膜晶体管11。基板10为绝缘基板，例如为玻璃基板，但不限于此，基板10也可以为柔性基板。薄膜晶体管11为低温多晶硅薄膜晶体管，但不限于此，薄膜晶体管11也可以为结晶金属氧化物薄膜晶体管。
在本实施例中，阵列基板100还包括遮光图案12和缓冲层13。遮光图案12位于薄膜晶体管11与基板10之间，缓冲层13位于遮光图案12与薄膜晶体管11之间。
在本实施例中，遮光图案12呈平直状态设置于基板10上。遮光图案12的制备材料包括金属和黑色有机材料中的至少一种。
在本实施例中，缓冲层13覆盖遮光图案12和基板10。缓冲层13的制备材料包括氮化硅和氧化硅中的至少一种。缓冲层13的厚度大于或等于2500埃且小于或等于3500埃，例如为2500埃、2800埃、3000埃或3500埃。
在本实施例中，薄膜晶体管11包括结晶有源图案111、栅极112、源极1161、漏极1162、栅极绝缘层113、层间绝缘层114以及保温层115。
在本实施例中，结晶有源图案111为低温多晶硅有源图案，但不限于此，结晶有源图案111也可以为结晶金属氧化物有源图案。结晶有源图案111的厚度大于或等于300埃且小于或等于600埃，例如为350埃、380埃、400埃、420埃、450埃、480埃、500埃或者600埃。
在本实施例中，结晶有源图案111设置于缓冲层13上。结晶有源图案111包括沟道1111、两个接触部1112以及两个过渡部1113。在与结晶有源图案111的厚度方向相交的方向上，两个接触部1112连接于沟道1111的相对两侧，一个过渡部1113连接于一个接触部1112与沟道1111之间。
具体地，在垂直于结晶有源图案111的厚度的方向上，两个接触部1112分别连接于沟道1111的相对两侧，一个过渡部1113连接于一个接触部1112与沟道1111之间。沟道1111以及两个过渡部1113均与遮光图案12重叠，以使遮光图案12对入射至沟道1111以及两个过渡部1113的光起到遮光作用。
需要说明的是，沟道1111没有掺杂离子，两个接触部1112以及两个过渡部1113均掺杂有离子，两个过渡部1113的离子掺杂浓度低于两个接触部1112的离子掺杂浓度。
在本实施例中，结晶有源图案111还包括至少一个凹槽111a，至少一个凹槽111a位于两个接触部1112中的至少一个上，至少一个凹槽111a位于接触部1112远离基板10的一侧，至少一个凹槽111a在结晶有源图案111的厚度方向上延伸，至少一个凹槽111a的深度小于或等于结晶有源图案111的厚度。
可以理解的是，至少一个凹槽111a可以设置于一个接触部1112上，也可以设置于两个接触部1112上。每个接触部1112上可以设置一个、两个或者两个以上凹槽111a。凹槽111a的深度可以等于结晶有源图案111的厚度，凹槽111a的深度也可以小于结晶有源图案111的厚度。
在本实施例中，至少一个凹槽111a位于至少一个接触部1112靠近沟道1111的位置，换言之，至少一个凹槽111a位于接触部1112的部分位置，且至少一个凹槽111a靠近过渡部1113设置。
本申请实施例结晶有源图案的凹槽的设计，使得结晶之前的结晶有源图案上具有突变点，该突变点更容易产生形成籽晶，进而使得凹槽在结晶以形成结晶有源图案的过程中起到晶粒定位的作用，凹槽靠近过渡部设置，有利于籽晶横向向结晶之前的过渡部和沟道生长。
具体地，如图1和图2所示，一个凹槽111a位于一个接触部1112靠近沟道1111的位置，凹槽111a的深度等于结晶有源图案111的厚度，即凹槽111a为靠近沟道1111设置的通孔。而且，一个凹槽111a在基板10上的正投影位于一个接触部1112在基板10上的正投影内，一个凹槽111a在基板10上的正投影的面积小于一个接触部1112在基板10上的正投影的面积，凹槽111a没有将接触部1112断开成分割的两部分。
在本申请另一实施例中，如图4和图5所示，图4为本申请另一实施例阵列基板的截面示意图，图5为图4中结晶有源图案的平面示意图。两个凹槽111a分别位于两个接触部1112靠近沟道1111的位置，两个凹槽111a对称地设置于沟道1111的相对两侧，且两个凹槽111a的深度小于结晶有源图案111的厚度。
在本实施例中，凹槽111a沿结晶有源图案111的厚度方向上的截面的形状可以为矩形、梯形或者其他形状。凹槽111a沿垂直于结晶有源图案111的厚度的方向上的截面的形状可以为矩形、圆形或者其他形状。
在本实施例中，保温层115起到保温作用，以减小散热速率。保温层115与沟道1111接触。保温层115位于结晶有源图案111远离基板10的表面上，但不限于此，保温层115也可以位于结晶有源图案111与缓冲层13之间且与结晶有源图案111靠近基板10的表面接触。
保温层115的厚度大于或等于100埃且小于或等于1000埃，例如为200埃、300埃、400埃、600埃、800埃或者1000埃。保温层115的制备材料包括但不限于氧化硅。
保温层115与沟道1111以及两个过渡部1113接触，保温层115不与两个接触部1112接触，以降低结晶之前的沟道1111以及两个过渡部1113在激光退火之后的散热速率，有利于沟道1111以及两个过渡部1113中形成大尺寸的晶粒。
在形成结晶有源图案的过程中，采用激光对非晶有源图案进行退火结晶处理后，保温层对晶化之前的沟道以及两个过渡部进行保温，非晶有源图案中待形成沟道以及两个过渡部的部分的散热变慢，配合在凹槽处产生的籽晶沿着非晶有源图案中待形成沟道以及两个过渡部的部分横向生长，进而使沟道以及两个过渡部中形成大尺寸晶粒。
在本实施例中，保温层115的折射率为n，保温层115的厚度为d，激光的波长为λ，n、d以及λ满足如下公式：2d×n=k×λ，其中，k为大于或等于1的整数，激光的波长λ大于或等于180纳米且小于或等于420纳米的激光。
其中，激光的波长λ可以为305纳米至310纳米，例如激光为由XeCl准分子激光器发出的波长λ为308纳米的激光。可以理解的是，激光的波长λ可以为185纳米至200纳米，例如，激光也可以为由ArF准分子激光器发出的波长为193纳米的激光；或者，光的波长λ可以为230纳米至250纳米，例如激光也可以为由KrF准分子激光器发出的波长为248纳米的激光。
保温层115的制备材料为氧化硅时，保温层115的折射率为1.6。k的取值可以为2，3，4，5或者6。
本申请实施例保温层的厚度d=kλ/（2n），使保温层在波长为λ的激光对非晶有源图案进行退火结晶过程中对激光起到抗反射作用，更多激光穿过保温层，保温层下方的非晶有源图案获得更多的激光能量，保温层下方的非晶有源图案中趋向于形成更大尺寸的晶粒，对应的，沟道以及两个过渡部中形成更大尺寸的晶粒，有利于提高薄膜晶体管的迁移率，进而有利于实现集成芯片集成在绝缘基板上。
在本实施例中，由于保温层和凹槽的相互配合作用，使得结晶有源图案111中包括尺寸大于或等于300纳米的晶粒，例如尺寸为320纳米、330纳米、345纳米、350纳米、360纳米、370纳米、380纳米、390纳米或者400纳米的晶粒。
在本实施例中，栅极112位于保温层115远离基板10的一侧，换言之，薄膜晶体管11为顶栅薄膜晶体管。可以理解的是，栅极112也可以位于结晶有源图案111与缓冲层13之间，换言之，薄膜晶体管11为底栅薄膜晶体管。栅极112对应沟道1111设置。栅极112的制备材料包括但不限于钼、铝、钛、铜以及银中的至少一种。
在本实施例中，栅极绝缘层113设置于栅极112与保温层115之间。栅极绝缘层113的制备材料包括但不限于氮化硅和氧化硅中的至少一种。栅极绝缘层113的厚度大于或等于500埃且小于或等于1500埃，例如为800埃、1000埃、1200埃、1300埃或者1500埃。
在本实施例中，栅极112位于结晶有源图案111与源极1161和漏极1162之间，源极1161和漏极1162同层设置，源极1161和漏极1162分别与两个接触部1112连接。源极1161和漏极1162的制备材料包括但不限于钼、铝、钛、铜以及银中的至少一种。
在本实施例中，层间绝缘层114位于结晶有源图案111与源极1161和漏极1162之间，且层间绝缘层114位于栅极112与源极1161和漏极1162之间。层间绝缘层114的制备材料包括但不限于氮化硅和氧化硅中的至少一种。层间绝缘层114的厚度大于或等于5000埃且小于或等于6500埃，例如为5200埃、5400埃、5500埃、5600埃或者5800埃。
在本实施例中，阵列基板100还包括两个接触孔100a，两个接触孔100a分别对应两个接触部1112设置，两个接触孔100a贯穿层间绝缘层114和栅极绝缘层113，源极1161通过一个接触孔100a与一个接触部1112接触，漏极1162通过另一个接触孔100a与另一个接触部1112接触。
可以理解的是，薄膜晶体管11为底栅薄膜晶体管时，两个接触孔100a只需要贯穿层间绝缘层114。
两个接触孔100a中的至少一者与至少一个凹槽111a重叠。具体地，在一个接触部1112上设置有一个凹槽111a的情况下，一个接触孔100a与一个凹槽111a重叠，源极1161和漏极1162中的一者通过一个接触孔100a和凹槽111a与一个接触部1112接触，使源极1161和漏极1162中的一者与接触部1112之间形成环接触；源极1161和漏极1162中的另一者通过另一个接触孔100a与另一个接触部1112远离基板10的表面接触。
可以理解的是，在两个接触部1112上均分别设置有一个凹槽111a的情况下，也可以两个接触孔100a与两个凹槽111a一一对应重叠，源极1161通过一个接触孔100a和一个凹槽111a与一个接触部1112之间形成环接触，漏极1162通过另一个接触孔100a和另一个凹槽111a与另一个接触部1112之间形成环接触。
在凹槽111a位于接触部1112的部分位置的情况下，接触孔100a的孔径R大于凹槽111a的开口尺寸L，以形成接触孔100a过程中能蚀刻掉位于凹槽111a中的栅极绝缘层，实现接触孔100a与凹槽111a之间的连通，进而实现源极1161和漏极1162中的一者与一个接触部1112的连接。
可以理解的是，两个接触孔100a也可以均不与凹槽111a重叠，凹槽111a位于接触部1112的部分位置，源极1161和漏极1162通过两个接触孔100a与接触部1112除凹槽111a之外的部分接触。
请参阅图6，其为本申请又一实施例阵列基板的截面示意图。本实施例阵列基板与图4所示阵列基板基本相似，相同之处不再赘述，不同之处包括，凹槽111a的深度小于结晶有源图案111的厚度，且一个接触部1112上的凹槽111a与接触部1112完全重叠，对应的，至少一个接触部1112与过渡部1113之间形成台阶。
在本实施例中，一个凹槽111a在基板10上的正投影与一个接触部1112在基板10上的正投影完全重合，对应的，一个凹槽111a在基板10上的正投影的面积与一个接触部1112在基板10上的正投影的面积相等。因此，凹槽111a是在结晶有源图案111的厚度方向上对接触部1112进行薄化而形成。
另外，本申请还提供一种阵列基板的制造方法，阵列基板的制造方法包括如下步骤：
如图7A所示，采用第一次构图工艺对遮光金属层进行图案化处理得到位于基板10上的遮光图案12，形成覆盖遮光图案12和基板10的缓冲层13。
如图7B、图7C以及图7D所示，于缓冲层13上形成整面的非晶硅半导体层14和整面的保温膜115a，采用第二次构图工艺对保温膜115a进行图案化处理得到保温层115；再采用第三次构图工艺对非晶硅半导体层14进行图案化处理得到非晶硅半导体图案141，非晶硅半导体图案141具有沟道区141a、两个接触区141b以及两个过渡区141c，两个接触区141b在垂直于非晶硅半导体图案141的厚度的方向上分别位于沟道区141a的相对两侧，一个过渡区141c连接于沟道区141a与一个接触区141b之间，保温层115与非晶硅半导体图案141的两个过渡区141c和沟道区141a重叠，遮光图案12与非晶硅半导体图案141的两个过渡区141c和沟道区141a重叠，非晶硅半导体图案141包括凹槽111a，凹槽111a位于一个接触区141b的部分位置且靠近过渡区141c设置，凹槽111a的深度等于非晶硅半导体图案141的厚度。
如图7E和图7F所示，采用XeCl准分子激光器发出的波长λ为308纳米的激光L对非晶硅半导体图案141进行退火处理，得到多晶硅半导体图案142。其中，激光进行退火处理时，在凹槽111a处容易形成籽晶1411，位于两个过渡区141c和沟道区141a的非晶硅半导体图案141在保温层115的作用下散热较慢，籽晶1411向过渡区141c和沟道区141a横向生长，使得过渡区141c和沟道区141a容易形成大尺寸晶粒。
另外，保温层115的折射率n、保温层115的厚度d以及激光的波长λ满足公式2d×n=k×λ时，k为大于或等于1的整数，保温层115在激光对非晶硅半导体图案141进行退火结晶过程中对激光起到抗反射作用，更多激光穿过保温层115，保温层115下方的非晶硅半导体图案141获得更多的激光能量，保温层115下方的非晶硅半导体图案141中趋向于形成更大尺寸的晶粒，对应的，过渡区141c和沟道区141a中进一步地形成更大尺寸的晶粒。
如图7G所示，采用重离子掺杂工艺对多晶硅半导体图案142的两个接触区141b进行处理，得到重掺杂多晶硅半导体图案143，重掺杂多晶硅半导体图案143包括位于两个接触区141b的接触部1112。
如图7H所示，形成覆盖重掺杂多晶硅半导体图案143和缓冲层13的栅极绝缘层113，且于栅极绝缘层113上通过第四次构图工艺对栅极金属层进行图案化处理以得到栅极112，栅极112对应沟道区141a设置，以栅极112作为掩模且采用轻离子掺杂工艺对两个过渡区141c进行处理，得到结晶有源图案111，结晶有源图案111包括位于沟道区141a的沟道1111和位于两个过渡区141c的过渡部1113，一个过渡部1113连接于一个接触部1112与沟道1111之间。
如图7I所示，形成覆盖栅极112和栅极绝缘层113的层间绝缘层114，采用第五次构图工艺对层间绝缘层114和栅极绝缘层113进行图案化处理，得到两个接触孔100a，两个接触孔100a均对应两个接触部1112设置，且两个接触孔100a中的一个接触孔100a与凹槽111a连通。
如图7J所示，于层间绝缘层114远离栅极绝缘层113的表面上、两个接触孔100a以及凹槽111a中形成源漏电极金属层，采用第六次构图工艺对源漏电极金属层进行图案化处理得到源极1161和漏极1162，源极1161通过一个接触孔100a和凹槽111a与一个接触部1112形成环形接触，漏极1162通过另一个接触孔100a与另一个接触部1112接触。
本申请实施例阵列基板的制造方法通过非晶硅半导体图案的两个接触区的至少一者设置凹槽，有利于在非晶硅半导体图案晶化以形成结晶有源图案过程中在凹槽处形成籽晶，籽晶向过渡区和沟道区生长，配合保温层使过渡区和沟道区的非晶硅半导体图案散热较慢，以使过渡区和沟道区中形成大尺寸晶粒，减少结晶有源图案的沟道中的晶界，进而提高薄膜晶体管的迁移率。
本申请还提供一种电子器件200，电子器件200为显示面板，电子器件200可以为液晶显示面板、有机发光二极管显示面板、量子点发光二极管显示面板、次毫米发光二极管显示面板、微米发光二极管显示面板中的至少一种。
具体地，如图8所示，其为本申请一实施例电子器件的截面示意图。电子器件200包括阵列基板100、彩膜基板300以及位于阵列基板100和彩膜基板300之间的液晶层（未示意出），阵列基板100与上述图1和图2所示阵列基板100基本相似，相同之处不再赘述，不同之处包括，阵列基板100还包括平坦化层15、公共电极16、钝化层17以及像素电极18。
其中，平坦化层15覆盖层间绝缘层114、源极1161和漏极1162，公共电极16设置于平坦化层15上，钝化层17覆盖公共电极16和平坦化层15，像素电极18设置于钝化层17上，像素电极18通过贯穿钝化层17和平坦化层15的过孔与漏极1162连接。
本申请实施例电子器件通过结晶有源图案的两个接触部的至少一者上设置凹槽，有利于在结晶以形成结晶有源图案过程中凹槽处形成籽晶，籽晶向靠近晶化前的沟道生长，配合保温层使晶化前的沟道散热较慢，以使沟道中形成大尺寸晶粒，减少结晶有源图案的沟道中的晶界，进而提高薄膜晶体管的迁移率，有利于实现集成芯片集成在电子器件的绝缘基板上，降低电子器件的成本。
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种薄膜晶体管，其中，所述薄膜晶体管包括：
    结晶有源图案，所述结晶有源图案包括：
    沟道；
    两个接触部，在与所述结晶有源图案的厚度方向相交的方向上，两个所述接触部连接于所述沟道的相对两侧；以及
    至少一个凹槽，位于两个所述接触部中的至少一个上，且在所述结晶有源图案的厚度方向上延伸；
    源极和漏极，分别与两个所述接触部连接；以及
    保温层，所述保温层与所述沟道接触。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述结晶有源图案还包括两个过渡部，一个所述过渡部连接于一个所述接触部与所述沟道之间，所述保温层还与两个所述过渡部接触。
  3. 根据权利要求1所述的薄膜晶体管，其中，所述结晶有源图案包括尺寸大于或等于300纳米的晶粒。
  4. 根据权利要求1所述的薄膜晶体管，其中，所述保温层的折射率为n，所述保温层的厚度为d，所述n、所述d以及激光的波长λ满足如下公式：
    2d×n=k×λ，其中，所述k为大于或等于1的整数，所述激光的波长λ大于或等于180纳米且小于或等于420纳米。
  5. 根据权利要求1所述的薄膜晶体管，其中，所述保温层的厚度大于或等于100埃且小于或等于1000埃。
  6. 根据权利要求1所述的薄膜晶体管，其中，所述凹槽的深度小于或等于所述结晶有源图案的厚度，所述凹槽位于至少一个所述接触部靠近所述沟道的位置。
  7. 根据权利要求1所述的薄膜晶体管，其中，所述凹槽的深度小于所述结晶有源图案的厚度，一个所述接触部上的所述凹槽与所述接触部完全重叠。
  8. 根据权利要求1所述的薄膜晶体管，其中，所述薄膜晶体管还包括：
    栅极，对应所述沟道设置；
    栅极绝缘层，位于所述栅极与所述结晶有源图案之间；
    层间绝缘层，位于所述结晶有源图案与所述源极和所述漏极之间；
    两个接触孔，至少贯穿所述层间绝缘层，所述源极和所述漏极分别通过两个所述接触孔与两个所述接触部连接。
  9. 根据权利要求8所述的薄膜晶体管，其中，所述栅极位于所述结晶有源图案与所述源极和漏极之间，所述层间绝缘层位于所述栅极与所述源极和所述漏极之间；
    两个所述接触孔还贯穿所述栅极绝缘层，两个所述接触孔中的至少一者与所述凹槽重叠，所述接触孔的孔径大于所述凹槽的开口尺寸。
  10. 根据权利要求1所述的薄膜晶体管，其中，所述结晶有源图案为低温多晶硅有源图案。
  11. 一种电子器件，其中，所述电子器件包括薄膜晶体管，所述薄膜晶体管包括：
    结晶有源图案，所述结晶有源图案包括：
    沟道；
    两个接触部，在与所述结晶有源图案的厚度方向相交的方向上，两个所述接触部连接于所述沟道的相对两侧；以及
    至少一个凹槽，位于两个所述接触部中的至少一个上，且在所述结晶有源图案的厚度方向上延伸；
    源极和漏极，分别与两个所述接触部连接；以及
    保温层，所述保温层与所述沟道接触。
  12. 根据权利要求11所述的电子器件，其中，所述结晶有源图案还包括两个过渡部，一个所述过渡部连接于一个所述接触部与所述沟道之间，所述保温层还与两个所述过渡部接触。
  13. 根据权利要求11所述的电子器件，其中，所述结晶有源图案包括尺寸大于或等于300纳米的晶粒。
  14. 根据权利要求11所述的电子器件，其中，所述保温层的折射率为n，所述保温层的厚度为d，所述n、所述d以及激光的波长λ满足如下公式：
    2d×n=k×λ，其中，所述k为大于或等于1的整数，所述激光的波长λ大于或等于180纳米且小于或等于420纳米。
  15. 根据权利要求11所述的电子器件，其中，所述保温层的厚度大于或等于100埃且小于或等于1000埃。
  16. 根据权利要求11所述的电子器件，其中，所述凹槽的深度小于或等于所述结晶有源图案的厚度，所述凹槽位于至少一个所述接触部靠近所述沟道的位置。
  17. 根据权利要求11所述的电子器件，其中，所述凹槽的深度小于所述结晶有源图案的厚度，一个所述接触部上的所述凹槽与所述接触部完全重叠。
  18. 根据权利要求11所述的电子器件，其中，所述薄膜晶体管还包括：
    栅极，对应所述沟道设置；
    栅极绝缘层，位于所述栅极与所述结晶有源图案之间；
    层间绝缘层，位于所述结晶有源图案与所述源极和所述漏极之间；
    两个接触孔，至少贯穿所述层间绝缘层，所述源极和所述漏极分别通过两个所述接触孔与两个所述接触部连接。
  19. 根据权利要求18所述的电子器件，其中，所述栅极位于所述结晶有源图案与所述源极和漏极之间，所述层间绝缘层位于所述栅极与所述源极和所述漏极之间；
    两个所述接触孔还贯穿所述栅极绝缘层，两个所述接触孔中的至少一者与所述凹槽重叠，所述接触孔的孔径大于所述凹槽的开口尺寸。
  20. 根据权利要求11所述的电子器件，其中，所述结晶有源图案为低温多晶硅有源图案。
PCT/CN2022/115992 2022-08-10 2022-08-30 薄膜晶体管及电子器件 WO2024031756A1 (zh)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005285826A (ja) * 2004-03-26 2005-10-13 Advanced Lcd Technologies Development Center Co Ltd 半導体薄膜の結晶化方法並びに結晶化装置、薄膜トランジスタ、およびこの薄膜トランジスタを使用した表示装置
CN1719615A (zh) * 2004-07-07 2006-01-11 三星Sdi株式会社 薄膜晶体管及其制造方法
CN105097550A (zh) * 2015-08-04 2015-11-25 深圳市华星光电技术有限公司 低温多晶硅薄膜晶体管的制作方法及低温多晶硅薄膜晶体管
CN110534528A (zh) * 2018-05-25 2019-12-03 乐金显示有限公司 Tft基板和包括该tft基板的显示装置
CN112687703A (zh) * 2020-12-24 2021-04-20 武汉华星光电半导体显示技术有限公司 显示面板
CN113823561A (zh) * 2020-06-18 2021-12-21 上海华力集成电路制造有限公司 半导体器件外延工艺及包括其形成的外延层的半导体器件

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005285826A (ja) * 2004-03-26 2005-10-13 Advanced Lcd Technologies Development Center Co Ltd 半導体薄膜の結晶化方法並びに結晶化装置、薄膜トランジスタ、およびこの薄膜トランジスタを使用した表示装置
CN1719615A (zh) * 2004-07-07 2006-01-11 三星Sdi株式会社 薄膜晶体管及其制造方法
CN105097550A (zh) * 2015-08-04 2015-11-25 深圳市华星光电技术有限公司 低温多晶硅薄膜晶体管的制作方法及低温多晶硅薄膜晶体管
CN110534528A (zh) * 2018-05-25 2019-12-03 乐金显示有限公司 Tft基板和包括该tft基板的显示装置
CN113823561A (zh) * 2020-06-18 2021-12-21 上海华力集成电路制造有限公司 半导体器件外延工艺及包括其形成的外延层的半导体器件
CN112687703A (zh) * 2020-12-24 2021-04-20 武汉华星光电半导体显示技术有限公司 显示面板

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