WO2024027110A1 - 一种2.5d chiplet绑定后测试电路及测试方法 - Google Patents

一种2.5d chiplet绑定后测试电路及测试方法 Download PDF

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WO2024027110A1
WO2024027110A1 PCT/CN2023/071577 CN2023071577W WO2024027110A1 WO 2024027110 A1 WO2024027110 A1 WO 2024027110A1 CN 2023071577 W CN2023071577 W CN 2023071577W WO 2024027110 A1 WO2024027110 A1 WO 2024027110A1
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test
output
signal
chip
register
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PCT/CN2023/071577
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English (en)
French (fr)
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蔡志匡
周国鹏
沈海军
徐彬彬
姚佳飞
王恒鹭
谢祖帅
肖建
王子轩
郭宇锋
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南京邮电大学
南京邮电大学南通研究院有限公司
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Publication of WO2024027110A1 publication Critical patent/WO2024027110A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process

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  • the invention relates to the field of chiplet testability design circuits, and in particular discloses a 2.5D chiplet post-binding test circuit, which belongs to the technical field of testing or measurement of semiconductor devices during manufacturing or processing.
  • Chiplet technology as a solution is the most prominent in the post-Moore era.
  • a Chiplet's on-chip network communication architecture is established based on the development of a variety of chips with a single specific function that can be modularly assembled with each other.
  • all components are bound through advanced packaging technologies such as system-level packaging. into a system-level chip.
  • Chiplet is limited by the number of pins and has a complex stacking structure, how to solve the problem of the chip after being bound to the interposer through only a set of JTAG external test ports on the interposer while satisfying the above constraints? The test has become the difficulty of chiplet testing.
  • CHIPS Common Heterogeneous Integration and IP Reuse Strategies
  • the present invention aims to propose a technical solution for implementing parallel testing of multiple chips or Chiplets through a set of JTAG ports to overcome the shortcomings of the existing parallel testing technology after multiple Chiplets are bound.
  • the purpose of the invention is to address the deficiencies of the above background technology and provide a 2.5D Chiplet post-binding test circuit based on the test structure of IEEE 1687 to achieve reliable parallel testing of multiple Chiplets through a set of JTAG ports or designated individual
  • the purpose of the invention of the test is to solve the technical problems that the existing parallel testing technology after binding multiple Chiplets is inflexible and the parallel testing solution after binding multiple Chiplets in the master-slave architecture cannot reliably test each Chiplet.
  • the invention proposes a 2.5D Chiplet post-binding test circuit, which includes an interposer dedicated TAP controller, an interposer test interface circuit and a core chip test output control circuit.
  • the interposer-specific TAP controller adds a core chip test configuration register based on the traditional TAP controller.
  • the core chip test configuration register outputs the control signal SEL_B, and an additional 1-bit hold signal Keep is designed to synchronize the control signal in the chip. Remains unchanged on reset.
  • the STACK instruction is also defined in the interposer-specific TAP controller.
  • the instruction register of the interposer-dedicated TAP controller receives the STACK instruction value in the configuration vector from the chip JTAG port. After decoding, the core chip test configuration register is connected to the interposer.
  • the configuration vector written into the core chip test configuration register from the TDI port is used to determine the core chip under test and the test output signal for performing parallel testing. Output the sequence control signal SEL_B.
  • the interposer test interface circuit includes multiple logic gates and registers, connecting the tdi, tms, tck, trst and tdo ports of each chip with the corresponding tdi_b, tms_b, tck_b, trst_b and tdo_b ports in the test interface circuit to form an intermediary The test path between the layer and the core chip, and then use the SEL_B signal to select the opening or closing of each test path.
  • the interposer test interface circuit receives the test vector from the chip's JTAG port in real time.
  • test data input port and test clock signal input of the core under test that performs parallel testing.
  • test mode selection signal input port, test reset signal input port, test data output port, and test each core under test generated based on the control signal output by the dedicated TAP controller of the interposer and the test clock input signal from the chip JTAG port.
  • the clock signal is transmitted to the test clock signal input port of each core under test.
  • the test mode selection signal of each core under test is generated based on the control signal output by the dedicated TAP controller of the interposer and the test mode selection signal from the JTAG port of the chip.
  • test mode selection signal input port of each tested core particle, and the test data input signal of each tested core particle moved in according to the test clock signal of each tested core particle is transmitted to the test data input signal input port of each tested core particle.
  • the chip test output control circuit includes multiple data selectors, logic gates and register groups. It receives the control signal output by the special TAP controller of the intermediary layer and uses the SEL_B signal to sequentially transmit the test output signal of each tested chip to the chip JTAG. port.
  • the core chip test output control circuit introduces the test output enable signal generated by the TAP controller to capture the effective test output results of the core chips that are being tested but have not been selected to be output through the test data output port during multi-core chip parallel testing, and store them in the core chip.
  • the data stored in the register group of the chip test results will be output after the output of the chip selected to output the test result through the test data output port is completed.
  • the present invention provides a 2.5D Chiplet post-binding test circuit.
  • the proposed test circuit meets the post-binding test requirements of the core particles in the 2.5D Chiplet and solves the control problem of the post-bind test of the core particles across the interposer layer.
  • the STACK instruction in the TAP controller By configuring the STACK instruction in the TAP controller and selecting to access the core chip test configuration register according to the STACK instruction, and then generating a control signal indicating the parallel test chip information and the test output signal output sequence, a single core chip can be selected for binding.
  • multiple cores can also be flexibly selected for parallel testing, which greatly shortens the testing time.
  • the parallel testing scheme of master-slave testing is abandoned, which effectively improves the reliability of parallel testing.
  • the 2.5D Chiplet binding test circuit proposed by this invention does not need to modify the original test structure of the chip. It uses a set of general JTAG ports on the interposer layer as external test ports and communicates with each chip through the interposer interface circuit. By connecting the universal JTAG port between each other, you can configure the test vector for each tested chip and transmit the test output signal of each tested chip to the external test port, and use a set of JTAG ports on the bound test circuit to implement the specified
  • the scheme of single core particle testing or multiple core particle parallel testing is versatile and easy to use and promote.
  • Figure 1 is a structural block diagram of a 2.5D Chiplet bound test circuit of the present invention.
  • FIG 2 is a specific structural diagram of the intermediary dedicated TAP controller shown in Figure 1.
  • Figure 3 is a specific structural diagram of the chip test configuration register shown in Figure 2.
  • FIG. 4 is a specific structural diagram of the interposer test interface circuit shown in FIG. 1 .
  • Figure 5 is a specific structural diagram of the core particle test output control circuit shown in Figure 1.
  • Figure 6 is a schematic diagram of the overall circuit structure of a 2.5D Chiplet bound test circuit in an embodiment of the present invention.
  • Figure 7 is a test flow chart of a test circuit after 2.5D Chiplet is bound in the embodiment of the present invention.
  • Figure 8 is a simulation waveform diagram of a parallel test chip of a 2.5D Chiplet bound test circuit in the embodiment of the present invention.
  • 201 to 221 are the first to twenty-first data selectors
  • 222 is the first AND gate
  • 223 is the first OR gate
  • 301 is the three AND gates
  • 302 is the three data selectors
  • 303 It is three registers
  • 401 ⁇ 402 is the first and second 3-to-2 data selector
  • 403 is a 6-to-1 data selector
  • 404 ⁇ 405 is the second and third AND gate
  • 406 is an inverter
  • 407 ⁇ 408 is the first and second register group.
  • the main design idea of a 2.5D chiplet bound test circuit in the embodiment of the present invention is to perform testability design on the interposer layer, insert the test circuit, input the test vector, and realize the parallel memory after multiple core chips are bound. Build self-test.
  • the corresponding structural block diagram is shown in Figure 1.
  • the test circuit of this embodiment includes a dedicated TAP controller for the interposer, an interposer test interface circuit and a die test output control circuit. First, input the configuration vector to the dedicated TAP controller of the interposer through the four external test ports of the test data input port TDI, test clock signal input port TCK, test mode selection signal input port TMS and test reset signal input port TRST on the interposer layer.
  • set the value of the SEL_B signal set the value of the SEL_B signal.
  • the interposer test interface circuit is used to provide tdi_b, tck_b, tms_b, trst_b, tdo_b ports, and control the SEL_B signal.
  • the tdi_b, tck_b, tms_b, trst_b, tdo_b ports provided by the interposer test interface circuit are connected to the test port of the selected core chip to be tested, and the core chip to be tested is generated based on SEL_B and the test vector received from the external test port.
  • the interposer test interface circuit transmits the test vector of the core to be tested to the test port corresponding to the core to be tested, and the core to be tested performs the test after receiving the test vector. Finally, the test results of the core particles enter the interposer test interface circuit through the tdo_b port, and then are transmitted to the core particle test output control circuit.
  • the core particle test output control circuit selects the test results of the corresponding core particles to be output to the outside under the control of the SEL_B signal.
  • the test data output port TDO The test data output port TDO.
  • FIG. 2 is a more detailed diagram of the interposer-specific TAP controller in Figure 1.
  • the interposer-specific TAP controller includes a finite state machine (FSM), an instruction register module, a data register module, and some combinational logic gates.
  • a new instruction named STACK is defined in the instruction register module, which is used to selectively access the newly added core chip test configuration register in the data register module.
  • the core chip test configuration register outputs the SEL_B signal, which is the SEL_B shown in Figure 1.
  • the signal provides control signals for the interposer test interface circuit and the chip test output control circuit.
  • the defined value of the STACK instruction is serially moved from the TDI to the instruction register module. After being processed by the instruction decoder, the STACK instruction that selects to access the core chip test configuration register is obtained.
  • the chip test configuration register When the STACK instruction is high level, the chip test configuration register is accessed. On the effective path between the test data input port and the test data output port of the intermediary dedicated TAP controller, the data stored in the core chip test configuration register (that is, the data so stored in the core chip test configuration register in Figure 3) is output to tdo_tap for TDO port.
  • the boundary scan register, bypass register, or instruction register When the boundary scan register, bypass register, or instruction register is connected to the effective path between the test data input port and the test data output of the interposer dedicated TAP controller, the data stored in the boundary scan register, bypass register, or instruction register is used as a transmission tdo_tap to TDO port.
  • Figure 3 is a more detailed diagram of the chip test configuration register in Figure 2, including the first to fourteenth registers 201 to 214, the fifteenth to twenty-first data selectors 215 to 221, and the first AND gate 222 and the first OR gate 223.
  • the clock terminals of the first to seventh registers 201 to 207 are connected to the tck signal input from the test clock signal input port TCK, and the fifteenth to twenty-first data selectors 215 to 221 are enabled in the data register shift generated by the FSM.
  • the signal shift_dr is 1, the test data input signal tdi is moved into the first to seventh registers 201 to 207 at the rising edge of tck.
  • the test data input signal tdi is shifted by the first to seventh registers 201 to 207 Output the data so stored in the chip test configuration register.
  • shift_dr is 0, the output values of the first to seventh registers 201 to 207 are fed back to the fifteenth to twenty-first data selectors 215 to 21 connected to their respective input terminals. 221.
  • the STACK signal and the data register update enable signal update_dr generated by the FSM are sent to the first AND gate 222, and the output of the first AND gate 222 terminal is connected to the clock terminal of the eighth to fourteenth registers 208 to 214.
  • the eighth register 208 When the output of the first AND gate 222 is flipped and at the falling edge of tck, the outputs of the first to seventh registers 201 to 207 are respectively moved into the eighth register.
  • the eighth register 208 outputs the Keep signal
  • the ninth to fourteenth registers 209 to 214 output the 6-bit SEL_B[5:0] signal.
  • the output of the first AND gate 222 When there is no flipping, the outputs of the eighth to fourteenth registers 208 to 214 remain unchanged.
  • the reset terminal of the eighth register 208 receives the asynchronous reset signal trst from the external TRST port.
  • the output signal Keep of the eighth register 208 and the synchronous reset signal reset from the FSM are sent to the first OR gate 223, and the output of the first OR gate 223 is connected.
  • the SEL_B signal remains unchanged except when the asynchronous reset trst signal is valid. On the contrary, when it is 0, the SEL_B signal remains unchanged. The signal is reset to the initial value 0 after the FSM enters the Test-Logic-Reset state (that is, the reset signal is low and active).
  • FIG 4 is a more detailed diagram of the interposer test interface circuit in Figure 1.
  • the interposer test interface circuit includes three AND gates 301, three data selectors 302 and three registers 303.
  • tdi_b in the interposer test interface circuit tck_b, tms_b, trst_b and tdo_b ports are respectively connected to the tdi, tck, tms, trst and tdo ports of the core on the interposer.
  • SEL_B[5], SEL_B[4] and SEL_B[3] in the SEL_B[5:3] signal are connected to two of the three AND gates 301 with the tck signal respectively.
  • three signals tck_b[2], tck_b[1] and tck_b[0] are output to the tck_b port.
  • the tms signal and the fixed value 1 are both connected to the two data input terminals of the three data selectors 302.
  • the data selection terminals of the three data selectors 302 are respectively 3-bit wide SEL_B[5:3] signals.
  • SEL_B When 1, the tms signal is directly input to the tms_b port.
  • the signal corresponding to the test core is not selected to be 1, that is, the output signal of the tms_b port is 1, preventing the FSM from being used when the tck_b signal is not turned off. Enter Test_Logic_Reset state to maintain synchronous reset.
  • FIG. 5 is a more detailed diagram of the die test output control circuit in Figure 1.
  • the die test output control circuit includes first and second 3-to-2 data selectors 401 and 402, and a 6-to-1 data selector 403. , second and third AND gates 404 and 405, an inverter 406, and first and second register sets 407 and 408. Since there is only one external test output port on the interposer, in order to meet the needs of multi-core parallel testing, a core test output control circuit is designed.
  • the test output signals tdo_b[2], tdo_b[1] and tdo_b[0] of the tested core chip that performs parallel testing are connected to the three data input terminals of the first 3-select 2 data selector 401.
  • the value of the data selection signal SEL_B[5:0] on the data selector 401 (that is, the SEL_B[5:0] output by the chip test configuration register), outputs tdo_din[1] and tdo_din[0], which are the first and Second register set 407 and 408 provide data input signals.
  • the die test clock signals tck_b[2], tck_b[1] and tck_b[0] on the interposer test interface circuit are connected to the three data input terminals of the second 3-select-2 data selector 402.
  • the second 3-select Select the value of the data selection signal SEL_B[5:3] on the 2 data selector 402 (that is, the data in SEL_B indicating the information of the core under test that performs parallel testing), output two clock signals, and then connect them to the second and second clock signals respectively.
  • the test output enable signal tdo_en generated by the interposer dedicated TAP controller is connected to the other end of the second and third AND gates 404 and 405 through the output of the inverter 406. on the input side.
  • the output terminals of the second and third AND gates 404 and 405 are respectively connected to the clock terminals of the first and second register groups 407 and 408, which can realize the tdo output test that is being tested but has not been selected during multi-core parallel testing.
  • the valid output results of the resulting core are moved into the register set.
  • tdo_b[2], tdo_b[1], tdo_b[0], the test output tdo_tap of the interposer dedicated TAP controller, the output tdo_dout[1] of the first register group 407 and the output tdo_dout[0] of the second register group 408 are Six data input signals of the 6-to-1 data selector 403, the 6-to-1 data selector 403 is based on the value of the data selection signal SEL_B[2:0] (that is, the data representing the output sequence of the tested core particle test output signal in the parallel test ) outputs the tdo signal to the TDO external port on the interposer.
  • Figure 6 is a schematic diagram of the overall circuit structure of this embodiment, including three core chips and one interposer.
  • the core chip includes a testable design circuit that has been inserted before binding and cannot be changed.
  • the figure only shows the TAP controller and the test circuit.
  • the interposer includes a dedicated TAP controller for the interposer, an interposer test interface circuit and a chip test output control circuit.
  • the memory parallel built-in self-test is performed.
  • the overall 2.5D Chiplet circuit is powered on and reset.
  • the interposer and the three The test signal channel between the core particles is initially closed.
  • input the configuration vector to the interposer dedicated TAP controller enter the STACK command mode, assign values to the Keep and SEL_B signals, and open the test interface channel between the interposer and core 2, core 1, and core 0.
  • input the test vector of the core particle to start the built-in self-test of the core particle 2, core particle 1 and core particle 0.
  • the TDO port first outputs the test result of the core particle 2, and the test result of the core particle 1 is stored in the core particle test.
  • the test results of chip 0 are stored in the register group 0 in the chip test output control circuit.
  • the test output of core chip 2 has also ended.
  • Enter the configuration vector enter the STACK command mode, and reassign the SEL_B signal to output the register group 1 in the core chip test output control circuit.
  • the value is the effective test result of the output core 1.
  • This reassignment of the SEL_B signal changes the data value of the test output signal output sequence. It is necessary to reassign the data in the SEL_B signal that represents the execution of parallel test core information.
  • Figure 8 is a simulation waveform diagram of the parallel testing of core 2, core 1 and core 0 in Figure 6.
  • the waveform diagram in box (1) in Figure 8 corresponds to the power-on initialization reset and input configuration vector steps in Figure 6. It can be observed that the STACK command signal is pulled high, and the SEL_B[5:0] signal has been configured to 6' b111100 and remains unchanged.
  • the waveform diagram in box (2) in Figure 8 corresponds to the input core particle test vector and the test result step of output core particle 2 in Figure 6. It can be observed that the GO in core particle 2, core particle 1 and core particle 0 and DONE indication signals have all been pulled high (valid), so it is judged that the bound parallel memory built-in self-test of core 2, core 1 and core 0 has passed.
  • the waveform diagram in box (3) in Figure 8 corresponds to the test result step of re-inputting the configuration vector and outputting core 1 in Figure 6. It can be observed that the SEL_B[5:0] signal is reconfigured to 6'b010111, so that The value of register group 407 in the core chip test output control circuit is output from TDO, that is, the effective test result of core chip 1 is output.
  • the waveform diagram in box (4) in Figure 8 corresponds to the test result step of re-inputting the configuration vector and outputting core 0 in Figure 6.
  • the SEL_B[5:0] signal is reconfigured to 6'b001000, so that The value of the register group 408 in the core chip test output control circuit is output from TDO, that is, the effective test result of core chip 0 is output.
  • the value of the SEL_B signal can be customized through the above steps to achieve flexible selection of core particles for post-binding testing.
  • select n chips as the objects of parallel testing and the SEL_B signal can be expressed as SEL_B[2n-1:0], where n bits The data is used to represent the information of the tested core chips that perform parallel testing, and the remaining n-bit data is used to represent the output sequence of the test output signals of the tested core chips that perform parallel testing; when 2 ⁇ n ⁇ N, the SEL_B signal represents the response to N Any n cores among the cores are tested in parallel.
  • the n tested cores receive the test vectors of each tested core generated by the interposer test interface circuit and perform built-in self-test at the same time.
  • One core chip in the chip is subjected to a separate designated test, making the multi-chiplet parallel testing solution proposed in this application more flexible.
  • the assignment of the SEL_B signal also has a certain degree of flexibility.
  • the data in the SEL_B signal that represents the information about the core particle under test can be assigned any value.

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Abstract

本发明公开一种2.5D Chiplet绑定后测试电路，属于半导体器件在制造或处理过程中的测试或测量的技术领域。该绑定后测试电路包括中介层专用TAP控制器、中介层测试接口电路和芯粒测试输出控制电路。中介层专用TAP控制器新增芯粒测试配置寄存器及其对应指令。中介层测试接口电路利用芯粒测试配置寄存器输出控制信号选择中介层和芯粒之间测试信号通道的开启或关闭。芯粒测试输出控制电路利用芯粒测试配置寄存器输出控制信号控制中介层上芯粒的测试数据输出。本发明满足2.5D芯粒的绑定后测试要求，可以自定义地选择单个或多个芯粒进行绑定后测试，不需修改芯粒原始的测试结构，通过中介层上的一组通用JTAG端口即可实现。

Description

一种2.5D CHIPLET绑定后测试电路及测试方法 技术领域
本发明涉及Chiplet可测性设计电路领域，尤其公开一种2.5D Chiplet绑定后测试电路，属于半导体器件在制造或处理过程中的测试或测量的技术领域。
背景技术
在芯片集成度越来越高和制程节点越来越小的情况下，单纯靠工艺来提升芯片性能的方法已不能满足集成电路市场的需求，作为解决方案的Chiplet技术是后摩尔时代里最突出的先进芯片设计技术，基于开发出的多种具有单一特定功能、可相互进行模块化组装的芯粒，建立一个Chiplet的片上网络通信架构，最后通过系统级封装等先进封装技术将所有组件绑定成一个系统级的芯片。
Chiplet的设计复杂性和高集成度导致芯粒在制造和使用过程中产生缺陷和故障的概率大大升高，其中一个芯粒出现故障则会影响整体Chiplet电路的性能。而为提高Chiplet产品的上市速度，通常大多数芯粒都是直接购买第三方的IP产品，其中的测试硬件资源已完成且不可再改动。芯粒在绑定前，可以通过自身的测试端口访问各自的测试结构以进行测试。然而，由于Chiplet受到引脚数量的限制且具有复杂的堆叠结构，所以如何在满足上述约束条件的同时，仅通过中介层上的一组JTAG外部测试端口，解决芯粒在与中介层绑定后的测试成为了Chiplet测试的难点。
针对Chiplet中芯粒跨越中介层的绑定后测试难题，国外的通用异构集成及知识产权复用策略(Common Heterogeneous Integration and IP Reuse Strategies，CHIPS)项目已具有一定的技术成果，国内在控制多芯粒测试结构方面还较为欠缺，主要是对三维电路的硅通孔测试的研究较多。现业界主流的测试结构是基于IEEE 1687标准协议进行设计，因此，基于IEEE 1149.1标准协议的3D测试结构，需要对3D测试结构进行更改以使其与当前主流的测试结构相兼容。一种能够检测上、下芯粒的自动芯粒检测器电路，将自动芯粒检测器电路集成到基于IEEE 1149.1标准协议的3D测试结构里，该电路虽可节省芯粒在绑定后测试中的测试路径配置时间，但不能指定某个芯粒的测试，缺乏灵活性。一种在中介层上主芯粒控制其余芯粒的2.5D测试结构，实现了一对多的测试访问控制机制，但若指定的主芯粒损坏，就无法测试其它芯粒。综上，本发明旨在提出一种通过一组JTAG端口实现多芯片或Chiplet并行测试的技术方案以克服现有多Chiplet绑定后并行测试技术的缺陷。
发明内容
本发明的发明目的是针对上述背景技术的不足，基于IEEE 1687的测试结构，提供一种2.5D Chiplet绑定后测试电路，实现通过一组JTAG端口对多Chiplet进行可靠的并行测试或指定的单独测试的发明目的，解决现有多Chiplet绑定后并行测试技术不灵活以及主从架构的多Chiplet绑定后并行测试方案不能对每一个Chiplet进行可靠测试的技术问题。
本发明为实现上述发明目的采用如下技术方案：
本发明提出的一种2.5D Chiplet绑定后测试电路，包括中介层专用TAP控制器、中介层测试接口电路和芯粒测试输出控制电路。
中介层专用TAP控制器在传统的TAP控制器基础上新增了一个芯粒测试配置寄存器，该芯粒测试配置寄存器输出控制信号SEL_B，且额外设计1位保持信号Keep使控制信号在芯粒同步复位时保持不变。中介层专用TAP控制器中还定义了STACK指令，中介层专用TAP控制器的指令寄存器接收来自芯片JTAG端口的配置向量中的STACK指令值，经译码后将芯粒测试配置寄存器接入中介层专用TAP控制器的测试数据输入端口与测试数据输出端口之间有效路径上，根据从TDI端口写入芯粒测试配置寄存器的配置向量生成用于确定执行并行测试的被测芯粒以及测试输出信号输出顺序控制信号SEL_B。
中介层测试接口电路包括多个逻辑门和寄存器，把各个芯粒的tdi、tms、tck、trst和tdo端口与测试接口电路里对应的tdi_b、tms_b、tck_b、trst_b和tdo_b端口相连以形成在中介层和芯粒之间的测试路径，再利用SEL_B信号选择每条测试路径的开启或关闭。中介层测试接口电路实时接收来自芯片JTAG端口的测试向量，在接收到中介层专用TAP控制器输出的控制信号时，连接至执行并行测试的被测芯粒的测试数据输入端口、测试时钟信号输入端口、测试模式选择信号输入端口、测试复位信号输入端口、测试数据输出端口，根据中介层专用TAP控制器输出的控制信号及来自芯片JTAG端口的测试时钟输入信号生成的各被测芯粒的测试时钟信号传输至各被测芯粒测试时钟信号输入端口，根据中介层专用TAP控制器输出的控制信号及来自芯片JTAG端口的测试模式选择信号生成的各被测芯粒的测试模式选择信号传输至各被测芯粒的测试模式选择信号输入端口，根据各被测芯粒的测试时钟信号移入的各被测芯粒的测试数据输入信号传输至各被测芯粒的测试数据输入信号输入端口，传输来自芯片JTAG端口的测试复位信号至各被测芯粒的测试复位信号输入端口，传输各被测芯粒的测试输出信号至芯粒测试输出控制电路。
芯粒测试输出控制电路，包括多个数据选择器、逻辑门和寄存器组，接收中介层专用TAP控制器输出的控制信号，利用SEL_B信号按序传输各被测芯粒的测试输出信号至芯片JTAG端口。
芯粒测试输出控制电路引入TAP控制器产生的测试输出使能信号，为多芯粒并行测试时捕获正在测试但未被选择通过测试数据输出端口输出的芯粒有效测试输出结果，并存入芯粒测试输出控制电路里的寄存器组中，待被选择通过测试数据输出端口输出测试结果的芯粒输出结束后再输出已存入芯粒测试结果的寄存器组里的数据。
本发明采用上述技术方案，具有以下有益效果：
(1)本发明提供一种2.5D Chiplet绑定后测试电路，所提出的测试电路满足2.5D Chiplet中芯粒的绑定后测试要求，解决芯粒跨越中介层绑定后测试的控制问题，通过在TAP控制器中配置STACK指令并依据STACK指令选择访问芯粒测试配置寄存器，进而生成表示并行测试芯粒信息及测试输出信号输出顺序的控制信号，既可以选择单个芯粒进行绑定后的单独测试，也可以灵活选择多个芯粒进行并行测试，大大缩短测试时间，且因摒弃主从测试的并行测试方案，有效提高并行测试的可靠性。
(2)本发明提出的2.5D Chiplet绑定后测试电路，不需修改芯粒原始的测试结构，将中介层上的一组通用JTAG端口作为外部测试端口，通过中介层接口电路与各个芯粒之间的通用JTAG端口连接，即可为各被测芯粒配置测试向量并将各被测芯粒的测试输出信号传 输至外部测试端口，利用绑定后测试电路上的一组JTAG端口实现指定单个芯粒测试或多个芯粒并行测试的方案，具有通用性，便于使用和推广。
附图说明
图1是本发明的一种2.5D Chiplet绑定后测试电路的结构框图。
图2是图1中所示中介层专用TAP控制器的具体结构图。
图3是图2中所示芯粒测试配置寄存器的具体结构图。
图4是图1中所示中介层测试接口电路的具体结构图。
图5是图1中所示芯粒测试输出控制电路的具体结构图。
图6是本发明实施例中一种2.5D Chiplet绑定后测试电路的整体电路结构示意图。
图7是本发明实施例中一种2.5D Chiplet绑定后测试电路的测试流程图。
图8是本发明实施例中一种2.5D Chiplet绑定后测试电路的并行测试芯粒的仿真波形图。
图中标号说明：201～221为第一至第二十一数据选择器，222为第一与门，223为第一或门，301为三个与门，302为三个数据选择器，303为三个寄存器，401～402为第一、第二3选2数据选择器，403为6选1数据选择器，404～405为第二、第三与门，406为反相器，407～408为第一、第二寄存器组。
具体实施方式
为了使本发明的目的、特征和优点更加明显易懂，下面结合说明书附图对本发明的具体实施方式做进一步地详细说明，所描述的实施例是本发明的一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本发明保护的范围。
为了更好地理解本发明，以下详细阐述本发明提出的一种2.5D Chiplet绑定后测试电路的实施例。
本发明实施例的一种2.5D Chiplet绑定后测试电路的主要设计思路是，对中介层进行可测性设计，插入测试电路，输入测试向量，实现多个芯粒绑定后的并行存储器内建自测试。对应的结构框图如图1所示，本实施例的测试电路包括中介层专用TAP控制器、中介层测试接口电路和芯粒测试输出控制电路。首先，通过中介层上的测试数据输入端口TDI、测试时钟信号输入端口TCK、测试模式选择信号输入端口TMS和测试复位信号输入端口TRST的4个外部测试端口输入配置向量到中介层专用TAP控制器里，设置SEL_B信号的数值。然后，仍通过TDI、TCK、TMS和TRST端口输入芯粒的测试向量到中介层测试接口电路里，中介层测试接口电路用于提供tdi_b、tck_b、tms_b、trst_b、tdo_b端口，在SEL_B信号的控制作用下，中介层测试接口电路提供的tdi_b、tck_b、tms_b、trst_b、tdo_b端口与被选择的待测试芯粒的测试端口连接，根据SEL_B以及从外部测试端口接收的测试向量生成待测试芯粒的测试向量，中介层测试接口电路传输待测试芯粒的测试向量到对应待测试芯粒的测试端口上，待测试芯粒接收到测试向量后进行测试。最后，芯粒的测试结果通过tdo_b端口进入中介层测试接口电路，再传输到芯粒测试输出控制电路，芯粒测试输出控制电路在SEL_B信号 的控制作用下选择对应芯粒的测试输出结果到外部的测试数据输出端口TDO。
图2是图1中的中介层专用TAP控制器的更详细示图，中介层专用TAP控制器包括有限状态机(FSM)、指令寄存器模块、数据寄存器模块和一些组合逻辑门。在指令寄存器模块中定义了一个名为STACK的新指令，用于选择访问数据寄存器模块中新增的芯粒测试配置寄存器，该芯粒测试配置寄存器输出SEL_B信号，即图1中所示的SEL_B信号，为中介层测试接口电路和芯粒测试输出控制电路提供控制信号。从TDI串行移入STACK指令的定义数值至指令寄存器模块，经指令译码器处理后，得到选择访问芯粒测试配置寄存器的STACK指令，当STACK指令为高电平时，芯粒测试配置寄存器接入中介层专用TAP控制器测试数据输入端口与测试数据输出端口之间有效路径上，输出芯粒测试配置寄存器中的存储数据(即图3中的芯粒测试配置寄存器存储的数据so)作为输出至TDO端口的tdo_tap。当边界扫描寄存器或旁路寄存器或指令寄存器接入中介层专用TAP控制器测试数据输入端口与测试数据输出之间有效路径上时，边界扫描寄存器或旁路寄存器或指令寄存器中存储的数据作为传输至TDO端口的tdo_tap。
图3是图2中的芯粒测试配置寄存器的更详细示图，包括第一至第十四寄存器201～214、第十五至第二十一数据选择器215～221、第一与门222和第一或门223。第一至第七寄存器201～207的时钟端接入从测试时钟信号输入端口TCK输入的tck信号，第十五至第二十一数据选择器215～221在FSM产生的数据寄存器移位使能信号shift_dr为1时，测试数据输入信号tdi在tck的上升沿时刻移入到第一至第七寄存器201～207中，测试数据输入信号tdi经第一至第七寄存器201～207的移位处理后输出芯粒测试配置寄存器存储的数据so，相反shift_dr为0时，则第一至第七寄存器201～207的输出值反馈给连接在各自输入端的第十五至第二十一数据选择器215～221。为了使芯粒测试配置寄存器的控制信号数值仅在STACK指令使能情况下更新，将STACK信号和FSM产生的数据寄存器更新使能信号update_dr送入第一与门222，第一与门222的输出端连接到第八至第十四寄存器208～214的时钟端，当第一与门222的输出有翻转且在tck下降沿时，第一至第七寄存器201～207的输出分别移入到第八至第十四寄存器208～214中，第八寄存器208输出Keep信号，第九至第十四寄存器209～214输出6位的SEL_B[5:0]信号，相反地，第一与门222的输出无翻转时，则第八至第十四寄存器208～214的输出不变。第八寄存器208的复位端接收来自外部TRST端口的异步复位信号trst，第八寄存器208的输出信号Keep与来自FSM的同步复位信号reset送入第一或门223，第一或门223的输出连接到第九至第十四寄存器209～214的复位端，当第一或门223的输出为1时，SEL_B信号除了在异步复位trst信号有效时保持原有值不变，相反为0时，SEL_B信号在FSM进入Test-Logic-Reset状态(即reset信号低有效)后被重置为初始值0。
图4是图1中的中介层测试接口电路的更详细示图，中介层测试接口电路包括三个与门301、三个数据选择器302和三个寄存器303，中介层测试接口电路中的tdi_b、tck_b、tms_b、trst_b和tdo_b端口分别与中介层上芯粒的tdi、tck、tms、trst和tdo端口相连。SEL_B[5:3]信号中的SEL_B[5]、SEL_B[4]和SEL_B[3](即表示执行并行测试的被测芯粒信息)分别与tck信号接到三个与门301的两个输入端上，输出三个信号tck_b[2]、tck_b[1]和tck_b[0](即图4中的tck_b[2:0])至tck_b端口。当SEL_B为0时，即芯粒没有选择被测试，使输入至tck_b端口的信号保持为0，防止发生翻转造成不必要的功耗损失。tms信号和固定值1都接到三个数据选择器302的两个数据输入端上，三个数据选择器302的数据选择端分别是3 位宽的SEL_B[5:3]信号，当SEL_B为1时，tms信号直接输入至tms_b端口，当相反为0时，使没有选择测试芯粒对应的信号为1，即tms_b端口输出信号为1，防止在tck_b信号没有被关掉的情况下使FSM进入Test_Logic_Reset状态以保持同步复位。在tdi与tdi_b[2]、tdi_b[1]和tdi_b[0](即图4中的tdi_b[2:0])之间分别加入三个寄存器303，进行时序调整，消除在2.5D Chiplet中测试数据经过长路径移位受到的时序影响。三个与门301的输出tck_b[2:0]分别接到三个寄存器303的时钟端，在三个与门301输出时钟信号的上升沿时刻使移入的测试数据tdi通过寄存器303输出到tdi_b端口上。tdo_b端口用于将被测试芯粒的测试输出传输至外部TDO端口。为了节省硬件开销，TRST端口到trst_b端口、tdo_b端口到TDO端口之间不添加任何逻辑。
图5是图1中的芯粒测试输出控制电路的更详细示图，芯粒测试输出控制电路包括第一、第二3选2数据选择器401和402、一个6选1的数据选择器403、第二、第三与门404和405、一个反相器406，以及第一、第二寄存器组407和408。由于在中介层上只存在一个外部测试输出端口，为满足多芯粒并行测试的需求，设计了芯粒测试输出控制电路。执行并行测试的被测芯粒的测试输出信号tdo_b[2]、tdo_b[1]和tdo_b[0]连到第一3选2数据选择器401的三个数据输入端上，根据第一3选2数据选择器401上的数据选择信号SEL_B[5:0]的值(即芯粒测试配置寄存器输出的SEL_B[5:0])，输出tdo_din[1]和tdo_din[0]，为第一、第二寄存器组407和408提供数据输入信号。在中介层测试接口电路上的芯粒测试时钟信号tck_b[2]、tck_b[1]和tck_b[0]连到第二3选2数据选择器402的三个数据输入端上，根据第二3选2数据选择器402上的数据选择信号SEL_B[5:3]的值(即SEL_B中表示执行并行测试的被测芯粒信息的数据)，输出两个时钟信号，再分别连到第二、第三与门404和405的一个输入端上，由中介层专用TAP控制器产生的测试输出使能信号tdo_en经过反相器406的输出连到第二、第三与门404和405的另一个输入端上。第二、第三与门404和405的输出端分别连到第一、第二寄存器组407和408的时钟端，可实现在多芯粒并行测试时把正在测试但未被选择通过tdo输出测试结果的芯粒的有效输出结果移入到寄存器组中。tdo_b[2]、tdo_b[1]、tdo_b[0]、中介层专用TAP控制器的测试输出tdo_tap、第一寄存器组407的输出tdo_dout[1]和第二寄存器组408的输出tdo_dout[0]是6选1数据选择器403的六个数据输入信号，6选1数据选择器403根据数据选择信号SEL_B[2:0]的数值(即表示并行测试的被测芯粒测试输出信号输出顺序的数据)输出tdo信号至中介层上TDO外部端口。
图6是此实施例的整体电路结构示意图，包括3个芯粒和1个中介层。芯粒中包括在绑定前已插入且不可改动的可测性设计电路，图中仅示意了TAP控制器和测试电路两个部分。在中介层中包括中介层专用TAP控制器、中介层测试接口电路和芯粒测试输出控制电路。
按照图7所示的测试流程图对芯粒2、芯粒1和芯粒0进行绑定后存储器并行内建自测试，先对整体2.5D Chiplet电路上电复位，此时中介层与三个芯粒之间的测试信号通道处于初始的关闭状态。接着，向中介层专用TAP控制器输入配置向量，进入STACK指令模式，对Keep和SEL_B信号进行赋值，打开中介层与芯粒2、芯粒1和芯粒0之间的测试接口通道。再接着输入芯粒的测试向量，启动芯粒2、芯粒1和芯粒0的内建自测试，同时TDO端口先输出芯粒2的测试结果，芯粒1的测试结果存入芯粒测试输出控制电路里的寄存器组1中，芯粒0的测试结果存入芯粒测试输出控制电路里的寄存器组0中。待所有的芯粒都测试完成后，此时 芯粒2的测试输出也已结束，输入配置向量，进入STACK指令模式，对SEL_B信号重新赋值，以输出芯粒测试输出控制电路里寄存器组1中的数值，即输出芯粒1的有效测试结果，此次对SEL_B信号的重新赋值进而改变测试输出信号输出顺序的数据值，对SEL_B信号中表示执行并行测试芯粒信息的数据进行重新赋值时需保持中介层测试接口电路输出不变，赋值后的SEL_B信号开启2个被测芯粒中一个被测芯粒测试输出信号存入的寄存器组的时钟信号并选择此寄存器组的输出至芯片JTAG端口。待寄存器组1输出完成后，再次输入配置向量，对SEL_B信号再次重新赋值，以输出芯粒测试输出控制电路里寄存器组0中的数值，即输出芯粒0的有效测试结果，此次对SEL_B信号的重新赋值与实现输出芯粒1有效测试结果的SEL_B信号的赋值操作相同。
图8是图6中芯粒2、芯粒1和芯粒0并行测试的仿真波形图。图8里框(1)中的波形图对应的是图6中的上电初始化复位和输入配置向量步骤，可观察到STACK指令信号拉高，和SEL_B[5:0]信号已配置为6’b111100且保持不变。图8里框(2)中的波形图对应的是图6中的输入芯粒测试向量和输出芯粒2的测试结果步骤，可观察到芯粒2、芯粒1和芯粒0中的GO和DONE指示信号均已拉高(有效)，因此判断芯粒2、芯粒1和芯粒0的绑定后并行存储器内建自测试均通过。图8里框(3)中的波形图对应的是图6中的再次输入配置向量和输出芯粒1的测试结果步骤，可观察到SEL_B[5:0]信号重新配置为6’b010111，使芯粒测试输出控制电路中寄存器组407的数值从TDO输出，即输出芯粒1的有效测试结果。图8里框(4)中的波形图对应的是图6中的再次输入配置向量和输出芯粒0的测试结果步骤，可观察到SEL_B[5:0]信号重新配置为6’b001000，使芯粒测试输出控制电路中寄存器组408的数值从TDO输出，即输出芯粒0的有效测试结果。
优选的，若改变芯粒的测试需求，可通过上述步骤自定义配置SEL_B信号的数值，实现灵活选择芯粒的绑定后测试。例如，当对包含N个芯粒的多Chiplet集成电路进行并行测试时，选择其中的n个芯粒为并行测试的对象，SEL_B信号可表示为SEL_B[2n-1:0]，其中的n位数据用于表示执行并行测试的被测芯粒的信息，其余的n位数据用于表示执行并行测试的被测芯粒测试输出信号的输出顺序；2≤n≤N时，SEL_B信号表示对N个芯粒中的任意n个芯粒进行并行测试，n个被测芯粒接收到中介层测试接口电路生成的各被测芯粒的测试向量后同时进行内建自测试，相较于主从架构的多Chiplet并行测试方案而言，在任意被测芯粒故障时，其余被测芯粒仍可以进行测试，实现多Chiplet的可靠并行测试；当n＝1时，SEL_B信号表示对N个芯粒中的1个芯粒进行单独的指定测试，使得本申请提出的多Chiplet并行测试方案更加灵活。另一方面，在整个测试过程中，对SEL_B信号的赋值也具有一定的灵活性，执行顺序输出各被测芯粒测试输出信号的过程中，可以在保证中介层测试接口电路输出不变的前提下对SEL_B信号中表示执行被测芯粒信息的数据可以任意赋值。
应说明的是，以上所述仅为本发明的优选方案，并非作为对本发明的进一步限定，凡是利用本发明说明书及附图内容所作的各种等效变化均在本发明的保护范围之内。

Claims (8)

  1. 一种2.5D Chiplet绑定后测试电路，其特征在于，对包括N个Chiplet的多Chiplet集成电路进行并行测试，所述2.5D Chiplet绑定后测试电路包括：
    中介层专用TAP控制器，接收来自芯片JTAG端口的配置向量，输出用于确定执行并行测试的被测芯粒以及测试输出信号输出顺序的控制信号；
    中介层测试接口电路，接收来自芯片JTAG端口的测试向量，在接收到所述中介层专用TAP控制器输出的控制信号时，连接至执行并行测试的被测芯粒的测试数据输入端口、测试时钟信号输入端口、测试模式选择信号输入端口、测试复位信号输入端口、测试数据输出端口，根据所述中介层专用TAP控制器输出的控制信号及来自芯片JTAG端口的测试时钟输入信号生成的各被测芯粒的测试时钟信号传输至各被测芯粒测试时钟信号输入端口，根据所述中介层专用TAP控制器输出的控制信号及来自芯片JTAG端口的测试模式选择信号生成的各被测芯粒的测试模式选择信号传输至各被测芯粒的测试模式选择信号输入端口，根据各被测芯粒的测试时钟信号移入的各被测芯粒的测试数据输入信号传输至各被测芯粒的测试数据输入端口，传输来自芯片JTAG端口的测试复位信号至各被测芯粒的测试复位信号输入端口，传输各被测芯粒的测试输出信号至芯粒测试输出控制电路；及，
    芯粒测试输出控制电路，接收所述中介层专用TAP控制器输出的控制信号，按序传输各被测芯粒的测试输出信号至芯片JTAG端口。
  2. 根据权利要求1所述的一种2.5D Chiplet绑定后测试电路，其特征在于，所述中介层专用TAP控制器包括指令寄存器模块和数据寄存器模块，所述数据寄存器模块包括芯粒测试配置寄存器，所述配置向量经指令寄存器模块处理后生成将芯粒测试配置寄存器接在中介层专用TAP控制器测试数据输入端口和测试数据输出端口之间的有效路径上的指令，所述芯粒测试配置寄存器接入所述有效路径后根据来自芯片JTAG端口的测试数据输入信号生成所述用于确定执行并行测试的被测芯粒以及测试输出信号输出顺序的控制信号。
  3. 根据权利要求1或2所述的一种2.5D Chiplet绑定后测试电路，其特征在于，所述用于确定执行并行测试的被测芯粒以及测试输出信号输出顺序的控制信号为具有2n位数据的信号SEL_B[2n-1:0]，其中的n位数据用于表示执行并行测试的被测芯粒的信息，其余的n位数据用于表示执行并行测试的被测芯粒测试输出信号的输出顺序，1≤n≤N。
  4. 根据权利要求3所述的一种2.5D Chiplet绑定后测试电路，其特征在于，所述中介层测试接口电路包括：
    n个与门，每个与门的一个输入端接收来自芯片JTAG端口的测试时钟输入信号，每个与门的另一个输入端接收表示执行并行测试的被测芯粒信息的n位数据中的一位数据，每个与门输出一个被测芯粒的测试时钟信号；
    n个数据选择器，每个数据选择器的一个输入端接收来自芯片JTAG端口的测试模式选择信号，每个数据选择器的另一个输入端接收高电平，每个数据选择器的数据选择端接收表示执行并行测试的被测芯粒信息的n位数据中的一位数据，每个数据选择器输出一个被测芯粒的测试模式选择信号；及，
    n个寄存器，每个寄存器的输入端接收来自芯片JTAG端口的测试数据输入信号，每个寄存器的时钟端与一个与门的输出端连接，每个寄存器输出一个被测芯粒的测试数据输入信号。
  5. 根据权利要求3所述的一种2.5D Chiplet绑定后测试电路，其特征在于，所述芯粒测 试输出控制电路包括：
    测试时钟信号多路选择器，其n个输入端中的每一个输入端分别接收一个被测芯粒的测试时钟输入信号，其数据选择端接收所述表示执行并行测试的被测芯粒信息的控制信号，其n-1个输出端中的每一个输出端分别输出一个被测芯粒的测试时钟信号；
    输入信号多路数据选择器，其n个输入端中的每一个输入端分别接收一个被测芯粒的测试输出信号，其数据选择端接收所述表示执行并行测试的被测芯粒以及测试输出信号输出顺序的控制信号，其n-1个输出端中的每一个输出端分别连接至一个寄存器组的输入端；
    n-1个与门，每个与门的一个输入端接测试时钟信号多路数据选择器的一个输出端，每个与门的另一个输入端接收来自中介层专用TAP控制器的测试输出使能信号的相反值，每个与门输出一个将一个被测芯粒的测试输出信号存入一个寄存器组的时钟信号；
    n-1个寄存器组，每个寄存器组的输入端接输入信号多路数据选择器的一个输出端，每个寄存器组的时钟端与一个与门的输出端连接，每个寄存器组输出其存储的被测芯粒的有效测试输出信号；及，
    输出信号多路选择器，其2n个输入端中的每一个输入端分别接收一个芯粒的测试输出信号、一个寄存器组的输出信号、中介层专用TAP控制器的输出信号，其数据选择端接收所述表示执行并行测试的被测芯粒测试输出信号输出顺序的控制信号，其输出端按序传输各被测芯粒的测试数据输出信号至芯片JTAG端口。
  6. 根据权利要求3所述的一种2.5D Chiplet绑定后测试电路，其特征在于，所述芯粒测试配置寄存器包括：
    第1至第2n+1寄存器组成的移位寄存器组，每个寄存器的输入端与一个二选一数据选择器的输出端连接，数据选择器的0端和与其连接的寄存器的输出端相连，与第1个寄存器连接的数据选择器的1端接收来自芯片JTAG的配置向量，与第i个寄存器连接的数据选择器的1端与第i-1个寄存器的输出端相连，各数据选择器的数据端接收来自中介层专用TAP控制器的移位使能信号，各寄存器的时钟端接收来自芯片JTAG端口的测试时钟输入信号，第2n+1寄存器输出芯粒测试配置寄存器存储的数据，2≤i≤2n+1；
    与门，其一个输入端接收将芯粒测试配置寄存器接在中介层专用TAP控制器测试数据输入端口和测试数据输出端口之间的有效路径上的指令，其另一个输入端接收来自中介层专用TAP控制器的数据寄存器更新使能信号；
    或门，其一个输入端接第2n+2寄存器的输出端，其另一个输入端接收来自中介层专用TAP控制器的同步测试复位信号；及，
    第2n+2至第4n+2寄存器，第2n+2寄存器的输入端、输出端均与第1寄存器的输出端连接，第j寄存器的输入端、输出端均与第i寄存器的输出端连接，第2n+2至第4n+2寄存器中的各寄存器的时钟端均与与门的输出端连接，第2n+2寄存器的复位端接收来自芯片JTAG端口的异步测试复位信号，第2n+3至第4n+2寄存器中的各寄存器的复位端均接或门的输出端，第2n+3至第4n+2寄存器输出的各位数据组成用于确定执行并行测试的被测芯粒以及测试输出信号输出顺序的控制信号，2n+3≤j≤4n+2。
  7. 一种2.5D Chiplet绑定后测试方法，其特征在于，
    将权利要求6所述测试电路上电初始化复位后，向芯片JTAG端口输入使被测芯粒的测试数据输入端口、测试时钟信号输入端口、测试模式选择信号输入端口、测试复位信号输入 端口、测试数据输出端口与中介层测试接口电路连接的配置向量；
    向芯片JTAG端口输入测试向量，各被测芯粒中的一个被测芯粒的测试输出信号直接输出至芯片JTAG端口，其余n-1个被测芯粒的测试输出信号按顺序等待输出；
    向芯片JTAG端口顺序输入n-1个配置向量，每一次输入的配置向量选择n-1个被测芯粒中一个被测芯粒的测试输出信号为输出对象。
  8. 根据权利要求7所述的一种2.5D Chiplet绑定后测试方法，其特征在于，向芯片JTAG端口顺序输入的n-1个配置向量用于对确定执行并行测试的被测芯粒以及测试输出信号输出顺序的控制信号进行n-1次赋值，每次赋值的依据是开启n-1个被测芯粒中一个被测芯粒测试输出信号存入的寄存器组的时钟信号并选择此寄存器组的输出至芯片JTAG端口。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117872103A (zh) * 2024-03-11 2024-04-12 南京邮电大学 一种通用测试芯粒

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115020266B (zh) * 2022-08-04 2022-11-04 南京邮电大学 一种2．5D Chiplet绑定后测试电路
CN115598495B (zh) * 2022-09-16 2024-01-30 深圳市奇普乐芯片技术有限公司 芯片测试配置生成方法、测试方法、装置及电子设备
CN115295065B (zh) * 2022-10-09 2022-12-13 南京邮电大学 一种基于灵活可配置模块的芯粒测试电路
CN115547404A (zh) * 2022-11-30 2022-12-30 普赛微科技(杭州)有限公司 用于先进封装mram存储器的测试架构及方法
CN116256620B (zh) * 2023-05-15 2023-07-14 中诚华隆计算机技术有限公司 Chiplet集成芯片的检测方法、装置、电子设备及存储介质
CN116718902B (zh) * 2023-08-11 2023-10-20 中诚华隆计算机技术有限公司 一种基于Chiplet的芯片内置自测试方法和系统
CN116859226B (zh) * 2023-09-04 2023-11-17 中国电子科技集团公司第五十八研究所 一种面向2.5d双芯粒互连封装系统的测试电路
CN117056279B (zh) * 2023-10-12 2024-01-26 之江实验室 可重构电路、可重构芯粒间互联的装置及其方法
CN117236263B (zh) * 2023-11-15 2024-02-06 之江实验室 一种多芯粒互联仿真方法、装置、存储介质及电子设备

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100174958A1 (en) * 2009-01-06 2010-07-08 Nec Electronics Corporation Test circuit including tap controller selectively outputting test signal based on mode and shift signals
CN102880536A (zh) * 2012-09-07 2013-01-16 杭州中天微系统有限公司 一种多核处理器的jtag调试方法
CN109473361A (zh) * 2018-10-24 2019-03-15 深圳赛意法微电子有限公司 半导体功率器件的并行测试方法
CN111183517A (zh) * 2018-01-17 2020-05-19 默升科技集团有限公司 具有中介层的并行prbs测试的ic裸片
CN112595966A (zh) * 2021-03-03 2021-04-02 南京邮电大学 一种基于IEEE标准Chiplet电路测试方法
CN114253184A (zh) * 2021-11-29 2022-03-29 山东云海国创云计算装备产业创新中心有限公司 一种jtag控制装置
CN115020266A (zh) * 2022-08-04 2022-09-06 南京邮电大学 一种2．5D Chiplet绑定后测试电路

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63241791A (ja) * 1987-03-27 1988-10-07 Matsushita Electric Ind Co Ltd 半導体記憶装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100174958A1 (en) * 2009-01-06 2010-07-08 Nec Electronics Corporation Test circuit including tap controller selectively outputting test signal based on mode and shift signals
CN102880536A (zh) * 2012-09-07 2013-01-16 杭州中天微系统有限公司 一种多核处理器的jtag调试方法
CN111183517A (zh) * 2018-01-17 2020-05-19 默升科技集团有限公司 具有中介层的并行prbs测试的ic裸片
CN109473361A (zh) * 2018-10-24 2019-03-15 深圳赛意法微电子有限公司 半导体功率器件的并行测试方法
CN112595966A (zh) * 2021-03-03 2021-04-02 南京邮电大学 一种基于IEEE标准Chiplet电路测试方法
CN114253184A (zh) * 2021-11-29 2022-03-29 山东云海国创云计算装备产业创新中心有限公司 一种jtag控制装置
CN115020266A (zh) * 2022-08-04 2022-09-06 南京邮电大学 一种2．5D Chiplet绑定后测试电路

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CN117872103B (zh) * 2024-03-11 2024-05-10 南京邮电大学 一种通用测试芯粒

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