JP2001507809A - コアのテスト制御 - Google Patents
コアのテスト制御Info
- Publication number
- JP2001507809A JP2001507809A JP52578399A JP52578399A JP2001507809A JP 2001507809 A JP2001507809 A JP 2001507809A JP 52578399 A JP52578399 A JP 52578399A JP 52578399 A JP52578399 A JP 52578399A JP 2001507809 A JP2001507809 A JP 2001507809A
- Authority
- JP
- Japan
- Prior art keywords
- core
- tcb
- test
- shift register
- chain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318555—Control logic
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.複数のコアを具え、各コアがこれらの各コアをテストモードに制御するため のそれぞれのコアテスト制御ブロック(TCB)に関連づけられ、各コアTC Bがテスト制御データを保持するためのコアシフトレジスタを具え、前記コア TCBがチェーン内に直列にリンクされ、前記各コアTCBが前記テスト制御 データを前記チェーンに沿ってシフトする第1モードと、前記テスト制御デー タを関連するコアに供給する第2モードとを有するようにした集積回路におい て、 前記チェーンにシステムTCBを設け、該システムTCBの出力端子を前記 各コアTCBに接続して、前記システムTCBが或る特定のテスト制御データ セットを受取ったら、前記コアTCBにシステムテストホールド信号を供給し て、前記コアTCBを前記第1モードか、第2モードのいずれかに切り換える ようにしたことを特徴とする集積回路。 2. 前記システムTCBを前記チェーンの終端部に位置させ、且つシステムシ フトレジスタを具えている前記システムTCBを前記チェーンの一部とし、前 記システムシフトレジスタの出力が前記システムTCBの出力を供給し、前記 集積回路が、前記コアシフトレジスタ及び前記システムシフトレジスタを初期 状態にリセットするリセット回路も具えていることを特徴とする請求の範囲1 に記載の集積回路。 3.各コアシフトレジスタを記憶素子の直列接続で構成した請求の範囲1に記載 の集積回路において、各記憶素子の入力端子にそれぞれのマルチプレクサを設 け、該マルチプレクサの第1入力によりテスト制御データを前記チェーンに沿 ってシフト可能とし、前記マルチプレクサの第2入力を前記記憶素子の出力端 子に接続し、前記マルチプレクサの状態が前記システムテストホールド信号の 制御下にあるようにしたことを特徴とする集積回路。 4.前記各コアTCBのコアシフトレジスタを、関連するイネーブリング回路を 介して各コアTCBに関連するコアに接続し、前記イネーブリング回路の出力 が、該イネーブリング回路の第1状態では予定した信号を搬送し、且つ第2状 態では前記コアシフトレジスタの内容を搬送し、前記イネーブリング回路の状態 が前記システムテストホールド信号の制御下にあるようにしたことを特徴とする 請求の範囲3に記載の集積回路。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP97203378.1 | 1997-10-31 | ||
EP97203378 | 1997-10-31 | ||
PCT/IB1998/001601 WO1999023503A1 (en) | 1997-10-31 | 1998-10-12 | Core test control |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2001507809A true JP2001507809A (ja) | 2001-06-12 |
JP3987585B2 JP3987585B2 (ja) | 2007-10-10 |
Family
ID=8228890
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52578399A Expired - Fee Related JP3987585B2 (ja) | 1997-10-31 | 1998-10-12 | コアのテスト制御 |
Country Status (7)
Country | Link |
---|---|
US (1) | US6061284A (ja) |
EP (1) | EP0950192B1 (ja) |
JP (1) | JP3987585B2 (ja) |
KR (1) | KR100567936B1 (ja) |
DE (1) | DE69833123T2 (ja) |
TW (1) | TW418330B (ja) |
WO (1) | WO1999023503A1 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6499124B1 (en) * | 1999-05-06 | 2002-12-24 | Xilinx, Inc. | Intest security circuit for boundary-scan architecture |
EP1158305A1 (en) * | 2000-05-15 | 2001-11-28 | Bull S.A. | System integrated on a chip of semiconductor material |
CN1471640A (zh) * | 2001-03-08 | 2004-01-28 | �ʼҷ����ֵ�������˾ | 用于测试可测试电子装置的方法 |
CA2360291A1 (en) | 2001-10-30 | 2003-04-30 | Benoit Nadeau-Dostie | Method and program product for designing hierarchical circuit for quiescent current testing and circuit produced thereby |
US6862717B2 (en) * | 2001-12-17 | 2005-03-01 | Logicvision, Inc. | Method and program product for designing hierarchical circuit for quiescent current testing |
US6934897B2 (en) * | 2002-04-05 | 2005-08-23 | Nilanjan Mukherjee | Scheduling the concurrent testing of multiple cores embedded in an integrated circuit |
KR100448706B1 (ko) * | 2002-07-23 | 2004-09-13 | 삼성전자주식회사 | 단일 칩 시스템 및 이 시스템의 테스트/디버그 방법 |
KR102038414B1 (ko) * | 2013-06-20 | 2019-11-26 | 에스케이하이닉스 주식회사 | 테스트 장치 및 그의 동작 방법 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5054024A (en) * | 1989-08-09 | 1991-10-01 | Texas Instruments Incorporated | System scan path architecture with remote bus controller |
DE68923086T2 (de) * | 1989-08-25 | 1996-01-25 | Philips Electronics Nv | Verfahren zum Testen von hierarchisch organisierten integrierten Schaltungen und integrierte Schaltungen, geeignet für einen solchen Test. |
US5130988A (en) * | 1990-09-17 | 1992-07-14 | Northern Telecom Limited | Software verification by fault insertion |
TW211094B (en) * | 1992-04-30 | 1993-08-11 | American Telephone & Telegraph | Built-in self-test network |
US5477545A (en) * | 1993-02-09 | 1995-12-19 | Lsi Logic Corporation | Method and apparatus for testing of core-cell based integrated circuits |
US5448525A (en) * | 1994-03-10 | 1995-09-05 | Intel Corporation | Apparatus for configuring a subset of an integrated circuit having boundary scan circuitry connected in series and a method thereof |
-
1998
- 1998-10-12 WO PCT/IB1998/001601 patent/WO1999023503A1/en active IP Right Grant
- 1998-10-12 JP JP52578399A patent/JP3987585B2/ja not_active Expired - Fee Related
- 1998-10-12 DE DE69833123T patent/DE69833123T2/de not_active Expired - Lifetime
- 1998-10-12 EP EP98945493A patent/EP0950192B1/en not_active Expired - Lifetime
- 1998-10-12 KR KR1019997005889A patent/KR100567936B1/ko not_active IP Right Cessation
- 1998-10-26 US US09/179,168 patent/US6061284A/en not_active Expired - Lifetime
- 1998-11-30 TW TW087119798A patent/TW418330B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0950192A1 (en) | 1999-10-20 |
DE69833123D1 (de) | 2006-03-30 |
US6061284A (en) | 2000-05-09 |
KR100567936B1 (ko) | 2006-04-07 |
EP0950192B1 (en) | 2006-01-04 |
JP3987585B2 (ja) | 2007-10-10 |
TW418330B (en) | 2001-01-11 |
DE69833123T2 (de) | 2006-08-24 |
KR20000069753A (ko) | 2000-11-25 |
WO1999023503A1 (en) | 1999-05-14 |
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