WO2024020997A1 - 像素电路和显示装置 - Google Patents

像素电路和显示装置 Download PDF

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Publication number
WO2024020997A1
WO2024020997A1 PCT/CN2022/108878 CN2022108878W WO2024020997A1 WO 2024020997 A1 WO2024020997 A1 WO 2024020997A1 CN 2022108878 W CN2022108878 W CN 2022108878W WO 2024020997 A1 WO2024020997 A1 WO 2024020997A1
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WIPO (PCT)
Prior art keywords
control
terminal
electrically connected
latch
inverter
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Application number
PCT/CN2022/108878
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English (en)
French (fr)
Inventor
丛宁
玄明花
张粲
王灿
牛晋飞
张晶晶
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/108878 priority Critical patent/WO2024020997A1/zh
Publication of WO2024020997A1 publication Critical patent/WO2024020997A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel circuit and a display device.
  • Micro LED micro light-emitting diode
  • Mini LED sub-millimeter light-emitting diode
  • the size of sub-millimeter light-emitting diodes is about 100 ⁇ m-300 ⁇ m, and the size of micro light-emitting diodes is less than 100 ⁇ m.
  • Micro LED display panels and Mini LED display panels cannot achieve high PPI (Pixels Per Inch, pixel density) display, and low grayscale display has poor uniformity.
  • an embodiment of the present disclosure provides a pixel circuit, including a light-emitting circuit, a light-emitting control circuit, a first control circuit and a switch control circuit;
  • the lighting control circuit is electrically connected to the lighting control terminal, the control voltage input terminal and the lighting circuit respectively, and is used to control the control voltage input terminal and the lighting circuit under the control of the lighting control signal provided by the lighting control terminal.
  • the light-emitting circuits are connected;
  • the light-emitting circuit is used to emit light according to the control voltage provided by the control voltage input terminal;
  • the first control circuit is electrically connected to at least two data voltage terminals, at least two scanning terminals and N switch control terminals respectively, and is used to control the scanning signal according to the data voltage terminal under the control of the scanning signal provided by the scanning terminal.
  • the data voltage provided controls the switch control signal provided to the switch control terminal;
  • N is an integer greater than 1;
  • the switch control circuit includes N switch control terminals, N lighting control voltage terminals and N switch control sub-circuits; n is a positive integer less than or equal to N;
  • the nth switch control sub-circuit is electrically connected to the nth switch control terminal, the nth light-emitting control voltage terminal and the control voltage input terminal respectively, and is used under the control of the nth switch control signal provided by the nth switch control terminal. , controlling the connection between the nth light-emitting control voltage terminal and the control voltage input terminal.
  • the lighting control voltage provided by the lighting control voltage terminal is a DC voltage
  • the lighting control voltages provided by the N lighting control voltage terminals are different from each other.
  • the lighting control voltage provided by the lighting control voltage terminal is a square wave voltage signal, and the duty ratios of the lighting control voltages provided by the N lighting control voltage terminals are different from each other.
  • N equals 2 a , a is a positive integer.
  • the first control circuit includes a first data writing circuit, a second data writing circuit and a first control sub-circuit;
  • the first data writing circuit is electrically connected to the first scanning terminal, the first data voltage terminal and the first data access terminal respectively, and is used to write the data under the control of the first scanning signal provided by the first scanning terminal.
  • the first data voltage provided by the first data voltage terminal is written into the first data access terminal;
  • the second data writing circuit is electrically connected to the second scanning terminal, the second data voltage terminal and the second data access terminal respectively, and is used to write the second data under the control of the second scanning signal provided by the second scanning terminal.
  • the second data voltage provided by the second data voltage terminal is written into the second data access terminal;
  • the first control sub-circuit is electrically connected to the first data access terminal, the second data access terminal and N switch control terminals respectively, and is used to control the electric potential of the first data access terminal and the The potential of the second data access terminal controls the provision of corresponding switch control signals to the N switch control terminals.
  • the first control sub-circuit includes a first latch, a second latch, a third latch, a fourth latch, a first control switch and a second control switch; N equals 4;
  • the input end of the first latch is electrically connected to the first data access end, the output end of the first latch is electrically connected to the control end of the first control switch, and the first latch
  • the register is used to latch the voltage signal connected to the first data access terminal and output a first output voltage, where the first output voltage is inverse phase with the voltage signal connected to the first data access terminal;
  • the input end of the second latch is electrically connected to the second data access end, the output end of the second latch is electrically connected to the control end of the second control switch, and the second latch
  • the register is used to latch the voltage signal connected to the second data access terminal and output a second output voltage, where the second output voltage is inverted with the voltage signal connected to the second data access terminal;
  • the input terminal of the third latch is electrically connected to the first terminal of the first control switch, the output terminal of the third latch is electrically connected to the control terminal of the first switch, and the third latch is electrically connected to the first terminal of the first control switch. latch the voltage signal connected to its input end and output a third output voltage, the third output voltage being inverted with the voltage signal connected to the input end of the third latch;
  • the input end of the fourth latch is electrically connected to the first end of the second control switch, the output end of the fourth latch is electrically connected to the third switch control end, and the fourth latch is electrically connected to the first end of the second control switch. latch the voltage signal connected to its input end and output a fourth output voltage, the fourth output voltage being inverted with the voltage signal connected to the input end of the fourth latch;
  • the control terminal of the first control switch is electrically connected to the output terminal of the first latch, the second terminal of the first control switch is electrically connected to the output terminal of the second latch, and the second terminal of the first control switch is electrically connected to the output terminal of the second latch.
  • a control switch is used to control the connection or disconnection between the first end of the first control switch and the second end of the first control switch under the control of the potential of its control end;
  • the control terminal of the second control switch is electrically connected to the input terminal of the first latch, and the second terminal of the second control switch is electrically connected to the input terminal of the second latch.
  • the second control switch is used to control the connection or disconnection between the first end of the second control switch and the second end of the second control switch under the control of the potential of its control end;
  • the first switch control terminal is electrically connected to the output terminal of the third latch, and the second switch control terminal is electrically connected to the input terminal of the third latch;
  • the third switch control terminal is electrically connected to the output terminal of the fourth latch, and the fourth switch control terminal is electrically connected to the input terminal of the fourth latch.
  • the first latch includes a first inverter and a second inverter
  • the input terminal of the first inverter is electrically connected to the input terminal of the first latch, and the output terminal of the first inverter is electrically connected to the output terminal of the first latch;
  • the input terminal of the second inverter is electrically connected to the output terminal of the first inverter, and the output terminal of the second inverter is electrically connected to the input terminal of the first inverter;
  • the second latch includes a third inverter and a fourth inverter
  • the input terminal of the third inverter is electrically connected to the input terminal of the second latch, and the output terminal of the third inverter is electrically connected to the output terminal of the second latch;
  • the input terminal of the fourth inverter is electrically connected to the output terminal of the third inverter, and the output terminal of the fourth inverter is electrically connected to the input terminal of the third inverter;
  • the third latch includes a fifth inverter and a sixth inverter
  • the input terminal of the fifth inverter is electrically connected to the input terminal of the third latch, and the output terminal of the fifth inverter is electrically connected to the output terminal of the third latch;
  • the input terminal of the sixth inverter is electrically connected to the output terminal of the fifth inverter, and the output terminal of the sixth inverter is electrically connected to the input terminal of the fifth inverter;
  • the fourth latch includes a seventh inverter and an eighth inverter
  • the input terminal of the seventh inverter is electrically connected to the input terminal of the fourth latch, and the output terminal of the seventh inverter is electrically connected to the output terminal of the fourth latch;
  • the input terminal of the eighth inverter is electrically connected to the output terminal of the seventh inverter, and the output terminal of the eighth inverter is electrically connected to the input terminal of the seventh inverter.
  • the first control switch is a first control transistor
  • the second control switch is a second control transistor
  • the control electrode of the first control transistor is electrically connected to the output terminal of the first latch, and the first electrode of the first control transistor is electrically connected to the input terminal of the third latch. an electrical connection between the second pole of the control transistor and the output terminal of the second latch;
  • the control electrode of the second control transistor is electrically connected to the input terminal of the first latch, and the first electrode of the second control transistor is electrically connected to the input terminal of the fourth latch.
  • the second pole of the two control transistors is electrically connected to the input terminal of the second latch.
  • the first data writing circuit includes a first writing transistor
  • the second data writing circuit includes a second writing transistor
  • the control electrode of the first writing transistor is electrically connected to the first scan terminal, the first electrode of the first writing transistor is electrically connected to the first data voltage terminal, and the control electrode of the first writing transistor is electrically connected to the first data voltage terminal.
  • the second pole is electrically connected to the first data access terminal;
  • the control electrode of the second writing transistor is electrically connected to the second scan terminal
  • the first electrode of the second writing transistor is electrically connected to the second data voltage terminal
  • the control electrode of the second writing transistor is electrically connected to the second data voltage terminal.
  • the second pole is electrically connected to the second data access terminal.
  • the first control circuit includes a first data writing circuit, a second data writing circuit, a third data writing circuit, a fourth data writing circuit and a second control subcircuit;
  • the first data writing circuit is electrically connected to the first scanning terminal, the first data voltage terminal and the first data access terminal respectively, and is used to write the data under the control of the first scanning signal provided by the first scanning terminal.
  • the first data voltage provided by the first data voltage terminal is written into the first data access terminal;
  • the second data writing circuit is electrically connected to the second scanning terminal, the second data voltage terminal and the second data access terminal respectively, and is used to write the second data under the control of the second scanning signal provided by the second scanning terminal.
  • the second data voltage provided by the second data voltage terminal is written into the second data access terminal;
  • the third data writing circuit is electrically connected to the third scanning terminal, the third data voltage terminal and the third data access terminal respectively, and is used to write the data under the control of the third scanning signal provided by the third scanning terminal.
  • the third data voltage provided by the third data voltage terminal is written into the third data access terminal;
  • the fourth data writing circuit is electrically connected to the fourth scanning terminal, the fourth data voltage terminal and the fourth data access terminal respectively, and is used to write the fourth data under the control of the fourth scanning signal provided by the fourth scanning terminal.
  • the fourth data voltage provided by the fourth data voltage terminal is written into the fourth data access terminal;
  • the second control subcircuit is respectively connected to the first data access terminal, the second data access terminal, the third data access terminal, the fourth data access terminal and N switch control terminals. Electrical connection, used to control the voltage to the said first data access terminal according to the potential of the first data access terminal, the potential of the second data access terminal, the potential of the third data access terminal and the potential of the fourth data access terminal.
  • the N switch control terminals provide corresponding switch control signals respectively.
  • the second control sub-circuit includes a first latch, a second latch, a third latch, a fourth latch, a fifth latch, a sixth latch, a seventh latch. latch, eighth latch, ninth latch, tenth latch, first control switch, second control switch, third control switch, fourth control switch, fifth control switch and sixth control Switch; N equals 8;
  • the input end of the first latch is electrically connected to the first data access end, the output end of the first latch is electrically connected to the control end of the first control switch, and the first latch
  • the register is used to latch the voltage signal connected to the first data access terminal and output a first output voltage, where the first output voltage is inverse phase with the voltage signal connected to the first data access terminal;
  • the input end of the second latch is electrically connected to the second data access end, the output end of the second latch is electrically connected to the control end of the second control switch, and the second latch
  • the register is used to latch the voltage signal connected to the second data access terminal and output a second output voltage, where the second output voltage is inverted with the voltage signal connected to the second data access terminal;
  • the input terminal of the third latch is electrically connected to the first terminal of the first control switch, and the output terminal of the third latch is electrically connected to the control terminal of the third control switch.
  • the third latch is used to latch the voltage signal connected to its input end and output a third output voltage, and the third output voltage is inverse phase with the voltage signal connected to the input end of the third latch;
  • the input end of the fourth latch is electrically connected to the first end of the second control switch, the output end of the fourth latch is electrically connected to the control end of the fifth control switch, and the fourth latch is electrically connected to the control end of the fifth control switch.
  • the latch is used to latch the voltage signal connected to its input end and output a fourth output voltage, where the fourth output voltage is inverse phase with the voltage signal connected to the input end of the fourth latch;
  • the input end of the fifth latch is electrically connected to the first end of the third control switch, the output end of the fifth latch is electrically connected to the second switch control end, and the fifth latch is electrically connected to the first end of the third control switch. latch the voltage signal connected to its input end and output a fifth output voltage, the fifth output voltage being inverted with the voltage signal connected to the input end of the fifth latch;
  • the input terminal of the sixth latch is electrically connected to the third data access terminal, the output terminal of the sixth latch is electrically connected to the second terminal of the third control switch, and the sixth latch is electrically connected to the second terminal of the third control switch.
  • the latch is used to latch the voltage signal connected to its input end and output a sixth output voltage, where the sixth output voltage is inverse phase with the voltage signal connected to the input end of the sixth latch;
  • the input end of the seventh latch is electrically connected to the first end of the fourth control switch, the output end of the seventh latch is electrically connected to the fourth switch control end, and the seventh latch is electrically connected to the first end of the fourth control switch. latch the voltage signal connected to its input end and output a seventh output voltage, the seventh output voltage being inverse phase with the voltage signal connected to the input end of the seventh latch;
  • the input terminal of the eighth latch is electrically connected to the first terminal of the fifth control switch, the output terminal of the eighth latch is electrically connected to the control terminal of the sixth switch, and the eighth latch is electrically connected to the first terminal of the fifth control switch. latch the voltage signal connected to its input end and output an eighth output voltage, the eighth output voltage having an inverse phase with the voltage signal connected to the input end of the eighth latch;
  • the input terminal of the ninth latch is electrically connected to the fourth data access terminal, and the output terminal of the ninth latch is electrically connected to the second terminal of the fifth control switch.
  • the latch is used to latch the voltage signal connected to its input end and output a ninth output voltage, where the ninth output voltage is inverse phase with the voltage signal connected to the input end of the ninth latch;
  • the input end of the tenth latch is electrically connected to the first end of the sixth control switch, the output end of the tenth latch is electrically connected to the eighth switch control end, and the tenth latch is electrically connected to the first end of the sixth control switch. latch the voltage signal connected to its input end and output a tenth output voltage, the tenth output voltage being inverted with the voltage signal connected to the input end of the tenth latch;
  • the control terminal of the first control switch is electrically connected to the output terminal of the first latch, the second terminal of the first control switch is electrically connected to the output terminal of the second latch, and the second terminal of the first control switch is electrically connected to the output terminal of the second latch.
  • a control switch is used to control the connection or disconnection between the first end of the first control switch and the second end of the first control switch under the control of the potential of its control end;
  • the control terminal of the second control switch is electrically connected to the input terminal of the first latch, and the second terminal of the second control switch is electrically connected to the input terminal of the second latch.
  • the second control switch is used to control the connection or disconnection between the first end of the second control switch and the second end of the second control switch under the control of the potential of its control end;
  • the control end of the third control switch is electrically connected to the output end of the third latch, and the third control switch is used to control the input of the fifth latch under the control of the potential of its control end.
  • the terminal is connected or disconnected from the output terminal of the sixth latch;
  • the control end of the fourth control switch is electrically connected to the input end of the third latch.
  • the fourth control switch is used to control the input of the seventh latch under the control of the potential of its control end.
  • the terminal is connected or disconnected from the input terminal of the sixth latch;
  • the control end of the fifth control switch is electrically connected to the output end of the fourth latch, and the fifth control switch is used to control the input of the eighth latch under the control of the potential of its control end.
  • the terminal is electrically connected to the output terminal of the ninth latch;
  • the control terminal of the sixth control switch is electrically connected to the input terminal of the fourth latch.
  • the sixth control switch is used to control the input of the tenth latch under the control of the potential of its control terminal.
  • the terminal is connected to the input terminal of the ninth latch;
  • the first switch control terminal is electrically connected to the input terminal of the fifth latch, and the seventh switch control terminal is electrically connected to the input terminal of the tenth latch.
  • the first latch includes a first inverter and a second inverter
  • the input terminal of the first inverter is electrically connected to the input terminal of the first latch, and the output terminal of the first inverter is electrically connected to the output terminal of the first latch;
  • the input terminal of the second inverter is electrically connected to the output terminal of the first inverter, and the output terminal of the second inverter is electrically connected to the input terminal of the first inverter;
  • the second latch includes a third inverter and a fourth inverter
  • the input terminal of the third inverter is electrically connected to the input terminal of the second latch, and the output terminal of the third inverter is electrically connected to the output terminal of the second latch;
  • the input terminal of the fourth inverter is electrically connected to the output terminal of the third inverter, and the output terminal of the fourth inverter is electrically connected to the input terminal of the third inverter;
  • the third latch includes a fifth inverter and a sixth inverter
  • the input terminal of the fifth inverter is electrically connected to the input terminal of the third latch, and the output terminal of the fifth inverter is electrically connected to the output terminal of the third latch;
  • the input terminal of the sixth inverter is electrically connected to the output terminal of the fifth inverter, and the output terminal of the sixth inverter is electrically connected to the input terminal of the fifth inverter;
  • the fourth latch includes a seventh inverter and an eighth inverter
  • the input terminal of the seventh inverter is electrically connected to the input terminal of the fourth latch, and the output terminal of the seventh inverter is electrically connected to the output terminal of the fourth latch;
  • the input terminal of the eighth inverter is electrically connected to the output terminal of the seventh inverter, and the output terminal of the eighth inverter is electrically connected to the input terminal of the seventh inverter;
  • the fifth latch includes a ninth inverter and a tenth inverter
  • the input terminal of the ninth inverter is electrically connected to the input terminal of the fifth latch, and the output terminal of the ninth inverter is electrically connected to the output terminal of the fifth latch;
  • the input terminal of the tenth inverter is electrically connected to the output terminal of the ninth inverter, and the output terminal of the tenth inverter is electrically connected to the input terminal of the ninth inverter;
  • the sixth latch includes an eleventh inverter and a twelfth inverter
  • the input terminal of the eleventh inverter is electrically connected to the input terminal of the sixth latch, and the output terminal of the eleventh inverter is electrically connected to the output terminal of the sixth latch;
  • the input terminal of the twelfth inverter is electrically connected to the output terminal of the eleventh inverter, and the output terminal of the twelfth inverter is electrically connected to the input terminal of the eleventh inverter. connect;
  • the seventh latch includes a thirteenth inverter and a fourteenth inverter
  • the input terminal of the thirteenth inverter is electrically connected to the input terminal of the seventh latch, and the output terminal of the thirteenth inverter is electrically connected to the output terminal of the seventh latch;
  • the input terminal of the fourteenth inverter is electrically connected to the output terminal of the thirteenth inverter, and the output terminal of the fourteenth inverter is electrically connected to the input terminal of the thirteenth inverter. connect;
  • the eighth latch includes a fifteenth inverter and a sixteenth inverter
  • the input terminal of the fifteenth inverter is electrically connected to the input terminal of the eighth latch, and the output terminal of the fifteenth inverter is electrically connected to the output terminal of the eighth latch;
  • the input terminal of the sixteenth inverter is electrically connected to the output terminal of the fifteenth inverter, and the output terminal of the sixteenth inverter is electrically connected to the input terminal of the fifteenth inverter. connect;
  • the ninth latch includes a seventeenth inverter and an eighteenth inverter
  • the input terminal of the seventeenth inverter is electrically connected to the input terminal of the ninth latch, and the output terminal of the seventeenth inverter is electrically connected to the output terminal of the ninth latch;
  • the input terminal of the eighteenth inverter is electrically connected to the output terminal of the seventeenth inverter, and the output terminal of the eighteenth inverter is electrically connected to the input terminal of the seventeenth inverter. connect;
  • the tenth latch includes a nineteenth inverter and a twentieth inverter;
  • the input terminal of the nineteenth inverter is electrically connected to the input terminal of the tenth latch, and the output terminal of the nineteenth inverter is electrically connected to the output terminal of the tenth latch;
  • the input terminal of the twentieth inverter is electrically connected to the output terminal of the nineteenth inverter, and the output terminal of the twentieth inverter is electrically connected to the input terminal of the nineteenth inverter. connect.
  • the first control switch is a first control transistor
  • the second control switch is a second control transistor
  • the third control switch is a third control transistor
  • the fourth control switch is a fourth control transistor.
  • the fifth control switch is a fifth control transistor, and the sixth control switch is a sixth control transistor;
  • the control electrode of the first control transistor is electrically connected to the output terminal of the first latch, and the first electrode of the first control transistor is electrically connected to the input terminal of the third latch. an electrical connection between the second pole of the control transistor and the output terminal of the second latch;
  • the control electrode of the second control transistor is electrically connected to the input terminal of the first latch, and the first electrode of the second control transistor is electrically connected to the input terminal of the fourth latch.
  • the second pole of the two control transistors is electrically connected to the input terminal of the second latch;
  • the control electrode of the third control transistor is electrically connected to the output terminal of the third latch, and the first electrode of the third control transistor is electrically connected to the input terminal of the fifth latch.
  • the second pole of the three control transistors is electrically connected to the output terminal of the sixth latch;
  • the control electrode of the fourth control transistor is electrically connected to the input terminal of the third latch, the first electrode of the fourth control transistor is electrically connected to the input terminal of the seventh latch, and the fourth control transistor is electrically connected to the input terminal of the seventh latch.
  • the second pole of the transistor is electrically connected to the input terminal of the sixth latch;
  • the control electrode of the fifth control transistor is electrically connected to the output terminal of the fourth latch, and the first electrode of the fifth control transistor is electrically connected to the input terminal of the eighth latch.
  • the second pole of the fifth control transistor is electrically connected to the output terminal of the ninth latch;
  • the control electrode of the sixth control transistor is electrically connected to the input terminal of the fourth latch, and the first electrode of the sixth control transistor is electrically connected to the input terminal of the tenth latch.
  • the second pole of the six control transistors is electrically connected to the input terminal of the ninth latch.
  • the first data writing circuit includes a first writing transistor
  • the second data writing circuit includes a second writing transistor
  • the third data writing circuit includes a third writing transistor
  • the fourth data writing circuit includes a fourth writing transistor
  • the control electrode of the first writing transistor is electrically connected to the first scan terminal, the first electrode of the first writing transistor is electrically connected to the first data voltage terminal, and the control electrode of the first writing transistor is electrically connected to the first data voltage terminal.
  • the second pole is electrically connected to the first data access terminal;
  • the control electrode of the second writing transistor is electrically connected to the second scan terminal, the first electrode of the second writing transistor is electrically connected to the second data voltage terminal, and the control electrode of the second writing transistor is electrically connected to the second data voltage terminal.
  • the second pole is electrically connected to the second data access terminal;
  • the control electrode of the third writing transistor is electrically connected to the third scan terminal, the first electrode of the third writing transistor is electrically connected to the third data voltage terminal, and the control electrode of the third writing transistor is electrically connected to the third data voltage terminal.
  • the second pole is electrically connected to the third data access terminal;
  • the control electrode of the fourth write transistor is electrically connected to the fourth scan terminal
  • the first electrode of the fourth write transistor is electrically connected to the fourth data voltage terminal
  • the control electrode of the fourth write transistor is electrically connected to the fourth data voltage terminal.
  • the second pole is electrically connected to the fourth data access terminal.
  • the light-emitting circuit includes a light-emitting element
  • the light-emitting control circuit is electrically connected to the first pole of the light-emitting element, and is used to control the communication between the control voltage input terminal and the first pole of the light-emitting element under the control of the light-emitting control signal;
  • the second pole of the light-emitting element is electrically connected to the first voltage terminal.
  • the light-emitting circuit includes an amplitude control sub-circuit, a driving sub-circuit, a first on-off control sub-circuit and a light-emitting element; the first end of the driving sub-circuit is electrically connected to the second voltage end;
  • the amplitude control sub-circuit is used to control the driving current generated by the driving sub-circuit according to the display data voltage
  • the lighting control circuit is used to control the connection between the control voltage input terminal and the control terminal of the first on-off control sub-circuit under the control of the lighting control signal;
  • the control end of the first on-off control sub-circuit is electrically connected to the light-emitting control circuit, the first end of the first on-off control sub-circuit is electrically connected to the second end of the driving sub-circuit, and the third The second end of an on-off control sub-circuit is electrically connected to the light-emitting element; the first on-off control sub-circuit is used to control the connection between the driving sub-circuit and the light-emitting element under the control of the potential of its control end. connected between.
  • the amplitude control subcircuit includes a data writing subcircuit, an energy storage subcircuit and a reset subcircuit;
  • the data writing sub-circuit is electrically connected to the first scanning line, the data line and the control end of the driving sub-circuit respectively, and is used to write the said data under the control of the first scanning signal provided by the first scanning line.
  • the data voltage provided by the data line is written into the control end of the driving subcircuit;
  • the reset sub-circuit is electrically connected to the first scan line, the reset voltage terminal and the second terminal of the driver sub-circuit respectively, and is used to control the reset voltage terminal to provide the voltage under the control of the first scan signal.
  • the reset voltage is written into the second terminal of the driving sub-circuit;
  • the energy storage sub-circuit is electrically connected to the control end of the driving sub-circuit and the second end of the driving sub-circuit, respectively, for storing electrical energy;
  • the driving sub-circuit is used to generate a driving current under the control of the potential of its control terminal.
  • the amplitude control subcircuit includes a data writing subcircuit and an energy storage subcircuit;
  • the data writing sub-circuit is electrically connected to the control end of the scanning line, the data line and the driving sub-circuit respectively.
  • the data writing sub-circuit is used to write the data under the control of the scanning signal provided by the scanning line.
  • the voltage of the data provided by the data line is written into the control end of the driving sub-circuit;
  • the energy storage sub-circuit is electrically connected to the control terminal and the first common electrode terminal of the driving sub-circuit respectively, and is used to store electrical energy;
  • the driving sub-circuit is used to generate a driving current under the control of the potential of its control terminal.
  • the scan line includes a second scan line and a third scan line
  • the data writing sub-circuit includes a first data writing transistor and a second data writing transistor
  • the control electrode of the first data writing transistor is electrically connected to the second scan line, the first electrode of the first data writing transistor is electrically connected to the data line, and the control electrode of the first data writing transistor is electrically connected to the data line.
  • the second pole is electrically connected to the control terminal of the driving subcircuit;
  • the control electrode of the second data writing transistor is electrically connected to the third scan line, the first electrode of the second data writing transistor is electrically connected to the data line, and the control electrode of the second data writing transistor is electrically connected to the data line.
  • the second pole is electrically connected to the control terminal of the driving subcircuit;
  • the first data writing transistor is an n-type transistor
  • the second data writing transistor is a p-type transistor
  • the nth switch control sub-circuit includes an nth switch control transistor
  • the control electrode of the nth switch control transistor is electrically connected to the nth switch control terminal, the first electrode of the nth switch control transistor is electrically connected to the nth lighting control voltage terminal, and the second electrode of the nth switch control transistor is electrically connected to The control voltage input terminal is electrically connected.
  • the light emission control circuit includes a light emission control transistor
  • the control electrode of the light-emitting control transistor is electrically connected to the light-emitting control terminal
  • the first electrode of the light-emitting control transistor is electrically connected to the control voltage input terminal
  • the second electrode of the light-emitting control transistor is electrically connected to the light-emitting circuit. Electrical connection.
  • the light-emitting element included in the light-emitting circuit is a micro light-emitting diode or a sub-millimeter light-emitting diode; the first pole of the light-emitting element is an anode, and the second pole of the light-emitting element is a cathode.
  • an embodiment of the present disclosure also provides a display device, including a display panel;
  • the display area of the display panel has multiple sub-pixels, and the above-mentioned pixel circuit is provided in each sub-pixel.
  • the display panel includes a silicon substrate
  • the pixel circuit is disposed on the silicon substrate.
  • Figure 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure
  • Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure
  • Figure 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 5 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 6 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 5;
  • Figure 7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 8 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 9 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 10 is an operating timing diagram of at least one embodiment of the pixel circuit shown in Figure 9;
  • Figure 11 is a structural diagram of at least one embodiment of a light-emitting circuit
  • Figure 12 is a structural diagram of at least one embodiment of the light-emitting circuit
  • Figure 13 is a structural diagram of at least one embodiment of the light-emitting circuit
  • Figure 14 is a structural diagram of at least one embodiment of the light-emitting circuit
  • Figure 15 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 16 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 17 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 18 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 19 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 20 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • Figure 21 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 22 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • the transistors used in all embodiments of the present disclosure may be transistors, thin film transistors, field effect transistors, or other devices with the same characteristics.
  • one pole is called the first pole and the other pole is called the second pole.
  • the control electrode when the transistor is a triode, the control electrode may be a base electrode, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base electrode. pole, the first pole may be an emitter, and the second pole may be a collector.
  • the control electrode when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, The control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
  • the pixel circuit described in the embodiment of the present disclosure includes a light-emitting circuit, a light-emitting control circuit, a first control circuit and a switch control circuit;
  • the lighting control circuit is electrically connected to the lighting control terminal, the control voltage input terminal and the lighting circuit respectively, and is used to control the control voltage input terminal and the lighting circuit under the control of the lighting control signal provided by the lighting control terminal.
  • the light-emitting circuits are connected;
  • the light-emitting circuit is used to emit light according to the control voltage provided by the input terminal of the control voltage terminal;
  • the first control circuit is electrically connected to at least two data voltage terminals, at least two scanning terminals and N switch control terminals respectively, and is used to control the scanning signal according to the data voltage terminal under the control of the scanning signal provided by the scanning terminal.
  • the data voltage provided controls the switch control signal provided to the switch control terminal;
  • N is an integer greater than 1;
  • the switch control circuit includes N switch control terminals, N lighting control voltage terminals and N switch control sub-circuits; n is a positive integer less than or equal to N;
  • the nth switch control sub-circuit is electrically connected to the nth switch control terminal, the nth light-emitting control voltage terminal and the control voltage input terminal respectively, and is used under the control of the nth switch control signal provided by the nth switch control terminal. , controlling the connection between the nth light-emitting control voltage terminal and the control voltage input terminal.
  • the first control circuit controls the switch control signal according to the data voltage under the control of the scan signal
  • each switch control sub-circuit controls the switch control signal under the control of the corresponding switch control signal.
  • the corresponding light-emitting control voltage terminal is connected to the control voltage input terminal to control the light-emitting brightness of the light-emitting circuit.
  • the light-emitting circuit may include a light-emitting element, and the light-emitting control circuit is electrically connected to the first electrode of the light-emitting element for controlling the control voltage input terminal under the control of the light-emitting control signal. is connected to the first pole of the light-emitting element, and the second pole of the light-emitting element is electrically connected to the first voltage terminal; at this time, the pixel circuit described in the embodiment of the present disclosure can omit the storage capacitor. Realizing the control of luminous brightness can reduce multiple masks, thereby reducing costs. Moreover, when the pixel circuit described in the embodiment of the present disclosure is working, there is no capacitor charging and discharging function, which greatly reduces power consumption.
  • the light-emitting element included in the light-emitting circuit may be a micro light-emitting diode or a sub-millimeter light-emitting diode.
  • the first pole of the light-emitting element is an anode, and the second pole of the light-emitting element is a cathode, but is not limited to this.
  • At least one embodiment of the present disclosure provides a MIP (Memory In Pixel) Micro LED (micro light-emitting diode) pixel circuit, which can be applied to watches and other devices with a small number of gray levels. application scenarios.
  • MIP Memory In Pixel
  • Micro LED micro light-emitting diode
  • the light-emitting circuit may include an amplitude control sub-circuit, a driving sub-circuit, a first on-off control sub-circuit and a light-emitting element;
  • the amplitude control sub-circuit is used to control the driving current generated by the driving sub-circuit according to the display data voltage
  • the lighting control circuit is used to control the connection between the control voltage input terminal and the control terminal of the first on-off control sub-circuit under the control of the lighting control signal;
  • the control end of the first on-off control sub-circuit is electrically connected to the lighting control circuit, the first end of the first on-off control sub-circuit is electrically connected to the second end of the driving sub-circuit, and the first on-off control sub-circuit is electrically connected to the second end of the driving sub-circuit.
  • the second end of an on-off control sub-circuit is electrically connected to the light-emitting element; the first on-off control sub-circuit is used to control the connection between the driving sub-circuit and the light-emitting element under the control of the potential of its control end.
  • the luminous brightness of the luminous element can be controlled by controlling the control voltage (the control voltage can be a square wave voltage signal) connected to the control terminal of the first on-off control sub-circuit and by controlling the luminous duration of the luminous element. , which can improve the uniformity of low grayscale display.
  • the control voltage can be a square wave voltage signal
  • the light-emitting control circuit when the light-emitting circuit includes an amplitude control sub-circuit, a driving sub-circuit, a first on-off control sub-circuit and a light-emitting element, the light-emitting control circuit, the first control circuit and the switch control circuit can be
  • the on-off time of the first on-off control sub-circuit is controlled to control the lighting duration of the light-emitting element, and the driving circuit generates a driving current according to the display data voltage to enable multi-gray scale display, which can be applied to various multi-gray scales. Show scene.
  • the n-th switch control sub-circuit includes an n-th switch control transistor
  • the control electrode of the nth switch control transistor is electrically connected to the nth switch control terminal, the first electrode of the nth switch control transistor is electrically connected to the nth lighting control voltage terminal, and the second electrode of the nth switch control transistor is electrically connected to The control voltage input terminal is electrically connected.
  • the light emission control circuit includes a light emission control transistor
  • the control electrode of the light-emitting control transistor is electrically connected to the light-emitting control terminal
  • the first electrode of the light-emitting control transistor is electrically connected to the control voltage input terminal
  • the second electrode of the light-emitting control transistor is electrically connected to the light-emitting element.
  • the first pole is electrically connected.
  • N 4 or 8 as an example.
  • N may be equal to 2 a , and a is a positive integer, but is not limited to this.
  • a can be a positive integer greater than 1 to increase the number of control voltages that can be provided to the control voltage input terminal I1 and increase the number of display gray levels.
  • the first voltage terminal may be a low voltage terminal, but is not limited to this.
  • the pixel circuit includes a light-emitting element 10, a light-emitting control circuit 11, a first control circuit 12 and a switch control circuit;
  • the light-emitting control circuit 11 is electrically connected to the light-emitting control terminal EM, the control voltage input terminal I1 and the first pole of the light-emitting element 10 respectively, and is used to control the light-emitting control signal provided by the light-emitting control terminal EM.
  • the control voltage input terminal I1 is connected to the first pole of the light-emitting element 10; the second pole of the light-emitting element 10 is electrically connected to the first voltage terminal V1;
  • the first control circuit 12 is respectively connected to the first data voltage terminal D1, the second data voltage terminal D2, the first scanning terminal G1, the second scanning terminal G2, the first switch control terminal A, the second switch control terminal B, and the The three switch control terminals C and the fourth switch control terminal D are electrically connected for controlling the first scanning signal provided by the first scanning terminal G1 and the second scanning signal provided by the second scanning terminal G2 according to The first data voltage Vdata1 provided by the first data voltage terminal D1 and the second data voltage Vdata2 provided by the second data voltage terminal D2 control the first switch control signal provided to the first switch control terminal A, A second switch control signal provided to the second switch control terminal B, a third switch control signal provided to the third switch control terminal C, and a fourth switch control signal provided to the fourth switch control terminal D. ;
  • the switch control circuit includes a first switch control terminal A, a second switch control terminal B, a third switch control terminal C, a fourth switch control terminal D, a first lighting control voltage terminal VC1, a second lighting control voltage terminal VC2, The third lighting control voltage terminal VC3, the fourth lighting control voltage terminal VC4, the first switch control sub-circuit 131, the second switch control sub-circuit 132, the third switch control sub-circuit 133 and the fourth switch control sub-circuit 134;
  • the first switch control sub-circuit 131 is electrically connected to the first switch control terminal A, the first lighting control voltage terminal VC1 and the control voltage input terminal I1 respectively, and is used to provide the first switch control terminal A with Under the control of the first switch control signal, control the connection between the first lighting control voltage terminal VC1 and the control voltage input terminal I1;
  • the second switch control sub-circuit 132 is electrically connected to the second switch control terminal B, the second lighting control voltage terminal VC2 and the control voltage input terminal I1 respectively, and is used to provide power at the second switch control terminal B. Under the control of the second switch control signal, control the connection between the second lighting control voltage terminal VC2 and the control voltage input terminal I1;
  • the third switch control sub-circuit 133 is electrically connected to the third switch control terminal C, the third lighting control voltage terminal VC3 and the control voltage input terminal I1 respectively, and is used to provide the third switch control terminal C with Under the control of the third switch control signal, control the connection between the third lighting control voltage terminal VC3 and the control voltage input terminal I1;
  • the fourth switch control sub-circuit 134 is electrically connected to the fourth switch control terminal D, the fourth lighting control voltage terminal VC4 and the control voltage input terminal I1 respectively, and is used to provide power at the fourth switch control terminal D. Under the control of the fourth switch control signal, the fourth lighting control voltage terminal VC4 is controlled to be connected to the control voltage input terminal I1.
  • the first control circuit 12 controls the supply of the first switch control signal, the second switch control signal, the third switch control signal and the fourth switch control signal. signal; the first switch control sub-circuit 131 controls the first lighting control voltage terminal VC1 to provide the first lighting control voltage to the control voltage input terminal I1 under the control of the first switching control signal; the The second switch control sub-circuit 132 controls the second light-emitting control voltage terminal VC2 to provide the second light-emitting control voltage to the control voltage input terminal I1 under the control of the second switch control signal; the third switch control sub-circuit 133 Under the control of the third switch control signal, the third lighting control voltage terminal VC3 is controlled to provide the third lighting control voltage to the control voltage input terminal I1; the fourth switch control sub-circuit 134 is in the Under the control of the fourth switch control signal, the fourth lighting control voltage terminal VC4 is controlled to provide the fourth lighting control voltage to the control voltage input terminal I1; the lighting
  • the pixel circuit includes a light-emitting element 10, a light-emitting control circuit 11, a first control circuit 12 and a switch control circuit;
  • the light-emitting control circuit 11 is electrically connected to the light-emitting control terminal EM, the control voltage input terminal I1 and the first pole of the light-emitting element 10 respectively, and is used to control the light-emitting control signal provided by the light-emitting control terminal EM.
  • the control voltage input terminal I1 is connected to the first pole of the light-emitting element 10; the second pole of the light-emitting element 10 is electrically connected to the first voltage terminal V1;
  • the first control circuit 12 is respectively connected to the first data voltage terminal D1, the second data voltage terminal D2, the third data voltage terminal D3, the fourth data voltage terminal D4, the first scanning terminal G1, the second scanning terminal G2, and the third data voltage terminal D4.
  • the terminal F, the seventh switch control terminal G and the eighth switch control terminal H are electrically connected for the first scanning signal provided at the first scanning terminal G1, the second scanning signal provided by the second scanning terminal G2, Under the control of the third scan signal provided by the third scan terminal G3 and the fourth scan signal provided by the fourth scan terminal G4, according to the first data voltage Vdata1 provided by the first data voltage terminal D1, the The second data voltage Vdata2 provided by the second data voltage terminal D2, the third data voltage Vdata3 provided by the third data voltage terminal D3, and the fourth data voltage Vdata4 provided by the fourth data voltage terminal
  • the switch control circuit includes a first switch control terminal A, a second switch control terminal B, a third switch control terminal C, a fourth switch control terminal D, a fifth switch control terminal E, a sixth switch control terminal F, a seventh switch control terminal switch control terminal G, eighth switch control terminal H, first lighting control voltage terminal VC1, second lighting control voltage terminal VC2, third lighting control voltage terminal VC3, fourth lighting control voltage terminal VC4, fifth lighting control voltage terminal VC5, the sixth lighting control voltage terminal VC6, the seventh lighting control voltage terminal VC7, the eighth lighting control voltage terminal VC8, the first switch control sub-circuit 131, the second switch control sub-circuit 132, the third switch control sub-circuit 133, the fourth switch control sub-circuit 134, the fifth switch control sub-circuit 135, the sixth switch control sub-circuit 136, the seventh switch control sub-circuit 137 and the eighth switch control sub-circuit 138;
  • the first switch control sub-circuit 131 is electrically connected to the first switch control terminal A, the first lighting control voltage terminal VC1 and the control voltage input terminal I1 respectively, and is used to provide the first switch control terminal A with Under the control of the first switch control signal, control the connection between the first lighting control voltage terminal VC1 and the control voltage input terminal I1;
  • the second switch control sub-circuit 132 is electrically connected to the second switch control terminal B, the second lighting control voltage terminal VC2 and the control voltage input terminal I1 respectively, and is used to provide power at the second switch control terminal B. Under the control of the second switch control signal, control the connection between the second lighting control voltage terminal VC2 and the control voltage input terminal I1;
  • the third switch control sub-circuit 133 is electrically connected to the third switch control terminal C, the third lighting control voltage terminal VC3 and the control voltage input terminal I1 respectively, and is used to provide the third switch control terminal C with Under the control of the third switch control signal, control the connection between the third lighting control voltage terminal VC3 and the control voltage input terminal I1;
  • the fourth switch control sub-circuit 134 is electrically connected to the fourth switch control terminal D, the fourth lighting control voltage terminal VC4 and the control voltage input terminal I1 respectively, and is used to provide power at the fourth switch control terminal D. Under the control of the fourth switch control signal, control the connection between the fourth lighting control voltage terminal VC4 and the control voltage input terminal I1;
  • the fifth switch control sub-circuit 135 is electrically connected to the fifth switch control terminal E, the second lighting control voltage terminal VC2 and the control voltage input terminal I1 respectively, and is used to provide the fifth switch control terminal E with Under the control of the fifth switch control signal, the fifth lighting control voltage terminal VC5 is controlled to be connected to the control voltage input terminal I1;
  • the sixth switch control sub-circuit 136 is electrically connected to the sixth switch control terminal F, the sixth lighting control voltage terminal VC6 and the control voltage input terminal I1 respectively, and is used to provide the sixth switch control terminal F. Under the control of the sixth switch control signal, the sixth lighting control voltage terminal VC6 is controlled to be connected to the control voltage input terminal I1;
  • the seventh switch control sub-circuit 137 is electrically connected to the seventh switch control terminal G, the seventh lighting control voltage terminal VC7 and the control voltage input terminal I1 respectively, and is used to provide the seventh switch control terminal G with Under the control of the seventh switch control signal, the seventh lighting control voltage terminal VC7 is controlled to be connected to the control voltage input terminal I1;
  • the eighth switch control sub-circuit 138 is electrically connected to the eighth switch control terminal H, the eighth lighting control voltage terminal VC8 and the control voltage input terminal I1 respectively, and is used to provide the eighth switch control terminal H with Under the control of the eighth switch control signal, the eighth lighting control voltage terminal VC8 is controlled to be connected to the control voltage input terminal I1.
  • the first control circuit 12 controls the supply of the first switch control signal, the second switch control signal, the third switch control signal, and the fourth switch control signal. signal, the fifth switch control signal, the sixth switch control signal, the seventh switch control signal and the eighth switch control signal; the first switch control sub-circuit 131 controls the The first lighting control voltage terminal VC1 provides the first lighting control voltage to the control voltage input terminal I1; the second switch control sub-circuit 132 controls the second lighting control voltage terminal under the control of the second switch control signal.
  • the third switch control sub-circuit 133 controls the third lighting control voltage terminal VC3 to provide a third lighting control voltage under the control of the third switch control signal.
  • the luminescence control voltage is supplied to the control voltage input terminal I1;
  • the fourth switch control sub-circuit 134 under the control of the fourth switch control signal, controls the fourth luminescence control voltage terminal VC4 to provide a fourth luminescence control voltage to The control voltage input terminal I1;
  • the fifth switch control sub-circuit 135, under the control of the fifth switch control signal controls the fifth lighting control voltage terminal VC5 to provide a fifth lighting control voltage to the control voltage input terminal I1;
  • the sixth switch control sub-circuit 136 controls the sixth lighting control voltage terminal VC6 to provide the sixth lighting control voltage to the control voltage input terminal I1 under the control of the sixth switch control signal;
  • the seventh switch control sub-circuit 137 controls the seventh lighting control voltage terminal VC7 to provide the seventh lighting control
  • the first control circuit 12 controls the supply of the first switch control signal, the second switch control signal, the third switch control signal, and the fourth switch control signal. signal, the fifth switch control signal, the sixth switch control signal, the seventh switch control signal and the eighth switch control signal; the first switch control sub-circuit 131 controls the The first lighting control voltage terminal VC1 provides the first lighting control voltage to the control voltage input terminal I1; the second switch control sub-circuit 132 controls the second lighting control voltage terminal under the control of the second switch control signal.
  • the third switch control sub-circuit 133 controls the third lighting control voltage terminal VC3 to provide a third lighting control voltage under the control of the third switch control signal.
  • the luminescence control voltage is supplied to the control voltage input terminal I1;
  • the fourth switch control sub-circuit 134 under the control of the fourth switch control signal, controls the fourth luminescence control voltage terminal VC4 to provide a fourth luminescence control voltage to The control voltage input terminal I1;
  • the fifth switch control sub-circuit 135, under the control of the fifth switch control signal controls the fifth lighting control voltage terminal VC5 to provide a fifth lighting control voltage to the control voltage input terminal I1;
  • the sixth switch control sub-circuit 136 controls the sixth lighting control voltage terminal VC6 to provide the sixth lighting control voltage to the control voltage input terminal I1 under the control of the sixth switch control signal;
  • the seventh switch control sub-circuit 137 controls the seventh lighting control voltage terminal VC7 to provide the seventh lighting control
  • the lighting control voltage provided by the lighting control voltage terminal is a DC voltage
  • the lighting control voltages provided by the N lighting control voltage terminals are different from each other.
  • the light-emitting control voltage may be a DC voltage, and by adjusting the voltage value of the light-emitting control voltage, the light-emitting brightness of the light-emitting element can be controlled.
  • the lighting control voltage provided by the lighting control voltage terminal is a square wave voltage signal, and the duty ratios of the lighting control voltages provided by the N lighting control voltage terminals are different from each other.
  • the light-emitting control voltage may be a square wave voltage signal, and the duty ratios of the N light-emitting control voltages are different from each other.
  • the luminescence control voltage is a square wave voltage signal, since the low gray scale brightness uniformity of the square wave voltage signal is better, the display uniformity can be improved by controlling the high voltage and luminescence duration.
  • the first control circuit includes a first data writing circuit, a second data writing circuit and a first control sub-circuit;
  • the first data writing circuit is electrically connected to the first scanning terminal, the first data voltage terminal and the first data access terminal respectively, and is used to write the data under the control of the first scanning signal provided by the first scanning terminal.
  • the first data voltage provided by the first data voltage terminal is written into the first data access terminal;
  • the second data writing circuit is electrically connected to the second scanning terminal, the second data voltage terminal and the second data access terminal respectively, and is used to write the second data under the control of the second scanning signal provided by the second scanning terminal.
  • the second data voltage provided by the second data voltage terminal is written into the second data access terminal;
  • the first control sub-circuit is electrically connected to the first data access terminal, the second data access terminal and N switch control terminals respectively, and is used to control the electric potential of the first data access terminal and the The potential of the second data access terminal controls the provision of corresponding switch control signals to the N switch control terminals.
  • the first control circuit may include a first data writing circuit, a second data writing circuit and a first control sub-circuit.
  • the first data writing circuit writes the first data under the control of the first scanning signal.
  • a data voltage is written into the first data access terminal
  • the second data writing circuit writes a second data voltage into the second data access terminal under the control of the second scan signal;
  • the first control subcircuit writes the second data voltage into the second data access terminal according to the The potential of the first data access terminal and the potential of the second data access terminal control to provide corresponding switch control signals to the N switch control terminals respectively.
  • the first control circuit includes a first data writing circuit 31, a second data Writing circuit 32 and first control sub-circuit 33;
  • the first data writing circuit 31 is electrically connected to the first scanning terminal G1, the first data voltage terminal D1 and the first data access terminal DI1 respectively, and is used to provide the first scanning signal at the first scanning terminal G1. Under the control of , write the first data voltage Vdata1 provided by the first data voltage terminal D1 into the first data access terminal DI1;
  • the second data writing circuit 32 is electrically connected to the second scanning terminal G2, the second data voltage terminal D2 and the second data access terminal DI2 respectively, and is used for providing the second scanning signal at the second scanning terminal G2. Under the control of , write the second data voltage Vdata2 provided by the second data voltage terminal D2 into the second data access terminal DI2;
  • the first control sub-circuit 33 is connected to the first data access terminal DI1, the second data access terminal DI2, the first switch control terminal A, the second switch control terminal B, and the third switch control terminal C respectively. It is electrically connected to the fourth switch control terminal D, and is used to control the provision of the first switch control to the first switch control terminal A according to the potential of the first data access terminal DI1 and the potential of the second data access terminal DI2.
  • the signal controls to provide the second switch control signal to the second switch control terminal B, controls to provide the third switch control signal to the third switch control terminal C, and controls to provide the fourth switch control signal to the fourth switch control terminal D.
  • the first control sub-circuit includes a first latch, a second latch, a third latch, a fourth latch, a first control switch and a second control switch; N equals 4;
  • the input end of the first latch is electrically connected to the first data access end, the output end of the first latch is electrically connected to the control end of the first control switch, and the first latch
  • the register is used to latch the voltage signal connected to the first data access terminal and output a first output voltage, where the first output voltage is inverse phase with the voltage signal connected to the first data access terminal;
  • the input end of the second latch is electrically connected to the second data access end, the output end of the second latch is electrically connected to the control end of the second control switch, and the second latch
  • the register is used to latch the voltage signal connected to the second data access terminal and output a second output voltage, where the second output voltage is inverted with the voltage signal connected to the second data access terminal;
  • the input terminal of the third latch is electrically connected to the first terminal of the first control switch, the output terminal of the third latch is electrically connected to the control terminal of the first switch, and the third latch is electrically connected to the first terminal of the first control switch. latch the voltage signal connected to its input end and output a third output voltage, the third output voltage being inverted with the voltage signal connected to the input end of the third latch;
  • the input end of the fourth latch is electrically connected to the first end of the second control switch, the output end of the fourth latch is electrically connected to the third switch control end, and the fourth latch is electrically connected to the first end of the second control switch. latch the voltage signal connected to its input end and output a fourth output voltage, the fourth output voltage being inverted with the voltage signal connected to the input end of the fourth latch;
  • the control terminal of the first control switch is electrically connected to the output terminal of the first latch, the second terminal of the first control switch is electrically connected to the output terminal of the second latch, and the second terminal of the first control switch is electrically connected to the output terminal of the second latch.
  • a control switch is used to control the connection or disconnection between the first end of the first control switch and the second end of the first control switch under the control of the potential of its control end;
  • the control terminal of the second control switch is electrically connected to the input terminal of the first latch, and the second terminal of the second control switch is electrically connected to the input terminal of the second latch.
  • the second control switch is used to control the connection or disconnection between the first end of the second control switch and the second end of the second control switch under the control of the potential of its control end;
  • the first switch control terminal is electrically connected to the output terminal of the third latch, and the second switch control terminal is electrically connected to the input terminal of the third latch;
  • the third switch control terminal is electrically connected to the output terminal of the fourth latch, and the fourth switch control terminal is electrically connected to the input terminal of the fourth latch.
  • the first control sub-circuit may include a first latch, a second latch, a third latch, a fourth latch, a first control switch and a second control switch.
  • the first latch latches the voltage signal connected to the first data access terminal and outputs a first output voltage.
  • the first output voltage is inverse phase with the voltage signal connected to the first data access terminal.
  • the second latch latches the voltage signal connected to the second data access terminal and outputs a second output voltage, and the second output voltage is the same as the voltage connected to the second data access terminal.
  • the signal is inverted; the third latch latches the voltage signal connected to its input end and outputs a third output voltage, and the third output voltage is the same as the voltage connected to the input end of the third latch.
  • the signal is inverted; the fourth latch latches the voltage signal connected to its input end and outputs a fourth output voltage, and the fourth output voltage is the same as the voltage connected to the input end of the fourth latch.
  • the signal is inverted; the first control switch controls the connection or disconnection between the first end of the first control switch and the second end of the first control switch under the control of the potential of its control end; the The second control switch controls the connection or disconnection between the first end of the second control switch and the second end of the second control switch under the control of the potential of its control end.
  • the first control sub-circuit includes a first latch S1, a second latch S2, a third latch S3, the fourth latch S4, the first control switch K1 and the second control switch K2;
  • the input terminal of the first latch S1 is electrically connected to the first data access terminal DI1, and the output terminal of the first latch S1 is electrically connected to the control terminal of the first control switch K1, so
  • the first latch S1 is used to latch the voltage signal connected to the first data access terminal DI1, and output the first output voltage Vo1 through the output terminal of the first latch S1.
  • the first The output voltage Vo1 is inverse phase with the voltage signal connected to the first data access terminal DI1;
  • the input terminal of the second latch S2 is electrically connected to the second data access terminal DI2, and the output terminal of the second latch S2 is electrically connected to the control terminal of the second control switch K2, so
  • the second latch S2 is used to latch the voltage signal connected to the second data access terminal DI2, and output the second output voltage Vo2 through the output terminal of the second latch S2.
  • the second The output voltage Vo2 is inverse phase with the voltage signal connected to the second data access terminal DI2;
  • the input terminal of the third latch S3 is electrically connected to the first terminal of the first control switch K1, and the output terminal of the third latch S3 is electrically connected to the first switch control terminal A.
  • the third latch S3 is used to latch the voltage signal connected to its input end, and output a third output voltage Vo3 through the output end of the third latch S3.
  • the third output voltage Vo3 is related to the third The voltage signal connected to the input terminal of latch S3 is inverted;
  • the input terminal of the fourth latch S4 is electrically connected to the first terminal of the second control switch K2, and the output terminal of the fourth latch S4 is electrically connected to the third switch control terminal C.
  • the fourth latch S4 is used to latch the voltage signal connected to its input end and output a fourth output voltage Vo4.
  • the fourth output voltage Vo4 and the voltage signal connected to the input end of the fourth latch S4 are reverse phase;
  • the control end of the first control switch K1 is electrically connected to the output end of the first latch S1, and the second end of the first control switch K1 is electrically connected to the output end of the second latch S2.
  • the first control switch K1 is used to control the connection or disconnection between the first end of the first control switch K1 and the second end of the first control switch K1 under the control of the potential of its control end;
  • the control end of the second control switch K2 is electrically connected to the input end of the first latch S1, and the second end of the second control switch K2 is electrically connected to the input end of the second latch S2.
  • the second control switch K2 is used to control the connection or disconnection between the first end of the second control switch K2 and the second end of the second control switch K2 under the control of the potential of its control end;
  • the first switch control terminal A is electrically connected to the output terminal of the third latch S3, and the second switch control terminal B is electrically connected to the input terminal of the third latch S3;
  • the third switch control terminal C is electrically connected to the output terminal of the fourth latch S4, and the fourth switch control terminal D is electrically connected to the input terminal of the fourth latch S4.
  • the first control sub-circuit may include a first latch, a second latch, a third latch, a fourth latch, a first control switch and a second control switch.
  • the first latch latches the voltage signal connected to the first data access terminal and outputs a first output voltage.
  • the first output voltage is inverse phase with the voltage signal connected to the first data access terminal.
  • the second latch latches the voltage signal connected to the second data access terminal and outputs a second output voltage, and the second output voltage is the same as the voltage connected to the second data access terminal.
  • the signal is inverted; the third latch latches the voltage signal connected to its input end and outputs a third output voltage, and the third output voltage is the same as the voltage connected to the input end of the third latch.
  • the signal is inverted; the fourth latch latches the voltage signal connected to its input end and outputs a fourth output voltage, and the fourth output voltage is the same as the voltage connected to the input end of the fourth latch.
  • the signal is inverted; the first control switch controls the connection or disconnection between the first end of the first control switch and the second end of the first control switch under the control of the potential of its control end; the The second control switch controls the connection or disconnection between the first end of the second control switch and the second end of the second control switch under the control of the potential of its control end.
  • the first latch includes a first inverter and a second inverter
  • the input terminal of the first inverter is electrically connected to the input terminal of the first latch, and the output terminal of the first inverter is electrically connected to the output terminal of the first latch;
  • the input terminal of the second inverter is electrically connected to the output terminal of the first inverter, and the output terminal of the second inverter is electrically connected to the input terminal of the first inverter;
  • the second latch includes a third inverter and a fourth inverter
  • the input terminal of the third inverter is electrically connected to the input terminal of the second latch, and the output terminal of the third inverter is electrically connected to the output terminal of the second latch;
  • the input terminal of the fourth inverter is electrically connected to the output terminal of the third inverter, and the output terminal of the fourth inverter is electrically connected to the input terminal of the third inverter;
  • the third latch includes a fifth inverter and a sixth inverter
  • the input terminal of the fifth inverter is electrically connected to the input terminal of the third latch, and the output terminal of the fifth inverter is electrically connected to the output terminal of the third latch;
  • the input terminal of the sixth inverter is electrically connected to the output terminal of the fifth inverter, and the output terminal of the sixth inverter is electrically connected to the input terminal of the fifth inverter;
  • the fourth latch includes a seventh inverter and an eighth inverter
  • the input terminal of the seventh inverter is electrically connected to the input terminal of the fourth latch, and the output terminal of the seventh inverter is electrically connected to the output terminal of the fourth latch;
  • the input terminal of the eighth inverter is electrically connected to the output terminal of the seventh inverter, and the output terminal of the eighth inverter is electrically connected to the input terminal of the seventh inverter.
  • the first control switch is a first control transistor
  • the second control switch is a second control transistor
  • the control electrode of the first control transistor is electrically connected to the output terminal of the first latch, and the first electrode of the first control transistor is electrically connected to the input terminal of the third latch. an electrical connection between the second pole of the control transistor and the output terminal of the second latch;
  • the control electrode of the second control transistor is electrically connected to the input terminal of the first latch, and the first electrode of the second control transistor is electrically connected to the input terminal of the fourth latch.
  • the second pole of the two control transistors is electrically connected to the input terminal of the second latch.
  • the first data writing circuit includes a first writing transistor
  • the second data writing circuit includes a second writing transistor
  • the control electrode of the first writing transistor is electrically connected to the first scan terminal, the first electrode of the first writing transistor is electrically connected to the first data voltage terminal, and the control electrode of the first writing transistor is electrically connected to the first data voltage terminal.
  • the second pole is electrically connected to the first data access terminal;
  • the control electrode of the second writing transistor is electrically connected to the second scan terminal
  • the first electrode of the second writing transistor is electrically connected to the second data voltage terminal
  • the control electrode of the second writing transistor is electrically connected to the second data voltage terminal.
  • the second pole is electrically connected to the second data access terminal.
  • the light-emitting element is a micro light-emitting diode M1;
  • the first latch S1 includes a first inverter F1 and a second inverter F2;
  • the input terminal of the first inverter F1 is electrically connected to the input terminal of the first latch S1, and the output terminal of the first inverter F1 is electrically connected to the output terminal of the first latch S1. connect;
  • the input terminal of the second inverter F2 is electrically connected to the output terminal of the first inverter F1, and the output terminal of the second inverter F2 is electrically connected to the input terminal of the first inverter F1. connect;
  • the second latch S2 includes a third inverter F3 and a fourth inverter F4;
  • the input terminal of the third inverter F3 is electrically connected to the input terminal of the second latch S2, and the output terminal of the third inverter F3 is electrically connected to the output terminal of the second latch S2. connect;
  • the input terminal of the fourth inverter F4 is electrically connected to the output terminal of the third inverter F3, and the output terminal of the fourth inverter F4 is electrically connected to the input terminal of the third inverter F3. connect;
  • the third latch S3 includes a fifth inverter F5 and a sixth inverter F6;
  • the input terminal of the fifth inverter F5 is electrically connected to the input terminal of the third latch S3, and the output terminal of the fifth inverter F5 is electrically connected to the output terminal of the third latch S3. connect;
  • the input terminal of the sixth inverter F6 is electrically connected to the output terminal of the fifth inverter F5, and the output terminal of the sixth inverter F6 is electrically connected to the input terminal of the fifth inverter F5. connect;
  • the fourth latch S4 includes a seventh inverter F7 and an eighth inverter F8;
  • the input terminal of the seventh inverter F7 is electrically connected to the input terminal of the fourth latch S4, and the output terminal of the seventh inverter F7 is electrically connected to the output terminal of the fourth latch S4. connect;
  • the input terminal of the eighth inverter F8 is electrically connected to the output terminal of the seventh inverter F7, and the output terminal of the eighth inverter F8 is electrically connected to the input terminal of the seventh inverter F7. connect;
  • the first control switch is a first control transistor TC1, and the second control switch is a second control transistor TC2;
  • the gate of the first control transistor TC1 is electrically connected to the output terminal of the first latch S1, and the drain of the first control transistor TC1 is electrically connected to the input terminal of the third latch S3, The source of the first control transistor TC1 is electrically connected to the output terminal of the second latch;
  • the gate of the second control transistor TC2 is electrically connected to the input terminal of the first latch S1, and the drain of the second control transistor TC2 is electrically connected to the input terminal of the fourth latch S4, The source of the second control transistor TC2 is electrically connected to the input terminal of the second latch S2;
  • the first data writing circuit 31 includes a first writing transistor TW1, and the second data writing circuit 32 includes a second writing transistor TW2;
  • the gate of the first writing transistor TW1 is electrically connected to the first scanning terminal G1, and the drain of the first writing transistor TW1 is electrically connected to the first data voltage terminal D1.
  • the source of the input transistor TW1 is electrically connected to the first data access terminal DI1;
  • the gate of the second writing transistor TW2 is electrically connected to the second scan terminal G2, and the drain of the second writing transistor TW2 is electrically connected to the first data voltage terminal D1.
  • the source of the input transistor TW2 is electrically connected to the second data access terminal DI2;
  • the first switch control sub-circuit 131 includes a first switch control transistor TK1;
  • the gate of the first switch control transistor TK1 is electrically connected to the first switch control terminal A, and the drain of the first switch control transistor TK1 is electrically connected to the first lighting control voltage terminal VC1.
  • the source is electrically connected to the control voltage input terminal I1;
  • the second switch control sub-circuit 132 includes a second switch control transistor TK2;
  • the gate of the second switch control transistor TK2 is electrically connected to the second switch control terminal B, and the drain of the second switch control transistor TK2 is electrically connected to the second lighting control voltage terminal VC2.
  • the source is electrically connected to the control voltage input terminal I1;
  • the third switch control sub-circuit 133 includes a third switch control transistor TK3;
  • the gate of the third switch control transistor TK3 is electrically connected to the third switch control terminal C, and the drain of the third switch control transistor TK3 is electrically connected to the third lighting control voltage terminal VC2.
  • the source is electrically connected to the control voltage input terminal I1;
  • the fourth switch control sub-circuit 134 includes a fourth switch control transistor TK4;
  • the gate of the fourth switch control transistor TK4 is electrically connected to the fourth switch control terminal D, and the drain of the fourth switch control transistor TK4 is electrically connected to the fourth lighting control voltage terminal VC4.
  • the source is electrically connected to the control voltage input terminal I1;
  • the light emission control circuit 11 includes a light emission control transistor TE;
  • the gate of the light-emitting control transistor TE is electrically connected to the light-emitting control terminal EM, the drain of the light-emitting control transistor TE is electrically connected to the control voltage input terminal I1, and the source of the light-emitting control transistor TE is connected to M1
  • the anode of M1 is electrically connected, and the cathode of M1 is electrically connected to the low voltage terminal VSS.
  • the first data voltage terminal D1 and the second data voltage terminal are the same data voltage terminal.
  • all transistors are n-type transistors, but are not limited to this.
  • the display cycle includes a first writing phase tw1, a second writing phase tw2 and a light emitting phase te that are set successively;
  • G1 provides a high voltage signal
  • D1 provides the first data voltage Vdata1
  • TW1 is turned on to write Vdata1 to the input terminal of S1;
  • G2 provides a high voltage signal
  • D1 provides the second data voltage Vdata2
  • TW2 is turned on to write Vdata2 to the input terminal of S2;
  • Vdata1 is a low voltage signal and Vdata2 is a low voltage signal
  • S1 outputs a high voltage signal
  • S2 outputs a high voltage signal
  • TC1 is turned on
  • TC2 is turned off
  • the input terminal of S3 is connected to a high voltage signal
  • the first switch control terminal A The low voltage signal is connected
  • the second switch control terminal B is connected to the high voltage signal
  • the potential of the third switch control terminal C and the fourth switch control terminal D are low voltage
  • TK1 is turned off
  • TK2 is turned on
  • TK3 and TK4 are turned off. off
  • I1 is connected to the second light-emitting control voltage
  • TE is turned on
  • the drain of TE is connected to the second light-emitting control voltage to drive M1 to emit light
  • Vdata1 is a low voltage signal and Vdata2 is a high voltage signal
  • S1 outputs a high voltage signal
  • S2 outputs a low voltage signal
  • TC1 is turned on
  • TC2 is turned off
  • the input terminal of S3 is connected to the low voltage signal
  • the first switch control terminal A The high voltage signal is connected
  • the second switch control terminal B is connected to the low voltage signal
  • the potential of the third switch control terminal C and the fourth switch control terminal D are low voltage
  • TK1 is turned on
  • TK2 is turned off
  • TK3 and TK4 are turned off. off
  • I1 is connected to the first light-emitting control voltage
  • TE is turned on
  • the drain of TE is connected to the first light-emitting control voltage to drive M1 to emit light
  • Vdata1 is a high voltage signal and Vdata2 is a low voltage signal
  • S1 outputs a low voltage signal
  • S2 outputs a high voltage signal
  • TC1 is turned off
  • TC2 is turned on
  • the input terminal of S4 is connected to the low voltage signal
  • the third switch control terminal C The high voltage signal is connected
  • the fourth switch control terminal D is connected to the low voltage signal
  • the potential of the first switch control terminal A and the potential of the second switch control terminal B are low voltage
  • TK3 is turned on
  • TK4 is turned off
  • TK1 and TK2 are turned off. off
  • I1 is connected to the third light-emitting control voltage
  • TE is turned on
  • the drain of TE is connected to the third light-emitting control voltage to drive M1 to emit light
  • Vdata1 is a high voltage signal and Vdata2 is a high voltage signal
  • S1 outputs a low voltage signal
  • S2 outputs a low voltage signal
  • TC1 is turned off
  • TC2 is turned on
  • the input terminal of S4 is connected to the high voltage signal
  • the third switch control terminal C When the low voltage signal is connected, the fourth switch control terminal D is connected to the high voltage signal, the potential of the first switch control terminal A and the potential of the second switch control terminal B are low voltage, TK4 is turned on, TK3 is turned off, and TK1 and TK2 are turned off. off, I1 is connected to the fourth light-emitting control voltage; in the light-emitting phase te, TE is turned on, and the drain of TE is connected to the fourth light-emitting control voltage to drive M1 to emit light.
  • the first control circuit includes a first data writing circuit, a second data writing circuit, a third data writing circuit, a fourth data writing circuit and a second control sub-circuit;
  • the first data writing circuit is electrically connected to the first scanning terminal, the first data voltage terminal and the first data access terminal respectively, and is used to write the data under the control of the first scanning signal provided by the first scanning terminal.
  • the first data voltage provided by the first data voltage terminal is written into the first data access terminal;
  • the second data writing circuit is electrically connected to the second scanning terminal, the second data voltage terminal and the second data access terminal respectively, and is used to write the second data under the control of the second scanning signal provided by the second scanning terminal.
  • the second data voltage provided by the second data voltage terminal is written into the second data access terminal;
  • the third data writing circuit is electrically connected to the third scanning terminal, the third data voltage terminal and the third data access terminal respectively, and is used to write the data under the control of the third scanning signal provided by the third scanning terminal.
  • the third data voltage provided by the third data voltage terminal is written into the third data access terminal;
  • the fourth data writing circuit is electrically connected to the fourth scanning terminal, the fourth data voltage terminal and the fourth data access terminal respectively, and is used to write the fourth data under the control of the fourth scanning signal provided by the fourth scanning terminal.
  • the fourth data voltage provided by the fourth data voltage terminal is written into the fourth data access terminal;
  • the second control subcircuit is respectively connected to the first data access terminal, the second data access terminal, the third data access terminal, the fourth data access terminal and N switch control terminals. Electrical connection, used to control the voltage to the said first data access terminal according to the potential of the first data access terminal, the potential of the second data access terminal, the potential of the third data access terminal and the potential of the fourth data access terminal.
  • the N switch control terminals provide corresponding switch control signals respectively.
  • the first control circuit includes a first data writing circuit 71, a second data writing circuit 72, a third data writing circuit input circuit 73, fourth data writing circuit 74 and second control sub-circuit 75;
  • the first data writing circuit 71 is electrically connected to the first scanning terminal G1, the first data voltage terminal D1 and the first data access terminal DI1 respectively, and is used to provide the first scanning signal at the first scanning terminal G1. Under the control of , write the first data voltage Vdata1 provided by the first data voltage terminal D1 into the first data access terminal DI1;
  • the second data writing circuit 72 is electrically connected to the second scanning terminal G2, the second data voltage terminal D2 and the second data access terminal DI2 respectively, and is used for providing the second scanning signal at the second scanning terminal G2. Under the control of , write the second data voltage Vdata2 provided by the second data voltage terminal D2 into the second data access terminal DI2;
  • the third data writing circuit 73 is electrically connected to the third scanning terminal G3, the third data voltage terminal D3 and the third data access terminal DI3 respectively, and is used for the third scanning signal provided at the third scanning terminal G3. Under the control of , write the third data voltage Vdata3 provided by the third data voltage terminal D3 into the third data access terminal DI3;
  • the fourth data writing circuit 74 is electrically connected to the fourth scanning terminal G4, the fourth data voltage terminal D4 and the fourth data access terminal DI4 respectively, and is used for the fourth scanning signal provided at the fourth scanning terminal G4. Under the control of , write the fourth data voltage Vdata4 provided by the fourth data voltage terminal D4 into the fourth data access terminal DI4;
  • the second control sub-circuit 75 is respectively connected to the first data access terminal DI1, the second data access terminal DI2, the third data access terminal DI3, the fourth data access terminal DI4, The first switch control terminal A, the second switch control terminal B, the third switch control terminal C, the fourth switch control terminal D, the fifth switch control terminal E, the sixth switch control terminal F, the seventh switch control terminal G and the The eight-switch control terminal H is electrically connected for controlling the potential of the first data access terminal DI1, the potential of the second data access terminal DI2, the potential of the third data access terminal DI3 and the potential of the third data access terminal DI3.
  • the potential of the fourth data access terminal DI4 controls the provision of the first switch control signal to the first switch control terminal A, the control of the provision of the second switch control signal to the second switch control terminal B, and the control of the provision of the second switch control signal to the third switch control terminal C.
  • the third switch control signal controls the provision of the fourth switch control signal to the fourth switch control terminal D, controls the provision of the fifth switch control signal to the fifth switch control terminal E, and controls the provision of the sixth switch control signal to the sixth switch control terminal F.
  • the second control sub-circuit includes a first latch, a second latch, a third latch, a fourth latch, a fifth latch, a sixth latch, a seventh latch. latch, eighth latch, ninth latch, tenth latch, first control switch, second control switch, third control switch, fourth control switch, fifth control switch and sixth control Switch; N equals 8;
  • the input end of the first latch is electrically connected to the first data access end, the output end of the first latch is electrically connected to the control end of the first control switch, and the first latch
  • the register is used to latch the voltage signal connected to the first data access terminal and output a first output voltage, where the first output voltage is inverse phase with the voltage signal connected to the first data access terminal;
  • the input end of the second latch is electrically connected to the second data access end, the output end of the second latch is electrically connected to the control end of the second control switch, and the second latch
  • the register is used to latch the voltage signal connected to the second data access terminal and output a second output voltage, where the second output voltage is inverted with the voltage signal connected to the second data access terminal;
  • the input terminal of the third latch is electrically connected to the first terminal of the first control switch, and the output terminal of the third latch is electrically connected to the control terminal of the third control switch.
  • the third latch is used to latch the voltage signal connected to its input end and output a third output voltage, and the third output voltage is inverse phase with the voltage signal connected to the input end of the third latch;
  • the input end of the fourth latch is electrically connected to the first end of the second control switch, the output end of the fourth latch is electrically connected to the control end of the fifth control switch, and the fourth latch is electrically connected to the control end of the fifth control switch.
  • the latch is used to latch the voltage signal connected to its input end and output a fourth output voltage, where the fourth output voltage is inverse phase with the voltage signal connected to the input end of the fourth latch;
  • the input end of the fifth latch is electrically connected to the first end of the third control switch, the output end of the fifth latch is electrically connected to the second switch control end, and the fifth latch is electrically connected to the first end of the third control switch. latch the voltage signal connected to its input end and output a fifth output voltage, the fifth output voltage being inverted with the voltage signal connected to the input end of the fifth latch;
  • the input terminal of the sixth latch is electrically connected to the third data access terminal, the output terminal of the sixth latch is electrically connected to the second terminal of the third control switch, and the sixth latch is electrically connected to the second terminal of the third control switch.
  • the latch is used to latch the voltage signal connected to its input end and output a sixth output voltage, where the sixth output voltage is inverse phase with the voltage signal connected to the input end of the sixth latch;
  • the input end of the seventh latch is electrically connected to the first end of the fourth control switch, the output end of the seventh latch is electrically connected to the fourth switch control end, and the seventh latch is electrically connected to the first end of the fourth control switch. latch the voltage signal connected to its input end and output a seventh output voltage, the seventh output voltage being inverse phase with the voltage signal connected to the input end of the seventh latch;
  • the input terminal of the eighth latch is electrically connected to the first terminal of the fifth control switch, the output terminal of the eighth latch is electrically connected to the control terminal of the sixth switch, and the eighth latch is electrically connected to the first terminal of the fifth control switch. latch the voltage signal connected to its input end and output an eighth output voltage, the eighth output voltage having an inverse phase with the voltage signal connected to the input end of the eighth latch;
  • the input terminal of the ninth latch is electrically connected to the fourth data access terminal, and the output terminal of the ninth latch is electrically connected to the second terminal of the fifth control switch.
  • the latch is used to latch the voltage signal connected to its input end and output a ninth output voltage, where the ninth output voltage is inverse phase with the voltage signal connected to the input end of the ninth latch;
  • the input end of the tenth latch is electrically connected to the first end of the sixth control switch, the output end of the tenth latch is electrically connected to the eighth switch control end, and the tenth latch is electrically connected to the first end of the sixth control switch. latch the voltage signal connected to its input end and output a tenth output voltage, the tenth output voltage being inverted with the voltage signal connected to the input end of the tenth latch;
  • the control terminal of the first control switch is electrically connected to the output terminal of the first latch, the second terminal of the first control switch is electrically connected to the output terminal of the second latch, and the second terminal of the first control switch is electrically connected to the output terminal of the second latch.
  • a control switch is used to control the connection or disconnection between the first end of the first control switch and the second end of the first control switch under the control of the potential of its control end;
  • the control terminal of the second control switch is electrically connected to the input terminal of the first latch, and the second terminal of the second control switch is electrically connected to the input terminal of the second latch.
  • the second control switch is used to control the connection or disconnection between the first end of the second control switch and the second end of the second control switch under the control of the potential of its control end;
  • the control end of the third control switch is electrically connected to the output end of the third latch, and the third control switch is used to control the input of the fifth latch under the control of the potential of its control end.
  • the terminal is connected or disconnected from the output terminal of the sixth latch;
  • the control end of the fourth control switch is electrically connected to the input end of the third latch.
  • the fourth control switch is used to control the input of the seventh latch under the control of the potential of its control end.
  • the terminal is connected or disconnected from the input terminal of the sixth latch;
  • the control end of the fifth control switch is electrically connected to the output end of the fourth latch, and the fifth control switch is used to control the input of the eighth latch under the control of the potential of its control end.
  • the terminal is electrically connected to the output terminal of the ninth latch;
  • the control terminal of the sixth control switch is electrically connected to the input terminal of the fourth latch.
  • the sixth control switch is used to control the input of the tenth latch under the control of the potential of its control terminal.
  • the terminal is connected to the input terminal of the ninth latch;
  • the first switch control terminal is electrically connected to the input terminal of the fifth latch, and the seventh switch control terminal is electrically connected to the input terminal of the tenth latch.
  • the second control sub-circuit includes a first latch S1, a second latch S2, a third latch S3, the fourth latch S4, the fifth latch S5, the sixth latch S6, the seventh latch S7, the eighth latch S8, the ninth latch S9, the tenth latch S10 , the first control switch K1, the second control switch K2, the third control switch K3, the fourth control switch K4, the fifth control switch K5 and the sixth control switch K6; N is equal to 8;
  • the input terminal of the first latch S1 is electrically connected to the first data access terminal DI1, and the output terminal of the first latch S1 is electrically connected to the control terminal of the first control switch K1, so
  • the first latch S1 is used to latch the voltage signal connected to the first data access terminal DI1, and output the first output voltage Vo1 through the output terminal of the first latch S1.
  • the first The output voltage Vo1 is inverse phase with the voltage signal connected to the first data access terminal DI1;
  • the input terminal of the second latch S2 is electrically connected to the second data access terminal DI2, and the output terminal of the second latch S2 is electrically connected to the control terminal of the second control switch K2, so
  • the second latch S2 is used to latch the voltage signal connected to the second data access terminal DI2, and output the second output voltage Vo2 through the output terminal of the second latch S2.
  • the second The output voltage Vo2 is inverse phase with the voltage signal connected to the second data access terminal DI2;
  • the input terminal of the third latch S3 is electrically connected to the first terminal of the first control switch K1, and the output terminal of the third latch S3 is electrically connected to the control terminal of the third control switch K3.
  • the third latch S3 is used to latch the voltage signal connected to its input terminal, and output the third output voltage Vo3 through the output terminal of the third latch S3, the third output voltage Vo3 and The voltage signal connected to the input terminal of the third latch S3 is inverted;
  • the input terminal of the fourth latch S4 is electrically connected to the first terminal of the second control switch K2, and the output terminal of the fourth latch S4 is electrically connected to the control terminal of the fifth control switch K5,
  • the fourth latch S4 is used to latch the voltage signal connected to its input terminal and output a fourth output voltage Vo4 through the output terminal of the fourth latch S4.
  • the fourth output voltage Vo4 is related to the voltage signal Vo4.
  • the voltage signal connected to the input terminal of the fourth latch S4 is inverted;
  • the input terminal of the fifth latch S5 is electrically connected to the first terminal of the third control switch K3, and the output terminal of the fifth latch S5 is electrically connected to the second switch control terminal B.
  • the fifth latch S5 is used to latch the voltage signal connected to its input terminal, and output a fifth output voltage Vo5 through the output terminal of the fifth latch S5.
  • the fifth output voltage Vo5 and the fifth The voltage signal connected to the input terminal of latch S5 is inverted;
  • the input terminal of the sixth latch S6 is electrically connected to the third data access terminal DI3, and the output terminal of the sixth latch S6 is electrically connected to the second terminal of the third control switch K3,
  • the sixth latch S6 is used to latch the voltage signal connected to its input terminal, and output a sixth output voltage Vo6 through the output terminal of the sixth latch S6.
  • the sixth output voltage Vo6 is equal to The voltage signal connected to the input terminal of the sixth latch S6 is inverted;
  • the input terminal of the seventh latch S7 is electrically connected to the first terminal of the fourth control switch K4, and the output terminal of the seventh latch S7 is electrically connected to the fourth switch control terminal D.
  • the seventh latch S7 is used to latch the voltage signal connected to its input end and output a seventh output voltage Vo7 through the seventh latch S7.
  • the seventh output voltage Vo7 is in contact with the seventh latch S7.
  • the voltage signal connected to the input terminal of S7 is inverted;
  • the input terminal of the eighth latch S8 is electrically connected to the first terminal of the fifth control switch K5, and the output terminal of the eighth latch S8 is electrically connected to the sixth switch control terminal F.
  • the eighth latch S8 is used to latch the voltage signal connected to its input terminal, and output an eighth output voltage Vo8 through the output terminal of the eighth latch S8.
  • the eighth output voltage Vo8 is the same as the eighth output voltage Vo8.
  • the voltage signal connected to the input terminal of latch S8 is inverted;
  • the input terminal of the ninth latch S9 is electrically connected to the fourth data access terminal DI4, and the output terminal of the ninth latch S9 is electrically connected to the second terminal of the fifth control switch K5,
  • the ninth latch S9 is used to latch the voltage signal connected to its input terminal, and output a ninth output voltage Vo9 through the ninth latch S9.
  • the ninth output voltage Vo9 is consistent with the first voltage signal Vo9.
  • the voltage signal connected to the input terminal of the nine latch S9 is inverted;
  • the input terminal of the tenth latch S10 is electrically connected to the first terminal of the sixth control switch K6, and the output terminal of the tenth latch S10 is electrically connected to the eighth switch control terminal H.
  • the tenth latch S10 is used to latch the voltage signal connected to its input terminal and output the tenth output voltage Vo10 through the output terminal of the tenth latch S10.
  • the tenth output voltage V10 is the same as the tenth output voltage Vo10.
  • the voltage signal connected to the input terminal of latch S10 is inverted;
  • the control end of the first control switch K1 is electrically connected to the output end of the first latch S1, and the second end of the first control switch K1 is electrically connected to the output end of the second latch S2.
  • the first control switch K1 is used to control the connection or disconnection between the first end of the first control switch K1 and the second end of the first control switch K1 under the control of the potential of its control end;
  • the control end of the second control switch K2 is electrically connected to the input end of the first latch S1, and the second end of the second control switch K2 is electrically connected to the input end of the second latch S2.
  • the second control switch K2 is used to control the connection or disconnection between the first end of the second control switch K2 and the second end of the second control switch K2 under the control of the potential of its control end;
  • the control end of the third control switch K3 is electrically connected to the output end of the third latch S3.
  • the third control switch K3 is used to control the fifth latch under the control of the potential of its control end.
  • the input terminal of the device S5 is connected or disconnected from the output terminal of the sixth latch S6;
  • the control end of the fourth control switch K4 is electrically connected to the input end of the third latch S3.
  • the fourth control switch K4 is used to control the seventh latch under the control of the potential of its control end.
  • the input terminal of the device S7 is connected or disconnected from the input terminal of the sixth latch S6;
  • the control end of the fifth control switch K5 is electrically connected to the output end of the fourth latch S4.
  • the fifth control switch K5 is used to control the eighth latch under the control of the potential of its control end.
  • the input terminal of the device S8 is electrically connected to the output terminal of the ninth latch S9;
  • the control terminal of the sixth control switch K6 is electrically connected to the input terminal of the fourth latch S4.
  • the sixth control switch K6 is used to control the tenth latch under the control of the potential of its control terminal.
  • the input terminal of the device S10 is connected to the input terminal of the ninth latch S9;
  • the first switch control terminal A is electrically connected to the input terminal of the fifth latch S5, and the seventh switch control terminal G is electrically connected to the input terminal of the tenth latch S10;
  • the third switch control terminal C is electrically connected to the input terminal of the seventh latch S7, and the fifth switch control terminal E is electrically connected to the input terminal of the eighth latch S8.
  • Vdata1 is a low voltage signal
  • Vdata2 is a low voltage signal
  • Vdata3 is a low voltage signal
  • Vdata4 is a low voltage signal
  • the gate of K1 is connected to the high voltage signal
  • the gate of K2 is connected to the low voltage signal
  • K1 is turned on.
  • K2 is turned off, the input terminal of S3 is connected to a high voltage signal
  • S3 outputs a low voltage signal
  • K3 is turned off
  • K4 is opened, the input terminal of S7 is connected to a low voltage signal, and S7 outputs a high voltage signal to the fourth switch control terminal D;
  • Vdata1 is a high voltage signal
  • Vdata2 is a low voltage signal
  • Vata3 is a low voltage signal
  • Vdata4 is a low voltage signal
  • S1 outputs a low voltage signal
  • K1 is turned off
  • S2 outputs a high voltage signal
  • K2 is turned on
  • the input terminal of S4 A low voltage signal is connected to the control terminal of K5.
  • a high voltage signal is connected to the control terminal of K5.
  • K5 is turned on and K6 is turned off.
  • a low voltage signal is connected to the input terminal of S9.
  • S9 outputs a high voltage signal and provides the high voltage signal to the third terminal through K5.
  • Vdata1 is a low voltage signal
  • Vdata2 is a high voltage signal
  • Vdata3 is a low voltage signal
  • Vdata4 is a low voltage signal
  • S1 outputs a high voltage signal
  • K1 is on
  • K2 is off
  • S2 outputs a low voltage signal
  • the input terminal of S3 When the low voltage signal is connected, S3 outputs a high voltage signal, K3 is turned on, K4 is turned off, S6 outputs a high voltage signal, and S6 provides the high voltage signal to the first switch control terminal A through the turned on K3;
  • Vdata1 is a low voltage signal
  • Vdata2 is a low voltage signal
  • Vdata3 is a high voltage signal
  • Vdata4 is a low voltage signal
  • S1 outputs a high voltage signal
  • S2 provides a high voltage signal
  • K1 is turned on
  • K2 is turned off
  • the input terminal of S3 A high voltage signal is connected
  • S3 outputs a low voltage signal
  • K3 is turned off
  • K4 is turned on
  • the input terminal of S7 is connected with a high voltage signal
  • the high voltage signal is written into the third switch control terminal C;
  • Vdata1 is a low voltage signal
  • Vdata2 is a low voltage signal
  • Vdata3 is a low voltage signal
  • Vdata4 is a high voltage signal
  • S1 outputs a high voltage signal
  • S2 outputs a high voltage signal
  • K1 is turned on
  • K2 is turned off
  • the input terminal of S3 A high voltage signal is connected
  • S3 outputs a low voltage signal
  • K3 is turned off
  • K4 is turned on
  • the input terminal of S6 is connected to a low voltage signal
  • the input terminal of S7 is connected to a low voltage signal
  • S7 outputs a high voltage signal to the fourth switch control End D;
  • Vdata1 is a high voltage signal
  • Vdata2 is a high voltage signal
  • Vdata3 is a low voltage signal
  • Vdata4 is a low voltage signal
  • S1 outputs a low voltage signal
  • S2 outputs a low voltage signal
  • K1 is turned off
  • K2 is turned on
  • the input terminal of S4 A high voltage signal is connected
  • S4 outputs a low voltage signal
  • K7 is turned off
  • K8 is turned on
  • the input terminal of S9 is connected to a low voltage signal
  • the input terminal of S10 is connected to a low voltage signal
  • S10 outputs a high voltage signal to the eighth switch control end H;
  • Vdata1 is a high voltage signal
  • Vdata2 is a high voltage signal
  • Vdata3 is a low voltage signal
  • Vdata4 is a high voltage signal
  • S1 outputs a low voltage signal
  • S2 outputs a low voltage signal
  • K1 is turned off
  • K2 is turned on
  • the input terminal of S4 A high voltage signal is connected
  • S4 outputs a low voltage signal
  • K7 is turned off
  • K8 is turned on
  • the input terminal of S9 is connected to a high voltage signal
  • the input terminal of S10 is connected to a high voltage signal
  • S10 outputs a low voltage signal to convert the high voltage
  • the signal is written into the seventh switch control terminal G;
  • Vdata1 is a high voltage signal
  • Vdata2 is a high voltage signal
  • Vdata3 is a high voltage signal
  • Vdata4 is a low voltage signal
  • S1 outputs a low voltage signal
  • S2 outputs a low voltage signal
  • K1 is turned off
  • K2 is turned on
  • the input terminal of S4 When a high voltage signal is connected, S4 outputs a low voltage signal, K7 is turned off, K8 is on, the input terminal of S9 is connected to a low voltage signal, S9 outputs a high voltage signal, the input terminal of S10 is connected to a low voltage signal, and S10 outputs a high voltage signal.
  • Vdata1 is a high voltage signal
  • Vdata2 is a high voltage signal
  • Vdata3 is a high voltage signal
  • Vdata4 is a high voltage signal
  • S1 outputs a low voltage signal
  • S2 outputs a low voltage signal
  • K1 is turned off
  • K2 is turned on
  • the input terminal of S4 When a high voltage signal is connected, S4 outputs a low voltage signal, K7 is turned off, K8 is on, the input terminal of S9 is connected to a high voltage signal, S9 outputs a low voltage signal, the input terminal of S10 is connected to a high voltage signal, and S10 outputs a low voltage signal. signal to provide a high voltage signal to the seventh switch control terminal G;
  • Vdata1 is a high voltage signal
  • Vdata2 is a low voltage signal
  • Vdata3 is a high voltage signal
  • Vdata4 is a high voltage signal
  • S1 outputs a low voltage signal
  • S2 outputs a high voltage signal
  • K1 is turned off
  • K2 is turned on
  • the input terminal of S4 When a low voltage signal is connected, S4 outputs a high voltage signal, K7 is on, K8 is off, the input terminal of S9 is connected to a high voltage signal, S9 outputs a low voltage signal to the input terminal of S8, and S8 outputs a high voltage signal to the sixth switch.
  • Control terminal F is a low voltage signal
  • Vdata1 is a high voltage signal
  • Vdata2 is a low voltage signal
  • Vdata3 is a low voltage signal
  • Vdata4 is a high voltage signal
  • S1 outputs a low voltage signal
  • S2 provides a high voltage signal
  • K1 is turned off
  • K2 is turned on
  • the input terminal of S4 When a low voltage signal is connected, S4 outputs a high voltage signal, K7 is on, K8 is off, the input terminal of S9 is connected to a high voltage signal, S9 outputs a low voltage signal to the input terminal of S8, and S8 outputs a high voltage signal to the sixth switch.
  • Control terminal F is a low voltage signal
  • Vdata2 is a low voltage signal
  • Vdata3 is a low voltage signal
  • Vdata4 is a high voltage signal
  • S2 provides a high voltage signal
  • K1 is turned off
  • K2 is turned on
  • the input terminal of S4 When a low voltage signal is connected, S4 outputs a high voltage signal
  • Vdata1 is a high voltage signal
  • Vdata2 is a low voltage signal
  • Vdata3 is a high voltage signal
  • Vdata4 is a low voltage signal
  • S1 outputs a low voltage signal
  • S2 provides a high voltage signal
  • K1 is turned off
  • K2 is turned on
  • the input terminal of S4 When a low voltage signal is connected, S4 outputs a high voltage signal, K7 is on, K8 is off, the input terminal of S9 is connected to a low voltage signal, S9 outputs a high voltage signal to the input terminal of S8, S8 outputs a low voltage signal, and S9 outputs a high voltage signal.
  • the voltage signal goes to the fifth switch control terminal E;
  • Vdata1 is a low voltage signal
  • Vdata2 is a high voltage signal
  • Vdata3 is a high voltage signal
  • Vdata4 is a high voltage signal
  • S1 outputs a high voltage signal
  • S2 outputs a low voltage signal
  • K1 is turned on
  • K2 is turned off
  • the input terminal of S3 Connect a low voltage signal
  • S3 outputs a high voltage signal
  • K3 is on
  • K4 off
  • the input terminal of S6 is connected to a high voltage signal
  • S6 outputs a low voltage signal
  • the input terminal of S5 is connected to a low voltage signal
  • S5 outputs a high voltage
  • the signal goes to the second switch control terminal B;
  • Vdata1 is a low voltage signal
  • Vdata2 is a high voltage signal
  • Vdata3 is a low voltage signal
  • Vdata4 is a high voltage signal
  • S1 outputs a high voltage signal
  • S2 outputs a low voltage signal
  • K1 is turned on
  • K2 is turned off
  • the input terminal of S3 A low voltage signal is connected
  • S3 outputs a high voltage signal
  • K3 is turned on
  • K4 is turned off
  • the input terminal of S6 is connected with a low voltage signal
  • S6 outputs a high voltage signal to the first switch control terminal A;
  • Vdata1 is a low voltage signal
  • Vdata2 is a high voltage signal
  • Vdata3 is a high voltage signal
  • Vdata4 is a low voltage signal
  • S1 outputs a high voltage signal
  • S2 outputs a low voltage signal
  • K1 is turned on
  • K2 is turned off
  • the input terminal of S3 Connect a low voltage signal
  • S3 outputs a high voltage signal
  • K3 is on
  • K4 is off
  • the input terminal of S6 is connected to a high voltage signal
  • S6 outputs a low voltage signal to the input terminal of S5, and S5 outputs a high voltage signal to the second switch.
  • Control terminal B is
  • Vdata1 is a low voltage signal
  • Vdata2 is a low voltage signal
  • Vdata3 is a high voltage signal
  • Vdata4 is a high voltage signal
  • S1 outputs a high voltage signal
  • S2 outputs a high voltage signal
  • K1 is turned on
  • K2 is turned off
  • the input terminal of S3 A high voltage signal is connected
  • S3 outputs a low voltage signal
  • K3 is turned off
  • K4 is turned on
  • the input terminal of S6 is connected to a high voltage signal
  • the input terminal of S7 is connected to a high voltage signal
  • S7 outputs a low voltage signal
  • the high voltage signal is connected to The signal is provided to the third switch control terminal C.
  • the first latch includes a first inverter and a second inverter
  • the input terminal of the first inverter is electrically connected to the input terminal of the first latch, and the output terminal of the first inverter is electrically connected to the output terminal of the first latch;
  • the input terminal of the second inverter is electrically connected to the output terminal of the first inverter, and the output terminal of the second inverter is electrically connected to the input terminal of the first inverter;
  • the second latch includes a third inverter and a fourth inverter
  • the input terminal of the third inverter is electrically connected to the input terminal of the second latch, and the output terminal of the third inverter is electrically connected to the output terminal of the second latch;
  • the input terminal of the fourth inverter is electrically connected to the output terminal of the third inverter, and the output terminal of the fourth inverter is electrically connected to the input terminal of the third inverter;
  • the third latch includes a fifth inverter and a sixth inverter
  • the input terminal of the fifth inverter is electrically connected to the input terminal of the third latch, and the output terminal of the fifth inverter is electrically connected to the output terminal of the third latch;
  • the input terminal of the sixth inverter is electrically connected to the output terminal of the fifth inverter, and the output terminal of the sixth inverter is electrically connected to the input terminal of the fifth inverter;
  • the fourth latch includes a seventh inverter and an eighth inverter
  • the input terminal of the seventh inverter is electrically connected to the input terminal of the fourth latch, and the output terminal of the seventh inverter is electrically connected to the output terminal of the fourth latch;
  • the input terminal of the eighth inverter is electrically connected to the output terminal of the seventh inverter, and the output terminal of the eighth inverter is electrically connected to the input terminal of the seventh inverter;
  • the fifth latch includes a ninth inverter and a tenth inverter
  • the input terminal of the ninth inverter is electrically connected to the input terminal of the fifth latch, and the output terminal of the ninth inverter is electrically connected to the output terminal of the fifth latch;
  • the input terminal of the tenth inverter is electrically connected to the output terminal of the ninth inverter, and the output terminal of the tenth inverter is electrically connected to the input terminal of the ninth inverter;
  • the sixth latch includes an eleventh inverter and a twelfth inverter
  • the input terminal of the eleventh inverter is electrically connected to the input terminal of the sixth latch, and the output terminal of the eleventh inverter is electrically connected to the output terminal of the sixth latch;
  • the input terminal of the twelfth inverter is electrically connected to the output terminal of the eleventh inverter, and the output terminal of the twelfth inverter is electrically connected to the input terminal of the eleventh inverter. connect;
  • the seventh latch includes a thirteenth inverter and a fourteenth inverter
  • the input terminal of the thirteenth inverter is electrically connected to the input terminal of the seventh latch, and the output terminal of the thirteenth inverter is electrically connected to the output terminal of the seventh latch;
  • the input terminal of the fourteenth inverter is electrically connected to the output terminal of the thirteenth inverter, and the output terminal of the fourteenth inverter is electrically connected to the input terminal of the thirteenth inverter. connect;
  • the eighth latch includes a fifteenth inverter and a sixteenth inverter
  • the input terminal of the fifteenth inverter is electrically connected to the input terminal of the eighth latch, and the output terminal of the fifteenth inverter is electrically connected to the output terminal of the eighth latch;
  • the input terminal of the sixteenth inverter is electrically connected to the output terminal of the fifteenth inverter, and the output terminal of the sixteenth inverter is electrically connected to the input terminal of the fifteenth inverter. connect;
  • the ninth latch includes a seventeenth inverter and an eighteenth inverter
  • the input terminal of the seventeenth inverter is electrically connected to the input terminal of the ninth latch, and the output terminal of the seventeenth inverter is electrically connected to the output terminal of the ninth latch;
  • the input terminal of the eighteenth inverter is electrically connected to the output terminal of the seventeenth inverter, and the output terminal of the eighteenth inverter is electrically connected to the input terminal of the seventeenth inverter. connect;
  • the tenth latch includes a nineteenth inverter and a twentieth inverter;
  • the input terminal of the nineteenth inverter is electrically connected to the input terminal of the tenth latch, and the output terminal of the nineteenth inverter is electrically connected to the output terminal of the tenth latch;
  • the input terminal of the twentieth inverter is electrically connected to the output terminal of the nineteenth inverter, and the output terminal of the twentieth inverter is electrically connected to the input terminal of the nineteenth inverter. connect.
  • the first control switch is a first control transistor
  • the second control switch is a second control transistor
  • the third control switch is a third control transistor
  • the fourth control switch is a fourth control transistor.
  • the fifth control switch is a fifth control transistor, and the sixth control switch is a sixth control transistor;
  • the control electrode of the first control transistor is electrically connected to the output terminal of the first latch, and the first electrode of the first control transistor is electrically connected to the input terminal of the third latch. an electrical connection between the second pole of the control transistor and the output terminal of the second latch;
  • the control electrode of the second control transistor is electrically connected to the input terminal of the first latch, and the first electrode of the second control transistor is electrically connected to the input terminal of the fourth latch.
  • the second pole of the two control transistors is electrically connected to the input terminal of the second latch;
  • the control electrode of the third control transistor is electrically connected to the output terminal of the third latch, and the first electrode of the third control transistor is electrically connected to the input terminal of the fifth latch.
  • the second pole of the three control transistors is electrically connected to the output terminal of the sixth latch;
  • the control electrode of the fourth control transistor is electrically connected to the input terminal of the third latch, the first electrode of the fourth control transistor is electrically connected to the input terminal of the seventh latch, and the fourth control transistor is electrically connected to the input terminal of the seventh latch.
  • the second pole of the transistor is electrically connected to the input terminal of the sixth latch;
  • the control electrode of the fifth control transistor is electrically connected to the output terminal of the fourth latch, and the first electrode of the fifth control transistor is electrically connected to the input terminal of the eighth latch.
  • the second pole of the fifth control transistor is electrically connected to the output terminal of the ninth latch;
  • the control electrode of the sixth control transistor is electrically connected to the input terminal of the fourth latch, and the first electrode of the sixth control transistor is electrically connected to the input terminal of the tenth latch.
  • the second pole of the six control transistors is electrically connected to the input terminal of the ninth latch.
  • the first data writing circuit includes a first writing transistor
  • the second data writing circuit includes a second writing transistor
  • the third data writing circuit includes a third writing transistor
  • the fourth data writing circuit includes a fourth writing transistor
  • the control electrode of the first writing transistor is electrically connected to the first scan terminal, the first electrode of the first writing transistor is electrically connected to the first data voltage terminal, and the control electrode of the first writing transistor is electrically connected to the first data voltage terminal.
  • the second pole is electrically connected to the first data access terminal;
  • the control electrode of the second writing transistor is electrically connected to the second scan terminal, the first electrode of the second writing transistor is electrically connected to the second data voltage terminal, and the control electrode of the second writing transistor is electrically connected to the second data voltage terminal.
  • the second pole is electrically connected to the second data access terminal;
  • the control electrode of the third writing transistor is electrically connected to the third scan terminal, the first electrode of the third writing transistor is electrically connected to the third data voltage terminal, and the control electrode of the third writing transistor is electrically connected to the third data voltage terminal.
  • the second pole is electrically connected to the third data access terminal;
  • the control electrode of the fourth write transistor is electrically connected to the fourth scan terminal
  • the first electrode of the fourth write transistor is electrically connected to the fourth data voltage terminal
  • the control electrode of the fourth write transistor is electrically connected to the fourth data voltage terminal.
  • the second pole is electrically connected to the fourth data access terminal.
  • the first latch includes a first inverter F1 and a second inverter F2;
  • the input terminal of the first inverter F1 is electrically connected to the input terminal of the first latch, and the output terminal of the first inverter F1 is electrically connected to the output terminal of the first latch;
  • the input terminal of the second inverter F2 is electrically connected to the output terminal of the first inverter F1, and the output terminal of the second inverter F2 is electrically connected to the input terminal of the first inverter F1. connect;
  • the second latch includes a third inverter F3 and a fourth inverter F4;
  • the input terminal of the third inverter F3 is electrically connected to the input terminal of the second latch, and the output terminal of the third inverter F3 is electrically connected to the output terminal of the second latch;
  • the input terminal of the fourth inverter F4 is electrically connected to the output terminal of the third inverter F3, and the output terminal of the fourth inverter F4 is electrically connected to the input terminal of the third inverter F3. connect;
  • the third latch includes a fifth inverter F5 and a sixth inverter F6;
  • the input terminal of the fifth inverter F5 is electrically connected to the input terminal of the third latch, and the output terminal of the fifth inverter F5 is electrically connected to the output terminal of the third latch;
  • the input terminal of the sixth inverter F6 is electrically connected to the output terminal of the fifth inverter F5, and the output terminal of the sixth inverter F6 is electrically connected to the input terminal of the fifth inverter F5. connect;
  • the fourth latch includes a seventh inverter F7 and an eighth inverter F8;
  • the input terminal of the seventh inverter F7 is electrically connected to the input terminal of the fourth latch, and the output terminal of the seventh inverter F7 is electrically connected to the output terminal of the fourth latch;
  • the input terminal of the eighth inverter F8 is electrically connected to the output terminal of the seventh inverter F7, and the output terminal of the eighth inverter F8 is electrically connected to the input terminal of the seventh inverter F7. connect;
  • the fifth latch includes a ninth inverter F9 and a tenth inverter F10;
  • the input terminal of the ninth inverter F9 is electrically connected to the input terminal of the fifth latch, and the output terminal of the ninth inverter F9 is electrically connected to the output terminal of the fifth latch;
  • the input terminal of the tenth inverter F10 is electrically connected to the output terminal of the ninth inverter F9, and the output terminal of the tenth inverter F10 is electrically connected to the input terminal of the fifth inverter F5. connect;
  • the sixth latch includes an eleventh inverter F11 and a twelfth inverter F12;
  • the input terminal of the eleventh inverter F11 is electrically connected to the input terminal of the sixth latch, and the output terminal of the eleventh inverter F11 is electrically connected to the output terminal of the sixth latch. connect;
  • the input terminal of the twelfth inverter F12 is electrically connected to the output terminal of the eleventh inverter F11, and the output terminal of the twelfth inverter F12 is electrically connected to the eleventh inverter F11.
  • the input terminal is electrically connected;
  • the seventh latch includes a thirteenth inverter F13 and a fourteenth inverter F14;
  • the input terminal of the thirteenth inverter F13 is electrically connected to the input terminal of the seventh latch, and the output terminal of the thirteenth inverter F13 is electrically connected to the output terminal of the seventh latch. connect;
  • the input terminal of the fourteenth inverter F14 is electrically connected to the output terminal of the thirteenth inverter F13, and the output terminal of the fourteenth inverter F14 is electrically connected to the thirteenth inverter F13.
  • the input terminal is electrically connected;
  • the eighth latch includes a fifteenth inverter F15 and a sixteenth inverter F16;
  • the input terminal of the fifteenth inverter F15 is electrically connected to the input terminal of the eighth latch, and the output terminal of the fifteenth inverter F15 is electrically connected to the output terminal of the eighth latch. connect;
  • the input terminal of the sixteenth inverter F16 is electrically connected to the output terminal of the fifteenth inverter F15, and the output terminal of the sixteenth inverter F16 is electrically connected to the fifteenth inverter F15.
  • the input terminal is electrically connected;
  • the ninth latch includes a seventeenth inverter F17 and an eighteenth inverter F18;
  • the input terminal of the seventeenth inverter F17 is electrically connected to the input terminal of the ninth latch, and the output terminal of the seventeenth inverter F17 is electrically connected to the output terminal of the ninth latch. connect;
  • the input terminal of the eighteenth inverter F18 is electrically connected to the output terminal of the seventeenth inverter F17, and the output terminal of the eighteenth inverter F18 is electrically connected to the seventeenth inverter F17.
  • the input terminal is electrically connected;
  • the tenth latch includes a nineteenth inverter F19 and a twentieth inverter F20;
  • the input terminal of the nineteenth inverter F19 is electrically connected to the input terminal of the tenth latch, and the output terminal of the nineteenth inverter S19 is electrically connected to the output terminal of the tenth latch. connect;
  • the input terminal of the twentieth inverter F20 is electrically connected to the output terminal of the nineteenth inverter F19, and the output terminal of the twentieth inverter F20 is electrically connected to the nineteenth inverter F19.
  • the input terminal is electrically connected;
  • the first control switch is a first control transistor TC1, the second control switch is a second control transistor TC2; the third control switch is a third control transistor TC3, and the fourth control switch is a fourth control transistor.
  • the gate of the first control transistor TC1 is electrically connected to the output terminal of the first latch S1, and the drain of the first control transistor TC1 is electrically connected to the input terminal of the third latch S3, The source of the first control transistor TC1 is electrically connected to the output terminal of the second latch S2;
  • the gate of the second control transistor TC2 is electrically connected to the input terminal of the first latch S1, and the drain of the second control transistor TC2 is electrically connected to the input terminal of the fourth latch S4, The source of the second control transistor TC2 is electrically connected to the input terminal of the second latch S2;
  • the gate of the third control transistor TC3 is electrically connected to the output terminal of the third latch S3, and the drain of the third control transistor TC3 is electrically connected to the input terminal of the fifth latch S5, The source of the third control transistor TC3 is electrically connected to the output terminal of the sixth latch S6;
  • the gate of the fourth control transistor TC4 is electrically connected to the input terminal of the third latch S3, and the drain of the fourth control transistor TC4 is electrically connected to the input terminal of the seventh latch S7.
  • the source of the fourth control transistor TC4 is electrically connected to the input terminal of the sixth latch S6;
  • the gate of the fifth control transistor TC5 is electrically connected to the output terminal of the fourth latch S4, and the drain of the fifth control transistor TC5 is electrically connected to the input terminal of the eighth latch S8, The source of the fifth control transistor TC5 is electrically connected to the output terminal of the ninth latch S9;
  • the gate of the sixth control transistor TC6 is electrically connected to the input terminal of the fourth latch S4, and the drain of the sixth control transistor TC6 is electrically connected to the input terminal of the tenth latch S10, The source of the sixth control transistor TC6 is electrically connected to the input terminal of the ninth latch S9;
  • the first data writing circuit includes a first writing transistor TW1, the second data writing circuit includes a second writing transistor TW2, the third data writing circuit includes a third writing transistor TW3, and the The fourth data writing circuit includes a fourth writing transistor TW4;
  • the gate of the first writing transistor TW1 is electrically connected to the first scanning terminal G1, and the drain of the first writing transistor TW1 is electrically connected to the first data voltage terminal D1.
  • the source of the input transistor TW1 is electrically connected to the first data access terminal DI1;
  • the gate of the second writing transistor TW2 is electrically connected to the second scan terminal G2, and the drain of the second writing transistor TW2 is electrically connected to the second data voltage terminal D2.
  • the source of the input transistor TW2 is electrically connected to the second data access terminal DI2;
  • the gate of the third writing transistor TW3 is electrically connected to the third scanning terminal G3, and the drain of the third writing transistor TW3 is electrically connected to the third data voltage terminal D3.
  • the source of the input transistor TW3 is electrically connected to the third data access terminal DI3;
  • the gate of the fourth writing transistor TW4 is electrically connected to the fourth scanning terminal G4, and the drain of the fourth writing transistor TW4 is electrically connected to the fourth data voltage terminal D4.
  • the source of the input transistor TW4 is electrically connected to the fourth data access terminal DI4;
  • the first switch control sub-circuit includes a first switch control transistor TK1;
  • the gate of the first switch control transistor TK1 is electrically connected to the first switch control terminal A, and the drain of the first switch control transistor TK1 is electrically connected to the first lighting control voltage terminal VC1.
  • the source is electrically connected to the control voltage input terminal I1;
  • the second switch control sub-circuit includes a second switch control transistor TK2;
  • the gate of the second switch control transistor TK2 is electrically connected to the second switch control terminal B, and the drain of the second switch control transistor TK2 is electrically connected to the second lighting control voltage terminal VC2.
  • the source is electrically connected to the control voltage input terminal I1;
  • the third switch control sub-circuit includes a third switch control transistor TK3;
  • the gate of the third switch control transistor TK3 is electrically connected to the third switch control terminal C, and the drain of the third switch control transistor TK3 is electrically connected to the third lighting control voltage terminal VC2.
  • the source is electrically connected to the control voltage input terminal I1;
  • the fourth switch control sub-circuit includes a fourth switch control transistor TK4;
  • the gate of the fourth switch control transistor TK4 is electrically connected to the fourth switch control terminal D, and the drain of the fourth switch control transistor TK4 is electrically connected to the fourth lighting control voltage terminal VC4.
  • the source is electrically connected to the control voltage input terminal I1;
  • the fifth switch control sub-circuit includes a fifth switch control transistor TK5;
  • the gate of the fifth switch control transistor TK5 is electrically connected to the fifth switch control terminal E, and the drain of the fifth switch control transistor TK5 is electrically connected to the fifth lighting control voltage terminal VC5.
  • the source is electrically connected to the control voltage input terminal I1;
  • the sixth switch control sub-circuit includes a sixth switch control transistor TK6;
  • the gate of the sixth switch control transistor TK6 is electrically connected to the sixth switch control terminal F, and the drain of the sixth switch control transistor TK6 is electrically connected to the sixth lighting control voltage terminal VC6.
  • the source is electrically connected to the control voltage input terminal I1;
  • the seventh switch control sub-circuit includes a seventh switch control transistor TK7;
  • the gate of the seventh switch control transistor TK7 is electrically connected to the seventh switch control terminal G, and the drain of the seventh switch control transistor TK7 is electrically connected to the seventh lighting control voltage terminal VC7.
  • the source is electrically connected to the control voltage input terminal I1;
  • the eighth switch control sub-circuit includes an eighth switch control transistor TK8;
  • the gate of the eighth switch control transistor TK8 is electrically connected to the eighth switch control terminal H, and the drain of the eighth switch control transistor TK8 is electrically connected to the eighth light-emitting control voltage terminal VC8.
  • the source is electrically connected to the control voltage input terminal I1;
  • the light emission control circuit includes a light emission control transistor TE;
  • the gate of the light-emitting control transistor TE is electrically connected to the light-emitting control terminal EM, the drain of the light-emitting control transistor TE is electrically connected to the control voltage input terminal I1, and the source of the light-emitting control transistor TE is connected to M1
  • the anode of M1 is electrically connected, and the cathode of M1 is electrically connected to the low voltage terminal VSS.
  • all transistors are n-type transistors, but are not limited to this.
  • the display cycle may include a first writing stage tw1, a second writing stage tw2, and a third writing stage set successively. tw3, the fourth writing stage tw4 and the lighting stage te;
  • G1 provides a high voltage signal
  • G2, G3 and G4 all provide low voltage signals
  • D1 provides the first data voltage Vdata1 to the first data access terminal DI1;
  • G2 provides a high voltage signal
  • G1, G3 and G4 all provide low voltage signals
  • D2 provides the second data voltage Vdata2 to the second data access terminal DI2;
  • G3 provides a high voltage signal
  • G1, G2 and G4 all provide low voltage signals
  • D3 provides the third data voltage Vdata3 to the third data access terminal DI3;
  • G4 provides a high voltage signal
  • G1, G2 and G3 all provide low voltage signals
  • D4 provides the fourth data voltage Vdata4 to the fourth data access terminal DI4;
  • Vdata1 is a low voltage signal
  • Vdata2 is a low voltage signal
  • Vdata3 is a low voltage signal
  • Vdata4 is a low voltage signal
  • the gate of K1 is connected to the high voltage signal
  • the gate of K2 is connected to the low voltage signal
  • K1 is turned on.
  • K2 is turned off, the input terminal of S3 is connected to a high voltage signal, S3 outputs a low voltage signal, K3 is turned off, K4 is turned on, the input terminal of S7 is connected to a low voltage signal, and S7 outputs a high voltage signal to the fourth switch control terminal D;
  • TK4 is turned on, TE is turned on, the drain of TE is connected to the fourth light-emitting control voltage, and M1 emits light;
  • Vdata1 is a high voltage signal
  • Vdata2 is a low voltage signal
  • Vata3 is a low voltage signal
  • Vdata4 is a low voltage signal
  • S1 outputs a low voltage signal
  • K1 is turned off
  • S2 outputs a high voltage signal
  • K2 is turned on
  • the input terminal of S4 A low voltage signal is connected to the control terminal of K5.
  • a high voltage signal is connected to the control terminal of K5.
  • K5 is turned on and K6 is turned off.
  • a low voltage signal is connected to the input terminal of S9.
  • S9 outputs a high voltage signal and provides the high voltage signal to the third terminal through K5.
  • Five-switch control terminal E in the light-emitting phase te, TK5 is turned on, TE is turned on, the drain of TE is connected to the fifth light-emitting control voltage, and M1 emits light;
  • Vdata1 is a low voltage signal
  • Vdata2 is a high voltage signal
  • Vdata3 is a low voltage signal
  • Vdata4 is a low voltage signal
  • S1 outputs a high voltage signal
  • K1 is on
  • K2 is off
  • S2 outputs a low voltage signal
  • the input terminal of S3 When the low-voltage signal is connected, S3 outputs a high-voltage signal, K3 is turned on, K4 is turned off, S6 outputs a high-voltage signal, and S6 provides the high-voltage signal to the first switch control terminal A through the turned-on K3; during the light-emitting phase te, TK1 is turned on, TE is turned on, the drain of TE is connected to the first light-emitting control voltage, and M1 emits light;
  • Vdata1 is a low voltage signal
  • Vdata2 is a low voltage signal
  • Vdata3 is a high voltage signal
  • Vdata4 is a low voltage signal
  • S1 outputs a high voltage signal
  • S2 provides a high voltage signal
  • K1 is turned on
  • K2 is turned off
  • the input terminal of S3 A high voltage signal is connected
  • S3 outputs a low voltage signal
  • K3 is turned off
  • K4 is turned on
  • the input terminal of S7 is connected with a high voltage signal
  • the high voltage signal is written into the third switch control terminal C
  • TK3 conducts On, TE is turned on, the drain of TE is connected to the third lighting control voltage, and M1 emits light;
  • Vdata1 is a low voltage signal
  • Vdata2 is a low voltage signal
  • Vdata3 is a low voltage signal
  • Vdata4 is a high voltage signal
  • S1 outputs a high voltage signal
  • S2 outputs a high voltage signal
  • K1 is turned on
  • K2 is turned off
  • the input terminal of S3 A high voltage signal is connected
  • S3 outputs a low voltage signal
  • K3 is turned off
  • K4 is turned on
  • the input terminal of S6 is connected to a low voltage signal
  • the input terminal of S7 is connected to a low voltage signal
  • S7 outputs a high voltage signal to the fourth switch control Terminal D
  • TK4 is turned on, TE is turned on, the drain of TE is connected to the fourth light-emitting control voltage, and M1 emits light
  • TK4 is turned on
  • TE is turned on
  • the drain of TE is connected to the fourth light-emitting control voltage
  • M1 emits light
  • Vdata1 is a high voltage signal
  • Vdata2 is a high voltage signal
  • Vdata3 is a low voltage signal
  • Vdata4 is a low voltage signal
  • S1 outputs a low voltage signal
  • S2 outputs a low voltage signal
  • K1 is turned off
  • K2 is turned on
  • the input terminal of S4 A high voltage signal is connected
  • S4 outputs a low voltage signal
  • K7 is turned off
  • K8 is turned on
  • the input terminal of S9 is connected to a low voltage signal
  • the input terminal of S10 is connected to a low voltage signal
  • S10 outputs a high voltage signal to the eighth switch control Terminal H
  • TK8 is turned on, TE is turned on, the drain of TE is connected to the eighth light-emitting control voltage
  • M1 emits light
  • Vdata1 is a high voltage signal
  • Vdata2 is a high voltage signal
  • Vdata3 is a low voltage signal
  • Vdata4 is a high voltage signal
  • S1 outputs a low voltage signal
  • S2 outputs a low voltage signal
  • K1 is turned off
  • K2 is turned on
  • the input terminal of S4 A high voltage signal is connected
  • S4 outputs a low voltage signal
  • K7 is turned off
  • K8 is turned on
  • the input terminal of S9 is connected to a high voltage signal
  • the input terminal of S10 is connected to a high voltage signal
  • S10 outputs a low voltage signal to convert the high voltage
  • the signal is written into the seventh switch control terminal G; during the light-emitting phase te, TK7 is turned on, TE is turned on, the drain of TE is connected to the seventh light-emitting control voltage, and M1 emits light;
  • Vdata1 is a high voltage signal
  • Vdata2 is a high voltage signal
  • Vdata3 is a high voltage signal
  • Vdata4 is a low voltage signal
  • S1 outputs a low voltage signal
  • S2 outputs a low voltage signal
  • K1 is turned off
  • K2 is turned on
  • the input terminal of S4 When a high voltage signal is connected, S4 outputs a low voltage signal, K7 is turned off, K8 is on, the input terminal of S9 is connected to a low voltage signal, S9 outputs a high voltage signal, the input terminal of S10 is connected to a low voltage signal, and S10 outputs a high voltage signal.
  • the signal goes to the eighth switch control terminal H; during the light-emitting phase te, TK8 is turned on, TE is turned on, the drain of TE is connected to the eighth light-emitting control voltage, and M1 emits light;
  • Vdata1 is a high voltage signal
  • Vdata2 is a high voltage signal
  • Vdata3 is a high voltage signal
  • Vdata4 is a high voltage signal
  • S1 outputs a low voltage signal
  • S2 outputs a low voltage signal
  • K1 is turned off
  • K2 is turned on
  • the input terminal of S4 When a high voltage signal is connected, S4 outputs a low voltage signal, K7 is turned off, K8 is on, the input terminal of S9 is connected to a high voltage signal, S9 outputs a low voltage signal, the input terminal of S10 is connected to a high voltage signal, and S10 outputs a low voltage signal.
  • TK7 is turned on, TE is turned on, the drain of TE is connected to the seventh light-emitting control voltage, and M1 emits light;
  • Vdata1 is a high voltage signal
  • Vdata2 is a low voltage signal
  • Vdata3 is a high voltage signal
  • Vdata4 is a high voltage signal
  • S1 outputs a low voltage signal
  • S2 outputs a high voltage signal
  • K1 is turned off
  • K2 is turned on
  • the input terminal of S4 When a low voltage signal is connected, S4 outputs a high voltage signal, K7 is on, K8 is off, the input terminal of S9 is connected to a high voltage signal, S9 outputs a low voltage signal to the input terminal of S8, and S8 outputs a high voltage signal to the sixth switch.
  • Control terminal F in the light-emitting phase te, TK6 is turned on, TE is turned on, the drain of TE is connected to the sixth light-emitting control voltage, and M1 emits light;
  • Vdata1 is a high voltage signal
  • Vdata2 is a low voltage signal
  • Vdata3 is a low voltage signal
  • Vdata4 is a high voltage signal
  • S1 outputs a low voltage signal
  • S2 provides a high voltage signal
  • K1 is turned off
  • K2 is turned on
  • the input terminal of S4 When a low voltage signal is connected, S4 outputs a high voltage signal, K7 is on, K8 is off, the input terminal of S9 is connected to a high voltage signal, S9 outputs a low voltage signal to the input terminal of S8, and S8 outputs a high voltage signal to the sixth switch.
  • Control terminal F in the light-emitting phase te, TK6 is turned on, TE is turned on, the drain of TE is connected to the sixth light-emitting control voltage, and M1 emits light;
  • Vdata1 is a high voltage signal
  • Vdata2 is a low voltage signal
  • Vdata3 is a high voltage signal
  • Vdata4 is a low voltage signal
  • S1 outputs a low voltage signal
  • S2 provides a high voltage signal
  • K1 is turned off
  • K2 is turned on
  • the input terminal of S4 When a low voltage signal is connected, S4 outputs a high voltage signal, K7 is on, K8 is off, the input terminal of S9 is connected to a low voltage signal, S9 outputs a high voltage signal to the input terminal of S8, S8 outputs a low voltage signal, and S9 outputs a high voltage signal.
  • the voltage signal goes to the fifth switch control terminal E; during the light-emitting phase te, TK5 is turned on, TE is turned on, the drain of TE is connected to the fifth light-emitting control voltage, and M1 emits light;
  • Vdata1 is a low voltage signal
  • Vdata2 is a high voltage signal
  • Vdata3 is a high voltage signal
  • Vdata4 is a high voltage signal
  • S1 outputs a high voltage signal
  • S2 outputs a low voltage signal
  • K1 is turned on
  • K2 is turned off
  • S3 outputs a high voltage signal
  • K4 is off
  • the input terminal of S6 is connected to a high voltage signal
  • S6 outputs a low voltage signal
  • the input terminal of S5 is connected to a low voltage signal
  • S5 outputs a high voltage
  • the signal goes to the second switch control terminal B; during the light-emitting phase te, TK2 is turned on, TE is turned on, the drain of TE is connected to the second light-emitting control voltage, and M1 emits light;
  • Vdata1 is a low voltage signal
  • Vdata2 is a high voltage signal
  • Vdata3 is a low voltage signal
  • Vdata4 is a high voltage signal
  • S1 outputs a high voltage signal
  • S2 outputs a low voltage signal
  • K1 is turned on
  • K2 is turned off
  • the input terminal of S3 When a low-voltage signal is connected, S3 outputs a high-voltage signal, K3 is turned on, K4 is turned off, the input terminal of S6 is connected with a low-voltage signal, and S6 outputs a high-voltage signal to the first switch control terminal A; during the light-emitting phase te, TK1 is turned on On, TE is turned on, the drain of TE is connected to the first light-emitting control voltage, and M1 emits light;
  • Vdata1 is a low voltage signal
  • Vdata2 is a high voltage signal
  • Vdata3 is a high voltage signal
  • Vdata4 is a low voltage signal
  • S1 outputs a high voltage signal
  • S2 outputs a low voltage signal
  • K1 is turned on
  • K2 is turned off
  • the input terminal of S3 Connect a low voltage signal
  • S3 outputs a high voltage signal
  • K3 is on
  • K4 off
  • the input terminal of S6 is connected to a high voltage signal
  • S6 outputs a low voltage signal to the input terminal of S5, and
  • S5 outputs a high voltage signal to the second switch.
  • Control terminal B in the light-emitting phase te, TK2 is turned on, TE is turned on, the drain of TE is connected to the second light-emitting control voltage, and M1 emits light;
  • Vdata1 is a low voltage signal
  • Vdata2 is a low voltage signal
  • Vdata3 is a high voltage signal
  • Vdata4 is a high voltage signal
  • S1 outputs a high voltage signal
  • S2 outputs a high voltage signal
  • K1 is turned on
  • K2 is turned off
  • the input terminal of S3 A high voltage signal is connected
  • S3 outputs a low voltage signal
  • K3 is turned off
  • K4 is turned on
  • the input terminal of S6 is connected to a high voltage signal
  • the input terminal of S7 is connected to a high voltage signal
  • S7 outputs a low voltage signal
  • the high voltage signal is connected to
  • the signal is provided to the third switch control terminal C; during the light-emitting phase te, TK3 is turned on, TE is turned on, the drain of TE is connected to the third light-emitting control voltage, and M1 emits light.
  • the light-emitting circuit may include an amplitude control sub-circuit, a driving sub-circuit, a first on-off control sub-circuit and a light-emitting element; the first terminal of the driving sub-circuit is electrically connected to the second voltage terminal. connect;
  • the amplitude control sub-circuit is used to control the driving current generated by the driving sub-circuit according to the display data voltage
  • the lighting control circuit is used to control the connection between the control voltage input terminal and the control terminal of the first on-off control sub-circuit under the control of the lighting control signal;
  • the control end of the first on-off control sub-circuit is electrically connected to the lighting control circuit, the first end of the first on-off control sub-circuit is electrically connected to the second end of the driving sub-circuit, and the first on-off control sub-circuit is electrically connected to the second end of the driving sub-circuit.
  • the second end of an on-off control sub-circuit is electrically connected to the light-emitting element; the first on-off control sub-circuit is used to control the connection between the driving sub-circuit and the light-emitting element under the control of the potential of its control end. connected between.
  • the second voltage terminal may be a high voltage terminal, but is not limited thereto.
  • the amplitude control subcircuit includes a data writing subcircuit, an energy storage subcircuit and a reset subcircuit;
  • the data writing sub-circuit is electrically connected to the first scanning line, the data line and the control end of the driving sub-circuit respectively, and is used to write the said data under the control of the first scanning signal provided by the first scanning line.
  • the data voltage provided by the data line is written into the control end of the driving subcircuit;
  • the reset sub-circuit is electrically connected to the first scan line, the reset voltage terminal and the second terminal of the driver sub-circuit respectively, and is used to control the reset voltage terminal to provide the voltage under the control of the first scan signal.
  • the reset voltage is written into the second terminal of the driving sub-circuit;
  • the energy storage sub-circuit is electrically connected to the control end of the driving sub-circuit and the second end of the driving sub-circuit, respectively, for storing electrical energy;
  • the driving sub-circuit is used to generate a driving current under the control of the potential of its control terminal.
  • the amplitude control subcircuit includes a data writing subcircuit and an energy storage subcircuit;
  • the data writing sub-circuit is electrically connected to the control end of the scanning line, the data line and the driving sub-circuit respectively.
  • the data writing sub-circuit is used to write the data under the control of the scanning signal provided by the scanning line.
  • the voltage of the data provided by the data line is written into the control end of the driving sub-circuit;
  • the energy storage sub-circuit is electrically connected to the control terminal and the first common electrode terminal of the driving sub-circuit respectively, and is used to store electrical energy;
  • the driving sub-circuit is used to generate a driving current under the control of the potential of its control terminal.
  • At least one embodiment of the light-emitting circuit may include an amplitude control sub-circuit 110, a driving sub-circuit 111, a first on-off control sub-circuit 112 and a light-emitting element 10; the first of the driving sub-circuit 111 terminal is electrically connected to the second voltage terminal V2;
  • the amplitude control sub-circuit 110 is electrically connected to the driving sub-circuit 111, and is used to control the driving current generated by the driving sub-circuit 111 according to the display data voltage;
  • the lighting control circuit 11 is used to control the connection between the control voltage input terminal I1 and the control terminal of the first on-off control sub-circuit 112 under the control of the lighting control signal;
  • the control end of the first on-off control sub-circuit 112 is electrically connected to the lighting control circuit 11, and the first end of the first on-off control sub-circuit 112 is electrically connected to the second end of the driving sub-circuit 111.
  • the second end of the first on-off control sub-circuit 112 is electrically connected to the first pole of the light-emitting element 10; the first on-off control sub-circuit 112 is used to control, under the control of the potential of its control end,
  • the driving sub-circuit 111 is connected to the light-emitting element 10;
  • the second pole of the light-emitting element 10 is electrically connected to the first voltage terminal V1.
  • the first voltage terminal V1 may be a low voltage terminal.
  • the amplitude control sub-circuit may include a data writing sub-circuit 121, an energy storage sub-circuit 122 and a reset sub-circuit 123;
  • the data writing sub-circuit 121 is electrically connected to the first scanning line GT1, the data line DA and the control end of the driving sub-circuit 111 respectively, and is used for controlling the first scanning signal provided on the first scanning line GT1 Next, the data voltage provided by the data line DA is written into the control end of the driving sub-circuit 111; the data line DA is used to provide a display data voltage;
  • the reset sub-circuit 123 is electrically connected to the first scan line GT1, the reset voltage terminal R1 and the second end of the drive sub-circuit 111, respectively, and is used to control the reset under the control of the first scan signal.
  • the reset voltage provided by voltage terminal R1 is written into the second terminal of the driving sub-circuit 111;
  • the energy storage sub-circuit 122 is electrically connected to the control end of the driving sub-circuit 111 and the second end of the driving sub-circuit 111 respectively, and is used to store electrical energy;
  • the driving sub-circuit 111 is used to generate a driving current under the control of the potential of its control terminal.
  • the amplitude control sub-circuit may include a data writing sub-circuit 121 and an energy storage sub-circuit 122;
  • the data writing sub-circuit 121 is electrically connected to the scanning line GT, the data line DA and the control end of the driving sub-circuit 111 respectively.
  • the data writing sub-circuit 121 is used to provide scanning signals on the scanning line GT. Under the control of, write the voltage of the data provided by the data line DA to the control end of the driving sub-circuit 111;
  • the energy storage sub-circuit 122 is electrically connected to the control terminal and the first common electrode terminal VM1 of the driving sub-circuit 111 respectively, and is used to store electrical energy;
  • the driving sub-circuit 111 is used to generate a driving current under the control of the potential of its control terminal.
  • the amplitude control sub-circuit may also include a second on-off control sub-circuit 141;
  • the second on-off control sub-circuit is electrically connected to the light-emitting control terminal EM, the second voltage terminal V2 and the first end of the driving sub-circuit 111 respectively, and is used for controlling the light-emitting control signal provided by the light-emitting control terminal EM. Under control, the second voltage terminal V2 is controlled to be connected to the first terminal of the driving sub-circuit 111 .
  • the light-emitting element 10 is replaced with at least one embodiment of the light-emitting circuit shown in Figure 11;
  • the lighting control circuit 11 is electrically connected to the control end of the first on-off control sub-circuit 112 .
  • the light-emitting element 10 is replaced with at least one embodiment of the light-emitting circuit shown in Figure 11;
  • the lighting control circuit 11 is electrically connected to the control end of the first on-off control sub-circuit 112 .
  • micro light-emitting diode M1 is replaced with at least one embodiment of the light-emitting circuit shown in Figure 11;
  • the source of the light emission control transistor TE is electrically connected to the control terminal of the first on-off control sub-circuit 112 .
  • the display cycle includes a first writing phase, a second writing phase and a light-emitting phase that are set successively;
  • G1 provides a high voltage signal
  • D1 provides the first data voltage Vdata1
  • TW1 is turned on to write Vdata1 to the input terminal of S1;
  • G2 provides a high voltage signal
  • D1 provides the second data voltage Vdata2
  • TW2 is turned on to write Vdata2 to the input terminal of S2;
  • Vdata1 is a low voltage signal and Vdata2 is a low voltage signal
  • S1 outputs a high voltage signal
  • S2 outputs a high voltage signal
  • TC1 is turned on
  • TC2 is turned off
  • the input terminal of S3 is connected to a high voltage signal
  • the first switch control terminal A The low voltage signal is connected
  • the second switch control terminal B is connected to the high voltage signal
  • the potential of the third switch control terminal C and the fourth switch control terminal D are low voltage
  • TK1 is turned off
  • TK2 is turned on
  • TK3 and TK4 are turned off. off
  • I1 is connected to the second light-emitting control voltage
  • TE is turned on
  • the drain of TE is connected to the second light-emitting control voltage
  • Vdata1 is a low voltage signal and Vdata2 is a high voltage signal
  • S1 outputs a high voltage signal
  • S2 outputs a low voltage signal
  • TC1 is turned on
  • TC2 is turned off
  • the input terminal of S3 is connected to the low voltage signal
  • the first switch control terminal A The high voltage signal is connected
  • the second switch control terminal B is connected to the low voltage signal
  • the potential of the third switch control terminal C and the fourth switch control terminal D are low voltage
  • TK1 is turned on
  • TK2 is turned off
  • TK3 and TK4 are turned off. is off
  • I1 is connected to the first light-emitting control voltage
  • TE is turned on
  • the drain of TE is connected to the first light-emitting control voltage
  • Vdata1 is a high voltage signal and Vdata2 is a low voltage signal
  • S1 outputs a low voltage signal
  • S2 outputs a high voltage signal
  • TC1 is turned off
  • TC2 is turned on
  • the input terminal of S4 is connected to the low voltage signal
  • the third switch control terminal C The high voltage signal is connected
  • the fourth switch control terminal D is connected to the low voltage signal
  • the potential of the first switch control terminal A and the potential of the second switch control terminal B are low voltage
  • TK3 is turned on
  • TK4 is turned off
  • TK1 and TK2 are turned off. off
  • I1 is connected to the third lighting control voltage
  • TE is turned on
  • the drain of TE is connected to the third lighting control voltage
  • Vdata1 is a high voltage signal and Vdata2 is a high voltage signal
  • S1 outputs a low voltage signal
  • S2 outputs a low voltage signal
  • TC1 is turned off
  • TC2 is turned on
  • the input terminal of S4 is connected to the high voltage signal
  • the third switch control terminal C When the low voltage signal is connected, the fourth switch control terminal D is connected to the high voltage signal, the potential of the first switch control terminal A and the potential of the second switch control terminal B are low voltage, TK4 is turned on, TK3 is turned off, and TK1 and TK2 are turned off. off, I1 is connected to the fourth lighting control voltage; during the lighting phase, TE is turned on, and the drain of TE is connected to the fourth lighting control voltage.
  • the first light-emitting control voltage, the second light-emitting control voltage, the third light-emitting control voltage and the fourth light-emitting control voltage may all be square wave voltage signals,
  • the duty cycle of the first lighting control voltage, the duty cycle of the second lighting control voltage, the duty cycle of the third lighting control voltage and the duty cycle of the fourth lighting control voltage are different, so that the first lighting control voltage can be controlled
  • the different conduction times of the on-off control subcircuit cause the light-emitting elements to emit light for different lengths of time, thereby enabling low-gray-scale display with different gray-scale values and improving the uniformity of low-gray-scale display.
  • the micro light-emitting diode M1 is replaced with at least one embodiment of the light-emitting circuit shown in Figure 11;
  • the source of the light emission control transistor TE is electrically connected to the control terminal of the first on-off control sub-circuit 112 .
  • the display cycle may include a first writing stage, a second writing stage, a third writing stage, a fourth writing stage and a light emitting stage that are set successively. stage;
  • G1 provides a high voltage signal
  • G2, G3 and G4 all provide low voltage signals
  • D1 provides the first data voltage Vdata1 to the first data access terminal DI1;
  • G2 provides a high voltage signal
  • G1, G3 and G4 all provide low voltage signals
  • D2 provides the second data voltage Vdata2 to the second data access terminal DI2;
  • G3 provides high voltage signals
  • G1, G2 and G4 all provide low voltage signals
  • D3 provides the third data voltage Vdata3 to the third data access terminal DI3;
  • G4 provides a high voltage signal
  • G1, G2 and G3 all provide low voltage signals
  • D4 provides the fourth data voltage Vdata4 to the fourth data access terminal DI4;
  • Vdata1 is a low voltage signal
  • Vdata2 is a low voltage signal
  • Vdata3 is a low voltage signal
  • Vdata4 is a low voltage signal
  • the gate of K1 is connected to the high voltage signal
  • the gate of K2 is connected to the low voltage signal
  • K1 is turned on.
  • K2 is turned off, the input terminal of S3 is connected to a high voltage signal
  • S3 outputs a low voltage signal
  • K3 is turned off
  • K4 is turned on
  • the input terminal of S7 is connected to a low voltage signal
  • S7 outputs a high voltage signal to the fourth switch control terminal D
  • TK4 is turned on, TE is turned on, and the drain of TE is connected to the fourth light-emitting control voltage
  • Vdata1 is a high voltage signal
  • Vdata2 is a low voltage signal
  • Vata3 is a low voltage signal
  • Vdata4 is a low voltage signal
  • S1 outputs a low voltage signal
  • K1 is turned off
  • S2 outputs a high voltage signal
  • K2 is turned on
  • the input terminal of S4 A low voltage signal is connected to the control terminal of K5.
  • a high voltage signal is connected to the control terminal of K5.
  • K5 is turned on and K6 is turned off.
  • a low voltage signal is connected to the input terminal of S9.
  • S9 outputs a high voltage signal and provides the high voltage signal to the third terminal through K5.
  • Five-switch control terminal E during the light-emitting phase, TK5 is turned on, TE is turned on, and the drain of TE is connected to the fifth light-emitting control voltage;
  • Vdata1 is a low voltage signal
  • Vdata2 is a high voltage signal
  • Vdata3 is a low voltage signal
  • Vdata4 is a low voltage signal
  • S1 outputs a high voltage signal
  • K1 is on
  • K2 is off
  • S2 outputs a low voltage signal
  • the input terminal of S3 When the low-voltage signal is connected, S3 outputs a high-voltage signal, K3 is turned on, K4 is turned off, S6 outputs a high-voltage signal, and S6 provides the high-voltage signal to the first switch control terminal A through the turned-on K3; during the light-emitting phase, TK1 Turn on, TE turns on, and the drain of TE is connected to the first light-emitting control voltage;
  • Vdata1 is a low voltage signal
  • Vdata2 is a low voltage signal
  • Vdata3 is a high voltage signal
  • Vdata4 is a low voltage signal
  • S1 outputs a high voltage signal
  • S2 provides a high voltage signal
  • K1 is turned on
  • K2 is turned off
  • the input terminal of S3 When a high-voltage signal is connected, S3 outputs a low-voltage signal, K3 is turned off, K4 is turned on, the input terminal of S7 is connected to a high-voltage signal, and the high-voltage signal is written into the third switch control terminal C; during the light-emitting phase, TK3 is turned on.
  • TE is turned on, and the drain of TE is connected to the third lighting control voltage;
  • Vdata1 is a low voltage signal
  • Vdata2 is a low voltage signal
  • Vdata3 is a low voltage signal
  • Vdata4 is a high voltage signal
  • S1 outputs a high voltage signal
  • S2 outputs a high voltage signal
  • K1 is turned on
  • K2 is turned off
  • the input terminal of S3 A high voltage signal is connected
  • S3 outputs a low voltage signal
  • K3 is turned off
  • K4 is turned on
  • the input terminal of S6 is connected to a low voltage signal
  • the input terminal of S7 is connected to a low voltage signal
  • S7 outputs a high voltage signal to the fourth switch control Terminal D
  • TK4 is turned on, TE is turned on, and the drain of TE is connected to the fourth light-emitting control voltage
  • Vdata1 is a high voltage signal
  • Vdata2 is a high voltage signal
  • Vdata3 is a low voltage signal
  • Vdata4 is a low voltage signal
  • S1 outputs a low voltage signal
  • S2 outputs a low voltage signal
  • K1 is turned off
  • K2 is turned on
  • the input terminal of S4 A high voltage signal is connected
  • S4 outputs a low voltage signal
  • K7 is turned off
  • K8 is turned on
  • the input terminal of S9 is connected to a low voltage signal
  • the input terminal of S10 is connected to a low voltage signal
  • S10 outputs a high voltage signal to the eighth switch control Terminal H
  • TK8 is turned on, TE is turned on, and the drain of TE is connected to the eighth light-emitting control voltage
  • TK8 is turned on
  • TE is turned on
  • the drain of TE is connected to the eighth light-emitting control voltage
  • Vdata1 is a high voltage signal
  • Vdata2 is a high voltage signal
  • Vdata3 is a low voltage signal
  • Vdata4 is a high voltage signal
  • S1 outputs a low voltage signal
  • S2 outputs a low voltage signal
  • K1 is turned off
  • K2 is turned on
  • the input terminal of S4 A high voltage signal is connected
  • S4 outputs a low voltage signal
  • K7 is turned off
  • K8 is turned on
  • the input terminal of S9 is connected to a high voltage signal
  • the input terminal of S10 is connected to a high voltage signal
  • S10 outputs a low voltage signal to convert the high voltage
  • the signal is written into the seventh switch control terminal G; during the light-emitting phase, TK7 is turned on, TE is turned on, and the drain of TE is connected to the seventh light-emitting control voltage;
  • Vdata1 is a high voltage signal
  • Vdata2 is a high voltage signal
  • Vdata3 is a high voltage signal
  • Vdata4 is a low voltage signal
  • S1 outputs a low voltage signal
  • S2 outputs a low voltage signal
  • K1 is turned off
  • K2 is turned on
  • the input terminal of S4 When a high voltage signal is connected, S4 outputs a low voltage signal, K7 is turned off, K8 is on, the input terminal of S9 is connected to a low voltage signal, S9 outputs a high voltage signal, the input terminal of S10 is connected to a low voltage signal, and S10 outputs a high voltage signal.
  • the signal goes to the eighth switch control terminal H; during the light-emitting phase, TK8 is turned on, TE is turned on, and the drain of TE is connected to the eighth light-emitting control voltage;
  • Vdata1 is a high voltage signal
  • Vdata2 is a high voltage signal
  • Vdata3 is a high voltage signal
  • Vdata4 is a high voltage signal
  • S1 outputs a low voltage signal
  • S2 outputs a low voltage signal
  • K1 is turned off
  • K2 is turned on
  • the input terminal of S4 When a high voltage signal is connected, S4 outputs a low voltage signal, K7 is turned off, K8 is on, the input terminal of S9 is connected to a high voltage signal, S9 outputs a low voltage signal, the input terminal of S10 is connected to a high voltage signal, and S10 outputs a low voltage signal.
  • Vdata1 is a high voltage signal
  • Vdata2 is a low voltage signal
  • Vdata3 is a high voltage signal
  • Vdata4 is a high voltage signal
  • S1 outputs a low voltage signal
  • S2 outputs a high voltage signal
  • K1 is turned off
  • K2 is turned on
  • the input terminal of S4 When a low voltage signal is connected, S4 outputs a high voltage signal, K7 is on, K8 is off, the input terminal of S9 is connected to a high voltage signal, S9 outputs a low voltage signal to the input terminal of S8, and S8 outputs a high voltage signal to the sixth switch.
  • Control terminal F during the light-emitting phase, TK6 is turned on, TE is turned on, and the drain of TE is connected to the sixth light-emitting control voltage;
  • Vdata1 is a high voltage signal
  • Vdata2 is a low voltage signal
  • Vdata3 is a low voltage signal
  • Vdata4 is a high voltage signal
  • S1 outputs a low voltage signal
  • S2 provides a high voltage signal
  • K1 is turned off
  • K2 is turned on
  • the input terminal of S4 When a low voltage signal is connected, S4 outputs a high voltage signal, K7 is on, K8 is off, the input terminal of S9 is connected to a high voltage signal, S9 outputs a low voltage signal to the input terminal of S8, and S8 outputs a high voltage signal to the sixth switch.
  • Control terminal F during the light-emitting phase, TK6 is turned on, TE is turned on, and the drain of TE is connected to the sixth light-emitting control voltage;
  • Vdata1 is a high voltage signal
  • Vdata2 is a low voltage signal
  • Vdata3 is a high voltage signal
  • Vdata4 is a low voltage signal
  • S1 outputs a low voltage signal
  • S2 provides a high voltage signal
  • K1 is turned off
  • K2 is turned on
  • the input terminal of S4 When a low voltage signal is connected, S4 outputs a high voltage signal, K7 is on, K8 is off, the input terminal of S9 is connected to a low voltage signal, S9 outputs a high voltage signal to the input terminal of S8, S8 outputs a low voltage signal, and S9 outputs a high voltage signal.
  • the voltage signal goes to the fifth switch control terminal E; during the light-emitting phase, TK5 is turned on, TE is turned on, and the drain of TE is connected to the fifth light-emitting control voltage;
  • Vdata1 is a low voltage signal
  • Vdata2 is a high voltage signal
  • Vdata3 is a high voltage signal
  • Vdata4 is a high voltage signal
  • S1 outputs a high voltage signal
  • S2 outputs a low voltage signal
  • K1 is turned on
  • K2 is turned off
  • S3 outputs a high voltage signal
  • K4 is off
  • the input terminal of S6 is connected to a high voltage signal
  • S6 outputs a low voltage signal
  • the input terminal of S5 is connected to a low voltage signal
  • S5 outputs a high voltage
  • the signal goes to the second switch control terminal B; during the light-emitting phase, TK2 is turned on, TE is turned on, and the drain of TE is connected to the second light-emitting control voltage;
  • Vdata1 is a low voltage signal
  • Vdata2 is a high voltage signal
  • Vdata3 is a low voltage signal
  • Vdata4 is a high voltage signal
  • S1 outputs a high voltage signal
  • S2 outputs a low voltage signal
  • K1 is turned on
  • K2 is turned off
  • the input terminal of S3 When a low-voltage signal is connected, S3 outputs a high-voltage signal, K3 is turned on, K4 is turned off, the input terminal of S6 is connected to a low-voltage signal, and S6 outputs a high-voltage signal to the first switch control terminal A; during the light-emitting phase, TK1 is turned on. , TE is turned on, and the drain of TE is connected to the first lighting control voltage;
  • Vdata1 is a low voltage signal
  • Vdata2 is a high voltage signal
  • Vdata3 is a high voltage signal
  • Vdata4 is a low voltage signal
  • S1 outputs a high voltage signal
  • S2 outputs a low voltage signal
  • K1 is turned on
  • K2 is turned off
  • the input terminal of S3 Connect a low voltage signal
  • S3 outputs a high voltage signal
  • K3 is on
  • K4 is off
  • the input terminal of S6 is connected to a high voltage signal
  • S6 outputs a low voltage signal to the input terminal of S5, and
  • S5 outputs a high voltage signal to the second switch.
  • Control terminal B during the light-emitting phase, TK2 is turned on, TE is turned on, and the drain of TE is connected to the second light-emitting control voltage;
  • Vdata1 is a low voltage signal
  • Vdata2 is a low voltage signal
  • Vdata3 is a high voltage signal
  • Vdata4 is a high voltage signal
  • S1 outputs a high voltage signal
  • S2 outputs a high voltage signal
  • K1 is turned on
  • K2 is turned off
  • the input terminal of S3 A high voltage signal is connected
  • S3 outputs a low voltage signal
  • K3 is turned off
  • K4 is turned on
  • the input terminal of S6 is connected to a high voltage signal
  • the input terminal of S7 is connected to a high voltage signal
  • S7 outputs a low voltage signal
  • the high voltage signal is connected to
  • the signal is provided to the third switch control terminal C; during the light-emitting phase, TK3 is turned on, TE is turned on, and the drain of TE is connected to the third light-emitting control voltage.
  • the first light-emitting control voltage, the second light-emitting control voltage, the third light-emitting control voltage, the fourth light-emitting control voltage, the fifth light-emitting control voltage, and the third light-emitting control voltage are used.
  • the sixth light-emitting control voltage, the seventh light-emitting control voltage and the eighth light-emitting control voltage may all be square wave voltage signals, and the duty cycle of the first light-emitting control voltage, the duty cycle of the second light-emitting control voltage, and the third light-emitting control voltage
  • the duty cycle is different, so that the conduction time of the first on-off control sub-circuit can be controlled to be different, thereby achieving low gray-scale display with different gray-scale values, and improving low gray-scale display uniformity.
  • the amplitude control subcircuit may include a data writing subcircuit, an energy storage subcircuit and a reset subcircuit;
  • the data writing sub-circuit includes a first data writing transistor T1; the energy storage sub-circuit includes a storage capacitor C1; the reset sub-circuit includes a reset transistor T3; the driving sub-circuit includes a driving transistor T0; An on-off control circuit includes a first on-off control transistor T4; the light-emitting element is a miniature light-emitting diode M1;
  • the source of TE is electrically connected to the gate of T4;
  • the gate of T1 is electrically connected to the scan line GT, the drain of T1 is electrically connected to the data line DA, and the source of T1 is electrically connected to the gate of T0;
  • the drain of T0 is electrically connected to the high voltage terminal VDD, the source of T0 is electrically connected to the drain of T4, the source of T4 is electrically connected to the anode of M1, and the cathode of M1 is electrically connected to the low voltage terminal VSS;
  • the first end of C1 is electrically connected to the gate of T0, and the second end of C1 is electrically connected to the source of T0.
  • each transistor is an n-type transistor, but is not limited to this.
  • first GT provides
  • High voltage signal, T1 and T3 are turned on to write the display data voltage provided by DA into the gate of T0, and write the reset voltage provided by R1 into the source of T0; after that, EM provides a high voltage signal, TE is turned on, and the A light-emitting control voltage, a second light-emitting control voltage, a third light-emitting control voltage or a fourth light-emitting control voltage are connected to the gate of T4 to control T4 to be turned on or off.
  • T4 When T4 is turned on, T0 drives M1 to emit light.
  • the amplitude control subcircuit may include a data writing subcircuit and an energy storage subcircuit;
  • the data writing sub-circuit includes a first data writing transistor T1 and a second data writing transistor T2; the energy storage sub-circuit includes a storage capacitor C1; the driving sub-circuit includes a driving transistor T0; the first pass The off control circuit includes a first on-off control transistor T4; the light-emitting element is a miniature light-emitting diode M1;
  • the source of TE is electrically connected to the gate of T4;
  • the first end of C1 is electrically connected to the gate of T0, and the second end of C2 is electrically connected to the first common electrode terminal VM1;
  • the gate of T1 is electrically connected to the first scan line GT1, the drain of T1 is electrically connected to the data line DA, the source of T1 is electrically connected to the gate of T0; the drain of T0 is electrically connected to the high voltage terminal VDD;
  • the gate of T2 is electrically connected to the second scan line GT2, the source of T2 is electrically connected to the data line DA, and the drain of T2 is electrically connected to the gate of T0;
  • the source of T0 is electrically connected to the drain of T4, the source of T4 is electrically connected to the anode of M1, and the cathode of M1 is electrically connected to the low voltage terminal VSS.
  • T1 is an n-type transistor
  • T2 is a p-type transistor, so as to expand the voltage range of the display data voltage provided by the data line DA that can be written into the gate of T0 .
  • T0 and T4 are n-type transistors.
  • first GT1 provides a high voltage signal or GT2 provides a low voltage signal
  • T1 or T2 is turned on to write the display data voltage provided by DA into the gate of T0. pole; after that, EM provides a high voltage signal, TE is turned on, and the first light-emitting control voltage, the second light-emitting control voltage, the third light-emitting control voltage, or the fourth light-emitting control voltage are connected to the gate of T4 to control T4 to turn on or off.
  • T4 is turned on, T0 drives M1 to emit light.
  • the amplitude control subcircuit may include a data writing subcircuit, an energy storage subcircuit and a reset subcircuit;
  • the data writing sub-circuit includes a first data writing transistor T1; the energy storage sub-circuit includes a storage capacitor C1; the reset sub-circuit includes a reset transistor T3; the driving sub-circuit includes a driving transistor T0; An on-off control circuit includes a first on-off control transistor T4; the light-emitting element is a miniature light-emitting diode M1;
  • the source of TE is electrically connected to the gate of T4;
  • the gate of T1 is electrically connected to the scan line GT, the drain of T1 is electrically connected to the data line DA, and the source of T1 is electrically connected to the gate of T0;
  • the drain of T0 is electrically connected to the high voltage terminal VDD, the source of T0 is electrically connected to the drain of T4, the source of T4 is electrically connected to the anode of M1, and the cathode of M1 is electrically connected to the low voltage terminal VSS;
  • the first end of C1 is electrically connected to the gate of T0, and the second end of C1 is electrically connected to the source of T0.
  • each transistor is an n-type transistor, but is not limited to this.
  • first GT provides a high voltage signal
  • T1 and T3 are opened to write the display data voltage provided by DA into the gate of T0
  • R1 is provided
  • the reset voltage is written into the source of T0; after that, EM provides a high voltage signal, TE is turned on, the first light-emitting control voltage, the second light-emitting control voltage, the third light-emitting control voltage, the fourth light-emitting control voltage, and the fifth light-emitting control voltage , the sixth light-emitting control voltage, the seventh light-emitting control voltage or the eighth light-emitting control voltage are connected to the gate of T4 to control T4 to be turned on or off.
  • T4 When T4 is turned on, T0 drives M1 to emit light.
  • the amplitude control subcircuit may include a data writing subcircuit and an energy storage subcircuit;
  • the data writing sub-circuit includes a first data writing transistor T1 and a second data writing transistor T2; the energy storage sub-circuit includes a storage capacitor C1; the driving sub-circuit includes a driving transistor T0; the first pass The off control circuit includes a first on-off control transistor T4; the light-emitting element is a miniature light-emitting diode M1;
  • the source of TE is electrically connected to the gate of T4;
  • the first end of C1 is electrically connected to the gate of T0, and the second end of C2 is electrically connected to the first common electrode terminal VM1;
  • the gate of T1 is electrically connected to the first scan line GT1, the drain of T1 is electrically connected to the data line DA, the source of T1 is electrically connected to the gate of T0; the drain of T0 is electrically connected to the high voltage terminal VDD;
  • the gate of T2 is electrically connected to the second scan line GT2, the source of T2 is electrically connected to the data line DA, and the drain of T2 is electrically connected to the gate of T0;
  • the source of T0 is electrically connected to the drain of T4, the source of T4 is electrically connected to the anode of M1, and the cathode of M1 is electrically connected to the low voltage terminal VSS.
  • T1 is an n-type transistor
  • T2 is a p-type transistor, so as to expand the voltage range of the display data voltage provided by the data line DA that can be written into the gate of T0 .
  • T0 and T4 are n-type transistors.
  • first GT1 provides a high voltage signal or GT2 provides a low voltage signal
  • T1 or T2 is turned on to write the display data voltage provided by DA into the gate of T0. pole; after that, EM provides a high voltage signal, TE is turned on, the first light-emitting control voltage, the second light-emitting control voltage, the third light-emitting control voltage, the fourth light-emitting control voltage, the fifth light-emitting control voltage, the sixth light-emitting control voltage
  • the seventh light-emitting control voltage or the eighth light-emitting control voltage is connected to the gate of T4 to control T4 to be turned on or off.
  • T0 drives M1 to emit light.
  • the display device includes a display panel; the display area of the display panel has a plurality of sub-pixels, and the above-mentioned pixel circuit is provided in each sub-pixel.
  • the display panel includes a silicon substrate; the pixel circuit is provided on the silicon substrate.
  • the transistors included in the pixel circuit may be CMOS (Complementary Metal Oxide Semiconductor) transistors.
  • the substrate included in the display panel may be a semiconductor substrate, such as a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate such as silicon germanium, etc. Any of substrates, SOI (Silicon On Insulator, silicon on insulator) substrates, etc.
  • the substrate may also include organic resin materials such as epoxy, triazine, silicone, or polyimide.
  • the substrate may be an FR4 type printed circuit board (PCB), or may be a flexible PCB that is easily deformed.
  • PCB printed circuit board
  • the substrate may include a ceramic material such as silicon nitride, AIN (aluminum nitride), or Al2O3 (aluminum trioxide), or a metal or metal compound, or a metal core printed circuit board (MCPCB) or Any of metal copper clad laminates (MCCL).
  • a ceramic material such as silicon nitride, AIN (aluminum nitride), or Al2O3 (aluminum trioxide), or a metal or metal compound, or a metal core printed circuit board (MCPCB) or Any of metal copper clad laminates (MCCL).
  • the display device may be a silicon-based display device
  • the display panel in the display device may include a silicon substrate
  • the pixel circuit in the display panel may be a silicon-based field effect transistor
  • the The silicon substrate may include silicon element, such as polycrystalline silicon or monocrystalline silicon.
  • a silicon-based field effect transistor may also be called a silicon-based transistor.
  • the silicon-based field effect transistor includes a silicon substrate, a thin film microbridge and at least one thin film transistor; wherein the silicon base includes at least one microcavity, each The microcavity makes the thin film microbridge located on the microcavity suspended; the thin film microbridge is arranged above the silicon substrate, and the thin film transistor is arranged above the central area of each thin film microbridge.
  • Silicon-based transistors have the following advantages over glass-based thin film transistors:
  • the size of silicon-based transistors is tens to hundreds of nanometers, and the size of glass-based thin film transistors is several microns to tens of microns. Silicon-based transistors are small in size.
  • the conduction time of silicon-based transistors is tens of picoseconds, and the conduction time of glass-based thin film transistors is between tens and hundreds of nanoseconds (nanoseconds). The conduction time of silicon-based transistors is faster.
  • the stability of silicon-based transistors is higher than that of transistors prepared on glass substrates.
  • the pixel driving circuit composed of glass-based transistors does not need to compensate for the threshold voltage.
  • the display device can be any product or component with a display function such as a watch, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

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Abstract

一种像素电路和显示装置。像素电路包括发光电路、发光控制电路（11）、第一控制电路（12）和开关控制电路，发光控制电路（11）在发光控制信号的控制下，控制控制电压输入端（I1）与发光电路之间连通，发光电路根据控制电压输入端（I1）提供的控制电压发光，第一控制电路（12）在扫描信号的控制下，根据数据电压控制开关控制信号，开关控制电路包括N个开关控制端、N个发光控制电压端和N个开关控制子电路，第n开关控制子电路在第n开关控制信号的控制下，控制第n发光控制电压端与控制电压输入端（I1）之间连通，N为大于1的整数，n为小于等于N的正整数。能够实现高PPI，并提升低灰阶显示均一性。

Description

像素电路和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路和显示装置。
背景技术
Micro LED(微型发光二极管)和Mini LED(次毫米发光二极管)因其亮度高、寿命长、体积小等诸多优点在显示领域有巨大应用前景。在相关技术中，次毫米发光二极管的尺寸约为100μm-300μm，微型发光二极管的尺寸为100μm以下。
目前Micro LED显示面板和Mini LED显示面板无法实现高PPI(Pixels Per Inch，像素密度)显示，并低灰阶显示均一性差。
发明内容
在一个方面中，本公开实施例提供了一种像素电路，包括发光电路、发光控制电路、第一控制电路和开关控制电路；
所述发光控制电路分别与发光控制端、控制电压输入端和所述发光电路电连接，用于在所述发光控制端提供的发光控制信号的控制下，控制所述控制电压输入端与所述发光电路之间连通；
所述发光电路用于根据所述控制电压输入端提供的控制电压发光；
所述第一控制电路分别与至少两个数据电压端、至少两个扫描端和N个开关控制端电连接，用于在所述扫描端提供的扫描信号的控制下，根据所述数据电压端提供的数据电压，控制提供至所述开关控制端的开关控制信号；N为大于1的整数；
所述开关控制电路包括N个开关控制端、N个发光控制电压端和N个开关控制子电路；n为小于等于N的正整数；
第n开关控制子电路分别与第n开关控制端、第n发光控制电压端和所述控制电压输入端电连接，用于在所述第n开关控制端提供的第n开关控制信号的控制下，控制所述第n发光控制电压端与所述控制电压输入端之间连 通。
可选的，所述发光控制电压端提供的发光控制电压为直流电压，所述N个发光控制电压端提供的发光控制电压互不相同。
可选的，所述发光控制电压端提供的发光控制电压为方波电压信号，N个发光控制电压端提供的发光控制电压的占空比互不相同。
可选的，N等于2 a，a为正整数。
可选的，所述第一控制电路包括第一数据写入电路、第二数据写入电路和第一控制子电路；
所述第一数据写入电路分别与第一扫描端、第一数据电压端和第一数据接入端电连接，用于在所述第一扫描端提供的第一扫描信号的控制下，将所述第一数据电压端提供的第一数据电压写入所述第一数据接入端；
所述第二数据写入电路分别与第二扫描端、第二数据电压端和第二数据接入端电连接，用于在所述第二扫描端提供的第二扫描信号的控制下，将所述第二数据电压端提供的第二数据电压写入所述第二数据接入端；
所述第一控制子电路分别与所述第一数据接入端、所述第二数据接入端和N个开关控制端电连接，用于根据所述第一数据接入端的电位和所述第二数据接入端的电位，控制向所述N个开关控制端分别提供相应的开关控制信号。
可选的，所述第一控制子电路包括第一锁存器、第二锁存器、第三锁存器、第四锁存器、第一控制开关和第二控制开关；N等于4；
所述第一锁存器的输入端与所述第一数据接入端电连接，所述第一锁存器的输出端与所述第一控制开关的控制端电连接，所述第一锁存器用于锁存所述第一数据接入端接入的电压信号，并输出第一输出电压，所述第一输出电压与所述第一数据接入端接入的电压信号反相；
所述第二锁存器的输入端与所述第二数据接入端电连接，所述第二锁存器的输出端与所述第二控制开关的控制端电连接，所述第二锁存器用于锁存所述第二数据接入端接入的电压信号，并输出第二输出电压，所述第二输出电压与所述第二数据接入端接入的电压信号反相；
所述第三锁存器的输入端与所述第一控制开关的第一端电连接，所述第 三锁存器的输出端与第一开关控制端电连接，所述第三锁存器用于锁存其输入端接入的电压信号，并输出第三输出电压，所述第三输出电压与所述第三锁存器的输入端接入的电压信号反相；
所述第四锁存器的输入端与所述第二控制开关的第一端电连接，所述第四锁存器的输出端与第三开关控制端电连接，所述第四锁存器用于锁存其输入端接入的电压信号，并输出第四输出电压，所述第四输出电压与所述第四锁存器的输入端接入的电压信号反相；
所述第一控制开关的控制端与所述第一锁存器的输出端电连接，所述第一控制开关的第二端与所述第二锁存器的输出端的电连接，所述第一控制开关用于在其控制端的电位的控制下，控制所述第一控制开关的第一端与所述第一控制开关的第二端之间连通或断开；
所述第二控制开关的控制端与所述第一锁存器的输入端电连接，所述第二控制开关的第二端与所述第二锁存器的输入端的电连接，所述第二控制开关用于在其控制端的电位的控制下，控制所述第二控制开关的第一端与所述第二控制开关的第二端之间连通或断开；
第一开关控制端与所述第三锁存器的输出端电连接，第二开关控制端与所述第三锁存器的输入端电连接；
第三开关控制端与所述第四锁存器的输出端电连接，第四开关控制端与所述第四锁存器的输入端电连接。
可选的，所述第一锁存器包括第一反相器和第二反相器；
所述第一反相器的输入端与所述第一锁存器的输入端电连接，所述第一反相器的输出端与所述第一锁存器的输出端电连接；
所述第二反相器的输入端与所述第一反相器的输出端电连接，所述第二反相器的输出端与所述第一反相器的输入端电连接；
所述第二锁存器包括第三反相器和第四反相器；
所述第三反相器的输入端与所述第二锁存器的输入端电连接，所述第三反相器的输出端与所述第二锁存器的输出端电连接；
所述第四反相器的输入端与所述第三反相器的输出端电连接，所述第四反相器的输出端与所述第三反相器的输入端电连接；
所述第三锁存器包括第五反相器和第六反相器；
所述第五反相器的输入端与所述第三锁存器的输入端电连接，所述第五反相器的输出端与所述第三锁存器的输出端电连接；
所述第六反相器的输入端与所述第五反相器的输出端电连接，所述第六反相器的输出端与所述第五反相器的输入端电连接；
所述第四锁存器包括第七反相器和第八反相器；
所述第七反相器的输入端与所述第四锁存器的输入端电连接，所述第七反相器的输出端与所述第四锁存器的输出端电连接；
所述第八反相器的输入端与所述第七反相器的输出端电连接，所述第八反相器的输出端与所述第七反相器的输入端电连接。
可选的，所述第一控制开关为第一控制晶体管，所述第二控制开关为第二控制晶体管；
所述第一控制晶体管的控制极与所述第一锁存器的输出端电连接，所述第一控制晶体管的第一极与所述第三锁存器的输入端电连接，所述第一控制晶体管的第二极与所述第二锁存器的输出端的电连接；
所述第二控制晶体管的控制极与所述第一锁存器的输入端电连接，所述第二控制晶体管的第一极与所述第四锁存器的输入端电连接，所述第二控制晶体管的第二极与所述第二锁存器的输入端的电连接。
可选的，所述第一数据写入电路包括第一写入晶体管，所述第二数据写入电路包括第二写入晶体管；
所述第一写入晶体管的控制极与所述第一扫描端电连接，所述第一写入晶体管的第一极与所述第一数据电压端电连接，所述第一写入晶体管的第二极与所述第一数据接入端电连接；
所述第二写入晶体管的控制极与所述第二扫描端电连接，所述第二写入晶体管的第一极与所述第二数据电压端电连接，所述第二写入晶体管的第二极与所述第二数据接入端电连接。
可选的，所述第一控制电路包括第一数据写入电路、第二数据写入电路、第三数据写入电路、第四数据写入电路和第二控制子电路；
所述第一数据写入电路分别与第一扫描端、第一数据电压端和第一数据 接入端电连接，用于在所述第一扫描端提供的第一扫描信号的控制下，将所述第一数据电压端提供的第一数据电压写入所述第一数据接入端；
所述第二数据写入电路分别与第二扫描端、第二数据电压端和第二数据接入端电连接，用于在所述第二扫描端提供的第二扫描信号的控制下，将所述第二数据电压端提供的第二数据电压写入所述第二数据接入端；
所述第三数据写入电路分别与第三扫描端、第三数据电压端和第三数据接入端电连接，用于在所述第三扫描端提供的第三扫描信号的控制下，将所述第三数据电压端提供的第三数据电压写入所述第三数据接入端；
所述第四数据写入电路分别与第四扫描端、第四数据电压端和第四数据接入端电连接，用于在所述第四扫描端提供的第四扫描信号的控制下，将所述第四数据电压端提供的第四数据电压写入所述第四数据接入端；
所述第二控制子电路分别与所述第一数据接入端、所述第二数据接入端、所述第三数据接入端、所述第四数据接入端和N个开关控制端电连接，用于根据所述第一数据接入端的电位、所述第二数据接入端的电位、所述第三数据接入端的电位和所述第四数据接入端的电位，控制向所述N个开关控制端分别提供相应的开关控制信号。
可选的，所述第二控制子电路包括第一锁存器、第二锁存器、第三锁存器、第四锁存器、第五锁存器、第六锁存器、第七锁存器、第八锁存器、第九锁存器、第十锁存器、第一控制开关、第二控制开关、第三控制开关、第四控制开关、第五控制开关和第六控制开关；N等于8；
所述第一锁存器的输入端与所述第一数据接入端电连接，所述第一锁存器的输出端与所述第一控制开关的控制端电连接，所述第一锁存器用于锁存所述第一数据接入端接入的电压信号，并输出第一输出电压，所述第一输出电压与所述第一数据接入端接入的电压信号反相；
所述第二锁存器的输入端与所述第二数据接入端电连接，所述第二锁存器的输出端与所述第二控制开关的控制端电连接，所述第二锁存器用于锁存所述第二数据接入端接入的电压信号，并输出第二输出电压，所述第二输出电压与所述第二数据接入端接入的电压信号反相；
所述第三锁存器的输入端与所述第一控制开关的第一端电连接，所述第 三锁存器的输出端与所述第三控制开关的控制端电连接，所述第三锁存器用于锁存其输入端接入的电压信号，并输出第三输出电压，所述第三输出电压与所述第三锁存器的输入端接入的电压信号反相；
所述第四锁存器的输入端与所述第二控制开关的第一端电连接，所述第四锁存器的输出端与第第五控制开关的控制端电连接，所述第四锁存器用于锁存其输入端接入的电压信号，并输出第四输出电压，所述第四输出电压与所述第四锁存器的输入端接入的电压信号反相；
所述第五锁存器的输入端与所述第三控制开关的第一端电连接，所述第五锁存器的输出端与第二开关控制端电连接，所述第五锁存器用于锁存其输入端接入的电压信号，并输出第五输出电压，所述第五输出电压与所述第五锁存器的输入端接入的电压信号反相；
所述第六锁存器的输入端与所述第三数据接入端电连接，所述第六锁存器的输出端与所述第三控制开关的第二端电连接，所述第六锁存器用于锁存其输入端接入的电压信号，并输出第六输出电压，所述第六输出电压与所述第六锁存器的输入端接入的电压信号反相；
所述第七锁存器的输入端与所述第四控制开关的第一端电连接，所述第七锁存器的输出端与第四开关控制端电连接，所述第七锁存器用于锁存其输入端接入的电压信号，并输出第七输出电压，所述第七输出电压与所述第七锁存器的输入端接入的电压信号反相；
所述第八锁存器的输入端与所述第五控制开关的第一端电连接，所述第八锁存器的输出端与第六开关控制端电连接，所述第八锁存器用于锁存其输入端接入的电压信号，并输出第八输出电压，所述第八输出电压与所述第八锁存器的输入端接入的电压信号反相；
所述第九锁存器的输入端与所述第四数据接入端电连接，所述第九锁存器的输出端与所述第五控制开关的第二端电连接，所述第九锁存器用于锁存其输入端接入的电压信号，并输出第九输出电压，所述第九输出电压与所述第九锁存器的输入端接入的电压信号反相；
所述第十锁存器的输入端与所述第六控制开关的第一端电连接，所述第十锁存器的输出端与第八开关控制端电连接，所述第十锁存器用于锁存其输 入端接入的电压信号，并输出第十输出电压，所述第十输出电压与所述第十锁存器的输入端接入的电压信号反相；
所述第一控制开关的控制端与所述第一锁存器的输出端电连接，所述第一控制开关的第二端与所述第二锁存器的输出端的电连接，所述第一控制开关用于在其控制端的电位的控制下，控制所述第一控制开关的第一端与所述第一控制开关的第二端之间连通或断开；
所述第二控制开关的控制端与所述第一锁存器的输入端电连接，所述第二控制开关的第二端与所述第二锁存器的输入端的电连接，所述第二控制开关用于在其控制端的电位的控制下，控制所述第二控制开关的第一端与所述第二控制开关的第二端之间连通或断开；
所述第三控制开关的控制端与所述第三锁存器的输出端电连接，所述第三控制开关用于在其控制端的电位的控制下，控制所述第五锁存器的输入端与所述第六锁存器的输出端之间连通或断开；
所述第四控制开关的控制端与所述第三锁存器的输入端电连接，所述第四控制开关用于在其控制端的电位的控制下，控制所述第七锁存器的输入端与所述第六锁存器的输入端之间连通或断开；
所述第五控制开关的控制端与所述第四锁存器的输出端电连接，所述第五控制开关用于在其控制端的电位的控制下，控制所述第八锁存器的输入端与所述第九锁存器的输出端电连接；
所述第六控制开关的控制端与所述第四锁存器的输入端电连接，所述第六控制开关用于在其控制端的电位的控制下，控制所述第十锁存器的输入端与所述第九锁存器的输入端之间连通；
第一开关控制端与第五锁存器的输入端电连接，第七开关控制端与第十锁存器的输入端电连接。
可选的，所述第一锁存器包括第一反相器和第二反相器；
所述第一反相器的输入端与所述第一锁存器的输入端电连接，所述第一反相器的输出端与所述第一锁存器的输出端电连接；
所述第二反相器的输入端与所述第一反相器的输出端电连接，所述第二反相器的输出端与所述第一反相器的输入端电连接；
所述第二锁存器包括第三反相器和第四反相器；
所述第三反相器的输入端与所述第二锁存器的输入端电连接，所述第三反相器的输出端与所述第二锁存器的输出端电连接；
所述第四反相器的输入端与所述第三反相器的输出端电连接，所述第四反相器的输出端与所述第三反相器的输入端电连接；
所述第三锁存器包括第五反相器和第六反相器；
所述第五反相器的输入端与所述第三锁存器的输入端电连接，所述第五反相器的输出端与所述第三锁存器的输出端电连接；
所述第六反相器的输入端与所述第五反相器的输出端电连接，所述第六反相器的输出端与所述第五反相器的输入端电连接；
所述第四锁存器包括第七反相器和第八反相器；
所述第七反相器的输入端与所述第四锁存器的输入端电连接，所述第七反相器的输出端与所述第四锁存器的输出端电连接；
所述第八反相器的输入端与所述第七反相器的输出端电连接，所述第八反相器的输出端与所述第七反相器的输入端电连接；
所述第五锁存器包括第九反相器和第十反相器；
所述第九反相器的输入端与所述第五锁存器的输入端电连接，所述第九反相器的输出端与所述第五锁存器的输出端电连接；
所述第十反相器的输入端与所述第九反相器的输出端电连接，所述第十反相器的输出端与所述第九反相器的输入端电连接；
所述第六锁存器包括第十一反相器和第十二反相器；
所述第十一反相器的输入端与所述第六锁存器的输入端电连接，所述第十一反相器的输出端与所述第六锁存器的输出端电连接；
所述第十二反相器的输入端与所述第十一反相器的输出端电连接，所述第十二反相器的输出端与所述第十一反相器的输入端电连接；
所述第七锁存器包括第十三反相器和第十四反相器；
所述第十三反相器的输入端与所述第七锁存器的输入端电连接，所述第十三反相器的输出端与所述第七锁存器的输出端电连接；
所述第十四反相器的输入端与所述第十三反相器的输出端电连接，所述 第十四反相器的输出端与所述第十三反相器的输入端电连接；
所述第八锁存器包括第十五反相器和第十六反相器；
所述第十五反相器的输入端与所述第八锁存器的输入端电连接，所述第十五反相器的输出端与所述第八锁存器的输出端电连接；
所述第十六反相器的输入端与所述第十五反相器的输出端电连接，所述第十六反相器的输出端与所述第十五反相器的输入端电连接；
所述第九锁存器包括第十七反相器和第十八反相器；
所述第十七反相器的输入端与所述第九锁存器的输入端电连接，所述第十七反相器的输出端与所述第九锁存器的输出端电连接；
所述第十八反相器的输入端与所述第十七反相器的输出端电连接，所述第十八反相器的输出端与所述第十七反相器的输入端电连接；
所述第十锁存器包括第十九反相器和第二十反相器；
所述第十九反相器的输入端与所述第十锁存器的输入端电连接，所述第十九反相器的输出端与所述第十锁存器的输出端电连接；
所述第二十反相器的输入端与所述第十九反相器的输出端电连接，所述第二十反相器的输出端与所述第十九反相器的输入端电连接。
可选的，所述第一控制开关为第一控制晶体管，所述第二控制开关为第二控制晶体管；所述第三控制开关为第三控制晶体管，所述第四控制开关为第四控制晶体管；第五控制开关为第五控制晶体管，所述第六控制开关为第六控制晶体管；
所述第一控制晶体管的控制极与所述第一锁存器的输出端电连接，所述第一控制晶体管的第一极与所述第三锁存器的输入端电连接，所述第一控制晶体管的第二极与所述第二锁存器的输出端的电连接；
所述第二控制晶体管的控制极与所述第一锁存器的输入端电连接，所述第二控制晶体管的第一极与所述第四锁存器的输入端电连接，所述第二控制晶体管的第二极与所述第二锁存器的输入端的电连接；
所述第三控制晶体管的控制极与所述第三锁存器的输出端电连接，所述第三控制晶体管的第一极与所述第五锁存器的输入端电连接，所述第三控制晶体管的第二极与所述第六锁存器的输出端电连接；
所述第四控制晶体管的控制极与所述第三锁存器的输入端电连接，所述第四控制晶体管的第一极与第七锁存器的输入端电连接，所述第四控制晶体管的第二极与所述第六锁存器的输入端电连接；
所述第五控制晶体管的控制极与所述第四锁存器的输出端电连接，所述第五控制晶体管的第一极与所述第八锁存器的输入端电连接，所述第五控制晶体管的第二极与所述第九锁存器的输出端电连接；
所述第六控制晶体管的控制极与所述第四锁存器的输入端电连接，所述第六控制晶体管的第一极与所述第十锁存器的输入端电连接，所述第六控制晶体管的第二极与所述第九锁存器的输入端电连接。
可选的，所述第一数据写入电路包括第一写入晶体管，所述第二数据写入电路包括第二写入晶体管，所述第三数据写入电路包括第三写入晶体管，所述第四数据写入电路包括第四写入晶体管；
所述第一写入晶体管的控制极与所述第一扫描端电连接，所述第一写入晶体管的第一极与所述第一数据电压端电连接，所述第一写入晶体管的第二极与所述第一数据接入端电连接；
所述第二写入晶体管的控制极与所述第二扫描端电连接，所述第二写入晶体管的第一极与所述第二数据电压端电连接，所述第二写入晶体管的第二极与所述第二数据接入端电连接；
所述第三写入晶体管的控制极与所述第三扫描端电连接，所述第三写入晶体管的第一极与所述第三数据电压端电连接，所述第三写入晶体管的第二极与所述第三数据接入端电连接；
所述第四写入晶体管的控制极与所述第四扫描端电连接，所述第四写入晶体管的第一极与所述第四数据电压端电连接，所述第四写入晶体管的第二极与所述第四数据接入端电连接。
可选的，所述发光电路包括发光元件；
所述发光控制电路与所述发光元件的第一极电连接，用于在所述发光控制信号的控制下，控制所述控制电压输入端与所述发光元件的第一极之间连通；
所述发光元件的第二极与第一电压端电连接。
可选的，所述发光电路包括幅度控制子电路、驱动子电路、第一通断控制子电路和发光元件；所述驱动子电路的第一端与第二电压端电连接；
所述幅度控制子电路用于根据显示数据电压，控制所述驱动子电路生成的驱动电流；
所述发光控制电路用于在所述发光控制信号的控制下，控制所述控制电压输入端与所述第一通断控制子电路的控制端之间连通；
所述第一通断控制子电路的控制端与所述发光控制电路电连接，所述第一通断控制子电路的第一端与所述驱动子电路的第二端电连接，所述第一通断控制子电路的第二端与所述发光元件电连接；所述第一通断控制子电路用于在其控制端的电位的控制下，控制所述驱动子电路与所述发光元件之间连通。
可选的，所述幅度控制子电路包括数据写入子电路、储能子电路和复位子电路；
所述数据写入子电路分别与第一扫描线、数据线和所述驱动子电路的控制端电连接，用于在所述第一扫描线提供的第一扫描信号的控制下，将所述数据线提供的数据电压写入所述驱动子电路的控制端；
所述复位子电路分别与第一扫描线、复位电压端和所述驱动子电路的第二端电连接，用于在所述第一扫描信号的控制下，控制将所述复位电压端提供的复位电压写入所述驱动子电路的第二端；
所述储能子电路分别与所述驱动子电路的控制端和所述驱动子电路的第二端电连接，用于储能电能；
所述驱动子电路用于在其控制端的电位的控制下，生成驱动电流。
可选的，所述幅度控制子电路包括数据写入子电路和储能子电路；
所述数据写入子电路分别与扫描线、数据线和所述驱动子电路的控制端电连接，所述数据写入子电路用于在所述扫描线提供的扫描信号的控制下，将所述数据线提供的数据的电压写入所述驱动子电路的控制端；
所述储能子电路分别与所述驱动子电路的控制端和第一公共电极端电连接，用于储存电能；
所述驱动子电路用于在其控制端的电位的控制下，生成驱动电流。
可选的，所述扫描线包括第二扫描线和第三扫描线；
所述数据写入子电路包括第一数据写入晶体管和第二数据写入晶体管；
所述第一数据写入晶体管的控制极与所述第二扫描线电连接，所述第一数据写入晶体管的第一极与所述数据线电连接，所述第一数据写入晶体管的第二极与所述驱动子电路的控制端电连接；
所述第二数据写入晶体管的控制极与所述第三扫描线电连接，所述第二数据写入晶体管的第一极与所述数据线电连接，所述第二数据写入晶体管的第二极与所述驱动子电路的控制端电连接；
所述第一数据写入晶体管为n型晶体管，所述第二数据写入晶体管为p型晶体管。
可选的，第n开关控制子电路包括第n开关控制晶体管；
第n开关控制晶体管的控制极与第n开关控制端电连接，所述第n开关控制晶体管的第一极与第n发光控制电压端电连接，所述第n开关控制晶体管的第二极与所述控制电压输入端电连接。
可选的，所述发光控制电路包括发光控制晶体管；
所述发光控制晶体管的控制极与所述发光控制端电连接，所述发光控制晶体管的第一极与所述控制电压输入端电连接，所述发光控制晶体管的第二极与所述发光电路电连接。
可选的，所述发光电路包括的发光元件为微型发光二极管或次毫米发光二极管；所述发光元件的第一极为阳极，所述发光元件的第二极为阴极。
在第二个方面中，本公开实施例还提供一种显示装置，包括显示面板；
所述显示面板的显示区域具有多个亚像素，每个亚像素内设置有上述的像素电路。
可选的，所述显示面板包括硅基板；
所述像素电路设置于所述硅基板上。
附图说明
图1是本公开至少一实施例所述的像素电路的结构图；
图2是本公开至少一实施例所述的像素电路的结构图；
图3是本公开至少一实施例所述的像素电路的结构图；
图4是本公开至少一实施例所述的像素电路的结构图；
图5是本公开至少一实施例所述的像素电路的电路图；
图6是图5所示的像素电路的至少一实施例的工作时序图；
图7是本公开至少一实施例所述的像素电路的结构图；
图8是本公开至少一实施例所述的像素电路的结构图；
图9是本公开至少一实施例所述的像素电路的电路图；
图10是图9所示的像素电路的至少一实施例的工作时序图；
图11是发光电路的至少一实施例的结构图；
图12是所述发光电路的至少一实施例的结构图；
图13是所述发光电路的至少一实施例的结构图；
图14是所述发光电路的至少一实施例的结构图；
图15是本公开至少一实施例所述的像素电路的电路图；
图16是本公开至少一实施例所述的像素电路的电路图；
图17是本公开至少一实施例所述的像素电路的电路图；
图18是本公开至少一实施例所述的像素电路的电路图；
图19是本公开至少一实施例所述的像素电路的电路图；
图20是本公开至少一实施例所述的像素电路的电路图；
图21是本公开至少一实施例所述的像素电路的电路图；
图22是本公开至少一实施例所述的像素电路的电路图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为三极管时，所述控制极可以为基极，所述第一极可以为集电极，所述第二极可以发射极；或者，所述控制极可以为基极，所述第一极可以为发射极，所述第二极可以集电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述控制极可以为栅极，所述第一极可以为漏极，所述第二极可以为源极；或者，所述控制极可以为栅极，所述第一极可以为源极，所述第二极可以为漏极。
本公开实施例所述的像素电路包括发光电路、发光控制电路、第一控制电路和开关控制电路；
所述发光控制电路分别与发光控制端、控制电压输入端和所述发光电路电连接，用于在所述发光控制端提供的发光控制信号的控制下，控制所述控制电压输入端与所述发光电路之间连通；
所述发光电路用于根据所述控制电压端输入端提供的控制电压发光；
所述第一控制电路分别与至少两个数据电压端、至少两个扫描端和N个开关控制端电连接，用于在所述扫描端提供的扫描信号的控制下，根据所述数据电压端提供的数据电压，控制提供至所述开关控制端的开关控制信号；N为大于1的整数；
所述开关控制电路包括N个开关控制端、N个发光控制电压端和N个开关控制子电路；n为小于等于N的正整数；
第n开关控制子电路分别与第n开关控制端、第n发光控制电压端和所述控制电压输入端电连接，用于在所述第n开关控制端提供的第n开关控制信号的控制下，控制所述第n发光控制电压端与所述控制电压输入端之间连通。
本公开实施例所述的像素电路在工作时，第一控制电路在扫描信号的控制下，根据数据电压，控制开关控制信号，各开关控制子电路分别在相应的开关控制信号的控制下，控制相应的发光控制电压端与所述控制电压输入端之间连通，以控制所述发光电路的发光亮度。
在具体实施时，所述发光电路可以包括发光元件，所述发光控制电路与所述发光元件的第一极电连接，用于在所述发光控制信号的控制下，控制所述控制电压输入端与所述发光元件的第一极之间连通，所述发光元件的第二 极与第一电压端电连接；此时本公开实施例所述的像素电路能够在省去存储电容的前提下，实现对发光亮度的控制，可以减少多张mask(掩膜)，从而降低了成本，并且，本公开实施例所述的像素电路在工作时，不存在电容充放电功能，大大降低了功耗。
可选的，所述发光电路包括的发光元件可以为微型发光二极管或次毫米发光二极管，所述发光元件的第一极为阳极，所述发光元件的第二极为阴极，但不以此为限。
当所述发光电路仅包括发光元件时，本公开至少一实施例提供一种MIP(Memory In Pixel，像素内存储器)Micro LED(微型发光二极管)像素电路，可以适用于手表等灰阶数较少的应用场景。
在本公开至少一实施例中，所述发光电路可以包括幅度控制子电路、驱动子电路、第一通断控制子电路和发光元件；
所述幅度控制子电路用于根据显示数据电压，控制所述驱动子电路生成的驱动电流；
所述发光控制电路用于在所述发光控制信号的控制下，控制所述控制电压输入端与所述第一通断控制子电路的控制端之间连通；
所述第一通断控制子电路的控制端与所述发光控制电路电连接，所述第一通断控制子电路的第一端与所述驱动子电路的第二端电连接，所述第一通断控制子电路的第二端与所述发光元件电连接；所述第一通断控制子电路用于在其控制端的电位的控制下，控制所述驱动子电路与所述发光元件之间连通，从而可以通过控制第一通断控制子电路的控制端接入的控制电压(所述控制电压可以为方波电压信号)，通过控制发光元件的发光时长，以控制发光元件的发光亮度，从而可以提升低灰阶显示的均一性。
在本公开至少一实施例中，当所述发光电路包括幅度控制子电路、驱动子电路、第一通断控制子电路和发光元件时，可以通过发光控制电路、第一控制电路和开关控制电路控制所述第一通断控制子电路的通断时间，以控制发光元件的发光时长，而驱动电路根据显示数据电压生成驱动电流，以能够实现多灰阶显示，可以应用于各种多灰阶显示场景。
在本公开至少一实施例中，第n开关控制子电路包括第n开关控制晶体 管；
第n开关控制晶体管的控制极与第n开关控制端电连接，所述第n开关控制晶体管的第一极与第n发光控制电压端电连接，所述第n开关控制晶体管的第二极与所述控制电压输入端电连接。
可选的，所述发光控制电路包括发光控制晶体管；
所述发光控制晶体管的控制极与所述发光控制端电连接，所述发光控制晶体管的第一极与所述控制电压输入端电连接，所述发光控制晶体管的第二极与所述发光元件的第一极电连接。
在本公开至少一实施例中，以N等于4或8为例说明。
在本公开至少一实施例中，N可以等于2 a，a为正整数，但不以此为限。
在优选情况下，a可以为大于1的正整数，以提升可以提供至所述控制电压输入端I1的控制电压的个数，提升显示灰阶数。
可选的，所述第一电压端可以为低电压端，但不以此为限。
如图1所示，本公开至少一实施例所述的像素电路包括发光元件10、发光控制电路11、第一控制电路12和开关控制电路；
所述发光控制电路11分别与发光控制端EM、控制电压输入端I1和所述发光元件10的第一极电连接，用于在所述发光控制端EM提供的发光控制信号的控制下，控制所述控制电压输入端I1与所述发光元件10的第一极之间连通；所述发光元件10的第二极与第一电压端V1电连接；
所述第一控制电路12分别与第一数据电压端D1、第二数据电压端D2、第一扫描端G1、第二扫描端G2、第一开关控制端A、第二开关控制端B、第三开关控制端C和第四开关控制端D电连接，用于在所述第一扫描端G1提供的第一扫描信号和所述第二扫描端G2提供的第二扫描信号的控制下，根据所述第一数据电压端D1提供的第一数据电压Vdata1和所述第二数据电压端D2提供的第二数据电压Vdata2，控制提供至所述第一开关控制端A的第一开关控制信号、提供至所述第二开关控制端B的第二开关控制信号、提供至所述第三开关控制端C的第三开关控制信号和提供至所述第四开关控制端D的第四开关控制信号；
所述开关控制电路包括第一开关控制端A、第二开关控制端B、第三开 关控制端C、第四开关控制端D、第一发光控制电压端VC1、第二发光控制电压端VC2、第三发光控制电压端VC3、第四发光控制电压端VC4、第一开关控制子电路131、第二开关控制子电路132、第三开关控制子电路133和第四开关控制子电路134；
所述第一开关控制子电路131分别与所述第一开关控制端A、第一发光控制电压端VC1和所述控制电压输入端I1电连接，用于在所述第一开关控制端A提供的第一开关控制信号的控制下，控制所述第一发光控制电压端VC1与所述控制电压输入端I1之间连通；
所述第二开关控制子电路132分别与所述第二开关控制端B、第二发光控制电压端VC2和所述控制电压输入端I1电连接，用于在所述第二开关控制端B提供的第二开关控制信号的控制下，控制所述第二发光控制电压端VC2与所述控制电压输入端I1之间连通；
所述第三开关控制子电路133分别与所述第三开关控制端C、第三发光控制电压端VC3和所述控制电压输入端I1电连接，用于在所述第三开关控制端C提供的第三开关控制信号的控制下，控制所述第三发光控制电压端VC3与所述控制电压输入端I1之间连通；
所述第四开关控制子电路134分别与所述第四开关控制端D、第四发光控制电压端VC4和所述控制电压输入端I1电连接，用于在所述第四开关控制端D提供的第四开关控制信号的控制下，控制所述第四发光控制电压端VC4与所述控制电压输入端I1之间连通。
本公开图1所示的像素电路的至少一实施例在工作时，所述第一控制电路12控制提供至第一开关控制信号、第二开关控制信号、第三开关控制信号和第四开关控制信号；所述第一开关控制子电路131在所述第一开关控制信号的控制下，控制所述第一发光控制电压端VC1提供第一发光控制电压至所述控制电压输入端I1；所述第二开关控制子电路132在第二开关控制信号的控制下，控制所述第二发光控制电压端VC2提供第二发光控制电压至所述控制电压输入端I1；所述第三开关控制子电路133在所述第三开关控制信号的控制下，控制所述第三发光控制电压端VC3提供第三发光控制电压至所述控制电压输入端I1；所述第四开关控制子电路134在所述第四开关控制信号的 控制下，控制所述第四发光控制电压端VC4提供第四发光控制电压至所述控制电压输入端I1；所述发光控制电路11在所述发光控制信号的控制下，控制所述控制电压输入端I1与所述发光元件10的第一极之间连通，以控制发光元件10发光，并能够根据所述控制电压端提供的发光控制电压，控制发光元件10的发光亮度。
如图2所示，本公开至少一实施例所述的像素电路包括发光元件10、发光控制电路11、第一控制电路12和开关控制电路；
所述发光控制电路11分别与发光控制端EM、控制电压输入端I1和所述发光元件10的第一极电连接，用于在所述发光控制端EM提供的发光控制信号的控制下，控制所述控制电压输入端I1与所述发光元件10的第一极之间连通；所述发光元件10的第二极与第一电压端V1电连接；
所述第一控制电路12分别与第一数据电压端D1、第二数据电压端D2、第三数据电压端D3、第四数据电压端D4、第一扫描端G1、第二扫描端G2、第三扫描端G3、第四扫描端G4、第一开关控制端A、第二开关控制端B、第三开关控制端C、第四开关控制端D、第五开关控制端E、第六开关控制端F、第七开关控制端G和第八开关控制端H电连接，用于在所述第一扫描端G1提供的第一扫描信号、所述第二扫描端G2提供的第二扫描信号、所述第三扫描端G3提供的第三扫描信号和所述第四扫描端G4提供的第四扫描信号的控制下，根据所述第一数据电压端D1提供的第一数据电压Vdata1、所述第二数据电压端D2提供的第二数据电压Vdata2、所述第三数据电压端D3提供的第三数据电压Vdata3和所述第四数据电压端D4提供的第四数据电压Vdata4，控制提供至所述第一开关控制端A的第一开关控制信号、提供至所述第二开关控制端B的第二开关控制信号、提供至所述第三开关控制端C的第三开关控制信号、提供至所述第四开关控制端D的第四开关控制信号、提供至所述第五开关控制端E的第五开关控制信号、提供至所述第六开关控制端F的第六开关控制信号、提供至所述第七开关控制端G的第七开关控制信号和提供至所述第八开关控制端H的第八开关控制信号；
所述开关控制电路包括第一开关控制端A、第二开关控制端B、第三开关控制端C、第四开关控制端D、第五开关控制端E、第六开关控制端F、第 七开关控制端G、第八开关控制端H、第一发光控制电压端VC1、第二发光控制电压端VC2、第三发光控制电压端VC3、第四发光控制电压端VC4、第五发光控制电压端VC5、第六发光控制电压端VC6、第七发光控制电压端VC7、第八发光控制电压端VC8、第一开关控制子电路131、第二开关控制子电路132、第三开关控制子电路133、第四开关控制子电路134、第五开关控制子电路135、第六开关控制子电路136、第七开关控制子电路137和第八开关控制子电路138；
所述第一开关控制子电路131分别与所述第一开关控制端A、第一发光控制电压端VC1和所述控制电压输入端I1电连接，用于在所述第一开关控制端A提供的第一开关控制信号的控制下，控制所述第一发光控制电压端VC1与所述控制电压输入端I1之间连通；
所述第二开关控制子电路132分别与所述第二开关控制端B、第二发光控制电压端VC2和所述控制电压输入端I1电连接，用于在所述第二开关控制端B提供的第二开关控制信号的控制下，控制所述第二发光控制电压端VC2与所述控制电压输入端I1之间连通；
所述第三开关控制子电路133分别与所述第三开关控制端C、第三发光控制电压端VC3和所述控制电压输入端I1电连接，用于在所述第三开关控制端C提供的第三开关控制信号的控制下，控制所述第三发光控制电压端VC3与所述控制电压输入端I1之间连通；
所述第四开关控制子电路134分别与所述第四开关控制端D、第四发光控制电压端VC4和所述控制电压输入端I1电连接，用于在所述第四开关控制端D提供的第四开关控制信号的控制下，控制所述第四发光控制电压端VC4与所述控制电压输入端I1之间连通；
所述第五开关控制子电路135分别与所述第五开关控制端E、第二发光控制电压端VC2和所述控制电压输入端I1电连接，用于在所述第五开关控制端E提供的第五开关控制信号的控制下，控制所述第五发光控制电压端VC5与所述控制电压输入端I1之间连通；
所述第六开关控制子电路136分别与所述第六开关控制端F、第六发光控制电压端VC6和所述控制电压输入端I1电连接，用于在所述第六开关控 制端F提供的第六开关控制信号的控制下，控制所述第六发光控制电压端VC6与所述控制电压输入端I1之间连通；
所述第七开关控制子电路137分别与所述第七开关控制端G、第七发光控制电压端VC7和所述控制电压输入端I1电连接，用于在所述第七开关控制端G提供的第七开关控制信号的控制下，控制所述第七发光控制电压端VC7与所述控制电压输入端I1之间连通；
所述第八开关控制子电路138分别与所述第八开关控制端H、第八发光控制电压端VC8和所述控制电压输入端I1电连接，用于在所述第八开关控制端H提供的第八开关控制信号的控制下，控制所述第八发光控制电压端VC8与所述控制电压输入端I1之间连通。
本公开图2所示的像素电路的至少一实施例在工作时，所述第一控制电路12控制提供至第一开关控制信号、第二开关控制信号、第三开关控制信号、第四开关控制信号、第五开关控制信号、第六开关控制信号、第七开关控制信号和第八开关控制信号；所述第一开关控制子电路131在所述第一开关控制信号的控制下，控制所述第一发光控制电压端VC1提供第一发光控制电压至所述控制电压输入端I1；所述第二开关控制子电路132在第二开关控制信号的控制下，控制所述第二发光控制电压端VC2提供第二发光控制电压至所述控制电压输入端I1；所述第三开关控制子电路133在所述第三开关控制信号的控制下，控制所述第三发光控制电压端VC3提供第三发光控制电压至所述控制电压输入端I1；所述第四开关控制子电路134在所述第四开关控制信号的控制下，控制所述第四发光控制电压端VC4提供第四发光控制电压至所述控制电压输入端I1；所述第五开关控制子电路135在所述第五开关控制信号的控制下，控制所述第五发光控制电压端VC5提供第五发光控制电压至所述控制电压输入端I1；所述第六开关控制子电路136在第六开关控制信号的控制下，控制所述第六发光控制电压端VC6提供第六发光控制电压至所述控制电压输入端I1；所述第七开关控制子电路137在所述第七开关控制信号的控制下，控制所述第七发光控制电压端VC7提供第七发光控制电压至所述控制电压输入端I1；所述第八开关控制子电路138在所述八开关控制信号的控制下，控制所述第八发光控制电压端VC8提供第八发光控制电压至所述控制 电压输入端I1；所述发光控制电路11在所述发光控制信号的控制下，控制所述控制电压输入端I1与所述发光元件10的第一极之间连通，以控制发光元件10发光，并能够根据所述控制电压端提供的发光控制电压，控制发光元件10的发光亮度。
本公开图2所示的像素电路的至少一实施例在工作时，所述第一控制电路12控制提供至第一开关控制信号、第二开关控制信号、第三开关控制信号、第四开关控制信号、第五开关控制信号、第六开关控制信号、第七开关控制信号和第八开关控制信号；所述第一开关控制子电路131在所述第一开关控制信号的控制下，控制所述第一发光控制电压端VC1提供第一发光控制电压至所述控制电压输入端I1；所述第二开关控制子电路132在第二开关控制信号的控制下，控制所述第二发光控制电压端VC2提供第二发光控制电压至所述控制电压输入端I1；所述第三开关控制子电路133在所述第三开关控制信号的控制下，控制所述第三发光控制电压端VC3提供第三发光控制电压至所述控制电压输入端I1；所述第四开关控制子电路134在所述第四开关控制信号的控制下，控制所述第四发光控制电压端VC4提供第四发光控制电压至所述控制电压输入端I1；所述第五开关控制子电路135在所述第五开关控制信号的控制下，控制所述第五发光控制电压端VC5提供第五发光控制电压至所述控制电压输入端I1；所述第六开关控制子电路136在第六开关控制信号的控制下，控制所述第六发光控制电压端VC6提供第六发光控制电压至所述控制电压输入端I1；所述第七开关控制子电路137在所述第七开关控制信号的控制下，控制所述第七发光控制电压端VC7提供第七发光控制电压至所述控制电压输入端I1；所述第八开关控制子电路138在所述第八开关控制信号的控制下，控制所述第八发光控制电压端VC8提供第八发光控制电压至所述控制电压输入端I1；所述发光控制电路11在所述发光控制信号的控制下，控制所述控制电压输入端I1与所述发光元件10的第一极之间连通，以控制发光元件10发光，并能够根据所述控制电压端提供的发光控制电压，控制发光元件10的发光亮度。
可选的，所述发光控制电压端提供的发光控制电压为直流电压，所述N个发光控制电压端提供的发光控制电压互不相同。
在具体实施时，所述发光控制电压可以为直流电压，通过调节所述发光控制电压的电压值，可以控制发光元件的发光亮度。
可选的，所述发光控制电压端提供的发光控制电压为方波电压信号，N个发光控制电压端提供的发光控制电压的占空比互不相同。
在具体实施时，所述发光控制电压可以为方波电压信号，N个发光控制电压的占空比互不相同。当所述发光控制电压为方波电压信号时，由于方波电压信号的低灰阶亮度均一性较好，因此可以通过高电压加发光时长控制以提升显示均一性。
可选的，所述第一控制电路包括第一数据写入电路、第二数据写入电路和第一控制子电路；
所述第一数据写入电路分别与第一扫描端、第一数据电压端和第一数据接入端电连接，用于在所述第一扫描端提供的第一扫描信号的控制下，将所述第一数据电压端提供的第一数据电压写入所述第一数据接入端；
所述第二数据写入电路分别与第二扫描端、第二数据电压端和第二数据接入端电连接，用于在所述第二扫描端提供的第二扫描信号的控制下，将所述第二数据电压端提供的第二数据电压写入所述第二数据接入端；
所述第一控制子电路分别与所述第一数据接入端、所述第二数据接入端和N个开关控制端电连接，用于根据所述第一数据接入端的电位和所述第二数据接入端的电位，控制向所述N个开关控制端分别提供相应的开关控制信号。
在具体实施时，所述第一控制电路可以包括第一数据写入电路、第二数据写入电路和第一控制子电路，第一数据写入电路在第一扫描信号的控制下，将第一数据电压写入第一数据接入端，第二数据写入电路在第二扫描信号的控制下，将第二数据电压写入所述第二数据接入端；第一控制子电路根据所述第一数据接入端的电位和所述第二数据接入端的电位，控制向所述N个开关控制端分别提供相应的开关控制信号。
在本公开至少一实施例中，如图3所示，在图1所示的像素电路的至少一实施例的基础上，所述第一控制电路包括第一数据写入电路31、第二数据写入电路32和第一控制子电路33；
所述第一数据写入电路31分别与第一扫描端G1、第一数据电压端D1和第一数据接入端DI1电连接，用于在所述第一扫描端G1提供的第一扫描信号的控制下，将所述第一数据电压端D1提供的第一数据电压Vdata1写入所述第一数据接入端DI1；
所述第二数据写入电路32分别与第二扫描端G2、第二数据电压端D2和第二数据接入端DI2电连接，用于在所述第二扫描端G2提供的第二扫描信号的控制下，将所述第二数据电压端D2提供的第二数据电压Vdata2写入所述第二数据接入端DI2；
所述第一控制子电路33分别与所述第一数据接入端DI1、所述第二数据接入端DI2、第一开关控制端A、第二开关控制端B、第三开关控制端C和第四开关控制端D电连接，用于根据所述第一数据接入端DI1的电位和所述第二数据接入端DI2的电位，控制向第一开关控制端A提供第一开关控制信号，控制向第二开关控制端B提供第二开关控制信号，控制向第三开关控制端C提供第三开关控制信号，控制向第四开关控制端D提供第四开关控制信号。
可选的，所述第一控制子电路包括第一锁存器、第二锁存器、第三锁存器、第四锁存器、第一控制开关和第二控制开关；N等于4；
所述第一锁存器的输入端与所述第一数据接入端电连接，所述第一锁存器的输出端与所述第一控制开关的控制端电连接，所述第一锁存器用于锁存所述第一数据接入端接入的电压信号，并输出第一输出电压，所述第一输出电压与所述第一数据接入端接入的电压信号反相；
所述第二锁存器的输入端与所述第二数据接入端电连接，所述第二锁存器的输出端与所述第二控制开关的控制端电连接，所述第二锁存器用于锁存所述第二数据接入端接入的电压信号，并输出第二输出电压，所述第二输出电压与所述第二数据接入端接入的电压信号反相；
所述第三锁存器的输入端与所述第一控制开关的第一端电连接，所述第三锁存器的输出端与第一开关控制端电连接，所述第三锁存器用于锁存其输入端接入的电压信号，并输出第三输出电压，所述第三输出电压与所述第三锁存器的输入端接入的电压信号反相；
所述第四锁存器的输入端与所述第二控制开关的第一端电连接，所述第四锁存器的输出端与第三开关控制端电连接，所述第四锁存器用于锁存其输入端接入的电压信号，并输出第四输出电压，所述第四输出电压与所述第四锁存器的输入端接入的电压信号反相；
所述第一控制开关的控制端与所述第一锁存器的输出端电连接，所述第一控制开关的第二端与所述第二锁存器的输出端的电连接，所述第一控制开关用于在其控制端的电位的控制下，控制所述第一控制开关的第一端与所述第一控制开关的第二端之间连通或断开；
所述第二控制开关的控制端与所述第一锁存器的输入端电连接，所述第二控制开关的第二端与所述第二锁存器的输入端的电连接，所述第二控制开关用于在其控制端的电位的控制下，控制所述第二控制开关的第一端与所述第二控制开关的第二端之间连通或断开；
第一开关控制端与所述第三锁存器的输出端电连接，第二开关控制端与所述第三锁存器的输入端电连接；
第三开关控制端与所述第四锁存器的输出端电连接，第四开关控制端与所述第四锁存器的输入端电连接。
在具体实施时，所述第一控制子电路可以包括第一锁存器、第二锁存器、第三锁存器、第四锁存器、第一控制开关和第二控制开关，所述第一锁存器锁存所述第一数据接入端接入的电压信号，并输出第一输出电压，所述第一输出电压与所述第一数据接入端接入的电压信号反相；所述第二锁存器锁存所述第二数据接入端接入的电压信号，并输出第二输出电压，所述第二输出电压与所述第二数据接入端接入的电压信号反相；所述第三锁存器锁存其输入端接入的电压信号，并输出第三输出电压，所述第三输出电压与所述第三锁存器的输入端接入的电压信号反相；所述第四锁存器锁存其输入端接入的电压信号，并输出第四输出电压，所述第四输出电压与所述第四锁存器的输入端接入的电压信号反相；所述第一控制开关在其控制端的电位的控制下，控制所述第一控制开关的第一端与所述第一控制开关的第二端之间连通或断开；所述第二控制开关在其控制端的电位的控制下，控制所述第二控制开关的第一端与所述第二控制开关的第二端之间连通或断开。
如图4所示，在图3所示的像素电路的至少一实施例的基础上，所述第一控制子电路包括第一锁存器S1、第二锁存器S2、第三锁存器S3、第四锁存器S4、第一控制开关K1和第二控制开关K2；
所述第一锁存器S1的输入端与所述第一数据接入端DI1电连接，所述第一锁存器S1的输出端与所述第一控制开关K1的控制端电连接，所述第一锁存器S1用于锁存所述第一数据接入端DI1接入的电压信号，并通过所述第一锁存器S1的输出端输出第一输出电压Vo1，所述第一输出电压Vo1与所述第一数据接入端DI1接入的电压信号反相；
所述第二锁存器S2的输入端与所述第二数据接入端DI2电连接，所述第二锁存器S2的输出端与所述第二控制开关K2的控制端电连接，所述第二锁存器S2用于锁存所述第二数据接入端DI2接入的电压信号，并通过所述第二锁存器S2的输出端输出第二输出电压Vo2，所述第二输出电压Vo2与所述第二数据接入端DI2接入的电压信号反相；
所述第三锁存器S3的输入端与所述第一控制开关K1的第一端电连接，所述第三锁存器S3的输出端与第一开关控制端A电连接，所述第三锁存器S3用于锁存其输入端接入的电压信号，并通过所述第三锁存器S3的输出端输出第三输出电压Vo3，所述第三输出电压Vo3与所述第三锁存器S3的输入端接入的电压信号反相；
所述第四锁存器S4的输入端与所述第二控制开关K2的第一端电连接，所述第四锁存器S4的输出端与第三开关控制端C电连接，所述第四锁存器S4用于锁存其输入端接入的电压信号，并输出第四输出电压Vo4，所述第四输出电压Vo4与所述第四锁存器S4的输入端接入的电压信号反相；
所述第一控制开关K1的控制端与所述第一锁存器S1的输出端电连接，所述第一控制开关K1的第二端与所述第二锁存器S2的输出端电连接，所述第一控制开关K1用于在其控制端的电位的控制下，控制所述第一控制开关K1的第一端与所述第一控制开关K1的第二端之间连通或断开；
所述第二控制开关K2的控制端与所述第一锁存器S1的输入端电连接，所述第二控制开关K2的第二端与所述第二锁存器S2的输入端的电连接，所述第二控制开关K2用于在其控制端的电位的控制下，控制所述第二控制开 关K2的第一端与所述第二控制开关K2的第二端之间连通或断开；
第一开关控制端A与所述第三锁存器S3的输出端电连接，第二开关控制端B与所述第三锁存器S3的输入端电连接；
第三开关控制端C与所述第四锁存器S4的输出端电连接，第四开关控制端D与所述第四锁存器S4的输入端电连接。
在具体实施时，所述第一控制子电路可以包括第一锁存器、第二锁存器、第三锁存器、第四锁存器、第一控制开关和第二控制开关，所述第一锁存器锁存所述第一数据接入端接入的电压信号，并输出第一输出电压，所述第一输出电压与所述第一数据接入端接入的电压信号反相；所述第二锁存器锁存所述第二数据接入端接入的电压信号，并输出第二输出电压，所述第二输出电压与所述第二数据接入端接入的电压信号反相；所述第三锁存器锁存其输入端接入的电压信号，并输出第三输出电压，所述第三输出电压与所述第三锁存器的输入端接入的电压信号反相；所述第四锁存器锁存其输入端接入的电压信号，并输出第四输出电压，所述第四输出电压与所述第四锁存器的输入端接入的电压信号反相；所述第一控制开关在其控制端的电位的控制下，控制所述第一控制开关的第一端与所述第一控制开关的第二端之间连通或断开；所述第二控制开关在其控制端的电位的控制下，控制所述第二控制开关的第一端与所述第二控制开关的第二端之间连通或断开。
在本公开至少一实施例中，所述第一锁存器包括第一反相器和第二反相器；
所述第一反相器的输入端与所述第一锁存器的输入端电连接，所述第一反相器的输出端与所述第一锁存器的输出端电连接；
所述第二反相器的输入端与所述第一反相器的输出端电连接，所述第二反相器的输出端与所述第一反相器的输入端电连接；
所述第二锁存器包括第三反相器和第四反相器；
所述第三反相器的输入端与所述第二锁存器的输入端电连接，所述第三反相器的输出端与所述第二锁存器的输出端电连接；
所述第四反相器的输入端与所述第三反相器的输出端电连接，所述第四反相器的输出端与所述第三反相器的输入端电连接；
所述第三锁存器包括第五反相器和第六反相器；
所述第五反相器的输入端与所述第三锁存器的输入端电连接，所述第五反相器的输出端与所述第三锁存器的输出端电连接；
所述第六反相器的输入端与所述第五反相器的输出端电连接，所述第六反相器的输出端与所述第五反相器的输入端电连接；
所述第四锁存器包括第七反相器和第八反相器；
所述第七反相器的输入端与所述第四锁存器的输入端电连接，所述第七反相器的输出端与所述第四锁存器的输出端电连接；
所述第八反相器的输入端与所述第七反相器的输出端电连接，所述第八反相器的输出端与所述第七反相器的输入端电连接。
可选的，所述第一控制开关为第一控制晶体管，所述第二控制开关为第二控制晶体管；
所述第一控制晶体管的控制极与所述第一锁存器的输出端电连接，所述第一控制晶体管的第一极与所述第三锁存器的输入端电连接，所述第一控制晶体管的第二极与所述第二锁存器的输出端的电连接；
所述第二控制晶体管的控制极与所述第一锁存器的输入端电连接，所述第二控制晶体管的第一极与所述第四锁存器的输入端电连接，所述第二控制晶体管的第二极与所述第二锁存器的输入端的电连接。
可选的，所述第一数据写入电路包括第一写入晶体管，所述第二数据写入电路包括第二写入晶体管；
所述第一写入晶体管的控制极与所述第一扫描端电连接，所述第一写入晶体管的第一极与所述第一数据电压端电连接，所述第一写入晶体管的第二极与所述第一数据接入端电连接；
所述第二写入晶体管的控制极与所述第二扫描端电连接，所述第二写入晶体管的第一极与所述第二数据电压端电连接，所述第二写入晶体管的第二极与所述第二数据接入端电连接。
如图5所示，在图4所示的像素电路的至少一实施例的基础上，发光元件为微型发光二极管M1；
所述第一锁存器S1包括第一反相器F1和第二反相器F2；
所述第一反相器F1的输入端与所述第一锁存器S1的输入端电连接，所述第一反相器F1的输出端与所述第一锁存器S1的输出端电连接；
所述第二反相器F2的输入端与所述第一反相器F1的输出端电连接，所述第二反相器F2的输出端与所述第一反相器F1的输入端电连接；
所述第二锁存器S2包括第三反相器F3和第四反相器F4；
所述第三反相器F3的输入端与所述第二锁存器S2的输入端电连接，所述第三反相器F3的输出端与所述第二锁存器S2的输出端电连接；
所述第四反相器F4的输入端与所述第三反相器F3的输出端电连接，所述第四反相器F4的输出端与所述第三反相器F3的输入端电连接；
所述第三锁存器S3包括第五反相器F5和第六反相器F6；
所述第五反相器F5的输入端与所述第三锁存器S3的输入端电连接，所述第五反相器F5的输出端与所述第三锁存器S3的输出端电连接；
所述第六反相器F6的输入端与所述第五反相器F5的输出端电连接，所述第六反相器F6的输出端与所述第五反相器F5的输入端电连接；
所述第四锁存器S4包括第七反相器F7和第八反相器F8；
所述第七反相器F7的输入端与所述第四锁存器S4的输入端电连接，所述第七反相器F7的输出端与所述第四锁存器S4的输出端电连接；
所述第八反相器F8的输入端与所述第七反相器F7的输出端电连接，所述第八反相器F8的输出端与所述第七反相器F7的输入端电连接；
所述第一控制开关为第一控制晶体管TC1，所述第二控制开关为第二控制晶体管TC2；
所述第一控制晶体管TC1的栅极与所述第一锁存器S1的输出端电连接，所述第一控制晶体管TC1的漏极与所述第三锁存器S3的输入端电连接，所述第一控制晶体管TC1的源极与所述第二锁存器的输出端的电连接；
所述第二控制晶体管TC2的栅极与所述第一锁存器S1的输入端电连接，所述第二控制晶体管TC2的漏极与所述第四锁存器S4的输入端电连接，所述第二控制晶体管TC2的源极与所述第二锁存器S2的输入端的电连接；
所述第一数据写入电路31包括第一写入晶体管TW1，所述第二数据写入电路32包括第二写入晶体管TW2；
所述第一写入晶体管TW1的栅极与所述第一扫描端G1电连接，所述第一写入晶体管TW1的漏极与所述第一数据电压端D1电连接，所述第一写入晶体管TW1的源极与所述第一数据接入端DI1电连接；
所述第二写入晶体管TW2的栅极与所述第二扫描端G2电连接，所述第二写入晶体管TW2的漏极与所述第一数据电压端D1电连接，所述第二写入晶体管TW2的源极与所述第二数据接入端DI2电连接；
第一开关控制子电路131包括第一开关控制晶体管TK1；
第一开关控制晶体管TK1的栅极与第一开关控制端A电连接，所述第一开关控制晶体管TK1的漏极与第一发光控制电压端VC1电连接，所述第一开关控制晶体管TK1的源极与所述控制电压输入端I1电连接；
第二开关控制子电路132包括第二开关控制晶体管TK2；
第二开关控制晶体管TK2的栅极与第二开关控制端B电连接，所述第二开关控制晶体管TK2的漏极与第二发光控制电压端VC2电连接，所述第二开关控制晶体管TK2的源极与所述控制电压输入端I1电连接；
第三开关控制子电路133包括第三开关控制晶体管TK3；
第三开关控制晶体管TK3的栅极与第三开关控制端C电连接，所述第三开关控制晶体管TK3的漏极与第三发光控制电压端VC2电连接，所述第三开关控制晶体管TK3的源极与所述控制电压输入端I1电连接；
第四开关控制子电路134包括第四开关控制晶体管TK4；
第四开关控制晶体管TK4的栅极与第四开关控制端D电连接，所述第四开关控制晶体管TK4的漏极与第四发光控制电压端VC4电连接，所述第四开关控制晶体管TK4的源极与所述控制电压输入端I1电连接；
所述发光控制电路11包括发光控制晶体管TE；
所述发光控制晶体管TE的栅极与所述发光控制端EM电连接，所述发光控制晶体管TE的漏极与所述控制电压输入端I1电连接，所述发光控制晶体管TE的源极与M1的阳极电连接，M1的阴极与低电压端VSS电连接。
在图5所示的至少一实施例中，第一数据电压端D1与第二数据电压端为同一数据电压端。
在图5所示的像素电路的至少一实施例中，所有晶体管都为n型晶体管， 但不以此为限。
如图6所示，本公开图5所示的像素电路的至少一实施例在工作时，显示周期包括先后设置的第一写入阶段tw1、第二写入阶段tw2和发光阶段te；
在第一写入阶段tw1，G1提供高电压信号，D1提供第一数据电压Vdata1，TW1打开，以将Vdata1写入S1的输入端；
在第二写入阶段tw2，G2提供高电压信号，D1提供第二数据电压Vdata2，TW2打开，以将Vdata2写入S2的输入端；
当Vdata1为低电压信号，Vdata2为低电压信号时，S1输出高电压信号，S2输出高电压信号，TC1导通，TC2关断，S3的输入端接入高电压信号，第一开关控制端A接入低电压信号，第二开关控制端B接入高电压信号，第三开关控制端C的电位和第四开关控制端D的电位为低电压，TK1关断，TK2打开，TK3和TK4关断，I1接入第二发光控制电压；在发光阶段te，TE打开，TE的漏极接入第二发光控制电压，以驱动M1发光；
当Vdata1为低电压信号，Vdata2为高电压信号时，S1输出高电压信号，S2输出低电压信号，TC1导通，TC2关断，S3的输入端接入低电压信号，第一开关控制端A接入高电压信号，第二开关控制端B接入低电压信号，第三开关控制端C的电位和第四开关控制端D的电位为低电压，TK1打开，TK2关断，TK3和TK4关断，I1接入第一发光控制电压；在发光阶段te，TE打开，TE的漏极接入第一发光控制电压，以驱动M1发光；
当Vdata1为高电压信号，Vdata2为低电压信号时，S1输出低电压信号，S2输出高电压信号，TC1关断，TC2导通，S4的输入端接入低电压信号，第三开关控制端C接入高电压信号，第四开关控制端D接入低电压信号，第一开关控制端A的电位和第二开关控制端B的电位为低电压，TK3打开，TK4关断，TK1和TK2关断，I1接入第三发光控制电压；在发光阶段te，TE打开，TE的漏极接入第三发光控制电压，以驱动M1发光；
当Vdata1为高电压信号，Vdata2为高电压信号时，S1输出低电压信号，S2输出低电压信号，TC1关断，TC2导通，S4的输入端接入高电压信号，第三开关控制端C接入低电压信号，第四开关控制端D接入高电压信号，第一开关控制端A的电位和第二开关控制端B的电位为低电压，TK4打开，TK3 关断，TK1和TK2关断，I1接入第四发光控制电压；在发光阶段te，TE打开，TE的漏极接入第四发光控制电压，以驱动M1发光。
在本公开至少一实施例中，所述第一控制电路包括第一数据写入电路、第二数据写入电路、第三数据写入电路、第四数据写入电路和第二控制子电路；
所述第一数据写入电路分别与第一扫描端、第一数据电压端和第一数据接入端电连接，用于在所述第一扫描端提供的第一扫描信号的控制下，将所述第一数据电压端提供的第一数据电压写入所述第一数据接入端；
所述第二数据写入电路分别与第二扫描端、第二数据电压端和第二数据接入端电连接，用于在所述第二扫描端提供的第二扫描信号的控制下，将所述第二数据电压端提供的第二数据电压写入所述第二数据接入端；
所述第三数据写入电路分别与第三扫描端、第三数据电压端和第三数据接入端电连接，用于在所述第三扫描端提供的第三扫描信号的控制下，将所述第三数据电压端提供的第三数据电压写入所述第三数据接入端；
所述第四数据写入电路分别与第四扫描端、第四数据电压端和第四数据接入端电连接，用于在所述第四扫描端提供的第四扫描信号的控制下，将所述第四数据电压端提供的第四数据电压写入所述第四数据接入端；
所述第二控制子电路分别与所述第一数据接入端、所述第二数据接入端、所述第三数据接入端、所述第四数据接入端和N个开关控制端电连接，用于根据所述第一数据接入端的电位、所述第二数据接入端的电位、所述第三数据接入端的电位和所述第四数据接入端的电位，控制向所述N个开关控制端分别提供相应的开关控制信号。
如图7所示，在图2所示的像素电路的至少一实施例的基础上，所述第一控制电路包括第一数据写入电路71、第二数据写入电路72、第三数据写入电路73、第四数据写入电路74和第二控制子电路75；
所述第一数据写入电路71分别与第一扫描端G1、第一数据电压端D1和第一数据接入端DI1电连接，用于在所述第一扫描端G1提供的第一扫描信号的控制下，将所述第一数据电压端D1提供的第一数据电压Vdata1写入所述第一数据接入端DI1；
所述第二数据写入电路72分别与第二扫描端G2、第二数据电压端D2和第二数据接入端DI2电连接，用于在所述第二扫描端G2提供的第二扫描信号的控制下，将所述第二数据电压端D2提供的第二数据电压Vdata2写入所述第二数据接入端DI2；
所述第三数据写入电路73分别与第三扫描端G3、第三数据电压端D3和第三数据接入端DI3电连接，用于在所述第三扫描端G3提供的第三扫描信号的控制下，将所述第三数据电压端D3提供的第三数据电压Vdata3写入所述第三数据接入端DI3；
所述第四数据写入电路74分别与第四扫描端G4、第四数据电压端D4和第四数据接入端DI4电连接，用于在所述第四扫描端G4提供的第四扫描信号的控制下，将所述第四数据电压端D4提供的第四数据电压Vdata4写入所述第四数据接入端DI4；
所述第二控制子电路75分别与所述第一数据接入端DI1、所述第二数据接入端DI2、所述第三数据接入端DI3、所述第四数据接入端DI4、第一开关控制端A、第二开关控制端B、第三开关控制端C、第四开关控制端D、第五开关控制端E、第六开关控制端F、第七开关控制端G和第八开关控制端H电连接，用于根据所述第一数据接入端DI1的电位、所述第二数据接入端DI2的电位、所述第三数据接入端DI3的电位和所述第四数据接入端DI4的电位，控制向所述第一开关控制端A提供第一开关控制信号，控制向第二开关控制端B提供第二开关控制信号，控制向第三开关控制端C提供第三开关控制信号，控制向第四开关控制端D提供第四开关控制信号，控制向第五开关控制端E提供第五开关控制信号，控制向第六开关控制端F提供第六开关控制信号，控制向第七开关控制端G提供第七开关控制信号，控制向第八开关控制端H提供第八开关控制信号。
可选的，所述第二控制子电路包括第一锁存器、第二锁存器、第三锁存器、第四锁存器、第五锁存器、第六锁存器、第七锁存器、第八锁存器、第九锁存器、第十锁存器、第一控制开关、第二控制开关、第三控制开关、第四控制开关、第五控制开关和第六控制开关；N等于8；
所述第一锁存器的输入端与所述第一数据接入端电连接，所述第一锁存 器的输出端与所述第一控制开关的控制端电连接，所述第一锁存器用于锁存所述第一数据接入端接入的电压信号，并输出第一输出电压，所述第一输出电压与所述第一数据接入端接入的电压信号反相；
所述第二锁存器的输入端与所述第二数据接入端电连接，所述第二锁存器的输出端与所述第二控制开关的控制端电连接，所述第二锁存器用于锁存所述第二数据接入端接入的电压信号，并输出第二输出电压，所述第二输出电压与所述第二数据接入端接入的电压信号反相；
所述第三锁存器的输入端与所述第一控制开关的第一端电连接，所述第三锁存器的输出端与所述第三控制开关的控制端电连接，所述第三锁存器用于锁存其输入端接入的电压信号，并输出第三输出电压，所述第三输出电压与所述第三锁存器的输入端接入的电压信号反相；
所述第四锁存器的输入端与所述第二控制开关的第一端电连接，所述第四锁存器的输出端与第第五控制开关的控制端电连接，所述第四锁存器用于锁存其输入端接入的电压信号，并输出第四输出电压，所述第四输出电压与所述第四锁存器的输入端接入的电压信号反相；
所述第五锁存器的输入端与所述第三控制开关的第一端电连接，所述第五锁存器的输出端与第二开关控制端电连接，所述第五锁存器用于锁存其输入端接入的电压信号，并输出第五输出电压，所述第五输出电压与所述第五锁存器的输入端接入的电压信号反相；
所述第六锁存器的输入端与所述第三数据接入端电连接，所述第六锁存器的输出端与所述第三控制开关的第二端电连接，所述第六锁存器用于锁存其输入端接入的电压信号，并输出第六输出电压，所述第六输出电压与所述第六锁存器的输入端接入的电压信号反相；
所述第七锁存器的输入端与所述第四控制开关的第一端电连接，所述第七锁存器的输出端与第四开关控制端电连接，所述第七锁存器用于锁存其输入端接入的电压信号，并输出第七输出电压，所述第七输出电压与所述第七锁存器的输入端接入的电压信号反相；
所述第八锁存器的输入端与所述第五控制开关的第一端电连接，所述第八锁存器的输出端与第六开关控制端电连接，所述第八锁存器用于锁存其输 入端接入的电压信号，并输出第八输出电压，所述第八输出电压与所述第八锁存器的输入端接入的电压信号反相；
所述第九锁存器的输入端与所述第四数据接入端电连接，所述第九锁存器的输出端与所述第五控制开关的第二端电连接，所述第九锁存器用于锁存其输入端接入的电压信号，并输出第九输出电压，所述第九输出电压与所述第九锁存器的输入端接入的电压信号反相；
所述第十锁存器的输入端与所述第六控制开关的第一端电连接，所述第十锁存器的输出端与第八开关控制端电连接，所述第十锁存器用于锁存其输入端接入的电压信号，并输出第十输出电压，所述第十输出电压与所述第十锁存器的输入端接入的电压信号反相；
所述第一控制开关的控制端与所述第一锁存器的输出端电连接，所述第一控制开关的第二端与所述第二锁存器的输出端的电连接，所述第一控制开关用于在其控制端的电位的控制下，控制所述第一控制开关的第一端与所述第一控制开关的第二端之间连通或断开；
所述第二控制开关的控制端与所述第一锁存器的输入端电连接，所述第二控制开关的第二端与所述第二锁存器的输入端的电连接，所述第二控制开关用于在其控制端的电位的控制下，控制所述第二控制开关的第一端与所述第二控制开关的第二端之间连通或断开；
所述第三控制开关的控制端与所述第三锁存器的输出端电连接，所述第三控制开关用于在其控制端的电位的控制下，控制所述第五锁存器的输入端与所述第六锁存器的输出端之间连通或断开；
所述第四控制开关的控制端与所述第三锁存器的输入端电连接，所述第四控制开关用于在其控制端的电位的控制下，控制所述第七锁存器的输入端与所述第六锁存器的输入端之间连通或断开；
所述第五控制开关的控制端与所述第四锁存器的输出端电连接，所述第五控制开关用于在其控制端的电位的控制下，控制所述第八锁存器的输入端与所述第九锁存器的输出端电连接；
所述第六控制开关的控制端与所述第四锁存器的输入端电连接，所述第六控制开关用于在其控制端的电位的控制下，控制所述第十锁存器的输入端 与所述第九锁存器的输入端之间连通；
第一开关控制端与第五锁存器的输入端电连接，第七开关控制端与第十锁存器的输入端电连接。
如图8所示，在图7所示的像素电路的至少一实施例的基础上，所述第二控制子电路包括第一锁存器S1、第二锁存器S2、第三锁存器S3、第四锁存器S4、第五锁存器S5、第六锁存器S6、第七锁存器S7、第八锁存器S8、第九锁存器S9、第十锁存器S10、第一控制开关K1、第二控制开关K2、第三控制开关K3、第四控制开关K4、第五控制开关K5和第六控制开关K6；N等于8；
所述第一锁存器S1的输入端与所述第一数据接入端DI1电连接，所述第一锁存器S1的输出端与所述第一控制开关K1的控制端电连接，所述第一锁存器S1用于锁存所述第一数据接入端DI1接入的电压信号，并通过所述第一锁存器S1的输出端输出第一输出电压Vo1，所述第一输出电压Vo1与所述第一数据接入端DI1接入的电压信号反相；
所述第二锁存器S2的输入端与所述第二数据接入端DI2电连接，所述第二锁存器S2的输出端与所述第二控制开关K2的控制端电连接，所述第二锁存器S2用于锁存所述第二数据接入端DI2接入的电压信号，并通过所述第二锁存器S2的输出端输出第二输出电压Vo2，所述第二输出电压Vo2与所述第二数据接入端DI2接入的电压信号反相；
所述第三锁存器S3的输入端与所述第一控制开关K1的第一端电连接，所述第三锁存器S3的输出端与所述第三控制开关K3的控制端电连接，所述第三锁存器S3用于锁存其输入端接入的电压信号，并通过所述第三锁存器S3的输出端输出第三输出电压Vo3，所述第三输出电压Vo3与所述第三锁存器S3的输入端接入的电压信号反相；
所述第四锁存器S4的输入端与所述第二控制开关K2的第一端电连接，所述第四锁存器S4的输出端与第第五控制开关K5的控制端电连接，所述第四锁存器S4用于锁存其输入端接入的电压信号，并通过所述第四锁存器S4的输出端输出第四输出电压Vo4，所述第四输出电压Vo4与所述第四锁存器S4的输入端接入的电压信号反相；
所述第五锁存器S5的输入端与所述第三控制开关K3的第一端电连接，所述第五锁存器S5的输出端与第二开关控制端B电连接，所述第五锁存器S5用于锁存其输入端接入的电压信号，并通过所述第五锁存器S5的输出端输出第五输出电压Vo5，所述第五输出电压Vo5与所述第五锁存器S5的输入端接入的电压信号反相；
所述第六锁存器S6的输入端与所述第三数据接入端DI3电连接，所述第六锁存器S6的输出端与所述第三控制开关K3的第二端电连接，所述第六锁存器S6用于锁存其输入端接入的电压信号，并通过所述第六锁存器S6的输出端输出输出第六输出电压Vo6，所述第六输出电压Vo6与所述第六锁存器S6的输入端接入的电压信号反相；
所述第七锁存器S7的输入端与所述第四控制开关K4的第一端电连接，所述第七锁存器S7的输出端与第四开关控制端D电连接，所述第七锁存器S7用于锁存其输入端接入的电压信号，并通过所述第七锁存器S7输出第七输出电压Vo7，所述第七输出电压Vo7与所述第七锁存器S7的输入端接入的电压信号反相；
所述第八锁存器S8的输入端与所述第五控制开关K5的第一端电连接，所述第八锁存器S8的输出端与第六开关控制端F电连接，所述第八锁存器S8用于锁存其输入端接入的电压信号，并通过所述第八锁存器S8的输出端输出第八输出电压Vo8，所述第八输出电压Vo8与所述第八锁存器S8的输入端接入的电压信号反相；
所述第九锁存器S9的输入端与所述第四数据接入端DI4电连接，所述第九锁存器S9的输出端与所述第五控制开关K5的第二端电连接，所述第九锁存器S9用于锁存其输入端接入的电压信号，并通过所述第九锁存器S9输出输出第九输出电压Vo9，所述第九输出电压Vo9与所述第九锁存器S9的输入端接入的电压信号反相；
所述第十锁存器S10的输入端与所述第六控制开关K6的第一端电连接，所述第十锁存器S10的输出端与第八开关控制端H电连接，所述第十锁存器S10用于锁存其输入端接入的电压信号，并通过所述第十锁存器S10的输出端输出第十输出电压Vo10，所述第十输出电压V10与所述第十锁存器S10 的输入端接入的电压信号反相；
所述第一控制开关K1的控制端与所述第一锁存器S1的输出端电连接，所述第一控制开关K1的第二端与所述第二锁存器S2的输出端的电连接，所述第一控制开关K1用于在其控制端的电位的控制下，控制所述第一控制开关K1的第一端与所述第一控制开关K1的第二端之间连通或断开；
所述第二控制开关K2的控制端与所述第一锁存器S1的输入端电连接，所述第二控制开关K2的第二端与所述第二锁存器S2的输入端的电连接，所述第二控制开关K2用于在其控制端的电位的控制下，控制所述第二控制开关K2的第一端与所述第二控制开关K2的第二端之间连通或断开；
所述第三控制开关K3的控制端与所述第三锁存器S3的输出端电连接，所述第三控制开关K3用于在其控制端的电位的控制下，控制所述第五锁存器S5的输入端与所述第六锁存器S6的输出端之间连通或断开；
所述第四控制开关K4的控制端与所述第三锁存器S3的输入端电连接，所述第四控制开关K4用于在其控制端的电位的控制下，控制所述第七锁存器S7的输入端与所述第六锁存器S6的输入端之间连通或断开；
所述第五控制开关K5的控制端与所述第四锁存器S4的输出端电连接，所述第五控制开关K5用于在其控制端的电位的控制下，控制所述第八锁存器S8的输入端与所述第九锁存器S9的输出端电连接；
所述第六控制开关K6的控制端与所述第四锁存器S4的输入端电连接，所述第六控制开关K6用于在其控制端的电位的控制下，控制所述第十锁存器S10的输入端与所述第九锁存器S9的输入端之间连通；
第一开关控制端A与第五锁存器S5的输入端电连接，第七开关控制端G与第十锁存器S10的输入端电连接；
第三开关控制端C与第七锁存器S7的输入端电连接，第五开关控制端E与第八锁存器S8的输入端电连接。
本公开如图8所示的像素电路的至少一实施例在工作时，
当Vdata1为低电压信号，Vdata2为低电压信号，Vdata3为低电压信号，Vdata4为低电压信号时，K1的栅极接入高电压信号，K2的栅极接入低电压信号，K1导通，K2关断，S3的输入端接入高电压信号，S3输出低电压信号， K3关断，K4打开，S7的输入端接入低电压信号，S7输出高电压信号至第四开关控制端D；
当Vdata1为高电压信号，Vdata2为低电压信号，Vata3为低电压信号，Vdata4为低电压信号时，S1输出低电压信号，K1关断，S2输出高电压信号，K2导通，S4的输入端接入低电压信号，K5的控制端接入高电压信号，K5导通，K6关断，S9的输入端接入低电压信号，S9输出高电压信号，并通过K5将高电压信号提供至第五开关控制端E；
当Vdata1为低电压信号，Vdata2为高电压信号，Vdata3为低电压信号，Vdata4为低电压信号时，S1输出高电压信号，K1导通，K2关断，S2输出低电压信号，S3的输入端接入低电压信号，S3输出高电压信号，K3导通，K4关断，S6输出高电压信号，S6通过导通的K3将高电压信号提供至第一开关控制端A；
当Vdata1为低电压信号，Vdata2为低电压信号，Vdata3为高电压信号，Vdata4为低电压信号时，S1输出高电压信号，S2提供高电压信号，K1导通，K2关断，S3的输入端接入高电压信号，S3输出低电压信号，K3关断，K4导通，S7的输入端接入高电压信号，将高电压信号写入第三开关控制端C；
当Vdata1为低电压信号，Vdata2为低电压信号，Vdata3为低电压信号，Vdata4为高电压信号时，S1输出高电压信号，S2输出高电压信号，K1导通，K2关断，S3的输入端接入高电压信号，S3输出低电压信号，K3关断，K4导通，S6的输入端接入低电压信号，S7的输入端接入低电压信号，S7输出高电压信号至第四开关控制端D；
当Vdata1为高电压信号，Vdata2为高电压信号，Vdata3为低电压信号，Vdata4为低电压信号时，S1输出低电压信号，S2输出低电压信号，K1关断，K2导通，S4的输入端接入高电压信号，S4输出低电压信号，K7关断，K8导通，S9的输入端接入低电压信号，S10的输入端接入低电压信号，S10输出高电压信号至第八开关控制端H；
当Vdata1为高电压信号，Vdata2为高电压信号，Vdata3为低电压信号，Vdata4为高电压信号时，S1输出低电压信号，S2输出低电压信号，K1关断，K2导通，S4的输入端接入高电压信号，S4输出低电压信号，K7关断，K8 导通，S9的输入端接入高电压信号，S10的输入端接入高电压信号，S10输出低电压信号，以将高电压信号写入第七开关控制端G；
当Vdata1为高电压信号，Vdata2为高电压信号，Vdata3为高电压信号，Vdata4为低电压信号时，S1输出低电压信号，S2输出低电压信号，K1关断，K2导通；S4的输入端接入高电压信号，S4输出低电压信号，K7关断，K8导通，S9的输入端接入低电压信号，S9输出高电压信号，S10的输入端接入低电压信号，S10输出高电压信号至第八开关控制端H；
当Vdata1为高电压信号，Vdata2为高电压信号，Vdata3为高电压信号，Vdata4为高电压信号时，S1输出低电压信号，S2输出低电压信号，K1关断，K2导通，S4的输入端接入高电压信号，S4输出低电压信号，K7关断，K8导通，S9的输入端接入高电压信号，S9输出低电压信号，S10的输入端接入高电压信号，S10输出低电压信号，以将高电压信号提供至第七开关控制端G；
当Vdata1为高电压信号，Vdata2为低电压信号，Vdata3为高电压信号，Vdata4为高电压信号时，S1输出低电压信号，S2输出高电压信号，K1关断，K2导通，S4的输入端接入低电压信号，S4输出高电压信号，K7导通，K8关断，S9的输入端接入高电压信号，S9输出低电压信号至S8的输入端，S8输出高电压信号至第六开关控制端F；
当Vdata1为高电压信号，Vdata2为低电压信号，Vdata3为低电压信号，Vdata4为高电压信号时，S1输出低电压信号，S2提供高电压信号，K1关断，K2导通，S4的输入端接入低电压信号，S4输出高电压信号，K7导通，K8关断，S9的输入端接入高电压信号，S9输出低电压信号至S8的输入端，S8输出高电压信号至第六开关控制端F；
当Vdata1为高电压信号，Vdata2为低电压信号，Vdata3为高电压信号，Vdata4为低电压信号时，S1输出低电压信号，S2提供高电压信号，K1关断，K2导通，S4的输入端接入低电压信号，S4输出高电压信号，K7导通，K8关断，S9的输入端接入低电压信号，S9输出高电压信号至S8的输入端，S8输出低电压信号，S9输出高电压信号至第五开关控制端E；
当Vdata1为低电压信号，Vdata2为高电压信号，Vdata3为高电压信号， Vdata4为高电压信号时，S1输出高电压信号，S2输出低电压信号，K1导通，K2关断，S3的输入端接入低电压信号，S3输出高电压信号，K3导通，K4关断，S6的输入端接入高电压信号，S6输出低电压信号，S5的输入端接入低电压信号，S5输出高电压信号至第二开关控制端B；
当Vdata1为低电压信号，Vdata2为高电压信号，Vdata3为低电压信号，Vdata4为高电压信号时，S1输出高电压信号，S2输出低电压信号，K1导通，K2关断，S3的输入端接入低电压信号，S3输出高电压信号，K3导通，K4关断，S6的输入端接入低电压信号，S6输出高电压信号至第一开关控制端A；
当Vdata1为低电压信号，Vdata2为高电压信号，Vdata3为高电压信号，Vdata4为低电压信号时，S1输出高电压信号，S2输出低电压信号，K1导通，K2关断，S3的输入端接入低电压信号，S3输出高电压信号，K3导通，K4关断，S6的输入端接入高电压信号，S6输出低电压信号至S5的输入端，S5输出高电压信号至第二开关控制端B；
当Vdata1为低电压信号，Vdata2为低电压信号，Vdata3为高电压信号，Vdata4为高电压信号时，S1输出高电压信号，S2输出高电压信号，K1导通，K2关断，S3的输入端接入高电压信号，S3输出低电压信号，K3关断，K4导通，S6的输入端接入高电压信号，S7的输入端接入高电压信号，S7输出低电压信号，并将高电压信号提供至第三开关控制端C。
在本公开至少一实施例中，所述第一锁存器包括第一反相器和第二反相器；
所述第一反相器的输入端与所述第一锁存器的输入端电连接，所述第一反相器的输出端与所述第一锁存器的输出端电连接；
所述第二反相器的输入端与所述第一反相器的输出端电连接，所述第二反相器的输出端与所述第一反相器的输入端电连接；
所述第二锁存器包括第三反相器和第四反相器；
所述第三反相器的输入端与所述第二锁存器的输入端电连接，所述第三反相器的输出端与所述第二锁存器的输出端电连接；
所述第四反相器的输入端与所述第三反相器的输出端电连接，所述第四反相器的输出端与所述第三反相器的输入端电连接；
所述第三锁存器包括第五反相器和第六反相器；
所述第五反相器的输入端与所述第三锁存器的输入端电连接，所述第五反相器的输出端与所述第三锁存器的输出端电连接；
所述第六反相器的输入端与所述第五反相器的输出端电连接，所述第六反相器的输出端与所述第五反相器的输入端电连接；
所述第四锁存器包括第七反相器和第八反相器；
所述第七反相器的输入端与所述第四锁存器的输入端电连接，所述第七反相器的输出端与所述第四锁存器的输出端电连接；
所述第八反相器的输入端与所述第七反相器的输出端电连接，所述第八反相器的输出端与所述第七反相器的输入端电连接；
所述第五锁存器包括第九反相器和第十反相器；
所述第九反相器的输入端与所述第五锁存器的输入端电连接，所述第九反相器的输出端与所述第五锁存器的输出端电连接；
所述第十反相器的输入端与所述第九反相器的输出端电连接，所述第十反相器的输出端与所述第九反相器的输入端电连接；
所述第六锁存器包括第十一反相器和第十二反相器；
所述第十一反相器的输入端与所述第六锁存器的输入端电连接，所述第十一反相器的输出端与所述第六锁存器的输出端电连接；
所述第十二反相器的输入端与所述第十一反相器的输出端电连接，所述第十二反相器的输出端与所述第十一反相器的输入端电连接；
所述第七锁存器包括第十三反相器和第十四反相器；
所述第十三反相器的输入端与所述第七锁存器的输入端电连接，所述第十三反相器的输出端与所述第七锁存器的输出端电连接；
所述第十四反相器的输入端与所述第十三反相器的输出端电连接，所述第十四反相器的输出端与所述第十三反相器的输入端电连接；
所述第八锁存器包括第十五反相器和第十六反相器；
所述第十五反相器的输入端与所述第八锁存器的输入端电连接，所述第十五反相器的输出端与所述第八锁存器的输出端电连接；
所述第十六反相器的输入端与所述第十五反相器的输出端电连接，所述 第十六反相器的输出端与所述第十五反相器的输入端电连接；
所述第九锁存器包括第十七反相器和第十八反相器；
所述第十七反相器的输入端与所述第九锁存器的输入端电连接，所述第十七反相器的输出端与所述第九锁存器的输出端电连接；
所述第十八反相器的输入端与所述第十七反相器的输出端电连接，所述第十八反相器的输出端与所述第十七反相器的输入端电连接；
所述第十锁存器包括第十九反相器和第二十反相器；
所述第十九反相器的输入端与所述第十锁存器的输入端电连接，所述第十九反相器的输出端与所述第十锁存器的输出端电连接；
所述第二十反相器的输入端与所述第十九反相器的输出端电连接，所述第二十反相器的输出端与所述第十九反相器的输入端电连接。
可选的，所述第一控制开关为第一控制晶体管，所述第二控制开关为第二控制晶体管；所述第三控制开关为第三控制晶体管，所述第四控制开关为第四控制晶体管；第五控制开关为第五控制晶体管，所述第六控制开关为第六控制晶体管；
所述第一控制晶体管的控制极与所述第一锁存器的输出端电连接，所述第一控制晶体管的第一极与所述第三锁存器的输入端电连接，所述第一控制晶体管的第二极与所述第二锁存器的输出端的电连接；
所述第二控制晶体管的控制极与所述第一锁存器的输入端电连接，所述第二控制晶体管的第一极与所述第四锁存器的输入端电连接，所述第二控制晶体管的第二极与所述第二锁存器的输入端的电连接；
所述第三控制晶体管的控制极与所述第三锁存器的输出端电连接，所述第三控制晶体管的第一极与所述第五锁存器的输入端电连接，所述第三控制晶体管的第二极与所述第六锁存器的输出端电连接；
所述第四控制晶体管的控制极与所述第三锁存器的输入端电连接，所述第四控制晶体管的第一极与第七锁存器的输入端电连接，所述第四控制晶体管的第二极与所述第六锁存器的输入端电连接；
所述第五控制晶体管的控制极与所述第四锁存器的输出端电连接，所述第五控制晶体管的第一极与所述第八锁存器的输入端电连接，所述第五控制 晶体管的第二极与所述第九锁存器的输出端电连接；
所述第六控制晶体管的控制极与所述第四锁存器的输入端电连接，所述第六控制晶体管的第一极与所述第十锁存器的输入端电连接，所述第六控制晶体管的第二极与所述第九锁存器的输入端电连接。
可选的，所述第一数据写入电路包括第一写入晶体管，所述第二数据写入电路包括第二写入晶体管，所述第三数据写入电路包括第三写入晶体管，所述第四数据写入电路包括第四写入晶体管；
所述第一写入晶体管的控制极与所述第一扫描端电连接，所述第一写入晶体管的第一极与所述第一数据电压端电连接，所述第一写入晶体管的第二极与所述第一数据接入端电连接；
所述第二写入晶体管的控制极与所述第二扫描端电连接，所述第二写入晶体管的第一极与所述第二数据电压端电连接，所述第二写入晶体管的第二极与所述第二数据接入端电连接；
所述第三写入晶体管的控制极与所述第三扫描端电连接，所述第三写入晶体管的第一极与所述第三数据电压端电连接，所述第三写入晶体管的第二极与所述第三数据接入端电连接；
所述第四写入晶体管的控制极与所述第四扫描端电连接，所述第四写入晶体管的第一极与所述第四数据电压端电连接，所述第四写入晶体管的第二极与所述第四数据接入端电连接。
如图9所示，在图8所示的像素电路的至少一实施例的基础上，所述第一锁存器包括第一反相器F1和第二反相器F2；
所述第一反相器F1的输入端与所述第一锁存器的输入端电连接，所述第一反相器F1的输出端与所述第一锁存器的输出端电连接；
所述第二反相器F2的输入端与所述第一反相器F1的输出端电连接，所述第二反相器F2的输出端与所述第一反相器F1的输入端电连接；
所述第二锁存器包括第三反相器F3和第四反相器F4；
所述第三反相器F3的输入端与所述第二锁存器的输入端电连接，所述第三反相器F3的输出端与所述第二锁存器的输出端电连接；
所述第四反相器F4的输入端与所述第三反相器F3的输出端电连接，所 述第四反相器F4的输出端与所述第三反相器F3的输入端电连接；
所述第三锁存器包括第五反相器F5和第六反相器F6；
所述第五反相器F5的输入端与所述第三锁存器的输入端电连接，所述第五反相器F5的输出端与所述第三锁存器的输出端电连接；
所述第六反相器F6的输入端与所述第五反相器F5的输出端电连接，所述第六反相器F6的输出端与所述第五反相器F5的输入端电连接；
所述第四锁存器包括第七反相器F7和第八反相器F8；
所述第七反相器F7的输入端与所述第四锁存器的输入端电连接，所述第七反相器F7的输出端与所述第四锁存器的输出端电连接；
所述第八反相器F8的输入端与所述第七反相器F7的输出端电连接，所述第八反相器F8的输出端与所述第七反相器F7的输入端电连接；
所述第五锁存器包括第九反相器F9和第十反相器F10；
所述第九反相器F9的输入端与所述第五锁存器的输入端电连接，所述第九反相器F9的输出端与所述第五锁存器的输出端电连接；
所述第十反相器F10的输入端与所述第九反相器F9的输出端电连接，所述第十反相器F10的输出端与所述第五反相器F5的输入端电连接；
所述第六锁存器包括第十一反相器F11和第十二反相器F12；
所述第十一反相器F11的输入端与所述第六锁存器的输入端电连接，所述第十一反相器F11的输出端与所述第六锁存器的输出端电连接；
所述第十二反相器F12的输入端与所述第十一反相器F11的输出端电连接，所述第十二反相器F12的输出端与所述第十一反相器F11的输入端电连接；
所述第七锁存器包括第十三反相器F13和第十四反相器F14；
所述第十三反相器F13的输入端与所述第七锁存器的输入端电连接，所述第十三反相器F13的输出端与所述第七锁存器的输出端电连接；
所述第十四反相器F14的输入端与所述第十三反相器F13的输出端电连接，所述第十四反相器F14的输出端与所述第十三反相器F13的输入端电连接；
所述第八锁存器包括第十五反相器F15和第十六反相器F16；
所述第十五反相器F15的输入端与所述第八锁存器的输入端电连接，所述第十五反相器F15的输出端与所述第八锁存器的输出端电连接；
所述第十六反相器F16的输入端与所述第十五反相器F15的输出端电连接，所述第十六反相器F16的输出端与所述第十五反相器F15的输入端电连接；
所述第九锁存器包括第十七反相器F17和第十八反相器F18；
所述第十七反相器F17的输入端与所述第九锁存器的输入端电连接，所述第十七反相器F17的输出端与所述第九锁存器的输出端电连接；
所述第十八反相器F18的输入端与所述第十七反相器F17的输出端电连接，所述第十八反相器F18的输出端与所述第十七反相器F17的输入端电连接；
所述第十锁存器包括第十九反相器F19和第二十反相器F20；
所述第十九反相器F19的输入端与所述第十锁存器的输入端电连接，所述第十九反相器S19的输出端与所述第十锁存器的输出端电连接；
所述第二十反相器F20的输入端与所述第十九反相器F19的输出端电连接，所述第二十反相器F20的输出端与所述第十九反相器F19的输入端电连接；
所述第一控制开关为第一控制晶体管TC1，所述第二控制开关为第二控制晶体管TC2；所述第三控制开关为第三控制晶体管TC3，所述第四控制开关为第四控制晶体管TC4；第五控制开关为第五控制晶体管TC5，所述第六控制开关为第六控制晶体管TC6；
所述第一控制晶体管TC1的栅极与所述第一锁存器S1的输出端电连接，所述第一控制晶体管TC1的漏极与所述第三锁存器S3的输入端电连接，所述第一控制晶体管TC1的源极与所述第二锁存器S2的输出端的电连接；
所述第二控制晶体管TC2的栅极与所述第一锁存器S1的输入端电连接，所述第二控制晶体管TC2的漏极与所述第四锁存器S4的输入端电连接，所述第二控制晶体管TC2的源极与所述第二锁存器S2的输入端的电连接；
所述第三控制晶体管TC3的栅极与所述第三锁存器S3的输出端电连接，所述第三控制晶体管TC3的漏极与所述第五锁存器S5的输入端电连接，所 述第三控制晶体管TC3的源极与所述第六锁存器S6的输出端电连接；
所述第四控制晶体管TC4的栅极与所述第三锁存器S3的输入端电连接，所述第四控制晶体管TC4的漏极与第七锁存器S7的输入端电连接，所述第四控制晶体管TC4的源极与所述第六锁存器S6的输入端电连接；
所述第五控制晶体管TC5的栅极与所述第四锁存器S4的输出端电连接，所述第五控制晶体管TC5的漏极与所述第八锁存器S8的输入端电连接，所述第五控制晶体管TC5的源极与所述第九锁存器S9的输出端电连接；
所述第六控制晶体管TC6的栅极与所述第四锁存器S4的输入端电连接，所述第六控制晶体管TC6的漏极与所述第十锁存器S10的输入端电连接，所述第六控制晶体管TC6的源极与所述第九锁存器S9的输入端电连接；
所述第一数据写入电路包括第一写入晶体管TW1，所述第二数据写入电路包括第二写入晶体管TW2，所述第三数据写入电路包括第三写入晶体管TW3，所述第四数据写入电路包括第四写入晶体管TW4；
所述第一写入晶体管TW1的栅极与所述第一扫描端G1电连接，所述第一写入晶体管TW1的漏极与所述第一数据电压端D1电连接，所述第一写入晶体管TW1的源极与所述第一数据接入端DI1电连接；
所述第二写入晶体管TW2的栅极与所述第二扫描端G2电连接，所述第二写入晶体管TW2的漏极与所述第二数据电压端D2电连接，所述第二写入晶体管TW2的源极与所述第二数据接入端DI2电连接；
所述第三写入晶体管TW3的栅极与所述第三扫描端G3电连接，所述第三写入晶体管TW3的漏极与所述第三数据电压端D3电连接，所述第三写入晶体管TW3的源极与所述第三数据接入端DI3电连接；
所述第四写入晶体管TW4的栅极与所述第四扫描端G4电连接，所述第四写入晶体管TW4的漏极与所述第四数据电压端D4电连接，所述第四写入晶体管TW4的源极与所述第四数据接入端DI4电连接；
第一开关控制子电路包括第一开关控制晶体管TK1；
第一开关控制晶体管TK1的栅极与第一开关控制端A电连接，所述第一开关控制晶体管TK1的漏极与第一发光控制电压端VC1电连接，所述第一开关控制晶体管TK1的源极与所述控制电压输入端I1电连接；
第二开关控制子电路包括第二开关控制晶体管TK2；
第二开关控制晶体管TK2的栅极与第二开关控制端B电连接，所述第二开关控制晶体管TK2的漏极与第二发光控制电压端VC2电连接，所述第二开关控制晶体管TK2的源极与所述控制电压输入端I1电连接；
第三开关控制子电路包括第三开关控制晶体管TK3；
第三开关控制晶体管TK3的栅极与第三开关控制端C电连接，所述第三开关控制晶体管TK3的漏极与第三发光控制电压端VC2电连接，所述第三开关控制晶体管TK3的源极与所述控制电压输入端I1电连接；
第四开关控制子电路包括第四开关控制晶体管TK4；
第四开关控制晶体管TK4的栅极与第四开关控制端D电连接，所述第四开关控制晶体管TK4的漏极与第四发光控制电压端VC4电连接，所述第四开关控制晶体管TK4的源极与所述控制电压输入端I1电连接；
第五开关控制子电路包括第五开关控制晶体管TK5；
第五开关控制晶体管TK5的栅极与第五开关控制端E电连接，所述第五开关控制晶体管TK5的漏极与第五发光控制电压端VC5电连接，所述第五开关控制晶体管TK5的源极与所述控制电压输入端I1电连接；
第六开关控制子电路包括第六开关控制晶体管TK6；
第六开关控制晶体管TK6的栅极与第六开关控制端F电连接，所述第六开关控制晶体管TK6的漏极与第六发光控制电压端VC6电连接，所述第六开关控制晶体管TK6的源极与所述控制电压输入端I1电连接；
第七开关控制子电路包括第七开关控制晶体管TK7；
第七开关控制晶体管TK7的栅极与第七开关控制端G电连接，所述第七开关控制晶体管TK7的漏极与第七发光控制电压端VC7电连接，所述第七开关控制晶体管TK7的源极与所述控制电压输入端I1电连接；
第八开关控制子电路包括第八开关控制晶体管TK8；
第八开关控制晶体管TK8的栅极与第八开关控制端H电连接，所述第八开关控制晶体管TK8的漏极与第八发光控制电压端VC8电连接，所述第八开关控制晶体管TK8的源极与所述控制电压输入端I1电连接；
所述发光控制电路包括发光控制晶体管TE；
所述发光控制晶体管TE的栅极与所述发光控制端EM电连接，所述发光控制晶体管TE的漏极与所述控制电压输入端I1电连接，所述发光控制晶体管TE的源极与M1的阳极电连接，M1的阴极与低电压端VSS电连接。
在图9所示的像素电路的至少一实施例中，所有晶体管都为n型晶体管，但不以此为限。
本公开图9所示的像素电路的至少一实施例在工作时，如图10所示，显示周期可以包括先后设置的第一写入阶段tw1、第二写入阶段tw2、第三写入阶段tw3、第四写入阶段tw4和发光阶段te；
在第一写入阶段tw1，G1提供高电压信号，G2、G3和G4都提供低电压信号，D1提供第一数据电压Vdata1至第一数据接入端DI1；
在第二写入阶段tw2，G2提供高电压信号，G1、G3和G4都提供低电压信号，D2提供第二数据电压Vdata2至第二数据接入端DI2；
在第三写入阶段tw3，G3提供高电压信号，G1、G2和G4都提供低电压信号，D3提供第三数据电压Vdata3至第三数据接入端DI3；
在第四写入阶段tw4，G4提供高电压信号，G1、G2和G3都提供低电压信号，D4提供第四数据电压Vdata4至第四数据接入端DI4；
当Vdata1为低电压信号，Vdata2为低电压信号，Vdata3为低电压信号，Vdata4为低电压信号时，K1的栅极接入高电压信号，K2的栅极接入低电压信号，K1导通，K2关断，S3的输入端接入高电压信号，S3输出低电压信号，K3关断，K4打开，S7的输入端接入低电压信号，S7输出高电压信号至第四开关控制端D；在发光阶段te，TK4导通，TE导通，TE的漏极接入第四发光控制电压，M1发光；
当Vdata1为高电压信号，Vdata2为低电压信号，Vata3为低电压信号，Vdata4为低电压信号时，S1输出低电压信号，K1关断，S2输出高电压信号，K2导通，S4的输入端接入低电压信号，K5的控制端接入高电压信号，K5导通，K6关断，S9的输入端接入低电压信号，S9输出高电压信号，并通过K5将高电压信号提供至第五开关控制端E；在发光阶段te，TK5导通，TE导通，TE的漏极接入第五发光控制电压，M1发光；
当Vdata1为低电压信号，Vdata2为高电压信号，Vdata3为低电压信号， Vdata4为低电压信号时，S1输出高电压信号，K1导通，K2关断，S2输出低电压信号，S3的输入端接入低电压信号，S3输出高电压信号，K3导通，K4关断，S6输出高电压信号，S6通过导通的K3将高电压信号提供至第一开关控制端A；在发光阶段te，TK1导通，TE导通，TE的漏极接入第一发光控制电压，M1发光；
当Vdata1为低电压信号，Vdata2为低电压信号，Vdata3为高电压信号，Vdata4为低电压信号时，S1输出高电压信号，S2提供高电压信号，K1导通，K2关断，S3的输入端接入高电压信号，S3输出低电压信号，K3关断，K4导通，S7的输入端接入高电压信号，将高电压信号写入第三开关控制端C；在发光阶段te，TK3导通，TE导通，TE的漏极接入第三发光控制电压，M1发光；
当Vdata1为低电压信号，Vdata2为低电压信号，Vdata3为低电压信号，Vdata4为高电压信号时，S1输出高电压信号，S2输出高电压信号，K1导通，K2关断，S3的输入端接入高电压信号，S3输出低电压信号，K3关断，K4导通，S6的输入端接入低电压信号，S7的输入端接入低电压信号，S7输出高电压信号至第四开关控制端D；在发光阶段te，TK4导通，TE导通，TE的漏极接入第四发光控制电压，M1发光；
当Vdata1为高电压信号，Vdata2为高电压信号，Vdata3为低电压信号，Vdata4为低电压信号时，S1输出低电压信号，S2输出低电压信号，K1关断，K2导通，S4的输入端接入高电压信号，S4输出低电压信号，K7关断，K8导通，S9的输入端接入低电压信号，S10的输入端接入低电压信号，S10输出高电压信号至第八开关控制端H；在发光阶段te，TK8导通，TE导通，TE的漏极接入第八发光控制电压，M1发光；
当Vdata1为高电压信号，Vdata2为高电压信号，Vdata3为低电压信号，Vdata4为高电压信号时，S1输出低电压信号，S2输出低电压信号，K1关断，K2导通，S4的输入端接入高电压信号，S4输出低电压信号，K7关断，K8导通，S9的输入端接入高电压信号，S10的输入端接入高电压信号，S10输出低电压信号，以将高电压信号写入第七开关控制端G；在发光阶段te，TK7导通，TE导通，TE的漏极接入第七发光控制电压，M1发光；
当Vdata1为高电压信号，Vdata2为高电压信号，Vdata3为高电压信号，Vdata4为低电压信号时，S1输出低电压信号，S2输出低电压信号，K1关断，K2导通；S4的输入端接入高电压信号，S4输出低电压信号，K7关断，K8导通，S9的输入端接入低电压信号，S9输出高电压信号，S10的输入端接入低电压信号，S10输出高电压信号至第八开关控制端H；在发光阶段te，TK8导通，TE导通，TE的漏极接入第八发光控制电压，M1发光；
当Vdata1为高电压信号，Vdata2为高电压信号，Vdata3为高电压信号，Vdata4为高电压信号时，S1输出低电压信号，S2输出低电压信号，K1关断，K2导通，S4的输入端接入高电压信号，S4输出低电压信号，K7关断，K8导通，S9的输入端接入高电压信号，S9输出低电压信号，S10的输入端接入高电压信号，S10输出低电压信号，以将高电压信号提供至第七开关控制端G；在发光阶段te，TK7导通，TE导通，TE的漏极接入第七发光控制电压，M1发光；
当Vdata1为高电压信号，Vdata2为低电压信号，Vdata3为高电压信号，Vdata4为高电压信号时，S1输出低电压信号，S2输出高电压信号，K1关断，K2导通，S4的输入端接入低电压信号，S4输出高电压信号，K7导通，K8关断，S9的输入端接入高电压信号，S9输出低电压信号至S8的输入端，S8输出高电压信号至第六开关控制端F；在发光阶段te，TK6导通，TE导通，TE的漏极接入第六发光控制电压，M1发光；
当Vdata1为高电压信号，Vdata2为低电压信号，Vdata3为低电压信号，Vdata4为高电压信号时，S1输出低电压信号，S2提供高电压信号，K1关断，K2导通，S4的输入端接入低电压信号，S4输出高电压信号，K7导通，K8关断，S9的输入端接入高电压信号，S9输出低电压信号至S8的输入端，S8输出高电压信号至第六开关控制端F；在发光阶段te，TK6导通，TE导通，TE的漏极接入第六发光控制电压，M1发光；
当Vdata1为高电压信号，Vdata2为低电压信号，Vdata3为高电压信号，Vdata4为低电压信号时，S1输出低电压信号，S2提供高电压信号，K1关断，K2导通，S4的输入端接入低电压信号，S4输出高电压信号，K7导通，K8关断，S9的输入端接入低电压信号，S9输出高电压信号至S8的输入端，S8 输出低电压信号，S9输出高电压信号至第五开关控制端E；在发光阶段te，TK5导通，TE导通，TE的漏极接入第五发光控制电压，M1发光；
当Vdata1为低电压信号，Vdata2为高电压信号，Vdata3为高电压信号，Vdata4为高电压信号时，S1输出高电压信号，S2输出低电压信号，K1导通，K2关断，S3的输入端接入低电压信号，S3输出高电压信号，K3导通，K4关断，S6的输入端接入高电压信号，S6输出低电压信号，S5的输入端接入低电压信号，S5输出高电压信号至第二开关控制端B；在发光阶段te，TK2导通，TE导通，TE的漏极接入第二发光控制电压，M1发光；
当Vdata1为低电压信号，Vdata2为高电压信号，Vdata3为低电压信号，Vdata4为高电压信号时，S1输出高电压信号，S2输出低电压信号，K1导通，K2关断，S3的输入端接入低电压信号，S3输出高电压信号，K3导通，K4关断，S6的输入端接入低电压信号，S6输出高电压信号至第一开关控制端A；在发光阶段te，TK1导通，TE导通，TE的漏极接入第一发光控制电压，M1发光；
当Vdata1为低电压信号，Vdata2为高电压信号，Vdata3为高电压信号，Vdata4为低电压信号时，S1输出高电压信号，S2输出低电压信号，K1导通，K2关断，S3的输入端接入低电压信号，S3输出高电压信号，K3导通，K4关断，S6的输入端接入高电压信号，S6输出低电压信号至S5的输入端，S5输出高电压信号至第二开关控制端B；在发光阶段te，TK2导通，TE导通，TE的漏极接入第二发光控制电压，M1发光；
当Vdata1为低电压信号，Vdata2为低电压信号，Vdata3为高电压信号，Vdata4为高电压信号时，S1输出高电压信号，S2输出高电压信号，K1导通，K2关断，S3的输入端接入高电压信号，S3输出低电压信号，K3关断，K4导通，S6的输入端接入高电压信号，S7的输入端接入高电压信号，S7输出低电压信号，并将高电压信号提供至第三开关控制端C；在发光阶段te，TK3导通，TE导通，TE的漏极接入第三发光控制电压，M1发光。
在本公开至少一实施例中，所述发光电路可以包括幅度控制子电路、驱动子电路、第一通断控制子电路和发光元件；所述驱动子电路的第一端与第二电压端电连接；
所述幅度控制子电路用于根据显示数据电压，控制所述驱动子电路生成的驱动电流；
所述发光控制电路用于在所述发光控制信号的控制下，控制所述控制电压输入端与所述第一通断控制子电路的控制端之间连通；
所述第一通断控制子电路的控制端与所述发光控制电路电连接，所述第一通断控制子电路的第一端与所述驱动子电路的第二端电连接，所述第一通断控制子电路的第二端与所述发光元件电连接；所述第一通断控制子电路用于在其控制端的电位的控制下，控制所述驱动子电路与所述发光元件之间连通。
在本公开至少一实施例中，所述第二电压端可以为高电压端，但不以此为限。
可选的，所述幅度控制子电路包括数据写入子电路、储能子电路和复位子电路；
所述数据写入子电路分别与第一扫描线、数据线和所述驱动子电路的控制端电连接，用于在所述第一扫描线提供的第一扫描信号的控制下，将所述数据线提供的数据电压写入所述驱动子电路的控制端；
所述复位子电路分别与第一扫描线、复位电压端和所述驱动子电路的第二端电连接，用于在所述第一扫描信号的控制下，控制将所述复位电压端提供的复位电压写入所述驱动子电路的第二端；
所述储能子电路分别与所述驱动子电路的控制端和所述驱动子电路的第二端电连接，用于储能电能；
所述驱动子电路用于在其控制端的电位的控制下，生成驱动电流。
可选的，所述幅度控制子电路包括数据写入子电路和储能子电路；
所述数据写入子电路分别与扫描线、数据线和所述驱动子电路的控制端电连接，所述数据写入子电路用于在所述扫描线提供的扫描信号的控制下，将所述数据线提供的数据的电压写入所述驱动子电路的控制端；
所述储能子电路分别与所述驱动子电路的控制端和第一公共电极端电连接，用于储存电能；
所述驱动子电路用于在其控制端的电位的控制下，生成驱动电流。
如图11所示，所述发光电路的至少一实施例可以包括幅度控制子电路110、驱动子电路111、第一通断控制子电路112和发光元件10；所述驱动子电路111的第一端与第二电压端V2电连接；
所述幅度控制子电路110与所述驱动子电路111电连接，用于根据显示数据电压，控制所述驱动子电路111生成的驱动电流；
所述发光控制电路11用于在所述发光控制信号的控制下，控制所述控制电压输入端I1与所述第一通断控制子电路112的控制端之间连通；
所述第一通断控制子电路112的控制端与所述发光控制电路11电连接，所述第一通断控制子电路112的第一端与所述驱动子电路111的第二端电连接，所述第一通断控制子电路112的第二端与所述发光元件10的第一极电连接；所述第一通断控制子电路112用于在其控制端的电位的控制下，控制所述驱动子电路111与所述发光元件10之间连通；
所述发光元件10的第二极与第一电压端V1电连接。
可选的，所述第一电压端V1可以为低电压端。
如图12所示，在图11所示的发光电路的至少一实施例的基础上，所述幅度控制子电路可以包括数据写入子电路121、储能子电路122和复位子电路123；
所述数据写入子电路121分别与第一扫描线GT1、数据线DA和所述驱动子电路111的控制端电连接，用于在所述第一扫描线GT1提供的第一扫描信号的控制下，将所述数据线DA提供的数据电压写入所述驱动子电路111的控制端；所述数据线DA用于提供显示数据电压；
所述复位子电路123分别与第一扫描线GT1、复位电压端R1和所述驱动子电路111的第二端电连接，用于在所述第一扫描信号的控制下，控制将所述复位电压端R1提供的复位电压写入所述驱动子电路111的第二端；
所述储能子电路122分别与所述驱动子电路111的控制端和所述驱动子电路111的第二端电连接，用于储能电能；
所述驱动子电路111用于在其控制端的电位的控制下，生成驱动电流。
如图13所示，在图11所示的至少一实施例的基础上，所述幅度控制子电路可以包括数据写入子电路121和储能子电路122；
所述数据写入子电路121分别与扫描线GT、数据线DA和所述驱动子电路111的控制端电连接，所述数据写入子电路121用于在所述扫描线GT提供的扫描信号的控制下，将所述数据线DA提供的数据的电压写入所述驱动子电路111的控制端；
所述储能子电路122分别与所述驱动子电路111的控制端和第一公共电极端VM1电连接，用于储存电能；
所述驱动子电路111用于在其控制端的电位的控制下，生成驱动电流。
如图14所示，在图13所示的至少一实施例的基础上，所述幅度控制子电路还可以包括第二通断控制子电路141；
所述第二通断控制子电路分别与发光控制端EM、第二电压端V2和所述驱动子电路111的第一端电连接，用于在所述发光控制端EM提供的发光控制信号的控制下，控制所述第二电压端V2与所述驱动子电路111的第一端之间连通。
如图15所示，在图1所示的至少一实施例的基础上，将发光元件10替换为图11所示的发光电路的至少一实施例；
所述发光控制电路11与所述第一通断控制子电路112的控制端电连接。
如图16所示，在图2所示的至少一实施例的基础上，将发光元件10替换为图11所示的发光电路的至少一实施例；
所述发光控制电路11与所述第一通断控制子电路112的控制端电连接。
如图17所示，在图5所示的至少一实施例的基础上，将微型发光二极管M1替换为图11所示的发光电路的至少一实施例；
所述发光控制晶体管TE的源极与所述第一通断控制子电路112的控制端电连接。
本公开如图17所示的像素电路的至少一实施例在工作时，显示周期包括先后设置的第一写入阶段、第二写入阶段和发光阶段；
在第一写入阶段，G1提供高电压信号，D1提供第一数据电压Vdata1，TW1打开，以将Vdata1写入S1的输入端；
在第二写入阶段，G2提供高电压信号，D1提供第二数据电压Vdata2，TW2打开，以将Vdata2写入S2的输入端；
当Vdata1为低电压信号，Vdata2为低电压信号时，S1输出高电压信号，S2输出高电压信号，TC1导通，TC2关断，S3的输入端接入高电压信号，第一开关控制端A接入低电压信号，第二开关控制端B接入高电压信号，第三开关控制端C的电位和第四开关控制端D的电位为低电压，TK1关断，TK2打开，TK3和TK4关断，I1接入第二发光控制电压；在发光阶段，TE打开，TE的漏极接入第二发光控制电压；
当Vdata1为低电压信号，Vdata2为高电压信号时，S1输出高电压信号，S2输出低电压信号，TC1导通，TC2关断，S3的输入端接入低电压信号，第一开关控制端A接入高电压信号，第二开关控制端B接入低电压信号，第三开关控制端C的电位和第四开关控制端D的电位为低电压，TK1打开，TK2关断，TK3和TK4关断，I1接入第一发光控制电压；在发光阶段，TE打开，TE的漏极接入第一发光控制电压；
当Vdata1为高电压信号，Vdata2为低电压信号时，S1输出低电压信号，S2输出高电压信号，TC1关断，TC2导通，S4的输入端接入低电压信号，第三开关控制端C接入高电压信号，第四开关控制端D接入低电压信号，第一开关控制端A的电位和第二开关控制端B的电位为低电压，TK3打开，TK4关断，TK1和TK2关断，I1接入第三发光控制电压；在发光阶段，TE打开，TE的漏极接入第三发光控制电压；
当Vdata1为高电压信号，Vdata2为高电压信号时，S1输出低电压信号，S2输出低电压信号，TC1关断，TC2导通，S4的输入端接入高电压信号，第三开关控制端C接入低电压信号，第四开关控制端D接入高电压信号，第一开关控制端A的电位和第二开关控制端B的电位为低电压，TK4打开，TK3关断，TK1和TK2关断，I1接入第四发光控制电压；在发光阶段，TE打开，TE的漏极接入第四发光控制电压。
本公开如图17所示的像素电路的至少一实施例在工作时，第一发光控制电压、第二发光控制电压、第三发光控制电压和第四发光控制电压可以都为方波电压信号，第一发光控制电压的占空比、第二发光控制电压的占空比、第三发光控制电压的占空比和第四发光控制电压的占空比不同，从而可以控制所述所述第一通断控制子电路的导通时间不同，使得发光元件的发光时长 不同，进而可以实现不同灰阶值的低灰阶显示，并能够提升低灰阶显示均一性。如图18所示，在图9所示的至少一实施例的基础上，将微型发光二极管M1替换为图11所示的发光电路的至少一实施例；
所述发光控制晶体管TE的源极与所述第一通断控制子电路112的控制端电连接。
本公开图18所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的第一写入阶段、第二写入阶段、第三写入阶段、第四写入阶段和发光阶段；
在第一写入阶段，G1提供高电压信号，G2、G3和G4都提供低电压信号，D1提供第一数据电压Vdata1至第一数据接入端DI1；
在第二写入阶段，G2提供高电压信号，G1、G3和G4都提供低电压信号，D2提供第二数据电压Vdata2至第二数据接入端DI2；
在第三写入阶段，G3提供高电压信号，G1、G2和G4都提供低电压信号，D3提供第三数据电压Vdata3至第三数据接入端DI3；
在第四写入阶段，G4提供高电压信号，G1、G2和G3都提供低电压信号，D4提供第四数据电压Vdata4至第四数据接入端DI4；
当Vdata1为低电压信号，Vdata2为低电压信号，Vdata3为低电压信号，Vdata4为低电压信号时，K1的栅极接入高电压信号，K2的栅极接入低电压信号，K1导通，K2关断，S3的输入端接入高电压信号，S3输出低电压信号，K3关断，K4打开，S7的输入端接入低电压信号，S7输出高电压信号至第四开关控制端D；在发光阶段，TK4导通，TE导通，TE的漏极接入第四发光控制电压；
当Vdata1为高电压信号，Vdata2为低电压信号，Vata3为低电压信号，Vdata4为低电压信号时，S1输出低电压信号，K1关断，S2输出高电压信号，K2导通，S4的输入端接入低电压信号，K5的控制端接入高电压信号，K5导通，K6关断，S9的输入端接入低电压信号，S9输出高电压信号，并通过K5将高电压信号提供至第五开关控制端E；在发光阶段，TK5导通，TE导通，TE的漏极接入第五发光控制电压；
当Vdata1为低电压信号，Vdata2为高电压信号，Vdata3为低电压信号， Vdata4为低电压信号时，S1输出高电压信号，K1导通，K2关断，S2输出低电压信号，S3的输入端接入低电压信号，S3输出高电压信号，K3导通，K4关断，S6输出高电压信号，S6通过导通的K3将高电压信号提供至第一开关控制端A；在发光阶段，TK1导通，TE导通，TE的漏极接入第一发光控制电压；
当Vdata1为低电压信号，Vdata2为低电压信号，Vdata3为高电压信号，Vdata4为低电压信号时，S1输出高电压信号，S2提供高电压信号，K1导通，K2关断，S3的输入端接入高电压信号，S3输出低电压信号，K3关断，K4导通，S7的输入端接入高电压信号，将高电压信号写入第三开关控制端C；在发光阶段，TK3导通，TE导通，TE的漏极接入第三发光控制电压；
当Vdata1为低电压信号，Vdata2为低电压信号，Vdata3为低电压信号，Vdata4为高电压信号时，S1输出高电压信号，S2输出高电压信号，K1导通，K2关断，S3的输入端接入高电压信号，S3输出低电压信号，K3关断，K4导通，S6的输入端接入低电压信号，S7的输入端接入低电压信号，S7输出高电压信号至第四开关控制端D；在发光阶段，TK4导通，TE导通，TE的漏极接入第四发光控制电压；
当Vdata1为高电压信号，Vdata2为高电压信号，Vdata3为低电压信号，Vdata4为低电压信号时，S1输出低电压信号，S2输出低电压信号，K1关断，K2导通，S4的输入端接入高电压信号，S4输出低电压信号，K7关断，K8导通，S9的输入端接入低电压信号，S10的输入端接入低电压信号，S10输出高电压信号至第八开关控制端H；在发光阶段，TK8导通，TE导通，TE的漏极接入第八发光控制电压；
当Vdata1为高电压信号，Vdata2为高电压信号，Vdata3为低电压信号，Vdata4为高电压信号时，S1输出低电压信号，S2输出低电压信号，K1关断，K2导通，S4的输入端接入高电压信号，S4输出低电压信号，K7关断，K8导通，S9的输入端接入高电压信号，S10的输入端接入高电压信号，S10输出低电压信号，以将高电压信号写入第七开关控制端G；在发光阶段，TK7导通，TE导通，TE的漏极接入第七发光控制电压；
当Vdata1为高电压信号，Vdata2为高电压信号，Vdata3为高电压信号， Vdata4为低电压信号时，S1输出低电压信号，S2输出低电压信号，K1关断，K2导通；S4的输入端接入高电压信号，S4输出低电压信号，K7关断，K8导通，S9的输入端接入低电压信号，S9输出高电压信号，S10的输入端接入低电压信号，S10输出高电压信号至第八开关控制端H；在发光阶段，TK8导通，TE导通，TE的漏极接入第八发光控制电压；
当Vdata1为高电压信号，Vdata2为高电压信号，Vdata3为高电压信号，Vdata4为高电压信号时，S1输出低电压信号，S2输出低电压信号，K1关断，K2导通，S4的输入端接入高电压信号，S4输出低电压信号，K7关断，K8导通，S9的输入端接入高电压信号，S9输出低电压信号，S10的输入端接入高电压信号，S10输出低电压信号，以将高电压信号提供至第七开关控制端G；在发光阶段，TK7导通，TE导通，TE的漏极接入第七发光控制电压；
当Vdata1为高电压信号，Vdata2为低电压信号，Vdata3为高电压信号，Vdata4为高电压信号时，S1输出低电压信号，S2输出高电压信号，K1关断，K2导通，S4的输入端接入低电压信号，S4输出高电压信号，K7导通，K8关断，S9的输入端接入高电压信号，S9输出低电压信号至S8的输入端，S8输出高电压信号至第六开关控制端F；在发光阶段，TK6导通，TE导通，TE的漏极接入第六发光控制电压；
当Vdata1为高电压信号，Vdata2为低电压信号，Vdata3为低电压信号，Vdata4为高电压信号时，S1输出低电压信号，S2提供高电压信号，K1关断，K2导通，S4的输入端接入低电压信号，S4输出高电压信号，K7导通，K8关断，S9的输入端接入高电压信号，S9输出低电压信号至S8的输入端，S8输出高电压信号至第六开关控制端F；在发光阶段，TK6导通，TE导通，TE的漏极接入第六发光控制电压；
当Vdata1为高电压信号，Vdata2为低电压信号，Vdata3为高电压信号，Vdata4为低电压信号时，S1输出低电压信号，S2提供高电压信号，K1关断，K2导通，S4的输入端接入低电压信号，S4输出高电压信号，K7导通，K8关断，S9的输入端接入低电压信号，S9输出高电压信号至S8的输入端，S8输出低电压信号，S9输出高电压信号至第五开关控制端E；在发光阶段，TK5导通，TE导通，TE的漏极接入第五发光控制电压；
当Vdata1为低电压信号，Vdata2为高电压信号，Vdata3为高电压信号，Vdata4为高电压信号时，S1输出高电压信号，S2输出低电压信号，K1导通，K2关断，S3的输入端接入低电压信号，S3输出高电压信号，K3导通，K4关断，S6的输入端接入高电压信号，S6输出低电压信号，S5的输入端接入低电压信号，S5输出高电压信号至第二开关控制端B；在发光阶段，TK2导通，TE导通，TE的漏极接入第二发光控制电压；
当Vdata1为低电压信号，Vdata2为高电压信号，Vdata3为低电压信号，Vdata4为高电压信号时，S1输出高电压信号，S2输出低电压信号，K1导通，K2关断，S3的输入端接入低电压信号，S3输出高电压信号，K3导通，K4关断，S6的输入端接入低电压信号，S6输出高电压信号至第一开关控制端A；在发光阶段，TK1导通，TE导通，TE的漏极接入第一发光控制电压；
当Vdata1为低电压信号，Vdata2为高电压信号，Vdata3为高电压信号，Vdata4为低电压信号时，S1输出高电压信号，S2输出低电压信号，K1导通，K2关断，S3的输入端接入低电压信号，S3输出高电压信号，K3导通，K4关断，S6的输入端接入高电压信号，S6输出低电压信号至S5的输入端，S5输出高电压信号至第二开关控制端B；在发光阶段，TK2导通，TE导通，TE的漏极接入第二发光控制电压；
当Vdata1为低电压信号，Vdata2为低电压信号，Vdata3为高电压信号，Vdata4为高电压信号时，S1输出高电压信号，S2输出高电压信号，K1导通，K2关断，S3的输入端接入高电压信号，S3输出低电压信号，K3关断，K4导通，S6的输入端接入高电压信号，S7的输入端接入高电压信号，S7输出低电压信号，并将高电压信号提供至第三开关控制端C；在发光阶段，TK3导通，TE导通，TE的漏极接入第三发光控制电压。
本公开如图18所示的像素电路的至少一实施例在工作时，第一发光控制电压、第二发光控制电压、第三发光控制电压、第四发光控制电压、第五发光控制电压、第六发光控制电压、第七发光控制电压和第八发光控制电压可以都为方波电压信号，第一发光控制电压的占空比、第二发光控制电压的占空比、第三发光控制电压的占空比、第四发光控制电压的占空比、第五发光控制电压的占空比、第六发光控制电压的占空比、第七发光控制电压的占空 比和第八发光控制电压的占空比不同，从而可以控制所述所述第一通断控制子电路的导通时间不同，进而可以实现不同灰阶值的低灰阶显示，并能够提升低灰阶显示均一性。
如图19所示，在图17所示的像素电路的至少一实施例的基础上，所述幅度控制子电路可以包括数据写入子电路、储能子电路和复位子电路；
所述数据写入子电路包括第一数据写入晶体管T1；所述储能子电路包括存储电容C1，所述复位子电路包括复位晶体管T3；所述驱动子电路包括驱动晶体管T0；所述第一通断控制电路包括第一通断控制晶体管T4；发光元件为微型发光二极管M1；
TE的源极与T4的栅极电连接；
T1的栅极与扫描线GT电连接，T1的漏极与数据线DA电连接，T1的源极与T0的栅极电连接；
T0的漏极与高电压端VDD电连接，T0的源极与T4的漏极电连接，T4的源极与M1的阳极电连接，M1的阴极与低电压端VSS电连接；
C1的第一端与T0的栅极电连接，C1的第二端与T0的源极电连接。
在图19中的至少一实施例中，各晶体管都为n型晶体管，但不以此为限。
本公开如图19所示的像素电路的至少一实施例在工作时，首先GT提供
高电压信号，T1和T3打开，以将DA提供的显示数据电压写入T0的栅极，并将R1提供的复位电压写入T0的源极；之后，EM提供高电压信号，TE打开，第一发光控制电压、第二发光控制电压、第三发光控制电压或第四发光控制电压接入T4的栅极，以控制T4导通或关断，当T4导通时，T0驱动M1发光。如图20所示，在图17所示的像素电路的至少一实施例的基础上，所述幅度控制子电路可以包括数据写入子电路和储能子电路；
所述数据写入子电路包括第一数据写入晶体管T1和第二数据写入晶体管T2；所述储能子电路包括存储电容C1；所述驱动子电路包括驱动晶体管T0；所述第一通断控制电路包括第一通断控制晶体管T4；发光元件为微型发光二极管M1；
TE的源极与T4的栅极电连接；
C1的第一端与T0的栅极电连接，C2的第二端与第一公共电极端VM1 电连接；
T1的栅极与第一扫描线GT1电连接，T1的漏极与数据线DA电连接，T1的源极与T0的栅极电连接；T0的漏极与高电压端VDD电连接；
T2的栅极与第二扫描线GT2电连接，T2的源极与数据线DA电连接，T2的漏极与T0的栅极电连接；
T0的源极与T4的漏极电连接，T4的源极与M1的阳极电连接，M1的阴极与低电压端VSS电连接。
在图20所示的至少一实施例中，T1为n型晶体管，T2为p型晶体管，以扩大能够写入T0的栅极的所述数据线DA提供的显示数据电压的电压范围。
在图20所示的至少一实施例中，T0和T4为n型晶体管。
本公开如图20所示的像素电路的至少一实施例在工作时，首先GT1提供高电压信号或GT2提供低电压信号，T1或T2打开，以将DA提供的显示数据电压写入T0的栅极；之后，EM提供高电压信号，TE打开，第一发光控制电压、第二发光控制电压、第三发光控制电压或第四发光控制电压接入T4的栅极，以控制T4导通或关断，当T4导通时，T0驱动M1发光。
如图21所示，在图18所示的像素电路的至少一实施例的基础上，所述幅度控制子电路可以包括数据写入子电路、储能子电路和复位子电路；
所述数据写入子电路包括第一数据写入晶体管T1；所述储能子电路包括存储电容C1，所述复位子电路包括复位晶体管T3；所述驱动子电路包括驱动晶体管T0；所述第一通断控制电路包括第一通断控制晶体管T4；发光元件为微型发光二极管M1；
TE的源极与T4的栅极电连接；
T1的栅极与扫描线GT电连接，T1的漏极与数据线DA电连接，T1的源极与T0的栅极电连接；
T0的漏极与高电压端VDD电连接，T0的源极与T4的漏极电连接，T4的源极与M1的阳极电连接，M1的阴极与低电压端VSS电连接；
C1的第一端与T0的栅极电连接，C1的第二端与T0的源极电连接。
在图21中的至少一实施例中，各晶体管都为n型晶体管，但不以此为限。
本公开如图21所示的像素电路的至少一实施例在工作时，首先GT提供 高电压信号，T1和T3打开，以将DA提供的显示数据电压写入T0的栅极，并将R1提供的复位电压写入T0的源极；之后，EM提供高电压信号，TE打开，第一发光控制电压、第二发光控制电压、第三发光控制电压、第四发光控制电压、第五发光控制电压、第六发光控制电压、第七发光控制电压或第八发光控制电压接入T4的栅极，以控制T4导通或关断，当T4导通时，T0驱动M1发光。
如图22所示，在图18所示的像素电路的至少一实施例的基础上，所述幅度控制子电路可以包括数据写入子电路和储能子电路；
所述数据写入子电路包括第一数据写入晶体管T1和第二数据写入晶体管T2；所述储能子电路包括存储电容C1；所述驱动子电路包括驱动晶体管T0；所述第一通断控制电路包括第一通断控制晶体管T4；发光元件为微型发光二极管M1；
TE的源极与T4的栅极电连接；
C1的第一端与T0的栅极电连接，C2的第二端与第一公共电极端VM1电连接；
T1的栅极与第一扫描线GT1电连接，T1的漏极与数据线DA电连接，T1的源极与T0的栅极电连接；T0的漏极与高电压端VDD电连接；
T2的栅极与第二扫描线GT2电连接，T2的源极与数据线DA电连接，T2的漏极与T0的栅极电连接；
T0的源极与T4的漏极电连接，T4的源极与M1的阳极电连接，M1的阴极与低电压端VSS电连接。
在图22所示的至少一实施例中，T1为n型晶体管，T2为p型晶体管，以扩大能够写入T0的栅极的所述数据线DA提供的显示数据电压的电压范围。
在图22所示的至少一实施例中，T0和T4为n型晶体管。
本公开如图22所示的像素电路的至少一实施例在工作时，首先GT1提供高电压信号或GT2提供低电压信号，T1或T2打开，以将DA提供的显示数据电压写入T0的栅极；之后，EM提供高电压信号，TE打开，第一发光控制电压、第二发光控制电压、第三发光控制电压、第四发光控制电压、第五发光控制电压、第六发光控制电压、第七发光控制电压或第八发光控制电 压接入T4的栅极，以控制T4导通或关断，当T4导通时，T0驱动M1发光。
本公开实施例所述的显示装置包括显示面板；所述显示面板的显示区域具有多个亚像素，每个亚像素内设置有上述的像素电路。
可选的，所述显示面板包括硅基板；所述像素电路设置于所述硅基板上。此时，所述像素电路包括的晶体管可以为CMOS(Complementary Metal Oxide Semiconductor指互补金属氧化物)晶体管。
在本公开至少一实施例中，显示面板包括的衬底可以为半导体衬底，诸如以硅或碳化硅等为材料的单晶半导体衬底或多晶半导体衬底、硅锗等的化合物半导体衬底、SOI(Silicon On Insulator，绝缘体上硅)衬底等中的任一种。所述衬底还可以包括诸如环氧树脂、三嗪、硅树脂或聚酰亚胺的有机树脂材料。在一些示例实施例中，衬底可以是FR4类型印刷电路板(PCB)，或者可以是易于变形的柔性PCB。在一些示例实施例中，衬底可以包括诸如氮化硅、AlN(氮化铝)或Al2O3(三氧化二铝)的陶瓷材料，或者金属或金属化合物，或者金属芯印刷电路板(MCPCB)或金属覆铜层压板(MCCL)中的任一种。
在本公开至少一实施例中，所述显示装置可以为硅基显示装置，所述显示装置中的显示面板包括硅基板，所述显示面板中的像素电路可以为硅基场效应管，所述硅基板可以包括硅元素，例如多晶硅或单晶硅。
在一些实施例中，硅基场效应管也可以称之为硅基晶体管，硅基场效应管包括硅基底、薄膜微桥和至少一个薄膜晶体管；其中，硅基底包括至少一个微腔，每一微腔使得位于该微腔上的薄膜微桥悬空；薄膜微桥设置在硅基底上方，薄膜晶体管设置在每一个薄膜微桥的中心区域上方。硅基晶体管相较于玻璃基的薄膜晶体管具有以下优点：
一、硅基晶体管的尺寸为几十纳米～几百纳米，玻璃基的薄膜晶体管尺寸为几微米～几十微米，硅基晶体管的体积小。
二、硅基晶体管的导通时间为几十皮秒(picosecond)，玻璃基的薄膜晶体管导通时间是几十至几百纳秒(nanosecond)之间，硅基晶体管导通时间较快。
三、硅基晶体管的稳定性高于玻璃基上制备的晶体管，玻璃基晶体管组成的像素驱动电路不需要进行对阈值电压进行补偿。
本公开实施例所提供的显示装置可以为手表、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (24)

  1. 一种像素电路，包括发光电路、发光控制电路、第一控制电路和开关控制电路；
    所述发光控制电路分别与发光控制端、控制电压输入端和所述发光电路电连接，用于在所述发光控制端提供的发光控制信号的控制下，控制所述控制电压输入端与所述发光电路之间连通；
    所述发光电路用于根据所述控制电压输入端提供的控制电压发光；
    所述第一控制电路分别与至少两个数据电压端、至少两个扫描端和N个开关控制端电连接，用于在所述扫描端提供的扫描信号的控制下，根据所述数据电压端提供的数据电压，控制提供至所述开关控制端的开关控制信号；N为大于1的整数；
    所述开关控制电路包括N个开关控制端、N个发光控制电压端和N个开关控制子电路；n为小于等于N的正整数；
    第n开关控制子电路分别与第n开关控制端、第n发光控制电压端和所述控制电压输入端电连接，用于在所述第n开关控制端提供的第n开关控制信号的控制下，控制所述第n发光控制电压端与所述控制电压输入端之间连通。
  2. 如权利要求1所述的像素电路，其中，所述发光控制电压端提供的发光控制电压为直流电压，所述N个发光控制电压端提供的发光控制电压互不相同。
  3. 如权利要求1所述的像素电路，其中，所述发光控制电压端提供的发光控制电压为方波电压信号，N个发光控制电压端提供的发光控制电压的占空比互不相同。
  4. 如权利要求1所述的像素电路，其中，N等于2 a，a为正整数。
  5. 如权利要求1所述的像素电路，其中，所述第一控制电路包括第一数据写入电路、第二数据写入电路和第一控制子电路；
    所述第一数据写入电路分别与第一扫描端、第一数据电压端和第一数据接入端电连接，用于在所述第一扫描端提供的第一扫描信号的控制下，将所 述第一数据电压端提供的第一数据电压写入所述第一数据接入端；
    所述第二数据写入电路分别与第二扫描端、第二数据电压端和第二数据接入端电连接，用于在所述第二扫描端提供的第二扫描信号的控制下，将所述第二数据电压端提供的第二数据电压写入所述第二数据接入端；
    所述第一控制子电路分别与所述第一数据接入端、所述第二数据接入端和N个开关控制端电连接，用于根据所述第一数据接入端的电位和所述第二数据接入端的电位，控制向所述N个开关控制端分别提供相应的开关控制信号。
  6. 如权利要求5所述的像素电路，其中，所述第一控制子电路包括第一锁存器、第二锁存器、第三锁存器、第四锁存器、第一控制开关和第二控制开关；N等于4；
    所述第一锁存器的输入端与所述第一数据接入端电连接，所述第一锁存器的输出端与所述第一控制开关的控制端电连接，所述第一锁存器用于锁存所述第一数据接入端接入的电压信号，并输出第一输出电压，所述第一输出电压与所述第一数据接入端接入的电压信号反相；
    所述第二锁存器的输入端与所述第二数据接入端电连接，所述第二锁存器的输出端与所述第二控制开关的控制端电连接，所述第二锁存器用于锁存所述第二数据接入端接入的电压信号，并输出第二输出电压，所述第二输出电压与所述第二数据接入端接入的电压信号反相；
    所述第三锁存器的输入端与所述第一控制开关的第一端电连接，所述第三锁存器的输出端与第一开关控制端电连接，所述第三锁存器用于锁存其输入端接入的电压信号，并输出第三输出电压，所述第三输出电压与所述第三锁存器的输入端接入的电压信号反相；
    所述第四锁存器的输入端与所述第二控制开关的第一端电连接，所述第四锁存器的输出端与第三开关控制端电连接，所述第四锁存器用于锁存其输入端接入的电压信号，并输出第四输出电压，所述第四输出电压与所述第四锁存器的输入端接入的电压信号反相；
    所述第一控制开关的控制端与所述第一锁存器的输出端电连接，所述第一控制开关的第二端与所述第二锁存器的输出端的电连接，所述第一控制开 关用于在其控制端的电位的控制下，控制所述第一控制开关的第一端与所述第一控制开关的第二端之间连通或断开；
    所述第二控制开关的控制端与所述第一锁存器的输入端电连接，所述第二控制开关的第二端与所述第二锁存器的输入端的电连接，所述第二控制开关用于在其控制端的电位的控制下，控制所述第二控制开关的第一端与所述第二控制开关的第二端之间连通或断开；
    第一开关控制端与所述第三锁存器的输出端电连接，第二开关控制端与所述第三锁存器的输入端电连接；
    第三开关控制端与所述第四锁存器的输出端电连接，第四开关控制端与所述第四锁存器的输入端电连接。
  7. 如权利要求6所述的像素电路，其中，所述第一锁存器包括第一反相器和第二反相器；
    所述第一反相器的输入端与所述第一锁存器的输入端电连接，所述第一反相器的输出端与所述第一锁存器的输出端电连接；
    所述第二反相器的输入端与所述第一反相器的输出端电连接，所述第二反相器的输出端与所述第一反相器的输入端电连接；
    所述第二锁存器包括第三反相器和第四反相器；
    所述第三反相器的输入端与所述第二锁存器的输入端电连接，所述第三反相器的输出端与所述第二锁存器的输出端电连接；
    所述第四反相器的输入端与所述第三反相器的输出端电连接，所述第四反相器的输出端与所述第三反相器的输入端电连接；
    所述第三锁存器包括第五反相器和第六反相器；
    所述第五反相器的输入端与所述第三锁存器的输入端电连接，所述第五反相器的输出端与所述第三锁存器的输出端电连接；
    所述第六反相器的输入端与所述第五反相器的输出端电连接，所述第六反相器的输出端与所述第五反相器的输入端电连接；
    所述第四锁存器包括第七反相器和第八反相器；
    所述第七反相器的输入端与所述第四锁存器的输入端电连接，所述第七反相器的输出端与所述第四锁存器的输出端电连接；
    所述第八反相器的输入端与所述第七反相器的输出端电连接，所述第八反相器的输出端与所述第七反相器的输入端电连接。
  8. 如权利要求6所述的像素电路，其中，所述第一控制开关为第一控制晶体管，所述第二控制开关为第二控制晶体管；
    所述第一控制晶体管的控制极与所述第一锁存器的输出端电连接，所述第一控制晶体管的第一极与所述第三锁存器的输入端电连接，所述第一控制晶体管的第二极与所述第二锁存器的输出端的电连接；
    所述第二控制晶体管的控制极与所述第一锁存器的输入端电连接，所述第二控制晶体管的第一极与所述第四锁存器的输入端电连接，所述第二控制晶体管的第二极与所述第二锁存器的输入端的电连接。
  9. 如权利要求5所述的像素电路，其中，所述第一数据写入电路包括第一写入晶体管，所述第二数据写入电路包括第二写入晶体管；
    所述第一写入晶体管的控制极与所述第一扫描端电连接，所述第一写入晶体管的第一极与所述第一数据电压端电连接，所述第一写入晶体管的第二极与所述第一数据接入端电连接；
    所述第二写入晶体管的控制极与所述第二扫描端电连接，所述第二写入晶体管的第一极与所述第二数据电压端电连接，所述第二写入晶体管的第二极与所述第二数据接入端电连接。
  10. 如权利要求1所述的像素电路，其中，所述第一控制电路包括第一数据写入电路、第二数据写入电路、第三数据写入电路、第四数据写入电路和第二控制子电路；
    所述第一数据写入电路分别与第一扫描端、第一数据电压端和第一数据接入端电连接，用于在所述第一扫描端提供的第一扫描信号的控制下，将所述第一数据电压端提供的第一数据电压写入所述第一数据接入端；
    所述第二数据写入电路分别与第二扫描端、第二数据电压端和第二数据接入端电连接，用于在所述第二扫描端提供的第二扫描信号的控制下，将所述第二数据电压端提供的第二数据电压写入所述第二数据接入端；
    所述第三数据写入电路分别与第三扫描端、第三数据电压端和第三数据接入端电连接，用于在所述第三扫描端提供的第三扫描信号的控制下，将所 述第三数据电压端提供的第三数据电压写入所述第三数据接入端；
    所述第四数据写入电路分别与第四扫描端、第四数据电压端和第四数据接入端电连接，用于在所述第四扫描端提供的第四扫描信号的控制下，将所述第四数据电压端提供的第四数据电压写入所述第四数据接入端；
    所述第二控制子电路分别与所述第一数据接入端、所述第二数据接入端、所述第三数据接入端、所述第四数据接入端和N个开关控制端电连接，用于根据所述第一数据接入端的电位、所述第二数据接入端的电位、所述第三数据接入端的电位和所述第四数据接入端的电位，控制向所述N个开关控制端分别提供相应的开关控制信号。
  11. 如权利要求10所述的像素电路，其中，所述第二控制子电路包括第一锁存器、第二锁存器、第三锁存器、第四锁存器、第五锁存器、第六锁存器、第七锁存器、第八锁存器、第九锁存器、第十锁存器、第一控制开关、第二控制开关、第三控制开关、第四控制开关、第五控制开关和第六控制开关；N等于8；
    所述第一锁存器的输入端与所述第一数据接入端电连接，所述第一锁存器的输出端与所述第一控制开关的控制端电连接，所述第一锁存器用于锁存所述第一数据接入端接入的电压信号，并输出第一输出电压，所述第一输出电压与所述第一数据接入端接入的电压信号反相；
    所述第二锁存器的输入端与所述第二数据接入端电连接，所述第二锁存器的输出端与所述第二控制开关的控制端电连接，所述第二锁存器用于锁存所述第二数据接入端接入的电压信号，并输出第二输出电压，所述第二输出电压与所述第二数据接入端接入的电压信号反相；
    所述第三锁存器的输入端与所述第一控制开关的第一端电连接，所述第三锁存器的输出端与所述第三控制开关的控制端电连接，所述第三锁存器用于锁存其输入端接入的电压信号，并输出第三输出电压，所述第三输出电压与所述第三锁存器的输入端接入的电压信号反相；
    所述第四锁存器的输入端与所述第二控制开关的第一端电连接，所述第四锁存器的输出端与第第五控制开关的控制端电连接，所述第四锁存器用于锁存其输入端接入的电压信号，并输出第四输出电压，所述第四输出电压与 所述第四锁存器的输入端接入的电压信号反相；
    所述第五锁存器的输入端与所述第三控制开关的第一端电连接，所述第五锁存器的输出端与第二开关控制端电连接，所述第五锁存器用于锁存其输入端接入的电压信号，并输出第五输出电压，所述第五输出电压与所述第五锁存器的输入端接入的电压信号反相；
    所述第六锁存器的输入端与所述第三数据接入端电连接，所述第六锁存器的输出端与所述第三控制开关的第二端电连接，所述第六锁存器用于锁存其输入端接入的电压信号，并输出第六输出电压，所述第六输出电压与所述第六锁存器的输入端接入的电压信号反相；
    所述第七锁存器的输入端与所述第四控制开关的第一端电连接，所述第七锁存器的输出端与第四开关控制端电连接，所述第七锁存器用于锁存其输入端接入的电压信号，并输出第七输出电压，所述第七输出电压与所述第七锁存器的输入端接入的电压信号反相；
    所述第八锁存器的输入端与所述第五控制开关的第一端电连接，所述第八锁存器的输出端与第六开关控制端电连接，所述第八锁存器用于锁存其输入端接入的电压信号，并输出第八输出电压，所述第八输出电压与所述第八锁存器的输入端接入的电压信号反相；
    所述第九锁存器的输入端与所述第四数据接入端电连接，所述第九锁存器的输出端与所述第五控制开关的第二端电连接，所述第九锁存器用于锁存其输入端接入的电压信号，并输出第九输出电压，所述第九输出电压与所述第九锁存器的输入端接入的电压信号反相；
    所述第十锁存器的输入端与所述第六控制开关的第一端电连接，所述第十锁存器的输出端与第八开关控制端电连接，所述第十锁存器用于锁存其输入端接入的电压信号，并输出第十输出电压，所述第十输出电压与所述第十锁存器的输入端接入的电压信号反相；
    所述第一控制开关的控制端与所述第一锁存器的输出端电连接，所述第一控制开关的第二端与所述第二锁存器的输出端的电连接，所述第一控制开关用于在其控制端的电位的控制下，控制所述第一控制开关的第一端与所述第一控制开关的第二端之间连通或断开；
    所述第二控制开关的控制端与所述第一锁存器的输入端电连接，所述第二控制开关的第二端与所述第二锁存器的输入端的电连接，所述第二控制开关用于在其控制端的电位的控制下，控制所述第二控制开关的第一端与所述第二控制开关的第二端之间连通或断开；
    所述第三控制开关的控制端与所述第三锁存器的输出端电连接，所述第三控制开关用于在其控制端的电位的控制下，控制所述第五锁存器的输入端与所述第六锁存器的输出端之间连通或断开；
    所述第四控制开关的控制端与所述第三锁存器的输入端电连接，所述第四控制开关用于在其控制端的电位的控制下，控制所述第七锁存器的输入端与所述第六锁存器的输入端之间连通或断开；
    所述第五控制开关的控制端与所述第四锁存器的输出端电连接，所述第五控制开关用于在其控制端的电位的控制下，控制所述第八锁存器的输入端与所述第九锁存器的输出端电连接；
    所述第六控制开关的控制端与所述第四锁存器的输入端电连接，所述第六控制开关用于在其控制端的电位的控制下，控制所述第十锁存器的输入端与所述第九锁存器的输入端之间连通；
    第一开关控制端与第五锁存器的输入端电连接，第七开关控制端与第十锁存器的输入端电连接。
  12. 如权利要求11所述的像素电路，其中，所述第一锁存器包括第一反相器和第二反相器；
    所述第一反相器的输入端与所述第一锁存器的输入端电连接，所述第一反相器的输出端与所述第一锁存器的输出端电连接；
    所述第二反相器的输入端与所述第一反相器的输出端电连接，所述第二反相器的输出端与所述第一反相器的输入端电连接；
    所述第二锁存器包括第三反相器和第四反相器；
    所述第三反相器的输入端与所述第二锁存器的输入端电连接，所述第三反相器的输出端与所述第二锁存器的输出端电连接；
    所述第四反相器的输入端与所述第三反相器的输出端电连接，所述第四反相器的输出端与所述第三反相器的输入端电连接；
    所述第三锁存器包括第五反相器和第六反相器；
    所述第五反相器的输入端与所述第三锁存器的输入端电连接，所述第五反相器的输出端与所述第三锁存器的输出端电连接；
    所述第六反相器的输入端与所述第五反相器的输出端电连接，所述第六反相器的输出端与所述第五反相器的输入端电连接；
    所述第四锁存器包括第七反相器和第八反相器；
    所述第七反相器的输入端与所述第四锁存器的输入端电连接，所述第七反相器的输出端与所述第四锁存器的输出端电连接；
    所述第八反相器的输入端与所述第七反相器的输出端电连接，所述第八反相器的输出端与所述第七反相器的输入端电连接；
    所述第五锁存器包括第九反相器和第十反相器；
    所述第九反相器的输入端与所述第五锁存器的输入端电连接，所述第九反相器的输出端与所述第五锁存器的输出端电连接；
    所述第十反相器的输入端与所述第九反相器的输出端电连接，所述第十反相器的输出端与所述第九反相器的输入端电连接；
    所述第六锁存器包括第十一反相器和第十二反相器；
    所述第十一反相器的输入端与所述第六锁存器的输入端电连接，所述第十一反相器的输出端与所述第六锁存器的输出端电连接；
    所述第十二反相器的输入端与所述第十一反相器的输出端电连接，所述第十二反相器的输出端与所述第十一反相器的输入端电连接；
    所述第七锁存器包括第十三反相器和第十四反相器；
    所述第十三反相器的输入端与所述第七锁存器的输入端电连接，所述第十三反相器的输出端与所述第七锁存器的输出端电连接；
    所述第十四反相器的输入端与所述第十三反相器的输出端电连接，所述第十四反相器的输出端与所述第十三反相器的输入端电连接；
    所述第八锁存器包括第十五反相器和第十六反相器；
    所述第十五反相器的输入端与所述第八锁存器的输入端电连接，所述第十五反相器的输出端与所述第八锁存器的输出端电连接；
    所述第十六反相器的输入端与所述第十五反相器的输出端电连接，所述 第十六反相器的输出端与所述第十五反相器的输入端电连接；
    所述第九锁存器包括第十七反相器和第十八反相器；
    所述第十七反相器的输入端与所述第九锁存器的输入端电连接，所述第十七反相器的输出端与所述第九锁存器的输出端电连接；
    所述第十八反相器的输入端与所述第十七反相器的输出端电连接，所述第十八反相器的输出端与所述第十七反相器的输入端电连接；
    所述第十锁存器包括第十九反相器和第二十反相器；
    所述第十九反相器的输入端与所述第十锁存器的输入端电连接，所述第十九反相器的输出端与所述第十锁存器的输出端电连接；
    所述第二十反相器的输入端与所述第十九反相器的输出端电连接，所述第二十反相器的输出端与所述第十九反相器的输入端电连接。
  13. 如权利要求11所述的像素电路，其中，所述第一控制开关为第一控制晶体管，所述第二控制开关为第二控制晶体管；所述第三控制开关为第三控制晶体管，所述第四控制开关为第四控制晶体管；第五控制开关为第五控制晶体管，所述第六控制开关为第六控制晶体管；
    所述第一控制晶体管的控制极与所述第一锁存器的输出端电连接，所述第一控制晶体管的第一极与所述第三锁存器的输入端电连接，所述第一控制晶体管的第二极与所述第二锁存器的输出端的电连接；
    所述第二控制晶体管的控制极与所述第一锁存器的输入端电连接，所述第二控制晶体管的第一极与所述第四锁存器的输入端电连接，所述第二控制晶体管的第二极与所述第二锁存器的输入端的电连接；
    所述第三控制晶体管的控制极与所述第三锁存器的输出端电连接，所述第三控制晶体管的第一极与所述第五锁存器的输入端电连接，所述第三控制晶体管的第二极与所述第六锁存器的输出端电连接；
    所述第四控制晶体管的控制极与所述第三锁存器的输入端电连接，所述第四控制晶体管的第一极与第七锁存器的输入端电连接，所述第四控制晶体管的第二极与所述第六锁存器的输入端电连接；
    所述第五控制晶体管的控制极与所述第四锁存器的输出端电连接，所述第五控制晶体管的第一极与所述第八锁存器的输入端电连接，所述第五控制 晶体管的第二极与所述第九锁存器的输出端电连接；
    所述第六控制晶体管的控制极与所述第四锁存器的输入端电连接，所述第六控制晶体管的第一极与所述第十锁存器的输入端电连接，所述第六控制晶体管的第二极与所述第九锁存器的输入端电连接。
  14. 如权利要求10所述的像素电路，其中，所述第一数据写入电路包括第一写入晶体管，所述第二数据写入电路包括第二写入晶体管，所述第三数据写入电路包括第三写入晶体管，所述第四数据写入电路包括第四写入晶体管；
    所述第一写入晶体管的控制极与所述第一扫描端电连接，所述第一写入晶体管的第一极与所述第一数据电压端电连接，所述第一写入晶体管的第二极与所述第一数据接入端电连接；
    所述第二写入晶体管的控制极与所述第二扫描端电连接，所述第二写入晶体管的第一极与所述第二数据电压端电连接，所述第二写入晶体管的第二极与所述第二数据接入端电连接；
    所述第三写入晶体管的控制极与所述第三扫描端电连接，所述第三写入晶体管的第一极与所述第三数据电压端电连接，所述第三写入晶体管的第二极与所述第三数据接入端电连接；
    所述第四写入晶体管的控制极与所述第四扫描端电连接，所述第四写入晶体管的第一极与所述第四数据电压端电连接，所述第四写入晶体管的第二极与所述第四数据接入端电连接。
  15. 如权利要求1至14中任一权利要求所述的像素电路，其中，所述发光电路包括发光元件；
    所述发光控制电路与所述发光元件的第一极电连接，用于在所述发光控制信号的控制下，控制所述控制电压输入端与所述发光元件的第一极之间连通；
    所述发光元件的第二极与第一电压端电连接。
  16. 如权利要求1至14中任一权利要求所述的像素电路，其中，所述发光电路包括幅度控制子电路、驱动子电路、第一通断控制子电路和发光元件；所述驱动子电路的第一端与第二电压端电连接；
    所述幅度控制子电路用于根据显示数据电压，控制所述驱动子电路生成的驱动电流；
    所述发光控制电路用于在所述发光控制信号的控制下，控制所述控制电压输入端与所述第一通断控制子电路的控制端之间连通；
    所述第一通断控制子电路的控制端与所述发光控制电路电连接，所述第一通断控制子电路的第一端与所述驱动子电路的第二端电连接，所述第一通断控制子电路的第二端与所述发光元件电连接；所述第一通断控制子电路用于在其控制端的电位的控制下，控制所述驱动子电路与所述发光元件之间连通。
  17. 如权利要求16所述的像素电路，其中，所述幅度控制子电路包括数据写入子电路、储能子电路和复位子电路；
    所述数据写入子电路分别与第一扫描线、数据线和所述驱动子电路的控制端电连接，用于在所述第一扫描线提供的第一扫描信号的控制下，将所述数据线提供的数据电压写入所述驱动子电路的控制端；
    所述复位子电路分别与第一扫描线、复位电压端和所述驱动子电路的第二端电连接，用于在所述第一扫描信号的控制下，控制将所述复位电压端提供的复位电压写入所述驱动子电路的第二端；
    所述储能子电路分别与所述驱动子电路的控制端和所述驱动子电路的第二端电连接，用于储能电能；
    所述驱动子电路用于在其控制端的电位的控制下，生成驱动电流。
  18. 如权利要求16所述的像素电路，其中，所述幅度控制子电路包括数据写入子电路和储能子电路；
    所述数据写入子电路分别与扫描线、数据线和所述驱动子电路的控制端电连接，所述数据写入子电路用于在所述扫描线提供的扫描信号的控制下，将所述数据线提供的数据的电压写入所述驱动子电路的控制端；
    所述储能子电路分别与所述驱动子电路的控制端和第一公共电极端电连接，用于储存电能；
    所述驱动子电路用于在其控制端的电位的控制下，生成驱动电流。
  19. 如权利要求18所述的像素电路，其中，所述扫描线包括第二扫描线 和第三扫描线；
    所述数据写入子电路包括第一数据写入晶体管和第二数据写入晶体管；
    所述第一数据写入晶体管的控制极与所述第二扫描线电连接，所述第一数据写入晶体管的第一极与所述数据线电连接，所述第一数据写入晶体管的第二极与所述驱动子电路的控制端电连接；
    所述第二数据写入晶体管的控制极与所述第三扫描线电连接，所述第二数据写入晶体管的第一极与所述数据线电连接，所述第二数据写入晶体管的第二极与所述驱动子电路的控制端电连接；
    所述第一数据写入晶体管为n型晶体管，所述第二数据写入晶体管为p型晶体管。
  20. 如权利要求1至14中任一权利要求所述的像素电路，其中，第n开关控制子电路包括第n开关控制晶体管；
    第n开关控制晶体管的控制极与第n开关控制端电连接，所述第n开关控制晶体管的第一极与第n发光控制电压端电连接，所述第n开关控制晶体管的第二极与所述控制电压输入端电连接。
  21. 如权利要求1至14中任一权利要求所述的像素电路，其中，所述发光控制电路包括发光控制晶体管；
    所述发光控制晶体管的控制极与所述发光控制端电连接，所述发光控制晶体管的第一极与所述控制电压输入端电连接，所述发光控制晶体管的第二极与所述发光电路电连接。
  22. 如权利要求1至14中任一权利要求所述的像素电路，其中，所述发光电路包括的发光元件为微型发光二极管或次毫米发光二极管；所述发光元件的第一极为阳极，所述发光元件的第二极为阴极。
  23. 一种显示装置，包括显示面板；
    所述显示面板的显示区域具有多个亚像素，每个亚像素内设置有如权利要求1至22中任一权利要求所述的像素电路。
  24. 如权利要求23所述的显示装置，其中，所述显示面板包括硅基板；
    所述像素电路设置于所述硅基板上。
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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105390086A (zh) * 2015-12-17 2016-03-09 武汉华星光电技术有限公司 栅极驱动电路和使用栅极驱动电路的显示器
CN109473079A (zh) * 2019-01-16 2019-03-15 京东方科技集团股份有限公司 像素电路、驱动方法与显示模组及其驱动方法
CN110021262A (zh) * 2018-07-04 2019-07-16 京东方科技集团股份有限公司 像素电路及其驱动方法、像素单元、显示面板
US20190228725A1 (en) * 2018-01-23 2019-07-25 Seiko Epson Corporation Display driver, electrooptic device, and electronic apparatus
CN210378422U (zh) * 2019-11-27 2020-04-21 京东方科技集团股份有限公司 像素电路和显示装置
CN113781951A (zh) * 2020-06-09 2021-12-10 京东方科技集团股份有限公司 一种显示面板及驱动方法
CN113936599A (zh) * 2021-10-28 2022-01-14 京东方科技集团股份有限公司 像素电路、驱动方法和显示装置
CN114360435A (zh) * 2020-09-28 2022-04-15 京东方科技集团股份有限公司 像素电路、像素驱动方法和显示装置
CN114446225A (zh) * 2022-02-15 2022-05-06 上海天马微电子有限公司 像素电路、显示面板以及显示装置

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105390086A (zh) * 2015-12-17 2016-03-09 武汉华星光电技术有限公司 栅极驱动电路和使用栅极驱动电路的显示器
US20190228725A1 (en) * 2018-01-23 2019-07-25 Seiko Epson Corporation Display driver, electrooptic device, and electronic apparatus
CN110021262A (zh) * 2018-07-04 2019-07-16 京东方科技集团股份有限公司 像素电路及其驱动方法、像素单元、显示面板
CN109473079A (zh) * 2019-01-16 2019-03-15 京东方科技集团股份有限公司 像素电路、驱动方法与显示模组及其驱动方法
CN210378422U (zh) * 2019-11-27 2020-04-21 京东方科技集团股份有限公司 像素电路和显示装置
CN113781951A (zh) * 2020-06-09 2021-12-10 京东方科技集团股份有限公司 一种显示面板及驱动方法
CN114360435A (zh) * 2020-09-28 2022-04-15 京东方科技集团股份有限公司 像素电路、像素驱动方法和显示装置
CN113936599A (zh) * 2021-10-28 2022-01-14 京东方科技集团股份有限公司 像素电路、驱动方法和显示装置
CN114446225A (zh) * 2022-02-15 2022-05-06 上海天马微电子有限公司 像素电路、显示面板以及显示装置

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