WO2024016256A1 - Unité de registre à décalage, circuit d'attaque de grille et procédé d'attaque de grille - Google Patents

Unité de registre à décalage, circuit d'attaque de grille et procédé d'attaque de grille Download PDF

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Publication number
WO2024016256A1
WO2024016256A1 PCT/CN2022/106996 CN2022106996W WO2024016256A1 WO 2024016256 A1 WO2024016256 A1 WO 2024016256A1 CN 2022106996 W CN2022106996 W CN 2022106996W WO 2024016256 A1 WO2024016256 A1 WO 2024016256A1
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WIPO (PCT)
Prior art keywords
node
sensing
circuit
pull
control
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PCT/CN2022/106996
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English (en)
Chinese (zh)
Inventor
冯雪欢
张大成
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京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Priority to PCT/CN2022/106996 priority Critical patent/WO2024016256A1/fr
Publication of WO2024016256A1 publication Critical patent/WO2024016256A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the invention relates to the field of display, and in particular to a shift register unit, a gate driving circuit and a gate driving method.
  • AMOLED Active matrix organic light emitting diode panels
  • OLED organic light-emitting diode
  • AMOLED can emit light by driving a thin film transistor to generate a driving current in a saturated state. This driving current drives the light-emitting device to emit light.
  • an embodiment of the present disclosure provides a shift register unit, which includes:
  • sensing control circuit connected to the first sensing signal input terminal, the second sensing signal input terminal, and the sensing control node, and configured to respond to the control of the effective level signal provided by the first sensing signal input terminal, writing the effective level signal provided by the second sensing signal input terminal to the sensing control node;
  • the first sensing input circuit is connected to the first level supply end, the first clock control signal input end, the sensing control node, and the first pull-up post node, and is configured to respond to the sensing control node. Control of the effective level signal and the effective level signal provided by the first clock control signal input terminal, writing the effective level signal provided by the first level supply terminal to the first pull-up post node ;
  • the first display input circuit is connected to the display signal input terminal, the third power supply terminal and the first pull-up node, and is configured to respond to the control of the effective level signal provided by the display signal input terminal.
  • the provided valid level signal is written to the first pull-up node;
  • a first switch circuit connected in series between the first pull-up node and the first pull-up post node, connected to the switch signal input terminal, and configured to respond to the control of the signal provided by the switch signal input terminal, To control the connection between the first pull-up node and the first pull-up post-node;
  • the first drive output circuit is connected to the first pull-up post node, the first drive clock signal input terminal, and the first drive signal output terminal, and is configured to respond to the effective level of the first pull-up post node.
  • the signal is controlled by writing the signal provided by the first driving clock signal input terminal to the first driving signal output terminal.
  • the first switch circuit includes: a seventy-first transistor
  • the control electrode of the seventy-first transistor is connected to the switch signal input terminal, the first electrode of the seventy-first transistor is connected to the first pull-up node, and the second electrode of the seventy-first transistor is connected to the switch signal input terminal. pole is connected to the first pull-up post node.
  • the first sensing input circuit includes:
  • the sensing input preparation subcircuit is connected to the sensing preparation node, the sensing control node, and the first level supply end, and is configured to respond to the control of the effective level signal provided by the sensing control node.
  • the signal provided by the first level supply terminal is written to the sensing preparation node;
  • a sensing input sub-circuit is connected to the sensing preparation node, the first clock control signal input terminal, and the first pull-up post node, and is configured to respond to the input signal provided by the first clock control signal input terminal.
  • the effective level signal is controlled to write the signal at the sensing preparation node to the first pull-up post node.
  • it also includes:
  • Sensing control anti-leakage circuit the sensing control circuit is connected to the second sensing signal input terminal through the sensing control anti-leakage circuit, the sensing control circuit is connected to the sensing control anti-leakage circuit At the sensing control anti-leakage node, the sensing control anti-leakage node is connected to the sensing preparation node;
  • the sensing control anti-leakage circuit is also connected to a third sensing signal input terminal, and the sensing control anti-leakage circuit is configured to respond to the control of the effective level signal provided by the third sensing signal input terminal so that The sensing control anti-leakage node forms a path with the second sensing signal input terminal, and the control of the non-effective level signal provided by the third sensing signal input terminal causes the sensing control to prevent leakage.
  • the leakage node forms an open circuit with the second sensing signal input terminal.
  • the third sensing signal input terminal is the first sensing signal input terminal.
  • the third sensing signal input terminal is the second sensing signal input terminal.
  • the sensing control anti-leakage circuit includes: a seventy-second transistor
  • the control electrode of the seventy-second transistor is connected to the third sensing signal input terminal, the first electrode of the seventy-second transistor is connected to the second sensing signal input terminal, and the seventy-second transistor is connected to the third sensing signal input terminal.
  • the second electrode of the two transistors is connected to the sensing control anti-leakage node.
  • the first level supply terminal is the third power terminal.
  • it also includes:
  • a first sensing input anti-leakage circuit the sensing input sub-circuit is connected to the sensing preparation node through the first sensing input anti-leakage circuit, the sensing input sub-circuit is connected to the first sensing The input anti-leakage circuit is connected to the first sensing input anti-leakage node;
  • the first sensing input anti-leakage circuit is also connected to the first clock control signal input terminal, and the first sensing input anti-leakage circuit is configured to respond to the effective power provided by the first clock control signal input terminal.
  • the control of the flat signal to form a path between the first sensing input leakage prevention node and the sensing preparation node, and the control of the non-effective level signal provided by the first clock control signal input terminal to An open circuit is formed between the first sensing input leakage prevention node and the sensing preparation node.
  • the first sensing input anti-leakage circuit includes: a seventy-third transistor
  • the control electrode of the seventy-third transistor is connected to the first clock control signal input terminal, the first electrode of the seventy-third transistor is connected to the sensing preparation node, and the control electrode of the seventy-third transistor is connected to the first clock control signal input terminal.
  • the second pole is connected to the first sensing input anti-leakage node.
  • it also includes:
  • Sensing control anti-leakage circuit the sensing control circuit is connected to the second sensing signal input terminal through the sensing control anti-leakage circuit, the sensing control circuit is connected to the sensing control anti-leakage circuit For sensing and controlling anti-leakage nodes;
  • the sensing control leakage prevention circuit is also connected to the first sensing signal input terminal, the sensing control node and a third power supply terminal, and the sensing control leakage prevention circuit is configured to respond to the first sensing signal. control the effective level signal provided by the sensing signal input terminal, write the effective level signal provided by the second sensing signal input terminal to the sensing control anti-leakage node, and respond to the sensing control node The effective level signal is controlled by writing the effective level signal provided by the third power supply terminal to the sensing control anti-leakage node.
  • the sensing control anti-leakage circuit includes: a seventy-fourth transistor and a seventy-fifth transistor;
  • the control electrode of the seventy-fourth transistor is connected to the first sensing signal input terminal, the first electrode of the seventy-fourth transistor is connected to the second sensing signal input terminal, and the seventy-fourth transistor is connected to the second sensing signal input terminal.
  • the second pole of the four transistors is connected to the sensing control anti-leakage node;
  • the control electrode of the seventy-fifth transistor is connected to the sensing control node, the first electrode of the seventy-fifth transistor is connected to the third power supply terminal, and the second electrode of the seventy-fifth transistor is connected to the sensing control node. Connected to the sensing control anti-leakage node.
  • the first level supply terminal is the first clock control signal input terminal
  • the shift register unit also includes:
  • the first sensing input anti-leakage circuit is connected to the sensing preparation node and the third level supply terminal, and is configured to respond to the control of the effective level signal provided by the third level supply terminal, The effective level signal provided by the three-level supply terminal is written to the sensing preparation node.
  • the first sensing input anti-leakage circuit includes: a seventy-sixth transistor
  • the control electrode of the seventy-sixth transistor is connected to the third level supply terminal, the first electrode of the seventy-sixth transistor is connected to the third level supply terminal, and the seventy-sixth transistor The second pole is connected to the sensing ready node.
  • it also includes:
  • the first sensing reset circuit is connected to the second clock control signal input terminal, the second level supply terminal and the first pull-up post node, and is configured to respond to the valid signal provided by the second clock control signal input terminal.
  • the level signal is controlled by writing the non-effective level signal provided by the second level supply terminal to the first pull-up post node.
  • the first sensing reset circuit includes: a seventy-seventh transistor
  • the control electrode of the seventy-seventh transistor is connected to the second clock control signal input terminal, the first electrode of the seventy-seventh transistor is connected to the first pull-up post node, and the seventy-seventh transistor is connected to the second clock control signal input terminal.
  • the second pole of the seven transistors is connected to the second level supply terminal.
  • it also includes:
  • the second drive output circuit is connected to the first pull-up post node, the second drive clock signal input terminal, and the second drive signal output terminal, and is configured to respond to the effective voltage at the first pull-up post node.
  • the control of the flat signal writes the signal provided by the second driving clock signal input terminal to the second driving signal output terminal;
  • the first cascade output circuit is connected to the first pull-up node, the first cascade clock signal input terminal, and the first cascade signal output terminal, and is configured to respond to the effective level signal at the first pull-up node.
  • the control writes the signal provided by the first cascade clock signal input terminal to the first cascade signal output terminal.
  • the shift register unit includes a first sensing reset circuit, the first sensing reset circuit is connected to a second clock control signal input terminal, a second level supply terminal and the first upper
  • the post-pull node connection is configured to write the non-valid level signal provided by the second level supply terminal to the third clock control signal in response to the control of the valid level signal provided by the first clock control signal input terminal.
  • the second level supply terminal is the first cascade signal output terminal.
  • it also includes:
  • the first display reset circuit is connected to the display reset signal input terminal, the second power supply terminal, and the first pull-up node, and is configured to respond to the control of the effective level signal provided by the display reset signal input terminal, and The non-effective level signal provided by the second power terminal is written to the first pull-up node;
  • the first global reset circuit is connected to the global reset signal input terminal, the second power supply terminal and the first pull-up node, and is configured to respond to the control of the effective level signal provided by the global reset signal input terminal.
  • the non-effective level signals provided by the two power terminals are written to the first pull-up node.
  • it also includes:
  • a first pull-down control circuit is connected to the second power terminal, the fifth power terminal, the first pull-up node and the first pull-down node, and is configured to write to the first pull-down node the same as the first pull-down node.
  • a first pull-up noise reduction circuit is connected to the second power terminal, the first pull-up node and the first pull-down node, and is configured to respond to the control of the effective level signal at the first pull-down node.
  • the non-effective level signal provided by the second power supply terminal is written to the first pull-up node;
  • the first cascade output circuit is also connected to the first pull-down node and the second power supply terminal, and is configured to, in response to the control of the effective level signal at the first pull-down node, convert the signal provided by the second power supply terminal to The non-effective level signal is written to the first cascade signal output terminal;
  • the first drive output circuit is also connected to the first pull-down node and the fourth power supply terminal, and the first drive output circuit is further configured to respond to the control of the effective level signal at the first pull-down node.
  • the non-effective level signal provided by the fourth power supply terminal is written to the first drive signal output terminal;
  • the second drive output circuit is also connected to the first pull-down node and the fourth power supply terminal, and the second drive output circuit is further configured to respond to the control of the effective level signal at the first pull-down node.
  • the non-effective level signal provided by the fourth power supply terminal is written to the second drive signal output terminal.
  • the shift register unit includes a first sensing reset circuit, the first sensing reset circuit is connected to a second clock control signal input terminal, a second level supply terminal and the first upper
  • the post-pull node connection is configured to write the non-valid level signal provided by the second level supply terminal to the third clock control signal in response to the control of the valid level signal provided by the first clock control signal input terminal.
  • the shift register unit also includes:
  • a first sensing reset anti-leakage circuit the first sensing reset circuit is connected to the second level supply end through the first sensing reset anti-leakage circuit;
  • the first sensing reset anti-leakage circuit is also connected to the first pull-down node, and the first sensing reset anti-leakage circuit is configured to respond to the control of the effective level signal at the first pull-down node. Forming a path between the first sensing reset circuit and the second level supply terminal, and resetting the first sensing in response to the control of the non-effective level signal at the first pull-down node An open circuit is formed between the circuit and the second level supply terminal.
  • the first sensing reset anti-leakage circuit includes: a seventy-eighth transistor
  • the control electrode of the seventy-eighth transistor is connected to the first pull-down node, the first electrode of the seventy-eighth transistor is connected to the first sensing reset anti-leakage circuit, and the seventy-eighth transistor is connected to the first pull-down node.
  • the second pole of the transistor is connected to the second level supply terminal.
  • it also includes:
  • a first voltage control circuit connected to the third power supply terminal, the first pull-up node, and the first voltage control node.
  • the first voltage control circuit is configured to respond to the control of the effective level signal at the first pull-up node. Write the effective level signal provided by the third power supply terminal to the first voltage control node;
  • the shift register unit further includes: at least one of a first leakage prevention circuit, a second leakage prevention circuit, and a third leakage prevention circuit;
  • the first global reset circuit is connected to the second power terminal through the first anti-leakage circuit, the first global reset circuit and the first anti-leakage circuit are connected to the first anti-leakage node, and the first anti-leakage circuit
  • the leakage node is connected to the first voltage control node
  • the first leakage prevention circuit is connected to the global reset signal input terminal
  • the first leakage prevention circuit is configured to respond to the effective level provided by the global reset signal input terminal.
  • the control of the signal causes a path to be formed between the first anti-leakage node and the second power terminal, and the control of the non-effective level signal provided by the global reset signal input terminal causes the first anti-leakage node to Open circuit with the second power terminal;
  • the first display reset circuit is connected to the second power terminal through the second anti-leakage circuit
  • the first display reset circuit and the second anti-leakage circuit are connected to the second anti-leakage node
  • the second anti-leakage circuit is connected to the second anti-leakage node.
  • the leakage node is connected to the first voltage control node
  • the second leakage prevention circuit is connected to the display reset signal input terminal
  • the second leakage prevention circuit is configured to respond to the effective level provided by the display reset signal input terminal.
  • the control of the signal causes a path to be formed between the second anti-leakage node and the second power terminal, and the control of the non-effective level signal provided by the display reset signal input terminal causes the second anti-leakage node to Open circuit with the second power terminal;
  • the first pull-up noise reduction circuit is connected to the second power terminal through the third anti-leakage circuit, and the first pull-up noise reduction circuit and the third anti-leakage circuit are connected to the third anti-leakage node, so
  • the third anti-leakage node is connected to the first voltage control node
  • the third anti-leakage circuit is connected to the first pull-down node
  • the third anti-leakage circuit is configured to respond to the first pull-down node.
  • the control of the effective level signal causes a path to be formed between the third anti-leakage node and the second power terminal, and in response to the control of the non-effective level signal at the first pull-down node, the third anti-leakage node
  • the leakage node is disconnected from the second power terminal.
  • it also includes:
  • the second sensing input circuit is connected to the first clock control signal input terminal, the sensing preparation node, and the second pull-up post node, and the second sensing input circuit is configured to respond to the first clock control Controlling the effective level signal provided by the signal input terminal, writing the signal at the sensing preparation node to the second pull-up post node;
  • the second display input circuit is connected to the display signal input terminal, the third power supply terminal and the second pull-up node, and is configured to respond to the control of the effective level signal provided by the display signal input terminal.
  • the provided valid level signal is written to the second pull-up node;
  • a second switch circuit connected in series between the second pull-up node and the second pull-up post node, connected to the switch signal input terminal, and configured to respond to the control of the signal provided by the switch signal input terminal, To control the connection between the second pull-up node and the second pull-up post node;
  • the third drive output circuit is connected to the second pull-up post node, the third drive clock signal input terminal, and the third drive signal output terminal, and is configured to respond to the effective level of the second pull-up post node.
  • the signal is controlled by writing the signal provided by the third driving clock signal input terminal to the third driving signal output terminal.
  • the second switch circuit includes: an eighty-first transistor
  • the control electrode of the eighty-first transistor is connected to the switch signal input terminal, the first electrode of the eighty-first transistor is connected to the second pull-up node, and the second electrode of the eighty-first transistor is connected to the switch signal input terminal. pole is connected to the second pull-up post node.
  • the shift register unit includes a first sensing input anti-leakage circuit, and the sensing input sub-circuit is connected to the sensing preparation node through the first sensing input anti-leakage circuit, The sensing input sub-circuit and the first sensing input leakage prevention circuit are connected to the first sensing input leakage prevention node;
  • the first sensing input anti-leakage circuit is also connected to the first clock control signal input terminal, and the first sensing input anti-leakage circuit is configured to respond to the effective power provided by the first clock control signal input terminal.
  • the second sensing input circuit is connected to the first sensing input leakage prevention node to be connected to the sensing preparation node through the first sensing input leakage prevention circuit.
  • it also includes:
  • a second sensing input anti-leakage circuit the second sensing input circuit is connected to the sensing preparation node through the second sensing input anti-leakage circuit, the second sensing input circuit is connected to the second The sensing input anti-leakage circuit is connected to the second sensing input anti-leakage node;
  • the second sensing input anti-leakage circuit is also connected to the first clock control signal input terminal, and the second sensing input anti-leakage circuit is configured to respond to the effective power provided by the first clock control signal input terminal.
  • the control of the flat signal to form a path between the second sensing input anti-leakage node and the sensing preparation node, and the control of the non-effective level signal provided by the first clock control signal input terminal to An open circuit is formed between the second sensing input leakage prevention node and the sensing preparation node.
  • the second sensing input anti-leakage circuit includes: an eighty-third transistor;
  • the control electrode of the eighty-third transistor is connected to the first clock control signal input terminal, the first electrode of the eighty-third transistor is connected to the sensing preparation node, and the control electrode of the eighty-third transistor is connected to the first clock control signal input terminal.
  • the second pole is connected to the second sensing input anti-leakage node.
  • it also includes:
  • the second sensing reset circuit is connected to the second clock control signal input terminal, the second level supply terminal and the second pull-up post node, and is configured to respond to the valid signal provided by the second clock control signal input terminal.
  • the level signal is controlled by writing the non-effective level signal provided by the second level supply terminal to the second pull-up post node.
  • the second sensing reset circuit includes: an eighty-seventh transistor
  • the control electrode of the eighty-seventh transistor is connected to the second clock control signal input terminal, the first electrode of the eighty-seventh transistor is connected to the second pull-up post node, and the eighty-seventh transistor is connected to the second pull-up post node.
  • the second pole of the seven transistors is connected to the second level supply terminal.
  • it also includes:
  • the fourth drive output circuit is connected to the second pull-up post node, the fourth drive clock signal input terminal, and the fourth drive signal output terminal, and is configured to respond to the effective voltage at the second pull-up post node.
  • the control of the flat signal writes the signal provided by the fourth driving clock signal input terminal to the fourth driving signal output terminal.
  • it also includes:
  • the second display reset circuit is connected to the display reset signal input terminal, the second power supply terminal, and the second pull-up node, and is configured to respond to the control of the effective level signal provided by the display reset signal input terminal, and The non-effective level signal provided by the second power terminal is written to the second pull-up node;
  • the second global reset circuit is connected to the global reset signal input terminal, the second power supply terminal and the second pull-up node, and is configured to respond to the control of the effective level signal provided by the global reset signal input terminal.
  • the non-effective level signals provided by the two power terminals are written to the second pull-up node.
  • it also includes:
  • the second pull-down control circuit is connected to the second power terminal, the fifth power terminal, the second pull-up node and the second pull-down node, and is configured to write to the second pull-down node the same value as the second pull-up node.
  • the voltage that is the opposite of the voltage at the node;
  • a second pull-up noise reduction circuit is connected to the second power terminal, the second pull-up node and the second pull-down node, and is configured to respond to the control of the effective level signal at the second pull-down node.
  • the non-effective level signal provided by the second power terminal is written to the second pull-up node;
  • the third drive output circuit is further connected to the second pull-down node and the fourth power supply terminal, and the third drive output circuit is further configured to control the effective level signal at the second pull-down node.
  • the non-effective level signal provided by the fourth power supply terminal is written to the third drive signal output terminal;
  • the fourth drive output circuit is further connected to the second pull-down node and a fourth power supply terminal, and the fourth drive output circuit is further configured to control the effective level signal at the second pull-down node.
  • the non-effective level signal provided by the fourth power supply terminal is written to the fourth driving signal output terminal.
  • the shift register unit includes a second sensing reset circuit, the second sensing reset circuit is connected to a second clock control signal input terminal, a second level supply terminal and the second upper Pulling the post node connection, configured to respond to the control of the valid level signal provided by the second clock control signal input terminal, writing the non-valid level signal provided by the second level supply terminal to the first Two pull-up post-nodes;
  • the shift register unit also includes:
  • the second sensing reset circuit is connected to the second level supply end through the second sensing reset anti-leakage circuit
  • the second sensing reset anti-leakage circuit is also connected to the second pull-down node, and the first sensing reset anti-leakage circuit is configured to respond to the control of the effective level signal at the second pull-down node so that the A path is formed between the second sensing reset circuit and the second level supply end, and in response to the control of the non-effective level signal at the second pull-down node, the second sensing reset circuit is connected to the second level supply terminal. An open circuit is formed between the second level supply terminals.
  • the second sensing reset anti-leakage circuit includes: an eighty-eighth transistor;
  • the control electrode of the eighty-eighth transistor is connected to the second pull-down node, the first electrode of the eighty-eighth transistor is connected to the second sensing reset anti-leakage circuit, and the eighty-eighth transistor The second pole is connected to the second level supply terminal.
  • the shift register unit includes a first sensing reset anti-leakage circuit, and the first sensing reset circuit is connected to the second level supply end through the first sensing reset anti-leakage circuit. ;
  • the first sensing reset anti-leakage circuit is also connected to the first pull-down node, and the first sensing reset anti-leakage circuit is configured to respond to the control of the effective level signal at the first pull-down node. Forming a path between the first sensing reset circuit and the second level supply terminal, and resetting the first sensing in response to the control of the non-effective level signal at the first pull-down node An open circuit is formed between the circuit and the second level supply terminal;
  • the first sensing reset anti-leakage circuit is also connected to the second pull-down node, and the first sensing reset anti-leakage circuit is further configured to respond to the control of the effective level signal at the second pull-down node such that A path is formed between the first sensing reset circuit and the second level supply terminal, and in response to the control of the non-effective level signal at the second pull-down node, the first sensing reset circuit and An open circuit is formed between the second level supply terminals;
  • the second sensing reset anti-leakage circuit is also connected to the first pull-down node, and the first sensing reset anti-leakage circuit is further configured to respond to the control of the effective level signal at the first pull-down node. So that a path is formed between the second sensing reset circuit and the second level supply end, and in response to the control of the non-effective level signal at the first pull-down node, the second sensing An open circuit is formed between the reset circuit and the second level supply terminal.
  • the first sensing reset anti-leakage circuit includes: a seventy-eighth transistor and a seventy-ninth transistor;
  • the second sensing reset anti-leakage circuit includes: an 88th transistor and an 89th transistor;
  • the control electrode of the seventy-eighth transistor is connected to the first pull-down node, the first electrode of the seventy-eighth transistor is connected to the first sensing reset anti-leakage circuit, and the seventy-eighth transistor is connected to the first pull-down node.
  • the second pole of the transistor is connected to the second level supply terminal;
  • the control electrode of the seventy-ninth transistor is connected to the second pull-down node, the first electrode of the seventy-ninth transistor is connected to the first sensing reset anti-leakage circuit, and the seventy-ninth transistor
  • the second pole is connected to the second level supply terminal
  • the control electrode of the eighty-eighth transistor is connected to the second pull-down node, the first electrode of the eighty-eighth transistor is connected to the second sensing reset anti-leakage circuit, and the eighty-eighth transistor
  • the second pole is connected to the second level supply terminal
  • the control electrode of the eighty-ninth transistor is connected to the first pull-down node, the first electrode of the eighty-ninth transistor is connected to the second sensing reset anti-leakage circuit, and the eighty-ninth transistor is connected to the first pull-down node.
  • the second pole of the transistor is connected to the second level supply terminal.
  • it also includes:
  • the second voltage control circuit is connected to the third power terminal, the second pull-up node, and the second voltage control node.
  • the second voltage control circuit is configured to respond to the control of the effective level signal at the second pull-up node. Write the effective level signal provided by the effective level supply terminal to the second voltage control node;
  • the shift register unit further includes: at least one of a fourth leakage prevention circuit, a fifth leakage prevention circuit, and a sixth leakage prevention circuit;
  • the second global reset circuit is connected to the second power terminal through the fourth anti-leakage circuit, the second global reset circuit and the fourth anti-leakage circuit are connected to a fourth anti-leakage node, and the fourth anti-leakage circuit
  • the leakage node is connected to the second voltage control node
  • the fourth leakage prevention circuit is connected to the global reset signal input terminal
  • the fourth leakage prevention circuit is configured to respond to the effective level provided by the global reset signal input terminal.
  • the control of the signal causes a path to be formed between the fourth anti-leakage node and the second power terminal, and the control of the non-effective level signal provided by the global reset signal input terminal causes the fourth anti-leakage node to Open circuit with the second power terminal;
  • the second display reset circuit is connected to the second power terminal through the fifth anti-leakage circuit, the second display reset circuit and the fifth anti-leakage circuit are connected to the fifth anti-leakage node, and the fifth anti-leakage circuit is connected to the fifth anti-leakage node.
  • the leakage node is connected to the second voltage control node, the fifth leakage prevention circuit is connected to the display reset signal input terminal, and the fifth leakage prevention circuit is configured to respond to the effective level provided by the display reset signal input terminal.
  • the control of the signal causes a path to be formed between the fifth anti-leakage node and the second power terminal, and the control of the non-effective level signal provided by the display reset signal input terminal causes the fifth anti-leakage node to Open circuit with the second power terminal;
  • the second pull-up noise reduction circuit is connected to the second power terminal through the sixth leakage prevention circuit, and the second pull-up noise reduction circuit and the sixth leakage prevention circuit are connected to the sixth leakage prevention node, so
  • the sixth anti-leakage node is connected to the second voltage control node
  • the sixth anti-leakage circuit is connected to the second pull-down node
  • the sixth anti-leakage circuit is configured to respond to the effective voltage at the second pull-down node.
  • the control of the flat signal causes a path to be formed between the sixth leakage prevention node and the second power terminal, and in response to the control of the non-effective level signal at the second pull-down node, the sixth leakage prevention node and The second power terminals are disconnected.
  • embodiments of the present disclosure also provide a shift register unit, which includes:
  • sensing control circuit connected to the first sensing signal input terminal, the second sensing signal input terminal, and the sensing control node, and configured to respond to the control of the effective level signal provided by the first sensing signal input terminal, writing the effective level signal provided by the second sensing signal input terminal to the sensing control node;
  • the first sensing input circuit includes: a sensing input preparation sub-circuit and a sensing input sub-circuit; wherein the sensing input preparation sub-circuit is connected to the sensing preparation node, the sensing control node and the first level supply end, and the sensing input
  • the input preparation subcircuit is configured to write the signal provided by the first level supply end to the sensing preparation node in response to the control of the effective level signal provided by the sensing control node;
  • the sensing input subcircuit Connected to the sensing preparation node, the first clock control signal input terminal, and the first pull-up post node, the sensing input sub-circuit is configured to respond to the effective level signal provided by the first clock control signal input terminal. Control, write the signal at the sensing preparation node to the first pull-up post node;
  • Sensing control anti-leakage circuit the sensing control circuit is connected to the second sensing signal input terminal through the sensing control anti-leakage circuit, the sensing control circuit is connected to the sensing control anti-leakage circuit At the sensing control anti-leakage node, the sensing control anti-leakage node is connected to the sensing preparation node; the sensing control anti-leakage circuit is also connected to the third sensing signal input terminal, and the sensing control anti-leakage node
  • the leakage circuit is configured to control the effective level signal provided by the third sensing signal input terminal so that the sensing control leakage prevention node forms a path with the second sensing signal input terminal, and in response to the control of the effective level signal provided by the third sensing signal input terminal.
  • the non-effective level signal provided by the third sensing signal input terminal is controlled so that the sensing control anti-leakage node and the second sensing signal input terminal form an open circuit;
  • the first drive output circuit is connected to the first pull-up post node, the first drive clock signal input terminal, and the first drive signal output terminal, and is configured to respond to the effective level of the first pull-up post node.
  • the signal is controlled by writing the signal provided by the first driving clock signal input terminal to the first driving signal output terminal.
  • the third sensing signal input terminal is the first sensing signal input terminal or the second sensing signal input terminal.
  • it also includes:
  • the first display input circuit is connected to the display signal input terminal, the third power supply terminal and the first pull-up node, and is configured to respond to the control of the effective level signal provided by the display signal input terminal, and the third power supply terminal The provided valid level signal is written to the first pull-up node;
  • the first pull-up node is connected to the first pull-up post node
  • the first level supply terminal is the third power terminal.
  • an embodiment of the present disclosure also provides a gate drive circuit, which includes: a plurality of cascaded shift register units, the shift register unit adopts any one of the above first and second aspects.
  • the shift register unit includes: a plurality of cascaded shift register units, the shift register unit adopts any one of the above first and second aspects.
  • embodiments of the present disclosure also provide a gate driving method, wherein the gate driving method is based on the shift register unit described in the first aspect, and the gate driving method includes:
  • the first switch circuit responds to the control of the effective level signal provided by the switch signal input terminal to form a path between the first pull-up node and the first pull-up post-node, and the sensing
  • the control circuit writes the effective level signal provided by the second sensing signal input end to the sensing control node in response to the control of the effective level signal provided by the first sensing signal input end
  • the first display input circuit writes the effective level signal provided by the third power supply terminal to the first pull-up node and the first pull-up node in response to the control of the effective level signal provided by the display signal input terminal.
  • Post node the first drive output circuit writes the signal provided by the first drive clock signal input end to the first drive in response to the control of the effective level signal at the first pull-up post node. Signal output terminal;
  • the first sensing input circuit responds to the control of the effective level signal at the sensing control node and the effective level signal provided by the first clock control signal input terminal, and controls the first level supply terminal to Provide a valid level signal to be written to the first pull-up post node;
  • the first switch circuit responds to the control of the effective level signal provided by the switch signal input terminal to form an open circuit between the first pull-up node and the first pull-up post-node, and the first The driving output circuit writes the signal provided by the first driving clock signal input terminal to the first driving signal output terminal in response to the control of the effective level signal at the first pull-up post-node.
  • Figure 1 is a schematic circuit structure diagram of a pixel circuit in an organic light-emitting diode display panel
  • Figure 2 is a working timing diagram of the pixel circuit shown in Figure 1;
  • Figure 3 is a schematic diagram of the circuit structure of a shift register unit related to the related art
  • Figure 4 is a schematic circuit structure diagram of a shift register unit provided by an embodiment of the present disclosure.
  • Figure 5 is a schematic circuit structure diagram of another shift register unit provided by an embodiment of the present disclosure.
  • Figure 6 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • Figure 7 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • Figure 8 is an operating timing diagram of the shift register unit shown in Figure 7;
  • FIGS 9 to 11 are other three working timing diagrams of the shift register unit shown in Figure 7;
  • Figure 12 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • Figure 13 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • Figures 14A and 14B are two working timing diagrams of the shift register unit shown in Figure 13;
  • Figure 15 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • Figure 16 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • Figure 17 is an operating timing diagram of the shift register unit shown in Figure 16;
  • Figure 18 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • Figure 19 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • Figure 20 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • Figure 21 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • 22A to 22D are schematic diagrams of various circuit structures of the sensing control circuit, the first sensing input circuit and the sensing control anti-leakage circuit in embodiments of the present disclosure
  • Figure 23 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • Figure 24 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • Figure 25 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • Figure 26 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • Figure 27 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • Figure 28 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • Figure 29 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • Figure 30 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • Figure 31 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • Figure 32 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • Figure 33 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • Figure 34 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • Figure 35 is a schematic circuit structure diagram of a gate drive circuit provided by an embodiment of the present disclosure.
  • Figure 36 is a method flow chart of a gate driving method provided by an embodiment of the present disclosure.
  • words such as “includes” or “includes” mean that the elements or things listed before the word include the elements or things listed after the word and their equivalents, without excluding other elements or things.
  • Words such as “connected” or “connected” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics.
  • the coupling methods of the drain and source of each transistor can be interchanged. Therefore, there is actually no difference between the drain and source of each transistor in this embodiment of the disclosure.
  • the control electrode i.e., the gate
  • one of the poles is called the drain and the other is called the source.
  • the thin film transistor used in the embodiment of the present disclosure may be an N-type transistor or a P-type transistor.
  • its first electrode may be a source electrode
  • its second electrode may be a drain electrode.
  • the thin film transistor is an N-type transistor.
  • valid level signal refers to a signal that can control the transistor to turn on after being input to the control electrode of the transistor
  • non-effective level signal refers to a signal that can control the transistor to turn off after being input to the control electrode of the transistor.
  • the high-level signal is an effective-level signal
  • the low-level signal is an inactive-level signal
  • the low-level signal is an effective-level signal
  • the high-level signal is Invalid level signal.
  • the transistor is an N-type transistor as an example.
  • the effective level signal refers to a high level signal
  • the non-effective level signal refers to a low level signal. It can be imagined that when a P-type transistor is used, the timing changes of the control signal need to be adjusted accordingly. The specific details will not be repeated here, but they should also be within the protection scope of this disclosure.
  • Figure 1 is a schematic circuit structure diagram of a pixel circuit in an organic light-emitting diode display panel.
  • Figure 2 is a working timing diagram of the pixel circuit shown in Figure 1.
  • one frame can be divided into two periods: the display driving period and the blank period; in the display driving period, each row of pixel units in the display panel completes the display driving; in the blank period, the display panel A certain row of pixel units in the pixel completes current extraction (i.e., sensing).
  • the pixel circuit includes a display switching transistor QTFT (the control electrode is connected to the first gate line G1), a driving transistor DTFT, a sensing switching transistor STFT (the control electrode is connected to the second gate line G2) and a Cst.
  • the working process of the pixel circuit includes at least the following two stages: a pixel driving stage (including a data voltage writing process) and a pixel sensing stage (including a current reading process).
  • the data voltage Vdata in the data line Data needs to be written to the pixel unit; in the pixel sensing stage, a test voltage Vsence needs to be written to the pixel unit through the data line Data and passed through the sensing switching transistor STFT.
  • the electrical signal at the drain of the drive transistor is read to the signal read line Sence.
  • the effective level voltage needs to be written to the gate of the sensing switch transistor STFT through the corresponding second gate line G2.
  • a pulse signal (called a “display driving pulse”) needs to be provided to the second gate line G2 during the display driving stage, but also a pulse signal needs to be provided to the second gate line G2 during the display driving stage.
  • a pulse signal with a relatively wide pulse width (“pixel sensing pulse”) is provided to the second gate line G2.
  • Figure 3 is a schematic circuit structure diagram of a shift register unit related to the related art.
  • the shift register unit includes a sensing control circuit 1, a first sensing input circuit 2, and a first sensing input circuit 2. a display input circuit 7 and a first drive output circuit 5.
  • the sensing control circuit 1 and the first sensing input circuit 2 are connected to the sensing control node H, and the first sensing input circuit 2, the first display input circuit 7 and the first driving output circuit 5 are connected to the first pull-up
  • the first drive output circuit 5 is configured with a first drive signal output terminal OUT2, and the first drive signal output terminal OUT2 is connected to the corresponding second gate line G2.
  • the first display input circuit 7 provides an effective level signal to the first pull-up node PU1 to control the first driving output circuit OUT2 to output a display driving pulse; in the pixel sensing stage, the first sensing The input circuit 2 provides an effective level signal to the first pull-up node PU1 to control the first drive output circuit 5 to output a pixel sensing pulse.
  • the first pull-up node PU1 will have a long period of time ( During this period of time, the first drive output circuit outputs display driving pulses) and is in a floating state.
  • the first pull-up node PU1 is connected to many circuit structures, and the first pull-up node PU1 is in a floating state, A longer time will cause greater noise interference at the first pull-up node PU1; for example, the electrical devices (such as transistors) in the first display input circuit 7 will interfere with the voltage at the first pull-up node PU1; at this time , the voltage at the first pull-up node PU1 will have a large swing, which will affect the output of the first drive output circuit 5 . For example, when the voltage at the first pull-up node PU1 is disturbed by noise and becomes an inactive level state at a certain moment, the first driving output circuit 5 may not output normally. It can be seen that how to ensure the stable output of the first driving output circuit 5 during the pixel sensing stage is an urgent technical problem that those skilled in the art need to solve.
  • Figure 4 is a schematic circuit structure diagram of a shift register unit provided by an embodiment of the present disclosure.
  • the shift register unit includes: a sensing control circuit 1, a first sensing input circuit 2, a first display Input circuit 7, first switch circuit 61 and first drive output circuit 5.
  • the sensing control circuit 1 is connected to the first sensing signal input terminal INPUT2_1, the second sensing signal input terminal INPUT2_2, and the sensing control node H, and the sensing control circuit 1 is configured to respond to the first sensing signal input terminal INPUT2_1
  • the effective level signal provided by the second sensing signal input terminal INPUT2_2 is controlled by writing the effective level signal provided by the second sensing signal input terminal INPUT2_2 to the sensing control node H.
  • the first sensing input circuit 2 is connected to the first level supply terminal, the first clock control signal input terminal CLKA, the sensing control node H, and the first pull-up post node PUB1, and is configured to respond Control the effective level signal provided by the sensing control node H and the effective level signal provided by the first clock control signal input terminal CLKA, and write the effective level signal provided by the first level supply end to the first pull-up Set node PUB1.
  • the first display input circuit 7 is connected to the display signal input terminal INPUT1, the third power supply terminal and the first pull-up node PU1.
  • the first display input circuit 7 is configured to respond to the control of the effective level signal provided by the display signal input terminal INPUT1, Write the effective level signal provided by the third power terminal to the first pull-up node PU1.
  • the first switch circuit 61 is connected in series between the first pull-up node PU1 and the first pull-up post node PUB1.
  • the first switch circuit 61 is connected to the switch signal input terminal SW.
  • the first switch circuit 61 is configured to respond to the switch signal input.
  • the signal provided by the terminal SW is controlled to control the connection between the first pull-up node PU1 and the first pull-up post-node PUB1.
  • the first drive output circuit 5 is connected to the first pull-up post node PUB1, the first drive clock signal input terminal CLKE, and the first drive signal output terminal OUT2.
  • the first drive output circuit 5 is configured to respond to the first pull-up post node.
  • the control of the effective level signal at node PUB1 writes the signal provided by the first driving clock signal input terminal CLKE to the first driving signal output terminal OUT2.
  • the first display input circuit 7 is connected to the first pull-up node PU1
  • the first sensing input circuit 2 and the first driving output circuit 5 are both connected to the first pull-up post node PUB1
  • the first pull-up node PU1 is connected to the first display input circuit 7.
  • the driving output circuit 5 is controlled by the effective level signal at the first pull-up post node PUB1 to operate.
  • a first switch circuit 61 is connected in series between the first pull-up node PU1 and the first pull-up post node PUB1.
  • a switch circuit 61 can control the connection between the first pull-up node PU1 and the first pull-up post-node PUB1.
  • the switch signal input terminal SW provides a valid level signal to make the first switch circuit 61 in a conductive state.
  • a path is formed between the first pull-up node PU1 and the first pull-up post-node PUB1.
  • the first display input circuit 7 provides an effective level signal to the first pull-up node PU1.
  • the effective level signal can be written to the first pull-up post node PUB1 through the first switch circuit 61 to control the first drive output circuit. 5 outputs display driving pulses.
  • the switch signal input terminal SW provides an effective level signal so that the first switch circuit 61 is in an off state.
  • the first sensing input circuit 2 provides an effective level signal to the first pull-up post-node PUB1.
  • the effective level signal It is impossible to write to the first pull-up node PU1; thereafter, the first drive output circuit 5 is controlled by the effective level signal at the first pull-up post-node PUB1 to output a pixel sensing pulse.
  • the first pull-up post-node PUB1 and the first pull-up node PU1 remain in an open-circuit state, so the electrical components in the first display input circuit 7 do not It will cause interference to the voltage at the first pull-up post node PUB1.
  • the noise interference at the first pull-up post-node PUB1 used to control the operation of the first drive output circuit 5 in the embodiment of the present disclosure is less than the noise interference at the first pull-up node PU1 used to control the operation of the first drive output circuit 5 in the related art; therefore, compared with the prior art, the first drive output circuit 5 in the present disclosure outputs pixel sensing The stability of the pulse process is better.
  • Figure 5 is a schematic circuit structure diagram of another shift register unit provided by an embodiment of the present disclosure.
  • the first switch circuit 61 includes: a seventy-first transistor M71; The control electrode of a transistor M71 is connected to the switch signal input terminal SW, the first electrode of the 71st transistor M71 is connected to the first pull-up node PU1, and the second electrode of the 71st transistor M71 is connected to the first pull-up node PU1. Node PUB1 is connected.
  • the seventy-first transistor M71 When the switch signal input terminal SW provides a valid level signal, the seventy-first transistor M71 is in a conductive state, and a path is formed between the first pull-up node PU1 and the first pull-up post-node PUB1; when the switch signal input terminal SW When an inactive level signal is provided, the seventy-first transistor M71 is in a cut-off state, and an open circuit is formed between the first pull-up node PU1 and the first pull-up post-node PUB1.
  • Figure 6 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • the first sensing input circuit 2 includes: a sensing input preparation subcircuit 201 and Sense input subcircuit 202.
  • the sensing input preparation sub-circuit 201 is connected to the sensing preparation node Z, the sensing control node H, and the first level supply end.
  • the sensing input preparation sub-circuit 201 is configured to respond to the effective level signal provided by the sensing control node H. Control, write the signal provided by the first level supply terminal to the sensing preparation node Z.
  • the sensing input sub-circuit 202 is connected to the sensing preparation node Z, the first clock control signal input terminal CLKA, and the first pull-up post node PUB1.
  • the sensing input sub-circuit 202 is configured to respond to the first clock control signal input terminal CLKA.
  • the signal at the sensing preparation node Z is written to the first pull-up post node PUB1 under the control of the provided valid level signal.
  • the first level supply terminal may be a third power terminal (which provides the effective level voltage VDD1) or the first clock control signal input terminal CLKA.
  • the shift register unit further includes: a first display reset circuit 8 and a first global reset circuit 6.
  • the first display reset circuit 8 is connected to the display reset signal input terminal RST, the second power supply terminal, and the first pull-up node PU1.
  • the first display reset circuit 8 is configured to respond to the effective level provided by the display reset signal input terminal RST.
  • the control of the signal is to write the inactive level signal provided by the second power terminal to the first pull-up node PU1.
  • the first global reset circuit 6 is connected to the global reset signal input terminal T-RST, the second power supply terminal, and the first pull-up node PU1.
  • the first global reset circuit 6 is configured to respond to the valid signal provided by the global reset signal input terminal T-RST.
  • the control of the level signal writes the inactive level signal provided by the second power terminal to the first pull-up node PU1.
  • FIG. 7 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure. As shown in FIG. 7 , the shift register unit shown in FIG. 7 is an embodiment based on the shift register unit shown in FIG. 6 Alternative implementations.
  • the sensing control circuit 1 includes a first transistor M1.
  • the control electrode of the first transistor M1 is connected to the first sensing signal input terminal INPUT2_1, the first electrode of the first transistor M1 is connected to the first sensing signal input terminal INPUT2_2, and the second electrode of the first transistor M1 is connected to the sensing control node. H connection.
  • the first sensing input circuit 2 includes a second transistor M2 and a third transistor M3.
  • the control electrode of the second transistor M2 is connected to the sensing control node H, the first electrode of the second transistor M2 is connected to the first level, and the second electrode of the second transistor M2 is connected to the sensing preparation node Z.
  • the control electrode of the third transistor M3 is connected to the first clock control signal input terminal CLKA, the first electrode of the third transistor M3 is connected to the sensing preparation node Z, and the second electrode of the third transistor M3 is connected to the first pull-up post node. PUB1 is connected.
  • the first switch circuit 61 includes a seventy-first transistor M71.
  • the control electrode of the 71st transistor M71 is connected to the switch signal input terminal SW, the first electrode of the 71st transistor M71 is connected to the first pull-up node PU1, and the second electrode of the 71st transistor M71 is connected to the first pull-up node PU1. Pull the connection of the post node PUB1.
  • the first global reset circuit 6 includes a seventh transistor M7.
  • the control electrode of the seventh transistor M7 is connected to the global reset signal input terminal T-RST, the first electrode of the seventh transistor M7 is connected to the first pull-up node PU1, and the second electrode of the seventh transistor M7 is connected to the second power terminal.
  • the first display input circuit 7 includes a ninth transistor M9.
  • the control electrode of the ninth transistor M9 is connected to the display signal input terminal INPUT1, the first electrode of the ninth transistor M9 is connected to the third power supply terminal, and the second electrode of the ninth transistor M9 is connected to the first pull-up node PU1.
  • the first display reset circuit 8 includes a tenth transistor M10.
  • the control electrode of the tenth transistor M10 is connected to the display reset signal input terminal RST, the first electrode of the tenth transistor M10 is connected to the first pull-up node PU1, and the second electrode of the tenth transistor M10 is connected to the second power terminal.
  • the first driving output circuit 5 includes a fifth transistor M5.
  • the control electrode of the fifth transistor M5 is connected to the first pull-up post node PUB1, the first electrode of the fifth transistor M5 is connected to the first drive clock signal input terminal CLKE, and the second electrode of the fifth transistor M5 is connected to the first drive signal.
  • the output terminal OUT2 is connected.
  • a first capacitor C1 is configured at the sensing control node H, and the first capacitor C1 can function to stabilize the voltage at the sensing control node H.
  • a second capacitor C2 is configured at the first drive signal output terminal OUT2.
  • the second capacitor C2 is beneficial to improving the stability of the signal output by the first drive signal output terminal OUT2.
  • the first level supply terminal may be a third power terminal (which provides the effective level voltage VDD1) or the first clock control signal input terminal CLKA.
  • Figure 8 is an operating timing diagram of the shift register unit shown in Figure 7. As shown in Figure 8, the second power supply terminal provides a low-level voltage VGL1, the third power supply terminal provides a high-level voltage VDD1, and the first power supply terminal
  • the flat supply terminal is the first clock control signal input terminal CLKA is taken as an example for an exemplary description.
  • the working process of the shift register unit includes: display driving stage, sensing driving stage and global reset stage t3.
  • the display driving stage includes: the sequential display input sub-stage t1_1, the display output sub-stage t1_2 and the display reset sub-stage t1_3;
  • the sensing driving stage includes: the sequential sensing preparation sub-stage t2_0 and the sensing input sub-stage t2_1 , sensing output sub-stage t2_2, sensing control reset sub-stage t2_3.
  • the switch signal input terminal SW provides a high-level signal
  • the 71st transistor M71 is in a conductive state, and a path is formed between the first pull-up node PU1 and the first pull-up post-node PUB1; and
  • the display signal input terminal INPUT1 provides a high-level signal
  • the ninth transistor M9 is in a conductive state, and the high-level voltage VDD1 is written to the first pull-up node PU1 through the ninth transistor M9.
  • the first pull-up node PU1 The voltage is at a high level.
  • the voltage at the first pull-up post-node PUB1 is also in a high level state.
  • the fifth transistor M5 is turned on, and the fifth transistor M5 is turned on.
  • a low-level signal provided by a driving clock signal input terminal CLKE is written to the first driving signal output terminal OUT2 through the fifth transistor M5, that is, the first driving signal output terminal OUT2 outputs a low-level signal.
  • the switch signal input terminal SW provides a high-level signal
  • the 71st transistor M71 maintains the on state
  • the path between the first pull-up node PU1 and the first pull-up post-node PUB1 is maintained; and
  • the display signal input terminal INPUT1 provides a low-level signal
  • the ninth transistor M9 is in a cut-off state.
  • the first pull-up node PU1 and the first pull-up post-node PUB1 are both in a floating state and maintain a high level.
  • the fifth transistor M5 maintains the on state.
  • the signal provided by the first driving clock signal input terminal CLKE changes from a low-level signal to a high-level signal.
  • the first pull-up node PU1 The voltage at the first pull-up post-node PUB1 is pulled up to a higher level, and the first drive signal output terminal OUT2 outputs a high-level signal (outputs a display driving pulse).
  • the signal provided by the first driving clock signal input terminal CLKE changes from a high-level signal to a low-level signal.
  • the first pull-up node The voltage at PU1 and the first pull-up post-node PUB1 is pulled down to the initial high level voltage, the fifth transistor M5 remains on, and the first drive signal output terminal OUT2 outputs a low level signal.
  • the display reset signal input terminal provides a high-level signal
  • the tenth transistor M10 is turned on, and the low-level voltage VGL1 is written to the first pull-up node PU1 and the first pull-up node through the tenth transistor M10
  • the voltages at the set node PUB1, the first pull-up node PU1 and the first pull-up post-node PUB1 are all in a low level state, so the fifth transistor M5 is in a cut-off state.
  • the first driving signal output terminal OUT2 is in a floating state, and the voltage at the first driving signal output terminal OUT2 maintains the low level state of the previous stage, so the first driving signal output terminal OUT2 outputs a low level signal.
  • the first sensing signal input terminal INPUT2_1 provides a high-level signal
  • the first transistor M1 is turned on
  • the high-level signal provided by the second sensing signal input terminal INPUT2_2 is written through the first transistor M1
  • the voltage at the sensing control node H is in a high level state, so the second transistor M2 is turned on. Since the first clock control signal input terminal CLKACLKA provides a low level signal, the third transistor M3 is turned off.
  • the first clock control signal input terminal CLKA provides a high-level signal
  • the third transistor M3 is turned on.
  • the second transistor M2 remains on, so the first clock control signal input terminal CLKA provides a high-level signal through the second transistor M2 and the third transistor M2.
  • the transistor M3 writes to the first pull-up post node PUB1, that is, the voltage at the first pull-up post node PUB1 is in a high level state. It should be noted that since the seventy-first transistor M71 is in the on state at this time, the voltage at the first pull-up node PU1 is also in a high level state.
  • the fifth transistor M5 is turned on, and the low level signal provided by the first driving clock signal input terminal CLKE is written to the first driving signal output terminal OUT2 through the fifth transistor M5, that is, the first driving signal output terminal OUT2 outputs a low level signal. flat signal.
  • the switch signal input terminal SW provides a low-level signal
  • the 71st transistor M71 is in a cut-off state
  • an open circuit is formed between the first pull-up node PU1 and the first pull-up post-node PUB1.
  • the signal provided by the first driving clock signal input terminal CLKE changes from a low-level signal to a high-level signal.
  • the first drive signal output terminal OUT2 outputs a high-level signal (outputs a pulse for pixel sensing). It should be noted that since the first pull-up node PU1 and the first pull-up post-node PUB1 are disconnected, the voltage at the first pull-up node PU1 will not be pulled up.
  • the signal provided by the first driving clock signal input terminal CLKE changes from a high-level signal to a low-level signal.
  • the first pull-up The voltage at the post-node PUB1 is pulled down to the initial high-level voltage, the fifth transistor M5 remains on, and the first drive signal output terminal OUT2 outputs a low-level signal.
  • the first sensing signal input terminal INPUT2_1 provides a high-level signal
  • the first transistor M1 is turned on
  • the low-level signal provided by the second sensing signal input terminal INPUT2_2 is written through the first transistor M1 Entering the sensing control node H
  • the voltage at the sensing control node H is in a low level state, so the second transistor M2 is turned off.
  • the third transistor M3 is also turned off.
  • the switch signal input terminal SW provides a high-level signal
  • the 71st transistor M71 is in a conductive state, and a path is formed between the first pull-up node PU1 and the first pull-up post-node PUB1.
  • the global reset signal input terminal provides a high-level signal, so the seventh transistor M7 is turned on, and the low-level voltage VGL1 is written to the first pull-up node PU1 through the seventh transistor M7.
  • the voltage at the first pull-up node PU1 is at low voltage. flat state.
  • the voltage at the first pull-up post-node PUB1 is in a low level state.
  • the fifth transistor M5 is in the off state.
  • the first driving signal output terminal OUT2 is in a floating state, and the voltage at the first driving signal output terminal OUT2 maintains the low level state of the previous stage, so the first driving signal output terminal OUT2 outputs a low level signal.
  • the sensing preparation sub-phase t2_0 is located within the display output sub-phase t1_2, and the sensing control reset sub-phase t2_3 is synchronized with the global reset phase t3.
  • This situation only serves an exemplary purpose and does not This may cause limitations to the technical solution of the present disclosure.
  • the display input sub-stage t1_1, the display output sub-stage t1_2 and the display reset sub-stage t1_3 are performed in sequence and are located within the display driving period, and the sensing preparation sub-stage t2_0, the sensing input sub-stage t2_1, The sensing output sub-stage t2_2 and the sensing control reset sub-stage t2_3 are performed in sequence.
  • the sensing preparation sub-stage t2_0 is located in the display driving period.
  • the sensing input sub-stage t2_1 and the sensing output sub-stage t2_2 are located in the sensing period.
  • the global reset is Phase t3 can be performed after the sensing output sub-phase t2_2.
  • Figures 9 to 11 are other three working timing diagrams of the shift register unit shown in Figure 7.
  • the sensing control reset sub-phase t2_3 is located in the global reset phase t3 Performed before;
  • the sensing preparation sub-phase t2_0 is performed before the display output sub-stage t1_2 (can be performed synchronously with the display input sub-stage t1_1);
  • the sensing control reset sub-stage t2_3 is located globally The reset phase t3 is performed after, and the sensing control reset sub-phase t2_3 can be performed within the display driving period of the next frame; these situations should all fall within the protection scope of the present disclosure.
  • the technical solution of the present disclosure can also adopt other working sequences (for example, the sensing preparation sub-phase t2_0 can be executed after the display output sub-phase t1_2), and no examples are given here.
  • Figure 12 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure. As shown in Figure 12, in some embodiments, the shift register unit is not only provided with the above-mentioned first switch circuit 61, but also A first sensing reset circuit 3 is provided.
  • the global reset circuit writes the low-level voltage VGL1 to the first pull-up module through the first switch circuit 61.
  • Set node PUB1 that is to say, the first pull-up post-node PUB1 is reset by relying on the first global reset circuit 6, and the first switch circuit 61 also needs to be in a conductive state during the global reset stage.
  • a global reset circuit has enough time to write the low-level voltage VGL1 to the first pull-up post-node PUB1, so it is necessary to make the moment when the first switch circuit switches from the off state to the on state as close as possible to the global reset.
  • the starting time of phase t3 is shorter.
  • the time between the end time of the sensing output sub-phase t2_2 and the start time of the global reset phase t3 is shorter.
  • the starting time of the global reset phase t3 overlaps.
  • the duration between the end time of the sensing output sub-phase t2_2 and the starting time of the global reset phase t3 in Figure 9 is the duration of one sensing control reset sub-phase t2_3; therefore, for The switching time of the first switch circuit 61 from the off state to the on state requires high accuracy.
  • a first sensing reset circuit is configured for the first pull-up post node PUB1.
  • the first sensing reset circuit can be used to perform a reset on the first pull-up post node PUB1. Reset, so that the reset of the first pull-up post node PUB1 no longer relies on the first global reset circuit 6 and the first switch circuit 61 . Only the first sensing reset circuit 3 will be described in detail below.
  • the first sensing reset circuit 3 is connected to the second clock control signal input terminal CLKB, the second level supply terminal and the first pull-up post node PUB1, and the first sensing reset circuit 3 is configured to respond to the second clock
  • the control of the valid level signal provided by the control signal input terminal CLKB writes the non-valid level signal provided by the second level supply terminal to the first pull-up post node PUB1.
  • the second level supply terminal can provide an inactive level signal for resetting when the first pull-up post node PUB1 needs to be reset.
  • the first sensing reset circuit 3 includes: a seventy-seventh transistor M77; the control electrode of the seventy-seventh transistor M77 is connected to the second clock control signal input terminal CLKB, and the control electrode of the seventy-seventh transistor M77 is connected to the second clock control signal input terminal CLKB.
  • One pole is connected to the first pull-up post node PUB1, and the second pole of the seventy-seventh transistor M77 is connected to the second level supply end.
  • Figure 13 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure. As shown in Figure 13, the shift register unit shown in Figure 13 is a specific shift register unit based on the shift register unit shown in Figure 12. alternative implementations.
  • the sensing control circuit 1 includes a first transistor M1, the first sensing input circuit 2 includes a second transistor M2 and a third transistor M3, the first switch circuit 61 includes a seventy-first transistor M71, and the first global reset circuit 6 It includes a seventh transistor M7, the first display input circuit 7 includes a ninth transistor M9, the first display reset circuit 8 includes a tenth transistor M10, the first drive output circuit 5 includes a fifth transistor M5, and the first sensing reset circuit 3 includes Seventy-seven transistor M77.
  • the connection relationship between each transistor can be referred to the content in the previous embodiment, and will not be described again here.
  • Figure 14A and Figure 14B are two working timing diagrams of the shift register unit shown in Figure 13.
  • the second power supply terminal provides a low-level voltage VGL1
  • the third power supply terminal provides a high-level voltage.
  • VDD1 the case where the first level supply terminal is the first clock control signal input terminal and the second level supply terminal is the second power supply terminal is taken as an example for description.
  • the working process of the shift register unit includes: display driving stage, sensing driving stage and global reset stage t3.
  • the display driving stage includes: display input sub-stage t1_1, display output sub-stage t1_2 and display reset sub-stage t1_3;
  • the sensing driving stage includes: sensing preparation sub-stage t2_0, sensing input sub-stage t2_1, sensing output sub-stage t2_2, sensing input reset sub-phase t2_3a and sensing control reset sub-phase t2_3.
  • FIG. 14A and FIG. 14B illustrate the situation where the sensing input reset sub-phase t2_3a, the sensing control reset sub-phase t2_3 and the global reset sub-phase t3 are performed simultaneously.
  • This situation only serves as an example. , which will not limit the technical solution of the present disclosure.
  • display input sub-stage t1_1, display output sub-stage t1_2, display reset sub-stage t1_3, sensing preparation sub-stage t2_0, sensing input sub-stage t2_1, sensing output sub-stage t2_2 and sensing control reset sub-stage t2_3 please refer to the contents in the previous embodiments and will not be described again here. Only the sensing input reset sub-phase t2_3a and the global reset phase t3 are described in detail below.
  • the second clock control signal input terminal CLKB provides a valid level signal
  • the seventy-seventh transistor M77 is in the on state
  • the low-level voltage VGL1 provided by the second level supply terminal passes through the The seventy-seven transistor M77 is written to the first pull-up post node PUB1 to reset the first pull-up post node PUB1.
  • the voltage at the first pull-up post node PUB1 is in a low level state, so the fifth transistor M5 is in cutoff state.
  • the first driving signal output terminal OUT2 is in a floating state, and the voltage at the first driving signal output terminal OUT2 maintains the low level state of the previous stage, so the first driving signal output terminal OUT2 outputs a low level signal.
  • the signal provided by the switch signal input terminal SW during the global reset phase t3 is a low-level signal, and the seventy-first transistor M71 is in the off state during the global reset phase t3 , that is, the first switch circuit 61 is in the global reset phase. Phase t3 is in the off state.
  • the signal provided by the switch signal input terminal SW during the global reset phase t3 is a high-level signal
  • the seventy-first transistor M71 is in a conductive state during the global reset phase t3 , that is, the first switch circuit 61 is in the global reset phase t3 .
  • the reset phase t3 is in the on state.
  • the first global reset circuit 6 and the first sensing reset circuit 3 can perform reset processing on the first pull-up post node PUB1 at the same time to improve the control of the first pull-up post node PUB1. reset speed.
  • the state of the first switch circuit 61 in the global reset phase t3 is not limited.
  • the second level supply terminal is the second power terminal is only an optional implementation in the embodiment of the present disclosure, and it does not limit the technical solution of the present disclosure.
  • any signal end that can provide a non-effective level signal in the sensing input reset sub-phase t2_3a can be used as the second level supply end in the embodiment of the present disclosure, for example, in the embodiment shown below
  • the first cascade signal output terminal can also serve as the second level supply terminal in this disclosure.
  • Figure 15 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure. As shown in Figure 15, in some embodiments, the shift register unit also includes: a second drive output circuit 9, a first stage Connect output circuit 13.
  • the second drive output circuit 9 is connected to the first pull-up post node PUB1, the second drive clock signal input terminal CLKD and the second drive signal output terminal OUT1.
  • the second drive output circuit 9 is configured to respond to the first pull-up post node.
  • the control of the active level signal at the node PUB1 writes the signal provided by the second driving clock signal input terminal CLKD to the second driving signal output terminal OUT1.
  • the second drive signal output terminal OUT1 is connected to the first gate line in the pixel unit of the corresponding row to provide the drive signal to the first gate line of the corresponding row.
  • the first cascade output circuit 13 is connected to the first pull-up node PU1, the first cascade clock signal input terminal CLKC, and the first cascade signal output terminal CR, and is configured to respond to the first pull-up
  • the control of the effective level signal at the node PU1 writes the signal provided by the first cascade clock signal input terminal CLKC to the first cascade signal output terminal CR.
  • the shift register unit further includes: a first pull-down control circuit 11 and a first pull-up noise reduction circuit 12 .
  • the first pull-down control circuit 11 is connected to the second power supply terminal, the fifth power supply terminal, the first pull-up node PU1 and the first pull-down node PD1.
  • the first pull-down control circuit 11 is configured to pull down to the first pull-down node PD1. Write a voltage that is inverse of the voltage at the first pull-up node PU1.
  • the first pull-up noise reduction circuit 12 is connected to the second power terminal, the first pull-up node PU1 and the first pull-down node PD1.
  • the first pull-up noise reduction circuit 12 is configured to respond to the effective voltage at the first pull-down node PD1.
  • the control of the flat signal writes the inactive level signal provided by the second power terminal to the first pull-up node PU1.
  • the first cascade output circuit 13 is also connected to the first pull-down node PD1 and the second power terminal.
  • the first cascade output circuit 13 is also configured to respond to the control of the effective level signal at the first pull-down node PD1.
  • the non-effective level signal provided by the two power supply terminals is written to the first cascade signal output terminal CR.
  • the first drive output circuit 5 is also connected to the first pull-down node PD1 and the fourth power supply terminal.
  • the first drive output circuit 5 is also configured to switch the fourth power supply terminal in response to the control of the effective level signal at the first pull-down node PD1.
  • the provided non-effective level signal is written to the first driving signal output terminal OUT2.
  • the second drive output circuit 9 is also connected to the first pull-down node PD1 and the fourth power supply terminal.
  • the second drive output circuit 9 is also configured to switch the fourth power supply terminal in response to the control of the effective level signal at the first pull-down node PD1.
  • the provided non-effective level signal is written to the second driving signal output terminal OUT1.
  • Figure 16 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure. As shown in Figure 16, the shift register unit shown in Figure 16 is an embodiment based on the shift register unit shown in Figure 15 Alternative implementations.
  • the sensing control circuit 1 includes: a first transistor M1.
  • the control electrode of the first transistor M1 is connected to the first sensing signal input terminal INPUY2_1, the first electrode of the first transistor M1 is connected to the second sensing signal input terminal INPUY2_2, and the second electrode of the first transistor M1 is connected to the sensing control node. H connection.
  • the first sensing input circuit 2 includes a second transistor M2 and a third transistor M3.
  • the control electrode of the second transistor M2 is connected to the sensing control node H, the first electrode of the second transistor M2 is connected to the first level supply terminal, and the second electrode of the second transistor M2 is connected to the sensing preparation node Z.
  • the control electrode of the third transistor M3 is connected to the first clock control signal input terminal CLKA, the first electrode of the third transistor M3 is connected to the sensing preparation node Z, and the second electrode of the third transistor M3 is connected to the first pull-up post node. PUB1 is connected.
  • the first switch circuit 61 includes a seventy-first transistor M71.
  • the control electrode of the 71st transistor M71 is connected to the switch signal input terminal SW, the first electrode of the 71st transistor M71 is connected to the first pull-up node PU1, and the second electrode of the 71st transistor M71 is connected to the first pull-up node PU1. Pull the connection of the post node PUB1.
  • the first global reset circuit 6 includes a seventh transistor M7.
  • the control electrode of the seventh transistor M7 is connected to the global reset signal input terminal T-RST, the first electrode of the seventh transistor M7 is connected to the first pull-up node PU1, and the second electrode of the seventh transistor M7 is connected to the second power terminal.
  • the first display input circuit 7 includes a ninth transistor M9.
  • the control electrode of the ninth transistor M9 is connected to the display signal input terminal INT, the first electrode of the ninth transistor M9 is connected to the third power supply terminal, and the second electrode of the ninth transistor M9 is connected to the first pull-up node PU1.
  • the first display reset circuit 8 includes a tenth transistor M10.
  • the control electrode of the tenth transistor M10 is connected to the display reset signal input terminal RST, the first electrode of the tenth transistor M10 is connected to the first pull-up node PU1, and the second electrode of the tenth transistor M10 is connected to the second power terminal.
  • the first pull-down control circuit 11 includes a twelfth transistor M12 and a thirteenth transistor M13.
  • the control electrode of the twelfth transistor M12 is connected to the fifth power terminal, the first electrode of the twelfth transistor M12 is connected to the fifth power terminal, and the second electrode of the twelfth transistor M12 is connected to the first pull-down node PD1.
  • the control electrode of the thirteenth transistor M13 is connected to the first pull-up node PU1, the first electrode of the thirteenth transistor M13 is connected to the first pull-down node PD1, and the second electrode of the thirteenth transistor M13 is connected to the second power terminal. .
  • the first pull-up noise reduction circuit 12 includes a fourteenth transistor M14.
  • the control electrode of the fourteenth transistor M14 is connected to the first pull-down node PD1, the first electrode of the fourteenth transistor M14 is connected to the first pull-up node PU1, and the second electrode of the fourteenth transistor M14 is connected to the second power terminal. .
  • the first driving output circuit 5 includes a fifth transistor M5 and a seventeenth transistor M17.
  • the control electrode of the fifth transistor M5 is connected to the first pull-up post node PUB1, the first electrode of the fifth transistor M5 is connected to the first drive clock signal input terminal CLKE, and the second electrode of the fifth transistor M5 is connected to the first drive signal.
  • the output terminal OUT2 is connected.
  • the control electrode of the seventeenth transistor M17 is connected to the first pull-down node PD1, the first electrode of the seventeenth transistor M17 is connected to the first drive signal output terminal OUT2, and the second electrode of the seventeenth transistor M17 is connected to the fourth power supply terminal. connect.
  • the second driving output circuit 9 includes a fifteenth transistor M15 and an eighteenth transistor M18.
  • the control electrode of the fifteenth transistor M15 is connected to the first pull-up post node PUB1, the first electrode of the fifteenth transistor M15 is connected to the second drive clock signal input terminal CLKD, and the second electrode of the fifteenth transistor M15 is connected to the second drive clock signal input terminal CLKD.
  • the second drive signal output terminal OUT1 is connected.
  • the control electrode of the eighteenth transistor M18 is connected to the first pull-down node PD1, the first electrode of the eighteenth transistor M18 is connected to the second drive signal output terminal OUT1, and the second electrode of the eighteenth transistor M18 is connected to the fourth power supply terminal. connect.
  • the first cascade output circuit 13 includes a sixteenth transistor M16 and a nineteenth transistor M19.
  • the control electrode of the sixteenth transistor M16 is connected to the first pull-up node PU1, the first electrode of the sixteenth transistor M16 is connected to the first cascade clock signal input terminal CLKC, and the second electrode of the sixteenth transistor M16 is connected to the first pull-up node PU1.
  • the cascade signal output terminal CR is connected.
  • the control electrode of the nineteenth transistor M19 is connected to the first pull-down node PD1, the first electrode of the nineteenth transistor M19 is connected to the cascade signal output terminal CR, and the second electrode of the nineteenth transistor M19 is connected to the fourth power supply terminal. .
  • a second capacitor C2 is configured at the first driving signal output terminal OUT2.
  • the first level supply terminal may be a third power supply terminal (which provides an effective level voltage) or a first clock control signal input terminal.
  • the second power terminal provides low-level voltage VGL1
  • the third power terminal provides high-level voltage VDD1
  • the fourth power terminal provides low-level voltage VGL2
  • the fifth power terminal provides high-level voltage VDDA.
  • Figure 17 is a working timing diagram of the shift register unit shown in Figure 16. As shown in Figure 17, the working process of the shift register unit includes: a display driving stage, a sensing driving stage and a global reset stage t3.
  • the display driving stage includes: the sequential display input sub-stage t1_1, the display output sub-stage t1_2 and the display reset sub-stage t1_3;
  • the sensing driving stage includes: the sequential sensing preparation sub-stage t2_0 and the sensing input sub-stage t2_1 , sensing output sub-stage t2_2, sensing control reset sub-stage t2_3.
  • shift register unit shown in Figure 16 can also operate with other operating timings, for example, any of the operating timings shown in Figures 9 to 11 can be used.
  • the shift register unit shown in Figure 15 and Figure 16 can not only provide a driving signal for the corresponding second gate line, but also provide a driving signal for the first gate line of the corresponding row, which is beneficial to reducing the number of gate driving circuits in the display panel. , which is conducive to the narrow bezel design of the product.
  • Figure 18 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure. As shown in Figure 18, the shift register unit shown in Figure 18 is an improvement based on the shift register unit shown in Figure 15.
  • the shift register unit shown in FIG. 18 not only includes the circuit shown in the shift register unit shown in FIG. 15 , but also includes a first sensing reset circuit 3 .
  • the first sensing reset circuit 3 is connected to the second clock control signal input terminal CLKB, the second level supply terminal and the first pull-up post node PUB1, and is configured to respond to the second clock control signal
  • the valid level signal provided by the input terminal CLKB is controlled to write the non-valid level signal provided by the second level supply terminal to the first pull-up post node PUB1.
  • the shift register unit further includes: a first sensing reset anti-leakage circuit 3a, the first sensing reset circuit 3 is connected to the second level supply end through the first sensing reset anti-leakage circuit 3a; A sensing reset anti-leakage circuit 3a is also connected to the first pull-down node PD1, and the first sensing reset anti-leakage circuit 3a is configured to respond to the control of the effective level signal at the first pull-down node PD1 to enable the first sensing A path is formed between the reset circuit 3 and the second level supply end, and in response to the control of the non-effective level signal at the first pull-down node PD1, there is a connection between the first sensing reset circuit 3 and the second level supply end. Create a circuit break.
  • the voltage at the first pull-up node PUB1 when the voltage at the first pull-up node PUB1 is at an active level state, the voltage at the first pull-down node PD1 is at an inactive level state.
  • the first sensing reset circuit 3 and An open circuit is formed between the second level supply terminals, which can effectively prevent the first pull-up post node PUB1 from discharging through the first sensing reset circuit 3 and the second level supply terminal.
  • the first sensing reset anti-leakage circuit 3a when the first sensing reset anti-leakage circuit 3a is provided in the shift register unit, in the sensing input reset sub-stage, the voltage at the first pull-down node PD1 is at an effective level. At this time, the A sensing reset anti-leakage circuit 3a responds to the control of the effective level signal at the first pull-down node PD1 to form a path between the first sensing reset circuit 3 and the second level supply end, and the second level supply end The provided non-effective level signal can be written to the first pull-up post node PUB1 through the first sensing reset anti-leakage circuit 3a and the first sensing reset circuit 3 to reset the first pull-up post node PUB1 .
  • the first sensing reset anti-leakage circuit 3a includes: a seventy-eighth transistor M78; the control electrode of the seventy-eighth transistor M78 is connected to the first pull-down node PD1, and the control electrode of the seventy-eighth transistor M78 is connected to the first pull-down node PD1.
  • One pole is connected to the first sensing reset anti-leakage circuit 3a, and the second pole of the seventy-eighth transistor M78 is connected to the second level supply end.
  • Figure 19 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure. As shown in Figure 19, the shift register unit shown in Figure 19 is an embodiment based on the shift register unit shown in Figure 18 Alternative implementations.
  • the sensing control circuit 1 includes a first transistor M1, the first sensing input circuit 2 includes a second transistor M2 and a third transistor M3, the first switch circuit 61 includes a seventy-first transistor M71, and the first global reset
  • the circuit 6 includes a seventh transistor M7
  • the first display input circuit 7 includes a ninth transistor M9
  • the first display reset circuit 8 includes a tenth transistor M10
  • the first pull-down control circuit 11 includes a twelfth transistor M12 and a thirteenth transistor M13
  • the first pull-up noise reduction circuit 12 includes a fourteenth transistor M14
  • the first drive output circuit 5 includes a fifth transistor M5 and a seventeenth transistor M17
  • the second drive output circuit 9 includes a fifteenth transistor M15 and a tenth transistor M13.
  • the first cascade output circuit 13 includes a sixteenth transistor M16 and a nineteenth transistor M19
  • the first sensing reset circuit 3 includes a seventy-seventh transistor M77
  • the first sensing reset anti-leakage circuit 3a includes a Seventy-Eight Transistor M78.
  • the connection relationship between each transistor can be referred to the content in the previous embodiment, and will not be described again here.
  • the second level supply terminal is the first cascade signal output terminal. Based on the working timing of the first cascade signal output terminal in Figure 17, it can be seen that the first cascade signal output terminal can provide an inactive level signal in the sensing input reset sub-phase t2_3a, so it can be used as a second level supply terminal.
  • the electrical device such as a transistor
  • the electrical device connected to the second level supply terminal will be in a high voltage state for a long time.
  • the electrical device connected to the second level supply terminal will Devices are prone to electrical characteristics drift due to the influence of high voltage for a long time.
  • the voltage connected to the second level supply terminal Electrical devices will not be in a high-voltage state for a long time, so the problem of electrical characteristic drift of electrical devices can be effectively improved.
  • Figure 20 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • the shift register unit includes a first global reset circuit 6, a first When displaying the reset circuit 8 and the first pull-up noise reduction circuit 12 , an anti-leakage design can be performed for at least one of the first global reset circuit 6 , the first display reset circuit 8 and the first pull-up noise reduction circuit 12 .
  • the shift register unit includes a first voltage control circuit 14; the first voltage control circuit 14 is connected to the third power supply terminal, the first pull-up node PU1, and the first voltage control node OFF1.
  • the first voltage control circuit 14 14 is configured to write the effective level signal provided by the effective level supply end to the first voltage control node OFF1 in response to the control of the effective level signal at the first pull-up node PU1.
  • the shift register unit also includes at least one of a first leakage prevention circuit 15 , a second leakage prevention circuit 16 , and a third leakage prevention circuit 17 .
  • the first global reset circuit 6 is connected to the second power terminal through the first anti-leakage circuit 15.
  • the first global reset circuit 6 and the first anti-leakage circuit 15 are connected to the first anti-leakage node Q1.
  • the first anti-leakage node Q1 Connected to the first voltage control node OFF1, the first anti-leakage circuit 15 is connected to the global reset signal input terminal T-RST.
  • the first anti-leakage circuit 15 is configured to respond to the effective level signal provided by the global reset signal input terminal T-RST.
  • the control causes a path to be formed between the first anti-leakage node Q1 and the second power supply terminal, and the control of the non-effective level signal provided by the global reset signal input terminal T-RST causes the first anti-leakage node Q1 to connect to the second power supply terminal. Break between terminals.
  • the first display reset circuit 8 is connected to the second power terminal through the first anti-leakage circuit 16.
  • the first display reset circuit 8 and the first anti-leakage circuit 16 are connected to the second anti-leakage node Q2.
  • the second anti-leakage node Q2 is connected to the second anti-leakage node Q2.
  • a control voltage node OFF1 is connected, and the first anti-leakage circuit 16 is connected with the display reset signal input terminal RST.
  • the first anti-leakage circuit 16 is configured to control the effective level signal provided by the display reset signal input terminal RST so that the second anti-leakage circuit 16 is connected.
  • a path is formed between the leakage node Q2 and the second power terminal, and in response to the control of the non-effective level signal provided by the display reset signal input terminal RST, the second anti-leakage node Q2 and the second power terminal are disconnected.
  • the first pull-up noise reduction circuit 12 is connected to the second power terminal through the third leakage prevention circuit 17.
  • the first pull-up noise reduction circuit 12 and the third leakage prevention circuit 17 are connected to the third leakage prevention node Q3.
  • the third leakage prevention circuit 17 is connected to the third leakage prevention node Q3.
  • the node Q3 is connected to the first voltage control node OFF1
  • the third anti-leakage circuit 17 is connected to the first pull-down node PD1
  • the third anti-leakage circuit 17 is configured to respond to the control of the effective level signal at the first pull-down node PD1 such that A path is formed between the third anti-leakage node Q3 and the second power terminal, and in response to the control of the inactive level signal at the first pull-down node PD1, the third anti-leakage node Q3 and the second power terminal are disconnected.
  • the third power supply terminal provides a valid level signal; as an example, the third power supply terminal provides a high level voltage VDD1, and the valid level supply terminal is the third power supply terminal.
  • the first voltage control circuit 14 includes a twentieth transistor M20.
  • the control electrode of the twentieth transistor M20 is connected to the first pull-up node PU1.
  • the first electrode of the twentieth transistor M20 is connected to the effective level supply. terminal is connected, and the second pole of the twentieth transistor M20 is connected to the first voltage control node OFF1.
  • the first anti-leakage circuit 15 includes a twenty-first transistor M21, the control electrode of the twenty-first transistor M21 is connected to the global reset signal input terminal T-RST, and the first electrode of the twenty-first transistor M21 It is connected to the first anti-leakage node Q1, and the second electrode of the twenty-second transistor M22 is connected to the second power terminal.
  • the first anti-leakage circuit 16 includes a twenty-second transistor M22, a control electrode of the twenty-second transistor M22 is connected to the display reset signal input terminal RST, and a first electrode of the twenty-second transistor M22 is connected to the display reset signal input terminal RST.
  • the second anti-leakage node Q2 is connected, and the second pole of the twenty-second transistor M22 is connected to the second power terminal.
  • the third anti-leakage circuit 17 includes: a twenty-third transistor M23, the control electrode of the twenty-third transistor M23 is connected to the first pull-down node PD1, and the first electrode of the twenty-third transistor M23 is connected to the first pull-down node PD1.
  • the third anti-leakage node Q3 is connected, and the second pole of the twenty-third transistor M23 is connected to the second power terminal.
  • FIG. 20 illustrates the case where the shift register unit includes the first anti-leakage circuit 15 , the first anti-leakage circuit 16 , and the third anti-leakage circuit 17 at the same time.
  • the first anti-leakage circuit 15 , the first anti-leakage circuit 16 , and the third anti-leakage circuit 17 can be provided according to actual needs.
  • the shift register unit further includes a first pull-down noise reduction circuit 18 and/or a second pull-down noise reduction circuit 19 .
  • the first pull-down noise reduction circuit 18 is connected to the first pull-down node PD1, the second power supply terminal, the sensing control node H and the first clock control signal input terminal CLKA, and the first pull-down noise reduction circuit 18 is configured to respond Controlling the effective level signal provided by the sensing control node H and the effective level signal provided by the first clock control signal input terminal CLKA, writing the inactive level signal provided by the second power supply terminal to the first pull-down node PD1 , to perform noise reduction processing on the output voltage of the first pull-down node PD1.
  • the second pull-down noise reduction circuit 19 is connected to the first pull-down node PD1, the second power terminal and the second sensing signal input terminal INPUT2_2.
  • the second pull-down noise reduction circuit 19 is configured to respond to the input signal of the second sensing signal input terminal INPUT2_2. Provide control of the valid level signal, and write the non-valid level signal provided by the second power supply terminal to the first pull-down node PD1 to perform noise reduction processing on the output voltage of the first pull-down node PD1.
  • the first pull-down noise reduction circuit 18 includes a twenty-ninth transistor M29 and a thirtieth transistor M30, and the second pull-down noise reduction circuit 19 includes a thirty-first transistor M31.
  • control electrode of the twenty-ninth transistor M29 is connected to the first clock control signal input terminal CLKA
  • first electrode of the twenty-ninth transistor M29 is connected to the first pull-down node PD1
  • second electrode of the twenty-ninth transistor M29 is connected to the first pull-down node PD1.
  • the first pole of the thirtieth transistor M30 is connected to the first pole of the thirtieth transistor M30.
  • the control electrode of the thirtieth transistor M30 is connected to the sensing control node H, and the second electrode of the thirtieth transistor M30 is connected to the second power terminal.
  • the control electrode of the thirty-first transistor M31 is connected to the second sensing signal input terminal INPUT2_2, the first electrode of the thirty-first transistor M31 is connected to the first pull-down node PD1, and the second electrode of the thirty-first transistor M31 is connected to the second sensing signal input terminal INPUT2_2.
  • the second power terminal is connected.
  • FIG. 21 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the disclosure. As shown in FIG. 21 , in the embodiment of the disclosure, an anti-leakage design is also carried out for the sensing control circuit.
  • the shift register unit further includes: a sensing control anti-leakage circuit 1a.
  • the sensing control circuit 1 is connected to the second sensing signal input terminal INPUT2_2 through the sensing control anti-leakage circuit 1a.
  • the sensing control circuit 1 The sensing control anti-leakage circuit 1a is connected to the sensing control anti-leakage node K, the sensing control anti-leakage node K is connected to the sensing preparation node Z; the sensing control anti-leakage circuit 1a is also connected to the third sensing signal input terminal INPUT2_3 connection, the sensing control anti-leakage circuit 1a is configured to respond to the control of the effective level signal provided by the third sensing signal input terminal INPUT2_2 so that a formation is formed between the sensing control anti-leakage node K and the second sensing signal input terminal INPUT2_2 path, and in response to the control of the non-effective level signal provided by the third sensing signal input terminal INPUT2_3, so that
  • the sensing control circuit 1 is designed to prevent leakage based on the voltage at the sensing preparation node Z.
  • the sensing control anti-leakage circuit 1a includes: a 72nd transistor M72; the control electrode of the 72nd transistor M72 is connected to the third sensing signal input terminal INPUT2_3, and the 72nd transistor M72 has a control electrode connected to the third sensing signal input terminal INPUT2_3.
  • One pole is connected to the second sensing signal input terminal INPUT2_2, and the second pole of the seventy-second transistor M72 is connected to the sensing control anti-leakage node K.
  • the 72nd transistor M72 When the third sensing signal input terminal INPUT2_3 provides a valid level signal, the 72nd transistor M72 is in a conductive state, and a path is formed between the sensing control leakage prevention node K and the second sensing signal input terminal INPUT2_2; in the third sensing signal input terminal INPUT2_2 When the third sensing signal input terminal INPUT2_3 provides an inactive level signal, the seventy-second transistor M72 is in a cut-off state, and an open circuit is formed between the sensing control anti-leakage node K and the second sensing signal input terminal INPUT2_2.
  • the first level supply terminal is a third power terminal.
  • the sensing control node H In the display output stage, the sensing control node H will be in a floating state for a long time, and the high-level voltage at the sensing control node H will be discharged through the sensing control circuit 1 and the second sensing signal input terminal INPUT2_2.
  • the sensing control anti-leakage circuit 1a is provided between the sensing control circuit 1 and the second sensing signal input terminal INPUT2_2, so that in the display output stage, the sensing control anti-leakage node K is connected to the third sensing signal input terminal INPUT2_2.
  • An open circuit is formed between the two sensing signal input terminals INPUT2_2, and at the same time, the high-level signal at the sensing preparation node Z is written to the sensing control anti-leakage node K, thereby effectively preventing the sensing control node H from passing through the sensing control circuit 1. Discharge to prevent leakage.
  • Figures 22A to 22D are schematic diagrams of various circuit structures of the sensing control circuit, the first sensing input circuit and the sensing control anti-leakage circuit in embodiments of the present disclosure. See Figures 22A and 22D.
  • the third sensing signal input terminal INPUT2_3 is the first sensing signal input terminal INPUT2_1.
  • the third sensing signal input terminal INPUT2_3 is the second sensing signal input terminal INPUT2_2.
  • the third sensing signal input terminal INPUT2_3 can also be a signal input terminal different from the first sensing signal input terminal INPUT2_1 and the second sensing signal input terminal INPUT2_2. This situation should also belong to scope of the present disclosure.
  • the gate drive circuit is configured with a random signal input line OE’.
  • one of the first sensing signal input terminal INPUT2_1 and the second sensing signal input terminal INPUT2_2 is connected to the random signal input line OE'.
  • Figure 22A, Figure 22B, and Figure 22D illustrate the situation where the first sensing signal input terminal INPUT2_1 is connected to the random signal input line OE';
  • Figure 22C illustrates the second sensing signal input terminal When INPUT2_2 is connected to the random signal input line OE'.
  • the display signal input terminal INPUT1 when one of the first sensing signal input terminal INPUT2_1 and the second sensing signal input terminal INPUT2_2 is connected to the random signal input line OE', one of the two The other is the display signal input terminal INPUT1; that is to say, the signal provided by the display signal input terminal INPUT1 can not only be provided to the first display input circuit 7 for use as a display driver cascade, but also can be provided to the sensing control circuit 1 for use. for pixel sensing cascade. Among them, FIG.
  • FIG. 22A exemplarily shows the situation where the first sensing signal input terminal INPUT2_1 is connected to the random signal input line OE' and the second sensing signal input terminal INPUT2_2 is the display signal input terminal INPUT1.
  • FIG. 22C exemplifies the situation.
  • the first sensing signal input terminal INPUT2_1 is the display signal input terminal INPUT1 and the second sensing signal input terminal INPUT2_2 is connected to the random signal input line OE'.
  • the other of the two can also be different from the display signal input terminal INPUT1 a signal input terminal.
  • the first sensing signal input terminal INPUT2_1 is connected to the random signal input line OE'
  • the third sensing signal input terminal INPUT2_3 and the second sensing signal input terminal INPUT2_2 are the same signal input terminal and Different from the display signal input terminal INPUT1.
  • the first sensing signal input terminal INPUT2_1 is connected to the random signal input line OE', and the second sensing signal input terminal INPUT2_2 is a signal input terminal different from the display signal input terminal INPUT1.
  • the third sensing signal input terminal INPUT2_3 is the display signal input terminal INPUT1.
  • any two of the first sensing signal input terminal INPUT2_1, the second sensing signal input terminal INPUT2_2, and the third sensing signal input terminal INPUT2_3 may be the same or different. This is not a limitation.
  • Figure 23 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • the shift register unit also includes: a first sensing input anti-leakage circuit 2a,
  • the sensing input sub-circuit 202 is connected to the sensing preparation node Z through the first sensing input anti-leakage circuit 2a.
  • the sensing input sub-circuit 202 and the first sensing input anti-leakage circuit 2a are connected to the first sensing input anti-leakage node.
  • the first sensing input anti-leakage circuit 2a is also connected to the first clock control signal input terminal CLKA, and the first sensing input anti-leakage circuit 2a is configured to respond to the effective level signal provided by the first clock control signal input terminal CLKA
  • the control is such that a path is formed between the first sensing input leakage prevention node Y1 and the sensing preparation node Z, and the control of the non-effective level signal provided by the first clock control signal input terminal CLKA is such that the first sensing An open circuit is formed between the input anti-leakage node Y1 and the sensing preparation node Z.
  • the first sensing input anti-leakage circuit 2a includes: a seventy-third transistor M73.
  • the control electrode of the 73rd transistor M73 is connected to the first clock control signal input terminal CLKA, the first electrode of the 73rd transistor M73 is connected to the sensing preparation node Z, and the second electrode of the 73rd transistor M73 is connected to the first clock control signal input terminal CLKA.
  • a sensing input is connected to the anti-leakage node Y1.
  • Figure 24 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure. As shown in Figure 24, it is another anti-leakage design of the sensing control circuit; in some embodiments, the shift register unit , also includes: a sensing control anti-leakage circuit 1a, the sensing control circuit is connected to the second sensing signal input terminal INPUT2_2 through the sensing control anti-leakage circuit 1a, the sensing control circuit and the sensing control anti-leakage circuit 1a are connected to the sensor The sensing control anti-leakage node K; the sensing control anti-leakage circuit 1a is also connected to the first sensing signal input terminal INPUT2_1, the sensing control node H and the third power supply terminal, and the sensing control anti-leakage circuit 1a is configured to respond to the first Control of the effective level signal provided by the sensing signal input terminal INPUT2_1, writing the effective level signal provided by the second sensing signal input terminal INPUT2_2 to the sensing control anti-
  • the sensing control anti-leakage circuit 1a includes: a seventy-fourth transistor M74 and a seventy-fifth transistor M75.
  • the control electrode of the seventy-fourth transistor M74 is connected to the first sensing signal input terminal INPUT2_1, the first electrode of the seventy-fourth transistor M74 is connected to the second sensing signal input terminal INPUT2_2, and the second electrode of the seventy-fourth transistor M74 is connected to the second sensing signal input terminal INPUT2_2.
  • the pole is connected to the sensing control anti-leakage node K.
  • the control electrode of the seventy-fifth transistor M75 is connected to the sensing control node H, the first electrode of the seventy-fifth transistor M75 is connected to the third power supply terminal, and the second electrode of the seventy-fifth transistor M75 is connected to the sensing control anti-leakage terminal. Node K is connected.
  • the first level supply terminal is the first clock control signal input terminal CLKA;
  • the shift register unit also includes: a first sensing input anti-leakage circuit 2a, connected to the sensing preparation node Z and the third voltage
  • the flat supply terminal is connected and configured to write the valid level signal provided by the third level supply terminal to the sensing preparation node Z in response to the control of the valid level signal provided by the third level supply terminal.
  • the third level supply terminal may be a first cascade signal output terminal, a first driving signal output terminal or a second driving signal output terminal.
  • the first sensing input anti-leakage circuit 2a includes: a seventy-sixth transistor M76; the control electrode of the seventy-sixth transistor M76 is connected to the third level supply end, and the third level of the seventy-sixth transistor M76 One pole is connected to the third level supply terminal, and the second pole of the seventy-sixth transistor M76 is connected to the sensing preparation node Z.
  • Figure 25 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • the shift register unit shown in Figure 25 not only includes the first sensing input circuit 1 in the previous embodiment,
  • the first display input circuit 7, the first switch circuit 61, and the first drive output circuit 5 also include: a second sensing input circuit 23, a second display input circuit 27, a second switch circuit 62, and a third drive output circuit 25. .
  • the second sensing input circuit 23 is connected to the first clock control signal input terminal CLKA, the sensing preparation node, and the second pull-up post node PUB2, and the second sensing input circuit 23 is configured to respond to the first clock control signal
  • the control of the effective level signal provided by the input terminal CLKA writes the signal at the sensing preparation node to the second pull-up post node PUB2.
  • the second display input circuit 27 is connected to the display signal input terminal INPUT1, the third power supply terminal and the second pull-up node PU2.
  • the second display input circuit 27 is configured to respond to the control of the effective level signal provided by the display signal input terminal INPUT1, Write the effective level signal provided by the third power terminal to the second pull-up node PU2.
  • the second switch circuit 62 is connected in series between the second pull-up node PU2 and the second pull-up post node PUB2.
  • the second switch circuit 62 is connected to the switch signal input terminal SW.
  • the second switch circuit 62 is configured to respond to the switch signal input. Control of the signal provided by terminal SW to control the connection between the second pull-up node PU2 and the second pull-up post node PUB2;
  • the third drive output circuit 25 is connected to the second pull-up post node PUB2, the third drive clock signal input terminal CLKE', and the third drive signal output terminal OUT2', and is configured to respond to the second pull-up
  • the control of the effective level signal at the post node PUB2 writes the signal provided by the third driving clock signal input terminal CLKE' to the third driving signal output terminal OUT2'.
  • the first drive output circuit 5 can be used to provide a corresponding drive signal to a second gate line configured in a certain row of pixel units in the display panel.
  • the third drive output circuit 25 can also be used to provide a corresponding drive signal to a second gate line configured in a certain row of pixel units in the display panel.
  • a second gate line configured in another row of pixel units in the display panel provides corresponding driving signals. That is to say, the shift register unit provided in this embodiment can be used to drive the second gate lines configured in two rows of pixel units (for example, two adjacent rows of pixel units).
  • the second switch circuit 62 can also effectively improve the stability of the third drive output circuit 25 outputting pulses for pixel sensing. Specifically, during the process of the third driving output circuit 25 outputting the pixel sensing pulse, the second pull-up post node PUB2 and the second pull-up node PU2 remain in an open circuit state, so the second display input circuit 27 The electrical device will not interfere with the voltage at the second pull-up post-node PUB2, so that the third drive output circuit 25 can have better stability in the process of outputting pulses for pixel sensing.
  • the second switch circuit 62 includes: an 81st transistor M81; the control electrode of the 81st transistor M81 is connected to the switch signal input terminal SW, and the first electrode of the 81st transistor M81 is connected to the second The pull-up node PU2 is connected, and the second pole of the eighty-first transistor M81 is connected to the second pull-up post node PUB2.
  • Figure 26 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • the shift register unit includes a first sensing input anti-leakage circuit 2a, and the sensing input sub-circuit 202 passes The first sensing input anti-leakage circuit 2a is connected to the sensing preparation node Z, and the sensing input sub-circuit 202 and the first sensing input anti-leakage circuit 2a are connected to the first sensing input anti-leakage node Y1.
  • the first sensing input anti-leakage circuit 2a is also connected to the first clock control signal input terminal CLKA.
  • the first sensing input anti-leakage circuit 2a is configured to respond to the control of the effective level signal provided by the first clock control signal input terminal CLKA. So that a path is formed between the first sensing input anti-leakage node Y1 and the sensing preparation node Z, and in response to the control of the non-effective level signal provided by the first clock control signal input terminal CLKA so that the first sensing input anti-leakage An open circuit is formed between the leakage node Y1 and the sensing preparation node Z.
  • the second sensing input circuit 23 is connected to the first sensing input leakage prevention node Y1 to be connected to the sensing preparation node z through the first sensing input leakage prevention circuit 2a.
  • the sensing input sub-circuit 202 and the second sensing input circuit 23 share the same first sensing input leakage prevention circuit 2a to achieve leakage prevention.
  • the first sensing input anti-leakage circuit 2a includes: a seventy-third transistor M73.
  • the control electrode of the 73rd transistor M73 is connected to the first clock control signal input terminal CLKA, the first electrode of the 73rd transistor M73 is connected to the sensing preparation node Z, and the second electrode of the 73rd transistor M73 is connected to the first clock control signal input terminal CLKA.
  • a sensing input is connected to the anti-leakage node Y1.
  • Figure 27 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • the sensing input sub-circuit 202 and the second sensing input circuit 23 in Figure 26 share the same first sensor. Different from the solution of sensing input leakage prevention circuit 2a to achieve leakage prevention, in the solution shown in Figure 27, the sensing input sub-circuit 202 implements leakage prevention through the first sensing input leakage prevention circuit 2a, and the second sensing input circuit 23 Anti-leakage is achieved through the second sensing input anti-leakage circuit 2b.
  • the second sensing input circuit 23 is connected to the sensing preparation node Z through the second sensing input anti-leakage circuit 2b, and the second sensing input circuit 23 and the second sensing input anti-leakage circuit 2b are connected to the second sensing node Z. Enter the anti-leakage node Y2.
  • the second sensing input anti-leakage circuit 2b is also connected to the first clock control signal input terminal CLKA.
  • the second sensing input anti-leakage circuit 2b is configured to respond to the control of the effective level signal provided by the first clock control signal input terminal CLKA. So that a path is formed between the second sensing input leakage prevention node Y2 and the sensing preparation node Z, and in response to the control of the non-effective level signal provided by the first clock control signal input terminal CLKA, the second sensing input leakage prevention node An open circuit is formed between the leakage node Y2 and the sensing preparation node Z.
  • the second sensing input anti-leakage circuit 2b includes: an eighty-third transistor M83.
  • the control electrode of the eighty-third transistor M83 is connected to the first clock control signal input terminal CLKA, the first electrode of the eighty-third transistor M83 is connected to the sensing preparation node Z, and the second electrode of the eighty-third transistor M83 is connected to the first clock control signal input terminal CLKA.
  • the second sensing input is connected to the anti-leakage node Y2.
  • Figure 28 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure. As shown in Figure 28, in some embodiments, the shift register unit also includes: a second display reset circuit 28 and a second global Reset circuit 26.
  • the second display reset circuit 28 is connected to the display reset signal input terminal RST, the second power supply terminal, and the second pull-up node PU2, and is configured to respond to the control of the effective level signal provided by the display reset signal input terminal RST.
  • the non-effective level signal provided by the two power terminals is written to the second pull-up node PU2.
  • the second global reset circuit 26 is connected to the global reset signal input terminal T-RST, the second power supply terminal, and the second pull-up node PU2, and is configured to respond to the control of the effective level signal provided by the global reset signal input terminal T-RST.
  • the inactive level signal provided by the second power terminal is written to the second pull-up node PU2.
  • the shift register unit further includes: a second sensing reset circuit 4, connected to the second clock control signal input terminal CLKB, the second level supply terminal and the second pull-up post node PUB2, configured as In response to the control of the valid level signal provided by the second clock control signal input terminal CLKB, the inactive level signal provided by the second level supply terminal is written to the second pull-up post node PUB2.
  • a second sensing reset circuit 4 connected to the second clock control signal input terminal CLKB, the second level supply terminal and the second pull-up post node PUB2, configured as In response to the control of the valid level signal provided by the second clock control signal input terminal CLKB, the inactive level signal provided by the second level supply terminal is written to the second pull-up post node PUB2.
  • the second sensing reset circuit 4 in the embodiment of the present disclosure can be used to reset the second pull-up post node, so that the second pull-up post node PUB2 is not reset. Then rely on the second global reset circuit 26 and the second switch circuit 62.
  • the second sensing reset circuit 4 includes: an eighty-seventh transistor M87.
  • the control electrode of the eighty-seventh transistor M87 is connected to the second clock control signal input terminal CLKB, the first electrode of the eighty-seventh transistor M87 is connected to the second pull-up post node PUB2, and the second electrode of the eighty-seventh transistor M87 is connected to the second pull-up post node PUB2.
  • the pole is connected to the second level supply terminal.
  • Figure 29 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • the shift register unit further includes: a fourth drive output circuit 29, a fourth driver
  • the output circuit 29 is connected to the second pull-up post node PUB2, the fourth drive clock signal input terminal CLKD', and the fourth drive signal output terminal OUT1', and is configured to respond to the effective level of the second pull-up post node PUB2
  • the control of the signal writes the signal provided by the fourth driving clock signal input terminal CLKD' to the fourth driving signal output terminal OUT1'.
  • the fourth drive signal output terminal OUT1' is connected to the first gate line in the pixel unit of the corresponding row to provide a drive signal to the first gate line of the corresponding row.
  • the first driving output circuit 5 and the second driving output circuit 9 can be respectively used to provide corresponding driving signals to a first gate line and a second gate line configured in a certain row of pixel units in the display panel.
  • the third driving output circuit 25 and the fourth driving output circuit 29 can be respectively used to provide corresponding driving signals to a first gate line and a second gate line configured in another row of pixel units in the display panel.
  • the shift register unit provided in this embodiment can be used to drive four gate lines configured in two rows of pixel units (for example, two adjacent rows of pixel units).
  • the shift register unit further includes: a second pull-down control circuit 31 and a second pull-up noise reduction circuit 32 .
  • the second pull-down control circuit 31 is connected to the second power terminal, the fifth power terminal, the second pull-up node PU2 and the second pull-down node PD2, and the second pull-down control circuit 31 is configured to write to the second pull-down node PD2 A voltage that is inverse to the voltage at the second pull-up node PU2.
  • the second pull-up noise reduction circuit 32 is connected to the second power terminal, the second pull-up node PU2 and the second pull-down node PD2.
  • the second pull-up noise reduction circuit 32 is configured to respond to the effective level signal at the second pull-down node PD2.
  • the control writes the non-effective level signal provided by the second power terminal to the second pull-up node PU2;
  • the third drive output circuit 25 is also connected to the second pull-down node PD2 and the fourth power supply terminal.
  • the third drive output circuit 25 is also configured to respond to the control of the effective level signal at the second pull-down node PD2 to provide the fourth power supply terminal.
  • the inactive level signal is written to the third drive signal output terminal OUT2'.
  • the fourth drive output circuit 29 is also connected to the second pull-down node PD2 and the fourth power supply terminal.
  • the fourth drive output circuit 29 is also configured to respond to the control of the effective level signal at the second pull-down node PD2 to provide the fourth power supply terminal.
  • the inactive level signal is written to the fourth drive signal output terminal OUT1'.
  • Figure 30 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure. As shown in Figure 30, the shift register unit shown in Figure 30 is an embodiment based on the shift register unit shown in Figure 29 Alternative implementations.
  • the sensing control circuit 1, the first pull-up noise reduction circuit 12, the first drive output circuit 5, the second drive output circuit 9, and the first cascade output circuit 13 please refer to the content in the previous embodiment, here No longer.
  • the second sensing input circuit 23 includes: a thirty-second transistor M32; the control electrode of the thirty-second transistor M32 is connected to the sensing control node H, and the first electrode of the thirty-second transistor M32 is connected to the first clock control signal input
  • the terminal CLKA is connected, and the second pole of the thirty-second transistor M32 is connected to the second pull-up node PU2.
  • the second switch circuit 62 includes: an 81st transistor M81; the control electrode of the 81st transistor M81 is connected to the switch signal input terminal SW, and the first electrode of the 81st transistor M81 is connected to the second The pull-up node PU2 is connected, and the second pole of the eighty-first transistor M81 is connected to the second pull-up post node PUB2.
  • the second display input circuit 27 includes a thirty-ninth transistor M39.
  • the control electrode of the thirty-ninth transistor M39 is connected to the display signal input terminal INPUT1, the first electrode of the thirty-ninth transistor M39 is connected to the third power supply terminal, and the second electrode of the thirty-ninth transistor M39 is connected to the second pull-up node. PU2 connection.
  • the third drive output circuit 25 includes the thirty-fifth transistor M35 and the forty-seventh transistor M47, and the fourth drive output circuit 29 includes the forty-fifth transistor M45 and the forty-eighth transistor M48.
  • control electrode of the thirty-fifth transistor M35 is connected to the second pull-up post node PUB2
  • the first electrode of the thirty-fifth transistor M35 is connected to the third driving clock signal input terminal CLKE'
  • the thirty-fifth transistor M35 The second pole is connected to the third drive signal output terminal OUT2'.
  • the control electrode of the forty-seventh transistor M47 is connected to the second pull-down node PD2, the first electrode of the forty-seventh transistor M47 is connected to the third drive signal output terminal OUT2', and the second electrode of the forty-seventh transistor M47 is connected to the third drive signal output terminal OUT2'.
  • the control electrode of the forty-fifth transistor M45 is connected to the second pull-up post node PUB2, the first electrode of the forty-fifth transistor M45 is connected to the fourth drive clock signal input terminal CLKD', and the first electrode of the forty-fifth transistor M45 is connected to the fourth drive clock signal input terminal CLKD'.
  • the two poles are connected to the fourth drive signal output terminal OUT1'.
  • the control electrode of the forty-eighth transistor M48 is connected to the second pull-down node PD2, the first electrode of the forty-eighth transistor M48 is connected to the fourth drive signal output terminal OUT1', and the second electrode of the forty-eighth transistor M48 is connected to the fourth drive signal output terminal OUT1'.
  • a fourth capacitor C4 is configured for the third driving signal output terminal OUT2'.
  • the second global reset circuit 26 includes the thirty-seventh transistor M37
  • the second display reset circuit 28 includes the fortieth transistor M40
  • the second pull-down control circuit 31 includes the forty-second transistor M42 and the fortieth transistor M40.
  • Three transistors M43, the second pull-up noise reduction circuit 32 includes a forty-fourth transistor M44.
  • the control electrode of the thirty-seventh transistor M37 is connected to the global reset signal input terminal T-RST, the first electrode of the thirty-seventh transistor M37 is connected to the second pull-up node PU2, and the second electrode of the thirty-seventh transistor M37 is connected to the global reset signal input terminal T-RST. Inactive level supply terminal connection.
  • the control electrode of the fortieth transistor M40 is connected to the display reset signal input terminal RST, the first electrode of the fortieth transistor M40 is connected to the second pull-up node PU2, and the second electrode of the fortieth transistor M40 is connected to the non-effective level supply end connection.
  • the control electrode of the forty-second transistor M42 is connected to the sixth power supply terminal, the first electrode of the forty-second transistor M42 is connected to the sixth power supply terminal (the sixth power supply terminal provides voltage VDDB), and the first electrode of the forty-second transistor M42 is connected to the sixth power supply terminal.
  • the two poles are connected to the second pull-down node PD2.
  • the control electrode of the 43rd transistor M43 is connected to the second pull-up node PU2, the first electrode of the 43rd transistor M43 is connected to the second pull-down node PD2, and the second electrode of the 43rd transistor M43 is connected to the inactive voltage.
  • Flat supply side connection
  • the control electrode of the forty-fourth transistor M44 is connected to the second pull-down node PD2, the first electrode of the forty-fourth transistor M44 is connected to the second pull-up node PU2, and the second electrode of the forty-fourth transistor M44 is connected to the inactive voltage.
  • Flat supply side connection
  • the fifth power terminal provides voltage VDDA and the sixth power terminal provides voltage VDDB.
  • VDDA and VDDB can switch between high-level voltage and low-level voltage (for example, every 1 frame or several frames). Perform a switch), and at any time one of VDDA and VDDB is a high-level voltage, and the other is a low-level voltage.
  • a second cascade output circuit (not shown) may also be included in the shift register unit.
  • the second cascade output circuit is connected to the second pull-up node, the second cascade clock signal input terminal, and the second cascade signal output terminal, and the second cascade output circuit is configured to respond to the effective level at the second pull-up node.
  • the control of the signal writes the signal provided by the second cascaded clock signal input terminal to the second cascaded signal output terminal.
  • the second cascade output circuit may also be connected to the second power terminal and the first pull-down node, and the second cascade output circuit is configured to respond to the control of the active level signal at the second pull-down node, Write the non-effective level signal provided by the second power supply terminal to the second cascade signal output terminal.
  • Figure 31 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • the shift register unit includes a second global reset circuit 26, a second When displaying the reset circuit 28 and the second pull-up noise reduction circuit 32, an anti-leakage design can be performed for at least one of the second global reset circuit 26, the second display reset circuit 28 and the first pull-up noise reduction circuit 32.
  • the shift register unit also includes: a second voltage control circuit 34; the second voltage control circuit 34 is connected to the third power supply terminal, the second pull-up node PU1, and the second voltage control node OFF2.
  • the voltage circuit 34 is configured to write the effective level signal provided by the third power supply terminal to the second voltage control node OFF2 in response to the control of the effective level signal at the second pull-up node PU2.
  • the shift register unit also includes: at least one of a fourth anti-leakage circuit 35 , a fifth anti-leakage circuit 36 , and a sixth anti-leakage circuit 37 .
  • the second global reset circuit 26 is connected to the second power terminal through the fourth anti-leakage circuit 35.
  • the second global reset circuit 26 and the fourth anti-leakage circuit 35 are connected to the fourth anti-leakage node Q4.
  • the fourth anti-leakage node Q4 Connected to the second voltage control node OFF2, the fourth anti-leakage circuit 35 is connected to the sensing reset signal input terminal T-RST.
  • the fourth anti-leakage circuit 35 is configured to respond to the effective power provided by the sensing reset signal input terminal T-RST.
  • the control of the flat signal causes a path to be formed between the fourth anti-leakage node Q4 and the second power supply terminal, and the control of the non-effective level signal provided by the cascade reset signal input terminal causes the fourth anti-leakage node Q4 to connect to the second power supply terminal. Break between terminals.
  • the second display reset circuit 28 is connected to the second power terminal through the fifth anti-leakage circuit 36.
  • the second display reset circuit 28 and the fifth anti-leakage circuit 36 are connected to the fifth anti-leakage node Q5.
  • the fifth anti-leakage node Q5 is connected to the fifth anti-leakage node Q5.
  • the second voltage control node OFF2 is connected, the fifth anti-leakage circuit 36 is connected with the display reset signal input terminal RST, and the fifth anti-leakage circuit 36 is configured to control the effective level signal provided by the display reset signal input terminal RST so that the fifth anti-leakage circuit 36 is connected.
  • a path is formed between the leakage node Q5 and the second power terminal, and the fifth anti-leakage node Q5 and the second power terminal are disconnected in response to the control of the non-effective level signal provided by the cascade reset signal input terminal.
  • the second pull-up noise reduction circuit 32 is connected to the second power terminal through the sixth leakage prevention circuit 37.
  • the second pull-up noise reduction circuit 32 and the sixth leakage prevention circuit 37 are connected to the sixth leakage prevention node Q6.
  • the sixth leakage prevention circuit 37 is connected to the sixth leakage prevention node Q6.
  • the node Q6 is connected to the second voltage control node OFF2
  • the sixth anti-leakage circuit 37 is connected to the second pull-down node PD2
  • the sixth anti-leakage circuit 37 is configured to respond to the control of the effective level signal at the second pull-down node PD2 so that the sixth A path is formed between the anti-leakage node Q6 and the second power terminal, and in response to the control of the inactive level signal at the second pull-down node PD2, the sixth anti-leakage node Q6 and the second power terminal are disconnected.
  • the second voltage control circuit 34 includes a fiftieth transistor M50.
  • the control electrode of the fiftieth transistor M50 is connected to the first pull-up node PU1.
  • the first electrode of the fiftieth transistor M50 is connected to the effective level supply. terminal is connected, and the second pole of the fiftieth transistor M50 is connected to the second voltage control node OFF2.
  • the fourth anti-leakage circuit 35 includes a fifty-first transistor M51, the control electrode of the fifty-first transistor M51 is connected to the sensing reset signal input terminal T-RST, and the first terminal of the fifty-first transistor M51 The second pole of the fifty-second transistor M52 is connected to the second power terminal.
  • the fifth anti-leakage circuit 36 includes a fifty-second transistor M52, a control electrode of the fifty-second transistor M52 is connected to the display reset signal input terminal RST, and a first electrode of the fifty-second transistor M52 is connected to the display reset signal input terminal RST.
  • the reset circuit is connected to the second voltage control node OFF2, and the second pole of the fifty-second transistor M52 is connected to the second power terminal.
  • the sixth anti-leakage circuit 37 includes: a fifty-third transistor M53, the control electrode of the fifty-third transistor M53 is connected to the second pull-down node PD2, and the first electrode of the fifty-third transistor M53 is connected to the second pull-down node PD2.
  • the second pull-down control circuit is connected to the second voltage control node OFF2, and the second pole of the fifty-third transistor M53 is connected to the second power terminal.
  • FIG. 31 illustrates a case where the shift register unit includes a fourth leakage prevention circuit 35 , a fifth leakage prevention circuit 36 , and a sixth leakage prevention circuit 37 at the same time.
  • the fourth anti-leakage circuit 35 , the fifth anti-leakage circuit 36 , and the sixth anti-leakage circuit 37 can be provided according to actual needs.
  • the shift register unit further includes a third pull-down noise reduction circuit 38 and/or a fourth pull-down noise reduction circuit 39 .
  • the third pull-down noise reduction circuit 38 is connected to the second pull-down node PD2, the second power terminal, the sensing control node H and the clock control signal input terminal CLKA, and the first pull-down noise reduction circuit 18 is configured to respond to the sensing control
  • the effective level signal at node H and the effective level signal provided by the clock control signal input terminal CLKA are controlled by writing the inactive level signal provided by the second power supply terminal to the first pull-down node PD1 to control the first pull-down node. Pull the output voltage of node PD1 for noise reduction processing.
  • the fourth pull-down noise reduction circuit 39 is connected to the second pull-down node PD2, the second power supply terminal and the second sensing signal input terminal INPUT2_2.
  • the second pull-down noise reduction circuit 19 is configured to respond to the input signal provided by the second sensing signal input terminal INPUT2_2.
  • the effective level signal is controlled by writing the non-effective level signal provided by the second power supply terminal to the first pull-down node PD1 to perform noise reduction processing on the output voltage of the first pull-down node PD1.
  • the third pull-down noise reduction circuit 38 includes the fifty-ninth transistor M59 and the sixtieth transistor M60, and the fourth pull-down noise reduction circuit 39 includes the sixty-first transistor M61.
  • control electrode of the fifty-ninth transistor M59 is connected to the first clock control signal input terminal CLKA, the first electrode of the fifty-ninth transistor M59 is connected to the second pull-down node PD2, and the second electrode of the fifty-ninth transistor M59 Connected to the first pole of the sixtieth transistor M60.
  • the control electrode of the sixtieth transistor M60 is connected to the sensing control node H, and the second electrode of the sixtieth transistor M60 is connected to the second power terminal.
  • the control electrode of the sixty-first transistor M61 is connected to the second sensing signal input terminal, the first electrode of the sixty-first transistor M61 is connected to the second pull-down node PD2, and the second electrode of the sixty-first transistor M61 is connected to the second pull-down node PD2. Power terminal connection.
  • Figure 32 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • the shift register unit includes a second sensing reset circuit 4.
  • the test reset circuit 4 is connected to the second clock control signal input terminal CLKB, the second level supply terminal and the second pull-up post node PUB2, and is configured to respond to the effective level signal provided by the second clock control signal input terminal CLKB. Control to write the non-effective level signal provided by the second level supply terminal to the second pull-up post-node PUB2.
  • the shift register unit also includes: a second sensing reset anti-leakage circuit 4b, the second sensing reset circuit is connected to the second level supply end through the second sensing reset anti-leakage circuit 4b; the second sensing reset anti-leakage circuit 4b is also connected to the second pull-down node PD2, and the second sensing reset anti-leakage circuit is configured to respond to the control of the effective level signal at the second pull-down node PD2 to cause the second sensing reset circuit to communicate with the second level supply A path is formed between the terminals, and an open circuit is formed between the first sensing reset circuit and the second level supply terminal in response to the control of the inactive level signal at the second pull-down node PD2.
  • the second sensing reset anti-leakage circuit 4b includes: the eighty-eighth transistor M88; the control electrode of the eighty-eighth transistor M88 is connected to the second pull-down node PD2, and the first pin of the eighty-eighth transistor M88 The second pole of the eighty-eighth transistor M88 is connected to the second level supply end.
  • the second sensing reset anti-leakage circuit 4b in the embodiment of the present disclosure can effectively prevent the second pull-up post-node PUB2 from passing through the second sensing reset circuit 4,
  • the second level supply terminal discharges.
  • Figure 33 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • the shift register unit includes a first sensing reset Anti-leakage circuit 3a, the first sensing reset circuit 3 is connected to the second level supply end through the first sensing reset anti-leakage circuit 3a; the first sensing reset anti-leakage circuit 3a is also connected to the first pull-down node PD1,
  • the first sensing reset anti-leakage circuit 3a is configured to form a path between the first sensing reset circuit 3 and the second level supply end in response to the control of the effective level signal at the first pull-down node PD1, and in response to The inactive level signal at the first pull-down node PD1 is controlled to form an open circuit between the first sensing reset circuit 3 and the second level supply end.
  • the first sensing reset anti-leakage circuit 3a is also connected to the second pull-down node PD2, and the first sensing reset anti-leakage circuit 3a is also configured to respond to the control of the effective level signal at the second pull-down node PD2 so that the first sensing A path is formed between the reset circuit 3 and the second level supply end, and in response to the control of the inactive level signal at the second pull-down node PD2, a path is formed between the first sensing reset circuit 3 and the second level supply end. Break circuit.
  • the second sensing reset anti-leakage circuit 3b is also connected to the first pull-down node PD1, and the first sensing reset anti-leakage circuit 3a is further configured to respond to the control of the effective level signal at the first pull-down node PD1 so that the second A path is formed between the sensing reset circuit 4 and the second level supply terminal, and in response to the control of the inactive level signal at the first pull-down node PD1, the second sensing reset circuit 4 is connected to the second level supply terminal. A break is formed between them.
  • the first sensing reset anti-leakage circuit 3a includes: a seventy-eighth transistor M78 and a seventy-ninth transistor M79;
  • the second sensing reset anti-leakage circuit 3b includes: the eighty-eighth transistor M88 and the eighty-ninth transistor M89;
  • the control electrode of the seventy-eighth transistor M78 is connected to the first pull-down node PD1, the first electrode of the seventy-eighth transistor M78 is connected to the first sensing reset anti-leakage circuit 3a, and the second electrode of the seventy-eighth transistor M78 Connected to the second level supply terminal.
  • the control electrode of the seventy-ninth transistor M79 is connected to the second pull-down node PD2, the first electrode of the seventy-ninth transistor M79 is connected to the first sensing reset anti-leakage circuit 3a, and the second electrode of the seventy-ninth transistor M79 is connected to the second pull-down node PD2.
  • the second level supply terminal is connected.
  • the control electrode of the eighty-eighth transistor M88 is connected to the second pull-down node PD2, the first electrode of the eighty-eighth transistor M88 is connected to the second sensing reset anti-leakage circuit 3b, and the second electrode of the eighty-eighth transistor M88 is connected to the second pull-down node PD2.
  • the second level supply terminal is connected.
  • the control electrode of the eighty-ninth transistor M89 is connected to the first pull-down node PD1, the first electrode of the eighty-ninth transistor M89 is connected to the second sensing reset anti-leakage circuit 3b, and the second electrode of the eighty-ninth transistor M89 Connected to the second level supply terminal.
  • the shift register unit includes a second sensing input circuit, a second display input circuit, a second switching circuit and a third driving output circuit
  • the shift in these embodiments can also work using any of the working sequences shown in Figures 8 to 11, Figure 14A, and Figure 14B.
  • circuit structure of a new shift register unit is obtained by combining some of the circuit structures in the above embodiments.
  • the circuit structure of the new shift register unit obtained by the combination shall also fall under the protection of the present disclosure. scope.
  • Figure 34 is a schematic circuit structure diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • the shift register unit includes: a sensing control circuit 1, a first sensing input circuit 2, a sensing The leakage prevention circuit 1a and the first drive output circuit 5 are controlled.
  • the sensing control circuit 1 is connected to the first sensing signal input terminal INPUT2_1, the second sensing signal input terminal INPUT2_2, and the sensing control node H, and the sensing control circuit 1 is configured to respond to the first sensing signal input terminal INPUT2_1
  • the effective level signal provided by the second sensing signal input terminal INPUT2_2 is controlled by writing the effective level signal provided by the second sensing signal input terminal INPUT2_2 to the sensing control node H.
  • the first sensing input circuit 2 includes: a sensing input preparation sub-circuit 201 and a sensing input sub-circuit 202; wherein the sensing input preparation sub-circuit 201 is connected with the sensing preparation node Z, the sensing control node H, the first level The supply end is connected, and the sensing input preparation sub-circuit 201 is configured to write the signal provided by the first level supply end to the sensing preparation node Z in response to the control of the effective level signal provided by the sensing control node H; sensing The input sub-circuit 202 is connected to the sensing preparation node Z, the first clock control signal input terminal CLKA, and the first pull-up post node PUB1.
  • the sensing input sub-circuit 202 is configured to respond to the input signal provided by the first clock control signal input terminal CLKA. Under the control of the effective level signal, the signal at the sensing preparation node Z is written to the first pull-up post-node PUB1.
  • the sensing control circuit 1 is connected to the second sensing signal input terminal through the sensing control anti-leakage circuit 1a.
  • the sensing control circuit and the sensing control anti-leakage circuit 1a are connected to the sensing control anti-leakage node K.
  • the sensing control anti-leakage node Node K is connected to the sensing preparation node Z; the sensing control anti-leakage circuit 1a is also connected to the third sensing signal input terminal INPUT2_3, and the sensing control anti-leakage circuit 1a is configured to respond to the input signal provided by the third sensing signal input terminal INPUT2_3
  • the control of the effective level signal so that the sensing control leakage prevention node K forms a path with the second sensing signal input terminal INPUT2_2, and the control of the non-effective level signal in response to the third sensing signal input terminal INPUT2_3 provided so that the sensing
  • the measurement control anti-leakage node K forms an open circuit with the second sensing signal input terminal INPUT2_2.
  • the first drive output circuit 5 is connected to the first pull-up post node PUB1, the first drive clock signal input terminal CLKE, and the first drive signal output terminal OUT2, and is configured to respond to the effective level of the first pull-up post node PUB1
  • the signal is controlled by writing the signal provided by the first driving clock signal input terminal CLKE to the first driving signal output terminal OUT2.
  • the sensing control circuit 1 is designed to prevent leakage based on the voltage at the sensing preparation node Z.
  • the third sensing signal input terminal INPUT2_3 is the first sensing signal input terminal INPUT2_1 or the second sensing signal input terminal INPUT2_2.
  • the shift register unit further includes: a first display input circuit 7, connected to the display signal input terminal INPUT1, the third power supply terminal and the first pull-up node PU1, configured to respond to the display signal input terminal INPUT1. Provide control of the effective level signal, and write the effective level signal provided by the third power supply terminal to the first pull-up node PU1; the first pull-up node PU1 is connected to the first pull-up post node PUB1.
  • the sensing control anti-leakage circuit 1a includes: a 72nd transistor M72; the control electrode of the 72nd transistor M72 is connected to the third sensing signal input terminal INPUT2_3, and the 72nd transistor M72 has a control electrode connected to the third sensing signal input terminal INPUT2_3.
  • One pole is connected to the second sensing signal input terminal INPUT2_2, and the second pole of the seventy-second transistor M72 is connected to the sensing control anti-leakage node K.
  • the 72nd transistor M72 When the third sensing signal input terminal INPUT2_3 provides a valid level signal, the 72nd transistor M72 is in a conductive state, and a path is formed between the sensing control leakage prevention node K and the second sensing signal input terminal INPUT2_2; in the third sensing signal input terminal INPUT2_2 When the third sensing signal input terminal INPUT2_3 provides an inactive level signal, the seventy-second transistor M72 is in a cut-off state, and an open circuit is formed between the sensing control anti-leakage node K and the second sensing signal input terminal INPUT2_2.
  • the first level supply terminal is a third power terminal.
  • the second drive output circuit, the first switch circuit, the first sensing reset circuit, and the first sensing reset anti-leakage circuit in the previous embodiment can also be optionally included.
  • FIG. 35 is a schematic circuit structure diagram of a gate drive circuit provided by an embodiment of the present disclosure.
  • the gate drive circuit includes a plurality of cascaded shift register units SRU1-SRU3, wherein the shift register The units SRU1 to SRU3 may use the shift register unit provided in any of the previous embodiments.
  • the shift register unit please refer to the content in the previous embodiments and will not be described again here.
  • each shift register unit SRU1 to SRU3 is used to drive gate lines corresponding to two rows of pixel units. That is to say, the shift register unit includes a first driving output circuit 5 and a second driving output circuit. circuit 9, the third drive output circuit 25, the fourth drive output circuit 29 and the first cascade output circuit 13.
  • each stage of shift register units SRU1 to SRU3 can be regarded as two shift register circuits, such as Bit register unit SRU1 includes shift register circuits SR1 and SR2, shift register unit SRU2 includes shift register circuits SR3 and SR4, and shift register unit SRU3 includes shift register circuits SR5 and SR6.
  • N shift register units can be configured in the gate drive circuit, and the N shift register units are cascaded, which can be regarded as a cascade of 2N shift register circuits.
  • the shift register circuit SR2n-1 located at the odd-numbered position is configured with a first sensing signal input terminal, a second sensing signal input terminal, and a first cascade signal output terminal CR
  • the shift register circuit SR2n-1 located at the even-numbered position is not configured with a first sensing signal input terminal, a second sensing signal input terminal, and a first cascade signal output terminal CR, where 1 ⁇ n ⁇ N and n is an integer.
  • FIG. 35 only illustrates the case of the three-stage shift register units SRU1 to SRU3 (the six-stage shift register circuits SR1 to SR6), and this case serves only as an example.
  • the second sensing signal input terminals of the shift register units SRU1 to SRU3 at each level are connected to their own configured first cascade signal output terminals CR or to the third level shift register units of other levels.
  • a cascade signal output terminal CR (for example, the first cascade signal output terminal of a shift register unit in the previous stage a, or the first cascade signal output terminal of a shift register unit in the subsequent stage a, a is positive integer) are connected;
  • the first clock control signal input terminal CLKA of the shift register units SRU1 ⁇ SRU3 at each level is connected to the first clock control signal line CKA;
  • the second clock control signal input terminal of the shift register units SRU1 ⁇ SRU3 at each level is connected CLKB is connected to the second clock control signal line CKB;
  • the global reset signal input terminal T-RST of the shift register units SRU1 to SRU3 at each level is connected to the global reset signal input line TRST', and the first sensing terminal of the shift register unit at each level is connected to the global reset signal input
  • the display signal input terminal INPUT1 located in the first-level shift register unit SRU1 is connected to the frame start signal input terminal STV.
  • the shift register unit The display signal input terminal INPUT1 of the register unit is connected to the first cascade signal output terminal CR of the previous stage shift register unit; the global reset signal input terminal T-RST of each level shift register unit is connected to the global reset signal supply terminal TRST. 'Connection; the display reset signal input terminal RST of the shift register unit located at the Nth level and the shift register unit located at the N-1th level is connected to the frame end reset signal line, except for the display reset signal input terminal RST located at the Nth level and the N-1th level.
  • the display reset signal input terminal RST of the shift register unit is connected to the first cascade signal output terminal CR of the two subsequent stage shift register units.
  • the gate driving circuit is configured with 6 first driving clock signal lines CKE1 ⁇ CKE6 and 6 second driving clock signal lines CKD1 ⁇ CKD6;
  • the first driving clock signal input terminal CLKE located at the 3i+1-level shift register unit SRU3i+1 is connected to the first driving clock signal line CKE1, and the second driving clock located at the 3i+1-level shift register unit SRU3i+1
  • the signal input terminal CLKD is connected to the second driving clock signal line CKD1 and is located at the 3i+1th stage shift register unit SRU3i+1.
  • the third driving clock signal input terminal CLKE' is connected to the second driving clock signal line CKE2 and is located at the 3ith stage.
  • the fourth driving clock signal input terminal CLKD' of the +1-stage shift register unit SRU3i+1 is connected to the second driving clock signal line CKD2.
  • the first driving clock signal input terminal CLKE located at the 3i+2-level shift register unit SRU3i+2 is connected to the first driving clock signal line CKE3, and the second driving clock located at the 3i+2-level shift register unit SRU3i+2
  • the signal input terminal CLKD is connected to the second driving clock signal line CKD3 and is located at the 3i+2-stage shift register unit SRU3i+2.
  • the third driving clock signal input terminal CLKE' is connected to the second driving clock signal line CKE4 and is located at the 3i-th level.
  • the fourth driving clock signal input terminal CLKD' of the +2-stage shift register unit SRU3i+2 is connected to the second driving clock signal line CKD4.
  • the first driving clock signal input terminal CLKE located at the 3i+3-level shift register unit SRU3i+3 is connected to the first driving clock signal line CKE5, and the second driving clock located at the 3i+3-level shift register unit SRU3i+3
  • the signal input terminal CLKD is connected to the second driving clock signal line CKD5 and is located at the 3i+3rd level shift register unit SRU3i+3.
  • the third driving clock signal input terminal CLKE' is connected to the second driving clock signal line CKE6 and is located at the 3ith level.
  • the fourth driving clock signal input terminal CLKD' of the +3-stage shift register unit SRU3i+3 is connected to the second driving clock signal line CKD6.
  • i is a positive integer and 3i+3 ⁇ N.
  • an embodiment of the present disclosure also provides a display panel, wherein the display panel includes the gate driving circuit provided in the previous embodiment.
  • the gate driving circuit provided in the previous embodiment.
  • the gate driving circuit is prepared on the array substrate of the display panel using GOA.
  • an embodiment of the present disclosure also provides a display device.
  • the display device includes the display panel provided in the previous embodiment.
  • the display panel provided in the previous embodiment.
  • the display panel please refer to the content in the previous embodiment, which will not be discussed here. Again.
  • the display device can be any product or component with a display function, such as a liquid crystal display screen, a wearable device, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • a display function such as a liquid crystal display screen, a wearable device, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • Other essential components of the display device are understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used to limit the present disclosure.
  • FIG. 36 is a method flow chart of a gate driving method provided by an embodiment of the present disclosure. As shown in Figure 36, the gate driving method includes:
  • Step S101 The first switch circuit responds to the control of the effective level signal provided by the switch signal input terminal to form a path between the first pull-up node and the first pull-up post-node, and the sensing control circuit responds to the first sensing
  • the effective level signal provided by the second sensing signal input terminal is controlled by writing the effective level signal provided by the second sensing signal input terminal to the sensing control node
  • the first display input circuit responds to the effective level signal provided by the display signal input terminal.
  • the control of the signal writes the effective level signal provided by the third power supply terminal to the first pull-up node and the first pull-up post-node
  • the first drive output circuit responds to the effective level signal at the first pull-up post-node.
  • the control writes the signal provided by the first driving clock signal input terminal to the first driving signal output terminal.
  • Step S102 The first sensing input circuit responds to the control of the effective level signal at the sensing control node and the effective level signal provided by the first clock control signal input end, and converts the effective level signal provided by the first level supply end. Write to the first pull-up post node.
  • Step S103 The first switch circuit responds to the control of the effective level signal provided by the switch signal input terminal to form an open circuit between the first pull-up node and the first pull-up post-node, and the first drive output circuit responds to the first The control of the active level signal at the post-pull-up node writes the signal provided by the first driving clock signal input terminal to the first driving signal output terminal.

Abstract

Une unité de registre à décalage, celle-ci comprenant : un circuit de commande de détection (1) conçu pour écrire un signal de niveau effectif fourni par une deuxième extrémité d'entrée de signal de détection (INPUT2_1) dans un nœud de commande de détection (H) ; un premier circuit d'entrée de détection (2) connecté à un premier nœud arrière d'excursion haute (PUB1) et conçu pour écrire un signal de niveau effectif fourni par une extrémité d'alimentation de premier niveau dans le premier nœud arrière d'excursion haute (PUB1) ; un premier circuit d'entrée d'affichage (7) connecté à un premier nœud d'excursion haute (PU1) et conçu pour écrire un signal de niveau effectif fourni par une troisième extrémité d'alimentation électrique dans le premier nœud d'excursion haute (PU1) ; un premier circuit de commutation (61) connecté en série entre le premier nœud d'excursion haute (PU1) et le premier nœud arrière d'excursion haute (PUB1) et conçu pour commander la connexion et la déconnexion entre le premier nœud d'excursion haute (PU1) et le premier nœud arrière d'excursion haute (PUB1) en réponse à la commande d'un signal fourni par une extrémité d'entrée de signal de commutation (SW) ; et un premier circuit de sortie d'attaque (5) connecté au premier nœud arrière d'excursion haute (PUB1) et conçu pour écrire un signal fourni par une première extrémité d'entrée de signal d'horloge d'attaque (CLKE) dans une première extrémité de sortie de signal d'attaque (OUT2).
PCT/CN2022/106996 2022-07-21 2022-07-21 Unité de registre à décalage, circuit d'attaque de grille et procédé d'attaque de grille WO2024016256A1 (fr)

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