WO2021147990A1 - Registre à décalage, circuit d'attaque de grille, dispositif d'affichage et procédé d'attaque de grille - Google Patents

Registre à décalage, circuit d'attaque de grille, dispositif d'affichage et procédé d'attaque de grille Download PDF

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Publication number
WO2021147990A1
WO2021147990A1 PCT/CN2021/073253 CN2021073253W WO2021147990A1 WO 2021147990 A1 WO2021147990 A1 WO 2021147990A1 CN 2021073253 W CN2021073253 W CN 2021073253W WO 2021147990 A1 WO2021147990 A1 WO 2021147990A1
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WIPO (PCT)
Prior art keywords
signal
transistor
sensing
terminal
level state
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PCT/CN2021/073253
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English (en)
Chinese (zh)
Inventor
冯雪欢
李永谦
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京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Priority to US17/427,607 priority Critical patent/US11545093B2/en
Publication of WO2021147990A1 publication Critical patent/WO2021147990A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a shift register, a gate driving circuit, a display device, and a gate driving method.
  • the array substrate row drive (Gate Driver on Array, GOA) technology is used to integrate transistors on the array substrate to scan and drive the gate lines in the display panel, thereby eliminating the need for gate driver ICs. Partly, it is conducive to the realization of the narrow frame.
  • each gate drive unit in the gate drive circuit (consisting of multiple gate drive units connected in cascade) is not only able to output and control the display switch transistor to be turned on during the display drive stage.
  • the driving signal can also output a driving signal for controlling the conduction of the sensing switch transistor during the sensing phase, that is, the gate driving unit needs to have the function of outputting double pulses.
  • the shift register in the related art can only output a single pulse signal, a case where one gate driving unit includes only one shift register (Shift Register) cannot meet the driving requirement.
  • the gate driving unit has the function of outputting double pulses.
  • the gate driving unit includes two shift registers and a signal combining circuit, the number of transistors required to be provided is relatively large, which is not conducive to the realization of a narrow frame.
  • an embodiment of the present disclosure provides a shift register, including: a display precharge reset circuit, a sensing control circuit, a sensing precharge reset circuit, a pull-down control circuit, a display noise reduction circuit, and an output circuit.
  • the sensing control circuit, the sensing precharge reset circuit are connected to the sensing control node, the display precharge reset circuit, the sensing precharge reset circuit, the pull-down control circuit, and the output circuit are connected to the A pull-down node, the pull-down control circuit, the display noise reduction circuit, and the output circuit are connected to the pull-down node, the output circuit is configured with at least one signal output terminal, and the output circuit includes one-to-one with the signal output terminal.
  • the display pre-charge reset circuit is connected to a first signal input terminal, a second signal input terminal, a first scanning power terminal, and a second scanning power terminal, and is configured to respond to the control of the first signal input terminal to switch the first signal input terminal
  • a first scan voltage provided by a scan power terminal is written into the pull-up node; and, in response to the control of the second signal input terminal, a second scan voltage provided by the second scan power terminal is written into the upper Pull node
  • the sensing control circuit is connected to a signal output terminal and a random signal terminal, and is configured to write the output signal provided by the signal output terminal to the sensing control node in response to the control of the random signal terminal;
  • the sensing pre-charge reset circuit is connected to the first clock signal terminal, the sensing reset signal terminal, and the second power terminal, and is configured to respond to the control of the voltage at the sensing control node to set the voltage in the active level state. Writing a signal to the pull-up node; and, in response to the control of the sensing reset signal terminal, writing the second operating voltage provided by the second power terminal to the pull-up node;
  • the pull-down control circuit is connected to the first power terminal and the second power terminal, and is configured to write a voltage opposite to the voltage at the pull-up node to the pull-down node;
  • the display noise reduction circuit is connected to the first signal input terminal, the second signal input terminal, the first scanning power terminal, and the second scanning power terminal, and is configured to respond to the first signal input Control of the terminal, writing the second scan voltage to the pull-down node; and, in response to the control of the second signal input terminal, writing the first scan voltage to the pull-down node;
  • the output sub-circuit is connected to the pull-up node, the pull-down node, the corresponding signal output terminal, the corresponding output clock signal terminal, and the reset power terminal, and is configured to respond to the control of the voltage at the pull-up node,
  • the output clock signal provided by the corresponding output clock signal terminal is written into the corresponding signal output terminal; and, in response to the control of the voltage at the pull-down node, the reset operating voltage provided by the reset power terminal is written into the corresponding signal output end.
  • the display precharge reset circuit includes: a first display transistor and a second display transistor;
  • the control electrode of the first display transistor is connected to the first signal input terminal, the first electrode of the first display transistor is connected to the first scan power terminal, and the second electrode of the first display transistor is connected to the The pull-up node connection;
  • the control electrode of the second display transistor is connected to the second signal input terminal, the first electrode of the second display transistor is connected to the pull-up node, and the second electrode of the second display transistor is connected to the The second scanning power terminal is connected.
  • the shift register further includes: an anti-leakage circuit
  • the leakage prevention circuit includes: a first leakage prevention transistor, a second leakage prevention transistor, and a third leakage prevention transistor; the second electrode of the first display transistor is connected to the pull-up node through the second leakage prevention transistor , The second electrode of the second display transistor is connected to the second scanning power supply terminal through the third leakage prevention transistor;
  • the control electrode of the first anti-leakage transistor is connected to the pull-up node, the first electrode of the first anti-leakage transistor is connected to the first power terminal, and the second electrode of the first anti-leakage transistor is connected to Anti-leakage node connection;
  • the control electrode of the second anti-leakage transistor is connected to the first signal input terminal, and the first electrode of the second anti-leakage transistor is connected to the second electrode of the first display transistor and the anti-leakage node,
  • the second pole of the second leakage prevention transistor is connected to the pull-up node;
  • the control electrode of the third anti-leakage transistor is connected to the second signal input terminal, and the first electrode of the third anti-leakage transistor is connected to the second electrode of the second display transistor and the anti-leakage node, The second electrode of the third anti-leakage transistor is connected to the second scanning power terminal.
  • the pull-down control circuit includes: a third display transistor and a fourth display transistor;
  • the control electrode of the third display transistor is connected to the first power terminal, the first electrode of the third display transistor is connected to the first power terminal, and the second electrode of the third display transistor is connected to the Drop-down node connection;
  • the control electrode of the fourth display transistor is connected to the pull-up node, the first electrode of the fourth display transistor is connected to the pull-down node, and the second electrode of the fourth display transistor is connected to the second power supply. ⁇ End connection.
  • the display noise reduction circuit includes: a fifth display transistor and a sixth display transistor;
  • the control electrode of the fifth display transistor is connected to the first signal input terminal, the first electrode of the fifth display transistor is connected to the pull-down node, and the second electrode of the fifth display transistor is connected to the first signal input terminal. 2. Scan power terminal connection;
  • the control electrode of the sixth display transistor is connected to the second signal input terminal, the first electrode of the sixth display transistor is connected to the pull-down node, and the second electrode of the sixth display transistor is connected to the second signal input terminal.
  • the output sub-circuit includes: a seventh display transistor and an eighth display transistor;
  • the control electrode of the seventh display transistor is connected to the pull-up node, the first electrode of the seventh display transistor is connected to the output clock signal terminal, and the second electrode of the seventh display transistor is connected to the corresponding terminal.
  • the signal output terminal is connected;
  • the control electrode of the eighth display transistor is connected to the pull-down node, the first electrode of the eighth display transistor is connected to the corresponding signal output terminal, and the second electrode of the eighth display transistor is connected to the reset power terminal connect.
  • the shift register further includes: a pull-up noise reduction circuit
  • the pull-up noise reduction circuit includes: a ninth display transistor
  • the control electrode of the ninth display transistor is connected to the pull-down node, the first electrode of the ninth display transistor is connected to the pull-up node, and the second electrode of the ninth display transistor is connected to the second power supply ⁇ End connection.
  • the shift register further includes: an anti-leakage circuit
  • the anti-leakage circuit includes: a first anti-leakage transistor and a fourth anti-leakage transistor, and the second electrode of the ninth display transistor is connected to the second power supply terminal through the fourth anti-leakage transistor;
  • the control electrode of the first anti-leakage transistor is connected to the pull-up node, the first electrode of the first anti-leakage transistor is connected to the first power terminal, and the second electrode of the first anti-leakage transistor is connected to Anti-leakage node connection;
  • the control electrode of the fourth anti-leakage transistor is connected to the pull-down node, and the first electrode of the fourth anti-leakage transistor is connected to the second electrode of the ninth display transistor and the anti-leakage node.
  • the second pole of the four anti-leakage transistor is connected to the second power terminal.
  • the sensing control circuit includes: a first sensing transistor
  • the control electrode of the first sensing transistor is connected to the random signal terminal, the first electrode of the first sensing transistor is connected to the signal output terminal, and the second electrode of the first sensing transistor is connected to the signal output terminal.
  • the sensing control node connection is connected to the random signal terminal, the first electrode of the first sensing transistor is connected to the signal output terminal, and the second electrode of the first sensing transistor is connected to the signal output terminal.
  • the shift register further includes: an anti-leakage circuit
  • the anti-leakage circuit includes: a fifth anti-leakage transistor and a sixth anti-leakage transistor, and the first electrode of the first sensing transistor is connected to the signal output terminal through the sixth anti-leakage transistor;
  • the control electrode of the fifth anti-leakage transistor is connected to the sensing control node, the first electrode of the fifth anti-leakage transistor is connected to the first power terminal, and the second electrode of the fifth anti-leakage transistor Connected to the first electrode of the first sensing transistor and the second electrode of the sixth leakage prevention transistor;
  • the control electrode of the sixth anti-leakage transistor is connected to the random signal terminal, the first electrode of the sixth transistor is connected to the signal output terminal, and the second electrode of the sixth transistor is connected to the sensing control terminal. Node connection.
  • the sensing precharge reset circuit includes: a second sensing transistor, a third sensing transistor, and a fourth sensing transistor;
  • the control electrode of the second sensing transistor is connected to the sensing control node, the first electrode of the second sensing transistor is connected to the first clock signal terminal, and the second electrode of the second sensing transistor is connected to the first clock signal terminal.
  • Pole is connected to the first pole of the third sensing transistor;
  • the control electrode of the third sensing transistor is connected to the first clock signal terminal, and the second electrode of the third sensing transistor is connected to the pull-up node;
  • the control electrode of the fourth sensing transistor is connected to the sensing reset signal terminal, the first electrode of the fourth sensing transistor is connected to the pull-up node, and the second electrode of the fourth sensing transistor is connected to the pull-up node. Connected to the second power source.
  • the sensing precharge reset circuit includes: a second sensing transistor, a third sensing transistor, a fourth sensing transistor, and a fifth sensing transistor;
  • the control electrode of the second sensing transistor is connected to the sensing control node, the first electrode of the second sensing transistor is connected to the first clock signal terminal, and the second electrode of the second sensing transistor is connected to the first clock signal terminal.
  • the electrode is connected to the first electrode of the third sensing transistor and the control electrode of the fifth sensing transistor;
  • the control electrode of the third sensing transistor is connected to the pull-down node, and the second electrode of the third sensing transistor is connected to the second power terminal;
  • the control electrode of the fourth sensing transistor is connected to the sensing reset signal terminal, the first electrode of the fourth sensing transistor is connected to the pull-up node, and the second electrode of the fourth sensing transistor is connected to the pull-up node. Connected to the second power supply;
  • the first pole of the fifth sensing transistor is connected to the first power terminal, and the second pole of the fifth sensing transistor is connected to the pull-up node.
  • the shift register further includes: an anti-leakage circuit
  • the anti-leakage circuit includes: a first anti-leakage transistor and a seventh anti-leakage transistor, and the second electrode of the fourth sensing transistor is connected to the second power supply terminal through the seventh anti-leakage transistor;
  • the control electrode of the first anti-leakage transistor is connected to the pull-up node, the first electrode of the first anti-leakage transistor is connected to the first power terminal, and the second electrode of the first anti-leakage transistor is connected to Anti-leakage node connection;
  • the control electrode of the seventh anti-leakage transistor is connected to the sensing reset signal terminal, and the first electrode of the seventh transistor is connected to the anti-leakage node and the second electrode of the fourth sensing transistor.
  • the shift register further includes: a sensing noise reduction circuit
  • the sensing noise reduction circuit includes: a sixth sensing transistor and a seventh sensing transistor;
  • the control electrode of the sixth sensing transistor is connected to the first clock signal terminal, the first electrode of the sixth sensing transistor is connected to the pull-down node, and the second electrode of the sixth sensing transistor is connected to The first electrode of the seventh sensing transistor is connected;
  • the control electrode of the seventh sensing transistor is connected to the sensing control node, and the second electrode of the seventh sensing transistor is connected to the second power terminal.
  • the output circuit is configured with three signal output terminals, and the output circuit includes three output sub-circuits arranged in a one-to-one correspondence with the signal output terminals.
  • an embodiment of the present disclosure further provides a gate driving circuit, including: N shift registers cascaded, the shift register adopts the shift register provided in the first aspect;
  • the first signal input terminal of the shift register at the first m stage is connected to the frame start signal input terminal, the first signal input terminal of the shift register at the i-th stage and a signal output terminal at the im-th stage shift register Connection, where m is a preset positive integer, m+1 ⁇ i ⁇ N, and i is a positive integer;
  • the random signal terminal of the shift register of each stage is connected with the random signal input terminal;
  • the second signal input terminal of the shift register at stage Nm to stage N is connected to the frame reset signal input terminal, and the reset signal terminal at stage k is connected to a signal output terminal of the shift register at stage k+m , Where 1 ⁇ k ⁇ Nm, and k is a positive integer;
  • the sensing reset signal end of the shift register of each level is connected with the sensing reset signal line.
  • the shift registers at each level are configured with three corresponding signal output terminals, which are respectively a first cascade signal output terminal, a first drive signal output terminal, and a second drive signal output terminal;
  • the signal output terminal connected to the sensing control circuit of the shift register of each stage is the first cascade signal output terminal corresponding to the shift register of the current stage;
  • the first signal input terminal of the shift register at the i-th stage is connected to the first cascade signal output terminal of the shift register at the i-mth stage;
  • the second signal input terminal of the shift register at the kth stage is connected to the first cascade signal output terminal of the shift register at the k+m stage;
  • the first driving signal output terminal and the second driving signal output terminal of the shift registers of each stage are respectively connected to two gate lines of the corresponding row.
  • the value of m is 3.
  • embodiments of the present disclosure also provide a display device, including: the gate driving circuit provided in the above-mentioned second aspect.
  • an embodiment of the present disclosure also provides a gate driving method, the gate driving method adopts the shift register provided in the above-mentioned first aspect, and the gate driving method includes:
  • the potential of the pull-up node is controlled by the display precharge reset circuit; the potential of the pull-down node is controlled by the display noise reduction circuit;
  • the output sub-circuit writes the output clock signal provided by the output clock signal terminal to the corresponding signal output in response to the control of the voltage of the pull-up node in the active level state. Terminal; wherein, in the display output stage, the stage where the output clock signal is in the active level state is the sensing control stage. In the sensing control stage, the sensing control circuit responds to the random signal provided by the random signal terminal , Writing the output signal in the active level state output by the signal output terminal to the sensing control node;
  • the potential of the pull-up node is controlled by the display precharge reset circuit; and the potential of the pull-down node is controlled by the display noise reduction circuit; the output sub-circuit is based on the The voltage of the pull-down node controls the potential of the signal output terminal;
  • the sensing pre-charging circuit responds to the control of the voltage of the sensing control node and the first clock signal provided by the first clock signal terminal to convert the voltage signal in a valid level state Write to the pull-up node;
  • the output sub-circuit writes the output clock signal provided by the output clock signal terminal to the corresponding signal in response to the control of the voltage of the pull-up node in the active level state.
  • the sensing precharge reset circuit responds to the control of the sensing reset signal provided by the sensing reset signal terminal, and controls the second power supply terminal in the inactive level state provided by the second power supply terminal. 2. Writing a working voltage to the pull-up node; the output sub-circuit responds to the control of the voltage of the pull-down node in the active level state, resets the inactive level state provided by the reset power terminal The working voltage is written into the signal output terminal.
  • the display pre-charge reset circuit responds to the control of the first input signal provided by the first signal input terminal to set the first scan power terminal at the active level.
  • the first scan voltage of the state is written to the pull-up node;
  • the display noise reduction circuit responds to the control of the first input signal provided by the first signal input terminal, and the second scan power terminal provides The second scan voltage in an inactive level state is written to the pull-down node;
  • the display pre-charge reset circuit responds to the control of the second input signal provided by the second signal input terminal to change the second scan voltage provided by the second scan voltage terminal in an inactive level state.
  • the display noise reduction circuit sets the signal provided by the first scanning power terminal at an effective level
  • the first scan voltage of the state is written to the pull-down node; the output sub-circuit responds to the control of the voltage of the pull-down node in the active level state, and the reset power supply terminal provides the inactive level state.
  • the reset working voltage of is written to the signal output terminal.
  • the first input signal is in an active level state
  • the second input signal is in an inactive level state
  • the random signal is in an inactive level state
  • the first clock signal is in an inactive level state
  • the sensing reset signal is in an inactive level state
  • the output clock signal is in an inactive level state
  • the first input signal is in an inactive level state
  • the second input signal is in an inactive level state
  • the random signal is in an active level state in the display effective level output stage
  • the output clock signal is in the non-valid level state
  • the first clock signal is in the non-valid level state
  • the sensing reset signal is in the non-valid level state
  • the output clock signal is displayed in the non-valid level state.
  • the effective level output stage is the effective level state and the non-effective level state is displayed during the non-effective level output stage;
  • the first input signal is in an inactive level state
  • the second input signal is in an active level state
  • the random signal is in an inactive level state
  • the first clock signal is In an inactive level state
  • the sensing reset signal is in an inactive level state
  • the output clock signal is switched between an inactive level state and an effective level state
  • the first input signal is in an inactive level state
  • the second input signal is in an inactive level state
  • the random signal is in an inactive level state
  • the first The clock signal is in an active level state
  • the sensing reset signal is in an inactive level state
  • the output clock signal is in an inactive level state
  • the first input signal is in an inactive level state
  • the second input signal is in an inactive level state
  • the random signal is in an inactive level state
  • the first clock The signal is in an inactive level state
  • the sensing reset signal is in an inactive level state
  • the output clock signal is in an active level state in the sensing effective level output stage and is in the sensing inactive level output stage Inactive level state;
  • the first input signal is in an inactive level state
  • the second input signal is in an inactive level state
  • the random signal is in an active level state
  • the first clock signal In an inactive level state
  • the sensing reset signal is in an active level state
  • the output clock signal is in an inactive level state
  • the display pre-charge reset circuit responds to the control of the second input signal provided by the second signal input terminal to set the second scan power terminal at the active level.
  • the second scan voltage of the state is written to the pull-up node;
  • the display noise reduction circuit responds to the control of the second input signal provided by the second signal input terminal, and sends the signal provided by the first scan power terminal The first scan voltage in an inactive level state is written to the pull-down node;
  • the display pre-charge reset circuit responds to the control of the first input signal provided by the first signal input terminal to reduce the first scan voltage provided by the first scan power terminal in an inactive level state.
  • the display noise reduction circuit sets the signal provided by the second scanning power terminal at an effective level
  • the second scan voltage in the state is written to the pull-down node; the output sub-circuit responds to the control of the voltage of the pull-down node in the active level state, and the reset power supply terminal provides the inactive level state.
  • the reset working voltage of is written to the signal output terminal.
  • the first input signal is in an inactive level state
  • the second input signal is in an active level state
  • the random signal is in an inactive level state
  • the first clock signal is in an inactive level state
  • the sensing reset signal is in an inactive level state
  • the output clock signal is in an inactive level state
  • the first input signal is in an inactive level state
  • the second input signal is in an inactive level state
  • the random signal is in an active level state in the display effective level output stage
  • the output clock signal is in the non-valid level state
  • the first clock signal is in the non-valid level state
  • the sensing reset signal is in the non-valid level state
  • the output clock signal is displayed in the non-valid level state.
  • the effective level output stage is the effective level state and the non-effective level state is displayed during the non-effective level output stage;
  • the first input signal is in an active level state
  • the second input signal is in an inactive level state
  • the random signal is in an inactive level state
  • the first clock signal is In an inactive level state
  • the sensing reset signal is in an inactive level state
  • the output clock signal is switched between an inactive level state and an effective level state
  • the first input signal is in an inactive level state
  • the second input signal is in an inactive level state
  • the random signal is in an inactive level state
  • the first The clock signal is in an active level state
  • the sensing reset signal is in an inactive level state
  • the output clock signal is in an inactive level state
  • the first input signal is in an inactive level state
  • the second input signal is in an inactive level state
  • the random signal is in an inactive level state
  • the first clock The signal is in an inactive level state
  • the sensing reset signal is in an inactive level state
  • the output clock signal is in an active level state in the sensing effective level output stage and is in the sensing inactive level output stage Inactive level state;
  • the first input signal is in an inactive level state
  • the second input signal is in an inactive level state
  • the random signal is in an active level state
  • the first clock signal In an inactive level state
  • the sensing reset signal is in an active level state
  • the output clock signal is in an inactive level state
  • FIG. 1 is a schematic diagram of the circuit structure of a pixel circuit in an organic light emitting diode display panel
  • FIG. 2 is a working timing diagram of the pixel circuit shown in FIG. 1;
  • FIG. 3 is a schematic structural diagram of a gate driving unit in the related art
  • FIG. 4 is a schematic diagram of a circuit structure of a shift register provided by an embodiment of the disclosure.
  • FIG. 5 is a schematic diagram of a circuit structure of a shift register provided by an embodiment of the disclosure.
  • FIG. 6a is a working timing diagram of the shift register shown in FIG. 5 corresponding to the gate driving circuit for forward scanning;
  • Fig. 6b is a working timing diagram of the shift register shown in Fig. 5 corresponding to the gate drive circuit performing reverse scanning
  • FIG. 7 is a schematic diagram of another circuit structure of a shift register provided by an embodiment of the disclosure.
  • FIG. 8 is a working timing diagram of the shift register shown in FIG. 7;
  • FIG. 9 is a schematic diagram of another circuit structure of a shift register provided by an embodiment of the disclosure.
  • FIG. 10 is a schematic diagram of still another circuit structure of the shift register provided by the embodiments of the disclosure.
  • FIG. 11 is a schematic diagram of still another circuit structure of the shift register provided by the embodiments of the present disclosure.
  • FIG. 12 is a schematic diagram of still another circuit structure of the shift register provided by the embodiments of the disclosure.
  • FIG. 13 is a schematic diagram of a circuit structure of a gate driving circuit provided by an embodiment of the disclosure.
  • FIG. 14 is a working timing diagram of the gate driving circuit shown in FIG. 13;
  • FIG. 15 is a flowchart of a gate driving method provided by an embodiment of the disclosure.
  • FIG. 16 is another flowchart of a gate driving method provided by an embodiment of the disclosure.
  • a transistor generally includes three electrodes: a gate, a source, and a drain.
  • the source and drain in the transistor are structurally symmetrical, and the two can be interchanged as needed.
  • the control electrode refers to the gate of the transistor, and one of the first electrode and the second electrode is the source and the other is the drain.
  • transistors can be divided into N-type transistors and P-type transistors; when the transistor is an N-type transistor, its turn-on voltage is a high-level voltage, and its cut-off voltage is a low-level voltage; when the transistor is a P-type transistor In the case of a transistor, its turn-on voltage is a low-level voltage, and its turn-off voltage is a high-level voltage.
  • the “effective level” in this disclosure refers to the voltage that can control the turn-on of the corresponding transistor, and the “ineffective level” refers to the voltage that can control the turn-off of the corresponding transistor; therefore, when the transistor is an N-type transistor, the effective level is Refers to the high level, and the non-effective level refers to the low level; when the transistor is a P-type transistor, the effective level refers to the low level and the non-effective level refers to the high level.
  • each transistor is an N-type transistor as an example for illustration.
  • the active level refers to the high level
  • the inactive level refers to the low level.
  • the transistors in the following embodiments can also be replaced with P-type transistors.
  • a frame of picture can be divided into two stages: the display driving stage and the sensing stage; in the display driving stage, each row of pixel circuits in the display panel completes the display driving; In the measurement phase, a row of pixel circuits in the display panel completes current extraction (ie, sensing).
  • Figure 1 is a schematic diagram of the circuit structure of a pixel circuit in an organic light-emitting diode display panel
  • Figure 2 is a working timing diagram of the pixel circuit shown in Figure 1, as shown in Figures 1 and 2
  • the pixel circuit includes a display switching transistor QTFT (control The pole is connected to the gate line G1), the driving transistor DTFT, the sensing switch transistor STFT (the control pole is connected to the gate line G2), and the capacitor Cst.
  • the pixel circuit includes at least the following two stages in the working process: a display driving stage (including a data voltage writing process) and a sensing stage (including a current reading process).
  • the data voltage Vdata in the data line Data needs to be written to the pixel circuit; in the sensing phase, a test voltage Vsense needs to be written to the pixel circuit through the data line Data, and the sensing switch transistor STFT is used to write a test voltage Vsense to the pixel circuit.
  • the electric signal at the drain of the driving transistor is read to the signal read line Sense. In both the data voltage writing process and the current reading process, it is necessary to write an effective level voltage to the gate of the sensing switch transistor STFT through the corresponding gate line G2.
  • the gate driving unit Since the duration of the data voltage writing process is longer than the duration of the current reading process, for the gate line G2 connected to the gate of the sensing switch transistor STFT, it needs to output a double pulse signal within one frame, and corresponds to The pulse width of the current reading process is larger than the pulse corresponding to the data voltage writing process. Therefore, this requires the gate driving unit to have the function of outputting double pulses with different pulse widths.
  • FIG 3 is a schematic structural diagram of a gate drive unit in the related art.
  • a first shift register and a second shift register are used in the related art.
  • the bit register and a signal combining circuit form a gate drive unit.
  • the first shift registers in each gate drive unit are cascaded, and the second shift registers in each gate drive unit are cascaded.
  • the first shift register is used for display
  • the driving phase outputs a driving signal for driving the sensing switch transistor
  • the second shift register is used for outputting a driving signal for driving the sensing switch transistor in the sensing phase.
  • the signal combining circuit will be located in the same gate driving unit as the second shift register.
  • the driving signals output by the two shift registers are combined, and a double pulse signal is output through the signal output terminal OUTPUT to meet the driving demand.
  • the gate driving unit composed of two shift registers and a signal combining circuit can meet the driving requirements, its structure is complicated and the number of transistors required to be provided is large, which is not conducive to the design of a narrow frame.
  • the technical solution of the present disclosure provides a shift register, which has the function of outputting double pulses, and can meet the driving requirements of the pixel circuit in the display driving phase and the sensing phase. Therefore, in the present disclosure
  • One of the shift registers can be used alone as a gate drive unit.
  • the gate drive unit includes two shift registers and a signal combining circuit
  • the technical solution of the present disclosure can greatly reduce the number of gates. The number of transistors in the pole drive unit facilitates the realization of a narrow frame.
  • the shift register includes: a display precharge reset circuit 3, a sensing control circuit 1, a sensing precharge reset circuit 2.
  • the pull-down control circuit 4, the display noise reduction circuit 5 and the output circuit, the sensing control circuit 1, the sensing precharge reset circuit 2 is connected to the sensing control node H, the display precharge reset circuit 3, the sensing precharge reset circuit 2.
  • the pull-down control circuit 4, the output circuit is connected to the pull-up node PU, and the pull-down control circuit 4, the display noise reduction circuit 5 and the output circuit are connected to the pull-down node PD.
  • the display precharge reset circuit 3 is connected to the first signal input terminal STU1, the second signal input terminal STU2, the first scanning power terminal D, and the second scanning power terminal R, and is configured to respond to the control of the first signal input terminal STU1
  • the first scan voltage provided by the first scan power terminal D is written into the pull-up node PU; and, in response to the control of the second signal input terminal STU2, the second scan voltage provided by the second scan power terminal R is written into the pull-up node PU.
  • the sensing control circuit 1 is connected to the signal output terminal OUT and the random signal terminal OE, and is configured to write the output signal provided by the signal output terminal OUT into the sensing control node H in response to the control of the random signal terminal OE.
  • the sensing precharge reset circuit 2 is connected to the first clock signal terminal CLKA, the sensing reset signal terminal STD, and the second power terminal, and is configured to respond to the control of the voltage at the sensing control node H, and the voltage at the active level state
  • the signal is written to the pull-up node PU; and, in response to the control of the sensing reset signal terminal STD, the second operating voltage is written to the pull-up node PU.
  • the pull-down control circuit 4 is connected to the first power supply terminal and the second power supply terminal, and is configured to write a voltage opposite to the voltage at the pull-up node PU to the pull-down node PD.
  • the display noise reduction circuit 5 is connected to the first signal input terminal STU1, the second signal input terminal STU2, the first scanning power terminal D, and the second scanning power terminal R, and is configured to respond to the control of the first signal input terminal STU1
  • the second scan voltage is written into the pull-down node PD; and, in response to the control of the second signal input terminal STU2, the first scan voltage is written into the pull-down node PD.
  • the output circuit is configured with at least one signal output terminal OUT, including at least one output sub-circuit 6 arranged in a one-to-one correspondence with the signal output terminal OUT; the output sub-circuit 6 is connected to the pull-up node PU, the pull-down node PD, and the corresponding signal output terminal OUT,
  • the corresponding output clock signal terminal CLKD and the reset power terminal are connected, and are configured to write the output clock signal provided by the corresponding output clock signal terminal CLKD to the corresponding signal output terminal OUT in response to the control of the voltage at the pull-up node PU; and In response to the control of the voltage at the pull-down node PD, the reset operating voltage provided by the reset power terminal is written into the corresponding signal output terminal OUT.
  • the number of signal output terminals is 1 to 4. It should be noted that FIG. 4 only exemplarily shows one signal output terminal, and this situation does not limit the technical solution of the present disclosure.
  • the precharge reset circuit 3 and the sense precharge reset circuit 2 can share one pull-down control circuit 4 and share one output circuit.
  • the shift register provided by the embodiments of the present disclosure can independently constitute a gate driving unit. Therefore, the gate driving unit in the present disclosure includes: a display precharge reset circuit, a sensing control circuit, a sensing precharge reset circuit, One pull-down control circuit and one output circuit. It can be seen that, compared with the gate driving unit in the related art, the technical solution of the present disclosure can save at least one pull-down control circuit and one output circuit by sharing the pull-down control circuit and the output circuit; at the same time, the present disclosure There is no need to set a signal combining circuit in the gate drive unit in.
  • the gate driving unit composed of the shift register provided in the present disclosure can save a pull-down control circuit, an output circuit, and a signal combining circuit. Therefore, the present disclosure
  • the technical solution can reduce the number of transistors in the gate driving unit, which is beneficial to the realization of a narrow frame.
  • the pull-down control circuit 4 may write a voltage opposite to the voltage at the pull-up node PU to the pull-down node PD in response to the control of the pull-up node PU.
  • the voltage at the pull-down node PD is easily disturbed by noise and drifts, thereby causing a false output.
  • the display noise reduction circuit 5 in the shift register, it is possible to continuously write a voltage opposite to the voltage at the pull-up node PU during the display precharge phase and during the display reset phase to the pull-down node PD (at the In the display pre-charge stage, the voltage at the pull-up node PU is at an effective level, and the voltage output from the noise reduction circuit 5 to the pull-down node PD is at an inactive level; in the display reset stage, the voltage at the pull-up node PU is at an inactive level It is displayed that the voltage output by the noise reduction circuit 5 to the pull-down node PD is at an effective level), so that noise reduction processing can be performed on the pull-down node PD to ensure a stable output of the signal output terminal OUT.
  • the shift register provided by the embodiment of the present disclosure can support the forward scan (scan output from the first stage shift register to the Nth stage shift register) and reverse scan (from the Nth stage shift register) of the gate drive circuit. From the first-stage shift register to the first-stage shift register, the scan output is performed sequentially), which can support the gate drive circuit to perform bidirectional scanning. For details, please refer to the subsequent description.
  • FIG. 5 is a schematic diagram of a circuit structure of a shift register provided by an embodiment of the disclosure. As shown in FIG. 5, the shift register shown in FIG. 5 is a specific solution based on the shift register shown in FIG. 4.
  • the display precharge reset circuit 3 includes: a first display transistor M1 and a second display transistor M2.
  • the control electrode of the first display transistor M1 is connected to the first signal input terminal STU1, the first electrode of the first display transistor M1 is connected to the first scan power terminal D, and the second electrode of the first display transistor M1 is connected to the pull-up node PU .
  • the control electrode of the second display transistor M2 is connected to the second signal input terminal STU2, the first electrode of the second display transistor M2 is connected to the pull-up node PU, and the second electrode of the second display transistor M2 is connected to the second scan power terminal R .
  • the pull-down control circuit 4 includes: a third display transistor M3 and a fourth display transistor M4.
  • the control electrode of the third display transistor M3 is connected to the first power terminal, the first electrode of the third display transistor M3 is connected to the first power terminal, and the second electrode of the third display transistor M3 is connected to the pull-down node PD.
  • the control electrode of the fourth display transistor M4 is connected to the pull-up node PU, the first electrode of the fourth display transistor M4 is connected to the pull-down node PD, and the second electrode of the fourth display transistor M4 is connected to the second power terminal.
  • the display noise reduction circuit 5 includes: a fifth display transistor M5 and a sixth display transistor M6.
  • the control electrode of the fifth display transistor M5 is connected to the first signal input terminal STU1, the first electrode of the fifth display transistor M5 is connected to the pull-down node PD, and the second electrode of the fifth display transistor M5 is connected to the second scanning power terminal R.
  • the control electrode of the sixth display transistor M6 is connected to the second signal input terminal STU2, the first electrode of the sixth display transistor M6 is connected to the pull-down node PD, and the second electrode of the sixth display transistor M6 is connected to the first scan power terminal D.
  • the output sub-circuit 6 includes: a seventh display transistor M7 and an eighth display transistor M8.
  • the control electrode of the seventh display transistor M7 is connected to the pull-up node PU, the first electrode of the seventh display transistor M7 is connected to the output clock signal terminal CLKD, and the second electrode of the seventh display transistor M7 is connected to the corresponding signal output terminal OUT.
  • the control electrode of the eighth display transistor M8 is connected to the pull-down node PD, the first electrode of the eighth display transistor M8 is connected to the corresponding signal output terminal OUT, and the second electrode of the eighth display transistor M8 is connected to the reset power terminal.
  • the shift register of the embodiment of the present disclosure further includes: a first capacitor C1, a first end of the first capacitor C1 is connected to the pull-up node PU, and a second end of the first capacitor C1 is connected to the signal output terminal OUT connect.
  • the first capacitor C1 can be used to ensure that the voltage of the pull-up node PU is always at a valid level during the display output stage and the sensing output stage.
  • the sensing control circuit 1 includes: a first sensing transistor T1; the control electrode of the first sensing transistor T1 is connected to the random signal terminal OE, and the first electrode of the first sensing transistor T1 is connected to the signal output terminal. OUT is connected, and the second electrode of the first sensing transistor T1 is connected to the sensing control node H.
  • the sensing precharge reset circuit 2 includes: a second sensing transistor T2, a third sensing transistor T3, and a fourth sensing transistor T4.
  • the control electrode of the second sensing transistor T2 is connected to the sensing control node H
  • the first electrode of the second sensing transistor T2 is connected to the first clock signal terminal CLKA
  • the second electrode of the second sensing transistor T2 is connected to the first clock signal terminal CLKA.
  • the first pole of the three sensing transistor T3 is connected.
  • the control electrode of the third sensing transistor T3 is connected to the first clock signal terminal CLKA
  • the second electrode of the third sensing transistor T3 is connected to the pull-up node PU.
  • the control electrode of the fourth sensing transistor T4 is connected to the sensing reset signal terminal STD, the first electrode of the fourth sensing transistor T4 is connected to the pull-up node PU, and the second electrode of the fourth sensing transistor T4 is connected to the second power supply .
  • the shift register in order to maintain the stability of the voltage at the sensing control node H, the shift register further includes: a second capacitor C2, the first end of the second capacitor C2 is connected to the sensing control node H, and the second capacitor C2 The second end is connected to the second power supply end.
  • the first scan voltage provided by the first scan power terminal D is a high-level voltage VGH
  • the second scan voltage provided by the second scan power terminal R is a low-level voltage VGL1
  • the first working voltage provided by the first power terminal is high
  • Fig. 6a is a working timing diagram of the shift register shown in Fig. 5 corresponding to the forward scanning of the gate drive circuit, as shown in Fig. 6a, and Fig. 6a shows the shift when the gate drive circuit performs forward scanning.
  • the working process of the shift register includes the following six stages, including a display precharge stage t1, a display output stage t2, a display reset stage t3, a sensing precharge stage t4, a sensing output stage t5, and a sensing reset stage t6.
  • the first input signal provided by the first signal input terminal STU1 is in a high level state
  • the second input signal provided by the second signal input terminal STU2 is in a low level state
  • the random signal terminal OE provides random
  • the signal is in a low-level state
  • the first clock signal provided by the first clock signal terminal CLKA is in a low-level state
  • the sensing reset signal provided by the sensing reset signal terminal STD is in a low-level state
  • the output clock signal terminal CLKD provides The output clock signal is in a low level state.
  • the first display transistor M1 Since the first input signal is in a high-level state and the second input signal is in a low-level state, the first display transistor M1 is turned on and the second display transistor M2 is turned off, and the first scan voltage VGH can be written through the first display transistor M1 Into the pull-up node PU, the voltage of the pull-up node PU is in a high-level state.
  • the fourth display transistor M4 and the seventh display transistor M7 are turned on, and the second operating voltage VGL1 is written to the pull-down node PD through the fourth display transistor M4.
  • the display transistor M3 is equivalent to a resistor, the voltage of the pull-down node PD is in a low level state, and the eighth display transistor M8 is turned off.
  • the fifth display transistor M5 is turned on, and the second scan voltage VGL1 is written to the pull-down node PD through the fifth display transistor M5 to reduce noise of the pull-down node PD handle.
  • the output clock signal can be written to the corresponding signal output terminal OUT through the seventh display transistor M7, and since the output clock signal is in a low level state, the signal output terminal OUT outputs a low level Signal.
  • the first sensing transistor T1 Since the random signal is in a low state, the first sensing transistor T1 is turned off, the sensing control node H is in a floating (Floaing) state, and the voltage of the sensing control node H maintains the low state of the previous stage.
  • the second sensing transistor T2, the third sensing transistor T3, and the fourth sensing transistor T4 are all in an off state. It should be noted that since the first sensing transistor T1 is turned off, no matter whether the output signal is in a high-level state or a low-level state, the voltage of the sensing control node H will not be affected.
  • the display output stage t2 includes: a display effective level output stage t21 (also referred to as a sensing control stage) and a display ineffective level output stage t22.
  • the first input signal provided by the first signal input terminal STU1 is in a low state
  • the second input signal provided by the second signal input terminal STU2 is in a low state
  • the random signal provided by the random signal terminal OE In the display effective level output stage t21 is in the high level state and in the display ineffective level output stage t22 is in the low level state
  • the first clock signal provided by the first clock signal terminal CLKA is in the low level state
  • the sensing reset signal provided by the signal terminal STD is in a low level state
  • the output clock signal provided by the output clock signal terminal CLKD is in a high level state during the display effective level output stage t21 and is in a low level state during the display non-effective level output stage t22 Level status.
  • both the first display transistor M1 and the second display transistor M2 are turned off, and the pull-up node PU is in a floating state.
  • the fourth transistor is continuously turned on, the pull-down node PD maintains a low level state, and the eighth display transistor M8 maintains an off state.
  • the signal output terminal OUT outputs a high-level signal.
  • the voltage of the pull-up node PU is pulled up to a higher state.
  • the voltage corresponding to each clock signal is VGH when the clock signal is at a high level
  • the corresponding voltage is VGL (approximately 0V) when the clock signal is at a low level.
  • the pre-charge stage t1 is displayed, the node PU is pulled up.
  • the voltage is approximately VGH, and at the initial moment of the display effective level output stage t21, the voltage of the pull-up node PU can be pulled up to approximately 2*VGH.
  • the output clock signal is switched from high level to low level, and the signal output terminal OUT outputs a low level signal; at the same time, Under the bootstrap action of the first capacitor C1, the voltage of the pull-up node PU drops to the level at the initial moment of the display driving phase, that is, drops to VGH, at this time the pull-up node PU is still in a high level state, and the seventh display The transistor M7 remains on.
  • the first sensing transistor T1 when entering the display effective level output stage t21 (corresponding to the sensing control stage), since the random signal is in a high level state, the first sensing transistor T1 is turned on. At this time, since the signal output terminal OUT outputs a high-level signal, the high-level signal can be written to the sensing control node H through the first sensing transistor T1, and the voltage at the sensing control node H is in a high-level state . At this time, the second sensing transistor T2 is turned on, and the first clock signal can be written to the first pole of the third sensing transistor T3 through the second sensing transistor T2. However, since the first clock signal is in a low level state, the third sensing transistor T3 is turned off.
  • the first sensing transistor T1 is turned off, and the sensing control node H is in a floating state. Under the action of the second capacitor C2, the voltage at the sensing control node H can maintain a high level state.
  • the first input signal provided by the first signal input terminal STU1 is in a low level state
  • the second input signal provided by the second signal input terminal STU2 is in a high level state
  • the random signal provided by the random signal terminal OE In the low state, the first clock signal provided by the first clock signal terminal CLKA is in the low state, the sensing reset signal provided by the sensing reset signal terminal STD is in the low state, and the output provided by the clock signal terminal CLKD is output
  • the clock signal switches between a low-level state and a high-level state.
  • the second display transistor M2 Since the second input signal is in a high-level state, the second display transistor M2 is turned on, and the second scan voltage VGL1 is written to the pull-up node PU through the second display transistor M2, and the pull-up node PU is in a low-level state. Both the fourth display transistor M4 and the seventh display transistor M7 are turned off. At this time, the first operating voltage VGH is written to the pull-down node PD through the third display transistor M3, the pull-down node PD is in a high level state, and the eighth display transistor M8 is turned on.
  • the sixth display transistor M6 is turned on, and the first scan voltage VGH is written to the pull-down node PD through the sixth display transistor M6 to reduce the noise of the pull-down node PD handle.
  • the eighth display transistor M8 Since the eighth display transistor M8 is turned on, the reset operating voltage VGL2 is written to the signal output terminal OUT through the eighth transistor, and the signal output terminal OUT outputs a low-level signal, which completes the display reset.
  • the first sensing transistor T1 and the third sensing transistor T3 always maintain the off state. Since the sensing control node H is always in the high level state, the second sensing transistor T2 always maintains the on state. Since the sensing reset signal is in a low level state, the fourth sensing transistor T4 always maintains an off state.
  • each transistor in the pixel circuit maintains the state during the display reset stage t3.
  • the sensing precharge stage t4 the first input signal provided by the first signal input terminal STU1 is in a low level state, the second input signal provided by the second signal input terminal STU2 is in a low level state, and the random signal terminal OE provides The random signal is in a low-level state, the first clock signal provided by the first clock signal terminal CLKA is in a high-level state, the sensing reset signal provided by the sensing reset signal terminal STD is in a low-level state, and the output clock signal terminal CLKD provides The output clock signal is in low level state.
  • the first sensing transistor T1 Since the random signal is in a low level state, the first sensing transistor T1 is turned off, the sensing control node H is in a floating state, maintaining the high level state of the previous stage, and the second sensing transistor T2 is in conduction State, the first clock signal in the high-level state is written to the first pole of the third sensing transistor T3 through the second sensing transistor T2. Also, because the first clock signal is in the high-level state, the third sensing transistor T3 is turned on, and the first clock signal in the high-level state can be written to the pull-up node PU through the third sensing transistor T3, and the pull-up node PU is in a high state.
  • the fourth display transistor M4 and the seventh display transistor M7 are turned on, and the second operating voltage VGL1 is written to the pull-down node PD through the fourth display transistor M4.
  • the display transistor M3 is equivalent to a resistor, the voltage of the pull-down node PD is in a low level state, and the eighth display transistor M8 is turned off.
  • the output clock signal can be written to the corresponding signal output terminal OUT through the seventh display transistor M7, and since the output clock signal is in a low level state, the signal output terminal OUT outputs a low level Signal.
  • the sensing output stage t5 includes: a sensing effective level output stage and a sensing non-effective level output stage.
  • the first input signal provided by the first signal input terminal STU1 is in a low level state
  • the second input signal provided by the second signal input terminal STU2 is in a low level state
  • the random signal terminal OE provides random
  • the signal is in a low-level state
  • the first clock signal provided by the first clock signal terminal CLKA is in a low-level state
  • the sensing reset signal provided by the sensing reset signal terminal STD is in a low-level state
  • the output clock signal terminal CLKD provides The output clock signal is in a high level state during the sensing effective level output stage and is in a low level state during the sensing non-effective level output stage.
  • the first sensing transistor T1 Since the random signal is in a low level state, the first sensing transistor T1 is turned off, the sensing control node H is in a floating state, maintaining the high level state of the previous stage, and the second sensing transistor T2 is in conduction State, the first clock signal in the low state is written to the first pole of the third sensing transistor T3 through the second sensing transistor T2. Since the first clock signal is in a low level state, the third sensing transistor T3 is turned off. At the same time, since the sensing reset signal is in a low level state, the fourth sensing transistor T4 is turned off.
  • both the first display transistor M1 and the second display transistor M2 are turned off, and the pull-up node PU is in a floating state.
  • the fourth transistor is continuously turned on, the pull-down node PD maintains a low level state, and the eighth display transistor M8 maintains an off state.
  • the signal output terminal OUT outputs a high level signal.
  • the voltage of the pull-up node PU is pulled up to a higher state.
  • the voltage corresponding to each clock signal is VGH when the clock signal is at a high level
  • the corresponding voltage is VGL (approximately 0V) when the clock signal is at a low level.
  • the pre-charge stage t1 is displayed, the node PU is pulled up.
  • the voltage is approximately VGH, and at the initial moment of the sensing effective level output phase, the voltage of the pull-up node PU can be pulled up to approximately 2*VGH.
  • the output clock signal is switched from high level to low level, and the signal output terminal OUT outputs a low level signal; at the same time, Under the bootstrap action of the first capacitor C1, the voltage of the pull-up node PU drops to the level at the initial moment of the display driving phase, that is, drops to VGH, at this time the pull-up node PU is still in a high level state, and the seventh display The transistor M7 remains on.
  • the sensing reset stage t6 the first input signal provided by the first signal input terminal STU1 is in a low level state, the second input signal provided by the second signal input terminal STU2 is in a low level state, and the random signal terminal OE provides random The signal is in a high-level state, the first clock signal provided by the first clock signal terminal CLKA is in a low-level state, the sensing reset signal provided by the sensing reset signal terminal STD is in a high-level state, and the output clock signal terminal CLKD provides The output clock signal is in a low level state.
  • the fourth sensing transistor T4 Since the sensing reset signal is in a high-level state, the fourth sensing transistor T4 is turned on, the second working voltage VGL1 is written to the pull-up node PU through the fourth sensing transistor T4, and the pull-up node PU is in a low-level state. Both the fourth display transistor M4 and the seventh display transistor M7 are turned off. At this time, the first operating voltage VGH is written to the pull-down node PD through the third display transistor M3, the pull-down node PD is in a high level state, and the eighth display transistor M8 is turned on. At the same time, since the eighth display transistor M8 is turned on, the reset operating voltage VGL2 is written to the signal output terminal OUT through the eighth transistor, and the signal output terminal OUT outputs a low-level signal, which completes the sensing reset.
  • the sensing reset stage t6 since the random signal is in a high-level state, the first sensing transistor T1 is turned on, and the low-level signal output by the signal output terminal OUT is written to the sensing control node through the first sensing transistor T1 H, the sensing control node H is in a low level state, and the second sensing transistor T2 is turned off.
  • Fig. 6b is a working sequence diagram of the shift register shown in Fig. 5 corresponding to the reverse scanning of the gate drive circuit, as shown in Fig. 6b, and Fig. 6b shows the shift when the gate drive circuit performs reverse scanning.
  • the working sequence of the register The first scan voltage provided by the first scan power terminal D is a low-level voltage VGL1, the second scan voltage provided by the second scan power terminal R is a high-level voltage VGH, and the first working voltage provided by the first power terminal is high The level voltage VGH, the second working voltage provided by the second power terminal is a low-level working voltage VGL1, and the reset working voltage provided by the reset power terminal is a low-level working voltage VGL2.
  • the difference between the timing sequence in Figure 6a is that in the timing diagram shown in Figure 6b, during the display pre-charge stage t1, the first input signal provided by the first signal input terminal STU1 is in a low level state, and the second signal input terminal STU2 provides The second input signal is in a high-level state, the first display transistor M1 is turned off, the second display transistor M2 is turned on, and the second scan voltage VGH is written to the pull-up node PU through the second display transistor M2, so that the pull-up node PU Perform pre-charge processing.
  • the first input signal provided by the first signal input terminal STU1 is in a high level state
  • the second input signal provided by the second signal input terminal STU2 is in a low level state
  • the first display transistor M1 is turned on.
  • the second display transistor M2 is turned off, and the first scan voltage VGL1 is written to the pull-up node PU through the first display transistor M1 to reset the pull-up node PU.
  • the shift register provided by the embodiments of the present disclosure can support bidirectional scanning of the gate driving circuit.
  • the shift register of the embodiment of the present disclosure further includes: a pull-up noise reduction circuit;
  • the pull-up noise reduction circuit includes: a ninth display transistor M9, the control electrode of the ninth display transistor M9 is connected to the pull-down node PD, The first pole of the ninth display transistor M9 is connected to the pull-up node PU, and the second pole of the ninth display transistor M9 is connected to the second power terminal.
  • the pull-up noise reduction circuit is configured to write the second working voltage in the inactive level state to the pull-up node PU when the voltage of the pull-down node PD is in the active level state, so as to perform noise reduction processing on the pull-up node PU;
  • the pull-up noise reduction circuit is not a necessary structure in this embodiment.
  • the shift register of the embodiment of the present disclosure further includes: a sensing noise reduction circuit; the sensing noise reduction circuit includes: a sixth sensing transistor T6 and a seventh sensing transistor T7.
  • the control electrode of the sixth sensing transistor T6 is connected to the first clock signal terminal CLKA, the first electrode of the sixth sensing transistor T6 is connected to the pull-down node PD, and the second electrode of the sixth sensing transistor T6 is connected to the seventh sensing transistor
  • the first electrode of T7 is connected; the control electrode of the seventh sensing transistor T7 is connected to the sensing control node H, and the second electrode of the seventh sensing transistor T7 is connected to the second power terminal.
  • the sensing pre-charge stage t4 the first clock signal and the sensing control node H are both in a high level state, at this time the second operating voltage VGL1 can be written by the seventh sensing transistor T7 and the sixth sensing transistor T6 Go to the pull-down node PD to perform noise reduction processing on the pull-down node PD.
  • the sensing noise reduction circuit is not a necessary structure in this embodiment.
  • FIG. 7 is a schematic diagram of another circuit structure of a shift register provided by an embodiment of the present disclosure
  • FIG. 8 is a working timing diagram of the shift register shown in FIG. 7, as shown in FIG. 7 and FIG. 8, and shown in FIG.
  • the difference shown in the shift register is that the number of signal output terminals in this embodiment is 3, that is, including signal output terminals OUT, OUT', and OUT". Accordingly, the number of output sub-circuits is 3, that is, including output Sub-circuit 6, 6'and 6".
  • the seventh display transistors M7, M7' and M7" in each output sub-circuit 6, 6'and 6" turn on or off at the same time
  • the eighth display transistors M8, M8 in each output sub-circuit 6, 6'and 6" 'And M8' are turned on or off at the same time.
  • the second pole of the eighth display transistor M8 may also be connected to the second power terminal instead of the reset power terminal.
  • the working process of the shift register shown in FIG. 7 is the same as the working process of the shift register shown in FIG. 5, and the specific content can be referred to the foregoing content, which will not be repeated here.
  • the output sub-circuit 6 and the output sub-circuit 6' are both connected to the output clock signal terminal CLKD, and the output sub-circuit 6" is connected to the output clock signal terminal CLKE; one of the three signal output terminals OUT, It is used to provide input signals to its own sensing control circuit 1, and to provide cascaded signals to other shift registers in the gate drive circuit; the other two signal output terminals OUT' and OUT" are respectively used to provide the corresponding row of pixel circuits
  • the gate line G1 connected to the control electrode of the switching transistor QTFT and the gate line G2 connected to the control electrode of the sensing switching transistor STFT provide a driving signal (the output clock signal terminal CLKD and signal output corresponding to the signal output terminal OUT'
  • the timing of the output clock signal terminal CLKE corresponding to the terminal OUT" can be referred to as shown in FIG. 8).
  • the technical solution of the present disclosure does not limit the number of signal output terminals and output sub-circuits, nor does it limit the output clock signal loaded in the output clock signal terminal connected to each output sub-circuit, that is, these output clock signal terminals
  • the output clock signal loaded in can be the same or different.
  • FIG. 9 is a schematic diagram of another circuit structure of the shift register provided by the embodiment of the disclosure. As shown in FIG. 9, the difference from the shift register shown in FIG. 5 and FIG. 7 is that in the shift register shown in FIG. An anti-leakage circuit is provided.
  • the leakage prevention circuit includes: a first leakage prevention transistor S1, a second leakage prevention transistor S2, a third leakage prevention transistor S3, a fourth leakage prevention transistor S4, a fifth leakage prevention transistor S5, and a sixth leakage prevention transistor S1.
  • the second electrode of the first display transistor M1 is connected to the pull-up node PU through the second leakage prevention transistor S2, and the second electrode of the second display transistor M2 is connected to the second scanning power terminal R through the third leakage prevention transistor S3.
  • the second electrode of the display transistor M9 is connected to the second power terminal through the fourth leakage prevention transistor S4, the first electrode of the first sensing transistor T1 is connected to the signal output terminal OUT through the sixth leakage prevention transistor S6, and the fourth sensing transistor The second pole of T4 is connected to the second power supply terminal through the seventh anti-leakage transistor S7.
  • the control electrode of the first anti-leakage transistor S1 is connected to the pull-up node PU, the first electrode of the first anti-leakage transistor S1 is connected to the first power supply terminal, and the second electrode of the first anti-leakage transistor S1 is connected to the anti-leakage node E.
  • the control electrode of the second anti-leakage transistor S2 is connected to the first signal input terminal STU1
  • the first electrode of the second anti-leakage transistor S2 is connected to the second electrode of the first display transistor M1 and the anti-leakage node E
  • the second pole of S2 is connected to the pull-up node PU.
  • the control electrode of the third anti-leakage transistor S3 is connected to the second signal input terminal STU2
  • the first electrode of the third anti-leakage transistor S3 is connected to the second electrode of the second display transistor M2 and the anti-leakage node E
  • the second pole of S3 is connected to the second scanning power terminal R.
  • the control electrode of the fourth anti-leakage transistor S4 is connected to the pull-down node PD, the first electrode of the fourth anti-leakage transistor S4 is connected to the second electrode of the ninth display transistor M9 and the anti-leakage node E, and the second electrode of the fourth anti-leakage transistor S4 The two poles are connected with the second power terminal.
  • the control electrode of the fifth anti-leakage transistor S5 is connected to the sensing control node H, the first electrode of the fifth anti-leakage transistor S5 is connected to the first power terminal, and the second electrode of the fifth anti-leakage transistor S5 is connected to the first sensing transistor The first pole of T1 and the second pole of the sixth leakage prevention transistor S6 are connected.
  • the control electrode of the sixth leakage prevention transistor S6 is connected to the random signal terminal OE, the first electrode signal output terminal OUT of the sixth leakage prevention transistor S6 is connected, and the second electrode of the sixth leakage prevention transistor S6 is connected to the first sensing transistor T1.
  • the first pole is connected.
  • the control electrode of the seventh anti-leakage transistor S7 is connected to the sensing reset signal terminal STD, the first electrode of the seventh anti-leakage transistor S7 is connected to the anti-leakage node E and the second electrode of the fourth sensing transistor T4, and the seventh anti-leakage transistor S7 is connected to the second electrode of the fourth sensing transistor T4.
  • the second pole of the transistor S7 is connected to the second power terminal.
  • first leakage prevention transistor S1 By providing the above-mentioned first leakage prevention transistor S1 to the seventh leakage prevention transistor S7, the first display transistor M1, the second display transistor M2, the ninth display transistor M9, the first sensing transistor T1, and the fourth sensing transistor can be effectively prevented T4 generates leakage current.
  • FIG. 10 is a schematic diagram of another circuit structure of the shift register provided by an embodiment of the disclosure. As shown in FIG. 10, the difference from the aforementioned shift register is that the sensing precharge reset in the shift register shown in FIG. 10
  • the circuit 2 includes: a second sensing transistor T2, a third sensing transistor T3, a fourth sensing transistor T4, and a fifth sensing transistor T5.
  • the control electrode of the second sensing transistor T2 is connected to the sensing control node H, the first electrode of the second sensing transistor T2 is connected to the first clock signal terminal CLKA, and the second electrode of the second sensing transistor T2 is connected to the third sensing terminal CLKA.
  • the first electrode of the sensing transistor T3 and the control electrode of the fifth sensing transistor T5 are connected.
  • the control electrode of the third sensing transistor T3 is connected to the pull-down node PD, and the second electrode of the third sensing transistor T3 is connected to the second power terminal.
  • the control electrode of the fourth sensing transistor T4 is connected to the sensing reset signal terminal STD, the first electrode of the fourth sensing transistor T4 is connected to the pull-up node PU, and the second electrode of the fourth sensing transistor T4 is connected to the second power supply .
  • the first pole of the fifth sensing transistor T5 is connected to the first power terminal, and the second pole of the fifth sensing transistor T5 is connected to the pull-up node PU.
  • the shift register of the embodiment of the present disclosure further includes a second capacitor C2, the first terminal of the second capacitor C2 is connected to the sensing control node H, and the second terminal of the second capacitor C2 is connected to the fifth sensing node H.
  • the control electrode of the transistor T5 is connected or connected to the second power supply terminal.
  • the driving sequence of the shift register shown in FIG. 10 may be as shown in FIG. 6, and the driving process of the shift register shown in FIG. 10 is the same as the driving process of the shift register shown in FIG. 6, and will not be repeated here.
  • FIG. 11 is a schematic diagram of another circuit structure of the shift register provided by an embodiment of the disclosure.
  • the number of signal output terminals in this embodiment is 3 , which includes the signal output terminals OUT, OUT' and OUT", correspondingly, the number of output sub-circuits is 3, that is, it includes output sub-circuits 6, 6'and 6".
  • the seventh display transistors M7, M7' and M7" in each output sub-circuit 6, 6'and 6" turn on or off at the same time
  • the eighth display transistors M8, M8 in each output sub-circuit 6, 6'and 6" 'And M8' are turned on or off at the same time.
  • the output sub-circuit 6 and the output sub-circuit 6' are both connected to the output clock signal terminal CLKD, and the output sub-circuit 6" is connected to the output clock signal terminal CLKE.
  • the second pole of the eighth display transistor M8 may also be connected to the second power terminal instead of the reset power terminal.
  • FIG. 12 is a schematic diagram of another circuit structure of the shift register provided by the embodiment of the disclosure. As shown in FIG. 12, the difference from the shift register shown in FIG. 10 and FIG. 11 is that in the shift register shown in FIG. An anti-leakage circuit is provided.
  • the leakage prevention circuit includes: a first leakage prevention transistor S1, a second leakage prevention transistor S2, a third leakage prevention transistor S3, a fourth leakage prevention transistor S4, a fifth leakage prevention transistor S5, and a sixth leakage prevention transistor S1.
  • Anti-leakage transistor S6 and seventh anti-leakage transistor S7 are examples of anti-leakage transistors in FIG. 12, please refer to the description of FIG. 9 in the foregoing embodiment, which will not be repeated here.
  • FIG. 13 is a schematic diagram of a circuit structure of a gate driving circuit provided by an embodiment of the present disclosure.
  • FIG. 14 is a working timing diagram of the gate driving circuit shown in FIG. 13.
  • the gate The driving circuit includes: cascaded N shift registers A1, A2, A3, A4, A5, A6, etc., among which the shift registers A1, A2, A3, A4, A5, A6, etc. are provided by any of the above embodiments
  • For the shift register for the corresponding descriptions of the shift registers A1, A2, A3, A4, A5, and A6, please refer to the corresponding content in the foregoing embodiment, which will not be repeated here.
  • FIG. 13 only exemplarily shows the first 6 stages of shift registers in the gate drive circuit.
  • the gate drive circuit may include N stages of shift registers, and N is a positive integer.
  • the first signal input terminal STU1 of the shift register at the first m stage can be connected to the frame start signal input terminal STV, and the shift register at the i-th stage
  • the first signal input terminal STU1 of may be connected to a signal output terminal OUT of the im-th stage shift register, where m is a preset positive integer, m+1 ⁇ i ⁇ N, and i is a positive integer.
  • the random signal terminal OE of the shift register of each stage can be connected to the random signal input terminal OE'; the second signal input terminal STU2 of the shift register located in the Nm-th stage to the Nth stage can be connected to the frame reset signal input terminal, located at the The second signal input terminal STU2 of the k stage can be connected to a signal output terminal OUT of the shift register of the k+m stage, where 1 ⁇ k ⁇ Nm, and k is a positive integer; the sensing reset of the shift registers of each stage
  • the signal terminal STD can be connected to the sensing reset signal line RST.
  • the first clock signal terminal CLKA of the shift registers of each level can be connected to the first clock signal line CKA, and the sensing reset signal terminal STD of the shift register of each level can be connected to the sensing reset signal line RST.
  • the frame start signal input terminal STV provides a frame start signal
  • the frame reset signal input terminal provides a frame reset signal
  • the frame start signal input terminal STV provides a frame reset signal
  • the frame reset signal input terminal provides a frame start signal
  • the shift registers of each stage are configured with corresponding three signal output terminals (the shift registers of each stage have three output sub-circuits), which are respectively the first cascade signal output terminal OUT and the first drive signal output terminal. Terminal OUT' and the second drive signal output terminal OUT".
  • the signal output terminal connected to the sensing control circuit of the shift register of each stage may be the first cascade signal output terminal OUT corresponding to the shift register of the current stage; the first signal input terminal STU1 of the shift register at the i-th stage It can be connected to the first cascade signal output terminal OUT of the im-th stage shift register; the second signal input terminal STU2 of the k-th stage shift register can be connected to the first stage of the k+m-th shift register
  • the connection signal output terminal OUT is connected; the first drive signal output terminal OUT' and the second drive signal output terminal OUT" of the shift registers of each level can be respectively connected to the two gate lines of the corresponding row.
  • the value of m is 3. That is, the first signal input terminal STU1 of the shift register of the first three stages is connected to the frame start signal input terminal STV, and the second signal input terminal STU2 of the shift register of the N-3 stage to the Nth stage is connected to the frame reset The signal input terminal is connected.
  • the first signal input terminal STU1 of the shift register at the i-th stage is connected to the first cascade signal output terminal OUT of the shift register at the i-3 stage.
  • the second signal input terminal STU2 is connected to the first cascade signal output terminal OUT of the shift register of the k+3 stage.
  • 12 output clock signal lines can be configured, which are respectively 6 first output clock signal lines CKD1 to CKD6 and 6 second output clock signal lines CKE1 to CKE1 to CKE1. CKE6.
  • the output clock signal terminal CKD connected to the output sub-circuit of the first cascade signal output terminal OUT is configured, and the output sub-circuit configured with the first drive signal output terminal OUT'
  • the connected output clock signal terminal CKD is all connected to the first output clock signal line CKD1; the output clock signal terminal CKE and the second output clock signal line CKE1 connected to the output sub-circuit configured with the second drive signal output terminal OUT" Connection, where 6j ⁇ N, and j is an integer.
  • the output clock signal terminal CKD connected to the output sub-circuit of the first cascade signal output terminal OUT is configured, and the output sub-circuit configured with the first drive signal output terminal OUT'
  • the connected output clock signal terminal CKD is all connected to the first output clock signal line CKD2; the output clock signal terminal CKE and the second output clock signal line CKE2 connected to the output sub-circuit configured with the second drive signal output terminal OUT" connect.
  • the output clock signal terminal CKD connected to the output sub-circuit of the first cascade signal output terminal OUT is configured, and the output sub-circuit configured with the first drive signal output terminal OUT'
  • the connected output clock signal terminal CKD is connected to the first output clock signal line CKD3;
  • the output clock signal terminal CKE connected to the output sub-circuit configured with the second drive signal output terminal OUT" is connected to the second output clock signal line CKE3 .
  • the output clock signal terminal CKD connected to the output sub-circuit of the first cascade signal output terminal OUT is configured, and the output sub-circuit configured with the first drive signal output terminal OUT'
  • the connected output clock signal terminal CKD is all connected to the first output clock signal line CKD4; the output clock signal terminal CKE and the second output clock signal line CKE4 connected to the output sub-circuit configured with the second drive signal output terminal OUT" connect.
  • the output clock signal terminal CKD connected to the output sub-circuit of the first cascade signal output terminal OUT is configured, and the output sub-circuit configured with the first drive signal output terminal OUT'
  • the connected output clock signal terminal CKD is all connected to the first output clock signal line CKD5; the output clock signal terminal CKE and the second output clock signal line CKE5 connected to the output sub-circuit configured with the second drive signal output terminal OUT" connect.
  • the output clock signal terminal CKD connected to the output sub-circuit configured with the first cascade signal output terminal OUT and the output sub-circuit configured with the first drive signal output terminal OUT' are connected
  • the output clock signal terminal CKD of is connected to the first output clock signal line CKD6;
  • the output clock signal terminal CKE connected to the output sub-circuit configured with the second drive signal output terminal OUT" is connected to the second output clock signal line CKE6.
  • FIG. 14 only exemplarily shows the driving timing of three consecutive frames when the gate driving circuit performs forward scanning.
  • the embodiments of the present disclosure also provide a display device, which includes a gate drive circuit, and the gate drive circuit adopts the gate drive circuit provided in the above-mentioned embodiments.
  • FIG. 15 is a flowchart of the gate driving method provided by the embodiments of the disclosure. As shown in FIG. 15, the gate driving method is based on the shift register provided in any of the foregoing embodiments. When the gate driving circuit adopts a positive During forward scanning, the gate driving method includes the following steps Q101 to Q106.
  • Step Q101 In the display precharge stage, the display precharge reset circuit responds to the control of the first input signal provided by the first signal input terminal, and writes the first scan voltage in the active level state provided by the first scan power terminal Into the pull-up node; the display noise reduction circuit responds to the control of the first input signal provided by the first signal input terminal, and writes the second scan voltage in the inactive level state provided by the second scan power terminal to the pull-down node .
  • Step Q102 In the display output stage, the output sub-circuit writes the output clock signal provided by the output clock signal terminal to the corresponding signal output terminal in response to the control of the voltage of the pull-up node in the active level state; In the display output stage, the stage where the output clock signal is in the active level state is the sensing control stage. In the sensing control stage, the sensing control circuit responds to the control of the random signal provided by the random signal terminal to output the signal output terminal in effect The output signal of the level state is written to the sensing control node.
  • Step Q103 In the display reset stage, the display precharge reset circuit responds to the control of the second input signal provided by the second signal input terminal, and writes the second scan voltage in the inactive level state provided by the second scan voltage terminal Input to the pull-up node; and, in response to the control of the second input signal provided by the second signal input terminal, the display noise reduction circuit writes the first scan voltage in the active level state provided by the first scan power terminal to the pull-down Node; the output sub-circuit responds to the control of the voltage of the pull-down node in the active level state, and writes the reset working voltage in the inactive level state provided by the reset power terminal to the signal output terminal.
  • Step Q104 In the sensing pre-charge stage, the sensing pre-charge circuit writes the voltage signal in the active level state in response to the control of the voltage of the sensing control node and the first clock signal provided by the first clock signal terminal. Pull the node.
  • Step Q105 In the sensing output stage, the output sub-circuit writes the output clock signal provided by the output clock signal terminal to the corresponding signal output terminal in response to the control of the voltage of the pull-up node in the active level state.
  • Step Q106 In the sensing reset stage, the sensing precharge reset circuit responds to the control of the sensing reset signal provided by the sensing reset signal terminal to control the second operating voltage provided by the second power terminal in an inactive level state Write to the pull-up node; the output sub-circuit responds to the control of the voltage of the pull-down node in the active level state, and writes the reset working voltage in the inactive level state provided by the reset power terminal to the signal output terminal.
  • FIG. 16 is another flowchart of the gate driving method provided by the embodiments of the disclosure. As shown in FIG. 16, the gate driving method is based on the shift register provided in any of the foregoing embodiments. When the gate driving circuit adopts In reverse scanning, the gate driving method includes the following steps S201 to S206.
  • Step S201 In the display precharge stage, the display precharge reset circuit responds to the control of the second input signal provided by the second signal input terminal, and writes the second scan voltage in the active level state provided by the second scan power terminal Into the pull-up node; the display noise reduction circuit responds to the control of the second input signal provided by the second signal input terminal, and writes the first scan voltage in the inactive level state provided by the first scan power terminal to the pull-down node .
  • Step S202 In the display output stage, the output sub-circuit writes the output clock signal provided by the output clock signal terminal to the corresponding signal output terminal in response to the control of the voltage of the pull-up node in the active level state; In the display output stage, the stage where the output clock signal is in the active level state is the sensing control stage. In the sensing control stage, the sensing control circuit responds to the control of the random signal provided by the random signal terminal to output the signal output terminal in effect The output signal of the level state is written to the sensing control node.
  • Step S203 In the display reset stage, the display precharge reset circuit responds to the control of the first input signal provided by the first signal input terminal, and writes the first scan voltage in the inactive level state provided by the first scan power terminal Input to the pull-up node; and, in response to the control of the first input signal provided by the first signal input terminal, the display noise reduction circuit writes the second scan voltage in the active level state provided by the second scan power terminal to the pull-down Node:
  • the output sub-circuit responds to the control of the voltage of the pull-down node in the active level state, and writes the reset working voltage in the inactive level state provided by the reset power terminal to the signal output terminal.
  • Step S204 In the sensing pre-charge stage, the sensing pre-charge reset circuit responds to the voltage of the sensing control node and the control of the first clock signal provided by the first clock signal terminal to write the voltage signal in a valid level state To the pull node.
  • Step S205 In the sensing output stage, the output sub-circuit writes the output clock signal provided by the output clock signal terminal to the corresponding signal output terminal in response to the control of the voltage of the pull-up node in the active level state.
  • Step S206 In the sensing reset stage, the sensing precharge reset circuit responds to the sensing reset signal control provided by the sensing reset signal terminal to control the second operating voltage provided by the second power terminal in an inactive level state. Write to the pull-up node; the output sub-circuit responds to the control of the voltage of the pull-down node in the active level state, and writes the reset working voltage in the inactive level state provided by the reset power terminal to the signal output terminal.
  • the low-level working voltage VGL1 can be less than the low-level working voltage VGL2, that is, the potential of VGL2 can be higher than the potential of VGL1 (generally, both VGL1 and VGL2 are negative potentials). DC low potential signal.
  • the values of the low-level operating voltages VGL1 and VGL2 may be the same or different according to needs, and the embodiments of the present disclosure do not specifically limit this.

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Abstract

Registre à décalage, circuit d'attaque de grille et procédé d'attaque de grille. Le registre à décalage comprend : un circuit de réinitialisation de précharge d'affichage (3), un circuit de commande de détection (1), un circuit de réinitialisation de précharge de détection (2), un circuit de commande d'excursion basse (4), un circuit de réduction de bruit d'affichage (5) et un circuit de sortie. Le circuit de commande de détection (1) et le circuit de réinitialisation de précharge de détection (2) sont connectés à un nœud de commande de détection. Le circuit de réinitialisation de précharge d'affichage (3), le circuit de réinitialisation de précharge de détection (2), le circuit de commande d'excursion basse (4) et le circuit de sortie sont connectés à un nœud d'excursion haute (PU). Le circuit de commande d'excursion basse (4), le circuit de réduction de bruit d'affichage (5) et le circuit de sortie sont connectés à un nœud d'excursion basse (PD). Le circuit de sortie est conçu pour comporter une ou plusieurs bornes de sortie de signal (OUT) et comprend un ou plusieurs sous-circuits de sortie (6) disposés en correspondance biunivoque avec les bornes de sortie de signal (OUT). Le circuit de réinitialisation de précharge d'affichage (3) est connecté à une première borne d'entrée de signal (STU1), à une seconde borne d'entrée de signal (STU2), à une première borne d'alimentation électrique de balayage (D) et à une seconde borne d'alimentation électrique de balayage (R), et est conçu pour écrire, en réponse à la commande de la première borne d'entrée de signal (STU1), une première tension de balayage fournie par la première borne d'alimentation électrique de balayage (D) sur le nœud d'excursion haute (PU), et pour écrire, en réponse à la commande de la seconde borne d'entrée de signal (STU2), une seconde tension de balayage fournie par la seconde borne d'alimentation électrique de balayage (R) sur le nœud d'excursion haute (PU). Le circuit de réduction de bruit d'affichage (5) est connecté à la première borne d'entrée de signal (STU1), à la seconde borne d'entrée de signal (STU2), à la première borne d'alimentation électrique de balayage (D) et à la seconde borne d'alimentation électrique de balayage (R), et est conçu pour écrire, en réponse à la commande de la première borne d'entrée de signal (STU1), la seconde tension de balayage sur le nœud d'excursion basse (PD), et pour écrire, en réponse à la commande de la seconde d'entrée de signal (STU2), la première tension de balayage sur le nœud d'excursion basse (PD).
PCT/CN2021/073253 2020-01-22 2021-01-22 Registre à décalage, circuit d'attaque de grille, dispositif d'affichage et procédé d'attaque de grille WO2021147990A1 (fr)

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CN114299878A (zh) * 2022-01-21 2022-04-08 合肥京东方卓印科技有限公司 扫描驱动电路及其修复方法、显示装置

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CN111179808B (zh) 2020-01-22 2023-04-18 合肥京东方卓印科技有限公司 移位寄存器、栅极驱动电路、显示装置和栅极驱动方法
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CN114596817B (zh) * 2022-03-23 2023-11-21 合肥京东方卓印科技有限公司 移位寄存器单元、栅极驱动电路、显示面板和显示装置
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