WO2024012437A1 - 横向绝缘栅双极晶体管及其制备方法 - Google Patents

横向绝缘栅双极晶体管及其制备方法 Download PDF

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Publication number
WO2024012437A1
WO2024012437A1 PCT/CN2023/106736 CN2023106736W WO2024012437A1 WO 2024012437 A1 WO2024012437 A1 WO 2024012437A1 CN 2023106736 W CN2023106736 W CN 2023106736W WO 2024012437 A1 WO2024012437 A1 WO 2024012437A1
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region
bipolar transistor
conductivity type
insulated gate
gate bipolar
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French (fr)
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刘腾
张森
何乃龙
赵景川
章文通
文天龙
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 

Definitions

  • the present application relates to the field of semiconductor technology, and in particular to lateral insulated gate bipolar transistors and preparation methods thereof.
  • Lateral Insulated-Gate Bipolar Transistor has the advantages of large current handling capability, low saturation voltage, small switching loss, simple driving circuit and low driving power. It is currently the most ideal power switching device. Lateral insulated gate bipolar transistors are widely used in electrode control, medium frequency switching power supplies, inverters and air conditioners.
  • a lateral insulated gate bipolar transistor and a preparation method thereof are provided to solve at least one of the above technical problems.
  • a lateral insulated gate bipolar transistor includes a drift region, a first well region, a first electrode extraction region, a second electrode extraction region and a conductance modulation structure.
  • the drift region has a first conductivity type, and the first well region is located in the drift region.
  • the upper surface layer has a second conductivity type, and the first conductivity type and the second conductivity type are opposite.
  • the first electrode lead-out area is provided on the upper surface layer of the first well area, and the second electrode lead-out area is provided on the upper surface layer of the drift area.
  • the conductivity modulation structure is disposed in the drift region between the first electrode lead-out area and the second electrode lead-out area.
  • the conductivity modulation structure includes a first doping region disposed on the upper surface layer of the drift region and having a first conductivity type, and a conductivity modulation structure disposed in the drift region.
  • the first doping region has a second doping region of the second conductivity type, and the doping concentration of the first doping region is greater than the doping concentration of the drift region.
  • the number of each of the first doped region and the second doped region is at least one.
  • both the first doping region and the second doping region are set in the floating position; or, the first doping region is set in the floating position, and the second doping region is connected to an external potential.
  • the doping depth of the first doping region is smaller than the doping depth of the first well region.
  • the doping concentration values of the first doped region and the second doped region are of the same order of magnitude.
  • the upper surface layer of the drift region is provided with at least one set of conductance modulation structure components, and each conductance modulation structure component includes a plurality of conductance modulation structures spaced apart along the length direction of the conductive channel.
  • the upper surface layer of the drift region is provided with a plurality of groups of conductivity modulation structure components spaced apart along the width direction of the conductive channel.
  • the lateral insulated gate bipolar transistor further includes a second well region disposed on the upper surface layer of the drift region and having a first conductivity type.
  • the second well region is located in a part of the entire conductance modulation structure away from the first well region. side.
  • the upper surface layer of the second well region is provided with a second electrode lead-out area, the second electrode lead-out area has the second conductivity type, and the first electrode lead-out area has the first conductivity type.
  • the upper surface layer of the first well region is further provided with a first well region lead-out region having a second conductivity type, and the potentials of the first well region lead-out region and the first electrode lead-out region are short-circuited together.
  • the lateral insulated gate bipolar transistor further includes a semiconductor substrate.
  • the semiconductor substrate includes a stacked substrate and a buried dielectric layer, and the drift region is provided on a side of the buried dielectric layer facing away from the substrate.
  • the lateral insulated gate bipolar transistor further includes a gate structure, the gate structure is located on the first well region, one side of the gate structure extends to cover a part of the first electrode lead-out region, and the gate structure The other side extends to cover part of the drift zone.
  • a field oxide layer is further provided on the upper surface of the drift region.
  • the gate structure includes a gate dielectric layer and a gate conductive layer.
  • the gate dielectric layer is disposed on the first well region and has one end extending to cover the first well region. The other end of a part of the electrode lead-out area extends to cover the drift area not covered by the field oxide layer, and is in contact with the field oxide layer.
  • the gate conductive layer is formed on the gate dielectric layer, and the side of the gate conductive layer away from the first electrode lead-out region also extends to cover a part of the field oxide layer.
  • the orthographic projection of all the conductance modulation structures on the drift region and the orthographic projection of the gate conductive layer on the drift region are arranged at a lateral distance.
  • a method for preparing a lateral insulated gate bipolar transistor including: providing a semiconductor substrate, the semiconductor substrate including a substrate having a second conductivity type; forming a drift region above the substrate on the semiconductor substrate, the drift region having a first The conductivity type, the first conductivity type and the second conductivity type are opposite; a first well region with the second conductivity type is formed on the upper surface layer of the drift region; a conductance modulation structure spaced apart from the first well region is formed in the drift region, the conductivity
  • the modulation structure includes a first doping region formed on the upper surface layer of the drift region and having a first conductivity type, and a second doping region formed in the first doping region and having a second conductivity type.
  • the first doping region The doping concentration is greater than that of the drift region; a first electrode extraction region and a second electrode extraction region are formed, the first electrode extraction region is formed on the upper surface layer of the first well region, and the second electrode extraction region is formed on the entire conductance modulation The side of the structure away from the first well region.
  • forming a conductance modulation structure spaced apart from the first well region in the drift region includes: injecting first conductivity type ions into part of the upper surface layer of the drift region, and pushing the well to form a first doping region; Implanting ions of the second conductivity type into the first doping region and pushing the well to form a second doping region.
  • Figure 1 is a schematic structural diagram of a lateral insulated gate bipolar transistor in the first embodiment
  • Figure 2 is a schematic structural diagram of a lateral insulated gate bipolar transistor in the second embodiment
  • Figure 3 is a schematic structural diagram of a lateral insulated gate bipolar transistor in the third embodiment
  • FIG. 4 is a flow chart of a method for manufacturing a lateral insulated gate bipolar transistor according to one or more embodiments.
  • 110 Semiconductor base; 111. Substrate; 112. Buried dielectric layer; 120. Drift area; 130. First electrode lead-out area; 140. Second electrode lead-out area; 150. Gate structure; 151. Field oxidation layer; 160, conductance modulation structure; 161, first doped region; 162, second doped region; 171, first well region; 172, first well region extraction region; 180, second well region.
  • an embodiment means that a particular feature, structure or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application.
  • the appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art understand, both explicitly and implicitly, that the embodiments described herein may be combined with other embodiments.
  • Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present application. Thus, variations from the shapes shown may be anticipated due, for example, to manufacturing techniques and/or tolerances. Thus, embodiments of the present application should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region that appears as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by an implant may result in some implantation in the area between the buried region and the surface through which the implant occurs. Therefore, the regions shown in the figures are schematic in nature and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the present application.
  • P-type and N-type impurities in order to distinguish the doping concentration, P+ type simply represents P type with heavy doping concentration, and P type represents medium doping concentration.
  • P-type with doping concentration P-type represents P-type with light doping concentration
  • N+ type represents N-type with heavy doping concentration
  • N-type represents N-type with medium doping concentration
  • N-type represents light doping concentration.
  • a lateral insulated gate bipolar transistor provided by an embodiment of the present application includes a drift region 120 , a first well region 171 , a first electrode extraction region 130 , a second electrode extraction region 140 and Conductance modulation structure 160.
  • the drift region 120 has a first conductivity type.
  • the first well region 171 is provided on the upper surface layer of the drift region 120.
  • the first well region 171 has a second conductivity type.
  • the first conductivity type and the second conductivity type are opposite.
  • One of the first conductivity type and the second conductivity type is P type, and the other type is N type.
  • the first conductivity type is N type and the second conductivity type is P type; or the first conductivity type is P type and the second conductivity type is N type.
  • the first electrode lead-out area 130 is provided on the upper surface layer of the first well area 171
  • the second electrode lead-out area 140 is provided on the upper surface layer of the drift area 120
  • the conductance modulation structure 160 is provided on the first electrode lead-out area 130 and the second electrode lead-out area
  • the conductance modulation structure 160 includes a first doped region 161 with a first conductivity type located on the upper surface layer of the drift region 120, and a first doped region 161 with a second conductivity located within the first doped region 161.
  • the doping concentration of the first doping region 161 is greater than the doping concentration of the drift region 120 .
  • the first doping region 161 has a first conductivity type
  • the second doping region 162 has a second conductivity type, so a PN junction can be formed between the first doping region 161 and the second doping region 162 .
  • the first conductivity type is N type
  • the second conductivity type is P type
  • the conductivity type of the first doped region 161 and the drift region 120 is N type
  • the second doped region 162 The conductivity type is P type.
  • the conductive channel of the lateral insulated gate bipolar transistor is opened, and electrons enter the drift region 120 from the first electrode lead-out area 130 through the conductive channel.
  • the number of electrons is increasing, and a large number of electrons rush to the second electrode lead-out region 140, and gradually form a voltage drop in the drift region 120. This voltage drop causes the formation of a pressure drop between the first doping region 161 and the second doping region 162.
  • the PN junction is forward-conducting, and a large number of holes are injected into the drift region 120 together with the second electrode lead-out region 140 to form a conductance modulation effect, which greatly reduces the on-state voltage drop of the lateral insulated gate bipolar transistor and reduces the lateral insulation Static power dissipation of gate bipolar transistors.
  • a superjunction-like structure is formed between the first doped region 161 and the second doped region 162, which can assist each other in depletion, so that the electric field will not break down in advance and will not affect the improvement. Withstand voltage of lateral insulated gate bipolar transistors. That is, while reducing the static power consumption of the device, a significant reduction in breakdown voltage is effectively avoided.
  • the doping concentration of the first doping region 161 is greater than the doping concentration of the drift region 120, which can increase the doping concentration of the drift region 120 and reduce the on-resistance.
  • the conductive channel of the lateral insulated gate bipolar transistor is opened, and electrons enter the drift region 120 from the first electrode extraction region 130 through the conductive channel.
  • the doping concentration is greater than the doping concentration of the drift region 120, which can make the drift region 120 less resistant to electrons, so that more and more electrons flow into the second electrode lead-out region 140, and an electron is formed in the drift region 120 faster.
  • the voltage drop of the forward conduction of the PN junction formed between the first doped region 161 and the second doped region 162 can inject a large number of holes into the drift region 120 together with the second electrode lead-out region 140 after the PN junction is forward-conducted. , forming a conductance modulation effect, greatly reducing the on-state voltage drop of the lateral insulated gate bipolar transistor, and reducing the static power consumption of the lateral insulated gate bipolar transistor.
  • the doping concentration of the first doped region 161 is too high, the holes that surge in after the forward bias of the parasitic PN diode formed between the first doped region 161 and the second doped region 162 will be absorbed by the second doped region 161 .
  • a doped region 161 is recombined. from shutdown state From the perspective of breakdown voltage, if the doping concentration of the first doping region 161 and the second doping region 162 is too high, it will cause the first doping region 161 and the The parasitic PN diode formed between the two doped regions 162 introduces a new electric field, causing premature breakdown of the device.
  • the doping concentration and volume of the first doping region 161 and the second doping region 162 need to be reasonably set according to the doping concentration of the drift region 120 and the requirements of the device, so as to meet the requirements of the lateral insulated gate bipolar transistor.
  • the number of the first doping region 161 and the second doping region 162 is at least one.
  • the number of the first doping region 161 and the second doping region 162 may be one or multiple.
  • a first doping region 161 may be provided with a plurality of independent second doping regions 162, and the first doping region 161 may have a generally thin layer structure.
  • the number of conductance modulation structures 160 needs to be reasonably set according to the doping concentration of the drift region 120 and the requirements of the device, so as to meet the on-state voltage drop and withstand voltage requirements of the lateral insulated gate bipolar transistor. It can also be understood that the arrangement of the conductance modulation structure 160 of the present application can ensure that the first doped region 161 and the second doped region 162 added in the drift region 120 are zero-biased in the static state. At this time, it is similar to a superjunction mutual interaction. At the same time, it is necessary to ensure that the remaining concentration and area of the first doped region 161 will not affect the depletion region of the drift region, and to avoid adding too many first doped regions 161 that cannot be consumed by the second doped region 162. This will cause the depletion region of the drift region to shrink as much as possible to avoid affecting the breakdown voltage of the device.
  • FIG. 3 shows an example of a first doped region 161 and a second doped region 162.
  • the conductance modulation structure 160 can form a low-resistance path for hole injection in the drift region 120, forming a significant conductance modulation effect, greatly reducing the on-state voltage drop of the lateral insulated gate bipolar transistor, and can effectively reduce the lateral voltage drop of the lateral insulated gate bipolar transistor. Static power dissipation of insulated gate bipolar transistors.
  • both the first doped region 161 and the second doped region 162 are provided in a floating state.
  • the first doped region 161 is provided in a floating state, and the second doped region 162 is connected to an external potential.
  • the doping depth of the first doped region 161 is smaller than the doping depth of the first well region 171 .
  • the doping concentration values of the first doped region 161 and the second doped region 162 are of the same order of magnitude, which can well meet the on-state voltage drop, withstand voltage and other requirements of the lateral insulated gate bipolar transistor. .
  • the upper surface layer of the drift region 120 is provided with at least one set of conductance modulation structural components.
  • Each conductance modulation structural component includes a plurality of conductance modulation components spaced apart along the length direction of the conductive channel. Structure160.
  • the conductive channel of the lateral insulated gate bipolar transistor is opened. It can be understood that the conductive channel is formed in the first well region 171 , so that electrons pass through the first electrode extraction region 130 When the conductive channel enters the drift region 120 and flows toward the second electrode lead-out region 140, as more and more electrons rush toward the second electrode lead-out region 140, Out of the region 140, a voltage drop can be formed in the drift region 120 to cause the PN junction formed between the first doped region 161 and the second doped region 162 in each conductance modulation structure 160 to conduct forward.
  • the plurality of conductance modulation structures 160 are not connected together, which can leave sufficient carrier movement paths for the drift region 120 .
  • the length direction of the conductive channel is parallel to the x-axis direction.
  • the upper surface layer of the drift region 120 is provided with multiple sets of conductivity modulation structure components spaced apart along the width direction of the conductive channel.
  • the width direction of the conductive channel is parallel to the y-axis direction.
  • the conductive channel of the lateral insulated gate bipolar transistor is opened, and more and more electrons flow from the first electrode lead-out area 130 to the second electrode lead-out area 140 through the conductive channel.
  • a voltage drop can be formed in the drift region 120 to cause the PN junction formed between the first doped region 161 and the second doped region 162 in each conductance modulation structure 160 to conduct forward.
  • the conductance modulation structure 160 can make the drift region 120 form a low-resistance path for hole injection, forming a significant conductance modulation effect, greatly reducing the on-state voltage drop of the lateral insulated gate bipolar transistor, and effectively reducing the lateral insulated gate bipolar transistor. static power dissipation of the transistor.
  • the lateral insulated gate bipolar transistor further includes a second well region 180 disposed on the upper surface layer of the drift region 120 and having a first conductivity type.
  • the second well region 180 is located away from the entire conductance modulation structure 160 and the first well.
  • a second electrode lead-out region 140 is provided on the upper surface of the second well region 180.
  • the second electrode lead-out region 140 has the second conductivity type
  • the first electrode lead-out region 130 has the first conductivity type. It can also be understood that all conductance modulation structures 160 are located in the drift region 120 between the first well region 171 and the second well region 180 .
  • the carriers stored in the drift region 120 that produce a conductance modulation effect in the on state can quickly flow to the drain through the second well region 180 of the first conductivity type. Effectively shorten the shutdown time.
  • the PN junction formed between the second electrode lead-out region 140 and the second well region 180 is reverse-biased, which can effectively prevent the second electrode lead-out region 140 from breakdown and improve the lateral Voltage withstand capabilities of insulated gate bipolar transistors.
  • the upper surface layer of the first well region 171 is also provided with a first well region lead-out region 172 having a second conductivity type.
  • the potentials of the first well region lead-out region 172 and the first electrode lead-out region 130 are short-circuited at Together.
  • the first electrode extraction region 130, the first well region extraction region 172 and the drift region 120 together form a parasitic NPN transistor. If the first well region 171 is not provided, when the lateral insulated gate bipolar transistor is turned on and satisfies Parasitic NPN After the base minority carrier of the transistor can cross the condition, the parasitic NPN transistor may be turned on, which will cause the lateral insulated gate bipolar transistor to fail during the turn-on stage. On the contrary, adding a first well region 171 of the second conductivity type below the extraction region 172 of the first well region of the second conductivity type can increase the base concentration of the parasitic NPN tube, and the minority carrier lifetime is reduced and cannot transition to the emission state.
  • Adding the first well region 171 is equivalent to forming a gradually changing channel doping in the first well region extraction region 172 and the first well region 171, which can adjust the threshold voltage, reduce the resistance of the substrate 111, prevent the parasitic NPN transistor from turning on, and The concentration of the first well region 171 can be increased, the channel length can be shortened, the on-resistance can be reduced, and the device area can be reduced.
  • the lateral insulated gate bipolar transistor further includes a semiconductor substrate 110.
  • the semiconductor substrate 110 includes a stacked substrate 111 and a buried dielectric layer 112.
  • the drift region 120 is provided on a side of the buried dielectric layer 112 facing away from the substrate 111.
  • the substrate 111 has the second conductivity type.
  • the second electrode lead-out region 140, the drift region 120 and the substrate 111 together form a PNP transistor.
  • the lateral insulated gate bipolar transistor when the lateral insulated gate bipolar transistor is turned on, it is very easy to turn on the PNP transistor and cause leakage.
  • the terminal current flows to the substrate 111 through this PNP transistor, causing failure. Therefore, a buried dielectric layer 112 is provided between the substrate 111 and the drift region 120.
  • the buried dielectric layer 112 achieves electrical isolation between the drift region 120 and the substrate 111, thereby avoiding the formation of the PNP transistor and effectively avoiding leakage and making the lateral insulated gate Bipolar transistors have the advantages of low leakage, low on-state resistance, and latch-up resistance.
  • the lateral insulated gate bipolar transistor further includes a gate structure.
  • the gate structure 150 is located on the first well region 171 .
  • One side of the gate structure 150 extends to cover a part of the first electrode lead-out region 130 .
  • the other side of the pole structure 150 extends to cover a portion of the drift region 120 .
  • a field oxide layer 151 is also provided on the upper surface of the drift region 120 .
  • the gate structure 150 also extends to cover a part of the field oxide layer 151 , and extends to cover the gate conductive layer on the field oxide layer 151 as a field. plate.
  • the gate structure 150 includes a gate dielectric layer and a gate conductive layer (the gate dielectric layer is not shown in FIGS. 1, 2, and 3 of this application), and the gate dielectric layer is disposed in the first well region. 171 , and one end extends to cover a part of the first electrode lead-out region 130 , and the other end extends to cover the drift region 120 that is not covered by the field oxide layer 151 , and is in contact with the field oxide layer 151 .
  • the gate conductive layer is formed on the gate dielectric layer, and the side of the gate conductive layer away from the first electrode lead-out region 130 also extends to cover a portion of the field oxide layer 151 .
  • the gate structure 150 is disposed on part of the first well region 171.
  • the first well region 171 and the gate structure 150 have an overlapping area for forming a conductive channel.
  • the gate structure 150 can also serve as an injection barrier layer for the first electrode lead-out region 130, so that the first electrode lead-out region 130 can perform self-aligned injection to ensure conductivity. The width of the channel.
  • the material of the gate conductive layer may be polysilicon material, or may be metal, metal nitride, or metal silicide, which is not specifically limited here.
  • the gate dielectric layer may include, but is not limited to, a silicon oxide layer.
  • the method of forming the gate dielectric layer can be chemical vapor deposition. process, physical vapor deposition process, atomic layer deposition process or In-Situ Steam Generation (ISSG) process, which are not specifically limited here.
  • the orthographic projection of all conductance modulation structures 160 on the drift region 120 is spaced in the lateral direction from the orthographic projection of the gate conductive layer on the drift region 120 . That is, the conductance modulation structure 160 is not disposed under the gate conductive layer, but is disposed between the gate conductive layer and the second well region 180 . The gate voltage of the gate conductive layer is prevented from affecting the conductance modulation structure 160 so as to better utilize the conductance modulation structure 160 to reduce the on-state voltage drop of the lateral insulated gate bipolar transistor.
  • FIG. 4 is a flow chart of a method for manufacturing a lateral insulated gate bipolar transistor in an embodiment, including the following steps:
  • the semiconductor substrate includes a substrate, and the substrate has a second conductivity type.
  • the drift region has a first conductivity type, and the first conductivity type and the second conductivity type are opposite.
  • the conductance modulation structure includes a first doping region formed on the upper surface layer of the drift region and having a first conductivity type, and a first doping region formed on the upper surface layer of the drift region. There is a second doped region of the second conductivity type in the region, and the doping concentration of the first doped region is greater than the doping concentration of the drift region.
  • first electrode lead-out area Form a first electrode lead-out area and a second electrode lead-out area.
  • the first electrode lead-out area is formed on the upper surface layer of the first well area, and the second electrode lead-out area is formed on the side of the entire conductance modulation structure away from the first well area.
  • the conductive channel of the lateral insulated gate bipolar transistor When the lateral insulated gate bipolar transistor is turned on, the conductive channel of the lateral insulated gate bipolar transistor is opened, and electrons pass through the first electrode lead-out area. The conductive channel enters the drift region. As the number of electrons increases, a large number of electrons rush to the second electrode extraction region and gradually form a voltage drop in the drift region.
  • This voltage drop causes the first doped region and the second doped region to
  • the PN junction formed between the impurity regions is forward-conducting, and together with the second electrode extraction region, a large number of holes are injected into the drift region, forming a conductance modulation effect, which greatly reduces the on-state voltage drop of the lateral insulated gate bipolar transistor, and reduces The static power consumption of lateral insulated gate bipolar transistors.
  • the lateral insulated gate bipolar transistor is turned off, a superjunction-like structure is formed between the first doped region and the second doped region, which can assist each other in depletion, so that the electric field will not break down in advance and will not affect the improvement of lateral insulation.
  • Withstand voltage of gate bipolar transistor That is, while reducing the static power consumption of the device, a significant reduction in breakdown voltage is effectively avoided.
  • the semiconductor substrate includes a stacked substrate and a buried dielectric layer, the second conductivity type is P-type, and the first conductivity type is N-type.
  • the substrate is a P-type silicon substrate, and the drift The area is the N-drift area.
  • the second conductivity type may be N-type and the first conductivity type may be P-type.
  • the buried dielectric layer is made of silicon oxide, such as silicon dioxide.
  • the drift region is implemented by high-temperature well pushing after implantation, and a certain doping concentration is required to ensure a current path.
  • step S230 while forming the first well region with the second conductivity type on the upper surface layer of the drift region, a second well region with the first conductivity type is also formed on the upper surface layer of the drift region, and the The second well region is spaced apart from the first well region; then in step S240, the conductance modulation structure is formed in the drift region between the first well region and the second well region; then in step S250, the second electrode extraction region is formed On the upper surface layer of the second well region, the second electrode lead-out area has the second conductivity type, and the first electrode lead-out area has the first conductivity type.
  • the stored carriers generated by the conductance modulation effect in the on-state in the drift region can quickly flow to the drain through the second well region of the first conductivity type, effectively shortening the off time.
  • the PN junction formed between the second electrode lead-out area and the second well area is reverse biased, which can effectively prevent breakdown of the second electrode lead-out area and improve the lateral insulated gate bipolar transistor. voltage resistance of the transistor.
  • forming a conductivity modulation structure spaced apart from the first well region in the drift region in step S240 includes: injecting first conductivity type ions into part of the upper surface layer of the drift region, and pushing the well to form a first doping region; inject ions of the second conductivity type into the first doping region, and push the well to form a second doping region, and the second doping region of the second conductivity type is surrounded by the first doping region of the first conductivity type, A PN junction can be formed between the first doped region and the second doped region.
  • step S240 and before step S250 it further includes:
  • step S2403. Form a gate conductive layer on the gate dielectric layer, and the gate conductive layer also extends to cover a part of the field oxide layer; then in step S250, the gate structure serves as an injection barrier layer for the first electrode extraction region to perform automatic In alignment with the implantation, a first electrode extraction region is formed on the upper surface layer of the first well region, and a part of the first electrode extraction region extends under the gate structure to ensure the width of the conductive channel.
  • step S250 includes: first forming a first electrode lead-out area; and then forming a second electrode lead-out area.
  • a first well area lead-out area is also formed.
  • the first well area lead-out area is also formed.
  • the region is formed on the upper surface layer of the first well region, the first well region lead-out region and the second electrode lead-out region both have a second conductivity type, the first electrode lead-out region has a first conductivity type, and a conductance modulation structure is formed in the first well region In the drift area between the first electrode lead-out area and the second electrode lead-out area, it can also be understood that the conductance modulation structure is formed in the drift area between the first electrode lead-out area and the second electrode lead-out area.
  • each step in the flow chart in the above embodiment is displayed in sequence according to the arrow prompts, these steps are not necessarily executed in the order indicated by the arrow. Unless explicitly stated in this article, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in the above flow chart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but may be executed at different times. The execution sequence is not necessarily sequential, but may be performed in turn or alternately with other steps or sub-steps of other steps or at least part of the stages. It should be noted that the above different embodiments can be combined with each other.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

本申请涉及一种横向绝缘栅双极晶体管及其制备方法。横向绝缘栅双极晶体管包括漂移区(120)、第一阱区(171)、第一电极引出区(130)、第二电极引出区(140)和电导调制结构(160)。漂移区(120)具有第一导电类型，第一阱区(171)设于漂移区(120)的上表层，且具有第二导电类型。电导调制结构(160)设于第一电极引出区(130)和第二电极引出区(140)之间的漂移区(120)内，电导调制结构(160)包括设于漂移区(120)的上表层且具有第一导电类型的第一掺杂区(161)，以及设于第一掺杂区(161)内且具有第二导电类型的第二掺杂区(162)。第一掺杂区(161)的掺杂浓度大于漂移区(120)的掺杂浓度。

Description

横向绝缘栅双极晶体管及其制备方法
相关申请的交叉引用
本申请引用于2022年07月12日递交的名称为“横向绝缘栅双极晶体管及其制备方法”的第202210816463.X号中国专利申请，其通过引用被全部并入本申请。
技术领域
本申请涉及半导体技术领域，特别是涉及横向绝缘栅双极晶体管及其制备方法。
背景技术
横向绝缘栅双极晶体管(Lateral Insulated-Gate Bipolar Transistor，LIGBT)具有电流处理能力大、饱和压降低、开关损耗小、驱动电路简单和驱动功率小等优点，是目前最理想的功率开关器件。横向绝缘栅双极晶体管广泛应用于电极控制、中频开关电源、逆变器和空调器等领域。
然而，传统的横向绝缘栅双极晶体管存在通态压降无法满足使用需求、静态功耗高、提前击穿等缺陷。
发明内容
根据本申请的各种实施例，提供一种横向绝缘栅双极晶体管及其制备方法，以解决上述至少一个技术问题。
为了实现本申请的目的，本申请采用如下技术方案：
一种横向绝缘栅双极晶体管，包括漂移区、第一阱区、第一电极引出区、第二电极引出区和电导调制结构，漂移区具有第一导电类型，第一阱区设于漂移区的上表层，且具有第二导电类型，第一导电类型和第二导电类型相反。第一电极引出区设于第一阱区的上表层，第二电极引出区设于漂移区的上表层。电导调制结构设于第一电极引出区和第二电极引出区之间的漂移区内，电导调制结构包括设于漂移区的上表层且具有第一导电类型的第一掺杂区，以及设于第一掺杂区内且具有第二导电类型的第二掺杂区，第一掺杂区的掺杂浓度大于漂移区的掺杂浓度。
在其中一个实施例中，第一掺杂区和第二掺杂区的数量均为至少一个。
在其中一个实施例中，第一掺杂区和第二掺杂区均浮空设置；或，第一掺杂区浮空设置，第二掺杂区外接电位。
在其中一个实施例中，第一掺杂区的掺杂深度小于第一阱区的掺杂深度。
在其中一个实施例中，第一掺杂区和第二掺杂区的掺杂浓度值的数量级相同。
在其中一个实施例中，漂移区的上表层设有至少一组电导调制结构组件，每一电导调制结构组件包括沿导电沟道的长度方向间隔布设的多个电导调制结构。
在其中一个实施例中，漂移区的上表层设有沿导电沟道的宽度方向间隔布设的多组电导调制结构组件。
在其中一个实施例中，横向绝缘栅双极晶体管还包括设于漂移区的上表层且具有第一导电类型的第二阱区，第二阱区位于全部电导调制结构远离第一阱区的一侧。第二阱区的上表层设有第二电极引出区，第二电极引出区具有第二导电类型，第一电极引出区具有第一导电类型。
在其中一个实施例中，第一阱区的上表层还设有具有第二导电类型的第一阱区引出区，第一阱区引出区与第一电极引出区的电位短接在一起。
在其中一个实施例中，横向绝缘栅双极晶体管还包括半导体基底，半导体基底包括层叠设置的衬底和掩埋介质层，漂移区设于掩埋介质层背离衬底的一侧。
在其中一个实施例中，横向绝缘栅双极晶体管还包括栅极结构，栅极结构位于第一阱区上，栅极结构的一侧延伸覆盖至第一电极引出区的一部分，栅极结构的另一侧延伸覆盖至漂移区的一部分。
在其中一个实施例中，在漂移区上表面还设有场氧化层，栅极结构包括栅介质层和栅极导电层，栅介质层设于第一阱区上，且一端延伸覆盖至第一电极引出区的一部分，另一端延伸覆盖至未被场氧化层覆盖的漂移区上，并与场氧化层接触。栅极导电层形成于栅介质层上，栅极导电层远离第一电极引出区的一侧还延伸覆盖至场氧化层的一部分。
在其中一个实施例中，全部所述电导调制结构在所述漂移区上的正投影，与所述栅极导电层在所述漂移区上的正投影之间沿横向间隔设置。
一种横向绝缘栅双极晶体管的制备方法，包括：提供半导体基底，半导体基底包括衬底，衬底具有第二导电类型；在半导体基底上形成位于衬底上方的漂移区，漂移区具有第一导电类型，第一导电类型和第二导电类型相反；在漂移区的上表层形成具有第二导电类型的第一阱区；在漂移区内形成与第一阱区间隔设置的电导调制结构，电导调制结构包括形成于漂移区的上表层且具有第一导电类型的第一掺杂区，以及形成于第一掺杂区内且具有第二导电类型的第二掺杂区，第一掺杂区的掺杂浓度大于漂移区的掺杂浓度；形成第一电极引出区和第二电极引出区，第一电极引出区形成于第一阱区的上表层，第二电极引出区形成于全部电导调制结构远离第一阱区的一侧。
在其中一个实施例中，在漂移区内形成与第一阱区间隔设置的电导调制结构，包括：向漂移区的部分上表层注入第一导电类型离子，并推阱形成第一掺杂区；向第一掺杂区内注入第二导电类型离子，并推阱形成第二掺杂区。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
通过阅读对下文优选实施方式的详细描述，各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。同时，为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围限制。
图1为第一实施例中横向绝缘栅双极晶体管的结构示意图；
图2为第二实施例中横向绝缘栅双极晶体管的结构示意图；
图3为第三实施例中横向绝缘栅双极晶体管的结构示意图；
图4为根据一个或多个实施例提供的横向绝缘栅双极晶体管的制备方法的流程图。
图中：110、半导体基底；111、衬底；112、掩埋介质层；120、漂移区；130、第一电极引出区；140、第二电极引出区；150、栅极结构；151、场氧化层；160、电导调制结构；161、第一掺杂区；162、第二掺杂区；171、第一阱区；172、第一阱区引出区；180、第二阱区。
具体实施方式
下面将结合附图对本申请技术方案的实施例进行详细的描述。以下实施例仅用于更加清楚地说明本申请的技术方案，因此只作为示例，而不能以此来限制本申请的保护范围。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同；本文中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请；本申请的说明书和权利要求书及上述附图说明中的术语“包括”和“具有”以及它们的任何变形，意图在于覆盖不排他的包含。
在本申请实施例的描述中，技术术语“第一”“第二”等仅用于区别不同对象，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量、特定顺序或主次关系。在本申请实施例的描述中，“多个”的含义是两个以上，除非另有明确具体的限定。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它 元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本申请教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本申请的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本申请的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本申请的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本申请的范围。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
在一些实施例中，请参阅图1，本申请一实施例的提供的横向绝缘栅双极晶体管包括漂移区120、第一阱区171、第一电极引出区130、第二电极引出区140以及电导调制结构160。
漂移区120具有第一导电类型，第一阱区171设于漂移区120的上表层，第一阱区171具有第二导电类型，第一导电类型和第二导电类型相反。
其中，第一导电类型和第二导电类型中的其中一种类型为P型，另一种类型为N型。例如，第一导电类型为N型，第二导电类型为P型；或者，第一导电类型为P型，第二导电类型为N型。
第一电极引出区130设于第一阱区171的上表层，第二电极引出区140设于漂移区120的上表层，电导调制结构160设于第一电极引出区130和第二电极引出区140之间的漂移区120内，电导调制结构160包括设于漂移区120的上表层且具有第一导电类型的第一掺杂区161，以及位于第一掺杂区161内且具有第二导电类型的第二掺杂区162，第一掺杂区161的掺杂浓度大于漂移区120的掺杂浓度。其中，第一掺杂区161具有第一导电类型，第二掺杂区162具有第二导电类型，因此第一掺杂区161和第二掺杂区162之间可以形成PN结。
示例性的，在本实施例中，第一导电类型为N型，第二导电类型为P型，即第一掺杂区161和漂移区120的导电类型为N型，第二掺杂区162的导电类型为P型。
上述横向绝缘栅双极晶体管，当横向绝缘栅双极晶体管开启时，横向绝缘栅双极晶体管的导电沟道打开，电子由第一电极引出区130通过该导电沟道进入漂移区120，随着电子数量越来越多，大量电子涌向第二电极引出区140，并在漂移区120内逐渐形成一个压降，此压降使得第一掺杂区161和第二掺杂区162之间形成的PN结正向导通，与第二电极引出区140一起向漂移区120注入大量空穴，形成电导调制效应，极大地降低了横向绝缘栅双极晶体管的通态压降，且降低了横向绝缘栅双极晶体管的静态功耗。而在横向绝缘栅双极晶体管关闭时，第一掺杂区161和第二掺杂区162之间形成类似超结的结构，可以相互辅助耗尽，使得电场不至于提前击穿，不影响提高横向绝缘栅双极晶体管的耐压。即，在降低了器件静态功耗的同时有效避免击穿电压的显著降低。
在本实施例中，第一掺杂区161的掺杂浓度大于漂移区120的掺杂浓度，可提高漂移区120的掺杂浓度，并降低导通电阻。如此，在横向绝缘栅双极晶体管开启时，横向绝缘栅双极晶体管的导电沟道打开，电子由第一电极引出区130通过该导电沟道进入漂移区120，因第一掺杂区161的掺杂浓度大于漂移区120的掺杂浓度，可使漂移区120对电子的阻力更小，以便越来越多的电子涌第二电极引出区140，并更快地在漂移区120形成一个使第一掺杂区161和第二掺杂区162之间形成的PN结正向导通的压降，PN结正向导通后，能与第二电极引出区140一起向漂移区120注入大量空穴，形成电导调制效应，极大地降低了横向绝缘栅双极晶体管的通态压降，且降低了横向绝缘栅双极晶体管的静态功耗。
需要说明的是，若第一掺杂区161的掺杂浓度过高，第一掺杂区161和第二掺杂区162之间形成的寄生PN二极管正偏后涌过来的空穴会被第一掺杂区161复合。从关断状态下 击穿电压的角度来看，若第一掺杂区161和第二掺杂区162的掺杂浓度过高，会导致横向绝缘栅双极晶体管在静态关断时第一掺杂区161和第二掺杂区162之间形成的寄生PN二极管引入新的电场，导致器件提前击穿。基于此，第一掺杂区161和第二掺杂区162的掺杂浓度和体积需要根据漂移区120的掺杂浓度和器件的需求进行合理的设置，在能兼顾满足横向绝缘栅双极晶体管的通态压降、耐压等需求的情况下，第一掺杂区161的掺杂浓度和体积越大越好。
在一些实施例中，请参阅图1-图3，第一掺杂区161和第二掺杂区162的数量均为至少一个。
第一掺杂区161和第二掺杂区162的数量可以为一个，也可以为多个。也可以是，一个第一掺杂区161内设有多个独立的第二掺杂区162，该第一掺杂区161大致呈薄层结构。也可以是，多条沿导电沟道的长度方向延伸的第一掺杂区161，每条第一掺杂区161内设有多个独立的第二掺杂区162。当然，也可以是，多条沿导电沟道的宽度方向延伸的第一掺杂区161，每条第一掺杂区161内设有多个独立的第二掺杂区162。在此不作具体限制。电导调制结构160的数量需要根据漂移区120的掺杂浓度和器件的需求进行合理的设置，以能兼顾满足横向绝缘栅双极晶体管的通态压降和耐压等需求。也可以理解为，本申请的电导调制结构160的设置方式均能确保漂移区120中增设的第一掺杂区161和第二掺杂区162在静态时零偏，这时候类似于超结相互耗尽，同时又能要保证第一掺杂区161残余的浓度与面积不至于影响到漂移区的耗尽区，避免增设过多的第一掺杂区161不能被第二掺杂区162耗尽造成漂移区的耗尽区收缩，避免影响器件的击穿电压。图3给出了一个第一掺杂区161和一个第二掺杂区162的示例。
可以理解，该电导调制结构160能使漂移区120形成空穴注入的低阻路径，形成显著的电导调制效应，极大地降低了横向绝缘栅双极晶体管的通态压降，且能有效降低横向绝缘栅双极晶体管的静态功耗。
在一些实施例中，第一掺杂区161和第二掺杂区162均浮空设置。
在另一些实施例中，第一掺杂区161浮空设置，第二掺杂区162外接电位。
在一些实施例中，第一掺杂区161的掺杂深度小于第一阱区171的掺杂深度。
在一些实施例中，第一掺杂区161和第二掺杂区162的掺杂浓度值的数量级相同，能很好地兼顾满足横向绝缘栅双极晶体管的通态压降、耐压等需求。
在一些实施例中，请参阅图1及图2，漂移区120的上表层设有至少一组电导调制结构组件，各电导调制结构组件包括沿导电沟道的长度方向间隔布设的多个电导调制结构160。
该横向绝缘栅双极晶体管开启时，横向绝缘栅双极晶体管的导电沟道打开，可以理解的是，该导电沟道形成于第一阱区171，如此，电子由第一电极引出区130通过该导电沟道进入漂移区120并涌向第二电极引出区140的过程中，随着越来越多的电子涌向第二电极引 出区140，可在漂移区120形成使各电导调制结构160中第一掺杂区161和第二掺杂区162之间形成的PN结正向导通的压降，如此，多个PN结能与第二电极引出区140一起向漂移区120注入大量空穴，形成显著的电导调制效应，极大地降低了横向绝缘栅双极晶体管的通态压降，能有效降低横向绝缘栅双极晶体管的静态功耗，还能避免提前击穿，不影响器件的耐压，击穿电压不会显著降低。而在横向绝缘栅双极晶体管关闭时，第一掺杂区和第二掺杂区之间形成类似超结的结构，可以相互辅助耗尽，使得电场不至于提前击穿，不影响提高横向绝缘栅双极晶体管的耐压。即，在降低了器件静态功耗的同时有效避免击穿电压的显著降低。
需要说明的是，多个电导调制结构160未连成一片，可以给漂移区120留出足够的载流子运动路径。
在一些实施例中，导电沟道的长度方向平行于x轴向。
在一些实施例中，请参阅图2，漂移区120的上表层设有沿导电沟道的宽度方向间隔布设的多组电导调制结构组件。
在一些实施例中，导电沟道的宽度方向平行于y轴向。
该横向绝缘栅双极晶体管开启时，横向绝缘栅双极晶体管的导电沟道打开，随着越来越多的电子由第一电极引出区130通过该导电沟道涌向第二电极引出区140，可在漂移区120形成使各电导调制结构160中第一掺杂区161和第二掺杂区162之间形成的PN结正向导通的压降，如此，多组电导调制结构组件中的电导调制结构160均能使漂移区120形成空穴注入的低阻路径，形成显著的电导调制效应，极大地降低了横向绝缘栅双极晶体管的通态压降，且能有效降低横向绝缘栅双极晶体管的静态功耗。
在一些实施例中，横向绝缘栅双极晶体管还包括设于漂移区120的上表层且具有第一导电类型的第二阱区180，第二阱区180位于全部电导调制结构160远离第一阱区171的一侧，第二阱区180的上表层设有第二电极引出区140，第二电极引出区140具有第二导电类型，第一电极引出区130具有第一导电类型。也可以理解为，全部电导调制结构160均位于第一阱区171与第二阱区180之间的漂移区120中。
当横向绝缘栅双极晶体管进入关断过程时，漂移区120中在导通状态产生电导调制效应所存储的载流子可以很快地通过第一导电类型的第二阱区180流向漏极，有效缩短了关断时间。同时当横向绝缘栅双极晶体管处于开态时，第二电极引出区140和第二阱区180之间形成的PN结反向偏置，可有效防止第二电极引出区140击穿，提高横向绝缘栅双极晶体管的耐压能力。
在一些实施例中，第一阱区171的上表层还设有具有第二导电类型的第一阱区引出区172，第一阱区引出区172与第一电极引出区130的电位短接在一起。
可以理解的是，第一电极引出区130、第一阱区引出区172和漂移区120共同构成一个寄生NPN三极管，若未设置第一阱区171，当横向绝缘栅双极晶体管导通且满足寄生NPN 三极管的基极少子可以渡越的条件后，可能会使得此寄生NPN三极管开启，这样会使得横向绝缘栅双极晶体管在开启阶段发生失效。反之，在第二导电类型的第一阱区引出区172下方加一个第二导电类型的第一阱区171，可以提高该寄生NPN管的基区浓度，少子寿命减小而无法渡越到发射极，这样就有效地避免了源端处寄生NPN管开启。增设第一阱区171相当于使第一阱区引出区172和第一阱区171形成缓变沟道掺杂，可调整阈值电压，减小衬底111电阻，防止寄生NPN管导通，并可提高第一阱区171的浓度，缩短沟道长度，降低导通电阻并减小器件面积。
在一些实施例中，横向绝缘栅双极晶体管还包括半导体基底110，半导体基底110包括层叠设置的衬底111和掩埋介质层112，漂移区120设于掩埋介质层112背离衬底111的一侧，衬底111具有第二导电类型。
若未设置掩埋介质层112，第二电极引出区140、漂移区120和衬底111共同构成一个PNP三极管，如此，当横向绝缘栅双极晶体管开启时，非常容易使得这个PNP三极管开启而导致漏端电流经由这个PNP三极管流向衬底111而导致失效。因此在衬底111和漂移区120设置掩埋介质层112，通过掩埋介质层112实现漂移区120与衬底111之间的电隔离，避免形成该PNP三极管，也能有效避免漏电，使横向绝缘栅双极晶体管具备低漏电、低开态电阻及抗闩锁能力等优点。
在一些实施例中，横向绝缘栅双极晶体管还包括栅极结构，栅极结构150位于第一阱区171上，栅极结构150的一侧延伸覆盖至第一电极引出区130的一部分，栅极结构150的另一侧延伸覆盖至漂移区120的一部分。
在一些实施例中，在漂移区120上表面还设有场氧化层151，栅极结构150还延伸覆盖至场氧化层151的一部分，延伸覆盖至场氧化层151上的栅极导电层作为场板。
在一些实施例中，栅极结构150包括栅介质层和栅极导电层(栅介质层在本申请图1、图2、图3中均未示出)，栅介质层设于第一阱区171上，且一端延伸覆盖至第一电极引出区130的一部分，另一端延伸覆盖至未被场氧化层151覆盖的漂移区120上，并与场氧化层151接触。栅极导电层形成于栅介质层上，栅极导电层远离第一电极引出区130的一侧还延伸覆盖至场氧化层151的一部分。
可以理解的是，栅极结构150设置在部分的第一阱区171上，一方面在外加电压的控制下，第一阱区171与栅极结构150有交叠的区域用于形成导电沟道；另一方面，在横向绝缘栅双极晶体管制备的过程中栅极结构150还可以作为第一电极引出区130的注入阻挡层，以使第一电极引出区130进行自对准注入，保证导电沟道的宽度。
栅极导电层的材料可以为多晶硅材料，也可为金属、金属氮化物、金属硅化物，在此不作具体限定。
栅介质层可以包括但不限于氧化硅层。形成栅介质层的方法可以为化学气相沉积工 艺、物理气相沉积工艺、原子层沉积工艺或原位水汽生成工艺(In-Situ Steam Generation，ISSG)，在此不作具体限定。
在一些实施例中，全部电导调制结构160在漂移区120上的正投影，与栅极导电层在漂移区120上的正投影具有沿横向的间隔。即电导调制结构160不设于栅极导电层下方，而设于栅极导电层与第二阱区180之间。避免栅极导电层的栅电压对电导调制结构160产生影响，以更好地利用电导调制结构160降低横向绝缘栅双极晶体管的通态压降。
本申请相应提供一种横向绝缘栅双极晶体管的制备方法，可以用于制造前述任一实施例的横向绝缘栅双极晶体管。图4是一实施例中横向绝缘栅双极晶体管的制备方法的流程图，包括下列步骤：
S210、提供半导体基底，半导体基底包括衬底，衬底具有第二导电类型。
S220、在半导体基底上形成位于衬底上方的漂移区，漂移区具有第一导电类型，第一导电类型和第二导电类型相反。
S230、在漂移区的上表层形成具有第二导电类型的第一阱区。
S240、在漂移区内形成与第一阱区间隔设置的电导调制结构，电导调制结构包括形成于漂移区的上表层且具有第一导电类型的第一掺杂区，以及形成于第一掺杂区内且具有第二导电类型的第二掺杂区，第一掺杂区的掺杂浓度大于漂移区的掺杂浓度。
S250、形成第一电极引出区和第二电极引出区，第一电极引出区形成于第一阱区的上表层，第二电极引出区形成于全部电导调制结构远离第一阱区的一侧。
该横向绝缘栅双极晶体管的制备方法制得的横向绝缘栅双极晶体管，当横向绝缘栅双极晶体管开启时，横向绝缘栅双极晶体管的导电沟道打开，电子由第一电极引出区通过该导电沟道进入漂移区，随着电子数量越来越多，大量电子涌向第二电极引出区，并在漂移区逐渐形成一个压降，此压降使得第一掺杂区和第二掺杂区之间形成的PN结正向导通，与第二电极引出区一起向漂移区注入大量空穴，形成电导调制效应，极大地降低了横向绝缘栅双极晶体管的通态压降，且降低了横向绝缘栅双极晶体管的静态功耗。而在横向绝缘栅双极晶体管关闭时，第一掺杂区和第二掺杂区之间形成类似超结的结构，可以相互辅助耗尽，使得电场不至于提前击穿，不影响提高横向绝缘栅双极晶体管的耐压。即，在降低了器件静态功耗的同时有效避免击穿电压的显著降低。
在一些实施例中，其中，半导体基底包括层叠设置的衬底和掩埋介质层，第二导电类型为P型，第一导电类型为N型，相应地，衬底为P型硅衬底，漂移区为N-漂移区。在其他的实施例中，也可以是第二导电类型为N型、第一导电类型为P型。
在一些实施例中，掩埋介质层的材质为硅的氧化物，例如二氧化硅。
在一些实施例中，漂移区通过注入后高温推阱实现，需要一定的掺杂浓度来保证电流通路。
在一些实施例中，步骤S230中，在漂移区的上表层形成具有第二导电类型的第一阱区的同时还在漂移区的上表层形成具有第一导电类型的第二阱区，且第二阱区与第一阱区间隔设置；则在步骤S240中，电导调制结构形成于第一阱区与第二阱区之间的漂移区中；则在步骤S250中，第二电极引出区形成于第二阱区的上表层，第二电极引出区具有第二导电类型，第一电极引出区具有第一导电类型。当横向绝缘栅双极晶体管进入关断过程时，漂移区中在导通状态产生电导调制效应所存储的载流子可以很快地通过第一导电类型的第二阱区流向漏极，有效缩短了关断时间。同时当横向绝缘栅双极晶体管处于开态时，第二电极引出区和第二阱区之间形成的PN结反向偏置，可有效防止第二电极引出区击穿，提高横向绝缘栅双极晶体管的耐压能力。
在一些实施例中，步骤S240中在漂移区内形成与第一阱区间隔设置的电导调制结构，包括：向漂移区的部分上表层注入第一导电类型离子，并推阱形成第一掺杂区；向第一掺杂区内注入第二导电类型离子，并推阱形成第二掺杂区，第二导电类型的第二掺杂区被第一导电类型的第一掺杂区包住，使得第一掺杂区和第二掺杂区之间可以形成PN结。
在一些实施例中，步骤S240之后，且在步骤S250之前，还包括：
S2401、在部分漂移区上形成场氧化层；
S2402、在部分第一阱区上形成栅介质层，栅介质层还延伸覆盖至未被场氧化层覆盖的漂移区上，并与场氧化层接触；
S2403、在栅介质层上形成栅极导电层，栅极导电层还延伸覆盖至场氧化层的一部分；则在步骤S250中，栅极结构作为第一电极引出区的注入阻挡层，以进行自对准注入，第一电极引出区形成于第一阱区的上表层，且第一电极引出区的一部分延伸至栅极结构下，保证导电沟道的宽度。
在一些实施例中，步骤S250，包括：先形成第一电极引出区；后形成第二电极引出区，且形成第二电极引出区的同时还形成第一阱区引出区，第一阱区引出区形成于第一阱区的上表层，第一阱区引出区和第二电极引出区均具有第二导电类型，第一电极引出区具有第一导电类型，电导调制结构形成于第一阱区与第二电极引出区之间的漂移区中，也可以理解为电导调制结构形成于第一电极引出区与第二电极引出区之间的漂移区中。
应该理解的是，虽然上述实施例中的流程图中的各个步骤按照箭头的提示依次显示，但是这些步骤并不是必然按照箭头提示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，上述流程图中的至少一部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些子步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤的子步骤或者阶段的至少一部分轮流或者交替地执行。需要说明的是，上述不同的实施例之间可以进行相互组合。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种横向绝缘栅双极晶体管，其中，横向绝缘栅双极晶体管包括：
    漂移区，具有第一导电类型；
    第一阱区，设于所述漂移区的上表层，具有第二导电类型，所述第一导电类型和所述第二导电类型相反；
    第一电极引出区和第二电极引出区，所述第一电极引出区设于所述第一阱区的上表层，所述第二电极引出区设于所述漂移区的上表层；
    电导调制结构，设于所述第一电极引出区和所述第二电极引出区之间的所述漂移区内，所述电导调制结构包括设于所述漂移区的上表层且具有第一导电类型的第一掺杂区，以及设于所述第一掺杂区内且具有第二导电类型的第二掺杂区，所述第一掺杂区的掺杂浓度大于所述漂移区的掺杂浓度。
  2. 根据权利要求1所述的横向绝缘栅双极晶体管，其中，所述第一掺杂区和所述第二掺杂区的数量均为至少一个。
  3. 根据权利要求1所述的横向绝缘栅双极晶体管，其中，所述第一掺杂区和所述第二掺杂区均浮空设置；或，
    所述第一掺杂区浮空设置，所述第二掺杂区外接电位。
  4. 根据权利要求1所述的横向绝缘栅双极晶体管，其中，所述第一掺杂区的掺杂深度小于所述第一阱区的掺杂深度。
  5. 根据权利要求1所述的横向绝缘栅双极晶体管，其中，所述第一掺杂区和所述第二掺杂区的掺杂浓度值的数量级相同。
  6. 根据权利要求1-5任一项所述的横向绝缘栅双极晶体管，其中，所述漂移区的上表层设有至少一组电导调制结构组件，每一所述电导调制结构组件包括沿导电沟道的长度方向间隔布设的多个所述电导调制结构。
  7. 根据权利要求6所述的横向绝缘栅双极晶体管，其中，所述漂移区的上表层设有沿导电沟道的宽度方向间隔布设的多组所述电导调制结构组件。
  8. 根据权利要求1所述的横向绝缘栅双极晶体管，其中，所述横向绝缘栅双极晶体管还包括设于所述漂移区的上表层且具有第一导电类型的第二阱区，所述第二阱区位于全部所述电导调制结构远离所述第一阱区的一侧；
    所述第二阱区的上表层设有所述第二电极引出区，所述第二电极引出区具有所述第二导电类型，所述第一电极引出区具有所述第一导电类型。
  9. 根据权利要求1所述的横向绝缘栅双极晶体管，其中，所述第一阱区的上表层还设有 具有第二导电类型的第一阱区引出区，所述第一阱区引出区与所述第一电极引出区的电位短接在一起。
  10. 根据权利要求1所述的横向绝缘栅双极晶体管，其中，所述横向绝缘栅双极晶体管还包括半导体基底，所述半导体基底包括层叠设置的衬底和掩埋介质层，所述漂移区设于所述掩埋介质层背离所述衬底的一侧。
  11. 根据权利要求1所述的横向绝缘栅双极晶体管，其中，所述横向绝缘栅双极晶体管还包括栅极结构，所述栅极结构位于所述第一阱区上，所述栅极结构的一侧延伸覆盖至所述第一电极引出区的一部分，所述栅极结构的另一侧延伸覆盖至所述漂移区的一部分。
  12. 根据权利要求11所述的横向绝缘栅双极晶体管，其中，在所述漂移区上表面还设有场氧化层，所述栅极结构包括栅介质层和栅极导电层，所述栅介质层设于所述第一阱区上，且一端延伸覆盖至所述第一电极引出区的一部分，另一端延伸覆盖至未被所述场氧化层覆盖的所述漂移区上，并与所述场氧化层接触；
    所述栅极导电层形成于所述栅介质层上，所述栅极导电层远离所述第一电极引出区的一侧还延伸覆盖至所述场氧化层的一部分。
  13. 根据权利要求12所述的横向绝缘栅双极晶体管，其中，全部所述电导调制结构在所述漂移区上的正投影，与所述栅极导电层在所述漂移区上的正投影之间沿横向间隔设置。
  14. 一种横向绝缘栅双极晶体管的制备方法，其中，横向绝缘栅双极晶体管的制备方法包括：
    提供半导体基底，所述半导体基底包括衬底，所述衬底具有第二导电类型；
    在所述半导体基底上形成位于所述衬底上方的漂移区，所述漂移区具有第一导电类型，所述第一导电类型和所述第二导电类型相反；
    在所述漂移区的上表层形成具有第二导电类型的第一阱区；
    在所述漂移区内形成与所述第一阱区间隔设置的电导调制结构，所述电导调制结构包括形成于所述漂移区的上表层且具有第一导电类型的第一掺杂区，以及形成于所述第一掺杂区内且具有第二导电类型的第二掺杂区，所述第一掺杂区的掺杂浓度大于所述漂移区的掺杂浓度；
    形成第一电极引出区和第二电极引出区，所述第一电极引出区形成于所述第一阱区的上表层，所述第二电极引出区形成于全部所述电导调制结构远离所述第一阱区的一侧。
  15. 根据权利要求14所述的横向绝缘栅双极晶体管的制备方法，其中，所述在所述漂移区内形成与所述第一阱区间隔设置的电导调制结构，包括：
    向所述漂移区的部分上表层注入第一导电类型离子，并推阱形成所述第一掺杂区；
    向所述第一掺杂区内注入第二导电类型离子，并推阱形成所述第二掺杂区。
PCT/CN2023/106736 2022-07-12 2023-07-11 横向绝缘栅双极晶体管及其制备方法 Ceased WO2024012437A1 (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118571762A (zh) * 2024-08-01 2024-08-30 杭州积海半导体有限公司 Ldmos器件的形成方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180012980A1 (en) * 2015-02-02 2018-01-11 Csmc Technologies Fab2 Co., Ltd. Lateral insulated gate bipolar transistor
CN110190113A (zh) * 2019-05-16 2019-08-30 东南大学 一种消除负阻效应的阳极短路型横向绝缘栅双极型晶体管
CN113690309A (zh) * 2021-07-14 2021-11-23 广东美的白色家电技术创新中心有限公司 Ligbt、制备方法、智能功率模块、驱动电路及电器
CN113745309A (zh) * 2020-05-27 2021-12-03 成都蓉矽半导体有限公司 一种具有渐变浓度掺杂层的横向双扩散碳化硅场效应晶体管

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2581233B2 (ja) * 1989-11-06 1997-02-12 富士電機株式会社 横型伝導度変調ｍｏｓｆｅｔ
US7473976B2 (en) * 2006-02-16 2009-01-06 Fairchild Semiconductor Corporation Lateral power transistor with self-biasing electrodes
US7605446B2 (en) * 2006-07-14 2009-10-20 Cambridge Semiconductor Limited Bipolar high voltage/power semiconductor device having first and second insulated gated and method of operation
CN102723354A (zh) * 2011-03-30 2012-10-10 无锡华润上华半导体有限公司 高压功率ldmos器件及其制造方法
CN111969049B (zh) * 2020-08-28 2022-08-23 电子科技大学 一种soi横向绝缘栅双极晶体管

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180012980A1 (en) * 2015-02-02 2018-01-11 Csmc Technologies Fab2 Co., Ltd. Lateral insulated gate bipolar transistor
CN110190113A (zh) * 2019-05-16 2019-08-30 东南大学 一种消除负阻效应的阳极短路型横向绝缘栅双极型晶体管
CN113745309A (zh) * 2020-05-27 2021-12-03 成都蓉矽半导体有限公司 一种具有渐变浓度掺杂层的横向双扩散碳化硅场效应晶体管
CN113690309A (zh) * 2021-07-14 2021-11-23 广东美的白色家电技术创新中心有限公司 Ligbt、制备方法、智能功率模块、驱动电路及电器

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118571762A (zh) * 2024-08-01 2024-08-30 杭州积海半导体有限公司 Ldmos器件的形成方法

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