WO2022252654A1 - 逆导型横向绝缘栅双极型晶体管 - Google Patents

逆导型横向绝缘栅双极型晶体管 Download PDF

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WO2022252654A1
WO2022252654A1 PCT/CN2022/073350 CN2022073350W WO2022252654A1 WO 2022252654 A1 WO2022252654 A1 WO 2022252654A1 CN 2022073350 W CN2022073350 W CN 2022073350W WO 2022252654 A1 WO2022252654 A1 WO 2022252654A1
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region
well
well region
bipolar transistor
gate bipolar
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PCT/CN2022/073350
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English (en)
French (fr)
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张森
顾炎
陈思宇
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无锡华润上华科技有限公司
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Priority to JP2023567960A priority Critical patent/JP2024516286A/ja
Publication of WO2022252654A1 publication Critical patent/WO2022252654A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]

Definitions

  • the present application relates to the technical field of semiconductor devices, in particular to a reverse conduction lateral insulated gate bipolar transistor.
  • Lateral Insulated-Gate Bipolar Transistor is a transistor that combines the advantages of MOS transistors and bipolar transistors.
  • Silicon on Insulator (SOI) technology is widely used in the manufacture of power integrated circuits due to its ideal dielectric isolation performance.
  • SOI-LIGBT device is a LIGBT device manufactured based on SOI technology.
  • Intelligent power modules are widely used in motor drives and motor drives. Under medium power conditions, fully integrated SOI-LIGBTs are often used as their power switching devices, and LIGBT parallel high-voltage freewheeling diodes (FWD) are the most Classic switching device structure.
  • FWD parallel high-voltage freewheeling diodes
  • the patent document CN111816699A proposes an adaptive SOI LIGBT device, which mainly integrates a Zener diode, because the Zener diode will adaptively reverse breakdown and conduction with the increase of the collector voltage.
  • the collector structure is a collector NMOS structure
  • the N-type buffer layer also has The second P-type well region, P+ well potential region, N+ collector region and collector groove gate; the P+ potential region and the P+ well potential region are short-circuited, so that the potential difference between the collector electrode and the P+ well potential region is also small, which cannot be achieved in the second P-type well region.
  • the inversion layer is formed in the P well region, which leads to the blocking of the conductive path between the N+ collector region and the N-type buffer layer, and the device cannot enter the unipolar conduction mode, thereby eliminating the snap-back effect when the device is conducting forward.
  • the structure of this patent document introduces a Zener diode.
  • the Zener diode generally has a Zener-type tunnel breakdown, when it is used as a freewheeling diode in a reverse-conducting LIGBT, it is used in the reverse breakdown It will be relatively limited under high voltage or ultra-high voltage conditions; and, although the Zener diode in this patent document has a certain effect in suppressing the snap-back effect of forward conduction, it cannot achieve faster recovery characteristics, due to its The setting of the collector structure, the turn-off rate of the switch in the reverse recovery stage of LIGBT still needs to be improved.
  • a reverse conduction lateral IGBT is provided.
  • a reverse conduction lateral insulated gate bipolar transistor comprising: a drift region formed on a substrate, a gate located on the drift region, an emitter located on the drift region and close to the gate side a pole region, and a collector region located on the drift region and away from the gate side;
  • Two or more N well regions arranged at intervals are provided on the side where the collector region of the drift region is located;
  • a P well region is provided between two or more N well regions arranged at intervals;
  • a P+ contact region is arranged on the N well region
  • An N+ contact region is arranged on the P well region
  • Both the P+ contact area and the N+ contact area are conductively connected to the collector terminal.
  • the two or more N well regions arranged at intervals at least include a first N well region and a second N well region; the P well region at least includes The first P well region between the second N well regions; the areas of the first N well region and the second N well region are equal, and the first N well region and the second N well region regions are distributed symmetrically with respect to the first P-well region.
  • the periphery of the N+ contact region is covered by the P well region.
  • the N+ contact region includes a first portion and a second portion; the first portion includes a sidewall portion and a bottom portion, and the sidewall portion extends in a direction perpendicular to the plane where the substrate is located , the bottom part is connected to the side wall part on a side close to the substrate; the second part is connected to the side wall part on a side away from the substrate; the depth of the side wall part is greater than that of the first part The depth of the second part.
  • the depth of the sidewall portion is greater than the depth of the P+ contact region.
  • a trench is formed in the P-well region; the sidewall portion and the bottom of the first portion are respectively doped by doping the side surface and the bottom surface of the trench And formed.
  • a filling structure is formed in the trench; the second portion is located on the filling structure.
  • the material of the filling structure includes insulating material and/or polysilicon.
  • the number of the P well regions is multiple, and the multiple N+ contact regions are located in the multiple P well regions respectively; the multiple N+ contact regions are parallel to the P+ contact regions. staggered distribution on the plane where the substrate is located.
  • more than two N well regions arranged at intervals and a plurality of P well regions are alternately distributed on a plane parallel to the substrate.
  • FIG. 1 is a schematic cross-sectional view of a common lateral insulated gate bipolar transistor
  • FIG. 2 is a schematic cross-sectional view of a reverse conduction lateral IGBT transistor provided in a related embodiment
  • FIG. 3 is a schematic cross-sectional view of a reverse conduction lateral IGBT transistor provided in the first embodiment
  • FIG. 4 is a schematic cross-sectional view of a reverse conduction lateral IGBT transistor provided in the second embodiment
  • 5a-5c are schematic top views of the collector region of the reverse conduction lateral IGBT in an alternative embodiment.
  • FIG. 1 is a schematic cross-sectional view of a common lateral insulated gate bipolar transistor.
  • the lateral insulated gate bipolar transistor includes: an SOI substrate (including a bottom silicon layer 100, a buried oxide layer 110 and a top silicon layer 120), located in the drift region 121 of the top silicon layer 120, the field oxide layer 130, the gate 140, the polysilicon field plate 150 at the collector, the emitter region on the drift region 121 and close to the gate side, and the drift region 121 and away from the collector region on the side of the gate.
  • the emitter region is provided with a channel region 161, and the channel region 161 is specifically a P well region, which is used as a conduction channel of a lateral MOS in LIGBT; a substrate ohmic contact region 171 and a source
  • the pole ohmic contact region 172, and the substrate ohmic contact region 171 and the source ohmic contact region 172 are all conductively connected to the emitter terminal.
  • the collector region is provided with an N-type buffer zone (hereinafter referred to as the N-well region 162), and the P+ contact region 173 is arranged on the N-well region 162; both the P+ contact region 173 and the polysilicon field plate 150 are conductively connected to the collector terminal.
  • the LIGBT needs to be connected in parallel with the FWD; when the LIGBT is forward-conducting, hole injection forms a large current conduction, driving the inductive load to work normally; when the LIGBT is turned off, the inductive load needs a loop because the current cannot change suddenly. At this time, the FWD connected in parallel will play the role of continuous flow. When the gate of LIGBT is turned on in the next stage, the FWD will return to the cut-off state after reverse recovery, and a working cycle ends.
  • LIGBT and FWD are two different types of devices, a high degree of matching is required to ensure normal switching characteristics during operation. Therefore, how to integrate independent FWD and LIGBT has become an important research direction in this field.
  • the present application firstly proposes a A related embodiment, the related embodiment provides a reverse conduction lateral insulated gate bipolar transistor, by improving the structure of the collector of the LIGBT, the switching characteristics of the LIGBT are improved. Please refer to FIG. 2 for details.
  • an N+ contact region 174 is also provided in the N well region 162, that is, an N+ contact region is added in the collector region.
  • the lower end of the N+ contact region 174 is surrounded by the P well region 163 . Therefore, when the LIGBT is normally turned on, the holes in the P+ contact region 173 are injected into the N well region 162 and the drift region 121 to generate a conductance modulation effect, and the current rises sharply after triggering the PNP transistor, and the LIGBT enters forward conduction work. At this time The N+ contact region 174 and the P well region 163 are in a reverse bias state, and electrons cannot pass through the depletion layer to form an LDMOS, so the normal turn-on operation is not affected when the forward LIGBT is turned on. When the LIGBT is reversely turned off, the collector of the LIGBT loses the voltage and becomes zero potential.
  • the inductive load current driven cannot change suddenly and flows in through the P+ of the emitter (please refer to the substrate ohmic contact area 171 in FIG. 2 ),
  • the N+ contact region 174 in the structure provided by this related embodiment there is a current path that can pass back to the coil during freewheeling, so there is no need to additionally connect FWD in parallel for freewheeling , the layout area can be greatly saved when the module is working, and the reliability of LIGBT is also improved.
  • the P+ contact region 173, the N+ contact region 174 and the P well region 163 are all arranged on the same N well region 162, and the minority carrier holes need to be transported during the LIGBT reverse recovery.
  • the reverse conduction lateral insulated gate bipolar transistor includes: a drift region formed on the substrate, a gate located on the drift region, and a gate located on the drift region and close to the gate. an emitter region, and a collector region on the side of the drift region away from the gate; where,
  • Two or more N well regions arranged at intervals are arranged on the side where the collector region of the drift region is located;
  • a P well region is provided between two or more N well regions arranged at intervals;
  • a P+ contact region is provided on the N well region
  • An N+ contact region is provided on the P well region
  • Both the P+ contact area and the N+ contact area are conductively connected to the collector terminal.
  • the embodiments of the present application improve the structure of the LIGBT collector region, which not only makes the improved device structure unnecessary to additionally connect FWD in parallel for freewheeling, but also greatly saves the layout area when the module is working. Improve the reliability of LIGBT, and because of the spaced arrangement of N well regions, the P well region is set between the spaced N well regions, thereby further improving the switch turn-off rate of LIGBT in the reverse recovery stage, and improving the overall device switching characteristics.
  • FIG. 3 is a schematic cross-sectional view of a reverse conduction lateral insulated gate bipolar transistor provided in the first embodiment of the present application; as shown in the figure, the reverse conduction lateral insulated gate bipolar transistor includes: Silicon layer 100 , buried oxide layer 110 and top silicon layer 120 .
  • the bottom silicon layer 100 has a first conductivity type, specifically, for example, the P type, that is, the bottom silicon layer 100 is a P-type substrate (Psub).
  • Psub P-type substrate
  • Its material is silicon; of course, the embodiment of the present application is not limited thereto, materials commonly used in this field, such as silicon carbide, gallium arsenide, indium phosphide or silicon germanium, etc., can also be used as the SOI substrate in the embodiment of the present application material of the underlying substrate.
  • the buried oxide layer 110 is located on the bottom silicon layer 100 and its material is usually silicon oxide, such as silicon dioxide.
  • the buried oxide layer 110 is generally named (BOX) in terms of function, and is specifically an insulating layer, and its material may also be other insulating materials not limited to silicon dioxide.
  • the top silicon layer 120 is located on the buried oxide layer 110, specifically, it may be an epitaxial layer with the second conductivity type, which is used as a layer for fabricating devices.
  • the top silicon layer 120 acts as a drift region (indicated by drift region 121 in the figure) in the LIGBT device.
  • the second conductivity type may be N-type, as a drift region, having a conductivity type opposite to that of the bottom silicon layer 100 .
  • the drift region 121 is specifically an N-region.
  • the material of the top silicon layer 120 is silicon; of course, the embodiment of the present application is not limited thereto, materials commonly used in this field, such as silicon carbide, gallium arsenide, indium phosphide or silicon germanium, etc., can also be used as the embodiment of the present application
  • the top substrate material of the SOI substrate can also be used as the embodiment of the present application.
  • the field oxide layer 130 is formed on the drift region 121, and the material of the field oxide layer 130 may be silicon oxide, such as silicon dioxide.
  • the field oxide layer 130 is the field region of the LIGBT, serving as the lateral isolation of the device.
  • a gate 140 is formed on the field oxide layer 130, and the material of the gate 140 is, for example, polysilicon, and serves as a gate of the LIGBT.
  • a polysilicon field plate 150 at the collector which acts as a polysilicon field plate at the collector of the LIGBT.
  • Both the channel region 161 and the N well region 162 are located on the drift region 121 , and they are arranged at intervals along the first direction in the figure.
  • the channel region 161 is located on a side close to the gate 140 ; the channel region 161 has a first conductivity type, specifically, for example, a P-well.
  • the channel region 161 forms a conduction channel of the lateral MOS.
  • the N well region 162 is located on a side away from the gate 140 .
  • the N well region 162 is in the collector region of the LIGBT and serves as an N-type buffer layer of the LIGBT to prevent punch through.
  • a substrate ohmic contact region 171 having a first conductivity type and a source ohmic contact region 172 having a second conductivity type are disposed in the channel region 161 .
  • the substrate ohmic contact region 171 is specifically a P+ type region, which is drawn out as the substrate.
  • the source ohmic contact region 172 is specifically an N+ type region, serving as a source ohmic contact of the MOS.
  • the source ohmic contact region 172 is in contact with the channel region 161 on a side facing the gate 140 to induce a channel in the channel region 161 .
  • the N-well region acts as a buffer for the LIGBT.
  • the buffer area is divided into two or more N-well regions arranged at intervals, so as to independently become a LIGBT unit.
  • a P+ contact region 173 is provided on the N well region, and the P+ contact region 173 can also be called a collector ohmic contact region, which serves as a collector ohmic contact of LIGBT and provides electrode extraction.
  • each N well region can be provided with an independent P+ contact region; each P+ contact region can be located in each corresponding N well region as shown in Figure 3, and the sides and bottom of the P+ contact region are covered by the N well region. Covering; each P+ contact region can also be located on each corresponding N well region, and only the bottom is covered by the N well region.
  • a P well region 163 is provided between two or more N well regions arranged at intervals (for example, between the first N well region 1621 and the second N well region 1622 );
  • An N+ contact region 174 is provided on the P well region 163; the N+ contact region 174 is used as the N+ lead of the collector terminal of the LIGBT, and is the cathode of a diode generated during reverse conduction.
  • both the P+ contact region 173 and the N+ contact region 174 are electrically connected to the collector terminal.
  • the direction perpendicular to the plane where the substrate is located is defined as the third direction, that is, the stacking direction of each layer structure.
  • Two first and second directions perpendicular to each other are defined on a plane parallel to the substrate.
  • the entire N well region 162 in the related embodiment is separated and becomes several independent ones (Fig. type N-well region), so that not only no additional parallel FWD is needed for freewheeling, but also the turn-off rate of the switch during the LIGBT reverse recovery stage can be improved.
  • the N+ contact region 174 (specifically, for example, a part other than the upper surface) is in direct contact with at least a part of the P well region 163; a PN junction is formed between the two, and is specifically P/N+. At least a part of the P well region 163 (at least including the part where the lower surface is located) is in direct contact with the drift region 121; a PN junction is formed between the two, and is specifically P/N-.
  • the potential barrier between the P well region 163 and the drift region 121 is obviously lower than the potential barrier between the P well region 163 and the N well region 162 in the related embodiment.
  • more than two N well regions arranged at intervals include at least the first N well region 1621 and the second N well region 1622 ; the P well region 163 includes at least the first N well region 1621 and the second N well region The first P well region between regions 1622 (because there is only one P well region in the section shown in FIG. 3 , so refer to the P well region 163 in the figure); The areas are equal, and the first N well region 1621 and the second N well region 1622 are distributed symmetrically with respect to the first P well region.
  • the areas of the first N well region and the second N well region are equal, and the first N well region and the second N well region are symmetrically distributed relative to the first P well region, when the device is conducting forward, The current can flow more evenly to each P+ contact area of the collector area, making the conduction characteristics of the device more stable; on the contrary, if the distribution is asymmetrical or non-uniform, it is easy to cause the device to advance before the PNP stage. When turned on, the entire device loses the conductance modulation effect and becomes an LDMOS. The same problem will also occur during reverse freewheeling.
  • the freewheeling characteristics of the reverse conduction type diode will decrease, the resistance will become larger and it will not be easy to recover quickly; while the first N well region and the second N well region When the areas are equal and symmetrically distributed, the freewheeling characteristics are better and the recovery is faster.
  • the first N well region 1621 , the first P well region and the second N well region 1622 are sequentially arranged, for example, along the first direction. This first direction is also the direction from the emitter region to the collector region.
  • the first N-well region 1621 , the first P-well region and the second N-well region 1622 may be sequentially adjacent to save area.
  • the N+ contact region 174 Along the direction parallel to the plane where the substrate is located, the surroundings of the N+ contact region 174 are covered by the P well region 163 . It can be understood that after the P well region 163 covers the N+ contact region 174, there will be no snap-back phenomenon like common LIGBTs at the initial stage of LIGBT turn-on (that is, when the forward voltage reaches a certain level, the current increases and the voltage decreases instead. ), because the N+ contact region 174 does not participate in the work when the LIGBT is turned on in the forward direction. Part of the minority carriers will pass through the PN junction barrier formed by the N+ contact region 174 and the P well region 163 and recombine with the N+ contact region 174, thereby reducing LIGBT tailing and turn-off loss.
  • FIG. 4 is a schematic cross-sectional view of a reverse conduction lateral IGBT provided in the second embodiment.
  • the N+ contact region 174 includes a first portion 1742 and a second portion 1744;
  • the first portion 1742 includes a sidewall portion and a bottom portion, and the sidewall portion extends along a direction perpendicular to the plane where the substrate is located, The bottom is connected to the side wall on the side close to the substrate;
  • the second part 1744 is connected to the side wall on the side away from the substrate; the depth of the side wall is greater than the depth of the second part 1744 .
  • the bottom of the second part 1744 and the first part 1742 can be used as the horizontal N+ lead-out of the LIGBT collector terminal; and the side wall of the first part 1742 can be used as the longitudinal N+ lead-out of the LIGBT collector terminal; the above are generated during reverse conduction cathode of the diode.
  • This second embodiment further achieves the following beneficial effects: on the one hand, the contact area of N+ is increased in the collector region, i.e., the lateral N+ and the vertical N+, and then the upper surface of the N+ contact region is electrically contacted; because the N+ The contact area is large, so the role of N+ as a reverse diode can be maximized, which greatly enhances the reverse flow capability of the reverse conduction LIGBT; at the same time, when it is used as a diode for reverse recovery, the minority carrier holes move along the side wall The number is greater than the number moving along the upper surface, so the path of minority carrier movement is shorter, which can further improve the efficiency of hole recombination, increase the reverse recovery time trr, and reduce the peak current Irr during reverse recovery.
  • the area of the LIGBT collector region can also be greatly reduced, because the pitch (that is, the pitch) of the structure forming the first part 1742 (specifically, the trench structure) can be designed to be very small, and in the case of the same depth The area of N+ injection will not be reduced, so the overall area of LIGBT can be reduced by reducing the area of the collector region.
  • the above-mentioned first part 1742 can be formed by first forming a trench in the P well region 163, doping the side surface and the bottom surface of the trench; then, filling the trench, and forming The second portion 1744 described above is formed.
  • the doping is performed by, for example, ion implantation and other processes.
  • a trench is formed in the P-well region 163; the sidewall portion and the bottom of the first portion 1742 are formed by doping the side surface and the bottom surface of the trench, respectively.
  • the cross-sectional shape of the first portion 1742 may be similar to the shape of the groove formed, for example, U-shaped.
  • a filling structure 180 is formed in the trench; the second portion 1744 is located on the filling structure 180 .
  • the material of the filling structure 180 includes insulating material and/or polysilicon.
  • the material of the filling structure 180 includes an insulating material, such as silicon oxide; and polysilicon may be further filled on the insulating material, thereby forming the second portion 1744 in the polysilicon.
  • polysilicon can be directly filled in the trench, and the second portion 1744 is formed on the upper surface of the polysilicon.
  • At least a filling material is included.
  • the depth of the sidewall portion of the first portion 1742 is, for example, greater than the depth of the P+ contact region 173 .
  • 5a-5c are schematic top views of the collector region of the reverse conduction lateral IGBT in an alternative embodiment.
  • the number of the above-mentioned P well regions can be multiple, and the multiple N+ contact regions are respectively located in the multiple P well regions; the multiple N+ contact regions and the P+ contact regions are alternately distributed on a plane parallel to the substrate. .
  • the P+ contact region is not explicitly shown, it can be understood that there is a P+ contact region between two adjacent N+ contact regions no matter along the first direction or along the second direction. Further, there is a P+ contact region between two adjacent N+ contact regions, and there is an N+ contact region between two adjacent P+ contact regions.
  • FIG. 5 b shows a possible situation, that is, the P+ contact region is located between each N+ contact region, and specifically is located between each P well region.
  • the P+ contact regions are connected as a whole, and the P well regions and the N+ contact regions located in the corresponding P well regions are similarly distributed in the P+ contact regions in an island shape.
  • the staggered distribution structure is more suitable for high current density; high current LIGBT is prone to snap-back phenomenon in the emitter region, and N+
  • the staggered layout with P+ can greatly eliminate the snap-back condition of the device, making the PN junction not easy to conduct, thereby improving the safe working area of LIGBT.
  • FIG. 5 a and FIG. 5 b do not show the situation inside the device (inside the top silicon layer 120 ), the dotted line in FIG. 5 c indicates the N well region inside the top silicon layer 120 . As shown in FIG. 5c, more than two N-well regions arranged at intervals may be alternately distributed with multiple P-well regions on a plane parallel to the substrate.
  • a plurality of N well regions and a plurality of P well regions are arranged in the manner of "N well region-P well region-N well region"; along the second direction, the plurality of The N well regions and the multiple P well regions are also arranged in the manner of "N well region-P well region-N well region".
  • the N well regions should be arranged at intervals below the P+ contact regions.
  • the N-well region may be adjacent to the P-well region; of course, the present application does not exclude the situation that there is a gap between them.
  • the P well region On the upper surface of the top silicon layer 120, the P well region should have an exposed portion; while the N well region may not be exposed.
  • the upper surface mentioned in each embodiment of the present application should be understood as the surface of the corresponding structure away from the substrate; correspondingly, the lower surface should be understood as the surface of the corresponding structure close to the substrate.
  • embodiments of the present application should not be limited to the particular shapes of regions shown herein but are to include deviations in shapes that result, for example, from manufacturing techniques.
  • an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region.
  • a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation was performed.
  • the regions shown in the figures are schematic in nature and their shapes do not indicate the actual shape of a region of a device and are not intended to limit the scope of the application.

Abstract

本申请实施例提供的逆导型横向绝缘栅双极型晶体管，包括：形成于衬底上的漂移区，位于所述漂移区上的栅极，位于漂移区上且靠近栅极一侧的发射极区域，以及位于漂移区上且远离栅极一侧的集电极区域；其中，在漂移区的集电极区域所在的一侧设置有两个以上间隔布置的N阱区；在两个以上间隔布置的N阱区之间设置有P阱区；在N阱区上设置有P+接触区；在P阱区上设置有N+接触区；P+接触区和N+接触区均与集电极引出端导电连接。

Description

逆导型横向绝缘栅双极型晶体管
相关申请的交叉引用
本申请要求于2021年5月31日提交中国专利局、申请号为2021106004896、发明名称为“逆导型横向绝缘栅双极型晶体管”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体器件技术领域，特别是涉及逆导型横向绝缘栅双极型晶体管。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成示例性技术。
横向绝缘栅双极型晶体管(Lateral Insulated-Gate Bipolar Transistor，LIGBT)，是一种将MOS管和双极晶体管优点集于一身的晶体管。而绝缘衬底上硅(Silicon on Insulator，SOI)技术以其理想的介质隔离性能，广泛应用于功率集成电路制造中。SOI-LIGBT器件是一种基于SOI技术制造的LIGBT器件。
智能功率模块(IPM)现广泛用于电机驱动和马达驱动中，在中功率的条件下经常会使用全集成的SOI-LIGBT作为其功率开关器件，而LIGBT并联高压续流二极管(FWD)为最经典的开关器件结构。当LIGBT正向导通时，空穴注入形成大电流导通，驱动感性负载正常工作；当LIGBT关断时，感性负载因其电流不能突变，需要有一个回路来续流，此时并联的FWD就起到了续流作用，当下一个阶段LIGBT的栅极打开，FWD经反向恢复后，重新回到截止状态，一个工作周期结束。
在集成功率模块设计时，由于LIGBT和FWD是两个不同类型器件，在工作时需要高度的匹配才可以保证开关特性正常，故在设计器件时需要考虑到LIGBT关断时的E off和FWD反向恢复时的trr二者的关系，否则容易造成过大的损耗和较长的延时，这对LIGBT模块的可靠性产生影响。
为了降低关断损耗，专利文献CN111816699A提出了一种具有自适应性的SOI LIGBT器件，其主要通过集成齐纳二极管，因齐纳二极管会随集电极电压上升而自适应性的反向击穿导通，在关断过程中也为快速抽取漂移区内存储的空穴提供了额外通路；在该专利文献中，还提及了集电极结构为集电极NMOS结构，在N型缓冲层中还具有第二P型阱区、P+阱电位区、N+集电极区和集电极槽栅；P+电位区与P+阱电位区短接，使得集电极与P+阱电位区的电势差也较小，无法在第二P阱区中形成反型层，导致N+集电区与N型缓冲层之间的导电通路被阻断，器件无法进入单极导电模式，从而消除器件正向导通时的snap-back效应。然而，该专利文献的结构中引入了齐纳二极管，由于齐纳二极管一般为齐纳型隧道击穿，当其作为逆导型LIGBT中的续流二极管使用时，在反向击穿时用在高压或超高压的条件下会比较局限；并且，该专利文献中的齐纳二极管虽然在抑制正向导通的snap-back效应方面有一定效果，但是却无法做到较快恢复的特性，由于其集电极结构的设置，LIGBT反向恢复阶段的开关关断速率仍有待提高。
发明内容
根据本申请的各种实施例，提供一种逆导型横向绝缘栅双极型晶体管。
一种逆导型横向绝缘栅双极型晶体管，包括：形成于衬底上的漂移区，位于所述漂移区上的栅极，位于所述漂移区上且靠近所述栅极一侧的发射极区域，以及位于所述漂移区上且远离所述栅极一侧的集电极区域；其中，
在所述漂移区的所述集电极区域所在的一侧设置有两个以上间隔布置的N阱区；
在两个以上间隔布置的所述N阱区之间设置有P阱区；
在所述N阱区上设置有P+接触区；
在所述P阱区上设置有N+接触区；
所述P+接触区和所述N+接触区均与集电极引出端导电连接。
在一可选实施例中，两个以上间隔设置的所述N阱区至少包括第一N阱区和第二N阱区；所述P阱区至少包括设置在所述第一N阱区和所述第二N阱区之间的第一P阱区；所述第一N阱区和所述第二N阱区的面积相等，且所述第一N阱区和所述第二N阱区相对于所述第一P阱区对称分布。
在一可选实施例中，沿平行于所述衬底所在平面的方向上，所述N+接触区的四周被所述P阱区包覆。
在一可选实施例中，所述N+接触区包括第一部分和第二部分；所述第一部分包括侧壁部和底部，所述侧壁部沿垂直于所述衬底所在平面的方向上延伸，所述底部在靠近所述衬底的一面连接所述侧壁部；所述第二部分在远离所述衬底的一面连接所述侧壁部；所述侧壁部的深度大于所述第二部分的深度。
在一可选实施例中，所述侧壁部的深度大于所述P+接触区的深度。
在一可选实施例中，在所述P阱区内形成有沟槽；所述第一部分的所述侧壁部和所述底部分别通过对所述沟槽的侧表面和底表面进行掺杂而形成。
在一可选实施例中，在所述沟槽内形成有填充结构；所述第二部分位于所述填充结构上。
在一可选实施例中，所述填充结构的材料包括绝缘材料和/或多晶硅。
在一可选实施例中，所述P阱区的数量为多个，多个N+接触区分别位于多个所述P阱区内；多个N+接触区与所述P+接触区在平行于所述衬底所在的平面上交错分布。
在一可选实施例中，两个以上间隔设置的所述N阱区与多个所述P阱区在平行于所述衬底所在的平面上交错分布。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请 的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例或示例性技术中的技术方案，下面将对实施例或示例性技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为一种常见横向绝缘栅双极型晶体管的剖面示意图；
图2为一相关实施例提供的逆导型横向绝缘栅双极型晶体管的剖面示意图；
图3为第一实施例提供的逆导型横向绝缘栅双极型晶体管的剖面示意图；
图4为第二实施例提供的逆导型横向绝缘栅双极型晶体管的剖面示意图；
图5a-图5c为一可选实施例中逆导型横向绝缘栅双极型晶体管的集电极区域的俯视示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦 合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...接触”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本申请教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应当理解的是，术语“包括/包含”或“具有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在，但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。同时，在本说明书中，术语“和/或”包括相关所列项目的任何及所有组合。
首先，请参考图1。图1为一种常见横向绝缘栅双极型晶体管的剖面示意图，如图所示，该横向绝缘栅双极型晶体管包括：SOI衬底(包括底硅层100、埋氧层110和顶硅层120)，位于顶硅层120的漂移区121，场氧化层130，栅极140，集电极处多晶硅场板150，位于漂移区121上且靠近栅极一 侧的发射极区域，以及位于漂移区121上且远离栅极一侧的集电极区域。其中，发射极区域设置有沟道区161，该沟道区161具体为P阱区，其作为LIGBT中横向MOS的导电沟道；在沟道区161上设置有衬底欧姆接触区171和源极欧姆接触区172，并且衬底欧姆接触区171和源极欧姆接触区172均与发射极引出端导电连接。集电极区域设置有N型缓冲区(下称N阱区162)，在N阱区162上设置有P+接触区173；P+接触区173和多晶硅场板150均与集电极引出端导电连接。
在上述结构中，LIGBT需要并联FWD；当LIGBT正向导通时，空穴注入形成大电流导通，驱动感性负载正常工作；当LIGBT关断时，感性负载因其电流不能突变，需要有一个回路来续流，此时并联的FWD就起到了续流作用，当下一个阶段LIGBT的栅极打开，FWD经反向恢复后，重新回到截止状态，一个工作周期结束。然而，由于LIGBT和FWD是两个不同类型器件，在工作时需要高度的匹配才可以保证开关特性正常，故如何将独立的FWD与LIGBT进行了集成，成为本领域的一个重要研究方向。
考虑到上述结构中，由于集电极为P+(请参考图1中P+接触区173)而使得LIGBT无电流泄放通路，只能从并联的二极管(即FWD)中流出；本申请首先提出了一相关实施例，该相关实施例提供了一种逆导型横向绝缘栅双极型晶体管，通过对LIGBT集电极结构的改进，提升了LIGBT在开关时的特性。具体请参考图2，如图所示，在该相关实施例中，在N阱区162内除设置P+接触区173外，还设置有N+接触区174，即在集电极区域增加了N+接触区；并且，在N+接触区174的下端用P阱区163包围。从而，当LIGBT正常导通时，P+接触区173的空穴注入到N阱区162和漂移区121中产生电导调制效应，触发了PNP三极管后电流急剧上升，LIGBT进入正向导通工作，此时N+接触区174和P阱区163处于反偏状态，电子无法渡越过耗尽层而形成LDMOS，故在正向LIGBT导通时不影响正常开启工作。当LIGBT反向关断时，LIGBT的集电极失去电压变为零电位，此时由于驱动的感性负载电流不能突变而通过发射极的P+(请参考图2中衬底欧姆接触区171)流入，相 比于现有技术中的常规结构，该相关实施例提供的结构由于N+接触区174的存在，使得续流时有电流通路可以通过回到线圈当中，故不需要额外再并联FWD来续流，在模块工作时可以大大节省版图面积，也提高了LIGBT的可靠性。
但是，在图2所示的相关实施例中，P+接触区173、N+接触区174和P阱区163均设置在同一个N阱区162上，在LIGBT反向恢复时，少子空穴需要渡越的势垒较高，LIGBT反向恢复阶段的开关关断速率有待提高。
基于此，本申请提出以下实施例，逆导型横向绝缘栅双极型晶体管包括：形成于衬底上的漂移区，位于漂移区上的栅极，位于漂移区上且靠近栅极一侧的发射极区域，以及位于漂移区上且远离栅极一侧的集电极区域；其中，
在漂移区的集电极区域所在的一侧设置有两个以上间隔布置的N阱区；
在两个以上间隔布置的N阱区之间设置有P阱区；
在N阱区上设置有P+接触区；
在P阱区上设置有N+接触区；
P+接触区和N+接触区均与集电极引出端导电连接。
可以理解地，相比于现有技术，本申请实施例通过改进LIGBT集电极区域的结构，不仅使得改进后的器件结构无需额外再并联FWD来续流，在模块工作时可以大大节省版图面积，提高LIGBT的可靠性，而且由于具有间隔布置的N阱区结构，P阱区设置在间隔布置的N阱区之间，从而进一步提升了LIGBT在反向恢复阶段的开关关断速率，提升了整个器件的开关特性。
首先，结合图3对本申请实施例进行进一步解释说明。图3为本申请第一实施例提供的逆导型横向绝缘栅双极型晶体管的剖面示意图；如图所示，该逆导型横向绝缘栅双极型晶体管包括：SOI衬底，即包括底硅层100、埋氧层110和顶硅层120。
底硅层100具有第一导电类型，具体例如为P型，即底硅层100为P型衬底(Psub)。其材料为硅；当然，本申请实施例也不限于此，本领域中常用的材料，如碳化硅、砷化镓、磷化铟或锗硅等，也可以作为本申请实施例中 SOI衬底的底层衬底的材料。
埋氧层110位于底硅层100上，其材料通常为硅的氧化物，例如二氧化硅。埋氧层110一般为从功能上而言的命名(BOX)，具体为一层绝缘层，其材料也可以为不限于二氧化硅的其他绝缘材料。
顶硅层120位于埋氧层110上，具体可以为具有第二导电类型的外延层，其作为制作器件的层。顶硅层120在LIGBT器件中作为漂移区(图中用漂移区121表示)。第二导电类型具体可以为N型，作为漂移区，具有的导电类型与底硅层100的导电类型相反。漂移区121具体为N-区。顶硅层120的材料为硅；当然，本申请实施例也不限于此，本领域中常用的材料，如碳化硅、砷化镓、磷化铟或锗硅等，也可以作为本申请实施例中SOI衬底的顶层衬底的材料。
场氧化层130形成于漂移区121上，场氧化层130的材料可以为硅的氧化物，例如二氧化硅。场氧化层130为LIGBT的场区，作为器件的横向隔离。
在场氧化层130上形成有栅极140，栅极140的材料例如为多晶硅，作为LIGBT的栅极。
在场氧化层130上还形成有集电极处多晶硅场板150，其作为LIGBT集电极处的多晶硅场板。
沟道区161和N阱区162均位于漂移区121上，且二者沿图中第一方向间隔设置。沟道区161位于靠近栅极140所在的一侧；沟道区161具有第一导电类型，具体例如为P阱。沟道区161形成横向MOS的导电沟道。N阱区162位于远离栅极140所在的一侧。N阱区162在LIGBT的集电极区域，作为LIGBT的N型缓冲层，以防止穿通。
在沟道区161内设置有具有第一导电类型的衬底欧姆接触区171和具有第二导电类型的源极欧姆接触区172。衬底欧姆接触区171具体为P+型区域，作为衬底引出。源极欧姆接触区172具体为N+型区域，作为MOS的源端欧姆接触。源极欧姆接触区172在朝向栅极140的一侧与沟道区161接触，以在沟道区161内感生出沟道。
在漂移区121的集电极区域(如图中虚线框所示)所在的一侧设置有两个以上间隔布置的N阱区(图3中以第一N阱区1621和第二N阱区1622为例加以示出)；该N阱区作为LIGBT的缓冲区。而本实施了提供的逆导型LIGBT中，将缓冲区分开，分成两个以上间隔布置的N阱区，从而独立成为LIGBT单元。
在N阱区上设置有P+接触区173，P+接触区173又可称为集电极欧姆接触区，其作为LIGBT的集电极欧姆接触，提供电极引出。具体地，各N阱区上可分别设置有独立的P+接触区；各P+接触区可以如图3所示分别位于对应的各N阱区内，P+接触区的侧面和底部均被N阱区包覆；各P+接触区也可以分别位于对应的各N阱区上，仅底部被N阱区包覆。
在两个以上间隔布置的N阱区之间(如第一N阱区1621和第二N阱区1622之间)设置有P阱区163；该P阱区163为正向导通截止P阱。
在该P阱区163上设置有N+接触区174；该N+接触区174作为LIGBT的集电极端的N+引出，为逆导时产生二极管的阴极。
如图所示，P+接触区173和N+接触区174均与集电极引出端导电连接。
如此，LIGBT的发射极(Emit)、集电极(Collector)、栅极(Gate)已在图中示出。
这里，将垂直于衬底所在的平面的方向定义为第三方向，即各层结构的堆叠方向。在平行于衬底所在的平面上定义两彼此垂直的第一方向和第二方向。
本申请实施例将相关实施例中整个的N阱区162分立开来，变为几个独立的(图3仅示意性地示出了两个N阱区，实际应用中可以是至少两个间隔型的N阱区)，如此，不仅无需额外再并联FWD来续流，而且可以提升在LIGBT反向恢复阶段的开关关断速率。
这里，应当理解的，N+接触区174的至少一部分(具体例如为除上表面以外的部分)与P阱区163的至少一部分直接接触；二者之间形成PN结，并具体为P/N+。P阱区163的至少一部分(至少包括下表面所在的部分)与 漂移区121直接接触；二者之间形成PN结，并具体为P/N-。P阱区163与漂移区121之间的势垒显然低于相关实施例中P阱区163与N阱区162之间的势垒。
请继续参考图3，两个以上间隔设置的N阱区至少包括第一N阱区1621和第二N阱区1622；P阱区163至少包括设置在第一N阱区1621和第二N阱区1622之间的第一P阱区(由于图3所示剖面仅存在一个P阱区，因此参考图中P阱区163即可)；第一N阱区1621和第二N阱区1622的面积相等，且第一N阱区1621和第二N阱区1622相对于第一P阱区对称分布。
可以理解地，由于第一N阱区和第二N阱区的面积相等，且第一N阱区和第二N阱区相对于第一P阱区对称分布，因此在器件正向导通时，电流能够更加均匀地流向集电极区域的每个P+接触区，使得器件的导通特性更加稳定；反之，如果呈非对称等非均匀分布的情况，则容易造成器件在未经过PNP阶段前就提前开启，使整个器件丧失电导调制效应而变成LDMOS。在反向续流时也会产生同样的问题，如果呈非均匀分布，逆导型的二极管续流特性下降，电阻变大且不容易快速恢复；而第一N阱区和第二N阱区的面积相等且对称分布时，续流特性较好，恢复较快。
第一N阱区1621、第一P阱区和第二N阱区1622例如沿第一方向依次布置。该第一方向也为从发射极区域到集电极区域的方向。第一N阱区1621、第一P阱区和第二N阱区1622可以依次邻接，以节省面积。
沿平行于衬底所在平面的方向上，N+接触区174的四周被P阱区163包覆。可以理解地，P阱区163将N+接触区174包覆后，在LIGBT开启初期不会像常见LIGBT那样有snap-back现象(即正向电压达到一定程度时，电流增大电压反而下降的现象)，因为N+接触区174不参与LIGBT正向开启时的工作，它此时是穿透的LIGBT那样工作，正向导通压降小，故有着较小的Vcesat特性；同时，在关断时有部分少子会渡越过N+接触区174和P阱区163形成的PN结势垒，而与N+接触区174复合掉，从而降低了LIGBT拖尾的现象，降低了关断损耗。
图4为第二实施例提供的逆导型横向绝缘栅双极型晶体管的剖面示意图。如图所示，在该实施例中，N+接触区174包括第一部分1742和第二部分1744；第一部分1742包括侧壁部和底部，侧壁部沿垂直于衬底所在平面的方向上延伸，底部在靠近衬底的一面连接侧壁部；第二部分1744在远离衬底的一面连接侧壁部；侧壁部的深度大于第二部分1744的深度。
这里，第二部分1744以及第一部分1742的底部，可以作为LIGBT集电极端的横向N+引出；而第一部分1742的侧壁部可以作为LIGBT集电极端的纵向N+引出；以上均为逆导时产生二极管的阴极。
该第二实施例进一步地实现了以下有益效果：一方面，在集电极区域增加了N+的接触面积，即横向N+和纵向N+，再在，N+接触区的上表面进行导电接触；因为N+的接触面积大，因此可以极大发挥N+作为反向二极管时的作用，大大增强了逆导LIGBT反向的续流能力；同时，在作为二极管反向恢复时，少子空穴沿着侧壁部移动的数量大于沿着上表面移动的数量，如此少子运动的路径更短，可以进一步提高空穴复合的效率，提高反向恢复时间trr，降低反向恢复时的峰值电流Irr。另一方面，还可以很大程度的减少LIGBT集电极区域的面积，因为形成第一部分1742的结构(具体为沟槽结构)的pitch(即间距)可以设计的很小，在相同深度情况下并不会减少N+注入面积，因此可以通过降低集电极区域的面积来减少LIGBT整体的面积。
在实际制备过程中，可以通过先在P阱区163内形成沟槽，对沟槽的侧表面和底表面进行掺杂而形成上述第一部分1742；然后，填充该沟槽，并在沟槽顶部形成上述第二部分1744。其中，掺杂例如采用离子注入等工艺执行。
在器件结构中，在P阱区163内形成有沟槽；第一部分1742的侧壁部和底部分别通过对沟槽的侧表面和底表面进行掺杂而形成。如此，第一部分1742的剖面形状可以与形成的沟槽的形状类似，例如为U形。
在沟槽内形成有填充结构180；第二部分1744位于填充结构180上。
上述填充结构180的材料包括绝缘材料和/或多晶硅。在一可选实施例中，填充结构180的材料包括绝缘材料，具体例如为氧化硅；并且在绝缘材料上 还可以进一步填充多晶硅，进而在多晶硅中形成第二部分1744。在另一可选实施例中，可以直接在沟槽中填充多晶硅，并在多晶硅的上表面形成第二部分1744。
如此，在第一部分1742和第二部分1744之间，即在N+接触区174内部，至少包括填充材料。
在本实施例中，第一部分1742的上述侧壁部的深度例如大于P+接触区173的深度。
图5a-图5c为一可选实施例中逆导型横向绝缘栅双极型晶体管的集电极区域的俯视示意图。
首先，请参考图5a。如图所示，上述P阱区的数量可以为多个，多个N+接触区分别位于多个P阱区内；多个N+接触区与P+接触区在平行于衬底所在的平面上交错分布。
这里，虽然没有明确示出P+接触区，但是可以理解地，无论沿第一方向还是沿第二方向，在相邻两N+接触区之间具有P+接触区。进一步地，相邻两N+接触区之间具有P+接触区，并且相邻两P+接触区之间具有N+接触区。
而图5b示出了一种可能情况，即P+接触区位于各N+接触区之间，且具体位于各P阱区之间。P+接触区连成一个整体，各P阱区及位于对应P阱区内的N+接触区类似于岛状分布在P+接触区内。
可以理解地，相对于方格型版图(或者矩阵阵列式排布)，交错分布的结构更加适合应用于高电流密度的情况；大电流LIGBT容易在发射极区域发生snap-back现象，而采用N+与P+的交错布局，可以极大程度的杜绝器件发生snap-back的条件，使得PN结不容易导通，从而提升LIGBT的安全工作区。
由于图5a和图5b没有示出器件内部(顶硅层120内部)的情况，因此利用图5c中虚线表示位于顶硅层120内部的N阱区。如图5c所示，两个以上间隔设置的N阱区可以与多个P阱区在平行于衬底所在的平面上交错分布。
在一具体实施例中，沿第一方向，多个N阱区与多个P阱区按照“N阱 区-P阱区-N阱区……”的方式排布；沿第二方向，多个N阱区与多个P阱区同样按照“N阱区-P阱区-N阱区……”的方式排布。
可以理解地，即使在图5b所示的P+接触区在顶硅层120的上表面连成一个整体的结构中，各N阱区在P+接触区下方还应当是间隔设置的。
N阱区可以与P阱区相邻接；当然，本申请也不排除二者之间留有空隙的情况。在顶硅层120的上表面，P阱区应当具有暴露的部分；而N阱区可以不被暴露。
本申请各实施例中提及的上表面应当理解为相应结构的远离衬底的表面；对应地，下表面应当理解为相应结构的靠近衬底的表面。
应当说明的是，本申请的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不表示器件的区的实际形状，且并不限定本申请的范围。
在本说明书的描述中，参考术语“在一实施例中”、“在一可选实施例中”、“在其他实施例中”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术语的示意性描述不一定指的是相同的实施例或示例。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种逆导型横向绝缘栅双极型晶体管，包括：形成于衬底中的漂移区，位于所述漂移区上的栅极，位于所述漂移区上且靠近所述栅极一侧的发射极区域，以及位于所述漂移区上且远离所述栅极一侧的集电极区域；其中，
    在所述漂移区的所述集电极区域所在的一侧设置有两个以上间隔布置的N阱区；
    在两个以上间隔布置的所述N阱区之间设置有P阱区；
    在所述N阱区上设置有P+接触区；
    在所述P阱区上设置有N+接触区；
    所述P+接触区和所述N+接触区均与集电极引出端导电连接。
  2. 根据权利要求1所述的逆导型横向绝缘栅双极型晶体管，其中两个以上间隔设置的所述N阱区至少包括第一N阱区和第二N阱区；所述P阱区至少包括设置在所述第一N阱区和所述第二N阱区之间的第一P阱区；所述第一N阱区和所述第二N阱区的面积相等，且所述第一N阱区和所述第二N阱区相对于所述第一P阱区对称分布。
  3. 根据权利要求2所述的逆导型横向绝缘栅双极型晶体管，其中从所述发射极区域到所述集电极区域的方向，所述第一N阱区、所述第一P阱区和所述第二N阱区依次布置。
  4. 根据权利要求1所述的逆导型横向绝缘栅双极型晶体管，其中沿平行于所述衬底所在平面的方向上，所述N+接触区的四周被所述P阱区包覆。
  5. 根据权利要求1所述的逆导型横向绝缘栅双极型晶体管，其中所述N+接触区包括第一部分和第二部分；所述第一部分包括侧壁部和底部，所述侧壁部沿垂直于所述衬底所在平面的方向上延伸，所述底部在靠近所述衬底的一面连接所述侧壁部；所述第二部分在远离所述衬底的一面连接所述侧壁部；所述侧壁部的深度大于所述第二部分的深度。
  6. 根据权利要求5所述的逆导型横向绝缘栅双极型晶体管，其中所述侧壁部的深度大于所述P+接触区的深度。
  7. 根据权利要求5所述的逆导型横向绝缘栅双极型晶体管，其中在所述P阱区内形成有沟槽；所述第一部分的所述侧壁部和所述底部分别通过对所述沟槽的侧表面和底表面进行掺杂而形成。
  8. 根据权利要求7所述的逆导型横向绝缘栅双极型晶体管，其中在所述沟槽内形成有填充结构；所述第二部分位于所述填充结构上。
  9. 根据权利要求8所述的逆导型横向绝缘栅双极型晶体管，其中所述填充结构的材料包括绝缘材料和/或多晶硅。
  10. 根据权利要求1所述的逆导型横向绝缘栅双极型晶体管，其中所述P阱区的数量为多个，多个N+接触区分别位于多个所述P阱区内；多个N+接触区与所述P+接触区在平行于所述衬底所在的平面上交错分布。
  11. 根据权利要求10所述的逆导型横向绝缘栅双极型晶体管，其中两个以上间隔设置的所述N阱区与多个所述P阱区在平行于所述衬底所在的平面上交错分布。
  12. 根据权利要求1所述的逆导型横向绝缘栅双极型晶体管，其中所述P阱区与所述漂移区之间的势垒低于所述P阱区与所述N阱区之间的势垒。
  13. 根据权利要求1所述的逆导型横向绝缘栅双极型晶体管，其中还包括位于所述漂移区上且靠近所述栅极所在的一侧的沟道区，所述沟道区形成导电沟道；其中，所述N阱区与所述沟道区间隔设置，以作为所述逆导型横向绝缘栅双极型晶体管的N型缓冲层。
  14. 根据权利要求13所述的逆导型横向绝缘栅双极型晶体管，其中在所述沟道区内设置有具有第一导电类型的衬底欧姆接触区和具有第二导电类型的源极欧姆接触区，所述源极欧姆接触区在朝向所述栅极的一侧与所述沟道区接触，以在所述沟道区内感生出沟道。
  15. 根据权利要求1所述的逆导型横向绝缘栅双极型晶体管，其中还包括形成于所述漂移区和所述栅极之间的场氧化层，所述场氧化层作为所述漂移区和所述栅极之间的隔离场区。
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