CN107516670B - 一种具有高电流上升率的栅控晶闸管 - Google Patents
一种具有高电流上升率的栅控晶闸管 Download PDFInfo
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Abstract
本发明提供了一种具有高电流上升率的栅控晶闸管,属于功率器件技术领域。本发明自下而上包括依次层叠设置的金属阳极、第一导电类型半导体掺杂衬底,第二导电类型半导体掺杂外延层,所述第二导电类型半导体掺杂外延层的上表面设置有金属阴极和绝缘栅,所述第二导电类型半导体掺杂外延层的顶层两端分别设置有第一导电类型半导体掺杂阱区,第二导电类型半导体掺杂阱区和第一导电类型半导体重掺杂区,第二导电类型半导体掺杂阱区材料的禁带宽度大于第一导电类型半导体掺杂阱区材料的禁带宽度,第一导电类型半导体掺杂阱区材料的禁带宽度大于第二导电类型半导体掺杂外延层的禁带宽度。基于本发明器件结构能够大幅度提高了栅控晶闸管的电流上升率。
Description
技术领域
本发明属于功率器件技术领域,具体涉及一种具有高电流上升率的栅控晶闸管。
背景技术
电容式能量存储器具有稳定的能量存储、高功率密度和高传输速度等优点,在具有高瞬时功率的脉冲功率系统中,系统的能源供给通常由电容式能量存储提供。脉冲宽度是由电路的时间常数决定的,因此电容式能量存储器需要足够低的负载阻抗以产生短脉冲大电流,从而实现脉冲功率系统中的高电流上升速率。火花隙等传统开关器件具有开关速率低、使用寿命短和效率低下等缺点,而固体开关器件因其优越轻便性、低成本和高效率等特点在脉冲功率系统中得到了应用。栅控晶闸管具有高电导调制效应与极低的导通电阻,因此栅控晶闸管器件在脉冲放电应用中具有明显的优势。但是在短脉冲操作中,特别是在快速开启时,器件有可能来不及达到导通状态以泄放脉冲能量,无法完成操作。或者因为泄放时间较长,器件同时经受高电压和大电流,导致结温升高,即使进入导通状态开始泄放脉冲能量,也会因为过热导致过早失效。
当栅控晶闸管应用在脉冲放电电路中时,需要器件能够承受具有高电流上升率(di/dt)的浪涌电流。一个有效提高器件承受浪涌电流的方法就是增加器件浓度梯度以实现阴极侧的载流子注入增强。对于N型栅控晶闸管而言,通过增加N阱浓度梯度,在三极管发射区形成对少子空穴的减速场,阻止基区的空穴往发射区扩散,增大发射极注入效率;通过增加P阱浓度梯度,在三极管基区中形成电子的加速场,增大基区输运系数。传统栅控晶闸管的制造工艺是基于DMOS技术的三重扩散工艺,由于阴极侧的P阱与N阱都是通过注入扩散形成,其浓度受器件正向导通能力与耐压要求所限制,在制造工艺中无法针对高的通态电流临界上升率di/dt特性进行浓度分布的调整。故而,亟需一种能够提升高电流上升特性,进而解决器件因无法快速泄放浪涌电流而失效的问题。
发明内容
本发明所要解决的技术问题在于:提供一种具有高电流上升率的栅控晶闸管。本发明为解决上述技术问题提供如下技术方案:
一种具有高电流上升率的栅控晶闸管,包括第一导电类型半导体掺杂衬底(2),设置于在所述第一导电类型半导体掺杂衬底(2)背面的金属阳极(1),设置在所述第一导电类型半导体掺杂衬底(2)正面的第二导电类型半导体掺杂外延层(3),所述第二导电类型半导体掺杂外延层(3)的顶层表面设置有金属阴极(7)和绝缘栅,其中绝缘栅位于中间,金属阴极(7)位于绝缘栅两边并与之相隔离;所述绝缘栅包括栅介质层(9)及设置于所述栅介质层(9)上表面的多晶硅栅(8);所述第二导电类型半导体掺杂外延层(3)的顶层两端分别设置有第一导电类型半导体掺杂阱区(4),所述第一导电类型半导体掺杂阱区(4)中设置有第二导电类型半导体掺杂阱区(5),所述第二导电类型半导体掺杂阱区(5)中设置有第一导电类型半导体重掺杂区(6);所述第二导电类型半导体掺杂阱区(5)及部分第一导电类型半导体重掺杂区(6)与金属阴极(7)连接,所述第一导电类型半导体掺杂阱区(4)、第二导电类型半导体掺杂阱区(5)和第一导电类型半导体重掺杂区(6)均与绝缘栅连接;其特征在于,第二导电类型半导体掺杂阱区(5)材料的禁带宽度大于第一导电类型半导体掺杂阱区(4)材料的禁带宽度,第一导电类型半导体掺杂阱区(4)材料的禁带宽度大于第二导电类型半导体掺杂外延层(3)的禁带宽度。
进一步的是,本发明中第一导电类型半导体为P型,第二导电类型半导体为N型。
进一步的是,本发明中第一导电类型半导体为N型,第二导电类型半导体为P型。
进一步的是,本发明中第一导电类型半导体或者所述第二导带类型半导体的材料为体硅、碳化硅、砷化镓、磷化铟或者锗硅复合材料。
本发明的有益效果在于:提供合理设置第一导电类型半导体掺杂阱区、第二导电类型半导体掺杂阱区及外延层的禁带宽度,定义第一导电类型半导体掺杂阱区、第二导电类型半导体掺杂阱区和外延层的禁带宽度值顺次为Eg1、Eg2和Eg3;本发明使得Eg1>Eg2>Eg3,藉由这一技术手段增大了NPN管和PNP管的电流放大系数αNPN和αPNP,使栅控晶闸管中的内部晶闸管结构的闩锁条件αNPN+αPNP≥1更容易达到。应用本发明器件结构在脉冲放电电路中时,能够迅速进入闩锁状态,承受很高的电流,获得高电流上升率di/dt。
附图说明
图1是本发明提供的一种具有高电流上升率的栅控晶闸管的剖面结构示意图;
图2是本发明提供的N型栅控晶闸管的等效电路示意图;
图3为本发明提供的一种具有高电流上升率的栅控晶闸管中N阱与P阱的PN结能带结构图,I为反射区,II为势垒区,III为基区。
图4为本发明提供的一种具有高电流上升率的栅控晶闸管中P阱与N-漂移区的PN结能带结构图,I为发射区,II为势垒区,III为基区。
具体实施方式
下面参照附图对本发明进行更全面的描述,在附图中相同的标号表示相同或者相似的组件或者元素。本发明的要旨在于提高一种具有高电流上升率的栅控晶闸管器件,栅控晶闸管器件可以是P型栅控晶闸管器件,也可以是N型栅控晶闸管器件。
实施例:
如图1所示,本实施例提供一种具有高电流上升率的栅控晶闸管,包括第一导电类型半导体掺杂衬底2,设置于在所述第一导电类型半导体掺杂衬底2背面的金属阳极1,设置在所述第一导电类型半导体掺杂衬底2正面的第二导电类型半导体掺杂外延层3,所述第二导电类型半导体掺杂外延层3的顶层表面设置有金属阴极7和绝缘栅,其中绝缘栅位于中间,金属阴极7位于绝缘栅两边并与之相隔离;所述绝缘栅包括栅介质层9及设置于所述栅介质层9上表面的多晶硅栅8;所述第二导电类型半导体掺杂外延层3的顶层两端分别设置有第一导电类型半导体掺杂阱区4,所述第一导电类型半导体掺杂阱区4中设置有第二导电类型半导体掺杂阱区5,所述第二导电类型半导体掺杂阱区5中设置有第一导电类型半导体重掺杂区6;所述第二导电类型半导体掺杂阱区5及部分第一导电类型半导体重掺杂区6与金属阴极7连接,所述第一导电类型半导体掺杂阱区4、第二导电类型半导体掺杂阱区5和第一导电类型半导体重掺杂区6均与绝缘栅连接;其特征在于,第二导电类型半导体掺杂阱区5材料的禁带宽度大于第一导电类型半导体掺杂阱区4材料的禁带宽度,第一导电类型半导体掺杂阱区4材料的禁带宽度大于第二导电类型半导体掺杂外延层3的禁带宽度。
本发明的要旨在于提供一种栅控晶闸管器件,基于上述技术方案,当第一导电类型半导体为P型半导体而第二导电类型半导体为N型半导体时,本发明提供的器件为N型栅控晶闸管器件;当第一导电类型半导体为N型半导体而第二导电类型半导体为P型半导体时,本发明提供的器件为P型栅控晶闸管器件。下面具体以N型栅控晶闸管器件为例对本发明的原理及特性进行详细说明,相应地,P型栅控晶闸管器件也类似,在此不再赘述:
如图2所示为本发明提供N型栅控晶闸管的等效电路示意图,其内部的晶闸管结构由N阱5、P阱4、N-外延层3和P+衬底2组成;其中,N阱5、P阱4和N-外延层3构成NPN三极管,P阱4、N-外延层3和P+衬底2构成了PNP三极管。
如图3所示为本发明栅控晶闸管的NPN三极管结构的发射区I(N阱5)和基区III(P阱4)形成的PN结能带图,其发射区I的禁带宽度Eg1大于基区III的禁带宽度Eg2,在空间电荷区II中形成势垒,发射区I中的电子注入基区III所需克服的势垒高度qV1小于基区III中的空穴注入发射区I所需克服的势垒高度qV2,基区III中的空穴注入发射区I变得更困难,因此NPN三极管的注入效率增加,增大了NPN管的电流放大系数αNPN。
如图4所示为本发明栅控晶闸管的PNP三极管结构的发射区I(P阱4)和基区III(N-外延层3)形成的PN结能带图,其发射区I的禁带宽度Eg2大于基区III的禁带宽度Eg3,在空间电荷区II中形成势垒,发射区I中的空穴注入基区III所需克服的势垒高度qV4小于基区III中的电子注入发射区I所需克服的势垒高度qV3,基区III中的电子注入发射区I变得更困难,因此PNP三极管的注入效率增加,增大了PNP管的电流放大系数αPNP。
本发明所提供的一种具有高电流上升率的栅控晶闸管器件,定义N阱5、P阱4和N-外延层3的禁带宽度值顺次为Eg1、Eg2和Eg3,由于改变了N阱和P阱的禁带宽度,使得Eg1>Eg2>Eg3,同时增大了NPN管和PNP管的电流放大系数αNPN和αPNP,使栅控晶闸管中的内部晶闸管结构的闩锁条件αNPN+αPNP≥1更容易达到。应用本发明器件结构在脉冲放电电路中时,能够迅速进入闩锁状态,承受很高的电流,获得高电流上升率di/dt。
以上结合附图对本发明的实施例进行了阐述,但是本发明并不局限于上述的具体实施方式,上述具体实施方式仅仅是示意性的,而不是限制性的,本领域的普通技术人员在本发明的启示下,在不脱离本发明宗旨和权利要求所保护的范围情况下,还可做出很多形式,这些均属于本发明的保护之内。
Claims (4)
1.一种具有高电流上升率的栅控晶闸管,包括第一导电类型半导体掺杂衬底(2),设置于在所述第一导电类型半导体掺杂衬底(2)背面的金属阳极(1),设置在所述第一导电类型半导体掺杂衬底(2)正面的第二导电类型半导体掺杂外延层(3),所述第二导电类型半导体掺杂外延层(3)的顶层表面设置有金属阴极(7)和绝缘栅,其中绝缘栅位于中间,金属阴极(7)位于绝缘栅两边并与之相隔离;所述绝缘栅包括栅介质层(9)及设置于所述栅介质层(9)上表面的多晶硅栅(8);所述第二导电类型半导体掺杂外延层(3)的顶层两端分别设置有第一导电类型半导体掺杂阱区(4),所述第一导电类型半导体掺杂阱区(4)中设置有第二导电类型半导体掺杂阱区(5),所述第二导电类型半导体掺杂阱区(5)中设置有第一导电类型半导体重掺杂区(6);所述第二导电类型半导体掺杂阱区(5)及部分第一导电类型半导体重掺杂区(6)与金属阴极(7)连接,所述第一导电类型半导体掺杂阱区(4)、第二导电类型半导体掺杂阱区(5)和第一导电类型半导体重掺杂区(6)均与栅介质层(9)连接;其特征在于,第二导电类型半导体掺杂阱区(5)材料的禁带宽度大于第一导电类型半导体掺杂阱区(4)材料的禁带宽度,第一导电类型半导体掺杂阱区(4)材料的禁带宽度大于第二导电类型半导体掺杂外延层(3)的禁带宽度。
2.根据权利要求1所述的一种具有高电流上升率的栅控晶闸管,其特征在于,第一导电类型半导体为P型,第二导电类型半导体为N型。
3.根据权利要求1所述的一种具有高电流上升率的栅控晶闸管,其特征在于,第一导电类型半导体为N型,第二导电类型半导体为P型。
4.根据权利要求1所述的一种具有高电流上升率的栅控晶闸管,其特征在于,第一导电类型半导体或者所述第二导电类型半导体的材料为体硅、碳化硅、砷化镓、磷化铟或者锗硅复合材料。
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WO1999017374A1 (en) * | 1997-09-30 | 1999-04-08 | Virginia Tech Intellectual Properties, Inc. | Emitter turn-off thyristors (eto) |
JPH11274482A (ja) * | 1998-03-20 | 1999-10-08 | Toshiba Corp | 半導体装置 |
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WO1999017374A1 (en) * | 1997-09-30 | 1999-04-08 | Virginia Tech Intellectual Properties, Inc. | Emitter turn-off thyristors (eto) |
US6933541B1 (en) * | 1997-09-30 | 2005-08-23 | Virginia Tech Intellectual Properties, Inc. | Emitter turn-off thyristors (ETO) |
JPH11274482A (ja) * | 1998-03-20 | 1999-10-08 | Toshiba Corp | 半導体装置 |
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