CN116264244A - Igbt器件 - Google Patents

Igbt器件 Download PDF

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CN116264244A
CN116264244A CN202111561080.4A CN202111561080A CN116264244A CN 116264244 A CN116264244 A CN 116264244A CN 202111561080 A CN202111561080 A CN 202111561080A CN 116264244 A CN116264244 A CN 116264244A
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gate
body region
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shielding
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刘伟
林敏之
袁愿林
王睿
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Suzhou Dongwei Semiconductor Co ltd
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Suzhou Dongwei Semiconductor Co ltd
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Priority to CN202111561080.4A priority Critical patent/CN116264244A/zh
Priority to PCT/CN2022/101534 priority patent/WO2023109080A1/zh
Priority to KR1020237001403A priority patent/KR20230092865A/ko
Priority to JP2023503499A priority patent/JP7485433B2/ja
Publication of CN116264244A publication Critical patent/CN116264244A/zh
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Abstract

本发明属于半导体功率器件技术领域，具体公开了一种IGBT器件，n型半导体层内的若干个栅沟槽，位于栅沟槽的下部内的屏蔽栅，位于栅沟槽的上部内的栅极，栅极、屏蔽栅与n型半导体层之间互相绝缘隔离；部分屏蔽栅外接栅极电压并定义为第一屏蔽栅，剩余的屏蔽栅外接发射极电压并定义为第二屏蔽栅，第一屏蔽栅与第二屏蔽栅交替间隔设置；位于n型半导体层内且介于相邻的栅沟槽之间的p型体区，p型体区包括第一p型体区和第二p型体区两部分，第一p型体区位于靠近相邻的第一屏蔽栅的一侧，第二p型体区位于靠近相邻的第二屏蔽栅的一侧，第一p型体区的掺杂浓度小于第二p型体区的掺杂浓度。

Description

IGBT器件
技术领域
本发明属于半导体功率器件技术领域，特别是涉及一种IGBT器件。
背景技术
绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor，IGBT)器件是由金属氧化物半导体(Metal Oxide Semiconductor，MOS)晶体管和双极型晶体管复合而成的一种器件，IGBT器件的输入极为MOS晶体管，输出极为PNP型晶体管，它融合了这两种晶体管器件的优点，既具有MOS晶体管驱动功率小和开关速度快的优点，又具有双极型晶体管饱和压降低和容量大的优点。IGBT器件由于p型体区与n型漂移区交界处空穴注入效率较低，载流子浓度分布很低，导致饱和压降升高，在关断时，n型漂移区内储存了大量的少数载流子，导致IGBT器件关断电流拖尾现象严重，关断损耗大。
发明内容
有鉴于此，本发明的目的是提供一种IGBT器件，以降低IGBT器件的关断损耗。
为达到本发明的上述目的，本发明提供了一种IGBT器件，包括：
p型集电极区；
位于所述p型集电极区之上的n型半导体层；
位于所述n型半导体层内的若干个栅沟槽，位于所述栅沟槽的下部内的屏蔽栅，位于所述栅沟槽的上部内的栅极，所述栅极、所述屏蔽栅与所述n型半导体层之间互相绝缘隔离；
部分所述屏蔽栅外接栅极电压并定义为第一屏蔽栅，剩余的所述屏蔽栅外接发射极电压并定义为第二屏蔽栅，所述第一屏蔽栅与所述第二屏蔽栅交替间隔设置；
位于所述n型半导体层内且介于相邻的所述栅沟槽之间的p型体区，所述p型体区包括第一p型体区和第二p型体区两部分，所述第一p型体区位于靠近相邻的所述第一屏蔽栅的一侧，所述第二p型体区位于靠近相邻的所述第二屏蔽栅的一侧，所述第一p型体区和所述第二p型体区内均设有n型发射极区，所述第一p型体区的掺杂浓度小于所述第二p型体区的掺杂浓度。
可选的，所述屏蔽栅由所述栅沟槽的下部向上延伸至所述栅沟槽的上部内。
可选的，所述栅沟槽的上部的宽度大于所述栅沟槽的下部的宽度。
可选的，还包括位于所述n型半导体层内的n型电荷存储区，所述n型电荷存储区位于所述栅极的下方。
可选的，还包括n型集电极区，所述n型集电极区位于所述n型半导体层下方且与所述p型集电极区交替间隔设置。
可选的，还包括n型场截止区，所述n型场截止区介于所述p型集电极区与所述n型半导体层之间。
本发明的IGBT器件，将低阈值电压Vth1与大栅电荷Qg1组合，高阈值电压Vth2和小栅电荷Qg2组合，IGBT器件从导通到关断的过程中，高Vth2和小Qg2组合的区域内的电流沟道会迅速关断，而低Vth1与大Qg1组合的区域内的电流沟道会晚点关断，由此，高Vth2和小Qg2组合的区域内电流沟道在刚关断时，低Vth1与大Qg1组合的区域内的电流沟道仍处于导通状态，随着栅电压Vg的进一步降低，低Vth1与大Qg1组合的区域内的电流沟道关断。从而，IGBT器件对外表现为低Vth1与大Qg1组合的区域的关断损耗，减少了高Vth2和小Qg2组合的区域的关断损耗，从整体上降低了IGBT器件的关断损耗。
附图说明
为了更加清楚地说明本发明示例性实施例的技术方案，下面对描述实施例中所需要用到的附图做一简单介绍。
图1是本发明提供的IGBT器件的第一个实施例的剖面结构示意图；
图2是本发明提供的IGBT器件的第二个实施例的剖面结构示意图。
具体实施方式
以下将结合本发明实施例中的附图，通过具体方式，完整地描述本发明的技术方案。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。同时，为清楚地说明本发明的具体实施方式，说明书附图中所列示意图，放大了本发明所述的层和区域的厚度，且所列图形大小并不代表实际尺寸。
图1是本发明提供的IGBT器件的第一个实施例的剖面结构示意图，如图1所示，本发明的IGBT器件包括p型集电极区20，位于p型集电极区20之上的n型半导体层21。
位于n型半导体层21内的若干个栅沟槽，位于栅沟槽的上部内的栅极25，位于栅沟槽的下部内的屏蔽栅27，屏蔽栅27可以仅位于栅沟槽的下部内，从而栅极25与屏蔽栅27为上下结构，可选的，屏蔽栅27也可以位于栅沟槽的下部内并向上延伸至栅沟槽的上部内，图1以屏蔽栅27位于栅沟槽的下部内并向上延伸至栅沟槽的上部内为例示出。同时，栅沟槽的上部的宽度可以大于、等于或者小于栅沟槽的下部的宽度，在图1中，以栅沟槽的上部的宽度大于栅沟槽的下部的宽度示出。
栅极25、屏蔽栅27与n型半导体层21之间互相绝缘隔离，在图1中，栅极25通过栅介质层24与n型半导体层21绝缘隔离，屏蔽栅27通过场氧化层26与栅极25和n型半导体层21隔离，通常，场氧化层26的厚度大于栅介质层24的厚度。
本发明的IGBT器件，部分屏蔽栅27外接栅极电压G并定义为第一屏蔽栅27a，剩余的栅沟槽内的屏蔽栅27外接发射极电压(图1中未示出)并定义为第二屏蔽栅27b，第一屏蔽栅27a与第二屏蔽栅27b交替间隔设置。
本发明的IGBT器件还包括位于n型半导体层21内且介于相邻的栅沟槽之间的p型体区22，p型体区22包括第一p型体区22a和第二p型体区22b两部分，第一p型体区22a位于靠近相邻的第一屏蔽栅27a的一侧，第二p型体区22b位于靠近相邻的第二屏蔽栅27b的一侧。第一p型体区22a和第二p型体区22b内均设有n型发射极区23。第一p型体区22a的掺杂浓度小于第二p型体区22b的掺杂浓度。
示例性的，图1中仅示出了4个p型体区22，且仅中间两个p型体区22完整的示出了第一p型体区22a和第二p型体区22b两部分，而边上的两个p型体区22仅示出了第二p型体区22b部分。
本发明的IGBT器件，第一p型体区22a内的电流沟道的阈值电压Vth1小于第二p型体区22b内的电流沟道的阈值电压Vth2。屏蔽栅27外接栅极电压时，该栅沟槽内的栅极25具有更大的栅电荷Qg1；屏蔽栅27外接发射极电压时，该栅沟槽内的栅极25具有小的栅电荷Qg2。将第一p型体区22a和第一屏蔽栅27a相邻设置，并将第二p型体区22b和第二屏蔽栅27b相邻设置，可以使得低Vth1与大Qg1组合，高Vth2和小Qg2组合，从而，IGBT器件从导通到关断的过程中，高Vth2和小Qg2组合的区域内电流沟道会迅速关断，而低Vth1与大Qg1组合的区域内的电流沟道会晚点关断，由此，高Vth2和小Qg2组合的区域内的电流沟道在刚关断时，低Vth1与大Qg1组合的区域内的电流沟道仍处于导通状态，随着栅电压Vg的进一步降低，低Vth1与大Qg1组合的区域的电流沟道关断。从而，IGBT器件对外表现为低Vth1与大Qg1组合的区域的关断损耗，减少了高Vth2和小Qg2组合的区域的关断损耗，从整体上降低了IGBT器件的关断损耗。
图2是本发明提供的IGBT器件的第二个实施例的剖面结构示意图，如图2所示，在图1所示IGBT器件结构的基础上，本发明的IGBT器件还包括位于n型半导体层21内的n型电荷存储区32，n型电荷存储区32位于栅极25的下方。本发明的IGBT器件还包括n型集电极区30，n型集电极区30位于n型半导体层21下方且与p型集电极区20交替间隔设置。可选的，本发明的IGBT器件还可以包括n型场截止区31，n型场截止区31介于p型集电极区20与n型半导体层21之间。n型电荷存储区32、n型场截止区31和n型集电极区30均为已知技术，本发明实施例中不再详细描述。
以上具体实施方式及实施例是对本发明技术思想的具体支持，不能以此限定本发明的保护范围，凡是按照本发明提出的技术思想，在本技术方案基础上所做的任何等同变化或等效的改动，均仍属于本发明技术方案保护的范围。

Claims (6)

1.IGBT器件，其特征在于，包括：
p型集电极区；
位于所述p型集电极区之上的n型半导体层；
位于所述n型半导体层内的若干个栅沟槽，位于所述栅沟槽的下部内的屏蔽栅，位于所述栅沟槽的上部内的栅极，所述栅极、所述屏蔽栅与所述n型半导体层之间互相绝缘隔离；
部分所述屏蔽栅外接栅极电压并定义为第一屏蔽栅，剩余的所述屏蔽栅外接发射极电压并定义为第二屏蔽栅，所述第一屏蔽栅与所述第二屏蔽栅交替间隔设置；
位于所述n型半导体层内且介于相邻的所述栅沟槽之间的p型体区，所述p型体区包括第一p型体区和第二p型体区两部分，所述第一p型体区位于靠近相邻的所述第一屏蔽栅的一侧，所述第二p型体区位于靠近相邻的所述第二屏蔽栅的一侧，所述第一p型体区和所述第二p型体区内均设有n型发射极区，所述第一p型体区的掺杂浓度小于所述第二p型体区的掺杂浓度。
2.如权利要求1所述的IGBT器件，其特征在于，所述屏蔽栅由所述栅沟槽的下部向上延伸至所述栅沟槽的上部内。
3.如权利要求2所述的IGBT器件，其特征在于，所述栅沟槽的上部的宽度大于所述栅沟槽的下部的宽度。
4.如权利要求3所述的IGBT器件，其特征在于，还包括位于所述n型半导体层内的n型电荷存储区，所述n型电荷存储区位于所述栅极的下方。
5.如权利要求1所述的IGBT器件，其特征在于，还包括n型集电极区，所述n型集电极区位于所述n型半导体层下方且与所述p型集电极区交替间隔设置。
6.如权利要求1所述的IGBT器件，其特征在于，还包括n型场截止区，所述n型场截止区介于所述p型集电极区与所述n型半导体层之间。
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