WO2024012283A1 - 显示基板以及显示装置 - Google Patents

显示基板以及显示装置 Download PDF

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Publication number
WO2024012283A1
WO2024012283A1 PCT/CN2023/105120 CN2023105120W WO2024012283A1 WO 2024012283 A1 WO2024012283 A1 WO 2024012283A1 CN 2023105120 W CN2023105120 W CN 2023105120W WO 2024012283 A1 WO2024012283 A1 WO 2024012283A1
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WO
WIPO (PCT)
Prior art keywords
sub
pixel
transistor
connection structure
base substrate
Prior art date
Application number
PCT/CN2023/105120
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English (en)
French (fr)
Inventor
龙春平
Original Assignee
京东方科技集团股份有限公司
北京京东方技术开发有限公司
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Publication of WO2024012283A1 publication Critical patent/WO2024012283A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels

Definitions

  • At least one embodiment of the present invention relates to a display substrate and a display device.
  • AMOLED Active Matrix Organic Light-Emitting Diode
  • LCDs liquid crystal displays
  • AMOLED Active Matrix Organic Light-Emitting Diode
  • a pixel circuit is provided in the display area, and a gate drive circuit, such as a GOA drive circuit, is provided in the frame area to provide drive signals to the pixel circuit.
  • At least one embodiment of the present invention provides a display substrate, which includes a substrate substrate on which a plurality of pixels arranged in an array are provided; each pixel in at least part of the plurality of pixels is It includes a plurality of sub-pixels, at least part of the plurality of sub-pixels including a pixel circuit, and the pixel circuit includes: a light-emitting device, a storage capacitor, a driving transistor and a data writing transistor, a data line and a first connection structure.
  • a light emitting device, a storage capacitor, a driving transistor and a data writing transistor each of the driving transistor and the data writing transistor includes an active layer, a gate electrode, a first electrode and a second electrode, the driving transistor is configured as The light-emitting device is controlled to emit light; a data line is connected to a first pole of the data writing transistor and is configured to provide a data signal to the data writing transistor; the data writing transistor is configured to respond to the data applied to the data writing transistor. writing the first scan signal to the gate of the transistor and writing the data signal to the gate of the driving transistor; the first connection structure is connected to the gate of the driving transistor and the first plate of the storage capacitor , the data lines and The first connection structures all extend along a first direction, and the data lines include overlapping portions.
  • the overlapping portions of the first connection structures and the data lines are at least partially opposite to each other in a second direction, and the second direction Parallel to the base substrate and perpendicular to the first direction; the overlapping portions of the first connection structure and the data line are insulated from each other, and the overlapping portions of the first connection structure and the data line respectively constitute parasitic The first plate and the second plate of the capacitor; the ratio of the capacitance value of the parasitic capacitance to the capacitance value of the storage capacitor is greater than 0.001 and less than 0.01.
  • the size of one sub-pixel in the second direction is greater than 50 ⁇ m, and the ratio of the capacitance value of the parasitic capacitor to the capacitance value of the storage capacitor is less than 0.005. .
  • the size of one sub-pixel in the second direction is less than or equal to 68 ⁇ m, and the ratio of the capacitance value of the parasitic capacitor to the capacitance value of the storage capacitor is greater than Equal to 0.003.
  • the size of one sub-pixel in the second direction is less than 50 ⁇ m, and the ratio of the capacitance value of the parasitic capacitor to the capacitance value of the storage capacitor is greater than 0.005. And less than 0.006.
  • the first connection structure includes a first portion extending along the first direction, and the first portion of the first connection structure is close to an overlapping portion of the data line.
  • the edge is a first edge
  • the first part of the first connection structure also has a second edge with an overlapping part away from the data line
  • the edge of the overlapping part of the data line close to the first connection structure is a third edge.
  • the plurality of sub-pixels include a first sub-pixel and a second sub-pixel adjacent to each other in the second direction; the second edge of the first connection structure of the first sub-pixel is on the substrate
  • the distance of the orthographic projection of the third edge of the overlapping portion of the data line of the second sub-pixel on the substrate on the substrate is a first distance
  • the first connection structure of the first sub-pixel The distance from the first edge to the third edge of the overlapping portion of the data line of the first sub-pixel is a second distance, and the ratio of the first distance to the second distance is greater than 14.
  • the size of one sub-pixel in the second direction is less than 50 ⁇ m, and the ratio of the first distance to the second distance is greater than 14 and less than 15.5.
  • the size of one sub-pixel in the second direction is greater than 50 ⁇ m, and the ratio of the first distance to the second distance is greater than 15.5.
  • the plurality of sub-pixels include a first sub-pixel and a second sub-pixel adjacent to each other in the second direction; the first connection of the first sub-pixel The structure is located between the data line of the first sub-pixel and the data line of the second sub-pixel in the second direction; the first connection structure of the first sub-pixel is on the base substrate.
  • the distance between the orthographic projection and the orthographic projection of the data line of the first sub-pixel on the base substrate is smaller than a size of one of the sub-pixels in the second direction, and the first sub-pixel
  • the distance between the orthographic projection of the first connection structure of the pixel on the base substrate and the orthographic projection of the data line of the second sub-pixel on the base substrate is less than one of the sub-pixels on the base substrate.
  • the first connection structure of the first sub-pixel is located between the data line of the first sub-pixel and the data line of the second sub-pixel in the second direction. between lines; the distance between the orthographic projection of the first connection structure of the first sub-pixel on the base substrate and the orthographic projection of the data line of the first sub-pixel on the base substrate is less than The size of one of the sub-pixels in the second direction, and the orthographic projection of the first connection structure of the first sub-pixel on the base substrate is in line with the data line of the second sub-pixel.
  • a distance between orthographic projections on the base substrate is greater than a size of one of the sub-pixels in the second direction.
  • the edge of the overlapping portion of the gate of the driving transistor of the first sub-pixel close to the data line of the second sub-pixel is a fourth edge; the first The distance from the second edge of the sub-pixel to the third edge of the second sub-pixel is equal to the distance from the second edge of the first sub-pixel to the fourth edge of the first sub-pixel. The sum of the distances from the edge to the third edge of the second sub-pixel.
  • the first connection structure and the data line are arranged in different layers, and the orthographic projection of the first connection structure on the base substrate is different from the orthographic projection of the data line.
  • the orthographic projection of the overlapping portion on the base substrate at least partially overlaps; or, the first connection structure and the data line are arranged in different layers, and the orthographic projection of the first connection structure on the base substrate overlaps with that of the data line. Orthographic projections of the overlapping portions of the data lines on the base substrate do not overlap.
  • the first connection structure and the data line are arranged on the same layer, and the overlapping portions of the first connection structure and the data line are opposite to each other in the second direction.
  • At least one of the overlapping portions of the data lines and the first connection structure includes a recessed portion, and the overlapping portions of the data lines and the first connection structure The recessed portion of either of the first connection structures is recessed in the second direction toward a direction away from the overlapping portion of the data line and the other of the first connection structures.
  • the overlapping portion of the data lines includes a first recessed portion, and the first recessed portion is recessed in a direction away from the first connection structure in the second direction.
  • the portion of the first connection structure opposite to the data line is in a straight strip shape.
  • the first connection structure includes a second recessed portion, and the second recessed portion is recessed in a direction away from the overlapping portion of the data lines in the second direction.
  • the overlapping portion of the data lines is in a straight strip shape.
  • the overlapping portion of the data lines includes a first recessed portion, and the first recessed portion is recessed in a direction away from the first connection structure in the second direction.
  • the first connection structure includes a second recessed portion, the second recessed portion is recessed in a direction away from the overlapping portion of the data line in the second direction.
  • a display substrate provided by an embodiment of the present invention further includes a first reset scanning signal line, a second reset scanning signal line, a first reset signal line and a second reset signal line;
  • the pixel circuit further includes: a first reset transistor and a second reset transistor.
  • the first reset transistor includes an active layer, the first reset scan signal line is configured to provide a first reset scan signal to a gate electrode of the first reset transistor, and a first electrode of the first reset transistor is connected to the drive The gate electrode of the transistor is electrically connected, the second electrode of the first reset transistor is configured to be electrically connected to the first reset signal line to receive the first reset signal, and the first reset transistor is configured to respond to the first reset signal line.
  • a reset scan signal writes the first reset signal to the gate of the driving transistor;
  • the second reset scan signal line is configured to provide a second reset scan signal to the gate of the second reset transistor, the A first electrode of the second reset transistor is electrically connected to the first display electrode of the light emitting device, and a second electrode of the second reset transistor is configured to be electrically connected to the second reset signal line to receive a second reset signal.
  • the second reset transistor is configured to write the second reset signal into the first display electrode of the light emitting device in response to the second reset scan signal;
  • the active layer of the first reset transistor is arranged along the Extending in a first direction, the first reset scanning signal line extends along the second direction;
  • the plurality of sub-pixels include first sub-pixels and second sub-pixels adjacent to each other in the second direction;
  • the plurality of sub-pixels also includes a third sub-pixel, the third sub-pixel is adjacent to the second sub-pixel in the first direction;
  • the portion of the second reset signal line located at one of the sub-pixels includes a transverse portion and a first longitudinal portion, said transverse portion extending along said second direction and having an opposite direction to each other in said second direction
  • the first end and the second end of the first longitudinal part are connected to the first end of the lateral part and extend along the first direction, and the lateral direction of the second reset signal line of the second sub-pixel
  • a portion of the orthographic projection on the base substrate at
  • the planar pattern of the sub-portion of the second reset signal line corresponding to one sub-pixel is an inverted "ji" shape; the "ji"-shaped sub-portion includes U-shaped groove, the lateral part of the second reset signal line serves as the bottom of the U-shaped groove.
  • a display substrate provided by an embodiment of the present invention further includes a compensation scanning signal line;
  • the pixel circuit further includes a compensation transistor, including an active layer, a gate electrode, a first electrode and a second electrode; the compensation scanning signal line configuration
  • the compensation transistor is configured to perform threshold compensation on the drive transistor in response to the second scan signal;
  • the active layer of the compensation transistor is connected to the gate of the compensation transistor.
  • the active layer of the first reset transistor forms an integrated structure.
  • the portion of the second reset signal line located in one of the sub-pixels further includes a second longitudinal portion, and the second longitudinal portion is connected to the second portion of the horizontal portion. terminals are connected and extend along the first direction, the active layer of the second reset transistor is located between the first longitudinal part and the second longitudinal part, and, in the same sub-pixel, in In the second direction, the distance from the first longitudinal part to the data line is greater than the distance from the second longitudinal part to the data line.
  • the distance between the active layer of the second reset transistor of the third subpixel and the first longitudinal portion of the second reset signal line of the second subpixel is smaller than the active layer of the second reset transistor of the third subpixel. The distance from the layer to the second longitudinal portion of the second reset signal line of the second sub-pixel.
  • the gate electrode of the driving transistor and the first plate of the storage capacitor are arranged on the same layer and form an integrated structure, and the second reset scanning signal line and the first plate of the storage capacitor are arranged in the same layer.
  • the gate electrode of the driving transistor is arranged on the same layer; the gate electrode of the driving transistor and the first plate of the storage capacitor are located on a side of the active layer of the driving transistor away from the substrate; the storage capacitor The second plate is located on the side of the gate of the driving transistor and the first plate of the storage capacitor away from the base substrate, and the compensation scanning signal line is connected to the second plate of the storage capacitor.
  • the active layer of the compensation transistor is located on the second plate of the storage capacitor
  • the second reset signal line is located on a side of the active layer of the compensation transistor away from the base substrate.
  • a display substrate provided by an embodiment of the present invention further includes a first reset scanning signal line and a first reset signal line
  • the pixel circuit further includes a first reset transistor.
  • the first reset transistor includes an active layer
  • the first reset scan signal line is configured to provide a first reset scan signal to the gate of the first reset transistor
  • the first electrode of the second reset transistor is connected to the drive
  • the gate electrode of the transistor is electrically connected
  • the second electrode of the first reset transistor is configured to be electrically connected to the first reset signal line to receive the first reset signal
  • the first reset transistor is configured to respond to the first reset signal line.
  • a reset scan signal writes the first reset signal to the gate of the driving transistor; the active layer of the first reset transistor and the active layer of the driving transistor are made of different materials and are arranged in different layers;
  • the first reset signal line is arranged on the same layer as the second plate of the storage capacitor.
  • the gate electrode of the compensation transistor and the gate electrode of the first reset transistor both have a double-gate structure, and the gate electrode of the compensation transistor includes a first gate electrode and a third gate electrode.
  • the gate of the first reset transistor includes a first gate and a second gate; the orthographic projection of the first gate of the compensation transistor on the base substrate is consistent with the third gate of the compensation transistor.
  • the orthographic projection of the two gates on the base substrate coincides with the orthographic projection of the first gate of the first reset transistor on the base substrate and the second gate of the first reset transistor.
  • the orthographic projections on the substrate are coincident.
  • the first gate of the compensation transistor and the first gate of the first reset transistor are arranged on the same layer as the second plate of the storage capacitor.
  • the second gate of the compensation transistor and the second gate of the first reset transistor are located on a side of the active layer of the compensation transistor and the active layer of the first reset transistor away from the base substrate, and is located on a side of the second reset signal line close to the base substrate.
  • the material of the active layer of the first reset transistor is an oxide semiconductor; the material of the active layer of the driving transistor and the data writing transistor is low-temperature polysilicon.
  • the first connection structure is located on a side of the second plate of the storage capacitor away from the base substrate; the second plate of the storage capacitor has The first via hole of the first plate of the storage capacitor is exposed, and the first connection structure passes through the first via hole to be connected to the first plate of the storage capacitor; the second plate of the storage capacitor is exposed.
  • Plate includes A first portion located on a first side of the first via hole in the second direction and a second portion located on a second side of the first via hole in the second direction, the first via hole The first side of the hole is opposite to the second side of the first via hole, and the second part of the second plate is located on a side of the first part of the second plate close to the data line;
  • the orthographic projection of the edge of the connection structure on the base substrate and the orthographic projection of the edge of the second part of the second plate close to the first connection structure on the base substrate overlap.
  • the first connection structure and the second reset signal line are arranged on the same layer; when the first connection structure and the data line are arranged on different layers, The data line is located on a side of the first connection structure away from the base substrate, or the data line is located on a side of the first connection structure close to the base substrate.
  • the first connection structure includes a first part extending along the first direction and a second part extending along the second direction.
  • the second part is connected to the first part of the first connection structure;
  • the active layer of the compensation transistor is located on a side of the first connection structure away from the data line, and the second part of the first connection structure Connected to the active layer of the compensation transistor.
  • the orthographic projection of the entire first connection structure on the base substrate is located at the orthographic projection of the first display electrode of the light-emitting device on the base substrate.
  • the plurality of sub-pixels include a first sub-pixel and a second sub-pixel adjacent to each other in the second direction; the first display electrode of the first sub-pixel covers the first sub-pixel and the The boundary of the second sub-pixel, and the orthographic projection of the first connection structure of the first sub-pixel on the base substrate and the orthogonal projection of the first connection structure of the second sub-pixel on the base substrate
  • the projections are all located within the orthographic projection of the first display electrode of the first sub-pixel on the base substrate.
  • the orthographic projection of the edge of the first display electrode of the first sub-pixel away from the second sub-pixel on the base substrate is different from the first sub-pixel.
  • the orthographic projection of the edge of the first connection structure of the pixel close to the data line of the first sub-pixel overlaps on the base substrate, and the edge of the first display electrode of the first sub-pixel close to the second sub-pixel.
  • the orthographic projection of the edge on the base substrate overlaps with the orthographic projection of the edge of the first connection structure of the second sub-pixel close to the data line of the second sub-pixel on the base substrate.
  • a part of the orthographic projection of the first structure on the base substrate is located on the orthographic projection of the first display electrode of the light-emitting device on the base substrate.
  • the plurality of sub-pixels include a first sub-pixel and a second sub-pixel adjacent to each other in the second direction; the first display electrode of the first sub-pixel covers the first sub-pixel and the The boundary of the second sub-pixel, and a part of the orthographic projection of the first connection structure of the first sub-pixel on the base substrate and the first connection structure of the second sub-pixel on the base substrate
  • a part of the orthographic projection is located within the orthographic projection of the first display electrode of the first sub-pixel on the base substrate.
  • the luminescent material of the luminescent device of the first sub-pixel emits green light.
  • the first plate of the storage capacitor has an upper surface away from the base substrate and a side surface intersecting the upper surface; the second plate of the storage capacitor
  • the plate includes: a middle part and an edge part.
  • the orthographic projection of the middle portion on the base substrate at least partially coincides with the orthographic projection of the first plate of the storage capacitor on the base substrate, and includes an upper surface of the first plate of the storage capacitor.
  • an edge portion at least partially surrounds the middle portion and is connected to the middle portion, and includes a bottom surface close to the base substrate and an inner side intersecting the bottom surface; the inner side is connected to the storage
  • the side surfaces of the first plates of the capacitor are opposite to each other, and the orthographic projection of the inner surface on a reference plane perpendicular to the substrate substrate is consistent with the orthographic projection of the first plate of the storage capacitor opposite to the inner surface.
  • the orthographic projection of the side surface on the reference plane at least partially overlaps; the distance between the inner side of the edge portion and the side surface of the first plate of the storage capacitor opposite to the inner side is less than The distance between the bottom surface of the middle part and the upper surface of the first plate of the storage capacitor.
  • the first display electrode of the light-emitting device has a first end and a second end opposite to each other in the second direction;
  • the display substrate includes a first semiconductor layer , the first semiconductor layer includes an active layer of the driving transistor and an active layer of the data writing transistor, the data line is connected to the first semiconductor layer through a second via hole;
  • the plurality of sub- The pixel includes a first sub-pixel and a second sub-pixel adjacent to each other in the second direction; the first display electrode of the first sub-pixel covers the boundary of the first sub-pixel and the second sub-pixel.
  • the orthographic projection of the first end of the first display electrode of the first sub-pixel on the substrate has a second via hole on the substrate in the second direction toward the first sub-pixel.
  • a convex and tapered first protrusion is projected, and an orthographic projection of the second end of the first display electrode of the first sub-pixel on the base substrate has a direction facing the second direction in the second direction.
  • the second via hole of the two sub-pixels projects a convex and tapered second protruding portion orthogonally on the base substrate, and the first protruding portion is connected to the second via hole of the first sub-pixel.
  • the orthographic projection of the hole on the base substrate is directly opposite in the second direction, and the orthographic projection of the second protruding portion and the second via hole of the second sub-pixel on the base substrate Opposite in the second direction; the luminescent material of the luminescent device of the first sub-pixel emits blue light.
  • the gate electrode of the driving transistor and the first plate of the storage capacitor are arranged on the same layer and form an integrated structure; the gate electrode of the driving transistor and the storage capacitor The first plate of the capacitor is located on a side of the active layer of the driving transistor away from the substrate; the second plate of the storage capacitor is located on the gate of the driving transistor and the third plate of the storage capacitor.
  • the display substrate On a side of a polar plate away from the base substrate, the display substrate further includes a first power line connected to a first voltage terminal and configured to provide a first power voltage to the pixel circuit, along The first direction extends; the pixel circuit also includes a second connection structure, the second connection structure is located between the first power line and the second plate of the storage capacitor in a direction perpendicular to the substrate. between the first power line and the second plate of the storage capacitor, wherein the second connection structure includes a horizontal part and a vertical part, and the horizontal part extends along the second direction, The vertical part is connected to the horizontal part and extends along the first direction; the orthographic projection of the first power line on the substrate substrate and the horizontal part of the second connection structure are on the substrate.
  • the orthographic projections on the base substrate overlap, and the orthographic projections of the first power line on the base substrate overlap with the orthographic projections of other structures arranged on the same layer as the second connection structure on the base substrate. There is no overlap.
  • the vertical portion is substantially aligned with the first connection structure in the first direction, and the orthographic projection of the horizontal portion on the base substrate is from the An orthographic projection of the vertical portion on the base substrate extends along the first direction to an orthographic projection of the first power line on the base substrate.
  • a display substrate provided by an embodiment of the present invention further includes a first insulating layer and a second insulating layer.
  • a first insulating layer is located between the first power line and the second connection structure;
  • a second insulating layer is located between the second connection structure and the second plate of the storage capacitor, wherein the third A horizontal part of a power line is connected to the second connection structure through a third via hole penetrating the first insulation layer,
  • the vertical portion of the second connection structure is connected to the second plate of the storage capacitor through a fourth via hole penetrating the second insulation layer.
  • the first power line and the data line are arranged on the same layer, and the second connection structure and the first connection structure are arranged on the same layer.
  • the pixel circuit further includes a first light-emitting transistor, the first light-emitting transistor is connected to the first electrode of the driving transistor and the first voltage terminal, and is configured to respond
  • the first light-emitting control signal applied to the gate of the first light-emitting transistor applies the first power supply voltage of the first voltage terminal to the first electrode of the driving transistor;
  • the display substrate includes a first semiconductor layer,
  • the first semiconductor layer includes an active layer of the driving transistor, an active layer of the data writing transistor and an active layer of the first light-emitting transistor, and a horizontal portion of the second connection structure passes through a fifth
  • the via hole is connected to the first semiconductor layer.
  • the horizontal part of the second connection structure has a first end and a second end opposite to each other in the second direction, and the first end of the horizontal part is located A side of the first power cord close to the vertical part is connected to the vertical part, and a second end of the horizontal part is located on a side of the first power cord away from the vertical part. and connected to the first semiconductor layer through the fifth via hole.
  • At least one embodiment of the present invention further provides a display device, which includes any display substrate provided by the embodiment of the present invention.
  • FIG. 1 is a schematic plan view of a display substrate according to an embodiment of the present invention.
  • FIG. 2A is a schematic diagram of a pixel circuit provided by at least one embodiment of the present invention.
  • FIG. 2B is a circuit diagram of a specific example of the pixel circuit shown in FIG. 2A.
  • FIG. 2C is a signal timing diagram of a driving method for a pixel circuit provided by at least one embodiment of the present invention.
  • 3A is a schematic plan view of a stack of a first semiconductor layer and a first conductive layer of a sub-pixel of a display substrate according to an embodiment of the present invention.
  • FIG. 3B shows a second conductive layer and a sub-pixel of a display substrate according to an embodiment of the present invention. Schematic plan view of the second semiconductor layer stack.
  • 3C is a schematic plan view of a first semiconductor layer, a first conductive layer, a second conductive layer and a second semiconductor layer stack of a sub-pixel of a display substrate according to an embodiment of the present invention.
  • 3D is a schematic plan view of a second conductive layer and a third conductive layer stack of a sub-pixel of a display substrate according to an embodiment of the present invention.
  • 3E is a schematic plan view of a first semiconductor layer, a first conductive layer, a second conductive layer, and a stack of a second semiconductor layer and a third conductive layer of a sub-pixel of a display substrate according to an embodiment of the present invention.
  • 3F is a schematic plan view of a stack of a first interlayer insulating layer and a fourth conductive layer of a sub-pixel of a display substrate according to an embodiment of the present invention.
  • 3G shows the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer, the third conductive layer stack and the first interlayer insulating layer of a sub-pixel of a display substrate according to an embodiment of the present invention. and a plan view of the fourth conductive layer stack.
  • 3H is a schematic plan view of a first flat layer and a fifth conductive layer stack of a sub-pixel of a display substrate according to an embodiment of the present invention.
  • 3I shows the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer, the third conductive layer stack and the first interlayer insulating layer of a sub-pixel of a display substrate according to an embodiment of the present invention. , a plan view of a stack of the fourth conductive layer, the first planar layer and the fifth conductive layer.
  • 3J is a schematic plan view of a stack of a second flat layer, a first electrode and a pixel defining layer of a sub-pixel of a display substrate according to an embodiment of the present invention.
  • 3K is a schematic plan view of a sub-pixel of a display substrate according to an embodiment of the present invention, that is, a stack of the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer and the third conductive layer of the sub-pixel. , a plan view of a stack of the first interlayer insulating layer, the fourth conductive layer, the first planarization layer, the fifth conductive layer, the second planarization layer, the first electrode and the pixel definition layer.
  • FIG. 4A is a schematic cross-sectional view along the active layer direction of the third transistor and the sixth transistor in FIG. 3K .
  • Figure 4B is a schematic structural diagram of a display substrate.
  • Figure 4C is a schematic diagram of an electrode facing a flat capacitor.
  • Figure 4D is a schematic diagram of a plate capacitor with tilted electrodes.
  • FIG. 4E is another schematic cross-sectional view of a display substrate provided by an embodiment of the present invention.
  • Figure 5 is a diagram of at least two adjacent sub-pixels of a display substrate according to an embodiment of the present invention. Schematic plan view.
  • FIG. 6 is a schematic diagram based on FIG. 5 after removing the first power line.
  • FIG. 7A is a schematic cross-sectional view from a first perspective along the active layer direction of the fourth transistor, the third transistor, the second transistor, and the first transistor in FIG. 3K .
  • FIG. 7B is a schematic cross-sectional view from a second perspective along the active layer direction of the fourth transistor, the third transistor, the second transistor, and the first transistor in FIG. 3K .
  • FIG. 7C is a schematic cross-sectional view along the active layer direction of the fifth transistor, the third transistor, and the sixth transistor in FIG. 3K , that is, a schematic cross-sectional view along line A1-A2 in FIG. 3K .
  • FIG. 7D is a schematic cross-sectional view along the active layer direction of the third transistor and the sixth transistor in FIG. 3K , that is, a schematic cross-sectional view along line B1 - B2 in FIG. 3K .
  • FIG. 8 is another schematic plan view of a display substrate provided by an embodiment of the present invention.
  • FIG. 9 is another schematic cross-sectional view of a display substrate provided by an embodiment of the present invention.
  • FIG. 10 is another schematic cross-sectional view of a display substrate provided by an embodiment of the present invention.
  • FIG. 11 is another schematic plan view of a display substrate provided by an embodiment of the present invention.
  • FIG. 12 is another schematic plan view of a display substrate provided by an embodiment of the present invention.
  • FIG. 13 is another schematic cross-sectional view of a display substrate provided by an embodiment of the present invention.
  • FIG. 14A is a schematic diagram of a first connection structure and data lines in a display substrate according to an embodiment of the present invention.
  • FIG. 14B is a schematic diagram of a first connection structure and data lines in another display substrate according to an embodiment of the present invention.
  • FIG. 14C is a schematic diagram of another first connection structure and data lines in a display substrate according to an embodiment of the present invention.
  • FIG. 15 is a schematic diagram of a display device according to at least one embodiment of the present invention.
  • the orthographic projection of a certain structure on the base substrate in this application refers to the orthographic projection of the structure on the main surface of the base substrate, and the main surface of the base substrate refers to the arrangement of the pixel circuit on the base substrate. s surface.
  • the “same layer arrangement” referred to in the present invention refers to structures formed by two (or more than two) structures formed by the same deposition process and patterned by the same patterning process. Their materials Can be the same or different.
  • the “continuous integrated structure” in the present invention refers to the interconnected structures formed by patterning the same film layer through the same patterning process. Their materials may be the same or different.
  • Scan(N)(n) represents the scanning signal line connected to the N-type TFT in the n-th row
  • Scan(N)(n-1) represents the scanning signal connected to the N-type TFT in the n-1th row.
  • Scan(N)(n+1) represents the scanning signal line of the n+1th row connected to the N-type TFT.
  • Scan(P)(n) represents the scanning signal line connected to the P-type TFT in the nth row
  • Scan(P)(n+1) represents the scanning signal line connected to the P-type TFT in the n+1th row.
  • the pixel driving circuit of AMOLED has multiple transistors.
  • a parasitic capacitance is often formed between the gate node of the driving transistor of a pixel driving circuit and its adjacent data line, causing the jump voltage on the data line to change during the display process.
  • the drive voltage of the drive transistor has an impact.
  • At least one embodiment of the present invention provides a display substrate, which includes a substrate substrate on which a plurality of pixels arranged in an array are provided; each pixel in at least part of the plurality of pixels is including a plurality of sub-pixels, at least a portion of the plurality of sub-pixels including pixel circuitry,
  • the pixel circuit includes: a light emitting device, a storage capacitor, a driving transistor and a data writing transistor, a data line and a first connection structure.
  • a light emitting device, a storage capacitor, a driving transistor and a data writing transistor each of the driving transistor and the data writing transistor includes an active layer, a gate electrode, a first electrode and a second electrode, the driving transistor is configured as The light-emitting device is controlled to emit light; a data line is connected to a first pole of the data writing transistor and is configured to provide a data signal to the data writing transistor; the data writing transistor is configured to respond to the data applied to the data writing transistor.
  • the first connection structure is connected to the gate of the driving transistor and the first plate of the storage capacitor , the data line and the first connection structure both extend along the first direction, and the data line includes an overlapping portion, and the overlapping portion of the first connection structure and the data line is at least partially opposite in the second direction.
  • the second direction is parallel to the base substrate and perpendicular to the first direction; the overlapping portions of the first connection structure and the data line are insulated from each other, and the first connection structure and the data line are insulated from each other.
  • the overlapping parts respectively constitute the first plate and the second plate of the parasitic capacitance; the ratio of the capacitance value of the parasitic capacitance to the capacitance value of the storage capacitor is greater than 0.001 and less than 0.01.
  • At least one embodiment of the present invention further provides a display device, which includes any display substrate provided by the embodiment of the present invention.
  • FIG. 1 is a schematic plan view of a display substrate provided by an embodiment of the present invention.
  • the display substrate 10 includes a plurality of pixels 100 arranged in an array. At least some of the pixels 100 of the plurality of pixels 100 include a plurality of sub-pixels. At least some of the sub-pixels of the plurality of sub-pixels include a light emitting device and A pixel circuit that drives a light-emitting device to emit light.
  • the pixel circuit may include a 2T1C (ie, two transistors and a capacitor) pixel circuit, a 4T2C, 5T1C, 7T1C or nTmC (n and m are positive integers) pixel circuits.
  • the pixel circuit may further include a compensation subcircuit, which may include an internal compensation subcircuit or an external compensation subcircuit, and the compensation subcircuit may include a transistor, a capacitor, or the like.
  • the pixel circuit may further include a reset circuit, a light emission control sub-circuit, a detection circuit, etc.
  • a plurality of pixels 100 are located in the display area.
  • some of the plurality of pixels 100 are dummy pixels 1000.
  • the dummy pixels 1000 do not participate in the display work.
  • Each dummy pixel 1000 includes a plurality of dummy sub-pixels. pixels, but not the sub-pixels that drive the display.
  • the display substrate 10 is an organic light-emitting diode (OLED) display substrate, and the light-emitting device is an OLED.
  • the display substrate 10 may also include a plurality of scanning lines and a plurality of data lines for providing scanning signals (control signals) and data signals for the plurality of sub-pixels, thereby driving the plurality of sub-pixels.
  • the display substrate 10 may further include power lines, detection lines, etc.
  • FIG. 2A is a schematic diagram of a pixel circuit provided by at least one embodiment of the present invention.
  • the pixel circuit unit includes a driving sub-circuit 122, a compensation sub-circuit 128, a data writing sub-circuit 126, a storage sub-circuit 127, a first light-emitting control sub-circuit 123, a second light-emitting control sub-circuit 124 and a third A reset sub-circuit 125 and a second reset sub-circuit 129.
  • the driving sub-circuit 122 includes a control terminal 122a, a first terminal 122b and a second terminal 122c, and is configured to be connected to the light-emitting device 20 and control the driving current flowing through the light-emitting device 20.
  • the control terminal 122a of the driving sub-circuit 122 is connected to the first node N1
  • the first terminal 122b of the driving sub-circuit 122 is connected to the second node N2 and is configured to receive the first power supply voltage VDD
  • the second terminal 122c of the driving sub-circuit 122 is connected to the second node N2.
  • the third node N3 is connected.
  • the data writing sub-circuit 126 includes a control terminal 126a, a first terminal 126b and a second terminal 126c.
  • the control terminal 126a is configured to receive the first scan signal Ga1
  • the first terminal 126b is configured to receive the data signal Vd
  • the second terminal 126c is connected to the first terminal 122b (ie, the second node N2) of the driving sub-circuit 122.
  • the data writing sub-circuit 126 is configured to write the data signal Vd into the first terminal 122b of the driving sub-circuit 122 in response to the first scanning signal Ga1.
  • the first terminal 126b of the data writing sub-circuit 126 is connected to the data line 12 to receive the data signal Vd, and the control terminal 126a is connected to the gate line 11 as a scan line to receive the first scan signal Ga1.
  • the data writing sub-circuit 126 may be turned on in response to the first scan signal Ga1, so that the data signal may be written to the first end 122b (second node N2) of the driving sub-circuit 122,
  • the data signal is stored in the storage sub-circuit 127 so that, for example, during the light-emitting phase, a driving current for driving the light-emitting device 20 to emit light can be generated based on the data signal.
  • the compensation subcircuit 128 includes a control terminal 128a, a first terminal 128b and a second terminal 128c.
  • the control terminal 128a of the compensation subcircuit 128 is configured to receive the second scan signal Ga2.
  • the first terminal 128b and the second terminal 128c of the compensation subcircuit 128 The terminal 128c is electrically connected to the second terminal 122c and the control terminal 122a of the driver sub-circuit 122 respectively, and the compensation sub-circuit 128 is configured to respond to the second scan signal Ga2 to the driver sub-circuit 122.
  • Circuit 122 performs threshold compensation.
  • the first scanning signal Ga1 may be the same as the second scanning signal Ga2.
  • the first scanning signal Ga1 and the second scanning signal Ga2 may be connected to the same signal output terminal.
  • the first scan signal Ga1 and the second scan signal Ga2 may be transmitted through the same scan line.
  • the first scanning signal Ga1 may also be different from the second scanning signal Ga2.
  • the first scan signal Ga1 and the second scan signal Ga2 may be connected to different signal output terminals.
  • the first scan signal Ga1 and the second scan signal Ga2 may be transmitted through different scan lines respectively.
  • the storage subcircuit 127 includes a first terminal 127a and a second terminal 127b.
  • the first terminal 127a of the storage subcircuit is configured to receive the first power supply voltage VDD.
  • the second terminal 127b of the storage subcircuit is connected to the control terminal of the driving subcircuit. 122a electrical connection.
  • the storage sub-circuit 127 is electrically connected to the control terminal 122a and the first voltage terminal vdd of the driving sub-circuit 122, and is configured to store the data signal written by the data writing sub-circuit 126.
  • the compensation subcircuit 128 may be turned on in response to the second scan signal Ga2, so that the data signal written by the data writing subcircuit 126 may be stored in the storage subcircuit 127.
  • the compensation subcircuit 128 can electrically connect the control terminal 122a and the second terminal 122c of the driving subcircuit 122, so that information related to the threshold voltage of the driving subcircuit 122 can also be stored accordingly.
  • the stored data signal and the threshold voltage can be used to control the driving sub-circuit 122 during the light-emitting phase, for example, so that the output of the driving sub-circuit 122 is compensated.
  • the first lighting control sub-circuit 123 is connected to the first terminal 122b (second node N2) of the driving sub-circuit 122 and the first voltage terminal vdd, and is configured to change the first voltage terminal vdd in response to the first lighting control signal EM1.
  • the first power supply voltage VDD is applied to the first terminal 122b of the driving sub-circuit 122.
  • the first lighting control sub-circuit 123 is connected to the first lighting control terminal EM1, the first voltage terminal vdd and the second node N2.
  • the second lighting control sub-circuit 124 is connected to the second lighting control terminal EM2, the first terminal 134 of the light-emitting device 20 and the second terminal 122c of the driving sub-circuit 122, and is configured to cause the driving current in response to the second lighting control signal. can be applied to the light emitting device 20 .
  • the second light-emitting control sub-circuit 124 is turned on in response to the second light-emitting control signal EM2 provided by the second light-emitting control terminal EM2, so that the driving sub-circuit 122 can pass the second light-emitting control signal EM2.
  • the light control sub-circuit 124 is electrically connected to the light-emitting device 20, thereby driving the light-emitting device 20 to emit light under the control of the driving current; and in the non-light-emitting phase, the second light-emitting control sub-circuit 124 is turned off in response to the second light-emitting control signal EM2, thereby avoiding When current flows through the light-emitting device 20 to cause it to emit light, the contrast of the corresponding display device can be improved.
  • the second light-emitting control sub-circuit 124 can also be turned on in response to the second light-emitting control signal EM2, so that the driving sub-circuit 122 and the light-emitting device 20 can be reset in combination with the reset sub-circuit.
  • the second lighting control signal EM2 may be the same as the first lighting control signal EM1.
  • the second lighting control signal EM2 may be connected to the same signal output terminal as the first lighting control signal EM1.
  • the second lighting control signal EM2 may be The first lighting control signal EM1 is transmitted through the same lighting control line.
  • the second lighting control signal EM2 may be different from the first lighting control signal EM1.
  • the second lighting control signal EM2 and the first lighting control signal EM1 may be connected to different signal output terminals respectively.
  • the second lighting control signal EM2 and the first lighting control signal EM1 may be transmitted through different lighting control lines respectively.
  • the first reset sub-circuit 125 is connected to the first reset voltage terminal Vinit1 and the control terminal 122a (first node N1 ) of the driving sub-circuit 122 , and is configured to apply the first reset voltage Vinit1 in response to the first reset control signal Rst1 to the control terminal 122a of the driver sub-circuit 122.
  • the second reset sub-circuit 129 is connected to the second reset voltage terminal Vinit2 and the first terminal 134 (fourth node N4) of the light emitting device 20, and is configured to apply the second reset voltage Vinit2 in response to the second reset control signal Rst2. to the first end 134 of the light emitting device 20 .
  • the first reset sub-circuit 125 and the second reset sub-circuit 129 may be turned on in response to the first reset control signal Rst1 and the second reset control signal Rst2, respectively, so that the second reset voltage Vinit2 may be applied to the first node respectively.
  • N1 and the first reset voltage Vinit1 is applied to the first terminal 134 of the light-emitting device 20, so that the driving sub-circuit 122, the compensation sub-circuit 128 and the light-emitting device 20 can be reset to eliminate the influence of the previous light-emitting stage.
  • the second reset control signal Rst2 of each row of sub-pixels may be the same signal as the first scanning signal Ga1 of the row of sub-pixels, and both may be transmitted through the same gate line (such as the reset control line 220b in FIG. 3A).
  • the first reset control signal Rst1 of each row of sub-pixels can be the same as the first scan signal Ga1 of the previous row of sub-pixels, and both can pass through the same gate line (for example, the reset control signal in FIG. 3A Line 220a) transmission.
  • the light-emitting device 20 includes a first end 134 and a second end 135 .
  • the first end 134 of the light-emitting device 20 is configured to be connected to the second end 122 c of the driving sub-circuit 122 .
  • the second end 135 of the light-emitting device 20 Configured to be connected to the second voltage terminal VSS.
  • the first end 134 of the light emitting device 20 may be connected to the fourth node N4 through the second light emitting control sub-circuit 124 .
  • Embodiments of the invention include, but are not limited to, this scenario.
  • the first node N1, the second node N2, the third node N3 and the fourth node N4 do not necessarily represent actual existing components, but represent relevant circuit connections in the circuit diagram. meeting point.
  • the symbol Vd can represent both the data signal terminal and the level of the data signal.
  • the symbols Ga1 and Ga2 can represent both the first scanning signal and the second scanning signal.
  • the signal can also represent the first scanning signal terminal and the second scanning signal terminal.
  • the symbol Rst1 can represent both the first reset control terminal and the first reset control signal.
  • the symbol Rst2 can represent both the second reset control terminal and the third reset control terminal. Two reset control signals.
  • the symbols Vinit1 and Vinit2 can represent both the first reset voltage terminal and the second reset voltage terminal and the first reset voltage and the second reset voltage.
  • the symbol VDD can represent both the first power supply voltage and the first reset voltage.
  • Power cord, the symbol VSS can represent both public power voltage and public power line. The following embodiments are the same and will not be described again.
  • FIG. 2B is a circuit diagram of a specific implementation example of the pixel circuit shown in FIG. 2A.
  • the pixel circuit includes first to seventh transistors T1, T2, T3, T4, T5, T6, T7 and a storage capacitor Cst.
  • the third transistor T3 is used as a driving transistor
  • the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor are used as switching transistors.
  • the driving subcircuit 122 may be implemented as a third transistor T3.
  • the gate electrode of the third transistor T3 serves as the control terminal 122a of the driving sub-circuit 122 and is connected to the first node N1; the first electrode of the third transistor T3 serves as the first terminal 122b of the driving sub-circuit 122 and is connected to the second node N2;
  • the second pole of the third transistor T3 serves as the second terminal 122c of the driving subcircuit 122 and is connected to the third node N3.
  • the data writing sub-circuit 126 may be implemented as a fourth transistor T4.
  • the gate T4g of the fourth transistor T4 is connected to the first scan line (first scan signal terminal Ga1) to receive For the first scan signal, the first pole T4s of the fourth transistor T4 is connected to the data line (data signal terminal Vd) to receive the data signal, and the second pole T4d of the fourth transistor T4 is connected to the first terminal 122b (th) of the driving subcircuit 122. Two nodes N2) are connected.
  • the compensation subcircuit 128 may be implemented as a second transistor T2.
  • the gate T2g, the first pole T2s and the second pole T2d of the second transistor T2 serve as the control terminal 128a, the first terminal 128b and the second terminal 128c of the compensation sub-circuit respectively.
  • the gate electrode of the second transistor T2 is configured to be connected to the second scan line (second scan signal terminal Ga2) to receive the second scan signal, the first electrode T2s of the second transistor T2 and the second electrode T3d of the third transistor T3 ( The third node N3) is connected, and the second electrode T3d of the second transistor T2 and the gate electrode T1g (the first node N1) of the third transistor T3 are electrically connected.
  • the storage sub-circuit 127 may be implemented as a storage capacitor Cst.
  • the storage capacitor Cst includes a first plate Cst1 and a second plate Cst2.
  • the first plate Cst2 is electrically connected to the first voltage terminal vdd.
  • the second plate Cst1 is electrically connected to the gate T1g (first node N1) of the third transistor T3.
  • the first lighting control sub-circuit 123 may be implemented as a fifth transistor T5.
  • the fifth transistor T5 is the first light emitting control transistor.
  • the gate T5g of the fifth transistor T5 is connected to the first light-emitting control line (first light-emitting control terminal EM1) to receive the first light-emitting control signal, and the first pole T5s of the fifth transistor T5 is connected to the first voltage terminal vdd to receive the first light-emitting control signal.
  • a power supply voltage VDD, the second pole T5d of the fifth transistor T5 is connected to the first terminal 122b (second node N2) of the driving sub-circuit 122.
  • the light-emitting device 20 is implemented as a light-emitting diode (LED), such as an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or an inorganic light-emitting diode, such as a micro light-emitting diode (Micro LED) or a micro OLED.
  • LED light-emitting diode
  • OLED organic light-emitting diode
  • QLED quantum dot light-emitting diode
  • an inorganic light-emitting diode such as a micro light-emitting diode (Micro LED) or a micro OLED.
  • the light-emitting device 20 may be a top-emitting structure, a bottom-emitting structure, or a double-sided emitting structure.
  • the light emitting device 20 can emit red light, green light, blue light or white light, etc.
  • the embodiments of the present invention do not limit the specific
  • the first end of the light-emitting device 20 includes a first display electrode 21 (as shown in FIG. 4A ), and the first display electrode is connected to the fourth node N4 and configured to be connected to the driving sub-circuit 122 through the second light-emitting control sub-circuit 124
  • the second end 122c of the light-emitting device 20 includes a second display electrode (for example, a cathode).
  • the second display electrode is configured to be connected to the common power supply voltage terminal VSS to receive the common power supply voltage VSS from the driving sub-circuit 122
  • the second terminal 122c flows into the circuit of the light-emitting device 20 to determine the brightness of the light-emitting device.
  • the common power supply voltage terminal VSS can be grounded, that is, VSS can be 0V.
  • the common supply voltage VSS may be a negative voltage.
  • the second lighting control sub-circuit 124 may be implemented as a sixth transistor T6.
  • the fifth transistor T6 is the second light emission control transistor.
  • the gate T6g of the sixth transistor T6 is connected to the second light-emitting control line (second light-emitting control terminal EM2) to receive the second light-emitting control signal, and the first electrode T6s of the sixth transistor T6 is connected to the second terminal 122c of the driving sub-circuit 122 (third node N3) is connected, and the second pole T6d of the sixth transistor T6 is connected to the first end 134 (the fourth node N4) of the light-emitting device 20.
  • the first reset sub-circuit 125 may be implemented as a first transistor T1
  • the second reset sub-circuit 129 may be implemented as a seventh transistor T7.
  • the gate T1g of the first transistor T1 is configured to be connected to the first reset control terminal Rst1 to receive the first reset control signal Rst1, and the first electrode T1s of the first transistor T1 is connected to the first reset voltage terminal Vinit1 to receive the first reset voltage. Vinit1, the second electrode T1d of the first transistor T1 is configured to be connected to the first node N1.
  • the gate T7g of the seventh transistor T7 is configured to be connected to the second reset control terminal Rst2 to receive the second reset control signal Rst2, and the first pole T7s of the seventh transistor T7 is connected to the second reset voltage terminal Vinit2 to receive the second reset voltage. Vinit2, the second pole T7d of the seventh transistor T7 is configured to be connected to the fourth node N4.
  • the transistors used in the embodiments of the present invention can be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • thin film transistors are used as examples for explanation.
  • the source and drain of the transistor used here can be symmetrical in structure, so there can be no structural difference between the source and drain.
  • one pole is directly described as the first pole and the other pole is the second pole.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages)
  • the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages)
  • the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages)
  • the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages) voltage).
  • the first to seventh transistors T1 - T7 are all P-type transistors, such as low-temperature polysilicon thin film transistors.
  • the embodiment of the present invention does not limit the type of transistor. When the type of transistor changes, the connection relationship in the circuit can be adjusted accordingly.
  • each frame image includes three stages, namely the initial transformation stage 1, data writing and compensation stage 2, and light emitting stage 3.
  • the first scan signal Ga1 is provided by the first scan signal line Scan(P)(n), and the second scan signal Ga2 is provided by the second scan signal line Scan(N)(n). ;
  • the first lighting control signal EM1 and the second lighting control signal EM2 are both provided by the lighting control line EM(P)(n).
  • FIG. 2C is a signal timing diagram of a driving method for a pixel circuit provided by at least one embodiment of the present invention. As shown in FIG. 2C , in this embodiment, the first scanning signal Ga1 and the second scanning signal Ga2 adopt the same signal, and the first luminescence control signal EM1 and the second luminescence control signal EM2 adopt the same signal.
  • the second reset control signal Rst2 and the first scanning signal Ga1/second scanning signal Ga2 can also use the same signal, that is, the second reset control signal Rst2 and the first scanning signal Ga1/second scanning signal Ga2 have the same waveform; That is, the first reset signal Rst1 of the sub-pixels in this row has the same waveform as the first scanning signal Ga1/second scanning signal Ga2 of the sub-pixels in the previous row, that is, the same signal is used.
  • different signals may be used as the first scanning signal Ga1, the second scanning signal Ga2, the first reset control signal Rst1, and the second reset control signal Rst2.
  • Different signals are used as the first lighting control signal EM1 and the second lighting control signal EM2 respectively.
  • the first reset control signal Rst1 is input to turn on the first transistor T1, and the first reset voltage Vinit1 is applied to the gate of the third transistor T3, thereby resetting the first node N1.
  • the first scan signal Ga1, the second scan signal Ga2 (i.e., the compensation scan signal) and the data signal Vd are input, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal Vd is generated by the fourth transistor.
  • T4 is written into the second node N2, and charges the first node N1 through the third transistor T3 and the second transistor T2, until the potential of the first node N1 changes to Vd+Vth, the third transistor T3 is turned off, and Vth is the third transistor.
  • Threshold voltage of T3 The potential of the first node N1 is stored and maintained in the storage capacitor Cst. That is to say, the voltage information with the data signal and the threshold voltage Vth is stored in the storage capacitor Cst for subsequent use in the light-emitting phase. display data and compensate the threshold voltage of the third transistor T3 itself.
  • the second reset control signal Rst2 may also be input to turn on the seventh transistor T7, and the second reset voltage Vinit2 is applied to the fourth node N4, thereby resetting the fourth node N4.
  • the fourth node N4 may be reset in the initialization phase 1.
  • the first reset control signal Rst1 and the second reset control signal Rst2 may be the same.
  • the first light emitting control signal EM1 and the second light emitting control signal EM2 are input to turn on the fifth transistor T5, the sixth transistor T6 and the third transistor T3.
  • the sixth transistor T6 applies the driving current to the OLED to cause it to emit light. .
  • the value of the driving current Id flowing through the OLED can be obtained according to the following formula:
  • Vth represents the threshold voltage of the third transistor T3
  • VGS represents the voltage between the gate and the source (here, the first electrode) of the third transistor T3
  • K is a value related to the third transistor T3 itself. constant value. It can be seen from the above calculation formula of Id that the driving current Id flowing through the OLED is no longer related to the threshold voltage Vth of the third transistor T3. This can realize compensation for the pixel circuit and solve the problem of the driving transistor (in the present invention).
  • the third transistor T3) has the problem of threshold voltage drift caused by the process and long-term operation, and its influence on the driving current Id can be eliminated, thereby improving the display effect of the display device using it.
  • 3A is a schematic plan view of a stack of a first semiconductor layer and a first conductive layer of a sub-pixel of a display substrate according to an embodiment of the present invention.
  • 3B is a schematic plan view of a second conductive layer and a second semiconductor layer stack of a sub-pixel of a display substrate according to an embodiment of the present invention.
  • 3C is a schematic plan view of a first semiconductor layer, a first conductive layer, a second conductive layer and a second semiconductor layer stack of a sub-pixel of a display substrate according to an embodiment of the present invention.
  • 3D is a schematic plan view of a second conductive layer and a third conductive layer stack of a sub-pixel of a display substrate according to an embodiment of the present invention.
  • 3E is a schematic plan view of a first semiconductor layer, a first conductive layer, a second conductive layer, and a stack of a second semiconductor layer and a third conductive layer of a sub-pixel of a display substrate according to an embodiment of the present invention.
  • 3F is a schematic plan view of a stack of a first interlayer insulating layer and a fourth conductive layer of a sub-pixel of a display substrate according to an embodiment of the present invention.
  • 3G shows the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer, the third conductive layer stack and the first interlayer insulating layer of a sub-pixel of a display substrate according to an embodiment of the present invention. and a plan view of the fourth conductive layer stack.
  • 3H is a schematic plan view of a first flat layer and a fifth conductive layer stack of a sub-pixel of a display substrate according to an embodiment of the present invention.
  • 3I shows the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer, the third conductive layer stack and the first interlayer insulating layer of a sub-pixel of a display substrate according to an embodiment of the present invention.
  • Figure 3J is a diagram of the present invention The embodiment provides a schematic plan view of a stack of a second flat layer, a first display electrode and a pixel defining layer of a sub-pixel of a display substrate.
  • 3K is a schematic plan view of a sub-pixel of a display substrate according to an embodiment of the present invention, that is, a stack of the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer and the third conductive layer of the sub-pixel. , a plan view of a stack of the first interlayer insulating layer, the fourth conductive layer, the first planarization layer, the fifth conductive layer, the second planarization layer, the first display electrode and the pixel definition layer.
  • FIG. 4A is a schematic cross-sectional view along the active layer direction of the third transistor and the sixth transistor in FIG. 3K .
  • Figure 4B is a schematic structural diagram of a display substrate.
  • the display substrate 10 includes a base substrate 200, a first signal line provided on the base substrate 200 that extends along the second direction D2 as a whole, and a first signal line that extends along the second direction D2 as a whole.
  • the intersecting second signal lines extend in the first direction D1; for example, the first signal line intersects with the second signal line to define a plurality of sub-pixels 100. It should be noted that the boundary of each of the plurality of sub-pixels is not necessarily the first signal line and the second signal line.
  • the first signal line and the second signal line intersect to define a sub-pixel.
  • a plurality of sub-pixels refers to a plurality of sub-pixels.
  • the arrangement of the pixels is consistent with the arrangement of multiple areas defined by the intersection of the first signal line and the second signal line, that is, the plurality of sub-pixels are consistent with the arrangement of multiple areas defined by the intersection of the first signal line and the second signal line.
  • the first signal line is a gate line serving as a scanning signal line
  • the second signal line is a data line
  • the first signal line is a data line
  • the second signal line is a gate line serving as a scanning signal line. Wire.
  • “extends generally along the second direction” means that it generally extends along the second direction, and at least the overall extension trend is to extend along the second direction.
  • the first signal line as an example, for example, in some examples, the first signal line that extends overall in the second direction may have a certain curved part, for example, may include a wavy part; or, in some examples, , the edge extending along the second direction of the first signal line that extends overall along the second direction may not be a smooth line, for example, the edge of the first signal line may have burrs or jagged edges.
  • the first signal line satisfies a bar shape extending along the second direction as a whole.
  • the data line extends as a whole along the first direction.
  • the first connection structure described below extends as a whole as along the first direction.
  • At least part of the plurality of sub-pixels each includes a pixel circuit, and the pixel circuit includes the above-mentioned light-emitting device 20 as well as the driving transistor T1 and the data writing transistor T2.
  • the sub-pixels refer to sub-pixels that perform display functions, not dummy sub-pixels.
  • the pixel circuit also includes a first connection structure C1.
  • the first connection structure C1 is connected to the gate T3g of the driving transistor T3 and the first plate Cst1 of the storage capacitor Cst.
  • the data line Data and the first connection structure C1 extend as a whole along the first direction D1, and the data line Data includes an overlapping portion D0.
  • a connection structure C1 is at least partially opposite to the overlapping portion D0 of the data line Data, that is, the first connection structure C1 and the overlapping portion D0 of the data line Data are at least partially opposite to each other in the second direction D2, and the second direction D2 is parallel to the substrate.
  • the substrate 200 is perpendicular to the first direction D1; for example, the entire overlapping portion D0 and the first connection structure C1 are disposed opposite to each other in the second direction D2.
  • the overlapping portion D0 of the first connection structure C1 and the data line Data is insulated from each other.
  • the overlapping portion D0 of the first connection structure C1 and the data line Data respectively constitute the first plate and the second plate of the parasitic capacitance Cgd; the parasitic capacitance Cgd
  • the ratio of the capacitance value to the capacitance value of the storage capacitor Cst is greater than 0.001 and less than 0.01.
  • the size S (Pixel Pitch) of a sub-pixel 100 in the second direction D2 is greater than 50 ⁇ m, and the capacitance value of the parasitic capacitance Cgd
  • the ratio to the capacitance value of the storage capacitor Cst is less than 0.005. It has been found through experiments that in a display substrate with sub-pixels having this size design, the ratio of the capacitance value of the parasitic capacitance Cgd to the capacitance value of the storage capacitor Cst is less than 0.005, which can significantly reduce the jump voltage on the data line Data during the display process.
  • the size S of one sub-pixel 100 in the second direction D2 is less than or equal to 68 ⁇ m, and the ratio of the capacitance value of the parasitic capacitor Cgd to the capacitance value of the storage capacitor Cst is greater than or equal to 0.003. It has been found through experiments that in a display substrate with sub-pixels having this size design, the ratio of the capacitance value of the parasitic capacitance Cgd to the capacitance value of the storage capacitor Cst can be greater than or equal to 0.003, and in this case, the display process can be significantly reduced.
  • the impact of the jump voltage on the driving voltage of the driving transistor T3 is taken into account to achieve high PPI and obtain better display effects. Especially in large-size display substrates or display panels, such as display substrates or display panels larger than 55 inches, it is necessary to reduce the driving voltage of the driving transistor T3 caused by the jump voltage on the data line Data during the display process while achieving high PPI. The impact is particularly significant.
  • the size S of one sub-pixel 100 in the second direction D2 is less than 50 ⁇ m, and the ratio of the capacitance value of the parasitic capacitor Cgd to the capacitance value of the storage capacitor Cst is greater than 0.005 and Less than 0.006. It has been found through experiments that in a display substrate with sub-pixels designed with this size, the size of a single sub-pixel is smaller to achieve high PPI. In this case, the jump voltage on the data line Data generates a driving voltage for the driving transistor T3. The impact is greater.
  • the ratio of the capacitance value of the parasitic capacitance Cgd to the capacitance value of the storage capacitor Cst is greater than 0004 and less than 0.006, which can reduce the impact of the jump voltage on the data line Data on the driving voltage of the driving transistor T3 during the display process.
  • FIG. 5 is a schematic plan view of at least two adjacent sub-pixels of a display substrate according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram after removing the first power line VDD based on FIG. 5 .
  • the plurality of sub-pixels 100 include a first sub-pixel P1 and a second sub-pixel P2 adjacent to each other in the second direction D2.
  • the first connection structure C1 includes a first part C11 extending along the first direction D1 and a second part C12 extending along the second direction. The second part C12 and the first part C11 is connected.
  • the edge of the first part C11 close to the overlapping part D0 of the data line Data is the first edge 1a.
  • the first part C11 also has a second edge 1b with the overlapping part D0 far away from the data line Data.
  • the overlapping part D0 of the data line Data is the third edge 1c.
  • the distance of the orthographic projection of the third edge 1c of the overlapping portion D0 of Data on the base substrate 200 is the first distance L1, that is, the distance 6 in FIG. 4A and FIG. 6.
  • the first connection structure C1 of the first sub-pixel P1 The distance from the first edge 1a to the third edge 1c of the overlapping portion D0 of the data line Data of the first sub-pixel P1 is the second distance L2, which is the distance 7 in Figure 6.
  • the first distance L1 and the second distance L2 The ratio is greater than 14. In this way, on the one hand, it can be guaranteed It is proved that the first connection structure C1 of this sub-pixel is separated from the data line Data of the adjacent sub-pixel by a large enough distance, and the distance L1 is greater than the distance between the first connection structure C1 of this sub-pixel and the data line Data of this sub-pixel. 14 times that of L2.
  • the above definitions of the first distance L1 and the second distance L2 are applicable to any sub-pixel in the pixel array of the display substrate. Therefore, the following description of the first distance L1 in the second sub-pixel P2 is also the same.
  • the size S of one sub-pixel 100 in the second direction D2 is less than 50 ⁇ m, and the ratio of the first distance L1 to the second distance L2 is greater than 14 and less than 15.5.
  • the ratio of the first distance L1 to the second distance L2 is greater than 14 and less than 15.5, which can achieve high PPI while achieving small parasitic capacitance Cgd.
  • the size S of one sub-pixel 100 in the second direction D2 is greater than 50 ⁇ m, for example, 50 ⁇ m ⁇ size S ⁇ 68 ⁇ m, and the ratio of the first distance L1 to the second distance L2 is greater than 15.5.
  • the ratio of the first distance L1 to the second distance L2 is greater than 14 and less than 15.5, which can achieve high PPI while achieving small parasitic capacitance Cgd.
  • the jump voltage on the data line Data has a particularly significant impact on the driving voltage of the driving transistor T3.
  • the first connection structure C1 of the first sub-pixel P1 is located on the data line Data1 of the first sub-pixel P1 and the data line of the second sub-pixel P2 in the second direction D2. between Data1.
  • the data line Data2 located on the left side of the data line Data1 of the first sub-pixel P1 and adjacent to it is on the left side of the first sub-pixel P1 and opposite to the first sub-pixel P1.
  • the data line of the adjacent sub-pixel (not shown in full) is located on the right side of the data line Data1 of the second sub-pixel P2 and the data line Data2 adjacent to it is on the right side of the second sub-pixel P2 and the second sub-pixel P2.
  • the distance between the orthographic projection of the first connection structure C1 of the first sub-pixel P1 on the base substrate 200 and the orthographic projection of the data line Data of the first sub-pixel P1 on the base substrate 200 is less than one sub-pixel 100
  • the size in the second direction D2 and the orthogonal projection of the first connection structure C1 of the first sub-pixel P1 on the base substrate 200 is the same as the orthogonal projection of the data line Data of the second sub-pixel P2 on the base substrate 200.
  • the distance between projections is greater than the size of one sub-pixel 100 in the second direction D2.
  • At least the first connection structure C1 and the data line Data of the first sub-pixel P1 and the second sub-pixel P2 adjacent to each other are symmetrical (mirror symmetric) with respect to the symmetry axis extending along the first direction.
  • it can better satisfy the requirement that the ratio of the first distance L1 to the second distance L2 be greater than 14, that is, the relationship between the data line Data of the second sub-pixel P1 and the first connection structure C1 of the first sub-pixel P1 can be increased as much as possible.
  • the orthographic projection of the first connection structure C1 of the first sub-pixel P1 on the base substrate 200 is the same as the orthographic projection of the data line Data of the first sub-pixel P1 on the base substrate 200 .
  • the distance between them is less than the size S of one sub-pixel in the second direction D2, and the orthographic projection of the first connection structure C1 of the first sub-pixel P1 on the base substrate 200 is different from the data line Data of the second sub-pixel P2.
  • the distance between orthographic projections on the base substrate 200 is smaller than the size S of one sub-pixel 100 in the second direction D2.
  • the first connection structure C1 and the data line Data of the first sub-pixel P1 and the second sub-pixel P2 adjacent to each other are asymmetric (non-mirror symmetric) with respect to the axis extending in the first direction.
  • the embodiment of the present invention does not limit the specific positions of each structure of the pixel circuit, as long as the above-mentioned relationship between the first distance L1 and the second distance L2 is satisfied.
  • the edge of the overlapping portion D0 of the gate T3g of the driving transistor T3 of the first subpixel P1 close to the data line Data of the second subpixel P2 is the fourth edge 1d;
  • the first The distance from the second edge 1b of the sub-pixel P1 to the third edge 1c of the second sub-pixel P2 is equal to the distance from the second edge 1b of the first sub-pixel P1 to the fourth edge 1d of the first sub-pixel P1 and the first sub-pixel The sum of the distances from the fourth edge 1d of P1 to the third edge 1c of the second sub-pixel P2.
  • the first connection structure C1 and the data line Data are arranged in different layers.
  • the orthographic projection of the first connection structure C1 on the base substrate 200 is the orthographic projection of the overlapping portion D0 of the data line Data on the base substrate 200 .
  • No overlap or, in some other embodiments, the first connection structure C1 and the data line Data are arranged in different layers, and the overlapping portion D0 of the orthographic projection of the first connection structure C1 on the base substrate 200 and the data line Data is on the base substrate 200
  • Figure 4C is a schematic diagram of a flat plate capacitor with electrodes facing directly;
  • Figure 4D is a schematic diagram of a flat plate capacitor with oblique electrodes.
  • facing the plate capacitor means that the two plates of the plate capacitor, such as electrode 1 and electrode 2, are facing each other, that is, the surfaces of electrode 1 and electrode 2 facing each other are parallel to each other and electrode 1 and electrode 2 are in the same direction.
  • the orthographic projections of the two parallel faces facing each other overlap.
  • the electrode tilted plate capacitor refers to the two plates of the plate capacitor, such as electrode 1 and electrode 2.
  • the surfaces facing each other are parallel to each other, and electrode 1 and electrode 2 are on surfaces parallel to the surfaces facing each other.
  • the orthographic projections partially overlap or do not overlap.
  • the capacitance value of the parasitic capacitance involved in the protection scope of the claims of the present invention shall be subject to the calculation method disclosed later in the specification.
  • A represents the surface area of the two electrodes 1 and 2 overlapping each other, and d represents the distance traveled by the electric power line.
  • C gd represents the capacitance value of the parasitic capacitance Cgd, and C gd satisfies formula (2):
  • ⁇ PI represents the dielectric constant of the medium between the overlapping portion D0 of the data line Data and the first connection structure C1 .
  • A represents the equivalent overlapping area of the overlapping portion D0 of the data line Data and the first connection structure C1.
  • the equivalent overlap area is the area of the surface where electrode 1 and electrode 2 are opposite to each other and are evenly distributed with electric power lines; for example, in the overlapping portion D0 of the data line Data on the lining
  • the orthographic projection on the base substrate 200 and the orthographic projection of the first connection structure C1 on the base substrate 200 do not overlap or at least partially overlap
  • the overlapping portion D0 of the data line Data and the first connection structure C1 are respectively equivalent to those in FIG. 4D of electrode 1 and electrode 2.
  • d represents the distance traveled by the power line.
  • W sd1 represents the width of the first connection structure C1 in the second direction D2, that is, the distance 5.
  • w sd1 represents the length of the first connection structure C1 in the first direction D1.
  • t PLN1 represents the distance between the first connection structure C1 and the data line Data in a direction perpendicular to the base substrate 200 .
  • d sd1 represents the distance between the first edge 1a of the first connection structure C1 and the third edge 1c of the data line Data in one sub-pixel, that is, the second distance L2.
  • the following uses an example to calculate the parasitic capacitance Cgd formed by the overlapping portion D0 of the adjacent first connection structure C1 and the data line Data in a sub-pixel.
  • Other plate capacitors can refer to this calculation method.
  • the first edge 1a of the first connection structure C1 representing the first sub-pixel P1 is on the base substrate 200
  • the distance of the orthographic projection of the third edge 1c of the overlapping portion D0 of the data line Data1 of the second sub-pixel P2 on the substrate 200 that is, the second distance L2.
  • ⁇ PI 4.0
  • t PLN1 1.24 ⁇ m
  • W sd1 5.4 ⁇ m
  • w sd1 5.4 ⁇ m.
  • the first connection structure C1 and the data line Data of the first sub-pixel P1 and the second sub-pixel P2 adjacent to each other shown in FIG. 5 are mirror symmetrical with respect to the symmetry axis extending along the first direction
  • first connection structure C1 and the data line Data of the first sub-pixel P1 and the second sub-pixel P2 adjacent to each other are non-mirror symmetrical
  • first connection structure C1 of one sub-pixel is in the third
  • a data line Data is set up on both sides of the two directions D2 at positions that are substantially equal to the distance from the first connection structure C1.
  • the ratio of the capacitance value of the parasitic capacitor Cgd to the capacitance value of the storage capacitor Cst in the mirror design with the same other conditions mentioned above is smaller.
  • the jump voltage on the data line Data of the display panel The impact on the driving voltage of the driving transistor T3 is small, and the display effect is better.
  • 1 Represents the spacing between the data line Data1 of the first sub-pixel P1 and the data line Data2 of the sub-pixel adjacent to the first sub-pixel P1 and asymmetrical to the first sub-pixel P1 (the first sub-pixels P1 adjacent to each other and the second sub-pixel P2 form a repeating unit.
  • the first sub-pixel P1 is far away from the second sub-image.
  • ⁇ PI 4.0
  • t PLN1 1.05 ⁇ m
  • w sd1 4.75 ⁇ m.
  • the first connection structure C1 and the data line Data of the first sub-pixel P1 and the second sub-pixel P2 adjacent to each other shown in FIG. 5 are mirror symmetrical with respect to the symmetry axis extending along the first direction
  • first connection structure C1 and the data line Data of the first sub-pixel P1 and the second sub-pixel P2 adjacent to each other are non-mirror symmetrical
  • first connection structure C1 of one sub-pixel is in the third
  • a data line Data is set up on both sides of the two directions D2 at positions that are substantially equal to the distance from the first connection structure C1.
  • the ratio of the capacitance value of the parasitic capacitor Cgd to the capacitance value of the storage capacitor Cst in the mirror design with the same other conditions mentioned above is smaller.
  • the jump voltage on the data line Data of the display panel The impact on the driving voltage of the driving transistor T3 is small, and the display effect is better.
  • ⁇ PI 4.0
  • t PLN1 1.24 ⁇ m
  • W sd1 7.5 ⁇ m
  • w sd1 4.3 ⁇ m.
  • connection structure C1 and the data line Data are mirror symmetrical with respect to the symmetry axis extending along the first direction
  • the first connection structure C1 of one sub-pixel only forms a parasitic relationship with the data line Data located on one side of it in the second direction D2.
  • the ratio of values is equal to 0.003.
  • S is less than 68 ⁇ m, that is, the width of a single sub-pixel is small, in order to achieve high PPI, space limitations are greater. Therefore, the ratio of the capacitance value of the parasitic capacitance Cgd to the capacitance value of the storage capacitor Cst can be less than 0.003.
  • first connection structure C1 and the data line Data of the first sub-pixel P1 and the second sub-pixel P2 adjacent to each other are non-mirror symmetrical
  • first connection structure C1 of one sub-pixel is in the third
  • a data line Data is set up on both sides of the two directions D2 at positions that are substantially equal to the distance from the first connection structure C1.
  • the ratio of the capacitance value of the parasitic capacitor Cgd to the capacitance value of the storage capacitor Cst in the mirror design with the same other conditions mentioned above is smaller.
  • the jump voltage on the data line Data of the display panel The impact on the driving voltage of the driving transistor T3 is small, and the display effect is better.
  • ⁇ PI 4.0
  • t PLN1 1.36 ⁇ m
  • W sd1 6 ⁇ m
  • w sd1 9 ⁇ m.
  • first connection structure C1 and the data line Data of the first sub-pixel P1 and the second sub-pixel P2 adjacent to each other shown in FIG. 5 are mirror symmetrical with respect to the symmetry axis extending along the first direction, one The first connection structure C1 of the sub-pixel only forms a parasitic capacitance Cgd with the data line Data located on one side of it in the second direction D2.
  • S is less than 50 ⁇ m, that is, the width of a single sub-pixel is smaller, in order to achieve high PPI, space limitations are further increased. Therefore, it can be satisfied that the ratio of the capacitance value of the parasitic capacitance Cgd to the capacitance value of the storage capacitor Cst is less than 0.003.
  • first connection structure C1 and the data line Data of the first sub-pixel P1 and the second sub-pixel P2 adjacent to each other are non-mirror symmetrical
  • first connection structure C1 of one sub-pixel is in the third
  • a data line Data is set up on both sides of the two directions D2 at positions that are substantially equal to the distance from the first connection structure C1.
  • the ratio of the capacitance value of the parasitic capacitor Cgd to the capacitance value of the storage capacitor Cst in the mirror design with the same other conditions mentioned above is smaller.
  • the jump voltage on the data line Data of the display panel The impact on the driving voltage of the driving transistor T3 is small, and the display effect is better.
  • the first connection structure C1 and the data line Data are arranged in different layers as an example.
  • the first connection structure C1 may be arranged on the same layer as the data line Data, and the overlapping portion D0 of the first connection structure C1 and the data line Data is opposite to each other in the second direction D2.
  • the present invention is not limited to the first connection structure C1 and the data line Data being arranged in different layers, as long as the ratio of the first distance L1 to the second distance L2 is greater than 14.
  • FIG. 4E is another schematic cross-sectional view of a display substrate provided by an embodiment of the present invention.
  • the first plate Cst1 of the storage capacitor Cst has an upper surface T01 away from the base substrate 200 and a side surface S01 intersecting the upper surface T01.
  • the second plate Cst2 of the storage capacitor Cst includes a middle portion CM and an edge portion CP.
  • the orthographic projection of the middle part CM on the base substrate 200 at least partially coincides with the orthographic projection of the first plate Cst1 of the storage capacitor Cst on the base substrate 200, and the middle part CM includes the same as the first plate Cst1 of the storage capacitor Cst.
  • the upper surface T01 is opposite to the bottom surface B01; the edge portion CP at least partially surrounds the middle portion CM and is connected to the middle portion CM, and the edge portion CP includes a bottom surface B02 close to the base substrate 200 and an inner side S02 that intersects the bottom surface B02.
  • the inner side S02 and the side surface S01 of the first plate Cst1 of the storage capacitor Cst are opposite to each other, and the orthographic projection of the inner side S02 on the reference plane perpendicular to the substrate substrate 200 is equal to the third side surface S01 of the storage capacitor Cst opposite to the inner side S02.
  • the orthographic projection of the side surface S01 of one plate Cst1 on the reference plane at least partially overlaps; between the inner side S02 of the edge portion CP and the side surface of the first plate Cst1 of the storage capacitor Cst opposite to the inner side S02,
  • the distance S1 is smaller than the distance S2 between the bottom surface of the middle part CM and the upper surface of the first plate Cst1 of the storage capacitor Cst, so that the limited space can be used to achieve a larger capacitance value of the storage capacitor Cst and improve the storage capacitance Cst.
  • the charge storage capability is also conducive to reducing the ratio of the parasitic capacitance Cgd formed by the overlapping portion D0 of the first connection structure C1 and the data line Data to the storage capacitance Cs, reducing the impact of the parasitic capacitance Cgd on the display effect, and improving the display effect.
  • the display substrate 10 includes a first semiconductor layer Active1, a first conductive layer Gate1, a second conductive layer, a first semiconductor layer Active1, a first conductive layer Gate1, and a first conductive layer Gate1 disposed on the base substrate 200 and arranged sequentially in a direction away from the base substrate 200.
  • the first signal line includes a first scanning signal line Scan(P)(n), a light emitting control line EM(P)(n) and a second reset scanning signal line Scan(P)(n+1).
  • the first scan signal line Scan(P)(n), the light emission control line EM(P)(n) and the second reset scan signal line Scan(P)(n+1) are located on the first conductive layer Gate1, and are generally along the second direction D2 extend.
  • the driving transistor T3 includes a gate T3g.
  • the gate T3g of the driving transistor T3 is also located on the first conductive layer Gate1.
  • the gate T3g of the driving transistor T3 and the first plate Cst1 of the capacitor are a continuous integrated structure.
  • the third A scanning signal line Scan(P)(n) a light emitting control line EM(P)(n) and a second reset scanning signal line Scan(P)(n+1)
  • the gate T3g of the driving transistor T3 and the storage capacitor Cst
  • the first plate Cst1 is set on the same layer.
  • the portion of the first scanning signal line Scan(P)(n) that overlaps with the first semiconductor layer Active1 constitutes the gate electrode T4g of the fourth transistor T4; the portion of the light emission control line EM(P)(n) that overlaps with the first semiconductor layer Active1
  • the two overlapping parts respectively constitute the gate electrode T5g of the fifth transistor T5 and the gate electrode T6g of the sixth transistor T6.
  • the fifth transistor T5 and the sixth transistor T6 serve as light-emitting control transistors, and the fifth transistor T5 serves as the first light-emitting control transistor.
  • the sixth transistor T6 is the second light emitting control transistor; the portion of the second reset scanning signal line Scan(P)(n+1) that overlaps the first semiconductor layer Active1 constitutes the gate T7g of the seventh transistor T7, and the seventh transistor T7 Transistor T7 serves as the second reset transistor.
  • the first semiconductor layer Active1 includes the active layer A3 of the driving transistor T3, the active layer A4 of the fourth transistor T4, the active layer A5 of the fifth transistor T5, the active layer A6 of the sixth transistor T6, and the seventh transistor. Active layer A7 of T7. Therefore, the gate T3g of the driving transistor T3 and the first plate Cst1 of the storage capacitor Cst are located on the side of the active layer A3 of the driving transistor T3 away from the base substrate 200 .
  • the third transistor T3 serves as the driving transistor T3 of the pixel circuit
  • the fourth transistor T4 serves as the data writing transistor T4 of the pixel circuit.
  • the driving transistor T3 is configured to control the light emitting device 20 to emit light
  • the data line Data is connected to the first electrode of the data writing transistor T4 and is configured to provide a data signal to the data writing transistor T4.
  • the data writing transistor T4 is configured to respond to the data applied to the data writing transistor T4.
  • the first scan signal is written to the gate of the transistor T4 and the data signal Vd is written to the gate T3g of the driving transistor T3; for example, the data write transistor T2 is configured to transmit the data signal Vd to By driving the transistor T1, the first scanning signal Ga1 is transmitted on the first scanning signal line Scan(P)(n), and the data signal Vd is transmitted on the second signal line.
  • Data, Data1 and Data2 in this application are used to refer to data lines in different embodiments or different sub-pixels. For details, please refer to the corresponding drawings.
  • the first signal line also includes a second scanning signal line Scan(N)(n) and a first reset scanning signal line Scan(N)(n-1).
  • the second scanning signal line Scan(N)(n) and the first reset scanning signal line Scan(N)(n-1) are located on the second conductive layer Gate2.
  • Second scanning signal line Scan(N)(n) The portion overlapping with the second semiconductor layer Active2 constitutes the gate T2g of the second transistor T2, and the second transistor T2 serves as a compensation transistor; the first reset scanning signal line Scan(N)(n-1) and the second semiconductor layer
  • the overlapping portion of Active2 forms the gate T1g of the first transistor T1, and the first transistor T1 serves as the first reset transistor.
  • the second semiconductor layer Active2 includes the active layer A1 of the first transistor T1 and the active layer A2 of the second transistor T2.
  • the active layers A1 to A7 of the first to seventh transistors mentioned here refer to the portions of the semiconductor layers used to form the first to seventh transistors that overlap with the gate electrodes of the respective transistors.
  • the second scanning signal line Scan(N)(n) serves as the compensation scanning signal line.
  • the second scanning signal line Scan(N)(n) is configured to apply the second scanning signal Ga2 (ie, the compensation scanning signal) to the gate T2g of the compensation transistor T2. signal), the compensation transistor T2 is configured to perform threshold compensation on the driving transistor T3 in response to the second scan signal Ga2.
  • the display substrate 10 further includes a first reset signal line Vini_N1.
  • the first reset signal line Vini_N1 is located on the second conductive layer Gate2.
  • the first reset scan signal line Scan(N)(n-1) is configured to provide the first reset scan signal, that is, the first reset control signal Rst1, to the gate T1g of the first reset transistor T1.
  • the electrode T1s is electrically connected to the gate electrode T3g of the driving transistor T3, and the second electrode T1d of the first reset transistor T1 is configured to be electrically connected to the first reset signal line Vini_N1 to receive the first reset signal such as the first reset voltage Vinit1.
  • the reset transistor T1 is configured to write the first reset voltage Vinit1 to the gate T3g of the driving transistor T3 in response to the first reset control signal Rst1.
  • the display substrate 10 further includes a second reset signal line Vini_OLED.
  • the second reset signal line Vini_OLED is located on the fourth conductive layer SD1.
  • the second reset scan signal line Scan(P)(n+1) is configured to provide the second reset scan signal Rst2 to the gate T7g of the second reset transistor T7, and the first electrode T7s of the second reset transistor T7 is connected to the first electrode T7s of the light emitting device 20.
  • the first display electrode 21 is electrically connected, and the second pole T7d of the second reset transistor T7 is configured to be electrically connected to the second reset signal line Vini_OLED to receive a second reset signal such as the second reset voltage Vinit2.
  • the second reset transistor T7 is configured as The second reset signal is written into the first display electrode 21 of the light emitting device 20 in response to the second reset scan signal Rst2.
  • the active layer A2 of the compensation transistor T2 and the active layer A1 of the first reset transistor T1 form an integrated structure AL1, and the integrated structure AL1 extends along the first direction D1. Therefore, it is also possible to Say the active layer A1 of the first reset transistor T1 extends along the first direction D1, Or the active layer A2 of the compensation transistor T2 extends along the first direction D1.
  • the active layer A1 of the first reset transistor T1 extends along the first direction D1
  • the active layer A2 of the compensation transistor T2 extends along the first direction D1.
  • FIG. 3C there is no overlap between the orthographic projection of the first semiconductor layer Active1 on the base substrate 200 and the orthographic projection of the second semiconductor layer Active2 on the base substrate 200 , so that respectively based on the first semiconductor layer Active1 The transistors formed with the second semiconductor layer Active2 will not interfere with each other.
  • the material of the first semiconductor layer Active1 is different from the material of the second semiconductor layer Active2.
  • the material of the first semiconductor layer Active1 includes but is not limited to silicon-based materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.).
  • the material of the first semiconductor layer Active1 is low-temperature polysilicon (LTPS).
  • the material of the second semiconductor layer Active2 is an oxide semiconductor, such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), AZO, IZTO, etc.
  • IGZO indium gallium zinc oxide
  • ZnO zinc oxide
  • AZO AZO
  • IZTO IZTO
  • the types of materials of the first semiconductor layer Active1 and the types of materials of the second semiconductor layer Active2 are not limited to the types listed above, and the embodiments of the present invention are not limited thereto.
  • the active layer located in the first semiconductor layer Active1 and the active layer located in the second semiconductor layer Active2 are made of different materials and are arranged in different layers.
  • the active layer A1 of the first reset transistor T1 and the active layer A1 of the driving transistor T3 are different.
  • the materials of layer A3 are different and arranged in different layers.
  • the second reset transistor T7 is a P-type transistor using LTPS material to make the active layer. Because the P-type transistor using LTPS material to make the active layer has higher mobility and more stable source voltage, it is suitable for driving organic light-emitting diodes such as OLED.
  • the first reset transistor T1 and the compensation transistor T2 that reset the driving transistor T3 are N-type transistors using oxide semiconductor materials to make the active layer, because N-type transistors using oxide semiconductor materials to make the active layer have lower The leakage current can better maintain the voltage stability of the driving transistor T3 and the storage capacitor Cst.
  • the type of each transistor of the pixel circuit and the material of the active layer are not limited to the above examples, and the embodiments of the present invention do not limit this.
  • the plurality of sub-pixels 100 include the third sub-pixel P3, the signal line Scan(N)(n+1) is the first reset scan signal line of the third sub-pixel P3, and the signal line Vini_N1' is the third
  • the first reset signal line of the sub-pixel P3, the third sub-pixel P3 and the second sub-pixel P2 are adjacent in the first direction D1.
  • the complete pixel circuit shown in FIGS. 3A-3K is the pixel circuit of the second sub-pixel P2, and also involves a part of the structure of the pixel circuit of the sub-pixel adjacent to the second sub-pixel P2, such as the third sub-pixel P3.
  • the second scanning signal line Scan(N)(n), the first reset scanning signal line Scan(N)(n-1), the first reset signal line Vini_N1, etc. in FIG. 3B all belong to the second sub-pixel P2.
  • the portion of the second reset signal line Vini_OLED located at one sub-pixel 100 includes a transverse portion VS1 and a first longitudinal portion VS2.
  • the transverse portion VS1 extends along the second direction D2 and has a second The first end and the second end opposite each other in the direction D2, the first longitudinal portion VS2 is connected to the first end of the transverse portion VS1 in the second direction D2 and extends along the first direction D1, and, as shown in FIG.
  • the lateral direction of the second reset signal line Vini_OLED of the second sub-pixel P2 The orthographic projection of part VS1 on the base substrate 200 at least partially overlaps with the orthographic projection of the first reset scanning signal line Scan(N)(n+1) of the third sub-pixel P3 on the base substrate 200.
  • the second sub-pixel The first vertical part VS2 of the second reset signal line Vini_OLED of P2 and the active layer of the first reset transistor of the third sub-pixel P3 are arranged at intervals in the second direction D2, that is, the first vertical part VS2 and the second semiconductor layer Active2
  • the integrated structure A31 composed of the active layer of the middle compensation transistor and the active layer of the first reset transistor is arranged at intervals in the second direction D2 (since the pixel circuit structure of each sub-pixel is a repeating unit, the third sub-pixel P3
  • the integrated molding structure A31 in the sub-pixel can refer to the position of the integrated molding structure AL in the sub-pixel as the second sub-pixel P2 located lower in FIG.
  • the first longitudinal portion VS2 extending in the direction D1 avoids the second semiconductor layer Active2, that is, there is no intersection between the orthographic projection of the first longitudinal portion VS2 on the base substrate 200 and the orthographic projection of the second semiconductor layer Active2 on the base substrate 200.
  • the on-state current and lower leakage current ensure that the voltage of the first node N1 connected to the gate of the driving transistor T3 and the storage capacitor Cst is more stable and less prone to leakage, so that the driving current of the driving transistor T3 is more stable and the light-emitting device
  • the luminous efficiency of 20 is more stable, and the display quality of the display device using the display substrate is improved.
  • the characteristic "the orthographic projection of the lateral portion VS1 of the second reset signal line Vini_OLED on the base substrate 200 and the first reset scanning signal line Scan(N)(n+1) of the third sub-pixel P3 on the base substrate 200 "The orthographic projection at least partially overlaps" can reduce the area occupied by the scanning signal lines and improve the aperture ratio of the display substrate. For example, as shown in FIGS.
  • the first longitudinal portion VS2 of the second reset signal line Vini_OLED of the second sub-pixel P2 corresponds to the active layer of the third sub-pixel P3 for forming the first reset transistor T1
  • the integrated molding structures AL1 of A1 are arranged at intervals in the second direction D2, that is, the first longitudinal part VS2 of the second reset signal line Vini_OLED of the second sub-pixel P2 avoids the active part of the first reset transistor T1 of the third sub-pixel P3.
  • Layer A1 is designed to utilize the limited space to optimize the positional relationship between the pixel circuit structures of multiple sub-pixels, with a compact arrangement to achieve high PPI.
  • the planar pattern of the sub-portion of the second reset signal line Vini_OLED corresponding to one sub-pixel 100 is an inverted "ji" shape; the "ji"-shaped sub-portion can not only achieve the above-mentioned avoidance of the third
  • the effect of the second semiconductor layer Active2 and the "J"-shaped sub-part also includes a U-shaped groove, and the lateral part VS1 of the second reset signal line Vini_OLED serves as the bottom of the U-shaped groove, in the U-shaped groove
  • Other wiring can be set up to rationally utilize space and improve the compactness of the structure.
  • the sub-portion of the second reset signal line Vini_OLED located at one sub-pixel 100 also includes a second longitudinal portion VS3.
  • the second longitudinal portion VS3 and the second longitudinal portion VS1 of the transverse portion VS1 are in the second direction D2. terminals connected and extending along the first direction D1, the active layer A7 of the second reset transistor T7 is located between the first longitudinal portion VS2 and the second longitudinal portion VS3, and, in the same sub-pixel 100, in the second direction D2 , the distance between the first longitudinal part VS2 and the data line Data is greater than the distance between the second longitudinal part VS3 and the data line Data.
  • the distance between the active layer of the second reset transistor T7 of the third sub-pixel P3 and the first longitudinal part VS2 of the second reset signal line Vini_OLED of the second sub-pixel P2 is smaller than the distance of the second reset transistor T7 of the third sub-pixel P3.
  • the distance from the source layer to the second longitudinal portion VS3 of the second reset signal line Vini_OLED of the second sub-pixel P2 is such that the first longitudinal portion VS2 of the second reset signal line Vini_OLED avoids the second semiconductor layer Active2 while being reasonable. Make use of limited space to avoid overly dense arrangement of signal lines.
  • the second plate Cst2 of the storage capacitor Cst is located on the second conductive layer Gate2 and is in contact with the second scanning signal line Scan(N)(n) and the first reset scanning signal line Scan(N)(n-1). )Same layer settings.
  • the second scanning signal line Scan(N)(n) is the compensation scanning signal line. Therefore, the second plate Cst2 of the storage capacitor Cst is located on the side away from the base substrate 200 of the gate electrode T3g of the driving transistor T3 and the first plate Cst1 of the storage capacitor Cst, compensating the scanning signal line and the third plate of the storage capacitor Cst.
  • the diode plate Cst2 is arranged on the same layer, and the first reset signal line Vini_N1 is arranged on the same layer as the second plate Cst2 of the storage capacitor Cst; the active layer A2 of the compensation transistor T2 is located on the second semiconductor layer Active2, so that the second electrode of the storage capacitor Cst The side of the electrode plate Cst2 away from the base substrate 200 .
  • the second reset signal line Vini_OLED is located on the fourth conductive layer SD1. Therefore, the second reset signal line Vini_OLED is located away from the active layer A2 of the compensation transistor T2. one side of the substrate 200 .
  • FIG. 7A is a schematic cross-sectional view from a first perspective along the active layer direction of the fourth transistor, the third transistor, the second transistor, and the first transistor in FIG. 3K .
  • FIG. 7B is a schematic cross-sectional view from a second perspective along the active layer direction of the fourth transistor, the third transistor, the second transistor, and the first transistor in FIG. 3K .
  • the gate electrode T2g of the compensation transistor T2 and the gate electrode T1g of the first reset transistor T1 are both double-gate structures.
  • the gate electrode T2g of the compensation transistor T2 includes a first gate electrode T2g1 and a second gate electrode T2g1.
  • the gate T2g2 and the gate T1g of the first reset transistor T1 include a first gate T1g1 and a second gate T1g2; the orthographic projection of the first gate T2g1 of the compensation transistor T2 on the substrate 200 is the same as the first gate T1g of the compensation transistor T2.
  • the orthographic projection of the two gates T2g2 on the substrate 200 coincides with the orthographic projection of the first gate T1g1 of the first reset transistor T1 on the substrate 200 and the orthographic projection of the second gate T1g2 of the first reset transistor T1 on the substrate.
  • the orthographic projections on the substrate 200 coincide.
  • the first gate T1g1 of the first reset transistor T1 and the first gate T2g1 of the compensation transistor T2 are located on the second conductive layer Gate2, and the second gate T1g2 of the first reset transistor T1 And the second gate T2g2 of the compensation transistor T2 is located on the third conductive layer Gate3.
  • the active layer A2 of the compensation transistor T2 and the second semiconductor layer Active2 where the active layer A1 of the first reset transistor T1 is located are located between the second conductive layer Gate2 and the third between the conductive layer Gate3, so that the first gate T2g1 of the compensation transistor T2 and the first gate T1g1 of the first reset transistor T1 are arranged on the same layer as the second plate Cst2 of the storage capacitor Cst, and the second gate of the compensation transistor T2
  • the electrode T2g2 and the second gate electrode T1g2 of the first reset transistor T1 are located on the side of the active layer A2 of the compensation transistor T2 and the active layer A1 of the first reset transistor T1 away from the base substrate 200, and are located on the second reset signal.
  • the line Vini_OLED is close to the side of the base substrate 200 .
  • the third conductive layer Gate3 also includes a dual-gate reset scanning signal line Scan(N)(n-1)' and a dual-gate compensation scanning signal line Scan(N)(n)'.
  • the portion of the double-gate reset scanning signal line Scan(N)(n-1)' that overlaps the first semiconductor layer Active1 constitutes the second gate T1g2 of the first reset transistor T1; double-gate compensation scan
  • the portion of the signal line Scan(N)(n)′ that overlaps the first semiconductor layer Active1 constitutes the second gate T2g2 of the compensation transistor T2.
  • the orthographic projection of the double-gate reset scanning signal line Scan(N)(n-1)' on the main surface of the base substrate 200 is the same as the orthographic projection of the first reset scanning signal line Scan(N)(n-1) on the base substrate 200
  • the orthographic projections on the main surface basically coincide; the orthographic projection of the double-gate compensation scanning signal line Scan(N)(n)' on the main surface of the base substrate 200 It substantially coincides with the orthographic projection of the second scanning signal line Scan(N)(n), that is, the compensation scanning signal line, on the main surface of the base substrate 200 .
  • the first connection structure C1 is located on the fourth conductive layer SD1, so that the first connection structure C1 and the second reset signal line Vini_OLED are arranged on the same layer and are located far away from the second plate Cst2 of the storage capacitor Cst.
  • One side of the base substrate 200 One side of the base substrate 200 .
  • the data line Data is located on the side of the first connection structure C1 away from the base substrate 200 one side.
  • the data line Data may be located on a side of the first connection structure C1 close to the base substrate 200 .
  • the interlayer insulating layer ILD of the display substrate 10 includes a first sub-insulating layer GI1 located between the first semiconductor layer Active1 and the first conductive layer Gate1, and a first sub-insulating layer GI1 located between the first conductive layer Gate1 and the second conductive layer Gate2.
  • the fourth sub-insulating layer GI2 between the conductive layers Gate3 and the fifth sub-insulating layer ILD2 between the third conductive layer Gate3 and the fourth conductive layer SD1.
  • the display substrate 10 further includes a sixth sub-insulating layer, that is, a first planar layer PLN1 located between the fourth conductive layer SD1 and the fifth conductive layer SD2, and a second second flat layer PLN1 located between the fifth conductive layer SD2 and the first display electrode 21.
  • a sixth sub-insulating layer that is, a first planar layer PLN1 located between the fourth conductive layer SD1 and the fifth conductive layer SD2, and a second second flat layer PLN1 located between the fifth conductive layer SD2 and the first display electrode 21.
  • the first flat layer PLN1 provides a flat surface for the fifth conductive layer SD2 disposed above it, facilitates the pattern design of the fifth insulating layer SD2, reduces the manufacturing difficulty of the fifth insulating layer SD2, and improves the yield.
  • the second flat layer PLN2 provides a flat surface for the first display electrode 21 disposed above it, facilitates the pattern design of the first display electrode 21 , reduces the manufacturing difficulty of the
  • the display substrate 10 further includes a pixel definition layer PDL.
  • the opening of the pixel definition layer PDL exposes a portion of the first display electrode of each sub-pixel 100 located in the light-emitting area.
  • the main body of the pixel definition layer PDL covers the first display electrode of each sub-pixel 100 . One shows the edge of the electrode.
  • the display substrate 10 further includes a barrier layer 02 located on the main surface of the base substrate 200 and on a side of the first semiconductor layer Active layer close to the base substrate 200 .
  • the barrier layer 02 is in contact with the base substrate 200 .
  • Barrier layer 02 can protect the substrate substrate, Prevent damage and corrosion to the base substrate during the process of forming subsequent film layers.
  • the display substrate 10 further includes a buffer layer 01 , which is located on a side of the barrier layer 02 away from the base substrate 200 to further protect the base substrate.
  • the second plate Cst2 of the storage capacitor Cst has a first via hole V1 that exposes the first plate Cst1 of the storage capacitor Cst, and the first connection structure C1 passes through the first via hole V1.
  • the first via hole V1 penetrates the second sub-insulating layer ILD0 in a direction perpendicular to the main surface of the base substrate 200 .
  • the display substrate also includes a second sub-insulating layer ILD0, a third sub-insulating layer ILD1, a fourth sub-insulating layer GI2 and a fifth sub-insulating layer that is connected to the first via V1 and penetrates in a direction perpendicular to the main surface of the substrate substrate 200 Through the via V9 of the layer ILD2, the first connection structure C1 is electrically connected to the first plate Cst1 of the storage capacitor Cst through the via V9 and the first via V1.
  • the first connection structure C1 includes a first part C11 extending along the first direction D1 and a second part C12 extending along the second direction D2.
  • the second part C11 of the first connection structure C1 is in contact with the first connection structure.
  • the first part C11 is connected, for example, the second part C11 of the first connection structure C1 and the first part C11 of the first connection structure form a continuous one-piece structure.
  • the active layer A2 of the compensation transistor T2 is located on the side of the first connection structure C1 away from the data line Data, and the second part C12 of the first connection structure C1 is connected to the active layer A2 of the compensation transistor T2.
  • one end of the first part C11 of the first connection structure C1 away from the second part C12 in the first direction D1 is electrically connected to the first plate Cst1 of the storage capacitor Cst through the via V9 and the first via V1.
  • the first connection The second part C12 of the structure C1 is connected to the active layer A2 of the compensation transistor T2 through a second via hole V10, which penetrates the fourth sub-insulating layer GI2 and the third sub-insulating layer GI2 in a direction perpendicular to the main surface of the base substrate 200.
  • the fifth insulating layer ILD2 (refer to Figure 4A).
  • the first power supply line VDD is connected to the first voltage terminal vdd and is configured to provide the first power supply voltage VDD to the pixel circuit.
  • the first power line VDD extends along the first direction D1.
  • the pixel circuit also includes a second connection structure C2.
  • the second connection structure C2 is located between the first power line VDD and the second plate Cst2 of the storage capacitor Cst in a direction perpendicular to the main surface of the base substrate 200, and is connected to the second plate Cst2 of the storage capacitor Cst.
  • the second connection structure C2 includes a horizontal part C21 and a vertical part C22.
  • the horizontal part C21 extends along the second direction D2.
  • the vertical part C22 is connected to the horizontal part C21 and extends along the first direction D1.
  • the first power line VDD is on the base substrate 200
  • the orthographic projection overlaps with the orthographic projection of the horizontal portion C21 of the second connection structure C2 on the base substrate 200, and the orthographic projection of the first power line VDD on the base substrate 200 is arranged on the same layer as the other second connection structures C2. There is no overlap in the orthographic projection of the structures on the base substrate 200 .
  • connection structure C2 connects the first power line VDD and the second plate Cst2 of the storage capacitor Cst; on the other hand, because the conductive layer where the second connection structure C2 is located and the conductive layer where the first power line VDD is located are perpendicular to the substrate,
  • the main surface direction of 200 is relatively close to each other. For example, the two are adjacent conductive layers.
  • the third The orthographic projection of a power line VDD on the base substrate 200 does not overlap with the orthographic projection of other structures arranged on the same layer as the second connection structure C2 on the base substrate 200 to avoid the resulting first power supply voltage VDD. It is unstable and improves the display effect of the display substrate.
  • the vertical portion C22 is substantially aligned with the first connection structure C1 in the first direction
  • the orthographic projection of the horizontal portion C21 on the base substrate 200 is from the orthographic projection of the vertical portion C22 on the base substrate 200 .
  • the orthographic projection extends along the first direction D1 to the orthographic projection of the first power line VDD on the base substrate 200 , so that the extension trend of the second connection structure C2 corresponds to the extension trend of the first power supply voltage VDD and the first connection structure C1 design, rationally utilizing the limited space to achieve a regular and compact wiring design, which is conducive to improving the production yield of the pixel structure and achieving high PPI.
  • the first insulating layer PLN1 is located between the first power line VDD and the second connection structure C2, and the second insulating layer (including the third sub-insulating layer ILD1, the fourth sub-insulating layer GI2 and the fifth The sub-insulating layer ILD2) is located between the second connection structure C2 and the second plate Cst2 of the storage capacitor Cst; the horizontal part C21 of the second connection structure C2 is connected to the first power supply through the third via V3 that penetrates the first insulating layer PLN1
  • the vertical part C22 of the second connection structure C2 passes through the fourth via V4 that penetrates the second insulating layer (that is, the fourth via V4 penetrates the third sub-insulating layer ILD1, the fourth sub-insulating layer GI2 and the The fifth insulating layer ILD2) and the second plate Cst2 of the storage capacitor Cst connect.
  • the vertical portion C22 of the second connection structure C2 extending along the first direction D1 and the horizontal portion C21 of the second connection structure C2 extending along the second direction D2 are respectively connected to the first power line VDD, thereby, through multiple A connection structure and multiple via holes realize the electrical connection between the first power line VDD and the second plate Cst2 of the storage capacitor Cst, reducing the risk of disconnection caused by the need for a single via hole to pass through a thick insulation layer; and, By cleverly positioning and shaping the second connection structure C2 and the relationship between the second connection structure C2 and the first power line VDD, the first power line VDD and the second plate Cst2 of the storage capacitor Cst are electrically connected, and a compact structure is realized. Pixel structure.
  • the first power line VDD and the data line Data are arranged on the same layer.
  • the first power line VDD and the data line Data are both located on the fifth conductive layer SD2;
  • the second connection structure C2 and the third A connection structure C1 is arranged on the same layer, and the second connection structure C2 and the first connection structure C1 are both located on the fourth conductive layer SD. Therefore, by rationally arranging the positional relationship between the auxiliary connection structures such as the second connection structure C2 and the first connection structure C1 and the first power line VDD and data line Data, it is possible to facilitate the production of each layer of the display substrate and realize the above-mentioned pixel circuit.
  • the first light emission control transistor T5 of the pixel circuit is connected to the first electrode and the first voltage terminal of the driving transistor T3, and is configured to respond to the first light emission control signal applied to the gate electrode T5g of the first light emission control transistor T5.
  • the first power supply voltage VDD of the first voltage terminal vdd is applied to the first electrode T3s of the driving transistor T3; as above, the first semiconductor layer Active1 includes the active layer A3 of the driving transistor T3, the active layer A4 of the data writing transistor T4 and Active layer A5 of the first light emission control transistor T5.
  • FIG. 7C is a schematic cross-sectional view along the active layer direction of the fifth transistor, the third transistor, and the sixth transistor in FIG.
  • FIG. 3K that is, a schematic cross-sectional view along line A1-A2 in FIG. 3K .
  • the horizontal portion C21 of the second connection structure C2 is connected to the first semiconductor layer Active1 through the fifth via V5.
  • the horizontal portion C21 of the second connection structure C2 has a first end and a second end opposite to each other in the second direction D2, and the first end of the horizontal portion C21 is located near the vertical portion C22 of the first power line VDD. side and connected to the vertical portion C22.
  • the second end of the horizontal portion C21 is located on the side of the first power line VDD away from the vertical portion C22 and is connected to the first semiconductor layer Active1 through the fifth via V5.
  • one sub-pixel 100 also includes a third connection structure C3.
  • data The line Data is connected to the first semiconductor layer Active1 through the via V2.
  • the via V2 includes penetrating the first sub-insulating layer GI1, the second sub-insulating layer ILD0, the third sub-insulating layer ILD1, the fourth sub-insulating layer GI2 and the third sub-insulating layer GI2.
  • the first sub-via V21 is connected to the first semiconductor layer Active1, thereby realizing the connection between the data line Data and the first semiconductor layer Active1.
  • FIG. 7C is a schematic cross-sectional view along the active layer direction of the fifth transistor, the third transistor, and the sixth transistor in FIG. 3K , that is, a schematic cross-sectional view along line A1-A2 in FIG. 3K .
  • FIG. 7D is a schematic cross-sectional view along the active layer direction of the third transistor and the sixth transistor in FIG. 3K , that is, a schematic cross-sectional view along line B1 - B2 in FIG. 3K .
  • one sub-pixel 100 further includes a fourth connection structure C4 and a fifth connection structure C5.
  • the fourth connection structure C4 is located on the fifth conductive layer SD2, and the fifth connection structure C5 is located on the fourth conductive layer SD1.
  • the first display electrode 21 is located on the surface of the second planar layer PLN2 away from the base substrate 200 and is connected to the first semiconductor layer Active1 through the fourth connection structure C4 and via holes.
  • the first display electrode 21 is connected to the fourth connection structure C4 through the via V8 located in the second planar layer PLN2; the fourth connection structure C4 is connected to the fifth connection structure C5 through the via V7 located in the first planar layer PLN1 Connection; the fifth connection structure C5 is connected to the first sub-insulating layer GI1, the second sub-insulating layer ILD0, the third sub-insulating layer ILD1, the fourth sub-insulating layer GI2 and the fifth sub-insulating layer ILD2 through a via V6.
  • the semiconductor layer Active1 is connected.
  • the first display electrode 21 is electrically connected to the first semiconductor layer Active1 through multiple connection structures and multiple via holes, that is, electrically connected to the second electrode T6d of the second light-emitting transistor T6, thereby reducing the need for a single via hole to pass through. Risk of wire breakage caused by thicker insulation layer.
  • the substrate substrate 200 can be a rigid substrate, such as a glass substrate, a silicon substrate, etc., or it can be formed of a flexible material with excellent heat resistance and durability, such as polyethylene.
  • Imide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, Polyethylene terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethylmethacrylate (PMMA), triacetylcellulose (TAC), Cyclic olefin polymer (COP) and cyclic olefin copolymer (COC), etc.
  • the materials of the first to fifth conductive layers may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and the like. Alloy materials made of metal combinations materials; or transparent conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), etc.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • ZnO zinc oxide
  • AZO aluminum zinc oxide
  • the first insulating layer and the second insulating layer are inorganic insulating layers, and their materials include at least one of silicon oxides such as silicon oxide, silicon nitride, and silicon oxynitride, silicon nitrides, or silicon oxynitrides.
  • Insulating materials including aluminum oxide, titanium nitride, etc. including metal oxynitride.
  • the pixel definition layer PDL, the first flat layer PLN1 and the second flat layer PLN2 can be organic insulating materials, such as polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA) and other organic insulating materials. The embodiment of the present invention does not limit this.
  • examples of the materials and thicknesses of the above-mentioned layers of the display substrate 10 are shown in Table 1 below.
  • the materials and thicknesses of the above-mentioned respective film layers in the direction perpendicular to the main surface of the base substrate are also not the same. Limited to the situations shown in Table 1.
  • the light-emitting device has a top-emission structure
  • the first display electrode 21 is reflective and the second display electrode is transmissive or semi-transmissive.
  • the first display electrode 21 is a material with a high work function to serve as an anode, such as an ITO/Ag/ITO stack structure
  • the second display electrode 21 is a material with a low work function to serve as a cathode, such as a semi-transmissive metal or metal Alloy material, for example, Ag/Mg alloy material.
  • FIG. 8 is another plan view of a display substrate provided by an embodiment of the present invention.
  • the first display electrode 21 of the first sub-pixel P1 covers the first The boundary between the sub-pixel P1 and the second sub-pixel P2, and a part of the orthographic projection of the first connection structure C1 of the first sub-pixel P1 on the substrate 200 and the first connection structure C1 of the second sub-pixel P2 on the substrate A part of the orthographic projection on the substrate 200 is located within the orthographic projection of the first display electrode 21 of the first sub-pixel P1 on the base substrate 200 .
  • the first display electrode is located in the junction area of two adjacent sub-pixels, so that the first display electrode covers a part of the first connection structure of each of the two adjacent sub-pixels to meet the specific needs of the electrode. Arrangement method to obtain better display effect.
  • the orthographic projection of the entire first connection structure C1 on the substrate 200 may be located within the orthographic projection of the first display electrode 21 of the light-emitting device 20 on the substrate 200; multiple sub-pixels including a first sub-pixel P1 and a second sub-pixel P2 adjacent to each other in the second direction D2; the first display electrode 21 of the first sub-pixel P1 covers the boundary of the first sub-pixel P1 and the second sub-pixel P2, and
  • the orthographic projection of the first connection structure C1 of the first sub-pixel P1 on the base substrate 200 and the orthographic projection of the first connection structure C1 of the second sub-pixel P2 on the base substrate 200 are both located on the first sub-pixel P1
  • a display electrode 21 is in orthographic projection on the base substrate 200 .
  • FIG. 9 is a schematic cross-sectional view of a display substrate including a first connection structure and a first display electrode according to an embodiment of the present invention.
  • a part of the orthographic projection of the first connection structure C1 on the main surface of the base substrate 200 is located within the orthographic projection of the first display electrode 21 of the light emitting device 20 on the main surface of the base substrate 200
  • another part of the orthographic projection of the first connection structure C1 on the main surface of the base substrate 200 is within the orthographic projection of the first display electrode 21 of the light-emitting device 20 on the main surface of the base substrate 200 , that is, the third A part of the connection structure C1 is covered by the first display electrode 21
  • another part of the first connection structure C1 is not covered by the first display electrode 21 .
  • FIG. 10 is a schematic cross-sectional view of a display substrate including a first connection structure and a first display electrode according to an embodiment of the present invention.
  • the orthographic projection of the entire first connection structure C1 on the base substrate 200 is located on the first display electrode 21 on the base substrate 200 within the orthographic projection.
  • the first display electrode 21 of one sub-pixel 100 is on the base substrate 200
  • the orthographic projection on the main surface of the sub-pixel 100 also overlaps with a part of the orthographic projection of the data line Data of the sub-pixel 100 on the main surface of the base substrate 200; in the sub-pixel 100, the first display electrode 21 is far away from the data line Data.
  • the orthographic projection of the edge close to the first connection structure C1 on the base substrate 200 is substantially aligned with the edge of the first connection structure C1 away from the data line Data.
  • the “basic alignment” here is not limited to absolute alignment. For example, if the alignment error of the two substantially aligned edges is within 3% of the width of the first connection structure C1 in the second direction D2, it can be considered as the two edges. Basic alignment.
  • FIG. 11 is another schematic plan view of a display substrate provided by an embodiment of the present invention.
  • the light-emitting material of the light-emitting device 20 of the first sub-pixel P1 emits green light. That is, covering a part of the first connection structure C1 of the first sub-pixel P1 and the first sub-pixel where the first display electrode 21 of the first connection structure C1 of the second sub-pixel P2 is located in the direction perpendicular to the base substrate 200 The luminescent layer of P1 emits green light.
  • green luminescent materials are the least sensitive to changes in voltage, and the jump in the data voltage transmitted by the data line near the first connection structure C1 causes the first The signal on the connection structure C1 jumps to a certain extent, and the first display electrode located in the boundary area of the adjacent sub-pixels and partially covering the first connection structure C1 of the two adjacent sub-pixels is relatively close to the first connection structure C1.
  • the first display using the first connection structure C1 covering the adjacent sub-pixels 100 (for example, the first sub-pixel P1 and the second sub-pixel P2)
  • the solution in which the light-emitting layer of the sub-pixel where the electrode 21 is located emits green light can minimize the impact of the voltage jump of the first connection structure C1 on the light-emitting device where the first display electrode is located.
  • the orthographic projection of the edge of the first display electrode 21 of the first sub-pixel P1 away from the second sub-pixel P2 on the base substrate 200 is different from the orthographic projection of the first connection structure C1 of the first sub-pixel P1
  • the orthographic projection of the edge of the data line Data close to the first sub-pixel P1 on the base substrate 200 is substantially aligned, and the edge of the first display electrode 21 of the first sub-pixel P1 close to the second sub-pixel P2 is on the base substrate 200
  • the orthographic projection of is substantially aligned with the orthographic projection of the edge of the first connection structure C1 of the second sub-pixel P2 close to the data line Data of the second sub-pixel P2 on the base substrate 200 .
  • the “basic alignment” here is not limited to absolute alignment. For example, if the alignment error of the two substantially aligned edges is within 3% of the width of the first connection structure C1 in the second direction D2, it can be considered as the two edges. Basic alignment.
  • FIG. 12 is another schematic plan view of a display substrate provided by an embodiment of the present invention.
  • the first display electrodes 21 of the light emitting device 20 have mutually disposed elements in the second direction D2 . Opposite first and second ends; the first display electrode 21 of the first sub-pixel P1 covers the boundary between the first sub-pixel P1 and the second sub-pixel P2, and the first display electrode 21 of the first sub-pixel P1
  • the orthographic projection on the base substrate 200 has a first protruding portion 21A that is convex and tapered in the second direction D2 toward the orthographic projection of the second via hole V2 of the first sub-pixel P1 on the base substrate 200 , the orthographic projection of the second end of the first display electrode 21 of the first sub-pixel P1 on the main surface of the substrate substrate 200 has the second via V2 in the second direction D2 toward the second sub-pixel P2 in the substrate
  • the luminescent material of the luminescent device 20 of the first sub-pixel P1 emits blue light.
  • blue luminescent materials are more sensitive to voltage changes.
  • the first display electrodes 21 of the sub-pixels where the light-emitting device 20 using the blue luminescent material is located are respectively close to the first display electrode 21 of the sub-pixel.
  • the two ends of the data line Data1 located on both sides of the first display electrode 21 in the two directions D2 are tapered and protruded, which can reduce the impact of the jump of the data voltage on the data line Data1 located on both sides of the first display electrode 21 on the first display electrode 21. 21 voltage effects.
  • the first protruding portion 21A and the second protruding portion 21B are symmetrically designed so that the display effect on both sides of the first display electrode 21 in the second direction D2 is relatively uniform.
  • the second via hole is used to connect the data line and the first semiconductor layer, and the second via hole may include two sub-via holes that are not connected to each other. , see the first sub-via hole and the second sub-via hole as described previously for details. However, in different sub-pixels, the positions of the two sub-via holes included in the second via hole are not necessarily the same. For example, as shown in Figure 12, the first sub-via V21 of the second via V2 of the first sub-pixel P1 and the first sub-via V21 of the second via V2 of the second sub-pixel P2 are located in their respective sub-pixels.
  • the corresponding positions in the pixels are basically the same; the second via V22 of the second via V2 of the first sub-pixel P1 corresponds to the position of the data line Data1 of the first sub-pixel P1, and the second via V22 of the second sub-pixel P2
  • the second sub-via V22 of V2 corresponds to the position of the data line Data1 of the second sub-pixel P2.
  • the data line Data1 of the first sub-pixel P1 and the data line Data1 of the second sub-pixel P2 are relative to the data line Data1 extending along the first direction D1.
  • the distance between the first sub-via V21 and the second sub-via V22 of the first sub-pixel P1 is smaller than the distance between the first sub-via V21 and the second sub-via V22 of the second sub-pixel P2 distance.
  • FIG. 13 is another schematic cross-sectional view of a display substrate provided by an embodiment of the present invention.
  • the second plate Cst2 of the storage capacitor Cst includes a first portion Cst21 located on the first side of the first via hole V1 in the second direction D2 and a first portion Cst21 located on the first side of the first via hole V1 in the second direction D2.
  • the second part Cst22 of the second side, the first side of the first via hole V1 is opposite to the second side of the first via hole V1
  • the second part Cst22 of the second plate Cst2 is located in the first part Cst21 of the second plate Cst2 The side close to the data line Data.
  • the edge E1 of the second portion Cst22 of the second plate Cst2 of the storage capacitor Cst close to the first connection structure C1 in the second direction D2 (that is, the second edge 1b of the above-mentioned first connection structure C1) is on the base substrate 200
  • the orthographic projection of the edge E2 of the first display electrode 21 close to the first connection structure C1 on the base substrate 200 , and the edge E3 of the second part of the second plate Cst2 close to the first connection structure C1 are on The orthographic projections on the base substrate 200 overlap (substantially align). In this way, it is beneficial to reduce the parasitic capacitance formed by the first display electrode 21 and the first connection structure C1, and is also beneficial to the planarization of the fourth conductive layer SD1.
  • At least one of the overlapping portion D0 of the data line Data and the first connection structure C1 includes a recessed portion, and at least one of the overlapping portion D0 of the data line Data and the first connection structure C1 Any one of the recessed portions is recessed in the second direction D2 toward a direction away from the other of the overlapping portion D0 of the data line Data and the first connection structure C1.
  • FIG. 14A is a schematic diagram of a first connection structure and data lines in a display substrate according to an embodiment of the present invention.
  • the overlapping portion of the data line Data includes a first recessed portion R1 , the first recessed portion R1 is recessed in a direction away from the first connection structure C1 in the second direction D2 , and the first recessed portion R1 is recessed in the second direction D2 .
  • the opposite part of the data line Data is in the shape of a straight bar.
  • the first recessed portion R1 increases the distance between the overlapping portion D0 of the data line Data and the first connection structure C1, and reduces the capacitance value of the parasitic capacitance formed by the overlapping portion D0 of the data line Data and the first connection structure C1. .
  • the data line Data and the first connection structure C1 are arranged in different layers. Therefore, a film layer different from the first connection structure C1 can be used to lay out the pattern of the data line Data, avoiding the need for the first connection structure C1, etc.
  • the structure imposes space restrictions on the design of the first recessed portion R1, and there is sufficient space to meet the design requirements of the first recessed portion R1.
  • the first connection structure C1 is located on the fourth conductive layer SD1
  • the data line Data is located on the fifth conductive layer SD2.
  • a connection structure C1 may be located on the fifth conductive layer SD2, and the data line Data may be located on the fourth conductive layer SD1.
  • the first connection structure and the data line can also be located on two different conductive layers. The present invention does not impose specific restrictions on the layers where the first connection structure and the data line are located.
  • FIG. 14B is a schematic diagram of a first connection structure and data lines in another display substrate according to an embodiment of the present invention.
  • the first connection structure C1 includes a second recessed portion R2 that is recessed in the second direction D2 toward a direction away from the overlapping portion D0 of the data line Data.
  • D0 is a straight bar. Therefore, the second recessed portion R2 increases the distance between the overlapping portion D0 of the data line Data and the first connection structure C1, and reduces the capacitance of the parasitic capacitance formed by the overlapping portion D0 of the data line Data and the first connection structure C1. value.
  • the data line Data and the first connection structure C1 are arranged in different layers. Therefore, a film layer different from the data line Data can be used to lay out the pattern of the first connection structure C1, avoiding the impact of the data line Data and other structures on the design. Due to the space limitation of the second recessed part R2, there is sufficient space to meet the design of the second recessed part R2.
  • the first connection structure C1 is located on the fourth conductive layer SD1
  • the data line Data is located on the fifth conductive layer SD2.
  • a connection structure C1 may be located on the fifth conductive layer SD2
  • the data line Data may be located on the fourth conductive layer SD1.
  • the first connection structure and the data line can also be located on two different conductive layers. The present invention does not impose specific restrictions on the layers where the first connection structure and the data line are located.
  • FIG. 14C is a schematic diagram of yet another first connection structure and data lines in a display substrate according to an embodiment of the present invention.
  • the overlapping portion D0 of the data line Data includes a first recessed portion R1
  • the first recessed portion R1 is recessed in a direction away from the first connection structure C1 in the second direction D2
  • the first connection structure C1 includes a second recessed portion R2 that is recessed in the second direction D2 toward a direction away from the overlapping portion D0 of the data line Data.
  • the portion of the first connection structure C1 opposite to the data line Data has a straight strip shape.
  • the first recessed portion R1 and the second recessed portion R2 jointly further increase the distance between the overlapping portion D0 of the data line Data and the first connection structure C1, and further reduce the distance between the overlapping portion D0 of the data line Data and the first connection structure C1.
  • the data line Data and the first connection structure C1 are arranged in different layers, thereby avoiding the space restrictions on designing the first recessed portion R1 and the second recessed portion R2, and there are sufficient spaces in different layers respectively.
  • the space can satisfy the design of the first recessed portion R1 and the second recessed portion R2.
  • the first connection structure C1 is located on the fourth conductive layer SD1
  • the data line Data is located on the fifth conductive layer SD2.
  • a connection structure C1 may be located on the fifth conductive layer SD2, and the data line Data may be located on the fourth conductive layer SD1.
  • the first connection structure and data lines They may also be located on two other different conductive layers. The present invention does not place specific restrictions on the layers where the first connection structure and the data line are located.
  • FIG. 15 is a schematic diagram of a display device provided by at least one embodiment of the present invention.
  • a display device 10 - 1 provided by at least one embodiment of the present invention includes any display panel 10 provided by an embodiment of the present invention.
  • the display device 10 - 1 may be, for example, a device with a display function such as an organic light emitting diode display device or other types of devices.
  • the embodiments of the present invention are not limited to this.
  • the display device 10-1 provided in at least one embodiment of the present invention can be a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • the display device 10-1 provided in at least one embodiment of the present invention can be a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • Embodiments of the present invention There are no restrictions on this.

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Abstract

一种显示基板以及显示装置，该显示基板中，驱动晶体管控制发光器件发光；数据线与数据写入晶体管的第一极连接且配置为给数据写入晶体管提供数据信号；数据写入晶体管响应于施加在数据写入晶体管的栅极的第一扫描信号而将数据信号写入驱动晶体管的栅极；第一连接结构与驱动晶体管的栅极以及存储电容的第一极板连接，数据线和第一连接结构均沿第一方向延伸且数据线包括重叠部分，第一连接结构与数据线的重叠部分至少部分相对，第二方向平行于衬底基板且垂直于第一方向；第一连接结构与数据线的重叠部分彼此绝缘，第一连接结构与数据线的重叠部分分别构成寄生电容的第一极板和第二极板；寄生电容的电容值与存储电容的电容值的比值大于0.001且小于0.01。

Description

显示基板以及显示装置
本申请要求于2022年07月12日递交的中国专利申请第202210811589.8号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本发明至少一实施例涉及一种显示基板以及显示装置。
背景技术
有源矩阵有机发光二极管(AMOLED，Active Matrix Organic Light-Emitting Diode)显示器与传统的液晶显示器(LCD)相比，具有自发光、广色域、高对比度、轻薄等优点，使其广泛应用于手机、平板电脑等领域，另外也广泛应用于智能手表等柔性可穿戴领域。通常在显示区中设置有像素电路，在边框区设置有栅驱动电路例如GOA驱动电路以向像素电路提供驱动信号。
发明内容
本发明至少一实施例提供一种显示基板，该显示基板包括衬底基板，衬底基板上设置有呈阵列排布的多个像素；所述多个像素中的至少部分像素中的每个像素包括多个子像素，所述多个子像素中的至少部分包括像素电路，所述像素电路包括：发光器件、存储电容、驱动晶体管和数据写入晶体管、数据线以及第一连接结构。发光器件、存储电容、驱动晶体管和数据写入晶体管，所述驱动晶体管和所述数据写入晶体管的每个包括有源层、栅极、第一极和第二极，所述驱动晶体管配置为控制所述发光器件发光；数据线与所述数据写入晶体管的第一极连接且配置为给所述数据写入晶体管提供数据信号；所述数据写入晶体管配置为响应于施加在所述数据写入晶体管的栅极的第一扫描信号而将所述数据信号写入所述驱动晶体管的栅极；第一连接结构与所述驱动晶体管的栅极以及所述存储电容的第一极板连接，所述数据线和 所述第一连接结构均沿第一方向延伸，且所述数据线包括重叠部分，所述第一连接结构与所述数据线的重叠部分在第二方向上至少部分相对，所述第二方向平行于所述衬底基板且垂直于所述第一方向；所述第一连接结构与所述数据线的重叠部分彼此绝缘，所述第一连接结构与所述数据线的重叠部分分别构成寄生电容的第一极板和第二极板；所述寄生电容的电容值与所述存储电容的电容值的比值大于0.001且小于0.01。
例如，本发明一实施例提供的显示基板中，一个所述子像素的在所述第二方向上的尺寸大于50μm，所述寄生电容的电容值与所述存储电容的电容值的比值小于0.005。
例如，本发明一实施例提供的显示基板中，一个所述子像素的在所述第二方向上的尺寸小于等于68μm，所述寄生电容的电容值与所述存储电容的电容值的比值大于等于0.003。
例如，本发明一实施例提供的显示基板中，一个所述子像素的在所述第二方向上的尺寸小于50μm，所述寄生电容的电容值与所述存储电容的电容值的比值大于0.005且小于0.006。
例如，本发明一实施例提供的显示基板中，所述第一连接结构包括沿所述第一方向延伸的第一部分，所述第一连接结构的第一部分的靠近所述数据线的重叠部分的边缘为第一边缘，所述第一连接结构的第一部分还具有与远离所述数据线的重叠部分的第二边缘，所述数据线的重叠部分的靠近所述第一连接结构的边缘为第三边缘；所述多个子像素包括在所述第二方向上彼此相邻的第一子像素和第二子像素；所述第一子像素的第一连接结构的第二边缘在所述衬底基板上的正投影到所述第二子像素的数据线的重叠部分的第三边缘在所述衬底基板上的正投影的距离为第一距离，所述第一子像素的第一连接结构的第一边缘到所述第一子像素的数据线的重叠部分的第三边缘的距离为第二距离，所述第一距离与所述第二距离的比值大于14。
例如，本发明一实施例提供的显示基板中，一个所述子像素的在所述第二方向上的尺寸小于50μm，所述第一距离与所述第二距离的比值大于14且小于15.5。
例如，本发明一实施例提供的显示基板中，一个所述子像素的在所述第二方向上的尺寸大于50μm，所述第一距离与所述第二距离的比值大于15.5。
例如，本发明一实施例提供的显示基板中，所述多个子像素包括在所述第二方向上彼此相邻的第一子像素和第二子像素；所述第一子像素的第一连接结构在所述第二方向上位于所述第一子像素的数据线和所述第二子像素的数据线之间；所述第一子像素的第一连接结构在所述衬底基板上的正投影与所述第一子像素的数据线在所述衬底基板上的正投影之间的距离小于一个所述子像素的在所述第二方向上的尺寸，并且，所述第一子像素的第一连接结构在所述衬底基板上的正投影与所述第二子像素的数据线在所述衬底基板上的正投影之间的距离小于一个所述子像素的在所述第二方向上的尺寸。
例如，本发明一实施例提供的显示基板中，所述第一子像素的第一连接结构在所述第二方向上位于所述第一子像素的数据线和所述第二子像素的数据线之间；所述第一子像素的第一连接结构在所述衬底基板上的正投影与所述第一子像素的数据线在所述衬底基板上的正投影之间的距离小于一个所述子像素的在所述第二方向上的尺寸，并且，所述第一子像素的第一连接结构在所述衬底基板上的正投影与所述第二子像素的数据线在所述衬底基板上的正投影之间的距离大于一个所述子像素的在所述第二方向上的尺寸。
例如，本发明一实施例提供的显示基板中，所述第一子像素的驱动晶体管的栅极的靠近所述第二子像素的数据线的重叠部分的边缘为第四边缘；所述第一子像素的第二边缘到所述第二子像素的第三边缘的距离等于所述第一子像素的第二边缘到所述第四边缘的距离与所述第一子像素的所述第四边缘到所述第二子像素的第三边缘的距离之和。
例如，本发明一实施例提供的显示基板中，所述第一连接结构与所述数据线异层设置，所述第一连接结构在所述衬底基板上的正投影与所述数据线的重叠部分在所述衬底基板上的正投影至少部分重叠；或者，所述第一连接结构与所述数据线异层设置，所述第一连接结构在所述衬底基板上的正投影与所述数据线的重叠部分在所述衬底基板上的正投影不重叠。
例如，本发明一实施例提供的显示基板中，所述第一连接结构与所述数据线同层设置，所述第一连接结构与所述数据线的重叠部分在第二方向上彼此相对。
例如，本发明一实施例提供的显示基板中，所述数据线的重叠部分和所述第一连接结构两者中的至少一者包括凹陷部，所述数据线的重叠部分和所 述第一连接结构两者中的任意一者的所述凹陷部在所述第二方向上朝向远离所述数据线的重叠部分和所述第一连接结构两者中的另一者的方向凹陷。
例如，本发明一实施例提供的显示基板中，所述数据线的重叠部分包括第一凹陷部，所述第一凹陷部在所述第二方向上朝向远离所述第一连接结构的方向凹陷，所述第一连接结构的与所述数据线相对的部分呈直的条形。
例如，本发明一实施例提供的显示基板中，所述第一连接结构包括第二凹陷部，所述第二凹陷部在所述第二方向上朝向远离所述数据线的重叠部分的方向凹陷，所述数据线的重叠部分呈直的条形。
例如，本发明一实施例提供的显示基板中，所述数据线的重叠部分包括第一凹陷部，所述第一凹陷部在所述第二方向上朝向远离所述第一连接结构的方向凹陷，并且，所述第一连接结构包括第二凹陷部，所述第二凹陷部在所述第二方向上朝向远离所述数据线的重叠部分的方向凹陷。
例如，本发明一实施例提供的显示基板还包括第一复位扫描信号线、第二复位扫描信号线、第一复位信号线和第二复位信号线；所述像素电路还包括：第一复位晶体管和第二复位晶体管。第一复位晶体管包括有源层，所述第一复位扫描信号线配置为给所述第一复位晶体管的栅极提供第一复位扫描信号，所述第一复位晶体管的第一极与所述驱动晶体管的栅极电连接，所述第一复位晶体管的第二极被配置为与所述第一复位信号线电连接以接收第一复位信号，所述第一复位晶体管配置为响应于所述第一复位扫描信号将所述第一复位信号写入所述驱动晶体管的栅极；所述第二复位扫描信号线配置为给所述第二复位晶体管的栅极提供第二复位扫描信号，所述第二复位晶体管的第一极与所述发光器件的第一显示电极电连接，所述第二复位晶体管的第二极被配置为与所述第二复位信号线电连接以接收第二复位信号，所述第二复位晶体管配置为响应于所述第二复位扫描信号将所述第二复位信号写入所述发光器件的第一显示电极；所述第一复位晶体管的有源层沿所述第一方向延伸，所述第一复位扫描信号线沿所述第二方向延伸；所述多个子像素包括在所述第二方向上彼此相邻的第一子像素和第二子像素；所述多个子像素还包括第三子像素，所述第三子像素与所述第二子像素在所述第一方向上相邻；所述第二复位信号线的位于一个所述子像素的部分包括横向部分和第一纵向部分，所述横向部分沿所述第二方向延伸且具有在所述第二方向上彼此相对 的第一端和第二端，所述第一纵向部分与所述横向部分的第一端连接且沿所述第一方向延伸，并且，所述第二子像素的第二复位信号线的横向部分在所述衬底基板上的正投影与所述第三子像素的第一复位扫描信号线在所述衬底基板上的正投影至少部分重叠，所述第二子像素的第二复位信号线的第一纵向部分与所述第三子像素的第一复位晶体管的有源层在所述第二方向上间隔排列。
例如，本发明一实施例提供的显示基板中，所述第二复位信号线的对应于一个子像素的子部的平面图形呈倒置的“几”字形；所述“几”字形的子部包括U形凹槽，所述第二复位信号线的横向部分作为所述U形凹槽的底部。
例如，本发明一实施例提供的显示基板还包括补偿扫描信号线；所述像素电路还包括补偿晶体管，包括有源层、栅极、第一极和第二极；所述补偿扫描信号线配置为给所述补偿晶体管的栅极施加第二扫描信号，所述补偿晶体管的配置为响应于所述第二扫描信号对该所述驱动晶体管进行阈值补偿；所述补偿晶体管的有源层与所述第一复位晶体管的有源层构成一体结构。
例如，本发明一实施例提供的显示基板中，所述第二复位信号线的位于一个所述子像素的部分还包括第二纵向部分，所述第二纵向部分与所述横向部分的第二端连接且沿所述第一方向延伸，所述第二复位晶体管的有源层位于所述第一纵向部分与所述第二纵向部分之间，并且，在同一个所述子像素中，在所述第二方向上，所述第一纵向部分到所述数据线的距离大于所述第二纵向部分到所述数据线的距。所述第三子像素的第二复位晶体管的有源层到所述第二子像素的第二复位信号线的第一纵向部分的距离小于所述第三子像素的第二复位晶体管的有源层到所述第二子像素的第二复位信号线的第二纵向部分的距离。
例如，本发明一实施例提供的显示基板中，所述驱动晶体管的栅极与所述存储电容的第一极板同层设置且构成一体成型结构，所述第二复位扫描信号线与所述驱动晶体管的栅极同层设置；所述驱动晶体管的栅极和所述存储电容的第一极板位于所述驱动晶体管的有源层的远离所述衬底基板的一侧；所述存储电容的第二极板位于所述驱动晶体管的栅极和所述存储电容的第一极板的远离所述衬底基板的一侧，所述补偿扫描信号线与所述存储电容的第二极板同层设置；所述补偿晶体管的有源层位于所述存储电容的第二极板 的远离所述衬底基板的一侧；所述第二复位信号线位于所述补偿晶体管的有源层的远离所述衬底基板的一侧。
例如，本发明一实施例提供的显示基板还包括第一复位扫描信号线和第一复位信号线，所述像素电路还包括第一复位晶体管。第一复位晶体管包括有源层，所述第一复位扫描信号线配置为给所述第一复位晶体管的栅极提供第一复位扫描信号，所述第二复位晶体管的第一极与所述驱动晶体管的栅极电连接，所述第一复位晶体管的第二极被配置为与所述第一复位信号线电连接以接收第一复位信号，所述第一复位晶体管配置为响应于所述第一复位扫描信号将所述第一复位信号写入所述驱动晶体管的栅极；所述第一复位晶体管的有源层与所述驱动晶体管的有源层的材料不同且异层设置；所述第一复位信号线与所述存储电容的第二极板同层设置。
例如，本发明一实施例提供的显示基板中，所述补偿晶体管的栅极和所述第一复位晶体管的栅极均为双栅结构，所述补偿晶体管的栅极包括第一栅极和第二栅极，所述第一复位晶体管的栅极包括第一栅极和第二栅极；所述补偿晶体管的第一栅极在所述衬底基板上的正投影与所述补偿晶体管的第二栅极在所述衬底基板上的正投影重合，所述第一复位晶体管的第一栅极在所述衬底基板上的正投影与所述第一复位晶体管的第二栅极在所述衬底基板上的正投影重合。
例如，本发明一实施例提供的显示基板中，所述补偿晶体管的第一栅极和所述第一复位晶体管的第一栅极与所述存储电容的第二极板同层设置，所述补偿晶体管的第二栅极和所述第一复位晶体管的第二栅极位于所述补偿晶体管的有源层和所述第一复位晶体管的有源层的远离所述衬底基板的一侧，且位于所述第二复位信号线的靠近所述衬底基板的一侧。
例如，本发明一实施例提供的显示基板中，所述第一复位晶体管的有源层的材料为氧化物半导体；所述驱动晶体管和所述数据写入晶体管的有源层的材料为低温多晶硅。
例如，本发明一实施例提供的显示基板中，所述第一连接结构位于所述存储电容的第二极板的远离所述衬底基板的一侧；所述存储电容的第二极板具有暴露所述存储电容的第一极板的第一过孔，所述第一连接结构穿过所述第一过孔而与所述存储电容的第一极板连接；所述存储电容的第二极板包括 位于所述第一过孔在所述第二方向上的第一侧的第一部分和位于所述第一过孔在所述第二方向上的第二侧的第二部分，所述第一过孔的第一侧与所述第一过孔的第二侧相对，所述第二极板的第二部分位于所述第二极板的第一部分的靠近所述数据线的一侧；所述第一连接结构在所述第二方向上靠近所述存储电容的第二极板的第二部分的边缘在所述衬底基板上的正投影、所述第一显示电极的靠近所述第一连接结构的边缘在所述衬底基板上的正投影、以及所述第二极板的第二部分的靠近所述第一连接结构的边缘在所述衬底基板上的正投影重叠。
例如，本发明一实施例提供的显示基板中，所述第一连接结构与所述第二复位信号线同层设置；在所述第一连接结构与所述数据线异层设置的情况下，所述数据线位于所述第一连接结构的远离所述衬底基板的一侧，或者，所述数据线位于所述第一连接结构的靠近所述衬底基板的一侧。
例如，本发明一实施例提供的显示基板中，所述第一连接结构包括沿所述第一方向延伸的第一部分和沿所述第二方向延伸的第二部分，所述第一连接结构的第二部分与所述第一连接结构的第一部分连接；所述补偿晶体管的有源层位于所述第一连接结构的远离所述数据线的一侧，所述第一连接结构的第二部分与所述补偿晶体管的有源层连接。
例如，本发明一实施例提供的显示基板中，整个所述第一连接结构在所述衬底基板上的正投影位于所述发光器件的第一显示电极在所述衬底基板上的正投影内；所述多个子像素包括在所述第二方向上彼此相邻的第一子像素和第二子像素；所述第一子像素的第一显示电极覆盖所述第一子像素与所述第二子像素的交界，且所述第一子像素的第一连接结构在所述衬底基板上的正投影与所述第二子像素的第一连接结构在所述衬底基板上的正投影均位于所述第一子像素的第一显示电极在所述衬底基板上的正投影内。
例如，本发明一实施例提供的显示基板中，所述第一子像素的第一显示电极的远离所述第二子像素的边缘在所述衬底基板上的正投影与所述第一子像素的第一连接结构的靠近所述第一子像素的数据线的边缘在所述衬底基板上的正投影重叠，所述第一子像素的第一显示电极的靠近所述第二子像素的边缘在所述衬底基板上的正投影与所述第二子像素的第一连接结构的靠近所述第二子像素的数据线的边缘在所述衬底基板上的正投影重叠。
例如，本发明一实施例提供的显示基板中，所述第一结构在所述衬底基板上的正投影的一部分位于所述发光器件的第一显示电极在所述衬底基板上的正投影内；所述多个子像素包括在所述第二方向上彼此相邻的第一子像素和第二子像素；所述第一子像素的第一显示电极覆盖所述第一子像素与所述第二子像素的交界，且所述第一子像素的第一连接结构在所述衬底基板上的正投影的一部分与所述第二子像素的第一连接结构在所述衬底基板上的正投影的一部分均位于所述第一子像素的第一显示电极在所述衬底基板上的正投影内。
例如，本发明一实施例提供的显示基板中，所述第一子像素的发光器件的发光材料发射绿光。
例如，本发明一实施例提供的显示基板中，所述存储电容的第一极板具有远离所述衬底基板的上表面和与所述上表面相交的侧表面；所述存储电容的第二极板包括：中间部分和边缘部分。中间部分在所述衬底基板上的正投影与所述存储电容的第一极板在所述衬底基板上的正投影至少部分重合，且包括与所述存储电容的第一极板的上表面相对的底面；边缘部分至少部分围绕所述中间部分且与所述中间部分连接，且包括靠近所述衬底基板的底面和与所述底面相交的内侧面；所述内侧面与所述存储电容的第一极板的侧表面彼此相对，且所述内侧面在垂直于所述衬底基板的参考面上的正投影与与所述内侧面相对的所述存储电容的第一极板的侧表面在所述参考面上的正投影至少部分重叠；所述边缘部分的内侧面与，与所述内侧面相对的所述存储电容的第一极板的侧表面，之间的距离小于所述中间部分的底面与所述存储电容的第一极板的上表面之间的距离。
例如，本发明一实施例提供的显示基板中，所述发光器件的第一显示电极具有在所述第二方向上彼此相对的第一端和第二端；所述显示基板包括第一半导体层，所述第一半导体层包括所述驱动晶体管的有源层和所述数据写入晶体管的有源层，所述数据线通过第二过孔与所述第一半导体层连接；所述多个子像素包括在所述第二方向上彼此相邻的第一子像素和第二子像素；所述第一子像素的第一显示电极覆盖所述第一子像素与所述第二子像素的交界，所述第一子像素的第一显示电极的第一端在所述衬底基板上的正投影具有在所述第二方向上朝向所述第一子像素的第二过孔在所述衬底基板上的正 投影凸出且渐缩的第一凸出部，所述第一子像素的第一显示电极的第二端在所述衬底基板上的正投影具有在所述第二方向上朝向所述第二子像素的第二过孔在所述衬底基板上的正投影凸出且渐缩的第二凸出部，并且，所述第一凸出部与所述第一子像素的第二过孔在所述衬底基板上的正投影在所述第二方向上正对，所述第二凸出部与所述第二子像素的第二过孔在所述衬底基板上的正投影在所述第二方向上正对；所述第一子像素的发光器件的发光材料发射蓝光。
例如，本发明一实施例提供的显示基板中，所述驱动晶体管的栅极与所述存储电容的第一极板同层设置且构成一体成型结构；所述驱动晶体管的栅极和所述存储电容的第一极板位于所述驱动晶体管的有源层的远离所述衬底基板的一侧；所述存储电容的第二极板位于所述驱动晶体管的栅极和所述存储电容的第一极板的远离所述衬底基板的一侧，所述显示基板还包括第一电源线，第一电源线与第一电压端连接且配置为给所述像素电路提供第一电源电压，沿所述第一方向延伸；所述像素电路还包括第二连接结构，第二连接结构在垂直于所述衬底基板的方向上位于所述第一电源线与所述存储电容的第二极板之间，且连接所述第一电源线和所述存储电容的第二极板，其中，所述第二连接结构包括水平部分和竖直部分，所述水平部分沿所述第二方向延伸，所述竖直部分与所述水平部分连接且沿所述第一方向延伸；所述第一电源线在所述衬底基板上的正投影与所述第二连接结构的水平部分在所述衬底基板上的正投影交叠，且所述第一电源线在所述衬底基板上的正投影与其他和所述第二连接结构同层设置的结构在所述衬底基板上的正投影不存在交叠。
例如，本发明一实施例提供的显示基板中，所述竖直部分与第一连接结构在所述第一方向上基本对齐，所述水平部分在所述衬底基板上的正投影自所述竖直部分在所述衬底基板上的正投影沿所述第一方向延伸至所述第一电源线在所述衬底基板上的正投影。
例如，本发明一实施例提供的显示基板还包括第一绝缘层和第二绝缘层。第一绝缘层位于所述第一电源线与所述第二连接结构之间；第二绝缘层位于所述第二连接结构与所述存储电容的第二极板之间，其中，所述第一电源线的水平部分通过贯穿所述第一绝缘层的第三过孔与所述第二连接结构连接， 所述第二连接结构的竖直部分通过贯穿所述第二绝缘层的第四过孔与所述存储电容的第二极板连接。
例如，本发明一实施例提供的显示基板中，所述第一电源线与所述数据线同层设置，所述第二连接结构与所述第一连接结构同层设置。
例如，本发明一实施例提供的显示基板中，所述像素电路还包括第一发光晶体管，第一发光晶体管与所述驱动晶体管的第一极以及所述第一电压端连接，且配置为响应于施加在所述第一发光晶体管的栅极的第一发光控制信号将所述第一电压端的第一电源电压施加至所述驱动晶体管的第一极；所述显示基板包括第一半导体层，所述第一半导体层包括所述驱动晶体管的有源层、所述数据写入晶体管的有源层和所述第一发光晶体管的有源层，所述第二连接结构的水平部分通过第五过孔与所述第一半导体层连接。
例如，本发明一实施例提供的显示基板中，所述第二连接结构的水平部分在所述第二方向上具有彼此相对的第一端和第二端，所述水平部分的第一端位于所述第一电源线的靠近所述竖直部分的一侧且与所述竖直部分连接，所述水平部分的第二端位于所述第一电源线的远离所述竖直部分的一侧且通过所述第五过孔与所述第一半导体层连接。
本发明至少一实施例还提供一种显示装置，该显示装置包括本发明实施例提供的任意一种显示基板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本发明一实施例提供的一种显示基板的平面示意图。
图2A为本发明至少一实施例提供的像素电路的示意图。
图2B为图2A所示的像素电路的一种具体示例的电路图。
图2C为本发明至少一实施例提供的像素电路的驱动方法的信号时序图。
图3A为本发明一实施例提供的一种显示基板的子像素的第一半导体层与第一导电层堆叠的平面示意图。
图3B为本发明一实施例提供的一种显示基板的子像素的第二导电层和 第二半导体层堆叠的平面示意图。
图3C为本发明一实施例提供的一种显示基板的子像素的第一半导体层、第一导电层、第二导电层和第二半导体层堆叠的平面示意图。
图3D为本发明一实施例提供的一种显示基板的子像素的第二导电层和第三导电层堆叠的平面示意图。
图3E为本发明一实施例提供的一种显示基板的子像素的第一半导体层、第一导电层、第二导电层、和第二半导体层和第三导电层堆叠的平面示意图。
图3F为本发明一实施例提供的一种显示基板的子像素的第一层间绝缘层和第四导电层堆叠的平面示意图。
图3G为本发明一实施例提供的一种显示基板的子像素的第一半导体层、第一导电层、第二导电层、第二半导体层、第三导电层堆叠、第一层间绝缘层和第四导电层堆叠的平面示意图。
图3H为本发明一实施例提供的一种显示基板的子像素的第一平坦层和第五导电层堆叠的平面示意图。
图3I为本发明一实施例提供的一种显示基板的子像素的第一半导体层、第一导电层、第二导电层、第二半导体层、第三导电层堆叠、第一层间绝缘层、第四导电层、第一平坦层和第五导电层堆叠的平面示意图。
图3J为本发明一实施例提供的一种显示基板的子像素的第二平坦层、第一电极和像素界定层堆叠的平面示意图。
图3K为本发明一实施例提供的一种显示基板的子像素的平面示意图，即子像素的第一半导体层、第一导电层、第二导电层、第二半导体层、第三导电层堆叠、第一层间绝缘层、第四导电层、第一平坦层、第五导电层、第二平坦层、第一电极和像素界定层堆叠的平面示意图。
图4A为依次沿图3K中的第三晶体管、第六晶体管的有源层走向的一种截面示意图。
图4B为一种显示基板的结构示意图。
图4C为一种电极正对平板电容的示意图。
图4D为一种电极斜置平板电容的示意图。
图4E是本发明一实施例提供的一种显示基板的再一种截面示意图。
图5为本发明一实施例提供的一种显示基板的相邻的至少两个子像素的 平面示意图。
图6是在图5的基础上移除了第一电源线之后的示意图。
图7A为依次沿图3K中的第四晶体管、第三晶体管、第二晶体管、第一晶体管的有源层走向在第一视角的截面示意图。
图7B为依次沿图3K中的第四晶体管、第三晶体管、第二晶体管、第一晶体管的有源层走向在第二视角的截面示意图。
图7C为依次沿图3K中的第五晶体管、第三晶体管、第六晶体管的有源层走向的截面示意图，即沿图3K中的A1-A2线的截面示意图。
图7D为依次沿图3K中的第三晶体管、第六晶体管的有源层走向的截面示意图，即沿图3K中的B1-B2线的截面示意图。
图8是本发明一实施例提供的一种显示基板的另一种平面示意图。
图9是本发明一实施例提供的一种显示基板的另一种截面示意图。
图10是本发明一实施例提供的一种显示基板的再一种截面示意图。
图11是本发明一实施例提供的一种显示基板的再一种平面示意图。
图12是本发明一实施例提供的一种显示基板的又一种平面示意图。
图13是本发明一实施例提供的一种显示基板的再一种截面示意图。
图14A为本发明一实施例提供的一种显示基板中的第一连接结构与数据线的示意图。
图14B为本发明一实施例提供的另一种显示基板中的第一连接结构与数据线的示意图。
图14C为本发明一实施例提供的又一种显示基板中的第一连接结构与数据线的示意图。
图15为本发明至少一实施例提供的显示装置示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本发明保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本发明中的附图并不是严格按实际比例绘制，显示基板中子像素和虚拟像素的个数也不是限定为图中所示的数量，各个结构的具体地尺寸和数量可根据实际需要进行确定。本发明中所描述的附图仅是结构示意图。
需要说明的是，本申请中的某结构在衬底基板上的正投影是指该结构在衬底基板的主表面上的正投影，衬底基板的主表面是指衬底基板的设置像素电路的表面。
需要说明的是，本发明中所称的“同层设置”是指两种(或两种以上)结构通过同一道沉积工艺形成并通过同一道构图工艺得以图案化而形成的结构，它们的材料可以相同或不同。本发明中的“连续的一体结构”是指该两种(或两种以上)结构由同一膜层经同一道构图工艺得以图案化而形成的彼此连接的结构，它们的材料可以相同或不同。
还需要说明的是，Scan(N)(n)代表第n行与N型TFT连接的扫描信号线，Scan(N)(n-1)代表第n-1行与N型TFT连接的扫描信号线，Scan(N)(n+1)代表第n+1行与N型TFT连接的扫描信号线。Scan(P)(n)代表第n行与P型TFT连接的扫描信号线，Scan(P)(n+1)代表第n+1行与P型TFT连接的扫描信号线。
一般AMOLED的像素的驱动电路具有多个晶体管，一个像素的驱动电路驱动晶体管的栅极节点与其相邻的数据线之间往往会形成寄生电容，使得在显示过程中数据线上的跳变电压对驱动晶体管的驱动电压产生影响。
本发明至少一实施例提供一种显示基板，该显示基板包括衬底基板，衬底基板上设置有呈阵列排布的多个像素；所述多个像素中的至少部分像素中的每个像素包括多个子像素，所述多个子像素中的至少部分包括像素电路， 所述像素电路包括：发光器件、存储电容、驱动晶体管和数据写入晶体管、数据线以及第一连接结构。发光器件、存储电容、驱动晶体管和数据写入晶体管，所述驱动晶体管和所述数据写入晶体管的每个包括有源层、栅极、第一极和第二极，所述驱动晶体管配置为控制所述发光器件发光；数据线与所述数据写入晶体管的第一极连接且配置为给所述数据写入晶体管提供数据信号；所述数据写入晶体管配置为响应于施加在所述数据写入晶体管的栅极的第一扫描信号而将所述数据信号写入所述驱动晶体管的栅极；第一连接结构与所述驱动晶体管的栅极以及所述存储电容的第一极板连接，所述数据线和所述第一连接结构均沿第一方向延伸，且所述数据线包括重叠部分，所述第一连接结构与所述数据线的重叠部分在第二方向上至少部分相对，所述第二方向平行于所述衬底基板且垂直于所述第一方向；所述第一连接结构与所述数据线的重叠部分彼此绝缘，所述第一连接结构与所述数据线的重叠部分分别构成寄生电容的第一极板和第二极板；所述寄生电容的电容值与所述存储电容的电容值的比值大于0.001且小于0.01。
需要说明的是，本发明的权利要求的保护范围所涉及的寄生电容的电容值，以说明书公开的计算方法为准。
本发明至少一实施例还提供一种显示装置，该显示装置包括本发明实施例提供的任意一种显示基板。
示例性地，图1为本发明一实施例提供的一种显示基板的平面示意图。如图1所示，例如，显示基板10包括呈阵列排布的多个像素100，多个像素100中的至少部分像素100包括多个子像素，多个子像素中的至少部分子像素包括发光器件和驱动发光器件发光的像素电路。例如，像素电路可以包括2T1C(即两个晶体管和一个电容)像素电路、4T2C、5T1C、7T1C或nTmC(n、m为正整数)像素电路。例如，在不同的实施例中，像素电路还可以包括补偿子电路，该补偿子电路包括内部补偿子电路或外部补偿子电路，补偿子电路可以包括晶体管、电容等。例如，根据需要，该像素电路还可以进一步包括复位电路、发光控制子电路、检测电路等。
例如，如图1所示，多个像素100位于显示区。例如，在一些实施例提供的显示基板10中，多个像素100中的部分像素为虚拟像素(dummy pixel)1000，虚拟像素1000不参与显示工作，每个虚拟像素1000包括多个虚拟子 像素，而不包含发挥显示驱动作用的子像素。
例如，在一些实施例中，该显示基板10是有机发光二极管(OLED)显示基板，该发光器件为OLED。该显示基板10还可以包括多条扫描线、多条数据线以用于为该多个子像素提供扫描信号(控制信号)和数据信号，从而驱动该多个子像素。根据需要，该显示基板10还可以进一步包括电源线、检测线等。
图2A为本发明至少一实施例提供的像素电路的示意图。如图2A所示，该像素电路单元包括驱动子电路122、补偿子电路128、数据写入子电路126、存储子电路127、第一发光控制子电路123、第二发光控制子电路124及第一复位子电路125和第二复位子电路129。
例如，该驱动子电路122包括控制端122a、第一端122b和第二端122c，且配置为与发光器件20连接并且控制流经发光器件20的驱动电流。驱动子电路122的控制端122a和第一节点N1连接，驱动子电路122的第一端122b和第二节点N2连接并配置为接收第一电源电压VDD，驱动子电路122的第二端122c和第三节点N3连接。
例如，该数据写入子电路126包括控制端126a、第一端126b和第二端126c，该控制端126a配置为接收第一扫描信号Ga1，第一端126b配置为接收数据信号Vd，第二端126c与驱动子电路122的第一端122b(也即第二节点N2)连接。该数据写入子电路126配置为响应于该第一扫描信号Ga1将该数据信号Vd写入驱动子电路122的第一端122b。例如，数据写入子电路126的第一端126b与数据线12连接以接收该数据信号Vd，控制端126a与作为扫描线的栅线11连接以接收该第一扫描信号Ga1。例如，在数据写入及补偿阶段，数据写入子电路126可以响应于第一扫描信号Ga1而开启，从而可以将数据信号写入驱动子电路122的第一端122b(第二节点N2)，并将数据信号存储在存储子电路127中，以在例如发光阶段时可以根据该数据信号生成驱动发光器件20发光的驱动电流。
例如，补偿子电路128包括控制端128a、第一端128b和第二端128c，补偿子电路128的控制端128a配置为接收第二扫描信号Ga2，补偿子电路128的第一端128b和第二端128c分别与驱动子电路122的第二端122c和控制端122a电连接，补偿子电路128配置为响应于该第二扫描信号Ga2对该驱动子 电路122进行阈值补偿。
例如，第一扫描信号Ga1可以与第二扫描信号Ga2相同。例如第一扫描信号Ga1可以与第二扫描信号Ga2连接到相同的信号输出端。例如，第一扫描信号Ga1可以与第二扫描信号Ga2通过相同的扫描线传输。
在另一些示例中，第一扫描信号Ga1也可以与第二扫描信号Ga2不同。例如，第一扫描信号Ga1可以与第二扫描信号Ga2连接到不同的信号输出端。例如，第一扫描信号Ga1可以与第二扫描信号Ga2分别通过不同的扫描线传输。
例如，存储子电路127包括第一端127a和第二端127b，该存储子电路的第一端127a配置为接收第一电源电压VDD，存储子电路的第二端127b与驱动子电路的控制端122a电连接。
例如，存储子电路127与驱动子电路122的控制端122a及第一电压端vdd电连接，配置为存储数据写入子电路126写入的数据信号。例如，在数据写入和补偿阶段，补偿子电路128可以响应于该第二扫描信号Ga2而开启，从而可以将数据写入子电路126写入的数据信号存储在该存储子电路127中。例如，同时在数据写入和补偿阶段，补偿子电路128可以将驱动子电路122的控制端122a和第二端122c电连接，从而可以使驱动子电路122的阈值电压的相关信息也相应地存储在该存储子电路中，从而例如在发光阶段可以利用存储的数据信号以及阈值电压对驱动子电路122进行控制，使得驱动子电路122的输出得到补偿。
例如，第一发光控制子电路123与驱动子电路122的第一端122b(第二节点N2)以及第一电压端vdd连接，且配置为响应于第一发光控制信号EM1将第一电压端vdd的第一电源电压VDD施加至驱动子电路122的第一端122b。例如，如图2A所示，第一发光控制子电路123和第一发光控制端EM1、第一电压端vdd以及第二节点N2连接。
例如，第二发光控制子电路124和第二发光控制端EM2、发光器件20的第一端134以及驱动子电路122的第二端122c连接，且配置为响应于第二发光控制信号使得驱动电流可被施加至发光器件20。
例如，在发光阶段，第二发光控制子电路124响应于第二发光控制端EM2提供的第二发光控制信号EM2而开启，从而驱动子电路122可以通过第二发 光控制子电路124与发光器件20电连接，从而驱动发光器件20在驱动电流控制下发光；而在非发光阶段，第二发光控制子电路124响应于第二发光控制信号EM2而截止，从而避免有电流流过发光器件20而使其发光，可以提高相应的显示装置的对比度。
又例如，在初始化阶段，第二发光控制子电路124也可以响应于第二发光控制信号EM2而开启，从而可以结合复位子电路以对驱动子电路122以及发光器件20进行复位操作。
例如，第二发光控制信号EM2可以与第一发光控制信号EM1相同，例如第二发光控制信号EM2可以与第一发光控制信号EM1连接到相同的信号输出端，例如，第二发光控制信号EM2可以与第一发光控制信号EM1通过相同的发光控制线传输。
在另一些示例中，第二发光控制信号EM2可以与第一发光控制信号EM1不同。例如，第二发光控制信号EM2可以与第一发光控制信号EM1分别连接到不同的信号输出端。例如，第二发光控制信号EM2可以与第一发光控制信号EM1分别通过不同的发光控制线传输。
例如，第一复位子电路125与第一复位电压端Vinit1以及驱动子电路122的控制端122a(第一节点N1)连接，且配置为响应于第一复位控制信号Rst1将第一复位电压Vinit1施加至驱动子电路122的控制端122a。
例如，第二复位子电路129与第二复位电压端Vinit2以及发光器件20的第一端134(第四节点N4)连接，且配置为响应于第二复位控制信号Rst2将第二复位电压Vinit2施加至发光器件20的第一端134。
例如，第一复位子电路125和第二复位子电路129可以分别响应于第一复位控制信号Rst1和第二复位控制信号Rst2而开启，从而可以将分别将第二复位电压Vinit2施加至第一节点N1以及将第一复位电压Vinit1施加至发光器件20的第一端134，从而可以对驱动子电路122、补偿子电路128以及发光器件20进行复位操作，消除之前的发光阶段的影响。
例如，每行子像素的第二复位控制信号Rst2可以与该行子像素的第一扫描信号Ga1为相同的信号，二者可以通过同一栅线(例如图3A中的复位控制线220b)传输。例如，每行子像素的第一复位控制信号Rst1可以与上一行子像素的第一扫描信号Ga1，二者可以通过同一栅线(例如图3A中的复位控 制线220a)传输。
例如，如图2A，发光器件20包括第一端134和第二端135，发光器件20的第一端134配置为与驱动子电路122的第二端122c连接，发光器件20的第二端135配置为与第二电压端VSS连接。例如，在一个示例中，如图2A所示，发光器件20的第一端134可以通过第二发光控制子电路124连接至第四节点N4。本发明的实施例包括但不限于此情形。
需要注意的是，在本发明实施例的说明中，第一节点N1、第二节点N2、第三节点N3和第四节点N4并非一定表示实际存在的部件，而是表示电路图中相关电路连接的汇合点。
需要说明的是，在本发明的实施例的描述中，符号Vd既可以表示数据信号端又可以表示数据信号的电平，同样地，符号Ga1、Ga2既可以表示第一扫描信号、第二扫描信号，也可以表示第一扫描信号端和第二扫描信号端，符号Rst1既可以表示第一复位控制端又可以表示第一复位控制信号，符号Rst2既可以表示第二复位控制端又可以表示第二复位控制信号，符号Vinit1、Vinit2既可以表示第一复位电压端和第二复位电压端又可以表示第一复位电压和第二复位电压，符号VDD既可以表示第一电源电压又可以表示第一电源线，符号VSS既可以表示公共电源电压又可以表示公共电源线。以下各实施例与此相同，不再赘述。
图2B为图2A所示的像素电路的一种具体实现示例的电路图。如图2B所示，该像素电路包括第一至第七晶体管T1、T2、T3、T4、T5、T6、T7以及包括存储电容Cst。例如，第三晶体管T3被用作驱动晶体管，第一晶体管T1、第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管被用作开关晶体管。
例如，如图2B所示，驱动子电路122可以实现为第三晶体管T3。第三晶体管T3的栅极作为驱动子电路122的控制端122a，和第一节点N1连接；第三晶体管T3的第一极作为驱动子电路122的第一端122b，和第二节点N2连接；第三晶体管T3的第二极作为驱动子电路122的第二端122c，和第三节点N3连接。
例如，如图2B所示，数据写入子电路126可以实现为第四晶体管T4。第四晶体管T4的栅极T4g和第一扫描线(第一扫描信号端Ga1)连接以接收 第一扫描信号，第四晶体管T4的第一极T4s和数据线(数据信号端Vd)连接以接收数据信号，第四晶体管T4的第二极T4d和驱动子电路122的第一端122b(第二节点N2)连接。
例如，如图2B所示，补偿子电路128可以实现为第二晶体管T2。第二晶体管T2的栅极T2g、第一极T2s和第二极T2d分别作为该补偿子电路的控制端128a、第一端128b和第二端128c。第二晶体管T2的栅极配置为和第二扫描线(第二扫描信号端Ga2)连接以接收第二扫描信号，第二晶体管T2的第一极T2s和第三晶体管T3的第二极T3d(第三节点N3)连接，第二晶体管T2的第二极T3d和第三晶体管T3的栅极T1g(第一节点N1)电连接。例如，如图2B所示，存储子电路127可以实现为存储电容Cst，该存储电容Cst包括第一极板Cst1和第二极板Cst2，该第一极板Cst2和第一电压端vdd电连接，该第二极板Cst1和第三晶体管T3的栅极T1g(第一节点N1)电连接。
例如，如图2B所示，第一发光控制子电路123可以实现为第五晶体管T5。第五晶体管T5即第一发光控制晶体管。第五晶体管T5的栅极T5g和第一发光控制线(第一发光控制端EM1)连接以接收第一发光控制信号，第五晶体管T5的第一极T5s和第一电压端vdd连接以接收第一电源电压VDD，第五晶体管T5的第二极T5d和驱动子电路122的第一端122b(第二节点N2)连接。
例如，发光器件20具体实现为发光二极管(LED)，例如可以是有机发光二极管(OLED)、量子点发光二极管(QLED)或者无机发光二极管，例如可以是微型发光二极管(Micro LED)或者微型OLED。例如，发光器件20可以为顶发射结构、底发射结构或双面发射结构。该发光器件20可以发红光、绿光、蓝光或白光等。本发明的实施例对发光器件的具体结构不作限制。
例如，发光器件20的第一端包括第一显示电极21(如图4A所示)，该第一显示电极和第四节点N4连接配置为通过第二发光控制子电路124连接到驱动子电路122的第二端122c，发光器件20的第二端包括第二显示电极(例如为阴极)，该第二显示电极配置为和公共电源电压端VSS连接以接收公共电源电压VSS，从驱动子电路122的第二端122c流入发光器件20的电路决定发光器件的亮度。例如公共电源电压端VSS可以接地，即VSS可以为0V。例如，公共电源电压VSS可以为负电压。
例如，第二发光控制子电路124可以实现为第六晶体管T6。第五晶体管T6即第二发光控制晶体管。第六晶体管T6的栅极T6g和第二发光控制线(第二发光控制端EM2)连接以接收第二发光控制信号，第六晶体管T6的第一极T6s和驱动子电路122的第二端122c(第三节点N3)连接，第六晶体管T6的第二极T6d和发光器件20的第一端134(第四节点N4)连接。
例如，第一复位子电路125可以实现为第一晶体管T1，第二复位子电路129实现为第七晶体管T7。第一晶体管T1的栅极T1g配置为和第一复位控制端Rst1连接以接收第一复位控制信号Rst1，第一晶体管T1的第一极T1s和第一复位电压端Vinit1连接以接收第一复位电压Vinit1，第一晶体管T1的第二极T1d配置为和第一节点N1连接。第七晶体管T7的栅极T7g配置为和第二复位控制端Rst2连接以接收第二复位控制信号Rst2，第七晶体管T7的第一极T7s和第二复位电压端Vinit2连接以接收第二复位电压Vinit2，第七晶体管T7的第二极T7d配置为和第四节点N4连接。
需要说明的是，本发明的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本发明的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本发明的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)，关闭电压为高电平电压(例如，5V、10V或其他合适的电压)；当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其他合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)。例如，如图2B所示，该第一至第七晶体管T1-T7均为P型晶体管，例如为低温多晶硅薄膜晶体管。然而本发明实施例对晶体管的类型不作限制，当晶体管的类型发生改变时，相应地调整电路中的连接关系即可。
以下结合图2C所示的信号时序图，对图2B所示的像素电路的工作原理进行说明。如图2C所示，每一帧图像的显示过程包括三个阶段，分别为初始 化阶段1、数据写入及补偿阶段2、和发光阶段3。
例如，结合图2B和图3A-3B，第一扫描信号Ga1由第一扫描信号线Scan(P)(n)提供，第二扫描信号Ga2由第二扫描信号线Scan(N)(n)提供；第一发光控制信号EM1和第二发光控制信号EM2均由发光控制线EM(P)(n)提供。图2C为本发明至少一实施例提供的像素电路的驱动方法的信号时序图。如图2C所示，在本实施例中，第一扫描信号Ga1和第二扫描信号Ga2采同一信号，第一发光控制信号EM1和第二发光控制信号EM2采用同一信号。例如，第二复位控制信号Rst2和第一扫描信号Ga1/第二扫描信号Ga2也可以采用同一信号，也即第二复位控制信号Rst2和第一扫描信号Ga1/第二扫描信号Ga2的波形相同；即本行子像素的第一复位信号Rst1与上一行子像素的第一扫描信号Ga1/第二扫描信号Ga2的波形相同，也即采用同一信号。然而，这并不作为对本发明的限制，在其它实施例中，可以采用不同的信号分别作为第一扫描信号Ga1、第二扫描信号Ga2、第一复位控制信号Rst1、第二复位控制信号Rst2，采用不同的信号分别作为第一发光控制信号EM1和第二发光控制信号EM2。
在初始化阶段1，输入第一复位控制信号Rst1以开启第一晶体管T1，将第一复位电压Vinit1施加至第三晶体管T3的栅极，从而对该第一节点N1复位。
在数据写入及补偿阶段2，输入第一扫描信号Ga1、第二扫描信号Ga2(即补偿扫描信号)以及数据信号Vd，第四晶体管T4和第二晶体管T2开启，数据信号Vd由第四晶体管T4写入第二节点N2，并经过第三晶体管T3和第二晶体管T2对第一节点N1充电，直至第一节点N1的电位变化至Vd+Vth时第三晶体管T3截止，Vth为第三晶体管T3的阈值电压。该第一节点N1的电位存储于存储电容Cst中得以保持，也就是说将带有数据信号和阈值电压Vth的电压信息存储在了存储电容Cst中，以用于后续在发光阶段时，提供灰度显示数据和对第三晶体管T3自身的阈值电压进行补偿。
在数据写入补偿阶段2，还可以输入第二复位控制信号Rst2以开启第七晶体管T7，将第二复位电压Vinit2施加至第四节点N4，从而对该第四节点N4复位。例如，对该第四节点N4的复位也可以在初始化阶段1进行，例如，第一复位控制信号Rst1和第二复位控制信号Rst2可以相同。本发明实施例对 此不作限制。
在发光阶段3，输入第一发光控制信号EM1和第二发光控制信号EM2以开启第五晶体管T5、第六晶体管T6和第三晶体管T3，第六晶体管T6将驱动电流施加至OLED以使其发光。流经OLED的驱动电流Id的值可以根据下述公式得出：
Id＝K(VGS-Vth)2＝K[(Vd+Vth-VDD)-Vth]2＝K(Vd-VDD)2，其中，K为第一晶体管的导电系数。
在上述公式中，Vth表示第三晶体管T3的阈值电压，VGS表示第三晶体管T3的栅极和源极(这里为第一极)之间的电压，K为与第三晶体管T3本身相关的一常数值。从上述Id的计算公式可以看出，流经OLED的驱动电流Id不再与第三晶体管T3的阈值电压Vth有关，由此可以实现对该像素电路的补偿，解决了驱动晶体管(在本发明的实施例中为第三晶体管T3)由于工艺制程及长时间的操作造成阈值电压漂移的问题，消除其对驱动电流Id的影响，从而可以改善采用其的显示装置的显示效果。
图3A为本发明一实施例提供的一种显示基板的子像素的第一半导体层与第一导电层堆叠的平面示意图。图3B为本发明一实施例提供的一种显示基板的子像素的第二导电层和第二半导体层堆叠的平面示意图。图3C为本发明一实施例提供的一种显示基板的子像素的第一半导体层、第一导电层、第二导电层和第二半导体层堆叠的平面示意图。图3D为本发明一实施例提供的一种显示基板的子像素的第二导电层和第三导电层堆叠的平面示意图。图3E为本发明一实施例提供的一种显示基板的子像素的第一半导体层、第一导电层、第二导电层、和第二半导体层和第三导电层堆叠的平面示意图。图3F为本发明一实施例提供的一种显示基板的子像素的第一层间绝缘层和第四导电层堆叠的平面示意图。图3G为本发明一实施例提供的一种显示基板的子像素的第一半导体层、第一导电层、第二导电层、第二半导体层、第三导电层堆叠、第一层间绝缘层和第四导电层堆叠的平面示意图。图3H为本发明一实施例提供的一种显示基板的子像素的第一平坦层和第五导电层堆叠的平面示意图。图3I为本发明一实施例提供的一种显示基板的子像素的第一半导体层、第一导电层、第二导电层、第二半导体层、第三导电层堆叠、第一层间绝缘层、第四导电层、第一平坦层和第五导电层堆叠的平面示意图。图3J为本发明一 实施例提供的一种显示基板的子像素的第二平坦层、第一显示电极和像素界定层堆叠的平面示意图。图3K为本发明一实施例提供的一种显示基板的子像素的平面示意图，即子像素的第一半导体层、第一导电层、第二导电层、第二半导体层、第三导电层堆叠、第一层间绝缘层、第四导电层、第一平坦层、第五导电层、第二平坦层、第一显示电极和像素界定层堆叠的平面示意图。图4A为依次沿图3K中的第三晶体管、第六晶体管的有源层走向的一种截面示意图。图4B为一种显示基板的结构示意图。
结合图3A-3I、和图4A，该显示基板10包括衬底基板200、设置在衬底基板200上的整体上沿第二方向D2延伸的第一信号线和整体上沿与第二方向D2相交的第一方向D1延伸的第二信号线；例如，第一信号线与第二信号线相交以限定出多个子像素100。需要说明的是，该多个子像素的每个的边界未必是第一信号线和第二信号线，第一信号线与第二信号线相交以限定出子像素是指多个子像素是指多个子像素的排列方式与第一信号线与第二信号线相交而限定出的多个区域的排列方式一致，即多个子像素与通过第一信号线与第二信号线相交而限定出的多个区域一一对应。例如第一信号线是作为扫描信号线的栅线，第二信号线是数据线；或者，在其他一些实施例中，第一信号线是数据线，第二信号线是作为扫描信号线的栅线。
需要说明的是，本发明中的“整体上沿第二方向延伸”是指大致上沿第二方向延伸，至少整体上的延伸趋势是沿第二方向延伸即可。以第一信号线为例，例如，在一些示例中，该整体上沿第二方向延伸的第一信号线可以带有一定的弯曲部分，例如可以包括波浪形的部分；或者，在一些示例中，该整体上沿第二方向延伸的第一信号线的沿第二方向延伸的边缘可以不是平滑的线条，例如第一信号线的边缘可以具有毛刺或锯齿。总之，第一信号线满足整体上沿第二方向延伸的条形即可。同理，对于“整体上沿第一方向延伸”也是如此，例如数据线整体上沿第一方向延伸，再例如，下述的第一连接结构整体上沿第一方向延伸。
多个子像素中至少部分子像素的每个包括像素电路，像素电路包括上述发光器件20以及驱动晶体管T1、数据写入晶体管T2。例如至少部分子像素是指执行显示功能的子像素，非dummy子像素。
如图3F和图3I所示，像素电路还包括第一连接结构C1，第一连接结构 C1与驱动晶体管T3的栅极T3g以及存储电容Cst的第一极板Cst1连接，数据线Data和第一连接结构C1均整体上沿第一方向D1延伸，且数据线Data包括重叠部分D0，第一连接结构C1与数据线Data的重叠部分D0至少部分相对，即第一连接结构C1与数据线Data的重叠部分D0至少部分在第二方向D2上彼此相对设置，第二方向D2平行于衬底基板200且垂直于第一方向D1；例如，整个重叠部分D0与第一连接结构C1在第二方向D2上彼此相对设置。第一连接结构C1与数据线Data的重叠部分D0彼此绝缘，第一连接结构C1与数据线Data的重叠部分D0分别构成寄生电容Cgd的第一极板和第二极板；该寄生电容Cgd的电容值与存储电容Cst的电容值的比值大于0.001且小于0.01。由此，通过试验得到，当寄生电容Cgd的电容值与存储电容Cst的电容值的比值小于0.01的时候，充到存储电容Cgd的电压(也就是数据信号)最多损失1％(偏离1％)，使得OLED驱动电流最多损失1％(偏离1％)，从而控制发光亮度的偏差在很小的范围内。通过控制寄生电容Cgd的电容值与存储电容Cst的电容值的比值在该范围，能够在实现小的寄生电容Cgd的同时兼顾实现高PPI，显著降低在显示过程中数据线Data上的跳变电压对驱动晶体管T3的驱动电压产生的影响，从而实现较高的显示质量。
以一个子像素的为例，如图3K所示，例如，在至少一实施例中，一个子像素100的在第二方向D2上的尺寸S(Pixel Pitch)大于50μm，寄生电容Cgd的电容值与存储电容Cst的电容值的比值小于0.005。经试验得到，在子像素具有该尺寸设计的显示基板中，寄生电容Cgd的电容值与存储电容Cst的电容值的比值小于0.005能够显著降低，降低在显示过程中数据线Data上的跳变电压对驱动晶体管T3的驱动电压产生的影响，且兼顾实现高PPI，获得较好的显示效果。尤其是在大尺寸显示基板或显示面板中，例如大于55英寸的显示基板或显示面板，兼顾实现高PPI的前提下降低在显示过程中数据线Data上的跳变电压对驱动晶体管T3的驱动电压产生的影响效果尤为显著。
如图3K所示，例如，在至少一实施例中，一个子像素100的在第二方向D2上的尺寸S小于等于68μm，寄生电容Cgd的电容值与存储电容Cst的电容值的比值大于等于0.003。经试验得到，在子像素具有该尺寸设计的显示基板中，寄生电容Cgd的电容值与存储电容Cst的电容值的比值能够做到大于等于0.003，并且，在该情况下，能够显著降低显示过程中数据线Data上的 跳变电压对驱动晶体管T3的驱动电压产生的影响，且兼顾实现高PPI，获得较好的显示效果。尤其是在大尺寸显示基板或显示面板中，例如大于55英寸的显示基板或显示面板，兼顾实现高PPI的前提下降低在显示过程中数据线Data上的跳变电压对驱动晶体管T3的驱动电压产生的影响效果尤为显著。
如图3K所示，例如，在至少一实施例中，一个子像素100的在第二方向D2上的尺寸S小于50μm，寄生电容Cgd的电容值与存储电容Cst的电容值的比值大于0.005且小于0.006。经试验得到，在子像素具有该尺寸设计的显示基板中，单个子像素的尺寸较小，以实现高PPI，这种情况下，数据线Data上的跳变电压对驱动晶体管T3的驱动电压产生的影响更大，寄生电容Cgd的电容值与存储电容Cst的电容值的比值大于0004且小于0.006能够在降低显示过程中数据线Data上的跳变电压对驱动晶体管T3的驱动电压产生的影响的同时兼顾实现高PPI，在兼顾这两者的情况下获得比较优质的显示效果。尤其是在大尺寸显示基板或显示面板中，例如大于55英寸的显示基板或显示面板，兼顾实现高PPI的前提下降低在显示过程中数据线Data上的跳变电压对驱动晶体管T3的驱动电压产生的影响效果尤为显著。
图5为本发明一实施例提供的一种显示基板的相邻的至少两个子像素的平面示意图。图6是在图5的基础上移除了第一电源线VDD之后的示意图。例如，如图5-6所示，多个子像素100包括在第二方向D2上彼此相邻的第一子像素P1和第二子像素P2。在一个子像素中，例如在第一子像素P1中，第一连接结构C1包括沿第一方向D1延伸的第一部分C11和沿第二方向延伸的第二部分C12，第二部分C12与第一部分C11连接，第一部分C11的靠近数据线Data的重叠部分D0的边缘为第一边缘1a，第一部分C11还具有与远离数据线Data的重叠部分D0的第二边缘1b，数据线Data的重叠部分D0的靠近第一连接结构C1的边缘为第三边缘1c。对于相邻的第一子像素P1和第二子像素P2，第一子像素P1的第一连接结构C1的第二边缘1b在衬底基板200上的正投影到第二子像素P2的数据线Data的重叠部分D0的第三边缘1c在衬底基板200上的正投影的距离为第一距离L1，也即图4A和图6中的距离⑥，第一子像素P1的第一连接结构C1的第一边缘1a到第一子像素P1的数据线Data的重叠部分D0的第三边缘1c的距离为第二距离L2，也即图6中的距离⑦，第一距离L1与第二距离L2的比值大于14。如此，一方面可以保 证，本子像素的第一连接结构C1与相邻的子像素的数据线Data间隔开足够大的距离，的距离L1大于本子像素的第一连接结构C1与本子像素的数据线Data之间的距离L2的14倍。从而大大减小相邻的子像素的数据线Data对本子像素的第一连接结构C1形成的寄生电容Cgd，从而大大降低显示过程中数据线Data上的跳变电压对驱动晶体管T3的驱动电压产生的影响，提高显示质量。
例如，上述对于第一距离L1和第二距离L2的定义适用于显示基板的像素阵列里的任何一个子像素。因此，下文中对于第二子像素P2中第一距离L1的描述也是如此。
对比图4B所示的一种显示基板与本发明的图5-6所示的本申请的一实施例提供的显示基板可知，在图4B所示的显示基板中，在一个子像素的第一连接结构C1’的左右两侧距离其较近的位置，分别设置有一条数据线Data1’和Data2’，这导致第一连接结构C1’与其左右两侧的数据线Data1’和Data2’均会产生较大的寄生电容，严重影响显示质量。然而，在本发明的图5-6所示的本申请的一实施例提供的显示基板中，第一距离L1与第二距离L2的比值大于14，较好地避免了这一问题。
例如，在至少一实施例中，一个子像素100的在第二方向D2上的尺寸S小于50μm，第一距离L1与第二距离L2的比值大于14且小于15.5。试验证明，在子像素具有该尺寸S小于50μm设计的显示基板中，第一距离L1与第二距离L2的比值在大于14且小于15.5能够在实现小的寄生电容Cgd的同时兼顾实现高PPI，尤其是对于在大尺寸显示基板或显示面板中，例如大于55英寸的显示基板或显示面板，兼顾实现高PPI的前提下降低在显示过程中数据线Data上的跳变电压对驱动晶体管T3的驱动电压产生的影响效果尤为显著。
例如，在至少一实施例中，一个子像素100的在第二方向D2上的尺寸S大于50μm，例如，50μm<尺寸S<68μm，第一距离L1与第二距离L2的比值大于15.5。试验证明，在子像素具有该尺寸S小于50μm设计的显示基板中，第一距离L1与第二距离L2的比值在大于14且小于15.5能够在实现小的寄生电容Cgd的同时兼顾实现高PPI，尤其是对于在大尺寸显示基板或显示面板中，例如大于55英寸的显示基板或显示面板，兼顾实现高PPI的前提下降 低在显示过程中数据线Data上的跳变电压对驱动晶体管T3的驱动电压产生的影响效果尤为显著。
例如，在图5-6所示的实施例中，第一子像素P1的第一连接结构C1在第二方向D2上位于第一子像素P1的数据线Data1和第二子像素P2的数据线Data1之间。需要说明的是，图5-6中，位于第一子像素P1的数据线Data1的左侧且与之相邻的数据线Data2为在第一子像素P1的左侧与第一子像素P1相邻的子像素(未完整示出)的数据线，位于第二子像素P2的数据线Data1的右侧且与之相邻的数据线Data2为在第二子像素P2的右侧与第二子像素P2相邻的子像素(未完整示出)的数据线。例如，第一子像素P1的第一连接结构C1在衬底基板200上的正投影与第一子像素P1的数据线Data在衬底基板200上的正投影之间的距离小于一个子像素100的在第二方向D2上的尺寸，并且，第一子像素P1的第一连接结构C1在衬底基板200上的正投影与第二子像素P2的数据线Data在衬底基板200上的正投影之间的距离大于一个子像素100的在第二方向D2上的尺寸。例如，彼此相邻的第一子像素P1与第二子像素P2的至少第一连接结构C1和数据线Data相对于沿第一方向延伸的对称轴对称(镜像对称)。如此，可以更好地满足在尽量实现第一距离L1与第二距离L2的比值大于14即尽量增大第二子像素P1的数据线Data与第一子像素P1的第一连接结构C1之间的距离的情况下，充分利用在第一方向上的长度来设计像素电路的布局，以实现较高的PPI。
或者，在其他实施例中，例如，第一子像素P1的第一连接结构C1在衬底基板200上的正投影与第一子像素P1的数据线Data在衬底基板200上的正投影之间的距离小于一个子像素的在第二方向D2上的尺寸S，并且，第一子像素P1的第一连接结构C1在衬底基板200上的正投影与第二子像素P2的数据线Data在衬底基板200上的正投影之间的距离小于一个子像素100的在第二方向D2上的尺寸S。即，彼此相邻的第一子像素P1与第二子像素P2的至少第一连接结构C1和数据线Data相对于沿第一方向延伸的轴非对称(非镜像对称)。本发明实施例对像素电路的各个结构的具体位置不作限定，只要满足第一距离L1与第二距离L2的上述关系即可。
例如，如图5-6所示，第一子像素P1的驱动晶体管T3的栅极T3g的靠近第二子像素P2的数据线Data的重叠部分D0的边缘为第四边缘1d；第一 子像素P1的第二边缘1b到第二子像素P2的第三边缘1c的距离等于第一子像素P1的第二边缘1b到第一子像素P1的第四边缘1d的距离与第一子像素P1的第四边缘1d到第二子像素P2的第三边缘1c的距离之和。
例如，参考图4A，第一连接结构C1与数据线Data异层设置，第一连接结构C1在衬底基板200上的正投影与数据线Data的重叠部分D0在衬底基板200上的正投影不重叠。或者，在其他一些实施例中，第一连接结构C1与数据线Data异层设置，第一连接结构C1在衬底基板200上的正投影与数据线Data的重叠部分D0在衬底基板200上的正投影至少部分重叠。
图4C为一种电极正对平板电容的示意图；图4D为一种电极斜置平板电容的示意图。参考图4C，正对平板电容是指平板电容的两个极板，例如电极1和电极2，彼此正对，也即电极1和电极2彼此相对的面彼此平行且电极1和电极2在与这二者彼此相对的面平行的面上的正投影重叠。参考图4D，电极斜置平板电容是指平板电容的两个极板例如电极1和电极2，彼此相对的面彼此平行且电极1和电极2在与这二者彼此相对的面平行的面上的正投影部分重叠或不重叠。本发明的权利要求的保护范围所涉及的寄生电容的电容值，以说明书的下文所公开的计算方法为准。
对于图4C所示的电极正对平板电容和图4D所示的电极斜置平板电容，电极1和电极2作为两个电容极板而形成的平板电容C满足公式(1)：
C＝ε×A/d       公式(1)
其中，A代表两个电极1和电极2彼此交叠的表面积，d代表电力线走过的距离。根据公式(1)，图4A所示的实施例中，
Cgd代表寄生电容Cgd的电容值，Cgd满足公式(2)：
Cgd＝ε×A/d＝εPI×(Wsd1×wsd1)/(t2 PLN1+d2 sd1)1/2公式(2)，其中，
参考图4A，εPI代表位于数据线Data的重叠部分D0与第一连接结构C1之间的介质的介电常数。
A代表数据线Data的重叠部分D0与第一连接结构C1的等效交叠面积。如图4D所示，在电极斜置平板电容中，在等效交叠面积为电极1和电极2彼此相对且均分布有电力线的表面的面积；例如，在数据线Data的重叠部分D0在衬底基板200上的正投影与第一连接结构C1在衬底基板200上的正投影不重叠时或至少部分重叠时，数据线Data的重叠部分D0和第一连接结构C1分别相当于图4D中的电极1和电极2。
d代表代表电力线走过的距离。
Wsd1代表第一连接结构C1在第二方向D2上的宽度，即距离⑤。
wsd1代表第一连接结构C1在第一方向D1上的长度。
tPLN1代表第一连接结构C1与数据线Data在垂直于衬底基板200的方向上的距离。
dsd1代表在一个子像素中第一连接结构C1的第一边缘1a与数据线Data的第三边缘1c之间的距离，即第二距离L2。
下面以一个示例对一个子像素中相邻的第一连接结构C1与数据线Data的重叠部分D0分别构成寄生电容Cgd进行计算。其他平板电容可参考该计算方法。
例如，在一个示例中，参考图4A和图6，以图4A为第二子像素P2的截面图为例，S＝51.4μm(大于50μm)，Cst＝42fF。各间距如下。
①代表第一子像素P1的数据线Data1与和第一子像素P1相邻且与第一子像素P1非对称的子像素的数据线Data2之间的间距(彼此相邻的第一子像素P1和第二子像素P2构成一个重复单元，在第一子像素P1的远离第二子像素P2的一侧与第一子像素P1相邻的该子像素属于另一个重复单元)，例如①＝3.4μm。
②代表第二子像素P2中数据线Data1与驱动晶体管T3的栅极T3g彼此靠近的边之间的间距，例如②＝1.4μm。
③代表驱动晶体管T3的栅极T3g在第二方向D2上的宽度，例如③＝11.5μm。
④代表第二子像素P2的驱动晶体管T3的栅极T3g上方的第一连接结构C1的第一边缘1a到驱动晶体管T3的栅极T3g的靠近第二子像素P2的数据线Data1之间的间距，例如④＝4μm。
⑤代表驱动晶体管T3的栅极T3g的第一连接结构C1的在第二方向D1上的宽度，例如⑤＝5.4μm。
⑥代表在一个子像素例如第二子像素P2中，第一连接结构C1的第二边缘1b到第一子像素P1的数据线Data1的重叠部分D0的第三边缘1c的距离，即上述第一距离L1，例如，在本示例中，⑥＝②+④＝5.4μm。
⑦代表第一子像素P1的第一连接结构C1的第一边缘1a在衬底基板200 上的正投影到第二子像素P2的数据线Data1的重叠部分D0的第三边缘1c在衬底基板200上的正投影的距离，即第二距离L2，例如，在本示例中，一条数据线Data1的线宽Data Width(例如多条数据线的线宽基本相等)＝2.5μm，从而⑦＝2×S-①-2×Data Width(数据线的线宽，例如多条数据线的线宽基本相等)-⑥-⑤＝2×51.4-3.4-2×2.5-5.4-5.4＝83.6μm。
从而，⑦/⑥＝15.48，即L2/L1＝15.48，满足第一距离L1与第二距离L2的比值大于14。
在上述尺寸的基础上，例如，εPI＝4.0，tPLN1＝1.24μm，dsd1＝L2＝⑥＝5.4μm，Wsd1＝5.4μm，wsd1＝5.4μm。
例如，在图5所示的彼此相邻的第一子像素P1与第二子像素P2的第一连接结构C1和数据线Data相对于沿第一方向延伸的对称轴镜像对称的情况下，一个子像素的第一连接结构C1只与在第二方向D2上位于其一侧的数据线Data形成寄生电容Cgd，因此，计算所得Cgd＝0.186fF，远小于Cst＝42fF，Cgd/Cst＝4.4×10-3，寄生电容Cgd的电容值与存储电容Cst的电容值的比值小于0.005。
例如，在彼此相邻的第一子像素P1与第二子像素P2的第一连接结构C1和数据线Data呈非镜像对称的情况下，例如在一个子像素的第一连接结构C1的在第二方向D2上的两侧距离第一连接结构C1基本相等的位置处分别设置一条数据线Data，从而形成的寄生电容近似两倍镜像设计时的寄生电容，即Cgd＝2×0.186fF＝0.11fF，Cgd/Cst＝8.8×10-3。与非镜像设计相比，上述其他条件相同的镜像设计中的寄生电容Cgd的电容值与存储电容Cst的电容值的比值较小，这种情况下的显示面板的数据线Data上的跳变电压对驱动晶体管T3的驱动电压产生的影响较小，表现的显示效果较优。
例如，在另一示例中，参考图4A和图6，以图4A为第二子像素P2的截面图为例，S＝45.2μm(小于50μm)，Cst＝29.2fF。按照同样地设计规则，下述各个距离按本示例中S的值与S＝51.4的示例中S的值的比作为参考进行计算，由此，各间距如下。
①代表第一子像素P1的数据线Data1与和第一子像素P1相邻且与第一子像素P1非对称的子像素的数据线Data2之间的间距(彼此相邻的第一子像素P1和第二子像素P2构成一个重复单元，在第一子像素P1的远离第二子像 素P2的一侧与第一子像素P1相邻的该子像素属于另一个重复单元)，例如①＝3.4×45.2/51.4＝3μm。
⑤代表驱动晶体管T3的栅极T3g的第一连接结构C1的在第二方向D1上的宽度，例如⑤＝5.4×45.2/51.4＝4.75μm。
⑥代表在一个子像素例如第二子像素P2中，第一连接结构C1的第二边缘1b到第一子像素P1的数据线Data1的重叠部分D0的第三边缘1c的距离，即上述第一距离L1，例如，在本示例中，⑥＝5.4×45.2/51.4＝4.75μm。
⑦代表第一子像素P1的第一连接结构C1的第一边缘1a在衬底基板200上的正投影到第二子像素P2的数据线Data1的重叠部分D0的第三边缘1c在衬底基板200上的正投影的距离，即第二距离L2，例如，在本示例中，一条数据线Data1的线宽Data Width(例如多条数据线的线宽基本相等)＝2.5μm，从而⑦＝2×S-①-2×Data Width-⑥-⑤＝2×45.2-3-2×2.5-4.75-4.75＝73.9μm。
从而，⑦/⑥＝15.56，即L2/L1＝15.56，满足第一距离L1与第二距离L2的比值大于14。
在上述尺寸的基础上，例如，εPI＝4.0，tPLN1＝1.05μm，dsd1＝L2＝⑥＝5.4×45.2/51.4＝4.75μm，Wsd1＝5.4×45.2/51.4＝4.75μm，wsd1＝4.75μm。
例如，在图5所示的彼此相邻的第一子像素P1与第二子像素P2的第一连接结构C1和数据线Data相对于沿第一方向延伸的对称轴镜像对称的情况下，一个子像素的第一连接结构C1只与在第二方向D2上位于其一侧的数据线Data形成寄生电容Cgd，因此，计算所得Cgd＝0.168fF，远小于Cst＝29.2fF，Cgd/Cst＝5.75×10-3，寄生电容Cgd的电容值与存储电容Cst的电容值的比值大于0.005。
例如，在彼此相邻的第一子像素P1与第二子像素P2的第一连接结构C1和数据线Data呈非镜像对称的情况下，例如在一个子像素的第一连接结构C1的在第二方向D2上的两侧距离第一连接结构C1基本相等的位置处分别设置一条数据线Data，从而形成的寄生电容近似两倍镜像设计时的寄生电容，即Cgd＝2×0.168fF＝0.33fF，Cgd/Cst＝10×10-3。与非镜像设计相比，上述其他条件相同的镜像设计中的寄生电容Cgd的电容值与存储电容Cst的电容值的比值较小，这种情况下的显示面板的数据线Data上的跳变电压对驱动晶体管T3的驱动电压产生的影响较小，表现的显示效果较优。
例如，在又一示例中，参考图4A和图6，以图4A为第二子像素P2的截面图为例，S＝68μm，Cst＝51.4fF。各间距如下。
①代表第一子像素P1的数据线Data1与和第一子像素P1相邻且与第一子像素P1非对称的子像素的数据线Data2之间的间距(彼此相邻的第一子像素P1和第二子像素P2构成一个重复单元，在第一子像素P1的远离第二子像素P2的一侧与第一子像素P1相邻的该子像素属于另一个重复单元)，例如①＝5.3μm。
②代表第二子像素P2中数据线Data1与驱动晶体管T3的栅极T3g彼此靠近的边之间的间距，例如②＝2.9μm。
③代表驱动晶体管T3的栅极T3g在第二方向D2上的宽度，例如③＝12μm。
④代表第二子像素P2的驱动晶体管T3的栅极T3g上方的第一连接结构C1的第一边缘1a到驱动晶体管T3的栅极T3g的靠近第二子像素P2的数据线Data1之间的间距，例如④＝4.3μm。
⑤代表驱动晶体管T3的栅极T3g的第一连接结构C1的在第二方向D1上的宽度，例如⑤＝7.5μm。
⑥代表在一个子像素例如第二子像素P2中，第一连接结构C1的第二边缘1b到第一子像素P1的数据线Data1的重叠部分D0的第三边缘1c的距离，即上述第一距离L1，例如，在本示例中，⑥＝②+④＝7.2μm。
⑦代表第一子像素P1的第一连接结构C1的第一边缘1a在衬底基板200上的正投影到第二子像素P2的数据线Data1的重叠部分D0的第三边缘1c在衬底基板200上的正投影的距离，即第二距离L2，例如，在本示例中，一条数据线Data1的线宽Data Width(例如多条数据线的线宽基本相等)＝2.4μm，从而⑦＝2×S-①-2×Data Width(数据线的线宽，例如多条数据线的线宽基本相等)-⑥-⑤＝2×68-5.3-2×2.4-7.2-4.3＝114.4μm。
从而，⑦/⑥＝15.9，即L2/L1＝15.9，满足第一距离L1与第二距离L2的比值大于14。
在上述尺寸的基础上，例如，εPI＝4.0，tPLN1＝1.24μm，dsd1＝L2＝⑥＝7.2μm，Wsd1＝7.5μm，wsd1＝4.3μm。
例如，在图5所示的彼此相邻的第一子像素P1与第二子像素P2的第一 连接结构C1和数据线Data相对于沿第一方向延伸的对称轴镜像对称的情况下，一个子像素的第一连接结构C1只与在第二方向D2上位于其一侧的数据线Data形成寄生电容Cgd，因此，计算所得Cgd＝0.155fF，远小于Cst＝51.4fF，Cgd/Cst＝3×10-3，即在S＝68μm的情况下，寄生电容Cgd的电容值与存储电容Cst的电容值的比值等于0.003。当S小于68μm时，即单个子像素的宽度较小，为了实现高PPI，空间的局限性较大，因此，可以满足寄生电容Cgd的电容值与存储电容Cst的电容值的比值小于0.003。
例如，在彼此相邻的第一子像素P1与第二子像素P2的第一连接结构C1和数据线Data呈非镜像对称的情况下，例如在一个子像素的第一连接结构C1的在第二方向D2上的两侧距离第一连接结构C1基本相等的位置处分别设置一条数据线Data，从而形成的寄生电容近似两倍镜像设计时的寄生电容，即Cgd＝2×0.155fF＝0.31fF，Cgd/Cst＝6×10-3。与非镜像设计相比，上述其他条件相同的镜像设计中的寄生电容Cgd的电容值与存储电容Cst的电容值的比值较小，这种情况下的显示面板的数据线Data上的跳变电压对驱动晶体管T3的驱动电压产生的影响较小，表现的显示效果较优。
例如，在再一示例中，参考图4A和图6，以图4A为第二子像素P2的截面图为例，S＝49.3μm(小于50μm)，Cst＝44.8fF。各间距如下。
①代表第一子像素P1的数据线Data1与和第一子像素P1相邻且与第一子像素P1非对称的子像素的数据线Data2之间的间距(彼此相邻的第一子像素P1和第二子像素P2构成一个重复单元，在第一子像素P1的远离第二子像素P2的一侧与第一子像素P1相邻的该子像素属于另一个重复单元)，例如①＝3.3μm。
②代表第二子像素P2中数据线Data1与驱动晶体管T3的栅极T3g彼此靠近的边之间的间距，例如②＝12.5μm。
③代表驱动晶体管T3的栅极T3g在第二方向D2上的宽度，例如③＝11.7μm。
④代表第二子像素P2的驱动晶体管T3的栅极T3g上方的第一连接结构C1的第一边缘1a到驱动晶体管T3的栅极T3g的靠近第二子像素P2的数据线Data1之间的间距，例如④＝3.3μm。
⑤代表驱动晶体管T3的栅极T3g的第一连接结构C1的在第二方向D1 上的宽度，例如⑤＝6μm。
⑥代表在一个子像素中，第一连接结构的远离该子像素中的数据线的重叠部分的边缘到与该子像素相邻的子像素的数据线的重叠部分的边缘的距离，例如，在本示例中，⑥＝2μm。
⑦代表第一子像素P1的第一连接结构C1的第一边缘1a在衬底基板200上的正投影到第二子像素P2的数据线Data1的重叠部分D0的第三边缘1c在衬底基板200上的正投影的距离，即第二距离L2，例如，在本示例中，一条数据线Data1的线宽Data Width(例如多条数据线的线宽基本相等)＝2.4μm，从而⑦＝28.3μm。
从而，⑦/⑥＝14.15，即L2/L1＝14.15，满足第一距离L1与第二距离L2的比值大于14。
在上述尺寸的基础上，例如，εPI＝4.0，tPLN1＝1.36μm，dsd1＝L2＝⑥＝4μm，Wsd1＝6μm，wsd1＝9μm。
例如，在图5所示的彼此相邻的第一子像素P1与第二子像素P2的第一连接结构C1和数据线Data相对于沿第一方向延伸的对称轴镜像对称的情况下，一个子像素的第一连接结构C1只与在第二方向D2上位于其一侧的数据线Data形成寄生电容Cgd，因此，计算所得Cgd＝0.24fF，远小于Cst＝44.8fF，Cgd/Cst＝5.4×10-3，即在S小于50μm的情况下，寄生电容Cgd的电容值与存储电容Cst的电容值的比值大于0.005且小于0.006。当S小于50μm时，即单个子像素的宽度更小，为了实现高PPI，空间的局限性进一步增大，因此，可以满足寄生电容Cgd的电容值与存储电容Cst的电容值的比值小于0.003。
例如，在彼此相邻的第一子像素P1与第二子像素P2的第一连接结构C1和数据线Data呈非镜像对称的情况下，例如在一个子像素的第一连接结构C1的在第二方向D2上的两侧距离第一连接结构C1基本相等的位置处分别设置一条数据线Data，从而形成的寄生电容近似两倍镜像设计时的寄生电容，即Cgd＝2*0.24fF＝0.48fF，Cgd/Cst＝10.8×10-3。与非镜像设计相比，上述其他条件相同的镜像设计中的寄生电容Cgd的电容值与存储电容Cst的电容值的比值较小，这种情况下的显示面板的数据线Data上的跳变电压对驱动晶体管T3的驱动电压产生的影响较小，表现的显示效果较优。
上述实施例以第一连接结构C1与数据线Data异层设置为例。当然，在 其他一些实施例中，第一连接结构C1可以与数据线Data同层设置，第一连接结构C1与数据线Data的重叠部分D0在第二方向D2上彼此相对。本发明不限于第一连接结构C1与数据线Data是异层设置，只要满足第一距离L1与第二距离L2的比值大于14即可。
图4E是本发明一实施例提供的一种显示基板的再一种截面示意图。例如，在至少一实施例中，如图4E所示，存储电容Cst的第一极板Cst1具有远离衬底基板200的上表面T01和与上表面T01相交的侧表面S01。存储电容Cst的第二极板Cst2包括中间部分CM和边缘部分CP。中间部分CM在衬底基板200上的正投影与存储电容Cst的第一极板Cst1在衬底基板200上的正投影至少部分重合，且中间部分CM包括与存储电容Cst的第一极板Cst1的上表面T01相对的底面B01；边缘部分CP至少部分围绕中间部分CM且与中间部分CM连接，且边缘部分CP包括靠近衬底基板200的底面B02和与底面B02相交的内侧面S02，内侧面S02与存储电容Cst的第一极板Cst1的侧表面S01彼此相对，且内侧面S02在垂直于衬底基板200的参考面上的正投影与，与该内侧面S02相对的存储电容Cst的第一极板Cst1的侧表面S01，在参考面上的正投影至少部分重叠；边缘部分CP的内侧面S02与，与内侧面S02相对的存储电容Cst的第一极板Cst1的侧表面，之间的距离S1小于中间部分CM的底面与存储电容Cst的第一极板Cst1的上表面之间的距离S2，以使得利用有限的空间实现更大的存储电容Cst的电容值，提高存储电容Cst的电荷存储能力，也有利于降低第一连接结构C1与数据线Data的重叠部分D0所形成的寄生电容Cgd与存储电容Cs的比值，降低寄生电容Cgd对显示效果的影响，提高显示效果。
为了清楚地描述子像素的结构特征，下面以一个示例对子像素的各个层的结构进行介绍。
结合图3A-3I和图4A，例如，该显示基板10包括设置于衬底基板200上且沿远离衬底基板200的方向依次排列的第一半导体层Active1、第一导电层Gate1、第二导电层Gate2、第二半导体层Active2、第三导电层堆叠Gate3、层间绝缘层ILD、第四导电层SD1、第一平坦层PLN1、第五导电层SD2。
如图3A所示，第一信号线包括第一扫描信号线Scan(P)(n)、发光控制线EM(P)(n)和第二复位扫描信号线Scan(P)(n+1)。例如，第一扫描信号线 Scan(P)(n)、发光控制线EM(P)(n)和第二复位扫描信号线Scan(P)(n+1)位于第一导电层Gate1，且整体上均沿第二方向D2延伸。驱动晶体管T3包括栅极T3g，例如驱动晶体管T3的栅极T3g也位于第一导电层Gate1；例如驱动晶体管T3的栅极T3g与电容的第一极板Cst1为连续的一体成型结构，如此，第一扫描信号线Scan(P)(n)、发光控制线EM(P)(n)和第二复位扫描信号线Scan(P)(n+1)、驱动晶体管T3的栅极T3g、存储电容Cst的第一极板Cst1同层设置。第一扫描信号线Scan(P)(n)的与第一半导体层Active1交叠的部分构成第四晶体管T4的栅极T4g；发光控制线EM(P)(n)的与第一半导体层Active1交叠的两个部分分别构成第五晶体管T5的栅极T5g和第六晶体管T6的栅极T6g，第五晶体管T5和第六晶体管T6作为发光控制晶体管，第五晶体管T5为第一发光控制晶体管，第六晶体管T6为第二发光控制晶体管；第二复位扫描信号线Scan(P)(n+1)的与第一半导体层Active1交叠的部分构成第七晶体管T7的栅极T7g，第七晶体管T7作为第二复位晶体管。从而，第一半导体层Active1包括驱动晶体管T3的有源层A3、第四晶体管T4的有源层A4、第五晶体管T5的有源层A5、第六晶体管T6的有源层A6和第七晶体管T7的有源层A7。由此，驱动晶体管T3的栅极T3g和存储电容Cst的第一极板Cst1位于驱动晶体管T3的有源层A3的远离衬底基板200的一侧。
例如，第三晶体管T3作为像素电路的驱动晶体管T3，第四晶体管T4作为像素电路的数据写入晶体管T4。驱动晶体管T3配置为控制发光器件20发光；数据线Data与数据写入晶体管T4的第一极连接且配置为给数据写入晶体管T4提供数据信号，数据写入晶体管T4配置为响应于施加在数据写入晶体管T4的栅极的第一扫描信号而将数据信号Vd写入驱动晶体管T3的栅极T3g；例如，数据写入晶体管T2配置为第一扫描信号Ga1的控制下将数据信号Vd传输至驱动晶体管T1，第一扫描信号Ga1在第一扫描信号线Scan(P)(n)上传输，数据信号Vd在第二信号线上传输。
本申请中的附图标记Data、Data1和Data2用于指代不同实施例中或不同子像素的数据线，具体可参照相应的附图。
如图3B所示，例如，第一信号线还包括第二扫描信号线Scan(N)(n)、第一复位扫描信号线Scan(N)(n-1)。例如，第二扫描信号线Scan(N)(n)和第一复位扫描信号线Scan(N)(n-1)位于第二导电层Gate2。第二扫描信号线Scan(N)(n) 的与第二半导体层Active2交叠的部分构成第二晶体管T2的栅极T2g，第二晶体管T2作为补偿晶体管；第一复位扫描信号线Scan(N)(n-1)的与第二半导体层Active2交叠的部分构成第一晶体管T1的栅极T1g，第一晶体管T1作为第一复位晶体管。从而，第二半导体层Active2包括第一晶体管T1的有源层A1和第二晶体管T2的有源层A2。
例如，这里说的第一到第七晶体管的有源层A1～A7是指用于形成第一到第七晶体管的半导体层的与各个晶体管的栅极重叠的部分。
第二扫描信号线Scan(N)(n)作为补偿扫描信号线，第二扫描信号线Scan(N)(n)配置为给补偿晶体管T2的栅极T2g施加第二扫描信号Ga2(即补偿扫描信号)，补偿晶体管T2的配置为响应于第二扫描信号Ga2对驱动晶体管T3进行阈值补偿。
例如，如图3B所示，显示基板10还包括第一复位信号线Vini_N1。例如，第一复位信号线Vini_N1位于第二导电层Gate2。第一复位扫描信号线Scan(N)(n-1)配置为给第一复位晶体管T1的栅极T1g提供第一复位扫描信号，即第一复位控制信号Rst1，第一复位晶体管T1的第一极T1s与驱动晶体管T3的栅极T3g电连接，第一复位晶体管T1的第二极T1d被配置为与第一复位信号线Vini_N1电连接以接收第一复位信号例如第一复位电压Vinit1，第一复位晶体管T1配置为响应于第一复位控制信号Rst1，将第一复位电压Vinit1写入驱动晶体管T3的栅极T3g。
如图3F，显示基板10还包括第二复位信号线Vini_OLED。例如，第二复位信号线Vini_OLED位于第四导电层SD1。第二复位扫描信号线Scan(P)(n+1)配置为给第二复位晶体管T7的栅极T7g提供第二复位扫描信号Rst2，第二复位晶体管T7的第一极T7s与发光器件20的第一显示电极21电连接，第二复位晶体管T7的第二极T7d被配置为与第二复位信号线Vini_OLED电连接以接收第二复位信号例如第二复位电压Vinit2，第二复位晶体管T7配置为响应于第二复位扫描信号Rst2将第二复位信号写入发光器件20的第一显示电极21。
例如，如图3B所示，补偿晶体管T2的有源层A2与第一复位晶体管T1的有源层A1构成一体成型结构AL1，该一体成型结构AL1沿第一方向D1延伸，由此，也可以说第一复位晶体管T1的有源层A1沿第一方向D1延伸， 或者补偿晶体管T2的有源层A2沿第一方向D1延伸。例如，如图3C所示，第一半导体层Active1在衬底基板200上的正投影与第二半导体层Active2在衬底基板200上的正投影不存在重叠，以使得分别基于第一半导体层Active1和第二半导体层Active2形成的晶体管之间彼此不会互相干扰。
例如，第一半导体层Active1的材料与第二半导体层Active2的材料不同。例如，第一半导体层Active1的材料包括但不限于硅基材料(非晶硅a-Si，多晶硅p-Si等)。例如，第一半导体层Active1的材料为低温多晶硅(LTPS)。例如，第二半导体层Active2的材料为氧化物半导体，例如氧化铟镓锌(IGZO)、氧化锌(ZnO)，AZO，IZTO等。当然，第一半导体层Active1的材料的种类和第二半导体层Active2的材料的种类不限于上述列举的种类，本发明实施例对此不作限定。由此，位于第一半导体层Active1的有源层与位于第二半导体层Active2的有源层的材料不同且异层设置，例如第一复位晶体管T1的有源层A1与驱动晶体管T3的有源层A3的材料不同且异层设置。
例如，至少一实施例中，对于图2B所示的7T1C像素电路中，驱动晶体管T3、数据写入晶体管T4、第一发光控制晶体管T5和第二发光控制晶体管T6、对发光器件进行复位的第二复位晶体管T7是采用LTPS材料制作有源层的P型晶体管，因为采用LTPS材料制作有源层的P型晶体管具有更高的迁移率和更稳定的源极电压，适合驱动有机发光二极管例如OLED；对驱动晶体管T3进行复位的第一复位晶体管T1和补偿晶体管T2是采用氧化物半导体材料制作有源层的N型晶体管，因为采用氧化物半导体材料制作有源层的N型晶体管具有更低的漏电流，可以更好地保持驱动晶体管T3和存储电容Cst的电压稳定。当然，在其他实施例中，像素电路的每个晶体管的类型、以及有源层的材料不局限于上述示例中的情况，本发明实施例对此不作限定。
结合图3B和图5，多个子像素100包括第三子像素P3，信号线Scan(N)(n+1)是第三子像素P3的第一复位扫描信号线，信号线Vini_N1'是第三子像素P3的第一复位信号线，第三子像素P3与第二子像素P2在第一方向D1上相邻。例如图3A-3K所示的完整的像素电路是第二子像素P2的像素电路，同时又涉及到与第二子像素P2相邻的子像素例如第三子像素P3的像素电路的一部分结构。图3B中的第二扫描信号线Scan(N)(n)、第一复位扫描信号线Scan(N)(n-1)和第一复位信号线Vini_N1等均属于第二子像素P2。
例如，如图3F和图3G所示，第二复位信号线Vini_OLED的位于一个子像素100的部分包括横向部分VS1和第一纵向部分VS2，横向部分VS1沿第二方向D2延伸且具有在第二方向D2上彼此相对的第一端和第二端，第一纵向部分VS2与横向部分VS1的在第二方向D2上的第一端连接且沿第一方向D1延伸，并且，以图5所示的第二子像素P2和第三子像素P3作为在第一方向D1上相邻的两个子像素为例，在图3F和图3G中，第二子像素P2的第二复位信号线Vini_OLED的横向部分VS1在衬底基板200上的正投影与第三子像素P3的第一复位扫描信号线Scan(N)(n+1)在衬底基板200上的正投影至少部分重叠，第二子像素P2的第二复位信号线Vini_OLED的第一纵向部分VS2与第三子像素P3的第一复位晶体管的有源层在第二方向D2上间隔排列，即第一纵向部分VS2与第二半导体层Active2中补偿晶体管的有源层与第一复位晶体管的有源层构成的一体成型结构A31在第二方向D2上间隔排列(由于每个子像素的像素电路结构为重复单元，因此，第三子像素P3中的一体成型结构A31可参考上述图3G中位于较为下方的作为第二子像素P2的子像素中的一体成型结构AL在子像素中的位置)，从而第二复位信号线Vini_OLED的沿第一方向D1延伸的第一纵向部分VS2避开第二半导体层Active2，即第一纵向部分VS2在衬底基板200上的正投影与第二半导体层Active2在衬底基板200上的正投影不存在交叠，以避免二者之间产生信号干扰，避免第二复位信号线Vini_OLED对补偿晶体管T2的有源层A2的影响，使得采用氧化物半导体材料作为有源层的补偿晶体管T2具有稳定的较高的开态电流和较低的漏电流；保证与驱动晶体管T3的栅极连接的第一节点N1和存储电容Cst的电压更加稳定，不容易漏电，从而驱动晶体管T3的驱动电流更加稳定，发光器件20的发光效率更加稳定，采用显示基板的显示装置的显示品质得到提高。尤其是在第二复位信号线Vini_OLED和第二半导体层Active2在垂直于衬底基板200的主表面的方向上位置比较靠近的情况下。并且，特征“第二复位信号线Vini_OLED的横向部分VS1在衬底基板200上的正投影与第三子像素P3的第一复位扫描信号线Scan(N)(n+1)在衬底基板200上的正投影至少部分重叠”可以减少扫描信号线所占用的面积，提高显示基板的开口率。例如，如图3F-3G所示，第二子像素P2的第二复位信号线Vini_OLED的第一纵向部分VS2对应与第三子像素P3的用于形成第一复位晶体管T1的有源层 A1的一体成型结构AL1在第二方向D2上间隔排列，即第二子像素P2的第二复位信号线Vini_OLED的第一纵向部分VS2避开第三子像素P3的第一复位晶体管T1的有源层A1，以利用有限的空间优化多个子像素的像素电路结构之间的位置关系设计，排布紧凑，实现高PPI。
例如，如图3I所示，第二复位信号线Vini_OLED的对应于一个子像素100的子部的平面图形呈倒置的“几”字形；该“几”字形的子部不仅可以实现上述避开第二半导体层Active2的效果，并且，该“几”字形的子部还包括U形凹槽，第二复位信号线Vini_OLED的横向部分VS1作为该U形凹槽的底部，在的U形凹槽中可设置其他走线，合理利用空间，提高结构的紧凑性。
例如，如图3I所示，第二复位信号线Vini_OLED的位于一个子像素100的子部分还包括第二纵向部分VS3，第二纵向部分VS3与横向部分VS1的在第二方向D2上的第二端连接且沿第一方向D1延伸，第二复位晶体管T7的有源层A7位于第一纵向部分VS2与第二纵向部分VS3之间，并且，在同一个子像素100中，在第二方向D2上，第一纵向部分VS2到数据线Data的距离大于第二纵向部分VS3到数据线Data的距离。第三子像素P3的第二复位晶体管T7的有源层到第二子像素P2的第二复位信号线Vini_OLED的第一纵向部分VS2的距离小于第三子像素P3的第二复位晶体管T7的有源层到第二子像素P2的第二复位信号线Vini_OLED的第二纵向部分VS3的距离，以在使得第二复位信号线Vini_OLED的第一纵向部分VS2避开第二半导体层Active2的同时，合理利用有限的空间，避免信号线排布过于密集。
如图3B所示，存储电容Cst的第二极板Cst2位于第二导电层Gate2，与第二扫描信号线Scan(N)(n)、第一复位扫描信号线Scan(N)(n-1)同层设置。第二扫描信号线Scan(N)(n)即补偿扫描信号线。由此，存储电容Cst的第二极板Cst2位于驱动晶体管T3的栅极T3g和存储电容Cst的第一极板Cst1的远离衬底基板200的一侧，补偿扫描信号线与存储电容Cst的第二极板Cst2同层设置，第一复位信号线Vini_N1与存储电容Cst的第二极板Cst2同层设置；补偿晶体管T2的有源层A2位于第二半导体层Active2，从而存储电容Cst的第二极板Cst2的远离衬底基板200的一侧。
如图3F-3G所示，第二复位信号线Vini_OLED位于第四导电层SD1，由此，第二复位信号线Vini_OLED位于补偿晶体管T2的有源层A2的远离衬底 基板200的一侧。
图7A为依次沿图3K中的第四晶体管、第三晶体管、第二晶体管、第一晶体管的有源层走向在第一视角的截面示意图。图7B为依次沿图3K中的第四晶体管、第三晶体管、第二晶体管、第一晶体管的有源层走向在第二视角的截面示意图。例如，参考图3E和图7A-7B，补偿晶体管T2的栅极T2g和第一复位晶体管T1的栅极T1g均为双栅结构，补偿晶体管T2的栅极T2g包括第一栅极T2g1和第二栅极T2g2，第一复位晶体管T1的栅极T1g包括第一栅极T1g1和第二栅极T1g2；补偿晶体管T2的第一栅极T2g1在衬底基板200上的正投影与补偿晶体管T2的第二栅极T2g2在衬底基板200上的正投影重合，第一复位晶体管T1的第一栅极T1g1在衬底基板200上的正投影与第一复位晶体管T1的第二栅极T1g2在衬底基板200上的正投影重合。
例如，参考图3E和图7A-7B，第一复位晶体管T1的第一栅极T1g1和补偿晶体管T2的第一栅极T2g1位于第二导电层Gate2，第一复位晶体管T1的第二栅极T1g2和补偿晶体管T2的第二栅极T2g2位于第三导电层Gate3。由于在垂直于衬底基板200的主表面的方向上，补偿晶体管T2的有源层A2和第一复位晶体管T1的有源层A1所在的第二半导体层Active2位于第二导电层Gate2与第三导电层Gate3之间，从而，补偿晶体管T2的第一栅极T2g1和第一复位晶体管T1的第一栅极T1g1与存储电容Cst的第二极板Cst2同层设置，补偿晶体管T2的第二栅极T2g2和第一复位晶体管T1的第二栅极T1g2位于补偿晶体管T2的有源层A2和第一复位晶体管T1的有源层A1的远离衬底基板200的一侧，且位于第二复位信号线Vini_OLED的靠近衬底基板200的一侧。
如图3D，第三导电层Gate3还包括双栅复位扫描信号线Scan(N)(n-1)’和双栅补偿扫描信号线Scan(N)(n)’。如图3E所示，双栅复位扫描信号线Scan(N)(n-1)’的与第一半导体层Active1交叠的部分构成第一复位晶体管T1的第二栅极T1g2；双栅补偿扫描信号线Scan(N)(n)’的与第一半导体层Active1交叠的部分构成补偿晶体管T2的第二栅极T2g2。
双栅复位扫描信号线Scan(N)(n-1)’在衬底基板200的主表面上的正投影与第一复位扫描信号线Scan(N)(n-1)在衬底基板200的主表面上的正投影基本重合；双栅补偿扫描信号线Scan(N)(n)’在衬底基板200的主表面上的正投影 与第二扫描信号线Scan(N)(n)，即补偿扫描信号线，在衬底基板200的主表面上的正投影基本重合。如此，能够减小用于实现双栅结构而设置的双栅复位扫描信号线Scan(N)(n-1)’和双栅补偿扫描信号线Scan(N)(n)’额外占用像素面积，从而提高显示基板的开口率。
如图3F所示，例如，第一连接结构C1位于第四导电层SD1，从而第一连接结构C1与第二复位信号线Vini_OLED同层设置，且位于存储电容Cst的第二极板Cst2的远离衬底基板200的一侧。
在第一连接结构C1与数据线Data异层设置的情况下，例如，在图3A-3I和图4A所示的实施例中，数据线Data位于第一连接结构C1的远离衬底基板200的一侧。或者，在其他实施例中，数据线Data可以位于第一连接结构C1的靠近衬底基板200的一侧。
参考图4A，显示基板10的层间绝缘层ILD包括位于第一半导体层Active1与第一导电层Gate1之间的第一子绝缘层GI1、位于第一导电层Gate1与第二导电层Gate2之间的第二子绝缘层ILD0；参考图7A，层间绝缘层ILD还包括位于第二导电层Gate2与第二半导体层Active2之间的第三子绝缘层ILD1、位于第二半导体层Active2与第三导电层Gate3之间的第四子绝缘层GI2以及位于第三导电层Gate3与第四导电层SD1之间的第五子绝缘层ILD2。
显示基板10还包括位于第四导电层SD1与第五导电层SD2之间的第六子绝缘层即第一平坦层PLN1、以及位于第五导电层SD2与第一显示电极21之间的第二平坦层PLN2。第一平坦层PLN1为设置于其上方的第五导电层SD2提供平坦表面，为第五绝缘层SD2的构图设计提供便利，且降低第五绝缘层SD2的制作难度，提高良率。第二平坦层PLN2为设置于其上方的第一显示电极21提供平坦表面，为第一显示电极21的构图设计提供便利，且降低第一显示电极21的制作难度，提高良率。
例如，如图4A所示，显示基板10还包括像素界定层PDL，像素界定层PDL的开口暴露出每个子像素100的第一显示电极的位于发光区域的一部分，像素界定层PDL的主体覆盖第一显示电极的边缘。
例如，如图4A所示，显示基板10还包括阻隔层02，阻隔层02位于衬底基板200的主表面上且位于第一半导体层Active层的靠近衬底基板200的一侧。例如阻隔层02与衬底基板200接触。阻隔层02可以保护衬底基板， 防止在形成后续的膜层的工艺中对衬底基板造成的破坏和腐蚀。例如，显示基板10还包括缓冲层01，缓冲层01位于阻隔层02的远离衬底基板200的一侧，以进一步保护衬底基板。
结合图3B、图3K和图4A，存储电容Cst的第二极板Cst2具有暴露存储电容Cst的第一极板Cst1的第一过孔V1，第一连接结构C1穿过第一过孔V1而与存储电容Cst的第一极板Cst1连接。第一过孔V1沿垂直于衬底基板200的主表面的方向贯穿第二子绝缘层ILD0。显示基板还包括与第一过孔V1连通且沿垂直于衬底基板200的主表面的方向贯穿第二子绝缘层ILD0、第三子绝缘层ILD1、第四子绝缘层GI2以及第五子绝缘层ILD2的过孔V9，第一连接结构C1通过过孔V9和第一过孔V1与存储电容Cst的第一极板Cst1电连接。
如图3F所示，第一连接结构C1包括沿第一方向D1延伸的第一部分C11和沿第二方向D2延伸的第二部分C12，第一连接结构C1的第二部分C11与第一连接结构的第一部分C11连接，例如第一连接结构C1的第二部分C11与第一连接结构的第一部分C11构成连续的一体成型结构。
结合图3F和图3I，补偿晶体管T2的有源层A2位于第一连接结构C1的远离数据线Data的一侧，第一连接结构C1的第二部分C12与补偿晶体管T2的有源层A2连接。例如，第一连接结构C1的第一部分C11在第一方向D1上远离第二部分C12的一端通过过孔V9和第一过孔V1与存储电容Cst的第一极板Cst1电连接，第一连接结构C1的第二部分C12通过第二过孔V10与补偿晶体管T2的有源层A2连接，第二过孔V10沿垂直于衬底基板200的主表面的方向贯穿第四子绝缘层GI2和第五子绝缘层ILD2(参考图4A)。
参考图3K和图4A，例如，在每个执行显示功能的子像素100中，第一电源线VDD与第一电压端vdd连接且配置为给像素电路提供第一电源电压VDD。例如第一电源线VDD沿第一方向D1延伸。像素电路还包括第二连接结构C2，第二连接结构C2在垂直于衬底基板200的主表面的方向上位于第一电源线VDD与存储电容Cst的第二极板Cst2之间，且连接第一电源线VDD和存储电容Cst的第二极板Cst2。例如，第二连接结构C2包括水平部分C21和竖直部分C22，水平部分C21沿第二方向D2延伸，竖直部分C22与水平部分C21连接且沿第一方向D1延伸。第一电源线VDD在衬底基板200上的 正投影与第二连接结构C2的水平部分C21在衬底基板200上的正投影交叠，且第一电源线VDD在衬底基板200上的正投影与其他和第二连接结构C2同层设置的结构在衬底基板200上的正投影不存在交叠。如此，一方面，便于实现利用第二连接结构C2的水平部分C21与第一电源线VDD交叠的部分将第二连接结构C2的水平部分C21与第一电源线VDD电连接，从而通过第二连接结构C2连接第一电源线VDD和存储电容Cst的第二极板Cst2；另一方面，由于第二连接结构C2所在的导电层与第一电源线VDD所在的导电层在垂直于衬底基板200的主表面方向上较为靠近例如二者为相邻的导电层，因此，如果第二连接结构C2所在的导电层中过多的结构与第一电源线VDD在垂直于衬底基板200的主表面方向上存在交叠，即第二连接结构C2所在的导电层中过多的结构在垂直于衬底基板200的主表面方向上的正投影与第一电源线VDD在垂直于衬底基板200的主表面方向上的正投影存在重叠，会造成对传输于第一电源线VDD上的第一电源电压VDD的干扰，使得第一电源电压VDD不稳，影响显示基板的显示效果，因此，第一电源线VDD在衬底基板200上的正投影与其他和第二连接结构C2同层设置的结构在衬底基板200上的正投影不存在交叠可以避免由此导致的第一电源电压VDD不稳，提高显示基板的显示效果。
例如，如图3K所示，竖直部分C22与第一连接结构C1在第一方向上基本对齐，水平部分C21在衬底基板200上的正投影自竖直部分C22在衬底基板200上的正投影沿第一方向D1延伸至第一电源线VDD在衬底基板200上的正投影，以使第二连接结构C2的延伸趋势相应于第一电源电压VDD与第一连接结构C1的延伸趋势设计，合理利用有限的空间，实现规整且紧凑的走线设计，利于提高像素结构的制作良率以及实现高PPI。
如图4A所示，例如，第一绝缘层PLN1位于第一电源线VDD与第二连接结构C2之间，第二绝缘层(包括第三子绝缘层ILD1、第四子绝缘层GI2以及第五子绝缘层ILD2)位于第二连接结构C2与存储电容Cst的第二极板Cst2之间；第二连接结构C2的水平部分C21通过贯穿第一绝缘层PLN1的第三过孔V3与第一电源线VDD连接，第二连接结构C2的竖直部分C22通过贯穿第二绝缘层的第四过孔V4(即，第四过孔V4贯穿第三子绝缘层ILD1、第四子绝缘层GI2以及第五子绝缘层ILD2)与存储电容Cst的第二极板Cst2 连接。如此，分别利用沿第一方向D1延伸的第二连接结构C2的竖直部分C22和沿第二方向D2延伸的第二连接结构C2的水平部分C21与第一电源线VDD连接，从而，通过多个连接结构和多个过孔实现第第一电源线VDD与存储电容Cst的第二极板Cst2电连接，降低由于单一过孔需要穿过较厚的绝缘层而造成的断线风险；并且，通过巧妙第二连接结构C2的位置和形状以及第二连接结构C2与第一电源线VDD的关系来实现将第一电源线VDD与存储电容Cst的第二极板Cst2电连接，且实现紧凑的像素结构。
例如，在图4A所示的实施例中，第一电源线VDD与数据线Data同层设置，例如第一电源线VDD与数据线Data均位于第五导电层SD2；第二连接结构C2与第一连接结构C1同层设置，第二连接结构C2与第一连接结构C1均位于第四导电层SD。从而，合理排布第二连接结构C2与第一连接结构C1等辅助连接结构与第一电源线VDD和数据线Data的位置关系，即便于显示基板各个层的制作，又能够实现上述像素电路。
例如，像素电路的第一发光控制晶体管T5与驱动晶体管T3的第一极以及第一电压端连接，且配置为响应于施加在第一发光控制晶体管T5的栅极T5g的第一发光控制信号将第一电压端vdd的第一电源电压VDD施加至驱动晶体管T3的第一极T3s；如上，第一半导体层Active1包括驱动晶体管T3的有源层A3、数据写入晶体管T4的有源层A4和第一发光控制晶体管T5的有源层A5。图7C为依次沿图3K中的第五晶体管、第三晶体管、第六晶体管的有源层走向的截面示意图，即沿图3K中的A1-A2线的截面示意图。参考图3K和图7C，第二连接结构C2的水平部分C21通过第五过孔V5与第一半导体层Active1连接。
例如，第二连接结构C2的水平部分C21在第二方向D2上具有彼此相对的第一端和第二端，水平部分C21的第一端位于第一电源线VDD的靠近竖直部分C22的一侧且与竖直部分C22连接，水平部分C21的第二端位于第一电源线VDD的远离竖直部分C22的一侧且通过第五过孔V5与第一半导体层Active1连接。从而，通过巧妙第二连接结构C2的位置和形状以及第二连接结构C2与第一电源线VDD的关系来实现将第一电源线VDD与存储电容Cst的第二极板Cst2电连接，且实现紧凑的像素结构。
参考图3K、图7A-7B，一个子像素100还包括第三连接结构C3。数据 线Data通过过孔V2以及与第一半导体层Active1连接，例如过孔V2包括贯穿第一子绝缘层GI1、第二子绝缘层ILD0、第三子绝缘层ILD1、第四子绝缘层GI2以及第五子绝缘层ILD2的第一子过孔V21和贯穿第一平坦层PLN1的第二子过孔V22，数据线Data通过第二子过孔V22与第三连接结构C3连接，第三连接结构C3通过第一子过孔V21与第一半导体层Active1连接，从而实现数据线Data与第一半导体层Active1连接。
图7C为依次沿图3K中的第五晶体管、第三晶体管、第六晶体管的有源层走向的截面示意图，即沿图3K中的A1-A2线的截面示意图。图7D为依次沿图3K中的第三晶体管、第六晶体管的有源层走向的截面示意图，即沿图3K中的B1-B2线的截面示意图。参考图3K和图7C-7D，一个子像素100还包括第四连接结构C4和第五连接结构C5。例如，第四连接结构C4位于第五导电层SD2，第五连接结构C5位于第四导电层SD1。第一显示电极21位于第二平坦层PLN2的远离衬底基板200的表面上且通过第四连接结构C4和过孔与第一半导体层Active1连接。例如，第一显示电极21通过位于第二平坦层PLN2中的过孔V8与第四连接结构C4连接；第四连接结构C4通过位于第一平坦层PLN1中的过孔V7与第五连接结构C5连接；第五连接结构C5通过贯穿第一子绝缘层GI1、第二子绝缘层ILD0、第三子绝缘层ILD1、第四子绝缘层GI2和第五子绝缘层ILD2的过孔V6与第一半导体层Active1连接。如此，通过多个连接结构和多个过孔实现第一显示电极21与第一半导体层Active1电连接，即与第二发光晶体管T6的第二极T6d电连接，降低由于单一过孔需要穿过较厚的绝缘层而造成的断线风险。
在本发明实施例提供的显示基板10中，例如，衬底基板200可以为刚性基板，例如玻璃基板、硅基板等，也可以由具有优良的耐热性和耐久性的柔性材料形成，例如聚酰亚胺(PI)、聚碳酸酯(PC)、聚乙烯对苯二甲酸乙二醇酯(PET)、聚乙烯、聚丙烯酸酯、多芳基化合物、聚醚酰亚胺、聚醚砜、聚乙二醇对苯二甲酸酯(PET)、聚乙烯(PE)、聚丙烯(PP)、聚砜(PSF)、聚甲基丙烯酸甲酯(PMMA)、三醋酸纤维素(TAC)、环烯烃聚合物(COP)和环烯烃共聚物(COC)等。
例如，该第一到第五导电层的材料可以包括金(Au)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钨(W)以及以上金属组合而成的合金材 料；或者透明导电金属氧化物材料，例如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化锌铝(AZO)等。
例如，第一绝缘层、第二绝缘层为无机绝缘层，其材料例如包括氧化硅、氮化硅、氮氧化硅等硅的氧化物、硅的氮化物或硅的氮氧化物中的至少之一，或者包括氧化铝、氮化钛等包括金属氮氧化物绝缘材料。例如，像素界定层PDL、第一平坦层PLN1和第二平坦层PLN2可以为有机绝缘材料，例如为聚酰亚胺(PI)、丙烯酸酯、环氧树脂、聚甲基丙烯酸甲酯(PMMA)等有机绝缘材料。本发明实施例对此不作限制。
在至少一实施例中，显示基板10的上述各个层的材料和厚度的示例如下表1所示，当然，上述各个膜层的材料和在垂直于衬底基板的主表面方向上的厚度也不限于表1所示的情况。
表1
例如，该发光器件为顶发射结构，第一显示电极21具有反射性而第二显示电极具有透射性或半透射性。例如，第一显示电极21为高功函数的材料以充当阳极，例如为ITO/Ag/ITO叠层结构；第二显示电极为低功函数的材料以充当阴极，例如为半透射的金属或金属合金材料，例如为Ag/Mg合金材料。
当然，以上各个膜层的材料和厚度均不局限于表1中的示例，本领域技术人员可以根据具体产品进行设计。
在另一些实施例中，例如，图8是本发明一实施例提供的一种显示基板的另一种平面示意图，如图8所示，第一子像素P1的第一显示电极21覆盖第一子像素P1与第二子像素P2的交界，且第一子像素P1的第一连接结构C1在衬底基板200上的正投影的一部分与第二子像素P2的第一连接结构C1在衬底基板200上的正投影的一部分均位于第一子像素P1的第一显示电极21在衬底基板200上的正投影内。这种情况下，第一显示电极位于相邻的两个子像素的交界区域，从而第一显示电极覆盖相邻的两个子像素的每个子像素的第一连接结构的一部分，以满足特定需求的电极排列方式，获得较好的显示效果。
在另一些实施例中，例如，可以是整个第一连接结构C1在衬底基板200上的正投影位于发光器件20的第一显示电极21在衬底基板200上的正投影内；多个子像素包括在第二方向D2上彼此相邻的第一子像素P1和第二子像素P2；第一子像素P1的第一显示电极21覆盖第一子像素P1与第二子像素P2的交界，且第一子像素P1的第一连接结构C1在衬底基板200上的正投影与第二子像素P2的第一连接结构C1在衬底基板200上的正投影均位于第一子像素P1的第一显示电极21在衬底基板200上的正投影内。图9是本发明一实施例提供的一种显示基板的包括第一连接结构和第一显示电极的截面示意图。例如，如图9所示，第一连接结构C1在衬底基板200的主表面上的正投影的一部分位于发光器件20的第一显示电极21在衬底基板200的主表面上的正投影内，第一连接结构C1在衬底基板200的主表面上的正投影的另一部分部在发光器件20的第一显示电极21在衬底基板200的主表面上的正投影内，也即，第一连接结构C1的一部分被第一显示电极21覆盖，第一连接结构C1的另一部分不被第一显示电极21覆盖。
图10是本发明一实施例提供的一种显示基板的包括第一连接结构和第一显示电极的截面示意图。例如，在图3K和图10所示的实施例中，在一个子像素100中，整个第一连接结构C1在衬底基板200上的正投影均位于第一显示电极21在衬底基板200上的正投影内。
例如，如图10所示，一个子像素100的第一显示电极21在衬底基板200 的主表面上的正投影还与该子像素100的数据线Data在衬底基板200的主表面上的正投影的一部分重叠；在该子像素100中，第一显示电极21的远离数据线Data且靠近第一连接结构C1的边缘在衬底基板200上的正投影与第一连接结构C1的远离数据线Data的边缘基本对齐。这里的“基本对齐”不限于是绝对的对齐，例如上述基本对齐的两个边缘的对齐误差在第一连接结构C1在第二方向D2上的宽度的3％以内即可认为是该两个边缘基本对齐。
例如，图11是本发明一实施例提供的一种显示基板的再一种平面示意图。如图11所示，第一子像素P1的发光器件20的发光材料发射绿光。即，在垂直于衬底基板200的方向上覆盖第一子像素P1的第一连接结构C1的一部分和第二子像素P2的第一连接结构C1的第一显示电极21所在的第一子像素P1的发光层发射绿光。因为相对于其他颜色的发光材料，例如有机发光二极管的发光材料，绿色的发光材料对电压的变化最不敏感，而由于第一连接结构C1附近的数据线传输的数据电压的跳变造成第一连接结构C1上的信号发生一定程度的跳变，且位于相邻的子像素边界区域且部分覆盖相邻的两个子像素第一连接结构C1的第一显示电极距离第一连接结构C1较近，因此，在多个子像素100的第一显示电极的排布方式中，采用覆盖相邻的子像素100(例如第一子像素P1和第二子像素P2)的第一连接结构C1的第一显示电极21所在的子像素的发光层发射绿光的方案，能够最大程度降低第一连接结构C1的电压跳变对该第一显示电极所在的发光器件的影响。
如图11所示，例如，第一子像素P1的第一显示电极21的远离第二子像素P2的边缘在衬底基板200上的正投影与第一子像素P1的第一连接结构C1的靠近第一子像素P1的数据线Data的边缘在衬底基板200上的正投影基本对齐，第一子像素P1的第一显示电极21的靠近第二子像素P2的边缘在衬底基板200上的正投影与第二子像素P2的第一连接结构C1的靠近第二子像素P2的数据线Data的边缘在衬底基板200上的正投影基本对齐。这里的“基本对齐”不限于是绝对的对齐，例如上述基本对齐的两个边缘的对齐误差在第一连接结构C1在第二方向D2上的宽度的3％以内即可认为是该两个边缘基本对齐。
图12是本发明一实施例提供的一种显示基板的又一种平面示意图。如图12所示，例如，发光器件20的第一显示电极21具有在第二方向D2上彼此 相对的第一端和第二端；第一子像素P1的第一显示电极21覆盖第一子像素P1与第二子像素P2的交界，第一子像素P1的第一显示电极21的第一端在衬底基板200上的正投影具有在第二方向D2上朝向第一子像素P1的第二过孔V2在衬底基板200上的正投影凸出且渐缩的第一凸出部21A，第一子像素P1的第一显示电极21的第二端在衬底基板200的主表面上的正投影具有在第二方向D2上朝向第二子像素P2的第二过孔V2在衬底基板200的主表面上的正投影凸出且渐缩的第二凸出部21B，并且，第一凸出部21A与第一子像素P1的第二过孔V2在衬底基板200的主表面上的正投影在第二方向D2上正对，第二凸出部21B与第二子像素P2的第二过孔V2在衬底基板200的主表面上的正投影在第二方向D2上正对；第一子像素P1的发光器件20的发光材料发射蓝光。相比于其他颜色的发光材料例如有机发光二极管的发光材料，蓝色发光材料对电压变化比较敏感，采用蓝色发光材料的发光器件20所在的子像素的第一显示电极21的分别靠近在第二方向D2上分别位于其两侧的数据线Data1的两端呈渐缩的凸出状，可以降低位于第一显示电极21两侧的数据线Data1上的数据电压的跳变对第一显示电极21的电压的影响。例如第一凸出部21A与第二凸出部21B对称设计以使得第一显示电极21在第二方向D2上的两侧的显示效果比较均匀。
需要说明的是，在第一子像素P1和第二子像素P2中，第二过孔均用于连接数据线和第一半导体层，第二过孔可以包括两个彼此不连通的子过孔，详见如之前的描述的第一子过孔和第二子过孔，但是，在不同的子像素中，第二过孔所包括的两个子过孔的位置不一定相同。例如，如图12所示，第一子像素P1的第二过孔V2的第一子过孔V21和第二子像素P2的第二过孔V2的第一子过孔V21在各自所在的子像素中相应的位置基本相同；第一子像素P1的第二过孔V2的第二子过孔V22对应于第一子像素P1的数据线Data1的位置，第二子像素P2的第二过孔V2的第二子过孔V22对应于第二子像素P2的数据线Data1的位置，第一子像素P1的数据线Data1与第二子像素P2的数据线Data1相对于沿第一方向D1延伸的对称轴对称，第一子像素P1的第一子过孔V21与第二子过孔V22之间的距离小于第二子像素P2的第一子过孔V21与第二子过孔V22之间的距离。
图13是本发明一实施例提供的一种显示基板的再一种截面示意图。例如， 如图13所示，存储电容Cst的第二极板Cst2包括位于第一过孔V1在第二方向D2上的第一侧的第一部分Cst21和位于第一过孔V1在第二方向D2上的第二侧的第二部分Cst22，第一过孔V1的第一侧与第一过孔V1的第二侧相对，第二极板Cst2的第二部分Cst22位于第二极板Cst2的第一部分Cst21的靠近数据线Data的一侧。第一连接结构C1在第二方向D2上靠近存储电容Cst的第二极板Cst2的第二部分Cst22的边缘E1(也即上述第一连接结构C1的第二边缘1b)在衬底基板200上的正投影、第一显示电极21的靠近第一连接结构C1的边缘E2在衬底基板200上的正投影、以及第二极板Cst2的第二部分的靠近第一连接结构C1的边缘E3在衬底基板200上的正投影重叠(基本对齐)。如此，有利于减小第一显示电极21和第一连接结构C1形成的寄生电容，也有利于第四导电层SD1的平坦化。
例如，在至少一实施例中，数据线Data的重叠部分D0和第一连接结构C1两者中的至少一者包括凹陷部，数据线Data的重叠部分D0和第一连接结构C1两者中的任意一者的凹陷部在第二方向D2上朝向远离数据线Data的重叠部分D0和第一连接结构C1两者中的另一者的方向凹陷。
示例性地，图14A为本发明一实施例提供的一种显示基板中的第一连接结构与数据线的示意图。如图14A所示，例如，数据线Data的重叠部分包括第一凹陷部R1，第一凹陷部R1在第二方向D2上朝向远离第一连接结构C1的方向凹陷，第一连接结构C1的与数据线Data相对的部分呈直的条形。如此，第一凹陷部R1增大数据线Data的重叠部分D0与第一连接结构C1之间的距离，减小了数据线的重叠部分D0与第一连接结构C1所形成的寄生电容的电容值。
例如，在图14A中，数据线Data与第一连接结构C1异层设置，从而，可利用不同于第一连接结构C1的膜层来布局数据线Data的图案，避免了第一连接结构C1等结构造成对设计第一凹陷部R1的空间限制，有充足的空间可以满足设计第一凹陷部R1。例如，第一连接结构C1位于上述第四导电层SD1，数据线Data位于上述第五导电层SD2。或者，在其他实施例中，也可以是一连接结构C1位于上述第五导电层SD2，数据线Data位于上述第四导电层SD1。当然，第一连接结构和数据线也可以分别位于其他不同的两个导电层，本发明对第一连接结构和数据线所在的层不作具体限制。
示例性地，图14B为本发明一实施例提供的另一种显示基板中的第一连接结构与数据线的示意图。如图14B所示，例如，第一连接结构C1包括第二凹陷部R2，第二凹陷部R2在第二方向D2上朝向远离数据线Data的重叠部分D0的方向凹陷，数据线Data的重叠部分D0呈直的条形。从而，第二凹陷部R2增大数据线Data的重叠部分D0与第一连接结构C1之间的距离，减小了数据线Data的重叠部分D0与第一连接结构C1所形成的寄生电容的电容值。
同样，例如，数据线Data与第一连接结构C1异层设置，从而，可利用不同于数据线Data的膜层来布局第一连接结构C1的图案，避免了数据线Data等结构造成对设计第二凹陷部R2的空间限制，有充足的空间可以满足设计第二凹陷部R2。例如，第一连接结构C1位于上述第四导电层SD1，数据线Data位于上述第五导电层SD2。或者，在其他实施例中，也可以是一连接结构C1位于上述第五导电层SD2，数据线Data位于上述第四导电层SD1。当然，第一连接结构和数据线也可以分别位于其他不同的两个导电层，本发明对第一连接结构和数据线所在的层不作具体限制。
示例性地，图14C为本发明一实施例提供的又一种显示基板中的第一连接结构与数据线的示意图。如图14C所示，例如，数据线Data的重叠部分D0包括第一凹陷部R1，第一凹陷部R1在第二方向D2上朝向远离第一连接结构C1的方向凹陷，并且，第一连接结构C1包括第二凹陷部R2，第二凹陷部R2在第二方向D2上朝向远离数据线Data的重叠部分D0的方向凹陷。如此，第一连接结构C1的与数据线Data相对的部分呈直的条形。如此，第一凹陷部R1和第二凹陷部R2共同进一步增大了数据线Data的重叠部分D0与第一连接结构C1之间的距离，更进一步地减小了数据线的重叠部分D0与第一连接结构C1所形成的寄生电容的电容值。
例如，在图14C中，数据线Data与第一连接结构C1异层设置，从而，避免了对设计第一凹陷部R1和第二凹陷部R2的空间限制，分别在不同的层中有充足的空间可以满足设计第一凹陷部R1和第二凹陷部R2。例如，第一连接结构C1位于上述第四导电层SD1，数据线Data位于上述第五导电层SD2。或者，在其他实施例中，也可以是一连接结构C1位于上述第五导电层SD2，数据线Data位于上述第四导电层SD1。当然，第一连接结构和数据线 也可以分别位于其他不同的两个导电层，本发明对第一连接结构和数据线所在的层不作具体限制。
本发明至少一实施例还提供一种显示装置，该显示装置包括本发明实施例提供的任意一种显示基板。图15是本发明至少一实施例提供的显示装置示意图。如图15所示，本发明至少一实施例提供的显示装置10-1包括本发明实施例提供的任意一种显示面板10。该显示装置10-1例如可以为有机发光二极管显示装置等具有显示功能的装置或其他类型的装置。本发明的实施例对此不作限制。
本发明实施例提供的显示装置的结构、功能及技术效果等可以参考上述本发明实施例提供的显示基板10中的相应描述，在此不再赘述。
例如，本发明至少一实施例提供的显示装置10-1可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本发明的实施例对此不作限制。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。

Claims (41)

  1. 一种显示基板，包括：
    衬底基板，设置有呈阵列排布的多个像素，其中，所述多个像素中的至少部分像素中的每个像素包括多个子像素，所述多个子像素中的至少部分包括像素电路，所述像素电路包括：
    发光器件、存储电容、驱动晶体管和数据写入晶体管，其中，所述驱动晶体管和所述数据写入晶体管的每个包括有源层、栅极、第一极和第二极，所述驱动晶体管配置为控制所述发光器件发光；
    数据线，与所述数据写入晶体管的第一极连接且配置为给所述数据写入晶体管提供数据信号，其中，所述数据写入晶体管配置为响应于施加在所述数据写入晶体管的栅极的第一扫描信号而将所述数据信号写入所述驱动晶体管的栅极；以及
    第一连接结构，与所述驱动晶体管的栅极以及所述存储电容的第一极板连接，其中，所述数据线和所述第一连接结构均沿第一方向延伸，且所述数据线包括重叠部分，所述第一连接结构与所述数据线的重叠部分在第二方向上至少部分相对，所述第二方向平行于所述衬底基板且垂直于所述第一方向；
    所述第一连接结构与所述数据线的重叠部分彼此绝缘，所述第一连接结构与所述数据线的重叠部分分别构成寄生电容的第一极板和第二极板；所述寄生电容的电容值与所述存储电容的电容值的比值大于0.001且小于0.01。
  2. 根据权利要求1所述的显示基板，其中，一个所述子像素的在所述第二方向上的尺寸大于50μm，所述寄生电容的电容值与所述存储电容的电容值的比值小于0.005。
  3. 根据权利要求2所述的显示基板，其中，一个所述子像素的在所述第二方向上的尺寸小于等于68μm，所述寄生电容的电容值与所述存储电容的电容值的比值大于等于0.003。
  4. 根据权利要求1所述的显示基板，其中，一个所述子像素的在所述第二方向上的尺寸小于50μm，所述寄生电容的电容值与所述存储电容的电容值的比值大于0.005且小于0.006。
  5. 根据权利要求1-4任一所述的显示基板，其中，所述第一连接结构包 括沿所述第一方向延伸的第一部分，所述第一连接结构的第一部分的靠近所述数据线的重叠部分的边缘为第一边缘，所述第一连接结构的第一部分还具有与远离所述数据线的重叠部分的第二边缘，所述数据线的重叠部分的靠近所述第一连接结构的边缘为第三边缘；
    所述多个子像素包括在所述第二方向上彼此相邻的第一子像素和第二子像素；所述第一子像素的第一连接结构的第二边缘在所述衬底基板上的正投影到所述第二子像素的数据线的重叠部分的第三边缘在所述衬底基板上的正投影的距离为第一距离，所述第一子像素的第一连接结构的第一边缘到所述第一子像素的数据线的重叠部分的第三边缘的距离为第二距离，所述第一距离与所述第二距离的比值大于14。
  6. 根据权利要求5所述的显示基板，其中，一个所述子像素的在所述第二方向上的尺寸小于50μm，所述第一距离与所述第二距离的比值大于14且小于15.5。
  7. 根据权利要求5所述的显示基板，其中，一个所述子像素的在所述第二方向上的尺寸大于50μm，所述第一距离与所述第二距离的比值大于15.5。
  8. 根据权利要求5-7任一所述的显示基板，其中，所述多个子像素包括在所述第二方向上彼此相邻的第一子像素和第二子像素；所述第一子像素的第一连接结构在所述第二方向上位于所述第一子像素的数据线和所述第二子像素的数据线之间；
    所述第一子像素的第一连接结构在所述衬底基板上的正投影与所述第一子像素的数据线在所述衬底基板上的正投影之间的距离小于一个所述子像素的在所述第二方向上的尺寸，并且，
    所述第一子像素的第一连接结构在所述衬底基板上的正投影与所述第二子像素的数据线在所述衬底基板上的正投影之间的距离小于一个所述子像素的在所述第二方向上的尺寸。
  9. 根据权利要求5-8任一所述的显示基板，其中，所述第一子像素的第一连接结构在所述第二方向上位于所述第一子像素的数据线和所述第二子像素的数据线之间；
    所述第一子像素的第一连接结构在所述衬底基板上的正投影与所述第一子像素的数据线在所述衬底基板上的正投影之间的距离小于一个所述子像素 的在所述第二方向上的尺寸，并且，
    所述第一子像素的第一连接结构在所述衬底基板上的正投影与所述第二子像素的数据线在所述衬底基板上的正投影之间的距离大于一个所述子像素的在所述第二方向上的尺寸。
  10. 根据权利要求5-9任一所述的显示基板，其中，所述第一子像素的驱动晶体管的栅极的靠近所述第二子像素的数据线的重叠部分的边缘为第四边缘；
    所述第一子像素的第二边缘到所述第二子像素的第三边缘的距离等于所述第一子像素的第二边缘到所述第四边缘的距离与所述第一子像素的所述第四边缘到所述第二子像素的第三边缘的距离之和。
  11. 根据权利要求10所述的显示基板，其中，所述第一连接结构与所述数据线异层设置，所述第一连接结构在所述衬底基板上的正投影与所述数据线的重叠部分在所述衬底基板上的正投影至少部分重叠；或者，
    所述第一连接结构与所述数据线异层设置，所述第一连接结构在所述衬底基板上的正投影与所述数据线的重叠部分在所述衬底基板上的正投影不重叠。
  12. 根据权利要求10所述的显示基板，其中，所述第一连接结构与所述数据线同层设置，所述第一连接结构与所述数据线的重叠部分在第二方向上彼此相对。
  13. 根据权利要求1-12任一所述的显示基板，其中，所述数据线的重叠部分和所述第一连接结构两者中的至少一者包括凹陷部，所述数据线的重叠部分和所述第一连接结构两者中的任意一者的所述凹陷部在所述第二方向上朝向远离所述数据线的重叠部分和所述第一连接结构两者中的另一者的方向凹陷。
  14. 根据权利要求13所述的显示基板，其中，
    所述数据线的重叠部分包括第一凹陷部，所述第一凹陷部在所述第二方向上朝向远离所述第一连接结构的方向凹陷，所述第一连接结构的与所述数据线相对的部分呈直的条形。
  15. 根据权利要求13所述的显示基板，其中，所述第一连接结构包括第二凹陷部，所述第二凹陷部在所述第二方向上朝向远离所述数据线的重叠部 分的方向凹陷，所述数据线的重叠部分呈直的条形。
  16. 根据权利要求13所述的显示基板，其中，
    所述数据线的重叠部分包括第一凹陷部，所述第一凹陷部在所述第二方向上朝向远离所述第一连接结构的方向凹陷，并且，所述第一连接结构包括第二凹陷部，所述第二凹陷部在所述第二方向上朝向远离所述数据线的重叠部分的方向凹陷。
  17. 根据权利要求1-16任一所述的显示基板，还包括第一复位扫描信号线、第二复位扫描信号线、第一复位信号线和第二复位信号线，其中，
    所述像素电路还包括：
    第一复位晶体管，包括有源层，其中，所述第一复位扫描信号线配置为给所述第一复位晶体管的栅极提供第一复位扫描信号，所述第一复位晶体管的第一极与所述驱动晶体管的栅极电连接，所述第一复位晶体管的第二极被配置为与所述第一复位信号线电连接以接收第一复位信号，所述第一复位晶体管配置为响应于所述第一复位扫描信号将所述第一复位信号写入所述驱动晶体管的栅极；以及
    第二复位晶体管，其中，所述第二复位扫描信号线配置为给所述第二复位晶体管的栅极提供第二复位扫描信号，所述第二复位晶体管的第一极与所述发光器件的第一显示电极电连接，所述第二复位晶体管的第二极被配置为与所述第二复位信号线电连接以接收第二复位信号，所述第二复位晶体管配置为响应于所述第二复位扫描信号将所述第二复位信号写入所述发光器件的第一显示电极；
    所述第一复位晶体管的有源层沿所述第一方向延伸，所述第一复位扫描信号线沿所述第二方向延伸；
    所述多个子像素包括在所述第二方向上彼此相邻的第一子像素和第二子像素；所述多个子像素还包括第三子像素，所述第三子像素与所述第二子像素在所述第一方向上相邻；
    所述第二复位信号线的位于所述多个子像素中的每个子像素的部分包括横向部分和第一纵向部分，所述横向部分沿所述第二方向延伸且具有在所述第二方向上彼此相对的第一端和第二端，所述第一纵向部分与所述横向部分的第一端连接且沿所述第一方向延伸，并且，所述第二子像素的第二复位信 号线的横向部分在所述衬底基板上的正投影与所述第三子像素的第一复位扫描信号线在所述衬底基板上的正投影至少部分重叠，所述第二子像素的第二复位信号线的第一纵向部分与所述第三子像素的第一复位晶体管的有源层在所述第二方向上间隔排列。
  18. 根据权利要求17所述的显示基板，其中，所述第二复位信号线的对应于一个子像素的子部的平面图形呈倒置的“几”字形；所述“几”字形的子部包括U形凹槽，所述第二复位信号线的横向部分作为所述U形凹槽的底部。
  19. 根据权利要求17或18所述的显示基板，还包括补偿扫描信号线，其中，
    所述像素电路还包括：
    补偿晶体管，包括有源层、栅极、第一极和第二极，其中，所述补偿扫描信号线配置为给所述补偿晶体管的栅极施加第二扫描信号，所述补偿晶体管的配置为响应于所述第二扫描信号对该所述驱动晶体管进行阈值补偿；
    所述补偿晶体管的有源层与所述第一复位晶体管的有源层构成一体结构。
  20. 根据权利要求17-19任一所述的显示基板，其中，所述第二复位信号线的位于一个所述子像素的部分还包括第二纵向部分，所述第二纵向部分与所述横向部分的第二端连接且沿所述第一方向延伸，所述第二复位晶体管的有源层位于所述第一纵向部分与所述第二纵向部分之间，并且，
    在同一个所述子像素中，在所述第二方向上，所述第一纵向部分到所述数据线的距离大于所述第二纵向部分到所述数据线的距离；
    所述第三子像素的第二复位晶体管的有源层到所述第二子像素的第二复位信号线的第一纵向部分的距离小于所述第三子像素的第二复位晶体管的有源层到所述第二子像素的第二复位信号线的第二纵向部分的距离。
  21. 根据权利要求19或20所述的显示基板，其中，所述驱动晶体管的栅极与所述存储电容的第一极板同层设置且构成一体成型结构，所述第二复位扫描信号线与所述驱动晶体管的栅极同层设置；
    所述驱动晶体管的栅极和所述存储电容的第一极板位于所述驱动晶体管的有源层的远离所述衬底基板的一侧；
    所述存储电容的第二极板位于所述驱动晶体管的栅极和所述存储电容的第一极板的远离所述衬底基板的一侧，所述补偿扫描信号线与所述存储电容的第二极板同层设置；
    所述补偿晶体管的有源层位于所述存储电容的第二极板的远离所述衬底基板的一侧；
    所述第二复位信号线位于所述补偿晶体管的有源层的远离所述衬底基板的一侧。
  22. 根据权利要求21所述的显示基板，还包括第一复位扫描信号线和第一复位信号线，其中，所述像素电路还包括：
    第一复位晶体管，包括有源层，其中，所述第一复位扫描信号线配置为给所述第一复位晶体管的栅极提供第一复位扫描信号，所述第二复位晶体管的第一极与所述驱动晶体管的栅极电连接，所述第一复位晶体管的第二极被配置为与所述第一复位信号线电连接以接收第一复位信号，所述第一复位晶体管配置为响应于所述第一复位扫描信号将所述第一复位信号写入所述驱动晶体管的栅极；
    所述第一复位晶体管的有源层与所述驱动晶体管的有源层的材料不同且异层设置；
    所述第一复位信号线与所述存储电容的第二极板同层设置。
  23. 根据权利要求22所述的显示基板，其中，所述补偿晶体管的栅极和所述第一复位晶体管的栅极均为双栅结构，所述补偿晶体管的栅极包括第一栅极和第二栅极，所述第一复位晶体管的栅极包括第一栅极和第二栅极；
    所述补偿晶体管的第一栅极在所述衬底基板上的正投影与所述补偿晶体管的第二栅极在所述衬底基板上的正投影重合，所述第一复位晶体管的第一栅极在所述衬底基板上的正投影与所述第一复位晶体管的第二栅极在所述衬底基板上的正投影重合。
  24. 根据权利要求23所述的显示基板，其中，所述补偿晶体管的第一栅极和所述第一复位晶体管的第一栅极与所述存储电容的第二极板同层设置，所述补偿晶体管的第二栅极和所述第一复位晶体管的第二栅极位于所述补偿晶体管的有源层和所述第一复位晶体管的有源层的远离所述衬底基板的一侧，且位于所述第二复位信号线的靠近所述衬底基板的一侧。
  25. 根据权利要求22-24任一所述的显示基板，其中，
    所述第一复位晶体管的有源层的材料为氧化物半导体；
    所述驱动晶体管和所述数据写入晶体管的有源层的材料为低温多晶硅。
  26. 根据权利要求21-25任一所述的显示基板，其中，所述第一连接结构位于所述存储电容的第二极板的远离所述衬底基板的一侧；
    所述存储电容的第二极板具有暴露所述存储电容的第一极板的第一过孔，所述第一连接结构穿过所述第一过孔而与所述存储电容的第一极板连接；所述存储电容的第二极板包括位于所述第一过孔在所述第二方向上的第一侧的第一部分和位于所述第一过孔在所述第二方向上的第二侧的第二部分，所述第一过孔的第一侧与所述第一过孔的第二侧相对，所述第二极板的第二部分位于所述第二极板的第一部分的靠近所述数据线的一侧；
    所述第一连接结构在所述第二方向上靠近所述存储电容的第二极板的第二部分的边缘在所述衬底基板上的正投影、所述第一显示电极的靠近所述第一连接结构的边缘在所述衬底基板上的正投影、以及所述第二极板的第二部分的靠近所述第一连接结构的边缘在所述衬底基板上的正投影重叠。
  27. 根据权利要求21-26任一所述的显示基板，其中，所述第一连接结构与所述第二复位信号线同层设置；
    在所述第一连接结构与所述数据线异层设置的情况下，所述数据线位于所述第一连接结构的远离所述衬底基板的一侧，或者，所述数据线位于所述第一连接结构的靠近所述衬底基板的一侧。
  28. 根据权利要求19和21-27任一所述的显示基板，其中，所述第一连接结构包括沿所述第一方向延伸的第一部分和沿所述第二方向延伸的第二部分，所述第一连接结构的第二部分与所述第一连接结构的第一部分连接；
    所述补偿晶体管的有源层位于所述第一连接结构的远离所述数据线的一侧，所述第一连接结构的第二部分与所述补偿晶体管的有源层连接。
  29. 根据权利要求1-28任一所述的显示基板，其中，整个所述第一连接结构在所述衬底基板上的正投影位于所述发光器件的第一显示电极在所述衬底基板上的正投影内；
    所述多个子像素包括在所述第二方向上彼此相邻的第一子像素和第二子像素；所述第一子像素的第一显示电极覆盖所述第一子像素与所述第二子像 素的交界，且所述第一子像素的第一连接结构在所述衬底基板上的正投影与所述第二子像素的第一连接结构在所述衬底基板上的正投影均位于所述第一子像素的第一显示电极在所述衬底基板上的正投影内。
  30. 根据权利要求29所述的显示基板，其中，所述第一子像素的第一显示电极的远离所述第二子像素的边缘在所述衬底基板上的正投影与所述第一子像素的第一连接结构的靠近所述第一子像素的数据线的边缘在所述衬底基板上的正投影重叠，所述第一子像素的第一显示电极的靠近所述第二子像素的边缘在所述衬底基板上的正投影与所述第二子像素的第一连接结构的靠近所述第二子像素的数据线的边缘在所述衬底基板上的正投影重叠。
  31. 根据权利要求1-28任一所述的显示基板，其中，所述第一连接结构在所述衬底基板上的正投影的一部分位于所述发光器件的第一显示电极在所述衬底基板上的正投影内；
    所述多个子像素包括在所述第二方向上彼此相邻的第一子像素和第二子像素；所述第一子像素的第一显示电极覆盖所述第一子像素与所述第二子像素的交界，且所述第一子像素的第一连接结构在所述衬底基板上的正投影的一部分与所述第二子像素的第一连接结构在所述衬底基板上的正投影的一部分均位于所述第一子像素的第一显示电极在所述衬底基板上的正投影内。
  32. 根据权利要求31所述的显示基板，其中，所述第一子像素的发光器件的发光材料发射绿光。
  33. 根据权利要求1-32任一所述的显示基板，其中，所述存储电容的第一极板具有远离所述衬底基板的上表面和与所述上表面相交的侧表面；
    所述存储电容的第二极板包括：
    中间部分，在所述衬底基板上的正投影与所述存储电容的第一极板在所述衬底基板上的正投影至少部分重合，且包括与所述存储电容的第一极板的上表面相对的底面；
    边缘部分，至少部分围绕所述中间部分且与所述中间部分连接，且包括靠近所述衬底基板的底面和与所述底面相交的内侧面，其中，所述内侧面与所述存储电容的第一极板的侧表面彼此相对，且所述内侧面在垂直于所述衬底基板的参考面上的正投影与，与所述内侧面相对的所述存储电容的第一极板的侧表面，在所述参考面上的正投影至少部分重叠，其中，
    所述边缘部分的内侧面与，与所述内侧面相对的所述存储电容的第一极板的侧表面，之间的距离小于所述中间部分的底面与所述存储电容的第一极板的上表面之间的距离。
  34. 根据权利要求1-33任一所述的显示基板，其中，所述发光器件的第一显示电极具有在所述第二方向上彼此相对的第一端和第二端；
    所述显示基板包括第一半导体层，所述第一半导体层包括所述驱动晶体管的有源层和所述数据写入晶体管的有源层，所述数据线通过第二过孔与所述第一半导体层连接；
    所述多个子像素包括在所述第二方向上彼此相邻的第一子像素和第二子像素；所述第一子像素的第一显示电极覆盖所述第一子像素与所述第二子像素的交界，所述第一子像素的第一显示电极的第一端在所述衬底基板上的正投影具有在所述第二方向上朝向所述第一子像素的第二过孔在所述衬底基板上的正投影凸出且渐缩的第一凸出部，所述第一子像素的第一显示电极的第二端在所述衬底基板上的正投影具有在所述第二方向上朝向所述第二子像素的第二过孔在所述衬底基板上的正投影凸出且渐缩的第二凸出部，并且，所述第一凸出部与所述第一子像素的第二过孔在所述衬底基板上的正投影在所述第二方向上正对，所述第二凸出部与所述第二子像素的第二过孔在所述衬底基板上的正投影在所述第二方向上正对；
    所述第一子像素的发光器件的发光材料发射蓝光。
  35. 根据权利要求1-34任一所述的显示基板，其中，所述驱动晶体管的栅极与所述存储电容的第一极板同层设置且构成一体成型结构；所述驱动晶体管的栅极和所述存储电容的第一极板位于所述驱动晶体管的有源层的远离所述衬底基板的一侧；所述存储电容的第二极板位于所述驱动晶体管的栅极和所述存储电容的第一极板的远离所述衬底基板的一侧，
    所述显示基板还包括：
    第一电源线，与第一电压端连接且配置为给所述像素电路提供第一电源电压，沿所述第一方向延伸；
    所述像素电路还包括：
    第二连接结构，在垂直于所述衬底基板的方向上位于所述第一电源线与所述存储电容的第二极板之间，且连接所述第一电源线和所述存储电容的第 二极板，其中，所述第二连接结构包括水平部分和竖直部分，所述水平部分沿所述第二方向延伸，所述竖直部分与所述水平部分连接且沿所述第一方向延伸；
    所述第一电源线在所述衬底基板上的正投影与所述第二连接结构的水平部分在所述衬底基板上的正投影交叠，且所述第一电源线在所述衬底基板上的正投影与其他和所述第二连接结构同层设置的结构在所述衬底基板上的正投影不存在交叠。
  36. 根据权利要求35所述的显示基板，其中，所述竖直部分与第一连接结构在所述第以方向上基本对齐，所述水平部分在所述衬底基板上的正投影自所述竖直部分在所述衬底基板上的正投影沿所述第一方向延伸至所述第一电源线在所述衬底基板上的正投影。
  37. 根据权利要求35或36所述的显示基板，还包括：
    第一绝缘层，位于所述第一电源线与所述第二连接结构之间；
    第二绝缘层，位于所述第二连接结构与所述存储电容的第二极板之间，其中，所述第一电源线的水平部分通过贯穿所述第一绝缘层的第三过孔与所述第二连接结构连接，所述第二连接结构的竖直部分通过贯穿所述第二绝缘层的第四过孔与所述存储电容的第二极板连接。
  38. 根据权利要求35-37任一所述的显示基板，其中，所述第一电源线与所述数据线同层设置，所述第二连接结构与所述第一连接结构同层设置。
  39. 根据权利要求35-38任一所述的显示基板，其中，所述像素电路还包括：
    第一发光晶体管，与所述驱动晶体管的第一极以及所述第一电压端连接，且配置为响应于施加在所述第一发光晶体管的栅极的第一发光控制信号将所述第一电压端的第一电源电压施加至所述驱动晶体管的第一极；
    所述显示基板包括第一半导体层，所述第一半导体层包括所述驱动晶体管的有源层、所述数据写入晶体管的有源层和所述第一发光晶体管的有源层，所述第二连接结构的水平部分通过第五过孔与所述第一半导体层连接。
  40. 根据权利要求39所述的显示基板，其中，所述第二连接结构的水平部分在所述第二方向上具有彼此相对的第一端和第二端，所述水平部分的第一端位于所述第一电源线的靠近所述竖直部分的一侧且与所述竖直部分连 接，所述水平部分的第二端位于所述第一电源线的远离所述竖直部分的一侧且通过所述第五过孔与所述第一半导体层连接。
  41. 一种显示装置，包括权利要求1-40任一所述的显示基板。
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