WO2024092510A1 - 显示面板以及显示装置 - Google Patents

显示面板以及显示装置 Download PDF

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Publication number
WO2024092510A1
WO2024092510A1 PCT/CN2022/129001 CN2022129001W WO2024092510A1 WO 2024092510 A1 WO2024092510 A1 WO 2024092510A1 CN 2022129001 W CN2022129001 W CN 2022129001W WO 2024092510 A1 WO2024092510 A1 WO 2024092510A1
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WIPO (PCT)
Prior art keywords
sub
electrostatic
electrostatic discharge
area
signal line
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PCT/CN2022/129001
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English (en)
French (fr)
Inventor
吴刘
袁志东
李永谦
孙力
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/129001 priority Critical patent/WO2024092510A1/zh
Publication of WO2024092510A1 publication Critical patent/WO2024092510A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • At least one embodiment of the present disclosure relates to a display panel and a display device.
  • an electrostatic discharge unit is crucial to the display circuit.
  • the electrostatic discharge unit can be set to release the static electricity of the display circuit to protect the display circuit.
  • Traditional display screens such as rectangular display screens, have enough bottom space to arrange the electrostatic discharge unit.
  • the frame shape of the special-shaped screen is irregular, and the space available for setting the electrostatic discharge unit is very small, which poses a challenge to changing the traditional arrangement of the electrostatic discharge unit.
  • At least one embodiment of the present disclosure provides a display panel, which includes: a display area, a non-display area, a first signal line, and a plurality of electrostatic release units.
  • the display area includes sub-pixels; the non-display area at least partially surrounds the display area and includes an electrostatic release region; the first signal line extends from the display area to the electrostatic release region as a whole along a first direction and is configured to provide a first display signal to the sub-pixel; a plurality of electrostatic release units are arranged in the first direction, each of the electrostatic release units includes at least one sub-electrostatic release unit, each of the at least one sub-electrostatic release unit includes an electrostatic release circuit and a first conductor, the electrostatic release circuit is electrically connected to the first signal line and the first conductor, and is configured to move the charge on the first signal line toward the first conductor; the plurality of electrostatic release units include two adjacent electrostatic release units adjacent in a second direction, the second direction is perpendic
  • At least one embodiment of the present disclosure provides a display panel in which, among the multiple sub-electrostatic release units of the multiple electrostatic release units, the orthographic projections of at least two of the sub-electrostatic release units on the surface parallel to the first direction do not overlap with each other and the orthographic projections on the surface parallel to the second direction at least partially overlap with each other.
  • At least one embodiment of the present disclosure provides a display panel in which a size of the electrostatic discharge circuit in the second direction is smaller than a size of the electrostatic discharge circuit in the first direction.
  • At least one embodiment of the present disclosure provides a display panel, wherein the display panel includes a plurality of first signal lines, and a plurality of sub-electrostatic release units of the plurality of electrostatic release units are respectively electrically connected to a first signal line among the plurality of first signal lines; at least one of the plurality of first signal lines includes a recessed portion located in the electrostatic release area, and the recessed portion constitutes a groove recessed toward one side in the second direction, and the sub-electrostatic release unit adjacent to the groove is at least partially located in the groove.
  • At least one embodiment of the present disclosure provides a display panel, wherein at least one electrostatic release unit among the multiple electrostatic release units includes two adjacent sub-electrostatic release units in the second direction, and two adjacent first signal lines each include a recessed portion located in the electrostatic release area, and the recessed portions of the two adjacent first signal lines constitute a groove recessed toward the same side in the second direction, and the two adjacent sub-electrostatic release units are respectively at least partially located in the groove formed by the recessed portions of the two adjacent first signal lines.
  • At least one embodiment of the present disclosure provides a display panel in which the first signal line connected to the at least one sub-electrostatic release unit includes: a first recessed portion and a second recessed portion.
  • the first recessed portion constitutes a first groove recessed toward the first side in the second direction;
  • the second recessed portion constitutes a second groove recessed toward the second side opposite to the first side in the second direction, and is arranged with the first recessed portion in the second direction;
  • the two adjacent electrostatic release units are respectively a first electrostatic release unit and a second electrostatic release unit, the orthographic projection of the first electrostatic release unit in parallel to the first direction is located within the orthographic projection of the first groove in parallel to the first direction, and the orthographic projection of the second electrostatic release unit in parallel to the first direction is located within the orthographic projection of the second groove in parallel to the first direction.
  • At least one embodiment of the present disclosure provides a display panel, in which a plurality of electrostatic release units constitute a plurality of electrostatic release unit groups arranged at intervals in the second direction, each of the electrostatic release unit groups includes M sub-electrostatic release unit groups, each of the sub-electrostatic release unit groups includes N electrostatic release units, each of the electrostatic release units includes Q sub-electrostatic release units, M and Q are positive integers greater than or equal to 1, and N is a positive integer greater than or equal to 2; at least some of the plurality of electrostatic release unit groups are periodically arranged in the second direction, and one electrostatic release unit group is a repeating unit in the period.
  • At least one embodiment of the present disclosure provides a display panel in which the number of sub-electrostatic release units included in an electrostatic release unit group is M*N*Q; when M is equal to 1, N is equal to 2, and Q is equal to 3, the width of an electrostatic release unit group in the second direction is less than or equal to 129.5 ⁇ m; or, when M is equal to 2, N is equal to 3, and Q is equal to 3, the width of an electrostatic release unit group in the second direction is less than or equal to 294 ⁇ m.
  • At least one embodiment of the present disclosure provides a display panel, wherein the resolution of the display panel is X*Y, where X represents the number of rows of the pixel array in the display area, and Y represents the number of columns of the pixel array in the display area, and X is greater than or equal to 960, and Y is greater than or equal to 1440.
  • At least one embodiment of the present disclosure provides a display panel, wherein the M sub-electrostatic release unit groups include a first sub-electrostatic release unit group and a second sub-electrostatic release unit group, and the first sub-electrostatic release unit group and the second sub-electrostatic release unit group are symmetrical or asymmetrical relative to the symmetry axis extending along the first direction.
  • At least one embodiment of the present disclosure provides a display panel, wherein the first display signal is a data signal, and the first signal line transmits the data signal; the sub-pixel includes a pixel circuit, and the pixel circuit includes: a light-emitting device, a driving transistor and a data writing transistor; the data writing transistor is configured to transmit the data signal to the driving transistor under the control of a first scanning signal; the driving transistor is configured to control the size of the driving current flowing through the light-emitting device according to the data signal, and the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light.
  • At least one embodiment of the present disclosure provides a display panel, wherein the non-display area includes a lead area, the lead area is provided with a driving circuit, and the driving circuit is configured to provide the first display signal to the first signal line; the electrostatic release area is located between the lead area and the display area, and the plurality of sub-electrostatic release units connected to the first signal line that provides the first display signal to all the sub-pixels are all located in the non-display area on the same side of the display area in the first direction.
  • At least one embodiment of the present disclosure provides a display panel, wherein the non-display area also includes a border area, the border area is located between the lead area and the display area, a first power lead is provided in the border area, and the first power lead is configured to provide a first power supply voltage to the sub-pixel; the lead area includes a data selection area located on a side of the border area away from the display area, a data selection unit is provided in the data selection area, and the electrostatic release area is located between the first power lead and the data selection area.
  • At least one embodiment of the present disclosure provides a display panel, in which the first end of the data selection unit close to the electrostatic release area is electrically connected to R first signal lines, and the second end of the data selection unit away from the electrostatic release area is electrically connected to S data leads, S and R are both positive integers and S is less than R; the S data leads are electrically connected to a drive circuit, and the first display signal is provided to the S data leads through the drive circuit.
  • At least one embodiment of the present disclosure provides a display panel in which the width of the region where the driving circuit is located in the second direction is smaller than the width of the electrostatic release region in the second direction.
  • At least one embodiment of the present disclosure provides a display panel, wherein the electrostatic release circuit includes a first sub-circuit, the first sub-circuit having a driving end, a first end, and a second end, wherein the driving end and the first end of the first sub-circuit are both electrically connected to the first signal line, and the second end of the first sub-circuit is electrically connected to the first conductor.
  • the sub-electrostatic release unit also includes a second conductor
  • the electrostatic release circuit is electrically connected to the first signal line and the second conductor, and is configured to move the charge on the first signal line toward the second conductor
  • the electrostatic release circuit also includes a second sub-circuit, the second sub-circuit has a driving end, a first end, and a second end, wherein the first end of the second sub-circuit is electrically connected to the first signal line, and the driving end and the second end of the second sub-circuit are both connected to the second conductor; the first sub-circuit and the second sub-circuit are arranged in the first direction.
  • At least one embodiment of the present disclosure provides a display panel, wherein the first sub-circuit includes a first transistor, and the second sub-circuit includes a second transistor; the gate and the first electrode of the first transistor are both electrically connected to the first signal line, and the second electrode of the first transistor is electrically connected to the first conductor; the first electrode of the second transistor is electrically connected to the first signal line, and the gate and the second electrode of the second transistor are both connected to the second conductor; the first transistor and the second transistor are arranged in the first direction, the first electrode and the second electrode of the first transistor are arranged in the first direction, and the first electrode and the second electrode of the second transistor are arranged in the first direction; the first transistor includes a first active layer, and the second transistor includes a second active layer; the first active layer and the second active layer both extend along the first direction, the width of the first active layer in the second direction is smaller than the length of the first active layer in the first direction, and the width of the second active layer in the second direction is smaller than the length of
  • At least one embodiment of the present disclosure provides a display panel, wherein the first conductor and the second conductor are arranged at intervals in the first direction, and the first conductor extends along the second direction;
  • the sub-electrostatic release unit includes a first gate portion;
  • the second conductor includes a main body portion extending along the second direction and a second gate portion connected to the main body portion and extending along the second direction, the first gate portion and the second gate portion are arranged at intervals in the first direction, and the first gate portion and the second gate portion are located between the main bodies of the first conductor and the second conductor; a portion of the first gate portion overlapping with the first active layer constitutes a gate of the first transistor, a portion of the second gate portion overlapping with the second active layer constitutes a gate of the second transistor, and the first gate portion is electrically connected to the first signal line.
  • the first gate portion includes a first strip portion extending along the first direction and a gate connection structure electrically connected to the first strip portion, the gate connection structure protrudes from the first strip portion in the second direction toward the first signal line from the first strip portion, and the gate connection structure is electrically connected to the first signal line through a first via;
  • the first gate portion also includes a first protrusion electrically connected to the first strip portion, the first protrusion protrudes from the first strip portion in the second direction away from the first signal line from the first strip portion, and a portion of the first protrusion overlapping with the first active layer constitutes the gate of the first transistor;
  • the second gate portion includes a second strip portion extending along the first direction and a second protrusion electrically connected to the second strip portion, the second protrusion protrudes from the second strip portion in the second direction from the second strip portion, and a portion of the second protrusion overlapping with the second active layer constitutes the gate of the second transistor.
  • At least one embodiment of the present disclosure provides a display panel, wherein the second protrusion protrudes from the second strip portion in the second direction away from the first signal line, the first strip portion and the second strip portion are basically aligned in the first direction, and the first protrusion and the second protrusion are basically aligned in the first direction.
  • At least one embodiment of the present disclosure provides a display panel, wherein the first active layer and the second active layer constitute a continuous, integrally formed electrostatic release semiconductor layer, and the electrostatic release semiconductor layer is generally in the shape of a strip extending along the first direction; the sub-electrostatic release unit also includes a data connection structure, which is electrically connected to the first signal line and protrudes from the first signal line in the second direction toward the electrostatic release semiconductor layer from the first signal line, and the first end of the data connection structure close to the first signal line in the second direction is electrically connected to the gate connection structure through the first via hole, and the second end of the data connection structure away from the first signal line in the second direction is electrically connected to the electrostatic release semiconductor layer through a second via hole, and the second via hole is located between the first protrusion and the second protrusion in the first direction.
  • At least one embodiment of the present disclosure provides a display panel, wherein the sub-electrostatic release unit also includes a first connection structure and a second connection structure; the first end of the first connection structure in the first direction is connected to the first conductor through a third via, and the second end of the first connection structure in the first direction is connected to the first active layer through a fourth via; the first end of the second connection structure in the first direction is connected to the main body of the second conductor through a fifth via, and the second end of the second connection structure in the first direction is connected to the second active layer through a sixth via.
  • At least one embodiment of the present disclosure provides a display panel, wherein the electrostatic release semiconductor layer is in a straight strip shape and is located on a side of the first strip portion and the second strip portion away from the first signal line.
  • a display panel further comprising: a reset voltage line and a reset voltage lead.
  • the reset voltage line is configured to provide a reset voltage signal to the sub-pixel, and includes a lead portion located in the non-display area, the lead portion of the reset voltage lead is located between two adjacent electrostatic release units and extends along the first direction, and the adjacent J lead portions are electrically connected via a reset connection line extending along the second direction; the first end of the reset voltage lead is electrically connected to the reset connection line, and the second end of the reset voltage lead is electrically connected to a drive circuit, and the drive circuit is configured to provide the reset voltage signal.
  • At least one embodiment of the present disclosure provides a display panel in which the width of the region where the driving circuit is located in the second direction is smaller than the width of the electrostatic release region in the second direction.
  • At least one embodiment of the present disclosure provides a display panel, which includes: a display area, a non-display area, a first signal line, and a plurality of electrostatic release units.
  • the display area includes sub-pixels; the non-display area at least partially surrounds the display area and includes an electrostatic release area; the first signal line extends from the display area to the electrostatic release area as a whole along a first direction, and is configured to provide a first display signal to the sub-pixel;
  • a plurality of electrostatic release units are arranged in the first direction, each of the electrostatic release units includes at least one sub-electrostatic release unit, each of the at least one sub-electrostatic release unit includes an electrostatic release circuit and a first conductor, the electrostatic release circuit is electrically connected to the first signal line and the first conductor, and is configured to move the charge on the first signal line toward the first conductor; in the plurality of electrostatic release units, the orthographic projections of every two adjacent electrostatic release units on a
  • At least one embodiment of the present disclosure provides a display panel, which includes: a display area, a non-display area, a first signal line, and a plurality of electrostatic release units.
  • the display area includes sub-pixels; the non-display area at least partially surrounds the display area and includes an electrostatic release region; the first signal line extends from the display area to the electrostatic release region as a whole along a first direction and is configured to provide a first display signal to the sub-pixel; a plurality of electrostatic release units are arranged in the first direction, each of the electrostatic release units includes at least one sub-electrostatic release unit, each of the at least one sub-electrostatic release unit includes an electrostatic release circuit and a first conductor, the electrostatic release circuit is electrically connected to the first signal line and the first conductor, and is configured to move the charge on the first signal line toward the first conductor; the non-display area includes a lead area, the lead area is provided with a driving circuit, and the driving circuit is configured
  • At least one embodiment of the present disclosure provides a display panel, which includes: a display area, a non-display area, a first signal line, and a plurality of electrostatic release units.
  • the display area includes sub-pixels; the non-display area at least partially surrounds the display area and includes an electrostatic release area; the first signal line extends from the display area to the electrostatic release area as a whole along a first direction, and is configured to provide a first display signal to the sub-pixel; a plurality of electrostatic release units are arranged in the first direction, each of the electrostatic release units includes at least one sub-electrostatic release unit, each of the at least one sub-electrostatic release unit includes an electrostatic release circuit and a first conductor, the electrostatic release circuit is electrically connected to the first signal line and the first conductor, and is configured to move the charge on the first signal line toward the first conductor; the size of the electrostatic release circuit in the second direction is smaller than the size of the electrostatic release circuit in the first direction,
  • FIG1 is a schematic diagram of an arrangement of electrostatic discharge units of a display panel
  • FIG2 is a schematic diagram of a planar structure of a display panel provided in an embodiment of the present disclosure
  • FIG3 is a schematic diagram of a local sub-pixel of the display area in FIG2 ;
  • FIG4A is a schematic diagram of an arrangement of an electrostatic discharge unit of a display panel provided by an embodiment of the present disclosure
  • FIG4B is a partial enlarged schematic diagram of FIG4A including an electrostatic release group
  • 4C is a schematic diagram showing the arrangement of another electrostatic discharge unit in the electrostatic discharge area of the display panel provided by an embodiment of the present disclosure
  • 4D is a schematic diagram of the arrangement of another electrostatic discharge unit in the electrostatic discharge area of the display panel provided by an embodiment of the present disclosure
  • 4E is a schematic diagram showing the arrangement of another electrostatic discharge unit in the electrostatic discharge area of the display panel provided by an embodiment of the present disclosure
  • FIG5A is a schematic diagram of an electrostatic discharge circuit of a sub-electrostatic discharge unit of a display panel provided by an embodiment of the present disclosure
  • FIG5B is a schematic diagram of a specific electrostatic discharge circuit of a sub-electrostatic discharge unit of a display panel provided by an embodiment of the present disclosure
  • FIG6A is a schematic diagram of a pixel circuit of a sub-pixel provided in at least one embodiment of the present disclosure
  • FIG6B is a circuit diagram of a specific implementation example of the pixel circuit shown in FIG6A ;
  • FIG6C is a signal timing diagram of a driving method for a pixel circuit provided by at least one embodiment of the present disclosure.
  • FIG. 7A is a schematic plan view of the structure of a sub-electrostatic discharge unit of a display panel provided by at least one embodiment of the present disclosure
  • FIG7B is a schematic diagram of a semiconductor layer of the sub-electrostatic discharge unit shown in FIG7A ;
  • FIG7C is a schematic diagram of a first conductive layer of the sub-electrostatic release unit shown in FIG7A ;
  • FIG7D is a schematic diagram of an interlayer insulating layer of the sub-electrostatic discharge unit shown in FIG7A ;
  • FIG7E is a schematic diagram of a second conductive layer of the sub-electrostatic release unit shown in FIG7A ;
  • FIG7F is a schematic cross-sectional view along line A1-A2 in FIG7A ;
  • FIG8 is a schematic diagram of several special-shaped display panels including an electrostatic discharge unit provided by an embodiment of the present disclosure
  • FIG9A is a schematic diagram of a Y-shaped display panel provided in an embodiment of the present disclosure.
  • FIG9B is a partial schematic plan view of a Y-shaped display panel including an electrostatic discharge area and a lead area;
  • FIG9C is a schematic diagram of a partial semiconductor layer shown in FIG9B ;
  • FIG9D is a schematic diagram of a partial first conductive layer shown in FIG9B ;
  • FIG9E is a schematic diagram of a local interlayer insulating layer shown in FIG9B ;
  • FIG9F is a schematic diagram of a partial second conductive layer shown in FIG9B ;
  • FIG10 is a schematic diagram of a data selection circuit of a display panel provided by an embodiment of the present disclosure.
  • FIG11 is a timing diagram of the operation of the data selection circuit shown in FIG10;
  • FIG12A is a structural plan view of a data selection unit of a display panel provided by an embodiment of the present disclosure.
  • FIG12B is a schematic diagram of a semiconductor layer of the data selection unit shown in FIG12A;
  • FIG12C is a schematic diagram of a first conductive layer of the data selection unit shown in FIG12A;
  • FIG12D is a schematic diagram of an interlayer insulating layer of the data selection unit shown in FIG12A;
  • FIG12E is a schematic diagram of a second conductive layer of the data selection unit shown in FIG12A;
  • FIG13A is a schematic diagram of a heart-shaped display panel provided by an embodiment of the present disclosure.
  • FIG13B is a partial plan view of a heart-shaped display panel including an electrostatic discharge area and a lead area;
  • FIG14A is a schematic diagram of a D-shaped display panel provided in an embodiment of the present disclosure.
  • FIG14B is a partial plan view of a D-shaped display panel including an electrostatic discharge area and a lead area;
  • FIG15A is a schematic diagram of an O-shaped display panel provided in an embodiment of the present disclosure.
  • FIG15B is a partial schematic plan view of an O-shaped display panel including an electrostatic discharge area and a lead area;
  • FIG16A is a schematic diagram of an I-shaped display panel provided in an embodiment of the present disclosure.
  • FIG. 16B is a partial plan view of an I-shaped display panel including an electrostatic discharge area and a lead area.
  • substantially aligned and “substantially the same” include certain errors, taking into account the errors associated with the measurement of specific quantities (e.g., limitations of the measurement system), and mean within an acceptable range of deviation for a specific value determined by a person of ordinary skill in the art.
  • substantially can mean within one or more standard deviations, and unless otherwise specified, can mean within a 10% or 5% deviation range of the value.
  • direct connection in the present disclosure means that two structures connected to each other (for example, A and B are directly connected, etc.) are in contact with each other, and there is no other structure between the two structures connected to each other as a medium for the connection between the two structures.
  • the two structures directly connected to each other can be a continuous integrated structure, in which case the materials of the two structures directly connected to each other are the same, and the two structures can be formed by the same composition process to simplify the manufacturing process of the display substrate; or, the materials of the two structures directly connected to each other can also be different, for example, the two structures directly connected to each other are both conductive signal lines, and the two structures can respectively use materials that match their functions to meet the requirements for different performances, such as different conductivity.
  • “same-layer arrangement” in the present disclosure refers to the relationship between multiple film layers formed after the same step (e.g., the same patterning process) is performed on a film formed of the same material. "Same-layer arrangement” here does not always mean that the thickness of the multiple film layers is the same or the height of the multiple film layers in the cross-sectional view is the same.
  • the transistors used in all examples of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. According to the role in the circuit, the transistors used in the examples of the present disclosure are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the examples of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, the source is called the first pole and the drain is called the second pole.
  • the switching transistor used in the examples of the present disclosure includes at least one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level, and the N-type switching transistor is turned on when the gate is at a high level and is turned off when the gate is at a low level.
  • an electrostatic discharge unit can be set to release the charges on the signal lines to protect the display circuit well.
  • FIG1 is a schematic diagram of the arrangement of electrostatic discharge units of a display panel.
  • the display panel shown in FIG1 the display panel includes a plurality of signal lines Data1, Data2...DataN, and a plurality of electrostatic discharge units electrically connected to the plurality of signal lines Data1, Data2...DataN are provided, namely, the ESD units represented by the rectangular frame in FIG1 , so as to perform electrostatic discharge on the plurality of signal lines Data1, Data2...DataN respectively.
  • the plurality of electrostatic discharge units are arranged in the horizontal direction, for example, when an electrostatic discharge unit needs to be provided for each signal line, and in order to achieve high resolution, the density of the signal lines is very high, the space left for providing more electrostatic discharge units is very limited.
  • the edge shape of some special-shaped screens is irregular, and the size of the bottom frame area of the special-shaped screen is very small, and it often does not have the width of the frame area of the rectangular display screen that is sufficient to provide a plurality of electrostatic discharge units, and a large number of electrostatic discharge units cannot be provided.
  • At least one embodiment of the present disclosure provides a display panel, which includes: a display area, a non-display area, a first signal line, and a plurality of electrostatic release units.
  • the display area includes sub-pixels; the non-display area at least partially surrounds the display area and includes an electrostatic release region; the first signal line extends from the display area to the electrostatic release region as a whole along a first direction and is configured to provide a first display signal to the sub-pixel; a plurality of electrostatic release units are arranged in the first direction, each of the electrostatic release units includes at least one sub-electrostatic release unit, each of the at least one sub-electrostatic release unit includes an electrostatic release circuit and a first conductor, the electrostatic release circuit is electrically connected to the first signal line and the first conductor, and is configured to move the charge on the first signal line toward the first conductor; the plurality of electrostatic release units include two adjacent electrostatic release units adjacent in a second direction, the second direction is perpendic
  • At least one embodiment of the present disclosure provides a display panel, which includes: a display area, a non-display area, a first signal line, and a plurality of electrostatic release units.
  • the display area includes sub-pixels; the non-display area at least partially surrounds the display area and includes an electrostatic release region; the first signal line extends from the display area to the electrostatic release region as a whole along a first direction and is configured to provide a first display signal to the sub-pixel; a plurality of electrostatic release units are arranged in the first direction, each of the electrostatic release units includes at least one sub-electrostatic release unit, each of the at least one sub-electrostatic release unit includes an electrostatic release circuit and a first conductor, the electrostatic release circuit is electrically connected to the first signal line and the first conductor, and is configured to move the charge on the first signal line toward the first conductor; among the plurality of electrostatic release units, the orthographic projections of every two adjacent electrostatic release units on a surface parallel to
  • At least one embodiment of the present disclosure provides a display panel, which includes: a display area, a non-display area, a first signal line, and a plurality of electrostatic release units.
  • the display area includes sub-pixels; the non-display area at least partially surrounds the display area and includes an electrostatic release region; the first signal line extends from the display area to the electrostatic release region as a whole along a first direction and is configured to provide a first display signal to the sub-pixel; a plurality of electrostatic release units are arranged in the first direction, each of the electrostatic release units includes at least one sub-electrostatic release unit, each of the at least one sub-electrostatic release unit includes an electrostatic release circuit and a first conductor, the electrostatic release circuit is electrically connected to the first signal line and the first conductor, and is configured to move the charge on the first signal line toward the first conductor; the non-display area includes a lead area, the lead area is provided with a driving circuit, and the driving circuit is configured
  • At least one embodiment of the present disclosure provides a display panel, which includes: a display area, a non-display area, a first signal line, and a plurality of electrostatic release units.
  • the display area includes sub-pixels; the non-display area at least partially surrounds the display area and includes an electrostatic release area; the first signal line extends from the display area to the electrostatic release area as a whole along a first direction, and is configured to provide a first display signal to the sub-pixel; a plurality of electrostatic release units are arranged in the first direction, each of the electrostatic release units includes at least one sub-electrostatic release unit, each of the at least one sub-electrostatic release unit includes an electrostatic release circuit and a first conductor, the electrostatic release circuit is electrically connected to the first signal line and the first conductor, and is configured to move the charge on the first signal line toward the first conductor; the size of the electrostatic release circuit in the second direction is smaller than the size of the electrostatic release circuit in the first direction,
  • FIG2 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure
  • FIG3 is a schematic diagram of a local sub-pixel of the display area in FIG2.
  • the display panel 10 provided by at least one embodiment of the present disclosure includes: a display area 1, a non-display area 2, a first signal line 01, and a plurality of electrostatic discharge units EU.
  • the display area 1 includes a plurality of sub-pixels 100, for example, as shown in FIG3, the plurality of sub-pixels are arranged in an array; of course, FIG3 is only an exemplary schematic diagram of a local sub-pixel of the display area 1, and the specific arrangement of the plurality of sub-pixels is not limited to the situation shown in FIG3.
  • the non-display area 2 at least partially surrounds the display area 1 and includes an electrostatic discharge area 20; the first signal line 01 extends from the display area 1 to the electrostatic discharge area 20 as a whole along the first direction D1, and is configured to provide a first display signal to the sub-pixel 100.
  • FIG4A is a schematic diagram of the arrangement of an electrostatic discharge unit of a display panel provided by an embodiment of the present disclosure in an electrostatic discharge area
  • FIG4B is a partial enlarged schematic diagram of FIG4A including an electrostatic discharge group.
  • multiple electrostatic release units EU are arranged in a first direction D1
  • each electrostatic release unit EU includes at least one sub-electrostatic release unit SEU.
  • Each of the at least one sub-electrostatic release unit SEU includes an electrostatic release circuit EC and a first conductor C1.
  • the electrostatic release circuit EC is electrically connected to the first signal line 01 and the first conductor C1, and is configured to move the charge on the first signal line 01 toward the first conductor C1, thereby reducing the charge on the first signal line 01; for example, each electrostatic release unit EU includes multiple sub-electrostatic release units SEU, and each sub-electrostatic release unit SEU is electrically connected to a first signal line 01 to perform electrostatic release on the first signal line 01.
  • the feature "the first signal line extends along the first direction as a whole” means that the routing trend of the first signal line is along the first direction, including the following situations: for example, the first signal line can be a straight line extending along the first direction; or, at least a portion of the first signal line has a certain bend or is inclined relative to the first direction, but the direction from the starting end to the ending end of the first signal line is along the first direction.
  • first signal line groups Data1, Data2, Data3, Data4...Data n-1 and Data n in Figure 4A respectively represent one or more first signal lines electrically connected to an electrostatic release unit EU and may respectively include multiple first signal lines 01 electrically connected to multiple sub-electrostatic release units SEU in the one electrostatic release unit EU.
  • the multiple electrostatic release units EU of the display panel 10 constitute a plurality of electrostatic release unit groups EUG arranged at intervals in the second direction D2, each electrostatic release unit group EUG includes M sub-electrostatic release unit groups SEUG, each sub-electrostatic release unit group SEUG includes N electrostatic release units EU, each electrostatic release unit EU includes Q sub-electrostatic release units SEU, M and Q are positive integers greater than or equal to 1, and N is a positive integer greater than or equal to 2.
  • the plurality of electrostatic discharge units EU include two adjacent electrostatic discharge units adjacent to each other in the second direction D2, the two adjacent electrostatic discharge units are, for example, a first electrostatic discharge unit EU1 and a second electrostatic discharge unit EU2, and the second direction D2 is perpendicular to the first direction D1.
  • the orthographic projections of the two adjacent electrostatic discharge units on a plane parallel to the first direction D1 do not overlap each other, and the orthographic projections on a plane parallel to the second direction D2 at least partially overlap each other, so that the first electrostatic discharge unit EU1 and the second electrostatic discharge unit EU2 are not only staggered in the first direction D1, but also staggered in the second direction D2, which can greatly reduce the space occupied by the plurality of electrostatic discharge units EU in the second direction D2, so that when the size of the electrostatic discharge area 20 in the second direction D2 is small, it is also possible to set more electrostatic discharge units.
  • the pixel array of the display area includes a plurality of sub-pixel columns extending along the first direction D1 and arranged in the second direction D2, and a plurality of sub-pixel rows extending along the second direction D2 and arranged in the first direction D1.
  • the display panel 10 includes a plurality of first signal lines 01, and one first signal line 01 provides a first display signal to a corresponding sub-pixel column.
  • the arrangement density of the sub-pixel columns is very high, so the arrangement density of the first signal lines 01 is also very high.
  • a sub-electrostatic discharge unit SEU needs to be set for each first signal line 01.
  • the electrostatic release area needs to have a sufficient size in the second direction D2 to set so many sub-electrostatic release units SEU.
  • the space left for setting more sub-electrostatic release units in the display panel 10 is very limited, for example, when the display panel 10 is an irregular display panel, the edge shape of the irregular display panel is irregular, and the size of the border area at the bottom of the irregular display panel is very small, that is, the size of the electrostatic release area 20 in Figure 2 in the second direction D2 is very small.
  • the above technical solution provided by the present disclosure can still achieve a sub-electrostatic release unit SEU for each first signal line 01 while achieving high resolution, thereby achieving a better electrostatic release effect.
  • the orthographic projections of the two adjacent electrostatic release units on the surface parallel to the second direction D2 at least partially overlap with each other can be understood as: the orthographic projections of at least part of the first electrostatic release unit EU1 and at least part of the second electrostatic release unit EU2 on the surface parallel to the second direction D2 at least partially overlap with each other, that is, as long as the orthographic projections of the two adjacent electrostatic release units on the surface parallel to the second direction D2 overlap, including the situation where the orthographic projection of part or all of the first electrostatic release unit EU1 on the surface parallel to the second direction D2 overlaps with the orthographic projection of the second electrostatic release unit EU2 on the surface parallel to the second direction D2, or the orthographic projection of part or all of the second electrostatic release unit EU2 on the surface parallel to the second direction D2 overlaps with the orthographic projection of the first electrostatic release unit EU1 on the surface parallel
  • FIG4B is a partially enlarged schematic diagram of FIG4A including an electrostatic release group.
  • the first electrostatic release unit EU1 includes three sub-electrostatic release units, namely, a first sub-electrostatic release unit S1a, a second sub-electrostatic release unit S2a, and a third sub-electrostatic release unit S3a.
  • the three sub-electrostatic release units S1a/S2a/S3a are respectively electrically connected to three first signal lines 01a/01b/01c arranged continuously in the second direction D2 to release the static electricity on the three first signal lines 01a/01b/01c, respectively. That is, the first signal line group Data1 in Figure 4A includes three first signal lines 01a/01b/01c.
  • the second electrostatic release unit EU2 includes three sub-electrostatic release units, namely, a first electrostatic release unit S1b, a second sub-electrostatic release unit S2b, and a third sub-electrostatic release unit S3b.
  • the three sub-electrostatic release units S1b/S2b/S3b are respectively electrically connected to three first signal lines 01d/01e/01f arranged continuously in the second direction D2, so as to release the static electricity on the three first signal lines 01d/01e/01f respectively. That is, the first signal line group Data1 in Figure 4A includes three first signal lines 01d/01e/01f.
  • the orthographic projections of the second electrostatic discharge unit EU2 and the first electrostatic discharge unit EU1 on a plane parallel to the second direction D2 at least partially overlap each other.
  • the orthographic projections of the multiple sub-electrostatic discharge units in the second electrostatic discharge unit EU2 and the multiple sub-electrostatic discharge units of the first electrostatic discharge unit EU1 on a plane parallel to the second direction D2 at least partially overlap each other, so as to effectively reduce the space occupied by the multiple electrostatic discharge units EU in the second direction D2.
  • At least two sub-electrostatic release units SEU such as the third sub-electrostatic release unit S3a of the first electrostatic release unit EU1 and the second sub-electrostatic release unit S2b of the second electrostatic release unit EU2, have their orthographic projections on the surface parallel to the first direction D1 not overlapping with each other and their orthographic projections on the surface parallel to the second direction D2 at least partially overlapping with each other, so as to further reduce the space occupied by the multiple electrostatic release units EU in the second direction D2.
  • the size of the electrostatic discharge circuit EC in the second direction D2 is smaller than the size of the electrostatic discharge circuit EC in the first direction D1.
  • the layout of each component of the electrostatic discharge circuit EC can be designed so that, while providing sufficient space for setting the electrostatic discharge circuit, the space in the first direction D2 is fully utilized, and the space occupied by the electrostatic discharge circuit EC in the second direction D2 is reduced, so that it is beneficial to set more sub-electrostatic discharge units in the second direction D2, realize electrostatic discharge for each first signal line, and meet the electrostatic discharge requirements of the display panel with a very small size of the electrostatic discharge area in the second direction D2.
  • At least one first signal line 01 includes a recessed portion located in the electrostatic release area 20.
  • the first signal line 01d includes a recessed portion P1 located in the electrostatic release area 20, and the recessed portion P1 constitutes a groove G1 that is recessed toward one side in the second direction D2.
  • the sub-electrostatic release unit adjacent to the groove G1, that is, the third sub-electrostatic release unit S3a of the first electrostatic release unit EU1 is at least partially located in the groove G1 to achieve misalignment and reduce the space occupied by multiple sub-electrostatic release units in the second direction D2.
  • the first signal line 01c electrically connected to the third sub-electrostatic release unit S3a located in the groove G1 is adjacent to the first signal line 01d having the groove G1; or, in other embodiments, the sub-electrostatic release unit located in the groove is electrically connected to the first signal line having the groove.
  • At least one electrostatic release unit among the multiple electrostatic release units EU includes two adjacent sub-electrostatic release units SEU in the second direction D2, and two adjacent signal lines, for example, the first signal line 01c and the first signal line 01d, both include a recessed portion P0/P1 located in the electrostatic release area 20, and the recessed portion P0 of the first signal line 01c and the recessed portion P1 of the first signal line 01d constitute a groove recessed toward the same side in the second direction D2, and two adjacent sub-electrostatic release units S2a/S3a are respectively at least partially located in the groove G0 formed by the recessed portion P0 of the first signal line 01c and the groove G1 formed by the recessed portion P1 of the first signal line 01d, so as to further effectively reduce the total width of the multiple electrostatic release units in the second direction D2 to meet the requirement of a narrower electrostatic release area.
  • the first signal line 01d electrically connected to the first sub-electrostatic release unit SEU of the first electrostatic release unit EU1 includes a first recessed portion P1 and a second recessed portion P2; the first recessed portion P1 constitutes a first groove G1 recessed toward the first side in the second direction D2; the second recessed portion P2 constitutes a second groove G2 recessed toward the second side opposite to the first side in the second direction D2, and is arranged with the first recessed portion G1 in the second direction D2, the first electrostatic release unit EU1 and the second electrostatic release unit EU2 are two adjacent electrostatic release units to each other, the orthographic projection of the first electrostatic release unit EU1 in parallel to the first direction D1 is located within the orthographic projection of the first groove G1 in parallel to the first direction D1, and the orthographic projection of the second electrostatic release unit EU2 in parallel to the first direction D1 is located within the orthographic projection of the second groove G2 in parallel to the first direction D
  • the third sub-electrostatic release unit S3a of the first electrostatic release unit EU1 and the first sub-electrostatic release unit S1b of the second electrostatic release unit EU2 are two sub-electrostatic release units adjacent to each other, the orthographic projection of the third sub-electrostatic release unit S3a in parallel to the first direction D1 is located within the orthographic projection of the first groove G1 in parallel to the first direction D1, and the orthographic projection of the first sub-electrostatic release unit S1b in parallel to the first direction D1 is located within the orthographic projection of the second groove G2 in parallel to the first direction D1, so as to reduce the space occupied by the adjacent electrostatic release units in the second direction D2.
  • first signal line 01c and the first signal line 01b adjacent to the first signal line 01d in the second direction D2 also have a first recessed portion and a second recessed portion similar to the first signal line 01d, and the orthographic projections of the first recessed portions and the second recessed portions of the plurality of first signal lines in parallel to the first direction D1 overlap with each other, so as to match the misalignment of the adjacent electrostatic release units in the second direction, and reduce the total width of the plurality of electrostatic release units and the plurality of first signal lines as a whole in the second direction D2.
  • At least part of the multiple electrostatic release unit groups EUG are arranged periodically in the second direction D2, and one electrostatic release unit group EUG is a repeating unit in the period, so that the arrangement of the multiple electrostatic release unit groups is relatively regular, which is conducive to making and maintaining the uniformity of the routing of multiple first signal lines, thereby maintaining the uniformity of the first display signals transmitted by the multiple first signal lines, and the uniformity of the electrostatic release effects on the multiple first signal lines.
  • the number of sub-electrostatic discharge units SEU included in an electrostatic discharge unit group is M*N*Q.
  • M is equal to 1
  • N is equal to 2
  • Q is equal to 3.
  • the width of an electrostatic discharge unit group EUG in the second direction D2 is less than or equal to 129.5 ⁇ m. The higher the resolution, the higher the requirement for reducing the total width of multiple electrostatic discharge units in the second direction D2.
  • the resolution of the display panel 10 is X*Y
  • X represents the number of rows of the pixel array in the display area 1
  • Y represents the number of columns of the pixel array in the display area 1
  • X is greater than or equal to 960
  • the above-mentioned arrangement provided by the embodiment of the present disclosure can also meet the requirement for the total width of multiple electrostatic discharge units in the second direction D2.
  • the non-display area 2 includes a lead area 21, which is a common bonding area.
  • the lead area 21 is provided with a chip on flex (COF, or, chip on film), and the chip on film includes a flexible circuit board (FPC) 23.
  • the flexible circuit board 23 includes a driving circuit IC, and the driving circuit IC is configured to provide a first display signal to the data line DL; the electrostatic discharge area 20 is located between the lead area 21 and the display area 1.
  • a plurality of sub-electrostatic discharge units SEU connected to the first signal line 01 that provides the first display signal to all sub-pixels 100 are all located in the non-display area 2 on the same side of the display area 1 in the first direction D1.
  • the sub-electrostatic discharge units SEU connected to the data line DL that provides the data signal to all sub-pixel columns are all located on the same side of the display area 1, for example, they are all arranged along one side of the display area 1, rather than a part of the sub-electrostatic discharge units SEU being arranged on the first side of the display area 1, and another part of the sub-electrostatic discharge units SEU being arranged on the second side of the display area 1 opposite to the first side thereof.
  • the non-display area 2 also includes a frame area, and the frame area includes a first frame area 2a and a second frame area 2b. The first frame area 2a is located on the first side of the display area 1.
  • the sub-electrostatic release units SEU connected to the data lines DL that provide data signals to all sub-pixel columns are located in the first frame area 2a, and are not arranged in the second frame area 2b. In this way, it is only necessary to set the driving circuit at a position adjacent to the first frame area 2a, which reduces the difficulty of manufacturing and simplifies the structure. Even in this case, the arrangement of the sub-electrostatic release units SEU provided by the embodiment of the present disclosure can also meet the requirement of using the limited width of the same side of the display area 1 in the second direction D2 to set a large number of sub-electrostatic release units SEU.
  • planar shape of the display panel is the above-mentioned special-shaped display panel 10
  • a large number of sub-electrostatic release units SEU can be set by using the limited width of a part of the special-shaped edge in the second direction D2, taking into account a higher PPI.
  • the first frame region 2a is located between the lead region 21 and the display region 1, and the second frame region 2b is located on the second side of the display region 1 opposite to the first side thereof.
  • a first power lead PL is provided in the first frame region 2a, and the first power lead PL is configured to provide a first power supply voltage VDD to the sub-pixel 100;
  • the lead region 21 includes a data selection region 22 located on a side of the frame region away from the display region 1, and a data selection unit is provided in the data selection region 22, and the electrostatic discharge region 20 is located between the first power lead PL and the data selection region 22.
  • the first power lead PL is configured to provide a second power supply voltage VSS to the sub-pixel 100.
  • the first power lead PL is arranged on the same layer as the gate T01g of the first electrostatic release transistor T01 described below, and is connected to the cathode of the sub-pixel covering the entire display area 1 in the non-display area 2 through a via or directly overlapped;
  • the material of the first power lead PL providing the second power supply voltage VSS is a transparent conductive material, such as indium zinc oxide (ITO), indium zinc oxide (IZO), etc.
  • Fig. 4C is a schematic diagram showing the arrangement of another electrostatic discharge unit in an electrostatic discharge area of a display panel provided by an embodiment of the present disclosure.
  • the embodiment shown in Fig. 4C is different from that in Fig. 4A in the following ways.
  • M is equal to 2
  • N is equal to 2
  • Q is equal to 3.
  • the M sub-electrostatic release unit groups SEUG include a first sub-electrostatic release unit group SEUG1 and a second sub-electrostatic release unit group SEUG2, and the first sub-electrostatic release unit group SEUG1 and the second sub-electrostatic release unit group SEUG2 are symmetrical with respect to the symmetry axis extending along the first direction D1, so that the arrangement of the multiple electrostatic release unit groups is relatively regular, which is conducive to making and maintaining the uniformity of the routing of multiple first signal lines, thereby maintaining the uniformity of the first display signals transmitted by the multiple first signal lines, and the uniformity of the electrostatic release effect on the multiple first signal lines.
  • the first sub-electrostatic release unit group and the second sub-electrostatic release unit group may also be asymmetric.
  • FIG. 4C Other features of the embodiment shown in FIG. 4C are the same as those of FIG. 4A and FIG. 4B , and reference may be made to the previous description.
  • FIG4D is a schematic diagram of the arrangement of another electrostatic discharge unit in the electrostatic discharge area of the display panel provided by an embodiment of the present disclosure.
  • the embodiment shown in FIG4D has the following differences from FIG4A.
  • the orthographic projections of the two on the plane parallel to the first direction D1 do not overlap with each other and are spaced apart from each other in the second direction D2, that is, the orthographic projections of the two on the plane parallel to the second direction D2 do not overlap with each other.
  • the distance between the two adjacent electrostatic discharge units in the second direction D2 is less than 1 micron, for example, the distance between the edges of the two adjacent electrostatic discharge units close to each other in the second direction D2 is less than 1 micron.
  • the width of an electrostatic release unit group in the second direction D2 is less than or equal to 294 ⁇ m, that is, the total width of 18 sub-electrostatic release units included in an electrostatic release unit group in the second direction D2 is 294 ⁇ m, so as to meet the requirement of providing sufficient space for setting up more electrostatic release units when the width of the electrostatic release area in the second direction D2 is narrower.
  • FIG. 4E is a schematic diagram of the arrangement of another electrostatic release unit in the electrostatic release area of the display panel provided by an embodiment of the present disclosure.
  • the difference between the embodiment shown in FIG. 4E and FIG. 4A is that, in the embodiment shown in FIG.
  • the orthographic projections of two adjacent electrostatic release units such as the first electrostatic release unit EU1 and the second electrostatic release unit EU2, on the surface parallel to the first direction D1 do not overlap with each other, and the orthographic projections on the surface parallel to the second direction D2 do not overlap with each other, so as to reduce the number of, for example, in each sub-electrostatic release unit group SEUG, the orthographic projections of two adjacent electrostatic release units on the surface parallel to the first direction D1 do not overlap with each other, and the orthographic projections on the surface parallel to the second direction D2 do not overlap with each other.
  • the orthographic projections of each two adjacent electrostatic release units EU on the surface parallel to the first direction D1 do not overlap with each other.
  • the other features of the embodiment shown in FIG. 4E are the same as those of FIG. 4A and FIG. 4B, and reference may be made to the previous description.
  • FIG5A is a schematic diagram of an electrostatic discharge circuit of a sub-electrostatic discharge unit of a display panel provided by an embodiment of the present disclosure.
  • the electrostatic discharge circuit EC includes a first sub-circuit 001, and the first sub-circuit 001 has a driving end, a first end, and a second end; the driving end and the first end of the first sub-circuit 001 are both electrically connected to the first signal line 01, and the second end of the first sub-circuit 001 is electrically connected to the first conductor C1.
  • the static electricity accumulated on the first signal line 01 can be conducted to the first conductor C1 through the first sub-circuit 001, thereby reducing the charge on the first signal line 01 and preventing the static electricity accumulated on the first signal line 01 from causing display defects.
  • the sub-electrostatic discharge unit SEU further includes a second conductor C2, the electrostatic discharge circuit EC is electrically connected to the first signal line 01 and the second conductor C2, and is configured to move the charge on the first signal line 01 toward the second conductor C2, thereby reducing the charge on the first signal line 01.
  • the electrostatic discharge circuit EC further includes a second sub-circuit 002, the second sub-circuit 002 has a driving end, a first end, and a second end, the first end of the second sub-circuit 002 is electrically connected to the first signal line 01, and the driving end and the second end of the second sub-circuit 002 are both connected to the second conductor C2.
  • the static electricity accumulated on the first signal line 01 can also be conducted to the second conductor C2 through the second sub-circuit 002, thereby reducing the charge on the first signal line 01 and preventing the static electricity accumulated on the first signal line 01 from causing display defects.
  • the electrostatic discharge circuit may include only the first sub-circuit but not the second sub-circuit.
  • the first sub-circuit 001 and the second sub-circuit 002 are arranged in the first direction D1, so as to reduce the total width of the first sub-circuit 001 and the second sub-circuit 002 in the second direction D2 by designing the arrangement of the first sub-circuit 001 and the second sub-circuit 002, thereby reducing the width of the sub-electrostatic release unit in the second direction D2 to meet the requirement of arranging more sub-electrostatic release units in the limited space in the second direction D2.
  • FIG5B is a schematic diagram of a specific electrostatic discharge circuit of a sub-electrostatic discharge unit of a display panel provided by an embodiment of the present disclosure.
  • the first sub-circuit 001 includes a first electrostatic discharge transistor T01
  • the second sub-circuit 002 includes a second electrostatic discharge transistor T02;
  • the gate T01g and the first pole T01s of the first electrostatic discharge transistor T01 are both electrically connected to the first signal line 01, and the second pole T01d of the first electrostatic discharge transistor T01 is electrically connected to the first conductor C1;
  • the first pole T02s of the second electrostatic discharge transistor T02 is electrically connected to the first signal line 01, and the gate T02g and the second pole T02d of the second electrostatic discharge transistor T02 are both connected to the second conductor C2.
  • the first conductor C1 is connected to the high voltage terminal VGH, and the second conductor C2 is connected to the low voltage terminal VGL.
  • the polarities of the voltages provided by the high voltage terminal VGH and the low voltage terminal VGL are opposite, for example, the polarity of the first voltage Vh provided by the high voltage terminal VGH is positive, and the polarity of the second voltage Vl provided by the low voltage terminal VGL is negative.
  • transistors can be divided into N-type and P-type transistors.
  • the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages)
  • the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages)
  • the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages)
  • the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages).
  • the working process of the electrostatic discharge circuit EC is as follows, taking the first electrostatic discharge transistor T01 and the second electrostatic discharge transistor T02 as N-type transistors as an example.
  • the first display signal for example, the data signal Vd described below
  • the gate T01g of the first electrostatic release transistor T01 responds to the high level and turns on the first electrostatic release transistor T01.
  • the second voltage Vl is at a low level, for example, -8V, -6V, etc.
  • the gate T02g of the second electrostatic release transistor T02 responds to the low level and turns off the second electrostatic release transistor T02.
  • the charge on the first signal line 01 is conducted to the first conductor C1 through the first electrostatic release transistor T01; when the first display signal (for example, the data signal Vd described below) transmitted on the first signal line 01 is at a high level, the gate T01g of the first electrostatic release transistor T01 responds to the high level and turns on the first electrostatic release transistor T01. When the signal Vd) is at a low level, the low level is, for example, -30V, -20V, -10V or other suitable voltages. The gate T01g of the first electrostatic release transistor T01 responds to the low level to turn off the first electrostatic release transistor T01.
  • the first display signal for example, the data signal Vd described below
  • Vd in the calculation formula represents the low level voltage of the first display signal transmitted on the first signal line 01
  • Vth represents the threshold voltage of the second electrostatic release transistor T02.
  • the second electrostatic release transistor T02 is turned on, and thus, the charge on the first signal line 01 is conducted to the second conductor C2 via the second electrostatic release transistor T02.
  • Vgs is greater than the threshold voltage of a normal transistor. In this way, when the first display signal transmitted on the first signal line 01 is at a high level or a low level, the static charge accumulated on the first signal line 01 can be released by the electrostatic discharge circuit EC shown in FIG. 5B .
  • a plurality of sub-pixels 100 are located in the display area 1.
  • some pixels in the plurality of sub-pixels 100 are dummy sub-pixels 1000, and the dummy sub-pixels 1000 do not participate in the display work.
  • the display substrate 10 is an organic light emitting diode (OLED) display substrate, and the light emitting device is an OLED.
  • the display substrate 10 may also include a plurality of scan lines and a plurality of data lines DL for providing scan signals (control signals) and data signals to the plurality of sub-pixels, thereby driving the plurality of sub-pixels.
  • the display substrate 10 may further include a power line, a detection line, etc.
  • FIG6A is a schematic diagram of a pixel circuit provided by at least one embodiment of the present disclosure.
  • the pixel circuit unit 100 includes a driving subcircuit 122, a compensation subcircuit 128, a data writing subcircuit 126, a storage subcircuit 127, a first light-emitting control subcircuit 123, a second light-emitting control subcircuit 124, and a first reset subcircuit 125 and a second reset subcircuit 129.
  • the driving sub-circuit 122 includes a control terminal 122a, a first terminal 122b, and a second terminal 122c, and is configured to be connected to the light emitting device 121 and control a driving current flowing through the light emitting device 121.
  • the control terminal 122a of the driving sub-circuit 122 is connected to the first node N1
  • the first terminal 122b of the driving sub-circuit 122 is connected to the second node N2 and is configured to receive the first power supply voltage VDD
  • the second terminal 122c of the driving sub-circuit 122 is connected to the third node N3.
  • the data writing subcircuit 126 includes a control terminal 126a, a first terminal 126b, and a second terminal 126c, wherein the control terminal 126a is configured to receive a first scanning signal Ga1, the first terminal 126b is configured to receive a data signal Vd, and the second terminal 126c is connected to a first terminal 122b (i.e., a second node N2) of the driving subcircuit 122.
  • the data writing subcircuit 126 is configured to write the data signal Vd into the first terminal 122b of the driving subcircuit 122 in response to the first scanning signal Ga1.
  • the first terminal 126b of the data writing subcircuit 126 is connected to the data line DL to receive the data signal Vd, and the control terminal 126a is connected to the gate line 11 as a scanning line to receive the first scanning signal Ga1.
  • the data writing sub-circuit 126 can be turned on in response to the first scanning signal Ga1, so that the data signal can be written to the first end 122b (the second node N2) of the driving sub-circuit 122, and the data signal can be stored in the storage sub-circuit 127, so that a driving current can be generated according to the data signal to drive the light-emitting device 121 to emit light, for example, in the light-emitting stage.
  • the compensation sub-circuit 128 includes a control terminal 128a, a first terminal 128b and a second terminal 128c.
  • the control terminal 128a of the compensation sub-circuit 128 is configured to receive a second scanning signal Ga2.
  • the first terminal 128b and the second terminal 128c of the compensation sub-circuit 128 are electrically connected to the second terminal 122c and the control terminal 122a of the driving sub-circuit 122, respectively.
  • the compensation sub-circuit 128 is configured to perform threshold compensation on the driving sub-circuit 122 in response to the second scanning signal Ga2.
  • the first scan signal Ga1 may be the same as the second scan signal Ga2.
  • the first scan signal Ga1 may be connected to the same signal output terminal as the second scan signal Ga2.
  • the first scan signal Ga1 may be transmitted through the same scan line as the second scan signal Ga2.
  • the first scan signal Ga1 may be different from the second scan signal Ga2.
  • the first scan signal Ga1 and the second scan signal Ga2 may be connected to different signal output terminals.
  • the first scan signal Ga1 and the second scan signal Ga2 may be transmitted through different scan lines.
  • the storage sub-circuit 127 includes a first terminal 127a and a second terminal 127b.
  • the first terminal 127a of the storage sub-circuit is configured to receive the first power supply voltage VDD, and the second terminal 127b of the storage sub-circuit is electrically connected to the control terminal 122a of the driving sub-circuit.
  • the storage subcircuit 127 is electrically connected to the control terminal 122a and the first voltage terminal vdd of the driving subcircuit 122, and is configured to store the data signal written by the data writing subcircuit 126.
  • the compensation subcircuit 128 can be turned on in response to the second scanning signal Ga2, so that the data signal written by the data writing subcircuit 126 can be stored in the storage subcircuit 127.
  • the compensation subcircuit 128 can electrically connect the control terminal 122a and the second terminal 122c of the driving subcircuit 122, so that the relevant information of the threshold voltage of the driving subcircuit 122 can also be correspondingly stored in the storage subcircuit, so that, for example, in the light emitting stage, the stored data signal and the threshold voltage can be used to control the driving subcircuit 122, so that the output of the driving subcircuit 122 is compensated.
  • the first light emitting control subcircuit 123 is connected to the first terminal 122b (second node N2) of the driving subcircuit 122 and the first voltage terminal vdd, and is configured to apply the first power supply voltage VDD of the first voltage terminal vdd to the first terminal 122b of the driving subcircuit 122 in response to the first light emitting control signal EM1.
  • the first light emitting control subcircuit 123 is connected to the first light emitting control terminal EM1, the first voltage terminal vdd, and the second node N2.
  • the second light emitting control subcircuit 124 is connected to the second light emitting control terminal EM2, the first terminal 134 of the light emitting device 121 and the second terminal 122c of the driving subcircuit 122, and is configured to respond to the second light emitting control signal so that the driving current can be applied to the light emitting device 121.
  • the second light-emitting control subcircuit 124 is turned on in response to the second light-emitting control signal EM2 provided by the second light-emitting control terminal EM2, so that the driving subcircuit 122 can be electrically connected to the light-emitting device 121 through the second light-emitting control subcircuit 124, thereby driving the light-emitting device 121 to emit light under the control of the driving current; while in the non-light-emitting stage, the second light-emitting control subcircuit 124 is turned off in response to the second light-emitting control signal EM2, thereby preventing current from flowing through the light-emitting device 121 to cause it to emit light, thereby improving the contrast of the corresponding display device.
  • the second light emitting control sub-circuit 124 may also be turned on in response to the second light emitting control signal EM2 , so that the reset sub-circuit may be combined to perform a reset operation on the driving sub-circuit 122 and the light emitting device 121 .
  • the second light emitting control signal EM2 may be the same as the first light emitting control signal EM1, for example, the second light emitting control signal EM2 may be connected to the same signal output terminal as the first light emitting control signal EM1, for example, the second light emitting control signal EM2 may be transmitted through the same light emitting control line as the first light emitting control signal EM1.
  • the second light emitting control signal EM2 may be different from the first light emitting control signal EM1.
  • the second light emitting control signal EM2 and the first light emitting control signal EM1 may be connected to different signal output terminals, respectively.
  • the second light emitting control signal EM2 and the first light emitting control signal EM1 may be transmitted through different light emitting control lines, respectively.
  • the first reset subcircuit 125 is connected to the first reset voltage terminal Vinit1 and the control terminal 122a (first node N1) of the driving subcircuit 122, and is configured to apply the first reset voltage Vinit1 to the control terminal 122a of the driving subcircuit 122 in response to the first reset control signal Rst1.
  • the second reset subcircuit 129 is connected to the second reset voltage terminal Vinit2 and the first terminal 134 (fourth node N4) of the light emitting device 121, and is configured to apply the second reset voltage Vinit2 to the first terminal 134 of the light emitting device 121 in response to the second reset control signal Rst2.
  • the first reset sub-circuit 125 and the second reset sub-circuit 129 can be turned on in response to the first reset control signal Rst1 and the second reset control signal Rst2, respectively, so that the second reset voltage Vinit2 can be applied to the first node N1 and the first reset voltage Vinit1 can be applied to the first end 134 of the light-emitting device 121, respectively, so that the driving sub-circuit 122, the compensation sub-circuit 128 and the light-emitting device 121 can be reset to eliminate the influence of the previous light-emitting stage.
  • the second reset control signal Rst2 of each row of sub-pixels can be the same signal as the first scanning signal Ga1 of the sub-pixels in the row, and the two can be transmitted through the same gate line (for example, the reset control line 220b in FIG. 3A ).
  • the first reset control signal Rst1 of each row of sub-pixels can be the same signal as the first scanning signal Ga1 of the sub-pixels in the previous row, and the two can be transmitted through the same gate line (for example, the reset control line 220a in FIG. 3A ).
  • the light emitting device 121 includes a first terminal 134 and a second terminal 135, the first terminal 134 of the light emitting device 121 is configured to be connected to the second terminal 122c of the driving subcircuit 122, and the second terminal 135 of the light emitting device 121 is configured to be connected to the second voltage terminal VSS.
  • the first terminal 134 of the light emitting device 121 can be connected to the fourth node N4 through the second light emitting control subcircuit 124.
  • Embodiments of the present disclosure include but are not limited to this case.
  • the first node N1, the second node N2, the third node N3 and the fourth node N4 do not necessarily represent actual existing components, but represent the meeting points of related circuit connections in the circuit diagram.
  • the symbol Vd can represent both the data signal terminal and the level of the data signal.
  • the symbols Ga1 and Ga2 can represent both the first scan signal and the second scan signal, and can also represent the first scan signal terminal and the second scan signal terminal.
  • the symbol Rst1 can represent both the first reset control terminal and the first reset control signal.
  • the symbol Rst2 can represent both the second reset control terminal and the second reset control signal.
  • the symbols Vinit1 and Vinit2 can represent both the first reset voltage terminal and the second reset voltage terminal and can also represent the first reset voltage and the second reset voltage.
  • the symbol VDD can represent both the first power supply voltage and the first power supply line.
  • the symbol VSS can represent both the common power supply voltage and the common power supply line. The following embodiments are the same as this and will not be repeated.
  • FIG6B is a circuit diagram of a specific implementation example of the pixel circuit shown in FIG6A.
  • the pixel circuit includes first to seventh transistors T1, T2, T3, T4, T5, T6, T7 and a storage capacitor Cst.
  • the first transistor T1 is used as a driving transistor, and the other second to seventh transistors are used as switching transistors.
  • the driving subcircuit 122 may be implemented as a first transistor T1.
  • the gate of the first transistor T1 serves as a control terminal 122a of the driving subcircuit 122 and is connected to the first node N1;
  • the first electrode of the first transistor T1 serves as a first terminal 122b of the driving subcircuit 122 and is connected to the second node N2;
  • the second electrode of the first transistor T1 serves as a second terminal 122c of the driving subcircuit 122 and is connected to the third node N3.
  • the data writing subcircuit 126 can be implemented as a second transistor T2.
  • the gate of the second transistor T2 is connected to the first scan line (first scan signal terminal Ga1) to receive the first scan signal
  • the first electrode of the second transistor T2 is connected to the data line DL (data signal terminal Vd) to receive the data signal
  • the second electrode of the second transistor T2 is connected to the first terminal 122b (second node N2) of the driving subcircuit 122.
  • the compensation subcircuit 128 can be implemented as a third transistor T3.
  • the gate, the first electrode and the second electrode of the third transistor T3 serve as the control terminal 128a, the first terminal 128b and the second terminal 128c of the compensation subcircuit, respectively.
  • the gate of the third transistor T3 is configured to be connected to the second scan line (the second scan signal terminal Ga2) to receive the second scan signal, the first electrode T3s of the third transistor T3 is connected to the second electrode T1d (the third node N3) of the first transistor T1, and the second electrode T3d of the third transistor T3 is electrically connected to the gate T1g (the first node N1) of the first transistor T1.
  • the storage subcircuit 127 can be implemented as a storage capacitor Cst, and the storage capacitor Cst includes a first plate Cst1 and a second plate Cst2, the first plate Cst2 is electrically connected to the first voltage terminal vdd, and the second plate Cst1 is electrically connected to the gate T1g (the first node N1) of the first transistor T1.
  • the first light emission control subcircuit 123 may be implemented as a fourth transistor T4.
  • a gate of the fourth transistor T4 is connected to the first light emission control line (first light emission control terminal EM1) to receive a first light emission control signal, a first electrode of the fourth transistor T4 is connected to the first voltage terminal vdd to receive a first power supply voltage, and a second electrode of the fourth transistor T4 is connected to the first terminal 122b (second node N2) of the driving subcircuit 122.
  • the light emitting device 121 is specifically implemented as a light emitting diode (LED), such as an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED) or an inorganic light emitting diode, such as a micro light emitting diode (Micro LED) or a micro OLED.
  • LED light emitting diode
  • OLED organic light emitting diode
  • QLED quantum dot light emitting diode
  • Micro LED micro light emitting diode
  • the light emitting device 121 can be a top emission structure, a bottom emission structure or a double-sided emission structure.
  • the light emitting device 121 can emit red light, green light, blue light or white light, etc.
  • the embodiments of the present disclosure do not limit the specific structure of the light emitting device.
  • the first end of the light emitting device 121 includes a first electrode (for example, an anode), which is connected to the fourth node N4 and configured to be connected to the second end 122c of the driving subcircuit 122 through the second light emitting control subcircuit 124.
  • the second end of the light emitting device 121 includes a second electrode (for example, a cathode), which is configured to be connected to the common power supply voltage terminal VSS to receive the common power supply voltage VSS.
  • the circuit that flows from the second end 122c of the driving subcircuit 122 into the light emitting device 121 determines the brightness of the light emitting device.
  • the common power supply voltage terminal VSS can be grounded, that is, VSS can be 0V.
  • the common power supply voltage VSS can be a negative voltage.
  • the second light emitting control subcircuit 124 can be implemented as a fifth transistor T5.
  • the gate of the fifth transistor T5 is connected to the second light emitting control line (the second light emitting control terminal EM2) to receive the second light emitting control signal
  • the first electrode of the fifth transistor T5 is connected to the second terminal 122c (the third node N3) of the driving subcircuit 122
  • the second electrode of the fifth transistor T5 is connected to the first terminal 134 (the fourth node N4) of the light emitting device 121.
  • the first reset subcircuit 125 can be implemented as a sixth transistor T6, and the second reset subcircuit can be implemented as a seventh transistor T7.
  • the gate of the sixth transistor T6 is configured to be connected to the first reset control terminal Rst1 to receive the first reset control signal Rst1, the first electrode of the sixth transistor T6 is connected to the first reset voltage terminal Vinit1 to receive the first reset voltage Vinit1, and the second electrode of the sixth transistor T6 is configured to be connected to the first node N1.
  • the gate of the seventh transistor T7 is configured to be connected to the second reset control terminal Rst2 to receive the second reset control signal Rst2, the first electrode of the seventh transistor T7 is connected to the second reset voltage terminal Vinit2 to receive the second reset voltage Vinit2, and the second electrode of the seventh transistor T7 is configured to be connected to the fourth node N4.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • the embodiments of the present disclosure are described by taking thin film transistors as examples.
  • the source and drain of the transistor used here may be symmetrical in structure, so the source and drain may be indistinguishable in structure.
  • one pole is directly described as the first pole and the other pole is directly described as the second pole.
  • the first to seventh transistors T1-T7 are all P-type transistors, such as low temperature polysilicon thin film transistors.
  • the disclosed embodiment does not limit the type of transistors. When the type of transistors changes, the connection relationship in the circuit can be adjusted accordingly.
  • each frame of image includes three stages, namely initialization stage 1, data writing and compensation stage 2, and light emitting stage 3.
  • the first scanning signal Ga1 and the second scanning signal Ga2 use the same signal
  • the first light-emitting control signal EM1 and the second light-emitting control signal EM2 use the same signal
  • the second reset control signal Rst2 and the first scanning signal Ga1/the second scanning signal Ga2 have the same waveform, that is, the second reset control signal Rst2 and the first scanning signal Ga1/the second scanning signal Ga2 can use the same signal
  • the first reset signal Rst1 of the sub-pixel in this row has the same waveform as the first scanning signal Ga1/the second scanning signal Ga2 of the sub-pixel in the previous row, that is, the same signal is used.
  • different signals can be used as the first scanning signal Ga1, the second scanning signal Ga2, the first reset control signal Rst1, and the second reset control signal Rst2, and different signals can be used as the first light-emitting control signal EM1 and the second light-emitting control signal EM2.
  • the first reset control signal Rst1 is input to turn on the sixth transistor T6, and the first reset voltage Vinit1 is applied to the gate of the first transistor T1, thereby resetting the first node N1.
  • the first scanning signal Ga1, the second scanning signal Ga2 and the data signal Vd are input, the second transistor T2 and the third transistor T3 are turned on, the data signal Vd is written into the second node N2 by the second transistor T2, and the first node N1 is charged through the first transistor T1 and the third transistor T3 until the potential of the first node N1 changes to Vd+Vth, and the first transistor T1 is turned off, where Vth is the threshold voltage of the first transistor T1.
  • the potential of the first node N1 is stored in the storage capacitor Cst and maintained, that is, the voltage information with the data signal and the threshold voltage Vth is stored in the storage capacitor Cst, so as to provide grayscale display data and compensate the threshold voltage of the first transistor T1 itself in the subsequent light-emitting stage.
  • the second reset control signal Rst2 may be input to turn on the seventh transistor T7, and the second reset voltage Vinit2 may be applied to the fourth node N4, thereby resetting the fourth node N4.
  • the fourth node N4 may also be reset in the initialization phase 1, for example, the first reset control signal Rst1 and the second reset control signal Rst2 may be the same.
  • the embodiments of the present disclosure are not limited to this.
  • the first light emitting control signal EM1 and the second light emitting control signal EM2 are input to turn on the fourth transistor T4, the fifth transistor T5 and the first transistor T1, and the fifth transistor T5 applies the driving current to the OLED to make it emit light.
  • the value of the driving current Id flowing through the OLED can be obtained according to the following formula:
  • Vth represents the threshold voltage of the first transistor T1
  • VGS represents the voltage between the gate and the source (here, the first electrode) of the first transistor T1
  • K is a constant value related to the first transistor T1 itself.
  • the display substrate 10 includes a base substrate 200, a first signal line 01 disposed on the base substrate 200 and extending along a first direction D1 as a whole, and a second signal line 02 extending along a second direction D2 as a whole; for example, the first signal line 01 intersects with the second signal line 02 to define a plurality of sub-pixels 100.
  • each of the plurality of sub-pixels is not necessarily the first signal line 01 and the second signal line 02, and the first signal line 01 intersects with the second signal line 02 to define a sub-pixel means that the arrangement of the plurality of sub-pixels is consistent with the arrangement of the plurality of regions defined by the intersection of the first signal line 01 and the second signal line 02, that is, the plurality of sub-pixels correspond one-to-one to the region.
  • the first signal line 01 is a data line DL
  • the second signal line 02 is a gate line as a scanning signal line.
  • the first display signal is a data signal Vd
  • the first signal line 01 transmits the data signal Vd
  • each of at least some of the sub-pixels 100 includes the above-mentioned pixel circuit, and the pixel circuit includes the above-mentioned light-emitting device, a driving transistor T1, and a data writing transistor T2, and the data writing transistor T2 is configured to transmit the data signal Vd to the driving transistor T1 under the control of the first scanning signal Ga1
  • the driving transistor T1 is configured to control the size of the driving current flowing through the light-emitting device according to the data signal Vd
  • the light-emitting device is configured to receive the driving current and be driven by the driving current to emit light.
  • the first signal line may also be other types of signal lines.
  • the first signal line is not limited to the above-mentioned data line DL.
  • Figure 7A is a plan schematic diagram of the structure of a sub-electrostatic release unit of a display panel provided by at least one embodiment of the present disclosure
  • Figure 7B is a schematic diagram of the semiconductor layer of the sub-electrostatic release unit shown in Figure 7A
  • Figure 7C is a schematic diagram of the first conductive layer of the sub-electrostatic release unit shown in Figure 7A
  • Figure 7D is a schematic diagram of the interlayer insulating layer of the sub-electrostatic release unit shown in Figure 7A
  • Figure 7E is a schematic diagram of the second conductive layer of the sub-electrostatic release unit shown in Figure 7A
  • Figure 7F is a cross-sectional schematic diagram along the A1-A2 line in Figure 7A.
  • the size of the electrostatic release circuit EC in the second direction D2 is smaller than the size of the electrostatic release circuit EC in the first direction D1, and the second direction D2 is perpendicular to the first direction D1, so as to reduce the width of each sub-electrostatic release unit in the second direction D2 as much as possible, thereby greatly reducing the total width of multiple sub-electrostatic release units in the second direction D2.
  • the first electrostatic release transistor T01 and the second electrostatic release transistor T02 are arranged in the first direction D1
  • the first electrode T01s and the second electrode T01d of the first electrostatic release transistor T01 are arranged in the first direction D1
  • the first electrode T02s and the second electrode T02d of the second electrostatic release transistor T02 are arranged in the first direction D1, so as to reduce the total width of the whole formed by the first electrostatic release transistor T01 and the second electrostatic release transistor T02 in the second direction D2 by designing the arrangement of the first electrostatic release transistor T01 and the second electrostatic release transistor T02, and the source and drain of the first electrostatic release transistor T01 and the source and drain of the second electrostatic release transistor T02, thereby reducing the width of the electrostatic release circuit in the second direction D2 and reducing the width of the sub-electrostatic release unit in the second direction D2, so as to meet the requirement of arranging more sub-electrostatic release units in the limited space in the second direction D2.
  • the first electrostatic release transistor T01 includes a first active layer T01a
  • the second electrostatic release transistor T02 includes a second active layer T02a
  • the first active layer T01a and the second active layer T02a both extend along the first direction D1
  • the width of the first active layer T01a in the second direction D2 is smaller than the length of the first active layer T01a in the first direction D1
  • the width of the second active layer T02a in the second direction D2 is smaller than the length of the second active layer T02a in the first direction D1, so as to utilize the space in the first direction D1 to arrange the first electrostatic release transistor T01 and the second electrostatic release transistor T02, while further reducing the width of the first electrostatic release transistor T01 and the second electrostatic release transistor T02 in the second direction D2, and taking into account the size of the first active layer and the second active layer, and taking into account the performance of the first electrostatic release transistor T01 and the second electrostatic release transistor T02.
  • the width of the first active layer T01a in the second direction D2 is smaller than the length of the first active layer T01a in the first direction D1
  • the width of the second active layer T02a in the second direction D2 is smaller than the length of the second active layer T02a in the first direction D1, so as to further reduce the width of the first electrostatic release transistor T01 and the second electrostatic release transistor T02 in the second direction D2 while taking into account the sizes of the first active layer and the second active layer and the performance of the first electrostatic release transistor T01 and the second electrostatic release transistor T02.
  • the electrostatic release semiconductor layer is located in the semiconductor layer ACT, the first active layer T01a and the second active layer T02a constitute a continuous integrated electrostatic release semiconductor layer, and the electrostatic release semiconductor layer is in a strip shape extending along the first direction D1 as a whole.
  • the electrostatic release semiconductor layer is in a straight strip shape and is located on the side of the first strip portion S1 and the second strip portion S2 away from the data line DL, so as to further reduce the space occupied by the first gate portion GP1, the second gate portion GP2 and the electrostatic release semiconductor layer in the second direction D2, thereby further reducing the width of a sub-electrostatic release unit in the second direction D2, and effectively reducing the total width occupied by multiple sub-electrostatic release units in the second direction D2.
  • the gate T01g of the first electrostatic release transistor T01 and the gate T02g of the second electrostatic release transistor T02 are all located in the first conductive layer 110; for example, the gate T01g of the first electrostatic release transistor T01 and the gate T02g of the second electrostatic release transistor T02 are both arranged in the same layer as the gate of the driving transistor T1 of the pixel circuit, so that they can be formed by the same mask and the same composition process as the gate of the driving transistor T1 of the pixel circuit, thereby simplifying the manufacturing process and simplifying the layer structure of the display panel.
  • the first conductor C1 and the second conductor C2 are arranged at intervals in the first direction D1, and the first conductor C1 extends along the second direction D2;
  • the sub-electrostatic release unit SEU includes a first gate portion GP1;
  • the second conductor C2 includes a main body portion CM extending along the second direction D2 and a second gate portion GP2 connected to the main body portion CM and extending along the second direction D2, for example, the second gate portion GP2 and the main body portion CM of the second conductor C2 form an integrally formed structure;
  • the first gate portion GP1 and the second gate portion GP2 are arranged at intervals in the first direction D1, and the first gate portion GP1 and the second gate portion GP2 are located between the main body portions CM of the first conductor C1 and the second conductor C2;
  • the portion of the first gate portion GP1 overlapping with the first active layer T01a constitutes the gate T01g of the first electrostatic release transistor T01,
  • the first gate portion GP1 includes a first strip portion S1 extending along a first direction D1 and a gate connection structure CG electrically connected to the first strip portion S1, the gate connection structure CG protrudes from the first strip portion S1 toward the data line DL in the second direction D2, and the gate connection structure CG is electrically connected to the data line DL through a first via hole V1.
  • the first gate portion GP1 also includes a first protrusion electrically connected to the first strip portion S1, the first protrusion protrudes from the first strip portion S1 away from the data line DL in the second direction D2, and a portion of the first protrusion overlapping the first active layer T01a constitutes a gate T01g of the first electrostatic release transistor T01; for example, the first protrusion includes a first connection block G1 and a second connection block G2 arranged in the first direction D1 and spaced from each other.
  • the second gate portion GP2 includes a second strip portion S2 extending along the first direction D1 and a second protrusion electrically connected to the second strip portion S2, the second protrusion protruding from the second strip portion S2 in the second direction D2, and a portion of the second protrusion overlapping the second active layer T02a constitutes the gate T02g of the second electrostatic discharge transistor T02.
  • the second protrusion includes a third connection block G3 and a fourth connection block G4 arranged in the first direction D1 and spaced from each other.
  • the second protrusion protrudes from the second strip portion S2 in the direction away from the data line DL in the second direction D2, the first strip portion S1 is basically aligned with the second strip portion S2 in the first direction D1, and the first protrusion is basically aligned with the second protrusion in the first direction D1 to reduce the width of the second gate portion GP2 in the second direction D2, thereby reducing the width of a sub-electrostatic release unit in the second direction D2, which can effectively reduce the total width occupied by multiple sub-electrostatic release units in the second direction D2.
  • the sub-electrostatic discharge unit SEU further includes a data connection structure DL1, which is electrically connected to the data line DL and protrudes from the data line DL in the second direction D2 toward the electrostatic discharge semiconductor layer.
  • the first end of the data connection structure DL1 close to the data line DL in the second direction D2 is electrically connected to the gate connection structure CG through the first via hole V1, so that the gate connection structure CG is electrically connected to the data line DL through the first via hole V1, that is, the gate T01g of the first electrostatic discharge transistor T01 is electrically connected to the data line DL.
  • the second end of the data connection structure DL1 away from the data line DL in the second direction D2 is electrically connected to the electrostatic release semiconductor layer through the second via hole V2, so that the first electrode T01s of the first electrostatic discharge transistor T01 is also electrically connected to the data line DL, and the first electrode T02s of the second electrostatic discharge transistor T02 is electrically connected to the data line DL.
  • the second via hole V2 is located between the first protrusion and the second protrusion in the first direction D1.
  • the data connection structure DL1 is electrically connected to the recessed portion of the first signal line 01 adjacent to the data connection structure DL1 .
  • the portion of the first signal line 01 in FIG. 7B electrically connected to the electrostatic discharge semiconductor layer is a part of the recessed portion.
  • the sub-electrostatic discharge unit SEU further includes a first connection structure 201 and a second connection structure 202; the first connection structure 201 and the second connection structure 202 are located in the second conductive layer 120.
  • the first end of the first connection structure 201 in the first direction D1 is connected to the first conductor C1 through the third via V3, and the second end of the first connection structure 201 in the first direction D1 is connected to the first active layer T01a through the fourth via V4, so that the second electrode T01d of the first electrostatic discharge transistor T01 is electrically connected to the first conductor C1.
  • the first end of the second connection structure 202 in the first direction D1 is connected to the main body CM of the second conductor C2 through the fifth via V5, and the second end of the second connection structure 202 in the first direction D1 is connected to the second active layer T02a through the sixth via V6, so that the gate T02g and the second electrode of the second electrostatic release transistor T02 are both connected to the second conductor C2.
  • the display panel 10 further includes a first insulating layer GI1 between the semiconductor layer ACT and the first conductive layer 110, a second insulating layer GI2 and an interlayer insulating layer ILD between the first conductive layer 110 and the second conductive layer 120; a first via hole V1 penetrates the second insulating layer GI2 and the interlayer insulating layer ILD, a second via hole V2 penetrates the first insulating layer GI1, the second insulating layer GI2 and the interlayer insulating layer ILD, a third via hole V3 penetrates the second insulating layer GI2 and the interlayer insulating layer ILD, a fourth via hole V4 penetrates the first insulating layer GI1, the second insulating layer GI2 and the interlayer insulating layer ILD, a fifth via hole V5 penetrates the second insulating layer GI2 and the interlayer insulating layer ILD, and a sixth via hole V6 penetrates the first insulating layer
  • the display substrate 10 further includes a buffer layer Buffer located on the base substrate 200 , and the semiconductor layer ACT is located on the buffer layer Buffer.
  • the buffer layer Buffer can prevent contamination and damage to the base substrate 200 during the manufacturing process, making other structures formed thereon purer and smoother.
  • the base substrate 200 can be a rigid substrate, such as a glass substrate, a silicon substrate, etc., or can be formed of a flexible material with excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), triacetyl cellulose (TAC), cycloolefin polymer (COP) and cycloolefin copolymer (COC), etc.
  • PI polyimide
  • PC polycarbonate
  • PET polyethylene terephthalate
  • PET polyethylene
  • polyacrylate polyarylate
  • polyetherimide polyethersulfone
  • PET polyethylene terephthalate
  • PET polyethylene
  • PE polypropylene
  • PSF polysulfone
  • the material of the semiconductor layer ACT includes but is not limited to silicon-based materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.) and organic materials (sixithiophene, polythiophene, etc.).
  • the materials of the first conductive layer and the second conductive layer may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W) and alloy materials formed by combinations of the above metals; or transparent conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), etc.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • ZnO zinc oxide
  • AZO aluminum zinc oxide
  • the first insulating layer GI1, the second insulating layer GI2, and the interlayer insulating layer ILD are inorganic insulating layers, and their materials include at least one of silicon oxides, silicon nitrides, or silicon oxynitrides, such as silicon oxide, silicon nitride, or silicon oxynitride, or include metal oxynitride insulating materials such as aluminum oxide and titanium nitride.
  • the embodiments of the present disclosure are not limited to this.
  • FIG8 is a schematic diagram of several special-shaped display panels including electrostatic discharge units provided by an embodiment of the present disclosure.
  • the plane shape of the display panel provided by the embodiment of the present disclosure is the letter Y-shaped, with a Y-shaped display area 1, and the electrostatic discharge area 20 is located at the bottom edge of the bottom Y-shaped display panel.
  • the maximum width L1 of the Y-shaped display panel in the second direction D2 is greater than the width L2 of the non-display area of the bottom of the Y-shaped display panel where the electrostatic discharge area 20 can be set in the second direction D2.
  • L1 156912 ⁇ m
  • L2 71640 ⁇ m
  • L2/L1 0.46.
  • the ratio of L2 to L1 is less than 0.5, which means that the size of the bottom space where the electrostatic discharge area can be set in the second direction is much smaller than the size of the space spanned by the display area in the second direction. Therefore, for example, for a variety of special-shaped display panels, especially for display panels where the ratio of L2 to L1 is less than 0.5, since the width of the space where the electrostatic discharge area can be set in the second direction D2 is small to a certain extent, it is necessary to greatly reduce the total width of multiple electrostatic discharge units ESD in the second direction D2.
  • Figure 9A is a schematic diagram of a Y-shaped display panel provided in an embodiment of the present disclosure
  • Figure 9B is a local planar schematic diagram of the Y-shaped display panel including an electrostatic release area and a lead area
  • Figure 9C is a schematic diagram of a local semiconductor layer shown in Figure 9B
  • Figure 9D is a schematic diagram of a local first conductive layer shown in Figure 9B
  • Figure 9E is a schematic diagram of a local interlayer insulating layer shown in Figure 9B
  • Figure 9F is a schematic diagram of a local second conductive layer shown in Figure 9B.
  • the embodiment shown in FIG9B adopts the arrangement of the electrostatic discharge units shown in FIG4A .
  • the arrangement of the adjacent first electrostatic discharge unit group EUG1 and the second electrostatic discharge unit group EUG2 is shown.
  • M is equal to 1
  • N is equal to 2
  • Q is equal to 3.
  • the width L IC of the region where the driving circuit IC is located (i.e., the space occupied by the driving circuit IC) in the second direction D2 is smaller than the width L ESD of the electrostatic discharge region 20 in the second direction D2.
  • the first end of the data selection unit MUXU close to the electrostatic discharge region 20 is electrically connected to R data lines DL, and the second end of the data selection unit MUXU away from the electrostatic discharge region 20 is electrically connected to S data leads, where S and R are both positive integers and S is smaller than R; the S data leads are electrically connected to the driving circuit, and the first display signal, i.e., the data signal Vd, is provided to the S data leads through the driving circuit.
  • the number of data leads can be reduced, thereby reducing the total width required for the plurality of data leads in the second direction D2, so as to adapt to the situation where the width L IC of the region where the driving circuit IC is located in the second direction D2 is smaller than the width L ESD of the electrostatic discharge region 20 in the second direction D2.
  • the first data line 01a is electrically connected to the first sub-electrostatic discharge unit S1a in the first electrostatic discharge unit EU1
  • the second data line 01b is electrically connected to the first sub-electrostatic discharge unit S1b in the second electrostatic discharge unit EU2.
  • the three sub-electrostatic discharge units S1a/S2a/S3a of the first electrostatic discharge unit EU1 respectively provide data signals Vd to the three sub-pixels located in the same pixel in the display area 1, for example, provide data signals Vd to the three sub-pixels of red, green and blue, respectively. That is, the first end of the data selection unit MUXU close to the electrostatic discharge area 20 is electrically connected to two data lines DL respectively, and the two data lines DL are electrically connected to two sub-pixels of the same color of adjacent pixels to provide data signals Vd to the two sub-pixels of the same color; the second end of the data selection unit MUXU away from the electrostatic discharge area 20 is electrically connected to a data lead 01c.
  • R is not limited to being equal to 2
  • S is not limited to being equal to 1.
  • R is equal to 2
  • S is equal to 1.
  • the second data line 01b can be switched across layers, which includes a first part 01b1, a second part 01b2 and a third part 01b3.
  • the first part 01b1 and the second part 01b2 are located in the second conductive layer 120
  • the third part 01b3 is located in the first conductive layer 110
  • the first end of the third part 01b3 is electrically connected to the first part 01b1 through a via
  • the second end of the third part 01b3 is electrically connected to the second part 01b2 through a via. Because, in this special-shaped screen, the space available for setting the electrostatic release unit and the driving circuit IC is very small, so that multiple data lines DL connected to multiple data selection units MUXU can be arranged in a limited space.
  • FIG10 is a schematic diagram of a data selection circuit of a display panel provided by an embodiment of the present disclosure
  • FIG11 is a working timing diagram of the data selection circuit shown in FIG10
  • FIG12A is a structural plan view of a data selection unit of a display panel provided by an embodiment of the present disclosure.
  • the data selection unit MUXU includes a data selection circuit, which includes a first data selection transistor T001 and a second data selection transistor T002.
  • the gate of the first data selection transistor T001 is electrically connected to the first data terminal to receive the first data driving signal MUXG1 from the first data terminal; the gate of the second data selection transistor T002 is electrically connected to the second data terminal to receive the second data driving signal MUXG2 from the second data terminal.
  • the first electrode of the first data selection transistor T001 is electrically connected to the first data line 01a to output the first output signal Output1 to the first data line 01a
  • the first electrode of the second data selection transistor T002 is electrically connected to the second data line 01b to output the second output signal Output2 to the second data line 01b.
  • the second electrode of the first data selection transistor T001 is electrically connected to the second electrode of the second data selection transistor T002, and both are electrically connected to the data lead 01c to receive the input data signal Input from the data lead 01c.
  • the working process of the data selection circuit is described by taking the second electrode of the first data selection transistor T001 and the second data selection transistor T002 as N-type transistors as an example.
  • the first data driving signal MUXG1 is at a high level and the second data driving signal MUXG2 is at a low level, so that the first data selection transistor T001 is turned on and the second data selection transistor T002 is turned off; at this time, the input data signal Input is the first data signal, and the first data signal is transmitted to the first data line 01a as the first output signal Output1 through the first data selection transistor T001, and then provided to the corresponding sub-pixel through the first data line 01a.
  • the first data driving signal MUXG1 is at a low level
  • the second data driving signal MUXG2 is at a high level, so that the first data selection transistor T001 is turned off and the second data selection transistor T002 is turned on; at this time, the input data signal Input is a second data signal different from the first data signal, and the second data signal is transmitted to the second data line 01b through the second data selection transistor T002 as the second output signal Output2, and then provided to the corresponding sub-pixel through the second data line 01b.
  • FIG12B shows an active layer T001a of a first data selection transistor T001 and an active layer T002a of a second data selection transistor T002.
  • the active layer T001a and the active layer T002a respectively include a plurality of islands arranged in a first direction D1.
  • FIG12C shows a gate T001g of the first data selection transistor T001 and a gate T002g of the second data selection transistor T002.
  • the first data line 01a is electrically connected to the active layer T001a of the first data selection transistor T001 through a first group of vias V01
  • the second data line 01b is electrically connected to the active layer T002a of the second data selection transistor T002 through a second group of vias V02
  • the data lead 01c is electrically connected to the active layer T001a and the active layer T002a through a third group of vias V03, for example, for each island, the active layer T001a and the active layer T002a are integrally formed.
  • the structure of multiple islands arranged in the first direction D1 is beneficial to increasing the width-to-length ratio of the gate T001g of the first data selection transistor T001 and the second data selection transistor T002, improving the performance of the transistor, and can reduce the width of multiple data selection units in the second direction D2 to meet the requirement that the size of the area where they are located in the second direction D2 is very limited.
  • the display panel 10 further includes: a reset voltage line RL and a reset voltage lead RL0.
  • the reset voltage line RL and the reset voltage lead RL0 are both located in the second conductive layer 120, in the same layer as the data line DL.
  • the reset voltage line RL is configured to provide a reset voltage signal to the sub-pixel 100, and includes a lead portion RL1/RL2 located in the non-display area; the first lead portion RL1 is located between two adjacent electrostatic discharge units EU1 and EU2 and extends along the first direction D1, and the adjacent J lead portions are electrically connected via a reset connection line RLC extending along the second direction D2; for example, in the embodiment shown in FIG.
  • the adjacent first lead portion RL1 and the second lead portion RL2 are electrically connected via a reset connection line RLC extending along the second direction D2.
  • the first end of the reset voltage lead RL0 is electrically connected to the reset connection line RLC
  • the second end of the reset voltage lead RL0 is electrically connected to the drive circuit IC
  • the drive circuit IC is configured to provide a reset voltage signal.
  • the reset voltage signal is the first reset voltage Vinit1 and the first reset voltage Vinit2 provided to the pixel circuit.
  • the first reset voltage Vinit1 and the first reset voltage Vinit2 may be the same, and are both provided by the driving circuit IC via the reset voltage line RL.
  • the planar shape of the display panel provided by the embodiment of the present disclosure is heart-shaped, having a heart-shaped display area 1, and the electrostatic discharge area 20 is located at the bottom edge of the heart-shaped display panel.
  • the maximum width L1 of the heart-shaped display panel in the second direction D2 is greater than the width L2 of the non-display area at the bottom of the heart-shaped display panel where the electrostatic discharge area 20 can be set in the second direction D2.
  • L1 231061 ⁇ m
  • L2 84651 ⁇ m
  • L2/L1 0.37.
  • the size of the bottom space in which the electrostatic discharge area can be set in the second direction is much smaller than the size of the space spanned by the display area in the second direction, and even the value of L2/L1 is smaller than the value of L2/L1 in the Y-shaped display panel. Therefore, for example, for this special-shaped display panel, since the width of the space in which the electrostatic discharge area can be set in the second direction D2 is small to a certain extent, it is necessary to greatly reduce the total width of multiple electrostatic discharge units ESD in the second direction D2.
  • FIG13A is a schematic diagram of a heart-shaped display panel provided in an embodiment of the present disclosure
  • FIG13B is a partial plan schematic diagram of the heart-shaped display panel including an electrostatic release area and a lead area.
  • the width L IC of the region where the driving circuit IC is located (i.e., the space occupied by the driving circuit IC) in the second direction D2 is smaller than the width L ESD of the electrostatic discharge region 20 in the second direction D2.
  • L ESD 70560 ⁇ m
  • L IC 47864 ⁇ m. Therefore, the design of the data selection circuit and the reset voltage lead can also refer to the design of the embodiment shown in FIG. 9B .
  • the embodiment shown in Fig. 13B adopts the arrangement of the electrostatic discharge units shown in Fig. 4D, showing an electrostatic discharge unit group EUG formed by the adjacent first electrostatic discharge unit sub-group SEUG1 and the second electrostatic discharge unit sub-group SEUG2.
  • the border width L borders on both sides + resolution * ⁇ .
  • the resolution of the heart-shaped display panel is 1440*1440.
  • M the number of staggered ESD units in the longitudinal direction
  • N the number of staggered ESD units in the longitudinal direction
  • Q the number of sub-electrostatic discharge units constitute an electrostatic discharge group EUG
  • the total width of an electrostatic discharge group EUG in the second direction is 129.5 ⁇ m.
  • this design can further reduce the total width of all electrostatic release units in the second direction, and under the requirement of higher PPI, it can also meet the requirement of smaller L2/L1 value in the heart-shaped display panel for a smaller total width of all electrostatic release units in the second direction.
  • each sub-electrostatic discharge unit and the data selection circuit for example, the structure of each sub-electrostatic discharge unit and the data selection circuit, reference may be made to the description of the embodiment shown in FIG. 9B .
  • the plane shape of the display panel provided by the embodiment of the present disclosure is a letter D shape, and the electrostatic discharge area 20 is located at the bottom edge of the D-shaped display panel.
  • the maximum width L1 of the D-shaped display panel in the second direction D2 is greater than the width L2 of the non-display area at the bottom of the D-shaped display panel where the electrostatic discharge area 20 can be set in the second direction D2.
  • L1 156912 ⁇ m
  • L2 97900 ⁇ m
  • L2/L1 0.62.
  • FIG14A is a schematic diagram of a D-shaped display panel provided in an embodiment of the present disclosure
  • FIG14B is a partial plan schematic diagram of the D-shaped display panel including an electrostatic release area and a lead area.
  • the embodiment shown in FIG14B adopts the arrangement of the electrostatic release unit shown in FIG4A.
  • An electrostatic release unit group EUG composed of the adjacent first sub-electrostatic release unit group SEUG1 and the second sub-electrostatic release unit group SEUG2 is shown.
  • the resolution of the D-shaped display panel is 960*1920, according to the arrangement of the two groups of staggered ESD units in the longitudinal direction, that is, M is equal to 1, N is equal to 2, Q is equal to 3, 6 electrostatic release units constitute an electrostatic release group EUG, and the total width of an electrostatic release group EUG in the second direction is 129.5 ⁇ m.
  • the embodiment shown in FIG14B is similar to the Y-shaped display panel. This design can also reduce the total width of all electrostatic discharge units in the second direction, satisfying the requirement of the smaller L2/L1 value in the heart-shaped display panel for a smaller total width of all electrostatic discharge units in the second direction.
  • FIG4C or FIG4D can also be used to further reduce the total width of all electrostatic discharge units in the second direction.
  • Other structures shown in FIG14B, such as the structure of each sub-electrostatic discharge unit, the data selection circuit, etc., can refer to the description of the embodiment shown in FIG9B.
  • the plane shape of the display panel provided by the embodiment of the present disclosure is the letter O-shaped, and the electrostatic discharge area 20 is located at the bottom edge of the O-shaped display panel.
  • the maximum width L1 of the O-shaped display panel in the second direction D2 is greater than the width L2 of the non-display area at the bottom of the O-shaped display panel where the electrostatic discharge area 20 can be set in the second direction D2.
  • L1 307835 ⁇ m
  • L2 164400 ⁇ m
  • L2/L1 0.53.
  • FIG15A is a schematic diagram of an O-shaped display panel provided in an embodiment of the present disclosure
  • FIG15B is a partial plan schematic diagram of the O-shaped display panel including an electrostatic release area and a lead area.
  • the resolution of the O-shaped display panel is 1920*3840, which is relatively high. Therefore, the O-shaped display panel has two COFs, and the total width of all electrostatic discharge units in the second direction D2 is twice that of one COF, and it is even more necessary to minimize the total width of each electrostatic discharge unit group and all electrostatic discharge units in the second direction D2.
  • the embodiment shown in FIG15B adopts the arrangement of the electrostatic discharge units shown in FIG4C.
  • An electrostatic discharge unit group EUG composed of the adjacent first sub-electrostatic discharge unit group SEUG1 and the second sub-electrostatic discharge unit group SEUG2 is shown.
  • this design can also reduce the total width of all electrostatic discharge units in the second direction, meeting the smaller L2/L1 value in the heart-shaped display panel for the smaller total width of all electrostatic discharge units in the second direction.
  • the arrangement of the electrostatic discharge units shown in FIG4D can also be used to further reduce the total width of all electrostatic discharge units in the second direction.
  • FIG. 15B for example, the structure of each sub-electrostatic discharge unit and the data selection circuit, reference may be made to the description of the embodiment shown in FIG. 9B .
  • the planar shape of the display panel provided by the embodiment of the present disclosure is letter I-shaped, and the electrostatic discharge area 20 is located at the bottom edge of the I-shaped display panel.
  • FIG16A is a schematic diagram of an I-shaped display panel provided in an embodiment of the present disclosure
  • FIG16B is a partial plan schematic diagram of the I-shaped display panel including an electrostatic release area and a lead area.
  • the embodiment shown in FIG16B adopts the arrangement of the electrostatic release unit shown in FIG4A.
  • An electrostatic release unit group EUG composed of adjacent first sub-electrostatic release unit group SEUG1 and second sub-electrostatic release unit group SEUG2 is shown.
  • L1 156912 ⁇ m
  • L2 156912 ⁇ m.
  • the width of the area of the bottom frame used to set the electrostatic release unit in the I-shaped panel in the second direction D2 is relatively sufficient relative to the width of the display area in the second direction D2. Therefore, for example, referring to FIG16B, the orthographic projections of the adjacent first electrostatic release unit EU1 and the second electrostatic release unit EU2 on the surface parallel to the second direction D2 do not overlap each other, and the orthographic projections on the surface parallel to the first direction D1 overlap each other, for example, substantially completely overlap, so as to keep the arrangement regular and reduce the difficulty of manufacturing.
  • the resolution of the I-shaped display panel is 960*1920.
  • the total width of the first and last three sub-electrostatic release units in the second direction is 260 ⁇ m.
  • the middle sub-electrostatic release unit six sub-electrostatic release units form an electrostatic release unit group, and the total width of an electrostatic release unit group in the second direction is 280 ⁇ m.
  • the width of the bottom space of the I-shaped display panel in the second direction is 156912 ⁇ m, which provides sufficient space for designing electrostatic release units.
  • the orthographic projections of two adjacent electrostatic release units on a surface parallel to the second direction D2 may at least partially overlap with each other, for example, by adopting the arrangement of the electrostatic release units shown in FIG. 4C or 4D to reduce the total width of all electrostatic release units in the second direction to adapt to a smaller I-shaped panel.
  • the width L IC of the region where the driving circuit IC is located (i.e., the space occupied by the driving circuit IC) in the second direction D2 is smaller than the width L ESD of the electrostatic discharge region 20 in the second direction D2.
  • L ESD 134383 ⁇ m
  • L IC 47864 ⁇ m. Therefore, the design of the data selection circuit and the reset voltage lead can also refer to the design of the embodiment shown in FIG. 9B .
  • each sub-electrostatic discharge unit and the data selection circuit for example, the structure of each sub-electrostatic discharge unit and the data selection circuit, reference may be made to the description of the embodiment shown in FIG. 9B .
  • At least one embodiment of the present disclosure provides a display device, including any display substrate provided in the embodiments of the present disclosure.
  • the display device may be, for example, an organic light emitting diode display device, a quantum dot light emitting diode display device, or other types of devices having a display function.
  • the embodiments of the present disclosure are not limited thereto.
  • the structure, function, technical effect, etc. of the display device provided by the embodiment of the present disclosure can refer to the corresponding description of the display substrate 10 provided by the above embodiment of the present disclosure, and will not be repeated here.
  • the display device provided in at least one embodiment of the present disclosure may be a display panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function, and the embodiments of the present disclosure are not limited thereto.

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Abstract

显示面板以及显示装置，该显示面板包括显示区、非显示区、第一信号线和多个静电释放单元。显示区包括子像素；非显示区围绕显示区且包括静电释放区域；第一信号线沿第一方向从显示区延伸至静电释放区域，且被配置为给子像素提供第一显示信号；多个静电释放单元在第一方向上排列，每个静电释放单元包括至少一个子静电释放单元，每个子静电释放单元包括静电释放电路和第一导体，静电释放电路与第一信号线和第一导体电连接，第一信号线上的电荷朝向第一导体移动；多个静电释放单元包括在第二方向上相邻的两个相邻的静电释放单元，第二方向与第一方向垂直，两个相邻的静电释放单元在第一方向上彼此不重叠且在第二方向上彼此至少部分重叠。

Description

显示面板以及显示装置 技术领域
本公开至少一实施例涉及一种显示面板以及显示装置。
背景技术
随着社会的发展，人们对生活的要求越来越高，传统的显示屏已经逐渐满足不了对定制化显示的要求，异形显示具有可定制化的特点，具有一定的优势。然而，异形的显示屏打破了传统显示屏的形状的设计规律，这意味着要更多的创新设计来适应其异形显示。
在显示面板中，静电释放单元对于显示电路至关重要，静电发生时，可以通过设置静电释放单元对显示电路的静电进行释放，以很好的保护显示电路。传统的显示屏，例如矩形显示屏，有足够的底部空间来排布的静电释放单元，但是，在一些边框尺寸较小的屏幕例如异形屏中，异形屏的边框形状不规则，可供设置静电释放单元的空间非常小，这对改变传统的静电释放单元排布方式提出了挑战。
发明内容
本公开至少一实施例提供一种显示面板，该显示面板包括：显示区、非显示区、第一信号线和多个静电释放单元。显示区包括子像素；非显示区至少部分围绕所述显示区，且包括静电释放区域；第一信号线整体上沿第一方向从所述显示区延伸至所述静电释放区域，且被配置为给所述子像素提供第一显示信号；多个静电释放单元在所述第一方向上排列，每个所述静电释放单元包括至少一个子静电释放单元，所述至少一个子静电释放单元中的每个包括静电释放电路和第一导体，所述静电释放电路与所述第一信号线和所述第一导体电连接，且被配置为使所述第一信号线上的电荷朝向所述第一导体移动；所述多个静电释放单元包括在第二方向上相邻的两个相邻的静电释放单元，所述第二方向与所述第一方向垂直，所述两个相邻的静电释放单元在 平行于所述第一方向的面上的正投影彼此不重叠且在平行于第二方向的面上的正投影彼此至少部分重叠，或者，所述两个相邻的静电释放单元在平行于所述第一方向的面上的正投影彼此不重叠且在所述第二方向上彼此之间的距离小于1微米。
例如，本公开至少一实施例提供一种显示面板中，在所述多个静电释放单元的多个子静电释放单元中，至少两个所述子静电释放单元在平行于所述第一方向的面上的正投影彼此不重叠且在平行于第二方向的面上的正投影彼此至少部分重叠。
例如，本公开至少一实施例提供一种显示面板中，所述静电释放电路在所述第二方向上的尺寸小于所述静电释放电路在所述第一方向上的尺寸。
例如，本公开至少一实施例提供一种显示面板中，所述显示面板包括多条所述第一信号线，所述多个静电释放单元的多个所述子静电释放单元分别与多条所述第一信号线中的一条第一信号线电连接；所述多条第一信号线中的至少一条包括位于所述静电释放区域的凹陷部，所述凹陷部构成在所述第二方向上的朝向一侧凹陷的凹槽，与所述凹槽相邻的所述子静电释放单元至少部分位于所述凹槽内。
例如，本公开至少一实施例提供一种显示面板中，所述多个静电释放单元中的至少一个静电释放单元包括在所述第二方向上相邻的两个所述子静电释放单元，相邻的两条所述第一信号线均包括位于所述静电释放区域的凹陷部，所述相邻的两条第一信号线的凹陷部构成在所述第二方向上朝向同一侧凹陷的凹槽，相邻的两个所述子静电释放单元分别至少部分位于所述相邻的两条第一信号线的凹陷部所构成的凹槽内。
例如，本公开至少一实施例提供一种显示面板中，与所述至少一个所述子静电释放单元连接的所述第一信号线包括：第一凹陷部、和第二凹陷部。第一凹陷部构成在所述第二方向上朝向第一侧凹陷的第一凹槽；第二凹陷部构成在所述第二方向上朝向与所述第一侧相对的第二侧凹陷的第二凹槽，且与所述第一凹陷部在所述第二方向上排列；所述两个相邻的静电释放单元分别为第一静电释放单元和第二静电释放单元，所述第一静电释放单元在平行于所述第一方向上的正投影位于所述第一凹槽在平行于所述第一方向上的正 投影内，所述第二静电释放单元在平行于所述第一方向上的正投影位于所述第二凹槽在平行于所述第一方向上的正投影内。
例如，本公开至少一实施例提供一种显示面板中，多个所述静电释放单元构成在第二方向上间隔排列的多个静电释放单元组，每个所述静电释放单元组包括M个子静电释放单元组，每个所述子静电释放单元组包括N个所述静电释放单元，每个所述静电释放单元包括Q个所述子静电释放单元，M和Q是大于等于1的正整数，N是大于等于2的正整数；所述多个静电释放单元组中的至少部分静电释放单元组在所述第二方向上呈周期排列，一个所述静电释放单元组为所述周期中的一个重复单元。
例如，本公开至少一实施例提供一种显示面板中，一个所述静电释放单元组包括的所述子静电释放单元的个数为M*N*Q；在M等于1，N等于2，Q等于3时，一个所述静电释放单元组在所述第二方向上的宽度小于等于129.5μm；或者，在M等于2，N等于3，Q等于3时，一个所述静电释放单元组在所述第二方向上的宽度小于等于294μm。
例如，本公开至少一实施例提供一种显示面板中，所述显示面板的分辨率为X*Y，X代表所述显示区中的像素阵列的行数，Y代表所述显示区中的像素阵列的列数，X大于等于960，Y大于等于1440。
例如，本公开至少一实施例提供一种显示面板中，所述M个子静电释放单元组包括第一子静电释放单元组和第二子静电释放单元组，第一子静电释放单元组和第二子静电释放单元组相对于沿所述第一方向延伸的对称轴对称或非对称。
例如，本公开至少一实施例提供一种显示面板中，所述第一显示信号为数据信号，所述第一信号线传输所述数据信号；所述子像素包括像素电路，所述像素电路包括：发光器件、驱动晶体管和数据写入晶体管；所述数据写入晶体管配置为在第一扫描信号的控制下将所述数据信号传输至所述驱动晶体管；所述驱动晶体管配置为根据所述数据信号控制流经所述发光器件的驱动电流的大小，所述发光器件配置为接收所述驱动电流且被所述驱动电流驱动以发光。
例如，本公开至少一实施例提供一种显示面板中，所述非显示区包括引 线区域，所述引线区域设置有驱动电路，所述驱动电路配置为给所述第一信号线提供所述第一显示信号；所述静电释放区域位于所述引线区域和所述显示区之间，且给全部所述子像素提供所述第一显示信号的所述第一信号线所连接的所述多个子静电释放单元均位于所述显示区在所述第一方向上的同一侧的所述非显示区中。
例如，本公开至少一实施例提供一种显示面板中，所述非显示区还包括边框区，所述边框区位于所述引线区域与所述显示区之间，所述边框区中设置有第一电源引线，所述第一电源引线配置为给所述子像素提供第一电源电压；所述引线区域包括位于所述边框区的远离所述显示区一侧的数据选择区域，所述数据选择区域中设置有数据选择单元，所述静电释放区域位于所述第一电源引线和所述数据选择区域之间。
例如，本公开至少一实施例提供一种显示面板中，所述数据选择单元的靠近静电释放区域的第一端与R条所述第一信号线电连接，所述数据选择单元的远离静电释放区域的第二端与S条数据引线电连接，S和R均为正整数且S小于R；所述S条数据引线电连接至驱动电路，通过所述驱动电路给所述S条数据引线提供所述第一显示信号。
例如，本公开至少一实施例提供一种显示面板中，所述驱动电路所在的区域在所述第二方向上的宽度小于所述静电释放区域在所述第二方向上的宽度。
例如，本公开至少一实施例提供一种显示面板中，所述静电释放电路包括第一子电路，第一子电路具有驱动端、第一端和第二端，其中，所述第一子电路的驱动端和第一端均与所述第一信号线电连接，所述第一子电路的第二端与所述第一导体电连接。
例如，本公开至少一实施例提供一种显示面板中，所述子静电释放单元还包括第二导体，所述静电释放电路与所述第一信号线和所述第二导体电连接，且被配置为使所述第一信号线上的电荷朝向所述第二导体移动；所述静电释放电路还包括第二子电路，第二子电路具有驱动端、第一端和第二端，其中，所述第二子电路的第一端与所述第一信号线电连接，所述第二子电路的驱动端和第二端均与所述第二导体连接；所述第一子电路和所述第二子电 路在所述第一方向上排列。
例如，本公开至少一实施例提供一种显示面板中，所述第一子电路包括第一晶体管，所述第二子电路包括第二晶体管；所述第一晶体管的栅极和第一极均与所述第一信号线电连接，所述第一晶体管的第二极与所述第一导体电连接；所述第二晶体管的第一极与所述第一信号线电连接，所述第二晶体管的栅极和第二极均与所述第二导体连接；所述第一晶体管和所述第二晶体管在所述第一方向上排列，所述第一晶体管的第一极和第二极在所述第一方向上排列，所述第二晶体管的第一极和第二极在所述第一方向上排列；所述第一晶体管包括第一有源层，所述第二晶体管包括第二有源层；所述第一有源层和所述第二有源层均沿所述第一方向延伸，所述第一有源层在所述第二方向上的宽度小于所述第一有源层在所述第一方向上的长度，所述第二有源层在所述第二方向上的宽度小于所述第二有源层在所述第一方向上的长度。
例如，本公开至少一实施例提供一种显示面板中，所述第一导体与所述第二导体在所述第一方向上间隔排列，且所述第一导体沿所述第二方向延伸；所述子静电释放单元包括第一栅极部；所述第二导体包括沿所述第二方向延伸的主体部和与所述主体部连接且沿所述第二方向延伸的第二栅极部，所述第一栅极部与所述第二栅极部在所述第一方向上间隔排列，且所述第一栅极部和所述第二栅极部位于所述第一导体与所述第二导体的主体部之间；所述第一栅极部的与所述第一有源层交叠的部分构成所述第一晶体管的栅极，所述第二栅极部的与所述第二有源层交叠的部分构成所述第二晶体管的栅极，且所述第一栅极部与所述第一信号线电连接。
例如，本公开至少一实施例提供一种显示面板中，所述第一栅极部包括沿所述第一方向延伸的第一条形部和与所述第一条形部电连接的栅连接结构，所述栅连接结构自所述第一条形部在所述第二方向上朝向所述第一信号线突出于所述第一条形部，所述栅连接结构与所述第一信号线通过第一过孔电连接；所述第一栅极部还包括与所述第一条形部电连接的第一突出部，所述第一突出部自所述第一条形部在所述第二方向上远离所述第一信号线突出于所述第一条形部，所述第一突出部的与所述第一有源层交叠的部分构成所述第一晶体管的栅极；所述第二栅极部包括沿所述第一方向延伸的第二条形 部和与所述第二条形部电连接的第二突出部，所述第二突出部自所述第二条形部在所述第二方向上突出于所述第二条形部，所述第二突出部的与所述第二有源层交叠的部分构成所述第二晶体管的栅极。
例如，本公开至少一实施例提供一种显示面板中，所述第二突出部自所述第二条形部在所述第二方向上沿远离所述第一信号线的方向突出于所述第二条形部，所述第一条形部与所述第二条形部在所述第一方向上基本对齐，所述第一突出部与所述第二突出部在所述第一方向上基本对齐。
例如，本公开至少一实施例提供一种显示面板中，所述第一有源层与所述第二有源层构成连续的一体成型的静电释放半导体层，所述静电释放半导体层整体上呈沿所述第一方向延伸的条形；所述子静电释放单元还包括数据连接结构，所述数据连接结构与所述第一信号线电连接且自所述第一信号线在所述第二方向朝向所述静电释放半导体层突出于所述第一信号线，所述数据连接结构在所述第二方向上靠近所述第一信号线的第一端通过所述第一过孔与所述栅连接结构电连接，所述数据连接结构在所述第二方向上远离所述第一信号线的第二端通过第二过孔与所述静电释放半导体层电连接，所述第二过孔在所述第一方向上位于所述第一突出部与所述第二突出部之间。
例如，本公开至少一实施例提供一种显示面板中，所述子静电释放单元还包括第一连接结构和第二连接结构；所述第一连接结构在所述第一方向上的第一端通过第三过孔与所述第一导体连接，所述第一连接结构在所述第一方向上的第二端通过第四过孔与所述第一有源层连接；所述第二连接结构在所述第一方向上的第一端通过第五过孔与所述第二导体的主体部连接，所述第二连接结构在所述第一方向上的第二端通过第六过孔与所述第二有源层连接。
例如，本公开至少一实施例提供一种显示面板中，所述静电释放半导体层静电释放半导体层呈直的条形，且位于所述第一条形部和所述第二条形部的远离所述第一信号线的一侧。
例如，本公开至少一实施例提供一种显示面板还包括：复位电压线和复位电压引线。复位电压线配置为给所述子像素提供复位电压信号，且包括位于所述非显示区的引线部，所述复位电压引线的引线部位于相邻的两个所述 静电释放单元之间且沿所述第一方向延伸，相邻的J条所述引线部经由沿所述第二方向延伸的复位连接线电连接；所述复位电压引线的第一端与所述复位连接线电连接，所述复位电压引线的第二端与驱动电路电连接，所述驱动电路配置为提供所述复位电压信号。
例如，本公开至少一实施例提供一种显示面板中，所述驱动电路所在的区域在所述第二方向上的宽度小于所述静电释放区域在所述第二方向上的宽度。
本公开至少一实施例提供一种显示面板，该显示面板包括：显示区、非显示区、第一信号线和多个静电释放单元。显示区包括子像素；非显示区至少部分围绕所述显示区，且包括静电释放区域；第一信号线，整体上沿第一方向从所述显示区延伸至所述静电释放区域，且被配置为给所述子像素提供第一显示信号；多个静电释放单元在所述第一方向上排列，每个所述静电释放单元包括至少一个子静电释放单元，所述至少一个子静电释放单元中的每个包括静电释放电路和第一导体，所述静电释放电路与所述第一信号线和所述第一导体电连接，且被配置为使所述第一信号线上的电荷朝向所述第一导体移动；在所述多个静电释放单元中，每两个相邻的所述静电释放单元在平行于所述第一方向的面上的正投影均彼此不重叠。
本公开至少一实施例提供一种显示面板，该显示面板包括：显示区、非显示区、第一信号线和多个静电释放单元。显示区包括子像素；非显示区至少部分围绕所述显示区，且包括静电释放区域；第一信号线，整体上沿第一方向从所述显示区延伸至所述静电释放区域，且被配置为给所述子像素提供第一显示信号；多个静电释放单元在所述第一方向上排列，每个所述静电释放单元包括至少一个子静电释放单元，所述至少一个子静电释放单元中的每个包括静电释放电路和第一导体，所述静电释放电路与所述第一信号线和所述第一导体电连接，且被配置为使所述第一信号线上的电荷朝向所述第一导体移动；所述非显示区包括引线区域，所述引线区域设置有驱动电路，所述驱动电路配置为给所述第一信号线提供所述第一显示信号；所述静电释放区域位于所述引线区域和所述显示区之间，且给全部所述子像素提供所述第一显示信号的所述第一信号线所连接的所述多个子静电释放单元均位于所述显 示区在所述第一方向上的同一侧。
本公开至少一实施例提供一种显示面板，该显示面板包括：显示区、非显示区、第一信号线和多个静电释放单元。显示区包括子像素；非显示区至少部分围绕所述显示区，且包括静电释放区域；第一信号线，整体上沿第一方向从所述显示区延伸至所述静电释放区域，且被配置为给所述子像素提供第一显示信号；多个静电释放单元在所述第一方向上排列，每个所述静电释放单元包括至少一个子静电释放单元，所述至少一个子静电释放单元中的每个包括静电释放电路和第一导体，所述静电释放电路与所述第一信号线和所述第一导体电连接，且被配置为使所述第一信号线上的电荷朝向所述第一导体移动；所述静电释放电路在第二方向上的尺寸小于所述静电释放电路在所述第一方向上的尺寸，所述第二方向与所述第一方向垂直。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1是一种显示面板的静电释放单元的排布方式示意图；
图2是本公开一实施例提供的一种显示面板的平面结构示意图；
图3是图2中的显示区的局部的子像素示意图；
图4A是本公开一实施例提供的显示面板的一种静电释放单元的排布示意图；
图4B是图4A的包括一个静电释放组的局部放大示意图；
图4C是本公开一实施例提供的显示面板的另一种静电释放单元在静电释放区域中的排布示意图；
图4D是本公开一实施例提供的显示面板的又一种静电释放单元在静电释放区域中的排布示意图；
图4E是本公开一实施例提供的显示面板的再一种静电释放单元在静电释放区域中的排布示意图；
图5A是本公开一实施例提供的一种显示面板的子静电释放单元的静电 释放电路的示意图；
图5B为是本公开一实施例提供的一种显示面板的子静电释放单元的一种具体的静电释放电路的示意图；
图6A为本公开至少一实施例提供的子像素的像素电路的示意图；
图6B为图6A所示的像素电路的一种具体实现示例的电路图；
图6C为本公开至少一实施例提供的像素电路的驱动方法的信号时序图；
图7A为本公开至少一实施例提供的显示面板的一个子静电释放单元的结构的平面示意图；
图7B为图7A所示的子静电释放单元的半导体层的示意图；
图7C为图7A所示的子静电释放单元的第一导电层的示意图；
图7D为图7A所示的子静电释放单元的层间绝缘层的示意图；
图7E为图7A所示的子静电释放单元的第二导电层的示意图；
图7F为沿图7A中的A1-A2线的截面示意图；
图8为本公开实施例提供的包括静电释放单元的几种异形显示面板的示意图；
图9A为本公开实施例提供的Y形显示面板的示意图；
图9B为Y形显示面板的包括静电释放区域和引线区域的局部的平面示意图；
图9C为图9B所示的局部的半导体层的示意图；
图9D为图9B所示的局部的第一导电层的示意图；
图9E为图9B所示的局部的层间绝缘层的示意图；
图9F为图9B所示的局部的第二导电层的示意图；
图10为本公开实施例提供的显示面板的数据选择电路示意图；
图11为图10所示的数据选择电路的工作时序图；
图12A为本公开实施例提供的显示面板的一个数据选择单元的结构平面图；
图12B为图12A所示的数据选择单元的半导体层示意图；
图12C为图12A所示的数据选择单元的第一导电层示意图；
图12D为图12A所示的数据选择单元的层间绝缘层示意图；
图12E为图12A所示的数据选择单元的第二导电层示意图；
图13A为本公开实施例提供的心形显示面板的示意图；
图13B为心形显示面板的包括静电释放区域和引线区域的局部的平面示意图；
图14A为本公开实施例提供的D形显示面板的示意图；
图14B为D形显示面板的包括静电释放区域和引线区域的局部的平面示意图；
图15A为本公开实施例提供的O形显示面板的示意图；
图15B为O形显示面板的包括静电释放区域和引线区域的局部的平面示意图；
图16A为本公开实施例提供的I形显示面板的示意图；
图16B为I形显示面板的包括静电释放区域和引线区域的局部的平面示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。以下所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现在该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开中使用的“基本对齐”“基本相同”等包含一定误差的情况，考虑到测量和与特定量的测量相关的误差(例如，测量系统的限制)，表示在本领域的普通技术人员所确定的对于特定值的可接受的偏差范围内。例如，“基本”能够表示在一个或多个标准偏差内，如无特别说明，可表示在所述值的10％或者5％偏差范围内。
在本公开中的术语“直接连接”是指彼此连接的两个结构(例如A与B直接连接等)彼此接触，彼此连接的两个结构之间不存在任何其他的结构作为两者连接的媒介。例如，彼此直接连接的两个结构可以是连续的一体成型结构，此时彼此直接连接的两个结构的材料是相同的，可以通过同一构图工艺形成该两个结构以简化显示基板的制作工艺；或者，彼此直接连接的两个结构的材料也可以是不同的，例如彼此直接连接的两个结构都是导电的信号线，两者可以分别采用与两者的功能相匹配的材料，满足对不同性能例如不同导电率的需求。
本公开中的术语“同层设置”指对同一材料形成的膜曾执行同一步骤(例如同一图案化工艺)后形成的多个膜层之间的关系。这里的“同层设置”并不总是指多个膜层的厚度相同或者多个膜层在截面图中的高度相同。
本公开所有示例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，根据在电路中的作用，本公开的示例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开示例中，为区分晶体管除栅极之外的两极，将其中源极称为第一极，漏极称为第二极。此外本公开示例所采用的开关晶体管包括P型开关晶体管和N型开关晶体管中的至少一个，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型开关晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
在显示面板中，信号线上容易积聚电荷，积聚的电荷会在显示过程中产生多种不利影响，甚至产生一些不可预测的影响显示质量的问题，因此，静电释放对于显示电路至关重要，当静电发生时，可以通过设置静电释放单元将信号线上的电荷进行释放，以很好的保护显示电路。
图1是一种显示面板的静电释放单元的排布方式示意图，在图1所示的 显示面板中，显示面板包括多条信号线Data1、Data2……DataN，设置有分别与多条信号线Data1、Data2……DataN电连接的多个静电释放单元，即图1中的矩形框所代表的ESD单元，以分别对多条信号线Data1、Data2……DataN进行静电释放。但是，多个静电释放单元在横向上排布，例如在需要对每条信号线都设置静电释放单元，且为了实现高分辨率，信号线的密度很高的况下，留给设置较多的静电释放单元的空间很有限。例如一些异形屏的边缘形状不规则，异形屏的底部边框区尺寸很小，往往不具备矩形显示屏的边框区所具有的足够设置多个静电释放单元的宽度，无法设置大量的静电释放单元。
本公开至少一实施例提供一种显示面板，该显示面板包括：显示区、非显示区、第一信号线和多个静电释放单元。显示区包括子像素；非显示区至少部分围绕所述显示区，且包括静电释放区域；第一信号线整体上沿第一方向从所述显示区延伸至所述静电释放区域，且被配置为给所述子像素提供第一显示信号；多个静电释放单元在所述第一方向上排列，每个所述静电释放单元包括至少一个子静电释放单元，所述至少一个子静电释放单元中的每个包括静电释放电路和第一导体，所述静电释放电路与所述第一信号线和所述第一导体电连接，且被配置为使所述第一信号线上的电荷朝向所述第一导体移动；所述多个静电释放单元包括在第二方向上相邻的两个相邻的静电释放单元，所述第二方向与所述第一方向垂直，所述两个相邻的静电释放单元在平行于所述第一方向的面上的正投影彼此不重叠且在平行于第二方向的面上的正投影彼此至少部分重叠，或者，所述两个相邻的静电释放单元在平行于所述第一方向的面上的正投影彼此不重叠且在所述第二方向上彼此之间的距离小于1微米。
本公开至少一实施例提供一种显示面板，该显示面板包括：显示区、非显示区、第一信号线和多个静电释放单元。显示区包括子像素；非显示区至少部分围绕所述显示区，且包括静电释放区域；第一信号线，整体上沿第一方向从所述显示区延伸至所述静电释放区域，且被配置为给所述子像素提供第一显示信号；多个静电释放单元在所述第一方向上排列，每个所述静电释放单元包括至少一个子静电释放单元，所述至少一个子静电释放单元中的每 个包括静电释放电路和第一导体，所述静电释放电路与所述第一信号线和所述第一导体电连接，且被配置为使所述第一信号线上的电荷朝向所述第一导体移动；在所述多个静电释放单元中，每两个相邻的所述静电释放单元在平行于所述第一方向的面上的正投影均彼此不重叠。
本公开至少一实施例提供一种显示面板，该显示面板包括：显示区、非显示区、第一信号线和多个静电释放单元。显示区包括子像素；非显示区至少部分围绕所述显示区，且包括静电释放区域；第一信号线，整体上沿第一方向从所述显示区延伸至所述静电释放区域，且被配置为给所述子像素提供第一显示信号；多个静电释放单元在所述第一方向上排列，每个所述静电释放单元包括至少一个子静电释放单元，所述至少一个子静电释放单元中的每个包括静电释放电路和第一导体，所述静电释放电路与所述第一信号线和所述第一导体电连接，且被配置为使所述第一信号线上的电荷朝向所述第一导体移动；所述非显示区包括引线区域，所述引线区域设置有驱动电路，所述驱动电路配置为给所述第一信号线提供所述第一显示信号；所述静电释放区域位于所述引线区域和所述显示区之间，且给全部所述子像素提供所述第一显示信号的所述第一信号线所连接的所述多个子静电释放单元均位于所述显示区在所述第一方向上的同一侧。
本公开至少一实施例提供一种显示面板，该显示面板包括：显示区、非显示区、第一信号线和多个静电释放单元。显示区包括子像素；非显示区至少部分围绕所述显示区，且包括静电释放区域；第一信号线，整体上沿第一方向从所述显示区延伸至所述静电释放区域，且被配置为给所述子像素提供第一显示信号；多个静电释放单元在所述第一方向上排列，每个所述静电释放单元包括至少一个子静电释放单元，所述至少一个子静电释放单元中的每个包括静电释放电路和第一导体，所述静电释放电路与所述第一信号线和所述第一导体电连接，且被配置为使所述第一信号线上的电荷朝向所述第一导体移动；所述静电释放电路在第二方向上的尺寸小于所述静电释放电路在所述第一方向上的尺寸，所述第二方向与所述第一方向垂直。
示例性地，图2是本公开一实施例提供的一种显示面板的平面结构示意图，图3是图2中的显示区的局部的子像素示意图。如图2-3所示，本公开 至少一实施例提供的显示面板10包括：显示区1、非显示区2、第一信号线01和多个静电释放单元EU。显示区1包括多个子像素100，例如，如图3所示，多个子像素呈阵列排列；当然，图3只是对显示区1的局部子像素的示例性示意，多个子像素的具体排布方式不限于图3所示的情形。非显示区2至少部分围绕显示区1，且包括静电释放区域20；第一信号线01整体上沿第一方向D1从显示区1延伸至静电释放区域20，且被配置为给子像素100提供第一显示信号。图4A是本公开一实施例提供的显示面板的一种静电释放单元在静电释放区域中的排布示意图，图4B是图4A在包括一个静电释放组的局部放大示意图。如图4A-4B所示，多个静电释放单元EU在第一方向D1上排列，每个静电释放单元EU包括至少一个子静电释放单元SEU，至少一个子静电释放单元SEU中的每个包括静电释放电路EC和第一导体C1，静电释放电路EC与第一信号线01和第一导体C1电连接，且被配置为使第一信号线01上的电荷朝向第一导体C1移动，从而减少第一信号线01上的电荷；例如，每个静电释放单元EU包括多个子静电释放单元SEU，每个子静电释放单元SEU与一条第一信号线01电连接以对该第一信号线01进行静电释放。
在本申请中，特征“所述第一信号线整体上沿第一方向延伸”是指：第一信号线的走线趋势是沿第一方向，包括以下情况：例如，第一信号线的可以为沿第一方向延伸的直线型；或者，第一信号线的至少一部分具有一定的弯折或者相对于第一方向倾斜，但是，从第一信号线的起始端到终止端的方向是沿第一方向的。
需要说明的是，图4A中的第一信号线组Data1、Data2、Data3、Data4……Data n-1和Data n分别代表与一个静电释放单元EU电连接的一条或多条第一信号线且分别可以包括分别与该一个静电释放单元EU中的多个子静电释放单元SEU电连接的多条第一信号线01。
例如，参考图4A，显示面板10的多个静电释放单元EU构成在第二方向D2上间隔排列的多个静电释放单元组EUG，每个静电释放单元组EUG包括M个子静电释放单元组SEUG，每个子静电释放单元组SEUG包括N个静电释放单元EU，每个静电释放单元EU包括Q个子静电释放单元SEU，M和Q是大于等于1的正整数，N是大于等于2的正整数。
如图4A所示，多个静电释放单元EU包括在第二方向D2上相邻的两个相邻的静电释放单元，该两个相邻的静电释放单元例如分别为第一静电释放单元EU1和第二静电释放单元EU2，第二方向D2与第一方向D1垂直。该两个相邻的静电释放单元在平行于第一方向D1的面上的正投影彼此不重叠且在平行于第二方向D2的面上的正投影彼此至少部分重叠，如此，第一静电释放单元EU1和第二静电释放单元EU2不仅在第一方向D1上错开，且在第二方向D2上错开，可以大大减小多个静电释放单元EU在第二方向D2上占用的空间，以在静电释放区域20在第二方向D2上的尺寸较小的情况下，也能够实现设置较多个静电释放单元。例如，显示区的像素阵列包括沿第一方向D1延伸且在第二方向D2上排列的多个子像素列和沿第二方向D2延伸的且在第一方向D1上排列的多个子像素行，显示面板10包括多条第一信号线01，一条第一信号线01给对应的一个子像素列提供第一显示信号；在显示面板的分辨率较高的情况下，子像素列的排布密度是非常高的，从而第一信号线01的排布密度也是是非常高的，为了实现较为理想的静电释放效果，保证每条第一信号线01上的静电都能被及时释放，需要针对每条第一信号线01设置子静电释放单元SEU，这种情况下，子静电释放单元SEU的个数很多，需要静电释放区域在第二方向D2上具有足够的尺寸来设置如此多的子静电释放单元SEU，然而，在显示面板10中留给设置较多的子静电释放单元的空间很有限的情形下，例如当显示面板10是异形显示面板时，异形显示面板的边缘形状不规则，位于异形显示面板的底部的边框区的尺寸很小，即图2中的静电释放区域20在第二方向D2上的尺寸很小，本公开提供的上述技术方案仍然能够在实现高分辨率的情况下，实现对每条第一信号线01设置子静电释放单元SEU，达到较好的静电释放效果。
这里，以两个相邻的静电释放单元例如分别为第一静电释放单元EU1和第二静电释放单元EU2为例，“两个相邻的静电释放单元在平行于第二方向D2的面上的正投影彼此至少部分重叠”可以理解为：第一静电释放单元EU1的至少部分与第二静电释放单元EU2的至少部分在平行于第二方向D2的面上的正投影彼此至少部分重叠，即只要两个相邻的静电释放单元在平行于第二方向D2的面上的正投影存在重叠即可，包括部分或整个第一静电释放单元EU1在平行于第二方向D2的面上的正投影与第二静电释放单元EU2在平 行于第二方向D2的面上的正投影存在重叠，或者，部分或整个第二静电释放单元EU2在平行于第二方向D2的面上的正投影与第一静电释放单元EU1在平行于第二方向D2的面上的正投影存在重叠的情形。
图4B是图4A的包括一个静电释放组的局部放大示意图，如图4B所示，以一个静电释放组EUG为例对静电释放组与第一信号线的关系进行说明。例如，如图4B所示，一个静电释放组EUG作为一个子静电释放组SEUG，即，一个静电释放组EUG只包括一个子静电释放组SEUG；例如，每个子静电释放单元组SEUG包括2个静电释放单元EU，每个静电释放单元EU包括3个子静电释放单元SEU，即，M＝1，N＝2，Q＝3；当然，这里只是以这种情况为例对一个静电释放组EUG的结构进行介绍，对于M、N和Q的值不做限定。例如，多个静电释放单元EU的多个子静电释放单元SEU分别与多条第一信号线01中的一条第一信号线01电连接，以对该第一信号线01上的静电进行释放。例如，如图4B所示，第一静电释放单元EU1包括三个子静电释放单元，分别为第一子静电释放单元S1a、第二子静电释放单元S2a、第三子静电释放单元S3a，这三个子静电释放单元S1a/S2a/S3a分别与三条在第二方向D2上连续排列的三条第一信号线01a/01b/01c电连接，以分别对三条第一信号线01a/01b/01c上的静电进行释放，也即，图4A中的第一信号线组Data1包括三条第一信号线01a/01b/01c。第二静电释放单元EU2包括三个子静电释放单元，分别为第一静电释放单元S1b、第二子静电释放单元S2b、第三子静电释放单元S3b，这三个子静电释放单元S1b/S2b/S3b分别与三条在第二方向D2上连续排列的三条第一信号线01d/01e/01f电连接，以分别对三条第一信号线01d/01e/01f上的静电进行释放，也即，图4A中的第一信号线组Data1包括三条第一信号线01d/01e/01f。
例如，结合图4A和图4B，第二静电释放单元EU2与第一静电释放单元EU1在平行于第二方向D2的面上的正投影彼此至少部分重叠。例如，第二静电释放单元EU2中的多个子静电释放单元与第一静电释放单元EU1的多个子静电释放单元在平行于第二方向D2的面上的正投影彼此至少部分重叠，以有效减小多个静电释放单元EU在第二方向D2上占用的空间。
例如，如图4B所示，在多个静电释放单元EU的多个子静电释放单元SEU中，至少两个子静电释放单元SEU，例如第一静电释放单元EU1的第 三子静电释放单元S3a与第二静电释放单元EU2的第二子静电释放单元S2b，在平行于第一方向D1的面上的正投影彼此不重叠且在平行于第二方向D2的面上的正投影彼此至少部分重叠，以进一步减小多个静电释放单元EU在第二方向D2上占用的空间。
例如，如图4B所示，对于每个子静电释放单元SEU，静电释放电路EC在第二方向D2上的尺寸小于静电释放电路EC在第一方向D1上的尺寸。如此，可通过对静电释放电路EC的各个元件的布局进行设计，以使得在满足给设置静电释放电路提供充足的空间的情况下，充分利用第一方向D2上的空间，减小静电释放电路EC在第二方向D2上所占用的空间，从而有利于在第二方向D2上设置更多的子静电释放单元，给每条第一信号线实现静电释放，满足静电释放区域在第二方向D2上的尺寸非常小的显示面板的静电释放需求。
例如，如图4B所示，至少一条第一信号线01包括位于静电释放区域20的凹陷部，以第一信号线01d为例，例如，第一信号线01d包括位于静电释放区域20的凹陷部P1，凹陷部P1构成在第二方向D2上的朝向一侧凹陷的凹槽G1，与凹槽G1相邻的子静电释放单元即第一静电释放单元EU1的第三子静电释放单元S3a至少部分位于凹槽G1内，以实现错位，减小多个子静电释放单元在第二方向D2上所占用空间。在图4B所示的实施例中，位于凹槽G1中的第三子静电释放单元S3a所电连接的第一信号线01c与具有该凹槽G1的第一信号线01d相邻；或者，在其他实施例中，位于凹槽中的子静电释放单元与具有该凹槽的第一信号线电连接。
例如，如图4B所示，多个静电释放单元EU中的至少一个静电释放单元包括在第二方向D2上相邻的两个子静电释放单元SEU，相邻的两条信号线，例如，第一信号线01c和第一信号线01d，均包括位于静电释放区域20的凹陷部P0/P1，第一信号线01c的凹陷部P0和第一信号线01d的凹陷部P1构成在第二方向D2上朝向同一侧凹陷的凹槽，相邻的两个子静电释放单元S2a/S3a分别至少部分位于第一信号线01c的凹陷部P0所构成的凹槽G0内和第一信号线01d的凹陷部P1所构成的凹槽G1内，以进一步有效减小多个静电释放单元在第二方向D2上的总宽度，满足较窄的静电释放区域的要求。
例如，如图4A和图4B所示，与第一静电释放单元EU1的第一子静电 释放单元SEU电连接的第一信号线01d包括第一凹陷部P1和第二凹陷部P2；第一凹陷部P1构成在第二方向D2上朝向第一侧凹陷的第一凹槽G1；第二凹陷部P2构成在第二方向D2上朝向与第一侧相对的第二侧凹陷的第二凹槽G2，且与第一凹陷部G1在第二方向D2上排列，第一静电释放单元EU1和第二静电释放单元EU2是彼此相邻的两个静电释放单元，第一静电释放单元EU1在平行于第一方向D1上的正投影位于第一凹槽G1在平行于第一方向D1上的正投影内，第二静电释放单元EU2在平行于第一方向D1上的正投影位于第二凹槽G2在平行于第一方向D1上的正投影内，以实现将相邻的两个静电释放单元在第二方向D2上错开，从而减小多个静电释放单元在第二方向D2上所占用的空间。进一步地，第一静电释放单元EU1的第三子静电释放单元S3a和第二静电释放单元EU2的第一子静电释放单元S1b是彼此相邻的两个子静电释放单元，第三子静电释放单元S3a在平行于第一方向D1上的正投影位于第一凹槽G1在平行于第一方向D1上的正投影内，第一子静电释放单元S1b在平行于第一方向D1上的正投影位于第二凹槽G2在平行于第一方向D1上的正投影内，以减小相邻的静电释放单元在第二方向D2上所占用的空间。并且，与第一信号线01d在第二方向D2上相邻的第一信号线01c、第一信号线01b也具有与第一信号线01d类似的第一凹陷部和第二凹陷部，多条第一信号线的第一凹陷部和第二凹陷部在平行于第一方向D1上的正投影分别彼此重叠，以配合相邻的静电释放单元在第二方向上的错位，减小多个静电释放单元和多条第一信号线整体在第二方向D2上的总宽度。
例如，如图4A所示，多个静电释放单元组EUG中的至少部分静电释放单元组在第二方向D2上呈周期排列，一个静电释放单元组EUG为周期中的一个重复单元，以使多个静电释放单元组的排列较为规整，有利于制作和保持多条第一信号线走线的均一性，从而保持多条第一信号线所传输的第一显示信号的均一性，以及对多条第一信号线的静电释放效果的均一性。
一个静电释放单元组包括的子静电释放单元SEU的个数为M*N*Q。例如，在图4A和图4B所示的实施例中，M等于1，N等于2，Q等于3。这种情况下，例如，一个静电释放单元组EUG在第二方向D2上的宽度小于等于129.5μm。分辨率越高，对于减小多个静电释放单元在第二方向D2上的总宽度的要求越高。例如，显示面板10的分辨率为X*Y，X代表显示区1 中的像素阵列的行数，Y代表显示区1中的像素阵列的列数，X大于等于960，Y大于等于1440；例如，X＝960，Y＝1920；或者，X＝1920，Y＝3840；或者，X＝1440，Y＝1440。对于具备如此较高的分辨率的显示面板，采用本公开实施例提供的上述排布方式也可以满足对于多个静电释放单元在第二方向D2上的总宽度的要求。
参考图2，例如，非显示区2包括引线区域21，引线区域即通常的Bonding区，引线区域21设置有覆晶薄膜(COF，Chip On Flex，or，Chip On Film)，覆晶薄膜包括柔性电路板(FPC)23。例如，柔性电路板23包括驱动电路IC，驱动电路IC配置为给数据线DL提供第一显示信号；静电释放区域20位于引线区域21和显示区1之间。例如，在本公开至少一实施例提供的显示面板10中，给全部子像素100提供第一显示信号的第一信号线01所连接的多个子静电释放单元SEU均位于显示区1在第一方向D1上的同一侧的非显示区2中。即，给全部子像素列提供数据信号的数据线DL所连接的子静电释放单元SEU均位于显示区1的同一侧，例如均沿显示区1的一条边设置，而不是一部分子静电释放单元SEU设置在显示区1的第一侧，另一部分子静电释放单元SEU设置在显示区1的与其第一侧相对的第二侧。例如，非显示区2还包括边框区，边框区包括第一边框区2a和第二边框区2b，第一边框区2a位于显示区1的第一侧，给全部子像素列提供数据信号的数据线DL所连接的子静电释放单元SEU均位于第一边框区2a中，而不设置于第二边框区2b中，如此，只需要在临近第一边框区2a的位置设置驱动电路即可，降低了制作难度，简化了结构。即使在这种情况下，采用本公开实施例提供的子静电释放单元SEU的排布方式也可以满足利用显示区1的同一侧在第二方向D2上有限的宽度来设置大量的子静电释放单元SEU，即使显示屏面板的平面形状是上述异形显示面板10，也可以利用异形的边缘的一部分在第二方向D2上的有限宽度来设置大量的子静电释放单元SEU，兼顾较高的PPI。
参考图2，例如，第一边框区2a位于引线区域21与显示区1之间，第二边框区2b位于显示区1的与其第一侧相对的第二侧。第一边框区2a中设置有第一电源引线PL，第一电源引线PL配置为给子像素100提供第一电源电压VDD；引线区域21包括位于边框区的远离显示区1一侧的数据选择区域22，数据选择区域22中设置有数据选择单元，静电释放区域20位于第一 电源引线PL和数据选择区域22之间。
或者，第一电源引线PL配置为给子像素100提供第二电源电压VSS，例如，第一电源引线PL与下述第一静电释放晶体管T01的栅极T01g同层设置，且与子像素的覆盖整个显示区1的的阴极在非显示区2中通过过孔连接或者直接搭接；例如，提供第二电源电压VSS的第一电源引线PL的材料为透明导电材料，例如氧化铟锌(ITO)、氧化铟锌(IZO)等。
图4C是本公开一实施例提供的显示面板的另一种静电释放单元在静电释放区域中的排布示意图。图4C所示的实施例与图4A具有以下区别。
在图4C所示的实施例中，在M等于2，N等于2，Q等于3。
例如，如图4C所示，M个子静电释放单元组SEUG包括第一子静电释放单元组SEUG1和第二子静电释放单元组SEUG2，第一子静电释放单元组SEUG1和第二子静电释放单元组SEUG2相对于沿第一方向D1延伸的对称轴对称，以使多个静电释放单元组的排列较为规整，有利于制作和保持多条第一信号线走线的均一性，从而保持多条第一信号线所传输的第一显示信号的均一性，以及对多条第一信号线的静电释放效果的均一性。或者，在其他实施例中，第一子静电释放单元组和第二子静电释放单元组也可以非对称。
图4C所示的实施例的其他特征均与图4A和图4B的相同，可参考之前的描述。
图4D是本公开一实施例提供的显示面板的又一种静电释放单元在静电释放区域中的排布示意图。图4D所示的实施例与图4A具有以下区别。例如，对于至少一部分静电释放单元，两个相邻的静电释放单元，以第一子静电释放单元组SEUG1的彼此相邻的第二静电释放单元EU2和第三静电释放单元EU3为例，在平行于第一方向D1的面上的正投影彼此不重叠且在所述第二方向D2上彼此间隔开，即这两者在平行于第二方向D2上的正投影彼此不重叠，这种情况下，例如，这两个相邻的静电释放单元在第二方向D2上彼此之间的距离小于1微米，例如两个相邻的静电释放单元的彼此靠近的边缘在第二方向D2上的距离小于1微米。
在图4D所示的实施例中，在M等于2，N等于3，Q等于3，这种情况下，一个静电释放单元组在第二方向D2上的宽度小于等于294μm，即，一个静电释放单元组包括的18个子静电释放单元在第二方向D2上的总宽度为 294μm，以满足当静电释放区域在第二方向D2上的宽度更窄的情况下为设置较多的静电释放单元提供充足空间的要求。
例如，图4E是本公开一实施例提供的显示面板的再一种静电释放单元在静电释放区域中的排布示意图。图4E所示的实施例与图4A的区别在于，在图4E所示的实施例中，相邻的两个静电释放单元，例如第一静电释放单元EU1和第二静电释放单元EU2，在平行于第一方向D1的面上的正投影彼此不交叠且在平行于第二方向D2的面上的正投影彼此不交叠，以一定程度上减小多个，例如每个子静电释放单元组SEUG中，相邻的两个静电释放单元在平行于第一方向D1的面上的正投影彼此不交叠且在平行于第二方向D2的面上的正投影彼此不交叠。例如，在本公开至少一实施例提供的显示面板10中，在多个静电释放单元EU中，每两个相邻的静电释放单元EU在平行于第一方向D1的面上的正投影均彼此不重叠。图4E所示的实施例的其他特征均与图4A和图4B的相同，可参考之前的描述。
图5A是本公开一实施例提供的一种显示面板的子静电释放单元的静电释放电路的示意图。如图5A所示，例如，静电释放电路EC包括第一子电路001，第一子电路001具有驱动端、第一端和第二端；第一子电路001的驱动端和第一端均与第一信号线01电连接，第一子电路001的第二端与第一导体C1电连接。如此，第一信号线01上积累的静电可通过第一子电路001传导至第一导体C1，从而，从而减少了第一信号线01上的电荷，防止第一信号线01上积累的静电造成显示缺陷。
如图5A所示，例如，子静电释放单元SEU还包括第二导体C2，静电释放电路EC与第一信号线01和第二导体C2电连接，且被配置为使第一信号线01上的电荷朝向第二导体C2移动，从而减少了第一信号线01上的电荷。静电释放电路EC还包括第二子电路002，第二子电路002具有驱动端、第一端和第二端，第二子电路002的第一端与第一信号线01电连接，第二子电路002的驱动端和第二端均与第二导体C2连接。如此，第一信号线01上积累的静电还可通过第二子电路002传导至第二导体C2，从而减少了第一信号线01上的电荷，防止第一信号线01上积累的静电造成显示缺陷。
例如，在一些实施例中，静电释放电路可以只包括上述第一子电路而不包括上述第二子电路。
例如，在显示面板10的静电释放区域20中，第一子电路001和第二子电路002在第一方向D1上排列，以通过设计第一子电路001和第二子电路002的排布方式，减小第一子电路001和第二子电路002在第二方向D2上的总宽度，从而减小子静电释放单元在第二方向D2上的宽度，以满足在第二方向D2上的有限的空间内排布更多的子静电释放单元。
图5B为是本公开一实施例提供的一种显示面板的子静电释放单元的一种具体的静电释放电路的示意图。如图5B所示，在该静电释放电路EC中，第一子电路001包括第一静电释放晶体管T01，第二子电路002包括第二静电释放晶体管T02；第一静电释放晶体管T01的栅极T01g和第一极T01s均与第一信号线01电连接，第一静电释放晶体管T01的第二极T01d与第一导体C1电连接；第二静电释放晶体管T02的第一极T02s与第一信号线01电连接，第二静电释放晶体管T02的栅极T02g和第二极T02d均与第二导体C2连接。第一导体C1连接高电压端VGH，第二导体C2连接低电压端VGL。例如，高电压端VGH和低电压端VGL提供的电压的极性相反，例如高电压端VGH提供的第一电压Vh的极性为正，低电压端VGL提供的第二电压Vl的极性为负。
按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)，关闭电压为高电平电压(例如，5V、10V或其他合适的电压)；当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其他合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)。
该静电释放电路EC的工作过程如下，在此以第一静电释放晶体管T01和第二静电释放晶体管T02均为N型晶体管为例。当第一信号线01上传输的第一显示信号(例如为下文所述的数据信号Vd)为高电平时，第一静电释放晶体管T01的栅极T01g响应于该高电平而使第一静电释放晶体管T01开启，此时，第二电压Vl为低电平例如为-8V、-6V等，第二静电释放晶体管T02的栅极T02g响应于该低电平而使第二静电释放晶体管T02处于关闭状态，由此，第一信号线01上的电荷经第一静电释放晶体管T01传导至第一导体C1；当第一信号线01上传输的第一显示信号(例如为下文所述的数据 信号Vd)为低电平时，该低电平例如为-30V、-20V、-10V或其他合适的电压，第一静电释放晶体管T01的栅极T01g响应于该低电平而使第一静电释放晶体管T01处于关闭状态，由于第二电压Vl为低电平电压且高于第一信号线01上传输的第一显示信号的低电平电压，即高于第一静电释放晶体管T01的栅极T01g上的低电平，例如第二电压Vl为-8V、-6V等，以使得第二静电释放晶体管T02的栅源电压Vgs＝Vg-Vs＝Vl-Vd>Vth，该计算公式中的Vd代表第一信号线01上传输的第一显示信号的低电平电压，Vth代表第二静电释放晶体管T02的阈值电压，从而，使得第二静电释放晶体管T02开启，由此，第一信号线01上的电荷经第二静电释放晶体管T02传导至第二导体C2。以Vl＝-8V且Vd＝-20V为例，此时，Vgs＝Vg-Vs＝Vl-Vd＝-8-(-20)＝16V，Vgs大于通常的晶体管的阈值电压。如此，在第一信号线01上传输的第一显示信号为高电平和低电平的情况下，均可以通过图5B所示的静电释放电路EC释放第一信号线01上积累的静电荷。
例如，如图3所示，多个子像素100位于显示区1。例如，在一些实施例提供的显示基板10中，多个子像素100中的部分像素为虚拟子像素(dummy sub-pixel)1000，虚拟子像素1000不参与显示工作。
例如，该显示基板10是有机发光二极管(OLED)显示基板，该发光器件为OLED。该显示基板10还可以包括多条扫描线、多条数据线DL以用于为该多个子像素提供扫描信号(控制信号)和数据信号，从而驱动该多个子像素。根据需要，该显示基板10还可以进一步包括电源线、检测线等。
图6A为本公开至少一实施例提供的像素电路的示意图。如图6A所示，该像素电路单元100包括驱动子电路122、补偿子电路128、数据写入子电路126、存储子电路127、第一发光控制子电路123、第二发光控制子电路124及第一复位子电路125和第二复位子电路129。
例如，该驱动子电路122包括控制端122a、第一端122b和第二端122c，且配置为与发光器件121连接并且控制流经发光器件121的驱动电流。驱动子电路122的控制端122a和第一节点N1连接，驱动子电路122的第一端122b和第二节点N2连接并配置为接收第一电源电压VDD，驱动子电路122的第二端122c和第三节点N3连接。
例如，该数据写入子电路126包括控制端126a、第一端126b和第二端 126c，该控制端126a配置为接收第一扫描信号Ga1，第一端126b配置为接收数据信号Vd，第二端126c与驱动子电路122的第一端122b(也即第二节点N2)连接。该数据写入子电路126配置为响应于该第一扫描信号Ga1将该数据信号Vd写入驱动子电路122的第一端122b。例如，数据写入子电路126的第一端126b与数据线DL连接以接收该数据信号Vd，控制端126a与作为扫描线的栅线11连接以接收该第一扫描信号Ga1。例如，在数据写入及补偿阶段，数据写入子电路126可以响应于第一扫描信号Ga1而开启，从而可以将数据信号写入驱动子电路122的第一端122b(第二节点N2)，并将数据信号存储在存储子电路127中，以在例如发光阶段时可以根据该数据信号生成驱动发光器件121发光的驱动电流。
例如，补偿子电路128包括控制端128a、第一端128b和第二端128c，补偿子电路128的控制端128a配置为接收第二扫描信号Ga2，补偿子电路128的第一端128b和第二端128c分别与驱动子电路122的第二端122c和控制端122a电连接，补偿子电路128配置为响应于该第二扫描信号Ga2对该驱动子电路122进行阈值补偿。
例如，第一扫描信号Ga1可以与第二扫描信号Ga2相同。例如第一扫描信号Ga1可以与第二扫描信号Ga2连接到相同的信号输出端。例如，第一扫描信号Ga1可以与第二扫描信号Ga2通过相同的扫描线传输。
在另一些示例中，第一扫描信号Ga1也可以与第二扫描信号Ga2不同。例如，第一扫描信号Ga1可以与第二扫描信号Ga2连接到不同的信号输出端。例如，第一扫描信号Ga1可以与第二扫描信号Ga2分别通过不同的扫描线传输。
例如，存储子电路127包括第一端127a和第二端127b，该存储子电路的第一端127a配置为接收第一电源电压VDD，存储子电路的第二端127b与驱动子电路的控制端122a电连接。
例如，存储子电路127与驱动子电路122的控制端122a及第一电压端vdd电连接，配置为存储数据写入子电路126写入的数据信号。例如，在数据写入和补偿阶段，补偿子电路128可以响应于该第二扫描信号Ga2而开启，从而可以将数据写入子电路126写入的数据信号存储在该存储子电路127中。例如，同时在数据写入和补偿阶段，补偿子电路128可以将驱动子电路122 的控制端122a和第二端122c电连接，从而可以使驱动子电路122的阈值电压的相关信息也相应地存储在该存储子电路中，从而例如在发光阶段可以利用存储的数据信号以及阈值电压对驱动子电路122进行控制，使得驱动子电路122的输出得到补偿。
例如，第一发光控制子电路123与驱动子电路122的第一端122b(第二节点N2)以及第一电压端vdd连接，且配置为响应于第一发光控制信号EM1将第一电压端vdd的第一电源电压VDD施加至驱动子电路122的第一端122b。例如，如图6A所示，第一发光控制子电路123和第一发光控制端EM1、第一电压端vdd以及第二节点N2连接。
例如，第二发光控制子电路124和第二发光控制端EM2、发光器件121的第一端134以及驱动子电路122的第二端122c连接，且配置为响应于第二发光控制信号使得驱动电流可被施加至发光器件121。
例如，在发光阶段，第二发光控制子电路124响应于第二发光控制端EM2提供的第二发光控制信号EM2而开启，从而驱动子电路122可以通过第二发光控制子电路124与发光器件121电连接，从而驱动发光器件121在驱动电流控制下发光；而在非发光阶段，第二发光控制子电路124响应于第二发光控制信号EM2而截止，从而避免有电流流过发光器件121而使其发光，可以提高相应的显示装置的对比度。
又例如，在初始化阶段，第二发光控制子电路124也可以响应于第二发光控制信号EM2而开启，从而可以结合复位子电路以对驱动子电路122以及发光器件121进行复位操作。
例如，第二发光控制信号EM2可以与第一发光控制信号EM1相同，例如第二发光控制信号EM2可以与第一发光控制信号EM1连接到相同的信号输出端，例如，第二发光控制信号EM2可以与第一发光控制信号EM1通过相同的发光控制线传输。
在另一些示例中，第二发光控制信号EM2可以与第一发光控制信号EM1不同。例如，第二发光控制信号EM2可以与第一发光控制信号EM1分别连接到不同的信号输出端。例如，第二发光控制信号EM2可以与第一发光控制信号EM1分别通过不同的发光控制线传输。
例如，第一复位子电路125与第一复位电压端Vinit1以及驱动子电路122 的控制端122a(第一节点N1)连接，且配置为响应于第一复位控制信号Rst1将第一复位电压Vinit1施加至驱动子电路122的控制端122a。
例如，第二复位子电路129与第二复位电压端Vinit2以及发光器件121的第一端134(第四节点N4)连接，且配置为响应于第二复位控制信号Rst2将第二复位电压Vinit2施加至发光器件121的第一端134。
例如，第一复位子电路125和第二复位子电路129可以分别响应于第一复位控制信号Rst1和第二复位控制信号Rst2而开启，从而可以将分别将第二复位电压Vinit2施加至第一节点N1以及将第一复位电压Vinit1施加至发光器件121的第一端134，从而可以对驱动子电路122、补偿子电路128以及发光器件121进行复位操作，消除之前的发光阶段的影响。
例如，每行子像素的第二复位控制信号Rst2可以与该行子像素的第一扫描信号Ga1为相同的信号，二者可以通过同一栅线(例如图3A中的复位控制线220b)传输。例如，每行子像素的第一复位控制信号Rst1可以与上一行子像素的第一扫描信号Ga1，二者可以通过同一栅线(例如图3A中的复位控制线220a)传输。
例如，如图6A，发光器件121包括第一端134和第二端135，发光器件121的第一端134配置为与驱动子电路122的第二端122c连接，发光器件121的第二端135配置为与第二电压端VSS连接。例如，在一个示例中，如图6A所示，发光器件121的第一端134可以通过第二发光控制子电路124连接至第四节点N4。本公开的实施例包括但不限于此情形。
需要注意的是，在本公开实施例的说明中，第一节点N1、第二节点N2、第三节点N3和第四节点N4并非一定表示实际存在的部件，而是表示电路图中相关电路连接的汇合点。
需要说明的是，在本公开的实施例的描述中，符号Vd既可以表示数据信号端又可以表示数据信号的电平，同样地，符号Ga1、Ga2既可以表示第一扫描信号、第二扫描信号，也可以表示第一扫描信号端和第二扫描信号端，符号Rst1既可以表示第一复位控制端又可以表示第一复位控制信号，符号Rst2既可以表示第二复位控制端又可以表示第二复位控制信号，符号Vinit1、Vinit2既可以表示第一复位电压端和第二复位电压端又可以表示第一复位电压和第二复位电压，符号VDD既可以表示第一电源电压又可以表示第一电 源线，符号VSS既可以表示公共电源电压又可以表示公共电源线。以下各实施例与此相同，不再赘述。
图6B为图6A所示的像素电路的一种具体实现示例的电路图。如图6B所示，该像素电路包括第一至第七晶体管T1、T2、T3、T4、T5、T6、T7以及包括存储电容Cst。例如，第一晶体管T1被用作驱动晶体管，其他的第二至第七晶体管被用作开关晶体管。
例如，如图6B所示，驱动子电路122可以实现为第一晶体管T1。第一晶体管T1的栅极作为驱动子电路122的控制端122a，和第一节点N1连接；第一晶体管T1的第一极作为驱动子电路122的第一端122b，和第二节点N2连接；第一晶体管T1的第二极作为驱动子电路122的第二端122c，和第三节点N3连接。
例如，如图6B所示，数据写入子电路126可以实现为第二晶体管T2。第二晶体管T2的栅极和第一扫描线(第一扫描信号端Ga1)连接以接收第一扫描信号，第二晶体管T2的第一极和数据线DL(数据信号端Vd)连接以接收数据信号，第二晶体管T2的第二极和驱动子电路122的第一端122b(第二节点N2)连接。
例如，如图6B所示，补偿子电路128可以实现为第三晶体管T3。第三晶体管T3的栅极、第一极和第二极分别作为该补偿子电路的控制端128a、第一端128b和第二端128c。第三晶体管T3的栅极配置为和第二扫描线(第二扫描信号端Ga2)连接以接收第二扫描信号，第三晶体管T3的第一极T3s和第一晶体管T1的第二极T1d(第三节点N3)连接，第三晶体管T3的第二极T3d和第一晶体管T1的栅极T1g(第一节点N1)电连接。例如，如图6B所示，存储子电路127可以实现为存储电容Cst，该存储电容Cst包括第一极板Cst1和第二极板Cst2，该第一极板Cst2和第一电压端vdd电连接，该第二极板Cst1和第一晶体管T1的栅极T1g(第一节点N1)电连接。
例如，如图6B所示，第一发光控制子电路123可以实现为第四晶体管T4。第四晶体管T4的栅极和第一发光控制线(第一发光控制端EM1)连接以接收第一发光控制信号，第四晶体管T4的第一极和第一电压端vdd连接以接收第一电源电压，第四晶体管T4的第二极和驱动子电路122的第一端122b(第二节点N2)连接。
例如，发光器件121具体实现为发光二极管(LED)，例如可以是有机发光二极管(OLED)、量子点发光二极管(QLED)或者无机发光二极管，例如可以是微型发光二极管(Micro LED)或者微型OLED。例如，发光器件121可以为顶发射结构、底发射结构或双面发射结构。该发光器件121可以发红光、绿光、蓝光或白光等。本公开的实施例对发光器件的具体结构不作限制。
例如，发光器件121的第一端包括第一电极(例如为阳极)，该第一电极和第四节点N4连接配置为通过第二发光控制子电路124连接到驱动子电路122的第二端122c，发光器件121的第二端包括第二电极(例如为阴极)，该第二电极配置为和公共电源电压端VSS连接以接收公共电源电压VSS，从驱动子电路122的第二端122c流入发光器件121的电路决定发光器件的亮度。例如公共电源电压端VSS可以接地，即VSS可以为0V。例如，公共电源电压VSS可以为负电压。
例如，第二发光控制子电路124可以实现为第五晶体管T5。第五晶体管T5的栅极和第二发光控制线(第二发光控制端EM2)连接以接收第二发光控制信号，第五晶体管T5的第一极和驱动子电路122的第二端122c(第三节点N3)连接，第五晶体管T5的第二极和发光器件121的第一端134(第四节点N4)连接。
例如，第一复位子电路125可以实现为第六晶体管T6，第二复位子电路实现为第七晶体管T7。第六晶体管T6的栅极配置为和第一复位控制端Rst1连接以接收第一复位控制信号Rst1，第六晶体管T6的第一极和第一复位电压端Vinit1连接以接收第一复位电压Vinit1，第六晶体管T6的第二极配置为和第一节点N1连接。第七晶体管T7的栅极配置为和第二复位控制端Rst2连接以接收第二复位控制信号Rst2，第七晶体管T7的第一极和第二复位电压端Vinit2连接以接收第二复位电压Vinit2，第七晶体管T7的第二极配置为和第四节点N4连接。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了 区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
例如，如图6B所示，该第一至第七晶体管T1-T7均为P型晶体管，例如为低温多晶硅薄膜晶体管。然而本公开实施例对晶体管的类型不作限制，当晶体管的类型发生改变时，相应地调整电路中的连接关系即可。
以下结合图6C所示的信号时序图，对图6B所示的像素电路的工作原理进行说明。如图6C所示，每一帧图像的显示过程包括三个阶段，分别为初始化阶段1、数据写入及补偿阶段2、和发光阶段3。
如图6C所示，在本实施例中，第一扫描信号Ga1和第二扫描信号Ga2采用同一信号，第一发光控制信号EM1和第二发光控制信号EM2采用同一信号；且第二复位控制信号Rst2和第一扫描信号Ga1/第二扫描信号Ga2的波形相同，也即第二复位控制信号Rst2、第一扫描信号Ga1/第二扫描信号Ga2可以采用同一信号；本行子像素的第一复位信号Rst1与上一行子像素的第一扫描信号Ga1/第二扫描信号Ga2的波形相同，也即采用同一信号。然而，这并不作为对本公开的限制，在其它实施例中，可以采用不同的信号分别作为第一扫描信号Ga1、第二扫描信号Ga2、第一复位控制信号Rst1、第二复位控制信号Rst2，采用不同的信号分别作为第一发光控制信号EM1和第二发光控制信号EM2。
在初始化阶段1，输入第一复位控制信号Rst1以开启第六晶体管T6，将第一复位电压Vinit1施加至第一晶体管T1的栅极，从而对该第一节点N1复位。
在数据写入及补偿阶段2，输入第一扫描信号Ga1、第二扫描信号Ga2以及数据信号Vd，第二晶体管T2和第三晶体管T3开启，数据信号Vd由第二晶体管T2写入第二节点N2，并经过第一晶体管T1和第三晶体管T3对第一节点N1充电，直至第一节点N1的电位变化至Vd+Vth时第一晶体管T1截止，其中Vth为第一晶体管T1的阈值电压。该第一节点N1的电位存储于存储电容Cst中得以保持，也就是说将带有数据信号和阈值电压Vth的电压信息存储在了存储电容Cst中，以用于后续在发光阶段时，提供灰度显示数据和对第一晶体管T1自身的阈值电压进行补偿。
在数据写入补偿阶段2，还可以输入第二复位控制信号Rst2以开启第七 晶体管T7，将第二复位电压Vinit2施加至第四节点N4，从而对该第四节点N4复位。例如，对该第四节点N4的复位也可以在初始化阶段1进行，例如，第一复位控制信号Rst1和第二复位控制信号Rst2可以相同。本公开实施例对此不作限制。
在发光阶段3，输入第一发光控制信号EM1和第二发光控制信号EM2以开启第四晶体管T4、第五晶体管T5和第一晶体管T1，第五晶体管T5将驱动电流施加至OLED以使其发光。流经OLED的驱动电流Id的值可以根据下述公式得出：
Id＝K(VGS-Vth)2＝K[(Vd+Vth-VDD)-Vth]2＝K(Vd-VDD)2，其中，K为第一晶体管的导电系数。
在上述公式中，Vth表示第一晶体管T1的阈值电压，VGS表示第一晶体管T1的栅极和源极(这里为第一极)之间的电压，K为与第一晶体管T1本身相关的一常数值。从上述Id的计算公式可以看出，流经OLED的驱动电流Id不再与第一晶体管T1的阈值电压Vth有关，由此可以实现对该像素电路的补偿，解决了驱动晶体管(在本公开的实施例中为第一晶体管T1)由于工艺制程及长时间的操作造成阈值电压漂移的问题，消除其对驱动电流Id的影响，从而可以改善采用其的显示装置的显示效果。
参考图3，该显示基板10包括衬底基板200、设置在衬底基板200上的整体上沿第一方向D1延伸的第一信号线01和整体上沿第二方向D2延伸的第二信号线02；例如，第一信号线01与第二信号线02相交以限定出多个子像素100。需要说明的是，该多个子像素的每个的边界未必是第一信号线01和第二信号线02，第一信号线01与第二信号线02相交以限定出子像素是指多个子像素是指多个子像素的排列方式与第一信号线01与第二信号线02相交而限定出的多个区域的排列方式一致，即多个子像素与该度过区域一一对应。
例如，第一信号线01是数据线DL，第二信号线02是作为扫描信号线的栅线。第一显示信号为数据信号Vd，第一信号线01传输数据信号Vd；多个子像素100中至少部分子像素100的每个包括上述像素电路，像素电路包括上述发光器件、驱动晶体管T1以及数据写入晶体管T2，数据写入晶体管T2配置为在第一扫描信号Ga1的控制下将数据信号Vd传输至驱动晶体管 T1；驱动晶体管T1配置为根据数据信号Vd控制流经发光器件的驱动电流的大小，发光器件配置为接收驱动电流且被驱动电流驱动以发光。
当然，在其他一些实施例中，第一信号线也可以是其他类型的信号线，在本公开中，第一信号线不局限于是上述数据线DL。
图7A为本公开至少一实施例提供的显示面板的一个子静电释放单元的结构的平面示意图；图7B为图7A所示的子静电释放单元的半导体层的示意图；图7C为图7A所示的子静电释放单元的第一导电层的示意图；图7D为图7A所示的子静电释放单元的层间绝缘层的示意图；图7E为图7A所示的子静电释放单元的第二导电层的示意图；图7F为沿途7A中的A1-A2线的截面示意图。
参考图7A，例如，在本公开至少一实施例提供的显示面板10中，静电释放电路EC在第二方向D2上的尺寸小于静电释放电路EC在第一方向D1上的尺寸，第二方向D2与第一方向D1垂直，以尽可能地减小每个子静电释放单元在第二方向D2上的宽度，从而大大减小多个子静电释放单元在第二方向D2上的总宽度。
参考图7A，例如，第一静电释放晶体管T01和第二静电释放晶体管T02在第一方向D1上排列，第一静电释放晶体管T01的第一极T01s和第二极T01d在第一方向D1上排列，第二静电释放晶体管T02的第一极T02s和第二极T02d在第一方向D1上排列，以通过设计第一静电释放晶体管T01和第二静电释放晶体管T02、第一静电释放晶体管T01的源漏极和第二静电释放晶体管T02的源漏极的排布方式，减小第一静电释放晶体管T01和第二静电释放晶体管T02构成的整体在第二方向D2上的总宽度，从而减小静电释放电路在第二方向D2上的宽度，减小子静电释放单元在第二方向D2上的宽度，以满足在第二方向D2上的有限的空间内排布更多的子静电释放单元。
参考图7A和图7B，例如，第一静电释放晶体管T01包括第一有源层T01a，第二静电释放晶体管T02包括第二有源层T02a；第一有源层T01a和第二有源层T02a均沿第一方向D1延伸，第一有源层T01a在第二方向D2上的宽度小于第一有源层T01a在第一方向D1上的长度，第二有源层T02a在第二方向D2上的宽度小于第二有源层T02a在第一方向D1上的长度，以利用第一方向D1上的空间排布第一静电释放晶体管T01和第二静电释放晶 体管T02，在进一步减小第一静电释放晶体管T01和第二静电释放晶体管T02在第二方向D2上的宽度的同时，能够兼顾第一有源层和第二有源层的尺寸，兼顾第一静电释放晶体管T01和第二静电释放晶体管T02的性能。例如，第一有源层T01a在第二方向D2上的宽度小于第一有源层T01a在第一方向D1上的长度，第二有源层T02a在第二方向D2上的宽度小于第二有源层T02a在第一方向D1上的长度，以进一步在进一步减小第一静电释放晶体管T01和第二静电释放晶体管T02在第二方向D2上的宽度的同时，兼顾第一有源层和第二有源层的尺寸，兼顾第一静电释放晶体管T01和第二静电释放晶体管T02的性能。
参考图7A和图7B，例如，静电释放半导体层位于半导体层ACT，第一有源层T01a与第二有源层T02a构成连续的一体成型的静电释放半导体层，静电释放半导体层整体上呈沿第一方向D1延伸的条形。例如，静电释放半导体层静电释放半导体层呈直的条形，且位于第一条形部S1和第二条形部S2的远离数据线DL的一侧，以进一步减小第一栅极部GP1、第二栅极部GP2和静电释放半导体层和在第二方向D2上占用的空间，从而进一步减小一个子静电释放单元在第二方向D2上的宽度，可有效减小多个子静电释放单元在第二方向D2上占用的总宽度。
参考图7A和图7C，例如，第一导体C1与第二导体C2、第一静电释放晶体管T01的栅极T01g和第二静电释放晶体管T02的栅极T02g均位于第一导电层110；例如一静电释放晶体管T01的栅极T01g和第二静电释放晶体管T02的栅极T02g均与像素电路的驱动晶体管T1的栅极同层设置，从而可以与像素电路的驱动晶体管T1的栅极采用同一掩膜通过同一构图工艺形成，简化制作工艺，且简化显示面板的层结构。第一导体C1与第二导体C2在第一方向D1上间隔排列，且第一导体C1沿第二方向D2延伸；子静电释放单元SEU包括第一栅极部GP1；第二导体C2包括沿第二方向D2延伸的主体部CM和与主体部CM连接且沿第二方向D2延伸的第二栅极部GP2，例如第二栅极部GP2与第二导体C2的主体部CM构成一体成型结构；第一栅极部GP1与第二栅极部GP2在第一方向D1上间隔排列，且第一栅极部GP1和第二栅极部GP2位于第一导体C1与第二导体C2的主体部CM之间；第一栅极部GP1的与第一有源层T01a交叠的部分构成第一静电释放晶体管 T01的栅极T01g，第二栅极部GP2的与第二有源层T02a交叠的部分构成第二静电释放晶体管T02的栅极T02g，且第一栅极部GP1与数据线DL电连接。
参考图7A和图7C，例如，第一栅极部GP1包括沿第一方向D1延伸的第一条形部S1和与第一条形部S1电连接的栅连接结构CG，栅连接结构CG自第一条形部S1在第二方向D2上朝向数据线DL突出于第一条形部S1，栅连接结构CG与数据线DL通过第一过孔V1电连接。第一栅极部GP1还包括与第一条形部S1电连接的第一突出部，第一突出部自第一条形部S1在第二方向D2上远离数据线DL突出于第一条形部S1，第一突出部的与第一有源层T01a交叠的部分构成第一静电释放晶体管T01的栅极T01g；例如，第一突出部包括在第一方向D1上排列且彼此间隔的第一连接块G1和第二连接块G2。第二栅极部GP2包括沿第一方向D1延伸的第二条形部S2和与第二条形部S2电连接的第二突出部，第二突出部自第二条形部S2在第二方向D2上突出于第二条形部S2，第二突出部的与第二有源层T02a交叠的部分构成第二静电释放晶体管T02的栅极T02g。例如，第二突出部包括在第一方向D1上排列且彼此间隔的第三连接块G3和第四连接块G4。
参考图7A和图7C，例如，第二突出部自第二条形部S2在第二方向D2上沿远离数据线DL的方向突出于第二条形部S2，第一条形部S1与第二条形部S2在第一方向D1上基本对齐，第一突出部与第二突出部在第一方向D1上基本对齐，以减小第二栅极部GP2在第二方向D2上的宽度，从而减小一个子静电释放单元在第二方向D2上的宽度，可有效减小多个子静电释放单元在第二方向D2上占用的总宽度。
参考图7A和图7E，例如，第一信号线01位于第二导电层120。子静电释放单元SEU还包括数据连接结构DL1，数据连接结构DL1与数据线DL电连接且自数据线DL在第二方向D2朝向静电释放半导体层突出于数据线DL，数据连接结构DL1在第二方向D2上靠近数据线DL的第一端通过第一过孔V1与栅连接结构CG电连接，从而实现栅连接结构CG与数据线DL通过第一过孔V1电连接，也即，实现第一静电释放晶体管T01的栅极T01g与数据线DL电连接。数据连接结构DL1在第二方向D2上远离数据线DL的第二端通过第二过孔V2与静电释放半导体层电连接，从而实现第一静电 释放晶体管T01的第一极T01s也与数据线DL电连接，以及第二静电释放晶体管T02的第一极T02s与数据线DL电连接。第二过孔V2在第一方向D1上位于第一突出部与第二突出部之间。例如，数据连接结构DL1与上述第一信号线01的与该数据连接结构DL1相邻的凹陷部电连接，例如，图7B中的第一信号线01的与静电释放半导体层电连接的部分是凹陷部的一部分。
参考图7A和图7E，例如，子静电释放单元SEU还包括第一连接结构201和第二连接结构202；第一连接结构201和第二连接结构202位于第二导电层120。第一连接结构201在第一方向D1上的第一端通过第三过孔V3与第一导体C1连接，第一连接结构201在第一方向D1上的第二端通过第四过孔V4与第一有源层T01a连接，从而实现第一静电释放晶体管T01的第二极T01d与第一导体C1电连接。第二连接结构202在第一方向D1上的第一端通过第五过孔V5与第二导体C2的主体部CM连接，第二连接结构202在第一方向D1上的第二端通过第六过孔V6与第二有源层T02a连接，从而实现第二静电释放晶体管T02的栅极T02g和第二极均与第二导体C2连接。
参考图7D和图7F，例如，显示面板10还包括位于半导体层ACT与第一导电层110之间的第一绝缘层GI1、位于第一导电层110与第二导电层120之间的第二绝缘层GI2和层间绝缘层ILD；第一过孔V1贯穿第二绝缘层GI2和层间绝缘层ILD，第二过孔V2贯穿第一绝缘层GI1、第二绝缘层GI2和层间绝缘层ILD，第三过孔V3贯穿第二绝缘层GI2和层间绝缘层ILD，第四过孔V4贯穿第一绝缘层GI1、第二绝缘层GI2和层间绝缘层ILD，第五过孔V5贯穿第二绝缘层GI2和层间绝缘层ILD，第六过孔V6贯穿第一绝缘层GI1、第二绝缘层GI2和层间绝缘层ILD。
参考图7F，显示基板10还包括位于衬底基板200上的缓冲层Buffer，半导体层ACT位于缓冲层Buffer上，缓冲层Buffer可以防止制作过程中对衬底基板200的污染和破坏，使形成于其上的其他结构更加纯净和平整。
在本公开实施例提供的显示基板10中，例如，衬底基板200可以为刚性基板，例如玻璃基板、硅基板等，也可以由具有优良的耐热性和耐久性的柔性材料形成，例如聚酰亚胺(PI)、聚碳酸酯(PC)、聚乙烯对苯二甲酸乙二醇酯(PET)、聚乙烯、聚丙烯酸酯、多芳基化合物、聚醚酰亚胺、聚醚砜、聚乙二醇对苯二甲酸酯(PET)、聚乙烯(PE)、聚丙烯(PP)、聚砜(PSF)、聚甲基 丙烯酸甲酯(PMMA)、三醋酸纤维素(TAC)、环烯烃聚合物(COP)和环烯烃共聚物(COC)等。
例如，该半导体层ACT的材料包括但不限于硅基材料(非晶硅a-Si，多晶硅p-Si等)、金属氧化物半导体(IGZO，ZnO，AZO，IZTO等)以及有机物材料(六噻吩，聚噻吩等)。
例如，第一导电层和第二导电层的材料可以包括金(Au)、银(Ag)、铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钨(W)以及以上金属组合而成的合金材料；或者透明导电金属氧化物材料，例如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化锌铝(AZO)等。
例如，第一绝缘层GI1、第二绝缘层GI2、层间绝缘层ILD为无机绝缘层，其材料例如包括氧化硅、氮化硅、氮氧化硅等硅的氧化物、硅的氮化物或硅的氮氧化物中的至少之一，或者包括氧化铝、氮化钛等包括金属氮氧化物绝缘材料。但是，本公开实施例对此不作限制。
图8为本公开实施例提供的包括静电释放单元的几种异形显示面板的示意图。例如，如图8中的(a)所示，本公开实施例提供的显示面板的平面形状为字母Y形，具有Y形的显示区1，静电释放区域20位于底部Y形显示面板的底部边缘处。Y形显示面板在第二方向D2上的最大宽度L1大于Y形显示面板的底部可供设置静电释放区域20的非显示区在第二方向D2上的宽度L2。例如，L1＝156912μm，L2＝71640μm，L2/L1＝0.46。L2与L1的比值小于0.5，这意味着可供设置静电释放区域的底部空间在第二方向上的尺寸相对于显示区所跨越的空间在第二方向上的尺寸的要小很多，因此，例如，对于多种异形显示面板，尤其对于L2与L1的比值小于0.5的显示面板，由于可供设置静电释放区域的空间在第二方向D2上的宽度小到一定程度，从而需要大大缩减多个静电释放单元ESD在第二方向D2上的总宽度。
图9A为本公开实施例提供的Y形显示面板的示意图；图9B为Y形显示面板的包括静电释放区域和引线区域的局部的平面示意图；图9C为图9B所示的局部的半导体层的示意图；图9D为图9B所示的局部的第一导电层的示意图；图9E为图9B所示的局部的层间绝缘层的示意图；图9F为图9B所示的局部的第二导电层的示意图。
图9B所示的实施例，采用了图4A所示的静电释放单元的排布方式。展 示了相邻的第一静电释放单元组EUG1和第二静电释放单元组EUG2的排布方式。例如，在图9B所示的实施例中，M等于1，N等于2，Q等于3。
参考图2和图9A，例如，驱动电路IC所在的区域(即驱动电路IC所占的空间)在第二方向D2上的宽度L IC小于静电释放区域20在第二方向D2上的宽度L ESD。由此，参考图2和图9B，例如，数据选择单元MUXU的靠近静电释放区域20的第一端与R条数据线DL电连接，数据选择单元MUXU的远离静电释放区域20的第二端与S条数据引线电连接，S和R均为正整数且S小于R；S条数据引线电连接至驱动电路，通过驱动电路给S条数据引线提供第一显示信号即数据信号Vd。如此，可以减少数据引线的个数，从而减小多条数据引线在第二方向D2上所需求的总宽度，以适应于驱动电路IC所在的区域在第二方向D2上的宽度L IC相对于静电释放区域20在第二方向D2上的宽度L ESD较小的情况。
例如，参考图9B，R＝2，S＝1，即，数据选择单元MUXU的靠近静电释放区域20的第一端与2条数据线DL电连接，这2条数据线DL分别为第一数据线01a和第二数据线01b，数据选择单元MUXU的远离静电释放区域20的第二端与1条数据引线01c电连接。参考图4B和图9B，例如，第一数据线01a与第一静电释放单元EU1中的第一子静电释放单元S1a电连接，第二数据线01b与第二静电释放单元EU2中的第一子静电释放单元S1b电连接。例如，第一静电释放单元EU1的三个子静电释放单元S1a/S2a/S3a分别对应给显示区1中的位于同一个像素的三个子像素提供数据信号Vd，例如分别给红、绿、蓝三个子像素提供数据信号Vd。即，数据选择单元MUXU的靠近静电释放区域20的第一端与分别与两条数据线DL电连接，这两条数据线DL分别与相邻的像个像素的同一颜色的两个子像素电连接以给该同一颜色的两个子像素提供数据信号Vd；数据选择单元MUXU的远离静电释放区域20的第二端与一条数据引线01c电连接。当然，R不限于等于2，S不限于等于1，优选R等于2且S等于1。如此，在减小了连接至驱动电路IC的多个数据引线的个数的同时，由于R的数值不是特别大，不会使太多条数据线共用一个数据选择电路，且同一个数据选择单元MUXU连接给同一颜色的多个子像素提供数据信号的数据线，对数据信号的选择控制相对容易，给显示效果带来的我影响较小，并且，由于该同一颜色的多个子像素是相邻的 且R的数值不是特别大，使得布线较简单，制作难度低。
参考图9B、图9D和图9F，例如，第二数据线01b可以跨层转接，其包括第一部分01b1、第二部分01b2和第三部分01b3，参考图9F，第一部分01b1和第二部分01b2位于第二导电层120，第三部分01b3位于第一导电层110，第三部分01b3的第一端通过过孔与第一部分01b1电连接，第三部分01b3的第二端通过过孔与第二部分01b2电连接，因为，在该异形屏中，可供设置静电释放单元和驱动电路IC的空间很小，如此，能够实现在有限的空间内布置与多个数据选择单元MUXU连接的多条数据线DL。
下面对一个数据选择单元MUXU的结构进行介绍。图10为本公开实施例提供的显示面板的数据选择电路示意图；图11为图10所示的数据选择电路的工作时序图；图12A为本公开实施例提供的显示面板的一个数据选择单元的结构平面图。
参考图10和图12A，数据选择单元MUXU包括数据选择电路，数据选择电路包括第一数据选择晶体管T001和第二数据选择晶体管T002。第一数据选择晶体管T001的栅极电连接第一数据端以接收来自第一数据端的第一数据驱动信号MUXG1；第二数据选择晶体管T002的栅极电连接第二数据端以接收来自第二数据端的第二数据驱动信号MUXG2。第一数据选择晶体管T001的第一极与第一数据线01a电连接以向第一数据线01a的输出第一输出信号Output1，第二数据选择晶体管T002的第一极与第二数据线01b电连接以向第二数据线01b输出第二输出信号Output2。第一数据选择晶体管T001的第二极与第二数据选择晶体管T002的第二极电连接，且均电连接至数据引线01c以接收来自数据引线01c的输入数据信号Input。
以第一数据选择晶体管T001的第二极与第二数据选择晶体管T002均为N型晶体管为例介绍数据选择电路的工作过程。参考图10-11，在第一阶段t1，第一数据驱动信号MUXG1为高电平，第二数据驱动信号MUXG2为低电平，以使得第一数据选择晶体管T001开启，第二数据选择晶体管T002关闭；此时，输入数据信号Input为第一数据信号，第一数据信号作为第一输出信号Output1通过第一数据选择晶体管T001传输到第一数据线01a，继而经第一数据线01a提供给对应的子像素。在第二阶段t2，第一数据驱动信号MUXG1为低电平，第二数据驱动信号MUXG2为高电平，以使得第一数据 选择晶体管T001关闭，第二数据选择晶体管T002开启；此时，输入数据信号Input为不同于第一数据信号的第二数据信号，第二数据信号作为第二输出信号Output2通过第二数据选择晶体管T002传输到第二数据线01b，继而经第二数据线01b提供给对应的子像素。
图12B示出了第一数据选择晶体管T001的有源层T001a和第二数据选择晶体管T002的有源层T002a。例如，有源层T001a和有源层T002a分别包括在第一方向D1上排列的多个岛。图12C示出了第一数据选择晶体管T001的栅极T001g和第二数据选择晶体管T002的栅极T002g。参考图12D-12E，第一数据线01a通过第一组过孔V01与第一数据选择晶体管T001的有源层T001a电连接，第二数据线01b通过第二组过孔V02与第二数据选择晶体管T002的有源层T002a电连接，数据引线01c通过第三组过孔V03与有源层T001a以及有源层T002a电连接，例如，对于每个岛，有源层T001a和有源层T002a一体成型。多个在第一方向D1上排列的岛的结构有利于增大第一数据选择晶体管T001的栅极T001g和第二数据选择晶体管T002的宽长比，提高晶体管的性能，且能够减小多个数据选择单元在第二方向D2上的宽度，满足其所在的区域在第二方向D2上的尺寸非常有限的要求。
参考图9B和图9F，例如，显示面板10还包括：复位电压线RL和复位电压引线RL0。例如复位电压线RL和复位电压引线RL0均位于第二导电层120，与数据线DL同层。复位电压线RL配置为给子像素100提供复位电压信号，且包括位于非显示区的引线部RL1/RL2；第一引线部RL1位于相邻的两个静电释放单元EU1和EU2之间且沿第一方向D1延伸，相邻的J条引线部经由沿第二方向D2延伸的复位连接线RLC电连接；例如，在图9B所示的实施例中，J＝2，相邻的第一引线部RL1和第二引线部RL2经由沿第二方向D2延伸的复位连接线RLC电连接。复位电压引线RL0的第一端与复位连接线RLC电连接，复位电压引线RL0的第二端与驱动电路IC电连接，驱动电路IC配置为提供复位电压信号。例如，该复位电压信号为上述提供给像素电路的第一复位电压Vinit1和第一复位电压Vinit2，第一复位电压Vinit1和第一复位电压Vinit2可以相同，均是通过驱动电路IC经复位电压线RL提供。
在另一个实施例中，例如，如图8中的(d)所示，本公开实施例提供的显示面板的平面形状为心形，具有心形的显示区1，静电释放区域20位于心 形显示面板的底部边缘处。心形显示面板在第二方向D2上的最大宽度L1大于心形显示面板的底部可供设置静电释放区域20的非显示区在第二方向D2上的宽度L2。例如，L1＝231061μm，L2＝84651μm，L2/L1＝0.37。这意味着可供设置静电释放区域的底部空间在第二方向上的尺寸相对于显示区所跨越的空间在第二方向上的尺寸的要小很多，甚至，L2/L1的值小于Y形显示面板中L2/L1的值，因此，例如，对于该异形显示面板，由于可供设置静电释放区域的空间在第二方向D2上的宽度小到一定程度，从而需要大大缩减多个静电释放单元ESD在第二方向D2上的总宽度。
图13A为本公开实施例提供的心形显示面板的示意图；图13B为心形显示面板的包括静电释放区域和引线区域的局部的平面示意图。
参考图2和图13A，例如，驱动电路IC所在的区域(即驱动电路IC所占的空间)在第二方向D2上的宽度L IC小于静电释放区域20在第二方向D2上的宽度L ESD。例如，L ESD＝70560μm，L IC＝47864μm。因此，数据选择电路和复位电压引线的设计同样可参考类似于图9B所示的实施例的设计。
图13B所示的实施例采用了图4D所示的静电释放单元的排布方式。展示了相邻的第一子静电释放单元组SEUG1和第二子静电释放单元组SEUG2所构成的一个静电释放单元组EUG。
设像素的Pitch为δ，则边框宽度L＝两侧边框+分辨率*δ。例如，心形显示面板的分辨率为1440*1440，根据纵向两组错向ESD单元排布方式，即M等于1，N等于2，Q等于3，6个子静电释放单元构成一个静电释放组EUG，一个静电释放组EUG在第二方向上的总宽度为129.5μm，那么总的ESD单元需求空间＝[(3*1440)/6]*129.5＝93528μm，而心形显示面板的底部空间只有84651μm，显然不够。于是心形显示面板的静电释放单元的排布方式就得采用图13B所示的纵向三组错向排布方式，即M等于2，N等于3，Q等于3，18个静电释放单元构成一个静电释放组EUG，一个静电释放组EUG的宽度为294μm，心形显示面板全部的静电释放单元需求的在第二方向D2上的总宽度等于[(3*1440)/18]*294＝70560μm。相对于Y形显示面板，这种设计能够进一步减小全部静电释放单元在第二方向上的总宽度，在满足较高PPI的要求下，还能够满足心形显示面板中更小的L2/L1的值对于全部静电释放单元在第二方向上的总宽度更小的要求。
图13B所示的其他结构，例如，每个子静电释放单元、数据选择电路的结构等可参考对于图9B所示的实施例的描述。
在另一个实施例中，例如，如图8中的(c)所示，本公开实施例提供的显示面板的平面形状为字母D形，静电释放区域20位于D形显示面板的底部边缘处。D形显示面板在第二方向D2上的最大宽度L1大于D形显示面板的底部可供设置静电释放区域20的非显示区在第二方向D2上的宽度L2。例如，L1＝156912μm，L2＝97900μm，L2/L1＝0.62。
图14A为本公开实施例提供的D形显示面板的示意图；图14B为D形显示面板的包括静电释放区域和引线区域的局部的平面示意图。
例如，图14B所示的实施例采用了图4A所示的静电释放单元的排布方式。展示了相邻的第一子静电释放单元组SEUG1和第二子静电释放单元组SEUG2所构成的一个静电释放单元组EUG。例如，在图14B所示的实施例中，例如，D形显示面板的分辨率为960*1920，根据纵向两组错向ESD单元排布方式，即M等于1，N等于2，Q等于3，6个静电释放单元构成一个静电释放组EUG，一个静电释放组EUG在第二方向上的总宽度为129.5μm，因此，D形显示面板的全部的静电释放单元需求的在第二方向上的总宽度等于[(3*960)/6]*129.5＝62160μm，由此可见，纵向两组错向ESD单元排布方式可以满足D形显示面板的情况，Y形显示面板的静电释放单元对空间的需求情况与D形显示面板的相同。图14B所示的实施例与Y形显示面板类似，该设计同样能够减小全部静电释放单元在第二方向上的总宽度，满足心形显示面板中更小的L2/L1的值对于全部静电释放单元在第二方向上的总宽度较小的要求。当然，也可以使用图4C或图4D所示的静电释放单元的排布方式，以进一步减小全部静电释放单元在第二方向上的总宽度。图14B所示的其他结构，例如，每个子静电释放单元、数据选择电路的结构等可参考对于图9B所示的实施例的描述。
在另一个实施例中，例如，如图8中的(e)所示，本公开实施例提供的显示面板的平面形状为字母O形，静电释放区域20位于O形显示面板的底部边缘处。O形显示面板在第二方向D2上的最大宽度L1大于O形显示面板的底部可供设置静电释放区域20的非显示区在第二方向D2上的宽度L2。例如，L1＝307835μm，L2＝164400μm，L2/L1＝0.53。
图15A为本公开实施例提供的O形显示面板的示意图；图15B为O形显示面板的包括静电释放区域和引线区域的局部的平面示意图。
参考图15A，例如，O形显示面板的分辨率为1920*3840，分辨率较高。因此，O形显示面板具有两个COF，全部的静电释放单元需求的在第二方向D2上的总宽度是设置一个COF的两倍，更需要尽量减小每个静电释放单组、以及全部静电释放单元在第二方向D2上的总宽度。
图15B所示的实施例采用了图4C所示的静电释放单元的排布方式。展示了相邻的第一子静电释放单元组SEUG1和第二子静电释放单元组SEUG2所构成的一个静电释放单元组EUG。例如，在图15B所示的实施例中，O形显示面板的全部的静电释放单元需求的在第二方向D2上的总宽度为D的两倍，即M等于2，N等于2，Q等于3，12个静电释放单元构成一个静电释放组EUG，因此，O形显示面板全部的静电释放单元需求的在第二方向D2上的总宽度等于2*[(3*960)/6]*129.5＝124320μm，与Y形显示面板类似，该设计同样能够减小全部静电释放单元在第二方向上的总宽度，满足心形显示面板中更小的L2/L1的值对于全部静电释放单元在第二方向上的总宽度较小的要求。当然，也可以使用图4D所示的静电释放单元的排布方式，以进一步减小全部静电释放单元在第二方向上的总宽度。图15B所示的其他结构，例如，每个子静电释放单元、数据选择电路的结构等可参考对于图9B所示的实施例的描述。
在另一个实施例中，例如，如图8中的(b)所示，本公开实施例提供的显示面板的平面形状为字母I形，静电释放区域20位于I形显示面板的底部边缘处。
图16A为本公开实施例提供的I形显示面板的示意图；图16B为I形显示面板的包括静电释放区域和引线区域的局部的平面示意图。
例如，图16B所示的实施例采用了图4A所示的静电释放单元的排布方式。展示了相邻的第一子静电释放单元组SEUG1和第二子静电释放单元组SEUG2所构成的一个静电释放单元组EUG。例如，I形显示面板在第二方向D2上的最大宽度L1等于I形显示面板的底部可供设置静电释放区域20的非显示区在第二方向D2上的宽度，即L2/L1＝1。例如，L1＝156912μm，L2＝156912μm。可见，I形面板中底部边框用于设置静电释放单元的区域相 在第二方向D2上的宽度相对于显示区在第二方向D2上的宽度比较充分，因此，例如，参考图16B，彼此相邻的第一静电释放单元EU1和第二静电释放单元EU2在平行于第二方向D2的面上的正投影彼此不重叠，且在平行于第一方向D1的面上的正投影彼此重叠例如基本完全重叠，以保持排列规整，降低制作难度。
例如I形显示面板的分辨率为960*1920，对于图16B的排布方式，首尾各3个子静电释放单元在第二方向上的总宽度为260μm，对于中间的子静电释放单元，6个子静电释放单元为一个静电释放单元组，一个静电释放单元组在第二方向上的总宽度为280μm，则全部静电释放单元在第二方向上的总宽度等于[(3*960-6)/6]*280+260＝134380μm，而I形显示面板的底部空间在第二方向上的宽度为156912μm，有充足的静电释放单元设计空间。
当然，在I形显示面板中，相邻的两个静电释放单元在平行于第二方向D2的面上的正投影彼此也可以至少部分重叠，例如采用图4C或图4D所示的静电释放单元的排布方式，以减小全部静电释放单元在第二方向上的总宽度，适应较小尺寸的I形面板。
参考图2和图16A，例如，驱动电路IC所在的区域(即驱动电路IC所占的空间)在第二方向D2上的宽度L IC小于静电释放区域20在第二方向D2上的宽度L ESD。例如，L ESD＝134383μm，L IC＝47864μm。因此，数据选择电路和复位电压引线的设计同样可参考类似于图9B所示的实施例的设计。
图16B所示的其他结构，例如，每个子静电释放单元、数据选择电路的结构等可参考对于图9B所示的实施例的描述。
本公开至少一实施例提供一种显示装置，包括本公开实施例提供的任一的显示基板。该显示装置例如可以为有机发光二极管显示装置、量子点发光二极管显示装置等具有显示功能的装置或其他类型的装置。本公开的实施例对此不作限制。
本公开实施例提供的显示装置的结构、功能及技术效果等可以参考上述本公开实施例提供的显示基板10中的相应描述，在此不再赘述。
例如，本公开至少一实施例提供的显示装置可以为显示面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开的实施例对此不作限制。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围根据权利要求书所界定的范围确定。

Claims (30)

  1. 一种显示面板，包括：
    显示区，包括子像素；
    非显示区，至少部分围绕所述显示区，且包括静电释放区域；
    第一信号线，整体上沿第一方向从所述显示区延伸至所述静电释放区域，且被配置为给所述子像素提供第一显示信号；
    多个静电释放单元，在所述第一方向上排列，其中，每个所述静电释放单元包括至少一个子静电释放单元，所述至少一个子静电释放单元中的每个包括静电释放电路和第一导体，所述静电释放电路与所述第一信号线和所述第一导体电连接，且被配置为使所述第一信号线上的电荷朝向所述第一导体移动；
    所述多个静电释放单元包括在第二方向上相邻的两个相邻的静电释放单元，所述第二方向与所述第一方向垂直，所述两个相邻的静电释放单元在平行于所述第一方向的面上的正投影彼此不重叠且在平行于第二方向的面上的正投影彼此至少部分重叠，或者，所述两个相邻的静电释放单元在平行于所述第一方向的面上的正投影彼此不重叠且在所述第二方向上彼此之间的距离小于1微米。
  2. 根据权利要求1所述的显示面板，其中，在所述多个静电释放单元的多个子静电释放单元中，至少两个所述子静电释放单元在平行于所述第一方向的面上的正投影彼此不重叠且在平行于第二方向的面上的正投影彼此至少部分重叠。
  3. 根据权利要求1所述的显示面板，其中，所述静电释放电路在所述第二方向上的尺寸小于所述静电释放电路在所述第一方向上的尺寸。
  4. 根据权利要求1所述的显示面板，其中，所述显示面板包括多条所述第一信号线，所述多个静电释放单元的多个所述子静电释放单元分别与多条所述第一信号线中的一条第一信号线电连接；
    所述多条第一信号线中的至少一条包括位于所述静电释放区域的凹陷部，所述凹陷部构成在所述第二方向上的朝向一侧凹陷的凹槽，与所述凹槽 相邻的所述子静电释放单元至少部分位于所述凹槽内。
  5. 根据权利要求4所述的显示面板，其中，所述多个静电释放单元中的至少一个静电释放单元包括在所述第二方向上相邻的两个所述子静电释放单元，相邻的两条所述第一信号线均包括位于所述静电释放区域的凹陷部，所述相邻的两条第一信号线的凹陷部构成在所述第二方向上朝向同一侧凹陷的凹槽，相邻的两个所述子静电释放单元分别至少部分位于所述相邻的两条第一信号线的凹陷部所构成的凹槽内。
  6. 根据权利要求5所述的显示面板，其中，与所述至少一个所述子静电释放单元连接的所述第一信号线包括：
    第一凹陷部，构成在所述第二方向上朝向第一侧凹陷的第一凹槽；
    第二凹陷部，构成在所述第二方向上朝向与所述第一侧相对的第二侧凹陷的第二凹槽，且与所述第一凹陷部在所述第二方向上排列，其中，所述两个相邻的静电释放单元分别为第一静电释放单元和第二静电释放单元，所述第一静电释放单元在平行于所述第一方向上的正投影位于所述第一凹槽在平行于所述第一方向上的正投影内，所述第二静电释放单元在平行于所述第一方向上的正投影位于所述第二凹槽在平行于所述第一方向上的正投影内。
  7. 根据权利要求1所述的显示面板，其中，多个所述静电释放单元构成在第二方向上间隔排列的多个静电释放单元组，每个所述静电释放单元组包括M个子静电释放单元组，每个所述子静电释放单元组包括N个所述静电释放单元，每个所述静电释放单元包括Q个所述子静电释放单元，M和Q是大于等于1的正整数，N是大于等于2的正整数；
    所述多个静电释放单元组中的至少部分静电释放单元组在所述第二方向上呈周期排列，一个所述静电释放单元组为所述周期中的一个重复单元。
  8. 根据权利要求7所述的显示面板，其中，一个所述静电释放单元组包括的所述子静电释放单元的个数为M*N*Q；
    在M等于1，N等于2，Q等于3时，一个所述静电释放单元组在所述第二方向上的宽度小于等于129.5μm；或者，
    在M等于2，N等于3，Q等于3时，一个所述静电释放单元组在所述第二方向上的宽度小于等于294μm。
  9. 根据权利要求8所述的显示面板，其中，所述显示面板的分辨率为X*Y，X代表所述显示区中的像素阵列的行数，Y代表所述显示区中的像素阵列的列数，X大于等于960，Y大于等于1440。
  10. 根据权利要求7所述的显示面板，其中，所述M个子静电释放单元组包括第一子静电释放单元组和第二子静电释放单元组，第一子静电释放单元组和第二子静电释放单元组相对于沿所述第一方向延伸的对称轴对称或非对称。
  11. 根据权利要求1-10任一所述的显示面板，其中，所述第一显示信号为数据信号，所述第一信号线传输所述数据信号；所述子像素包括像素电路，所述像素电路包括：
    发光器件、驱动晶体管和数据写入晶体管，其中，所述数据写入晶体管配置为在第一扫描信号的控制下将所述数据信号传输至所述驱动晶体管；
    所述驱动晶体管配置为根据所述数据信号控制流经所述发光器件的驱动电流的大小，所述发光器件配置为接收所述驱动电流且被所述驱动电流驱动以发光。
  12. 根据权利要求1-11任一所述的显示面板，其中，所述非显示区包括引线区域，所述引线区域设置有驱动电路，所述驱动电路配置为给所述第一信号线提供所述第一显示信号；
    所述静电释放区域位于所述引线区域和所述显示区之间，且给全部所述子像素提供所述第一显示信号的所述第一信号线所连接的所述多个子静电释放单元均位于所述显示区在所述第一方向上的同一侧的所述非显示区中。
  13. 根据权利要求12所述的显示面板，其中，所述非显示区还包括边框区，所述边框区位于所述引线区域与所述显示区之间，所述边框区中设置有第一电源引线，所述第一电源引线配置为给所述子像素提供第一电源电压；
    所述引线区域包括位于所述边框区的远离所述显示区一侧的数据选择区域，所述数据选择区域中设置有数据选择单元，所述静电释放区域位于所述第一电源引线和所述数据选择区域之间。
  14. 根据权利要求12或13所述的显示面板，其中，所述数据选择单元的靠近静电释放区域的第一端与R条所述第一信号线电连接，所述数据选择 单元的远离静电释放区域的第二端与S条数据引线电连接，S和R均为正整数且S小于R；所述S条数据引线电连接至驱动电路，通过所述驱动电路给所述S条数据引线提供所述第一显示信号。
  15. 根据权利要求12-14任一所述的显示面板，其中，所述驱动电路所在的区域在所述第二方向上的宽度小于所述静电释放区域在所述第二方向上的宽度。
  16. 根据权利要求1-15任一所述的显示面板，其中，所述静电释放电路包括：
    第一子电路，具有驱动端、第一端和第二端，其中，所述第一子电路的驱动端和第一端均与所述第一信号线电连接，所述第一子电路的第二端与所述第一导体电连接。
  17. 根据权利要求16所述的显示面板，其中，所述子静电释放单元还包括第二导体，所述静电释放电路与所述第一信号线和所述第二导体电连接，且被配置为使所述第一信号线上的电荷朝向所述第二导体移动；
    所述静电释放电路还包括：
    第二子电路，具有驱动端、第一端和第二端，其中，所述第二子电路的第一端与所述第一信号线电连接，所述第二子电路的驱动端和第二端均与所述第二导体连接；
    所述第一子电路和所述第二子电路在所述第一方向上排列。
  18. 根据权利要求17所述的显示面板，其中，所述第一子电路包括第一晶体管，所述第二子电路包括第二晶体管；所述第一晶体管的栅极和第一极均与所述第一信号线电连接，所述第一晶体管的第二极与所述第一导体电连接；所述第二晶体管的第一极与所述第一信号线电连接，所述第二晶体管的栅极和第二极均与所述第二导体连接；
    所述第一晶体管和所述第二晶体管在所述第一方向上排列，所述第一晶体管的第一极和第二极在所述第一方向上排列，所述第二晶体管的第一极和第二极在所述第一方向上排列；
    所述第一晶体管包括第一有源层，所述第二晶体管包括第二有源层；所述第一有源层和所述第二有源层均沿所述第一方向延伸，所述第一有源层在 所述第二方向上的宽度小于所述第一有源层在所述第一方向上的长度，所述第二有源层在所述第二方向上的宽度小于所述第二有源层在所述第一方向上的长度。
  19. 根据权利要求18所述的显示面板，其中，所述第一导体与所述第二导体在所述第一方向上间隔排列，且所述第一导体沿所述第二方向延伸；
    所述子静电释放单元包括第一栅极部；所述第二导体包括沿所述第二方向延伸的主体部和与所述主体部连接且沿所述第二方向延伸的第二栅极部，所述第一栅极部与所述第二栅极部在所述第一方向上间隔排列，且所述第一栅极部和所述第二栅极部位于所述第一导体与所述第二导体的主体部之间；所述第一栅极部的与所述第一有源层交叠的部分构成所述第一晶体管的栅极，所述第二栅极部的与所述第二有源层交叠的部分构成所述第二晶体管的栅极，且所述第一栅极部与所述第一信号线电连接。
  20. 根据权利要求19所述的显示面板，其中，所述第一栅极部包括沿所述第一方向延伸的第一条形部和与所述第一条形部电连接的栅连接结构，所述栅连接结构自所述第一条形部在所述第二方向上朝向所述第一信号线突出于所述第一条形部，所述栅连接结构与所述第一信号线通过第一过孔电连接；
    所述第一栅极部还包括与所述第一条形部电连接的第一突出部，所述第一突出部自所述第一条形部在所述第二方向上远离所述第一信号线突出于所述第一条形部，所述第一突出部的与所述第一有源层交叠的部分构成所述第一晶体管的栅极；
    所述第二栅极部包括沿所述第一方向延伸的第二条形部和与所述第二条形部电连接的第二突出部，所述第二突出部自所述第二条形部在所述第二方向上突出于所述第二条形部，所述第二突出部的与所述第二有源层交叠的部分构成所述第二晶体管的栅极。
  21. 根据权利要求20所述的显示面板，其中，
    所述第二突出部自所述第二条形部在所述第二方向上沿远离所述第一信号线的方向突出于所述第二条形部，所述第一条形部与所述第二条形部在所述第一方向上基本对齐，所述第一突出部与所述第二突出部在所述第一方向上基本对齐。
  22. 根据权利要求20所述的显示面板，其中，所述第一有源层与所述第二有源层构成连续的一体成型的静电释放半导体层，所述静电释放半导体层整体上呈沿所述第一方向延伸的条形；
    所述子静电释放单元还包括数据连接结构，所述数据连接结构与所述第一信号线电连接且自所述第一信号线在所述第二方向朝向所述静电释放半导体层突出于所述第一信号线，所述数据连接结构在所述第二方向上靠近所述第一信号线的第一端通过所述第一过孔与所述栅连接结构电连接，所述数据连接结构在所述第二方向上远离所述第一信号线的第二端通过第二过孔与所述静电释放半导体层电连接，所述第二过孔在所述第一方向上位于所述第一突出部与所述第二突出部之间。
  23. 根据权利要求22所述的显示面板，其中，所述子静电释放单元还包括第一连接结构和第二连接结构；
    所述第一连接结构在所述第一方向上的第一端通过第三过孔与所述第一导体连接，所述第一连接结构在所述第一方向上的第二端通过第四过孔与所述第一有源层连接；
    所述第二连接结构在所述第一方向上的第一端通过第五过孔与所述第二导体的主体部连接，所述第二连接结构在所述第一方向上的第二端通过第六过孔与所述第二有源层连接。
  24. 根据权利要求22所述的显示面板，其中，所述静电释放半导体层呈直的条形，且位于所述第一条形部和所述第二条形部的远离所述第一信号线的一侧。
  25. 根据权利要求1-24任一所述的显示面板，还包括：
    复位电压线，配置为给所述子像素提供复位电压信号，且包括位于所述非显示区的引线部，其中，所述复位电压引线的引线部位于相邻的两个所述静电释放单元之间且沿所述第一方向延伸，相邻的J条所述引线部经由沿所述第二方向延伸的复位连接线电连接；以及
    复位电压引线，其中，所述复位电压引线的第一端与所述复位连接线电连接，所述复位电压引线的第二端与驱动电路电连接，所述驱动电路配置为提供所述复位电压信号。
  26. 根据权利要求25所述的显示面板，其中，所述驱动电路所在的区域在所述第二方向上的宽度小于所述静电释放区域在所述第二方向上的宽度。
  27. 一种显示面板，包括：
    显示区，包括子像素；
    非显示区，至少部分围绕所述显示区，且包括静电释放区域；
    第一信号线，整体上沿第一方向从所述显示区延伸至所述静电释放区域，且被配置为给所述子像素提供第一显示信号；
    多个静电释放单元，在所述第一方向上排列，其中，每个所述静电释放单元包括至少一个子静电释放单元，所述至少一个子静电释放单元中的每个包括静电释放电路和第一导体，所述静电释放电路与所述第一信号线和所述第一导体电连接，且被配置为使所述第一信号线上的电荷朝向所述第一导体移动；
    在所述多个静电释放单元中，每两个相邻的所述静电释放单元在平行于所述第一方向的面上的正投影均彼此不重叠。
  28. 一种显示面板，包括：
    显示区，包括子像素；
    非显示区，至少部分围绕所述显示区，且包括静电释放区域；
    第一信号线，整体上沿第一方向从所述显示区延伸至所述静电释放区域，且被配置为给所述子像素提供第一显示信号；
    多个静电释放单元，在所述第一方向上排列，其中，每个所述静电释放单元包括至少一个子静电释放单元，所述至少一个子静电释放单元中的每个包括静电释放电路和第一导体，所述静电释放电路与所述第一信号线和所述第一导体电连接，且被配置为使所述第一信号线上的电荷朝向所述第一导体移动；
    所述非显示区包括引线区域，所述引线区域设置有驱动电路，所述驱动电路配置为给所述第一信号线提供所述第一显示信号；
    所述静电释放区域位于所述引线区域和所述显示区之间，且给全部所述子像素提供所述第一显示信号的所述第一信号线所连接的所述多个子静电释放单元均位于所述显示区在所述第一方向上的同一侧。
  29. 一种显示面板，包括：
    显示区，包括子像素；
    非显示区，至少部分围绕所述显示区，且包括静电释放区域；
    第一信号线，整体上沿第一方向从所述显示区延伸至所述静电释放区域，且被配置为给所述子像素提供第一显示信号；
    多个静电释放单元，在所述第一方向上排列，其中，每个所述静电释放单元包括至少一个子静电释放单元，所述至少一个子静电释放单元中的每个包括静电释放电路和第一导体，所述静电释放电路与所述第一信号线和所述第一导体电连接，且被配置为使所述第一信号线上的电荷朝向所述第一导体移动；
    所述静电释放电路在第二方向上的尺寸小于所述静电释放电路在所述第一方向上的尺寸，所述第二方向与所述第一方向垂直。
  30. 一种显示装置，包括根据权利要求1-29任一所述的显示面板。
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