WO2024011738A1 - 一种感测放大器电路及触发器 - Google Patents

一种感测放大器电路及触发器 Download PDF

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Publication number
WO2024011738A1
WO2024011738A1 PCT/CN2022/117319 CN2022117319W WO2024011738A1 WO 2024011738 A1 WO2024011738 A1 WO 2024011738A1 CN 2022117319 W CN2022117319 W CN 2022117319W WO 2024011738 A1 WO2024011738 A1 WO 2024011738A1
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Prior art keywords
signal
circuit
switching device
node
amplifier circuit
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PCT/CN2022/117319
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English (en)
French (fr)
Inventor
史丹丹
巩启凡
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长鑫存储技术有限公司
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Priority to US18/152,334 priority Critical patent/US11979121B2/en
Publication of WO2024011738A1 publication Critical patent/WO2024011738A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit

Definitions

  • the present disclosure relates to, but is not limited to, a sense amplifier circuit and a flip-flop.
  • Flip-Flop is one of the basic logic unit circuits that constitute digital systems, such as high-speed circuit systems.
  • Flip-Flop, or FF for short is one of the basic logic unit circuits that constitute a digital system. It has trigger flipping characteristics and can convert between two stable states under the action of input signal. The performance of flip-flops has an important impact on the performance of digital systems, especially high-speed digital systems.
  • Transmission Gate Flip-Flop is a type of master-slave two-phase clock flip-flop. It consists of a master latch that is sensitive to low levels and a slave latch that is sensitive to high levels. The triggers are connected one after the other. If the setup time is not enough, the data will not be stably latched by the flip-flop on the rising edge of the clock signal CLK.
  • Pulse Triggered Flip Flop has greatly improved the shortcomings of TGFF's long setup time, but requires additional circuitry to generate a clock tree, which increases power consumption and area overhead.
  • SDFF Semi-Dynamic Flip-Flop
  • the flip-flop based on the sense amplifier is composed of the master stage of the fast differential sense amplifier and the slave stage of the SR latch. It has a small setup time and hold time and is relatively free from the above problems. It is a kind of device suitable for low supply voltage. s solution. In the existing technology, differential sensitive amplifiers have the problem of having many charging and discharging nodes, which can easily lead to data acquisition errors.
  • the present disclosure provides a sense amplifier circuit and a flip-flop.
  • a first aspect of the present disclosure provides a sense amplifier circuit including:
  • the charging module is configured to charge the setting signal node and the reset signal node according to the clock signal;
  • the sensing module is coupled to the charging module and is configured to sense and amplify the differential input signal according to the clock signal;
  • the sensing module includes a first amplification circuit, a second amplification circuit, and a cross-jump transfer circuit cross-connected between the first amplification circuit and the second amplification circuit;
  • the cross-jump transfer circuit includes a first transfer circuit and a second Transfer circuit;
  • the first transfer circuit is used to transfer the effective signal of the second amplification circuit to the first amplification circuit when the induction is completed and the differential input signal undergoes a first transition, so that the setting signal of the setting signal node and the reset signal node are The reset signal remains unchanged;
  • the second transfer circuit is used to transfer the effective signal of the first amplification circuit to the second amplification circuit when the induction is completed and the differential input signal undergoes a second transition, so that the setting signal of the setting signal no
  • the first amplifying circuit includes a first input signal amplifying circuit and a first clock signal sensing amplifying circuit connected in series;
  • the second amplifying circuit includes a second input signal amplifying circuit and a second clock signal sensing amplifying circuit connected in series. circuit;
  • the second clock signal sensing amplifying circuit and the first input signal amplifying circuit are connected through a first transfer circuit;
  • the first clock signal sensing amplifying circuit and the second input signal amplifying circuit are connected through a second Transfer circuit connections.
  • the first transfer circuit is connected in parallel with the first input signal amplification circuit, the first end of the first transfer circuit and the first end of the first input signal amplification circuit are both connected to a signal node, and the second end of the first transfer circuit and the first The second terminals of the input signal amplifier circuit are both connected to the first terminal of the first clock signal sensing amplifier circuit; the control terminal of the first transfer circuit is connected to the second terminal of the second clock signal sensing amplifier circuit; the second transfer circuit is connected to the first terminal of the first clock signal sensing amplifier circuit.
  • Two input signal amplification circuits are connected in parallel, the first end of the second transfer circuit and the first end of the second input signal amplification circuit are both connected to the reset signal node, the second end of the second transfer circuit and the second end of the second input signal amplification circuit are connected Both are connected to the first end of the second clock signal sensing amplifier circuit; the control end of the second transfer circuit is connected to the second end of the first clock signal sensing amplifier circuit.
  • the differential input signal includes an original data signal and an inverted data signal
  • the first amplification circuit receives the original data signal and is used for conducting during the sensing stage and pulling down the setting signal to a low level through the first pull-down path
  • the second amplifier circuit receives the inverted data signal and is used to conduct during the sensing phase and pull down the reset signal to a low level through the second pull-down path.
  • the first amplification circuit also includes a first ground amplification circuit; wherein the first input signal amplification circuit, the first clock signal sensing amplification circuit and the first ground amplification circuit are connected in series in sequence, and the first terminal of the first input signal amplification circuit Connected to the setting signal node, the second end of the first grounded amplifying circuit is connected to the ground; the control end of the first grounded amplifying circuit is connected to the reset signal node for turning on or off under the action of the reset signal; the second amplifying circuit also It includes a second ground amplifier circuit; wherein the second input signal amplifier circuit, the second clock signal sensing amplifier circuit and the second ground amplifier circuit are connected in series in sequence, the first end of the second input signal amplifier circuit is connected to the reset signal node, and the second input signal amplifier circuit is connected in series. The second end of the two-ground amplifier circuit is connected to the ground; the control end of the second ground-amplifier circuit is connected to the setting signal node for turning on or off under the action of the setting signal.
  • the charging module includes a first charging circuit and a second charging circuit; the first charging circuit is used to charge the setting signal node according to the clock signal; the second charging circuit is used to charge the reset signal node according to the clock signal; The first ends of the first charging circuit and the second charging circuit are both connected to the power supply; the second end of the first charging circuit is connected to the sensing module by setting a signal node; the second end of the second charging circuit is connected to the sensing module. Connect via the reset signal node.
  • the charging module also includes a first signal maintenance circuit and a second signal maintenance circuit; the first signal maintenance circuit is connected in parallel with the first charging circuit, and the first signal maintenance circuit is connected with the reset signal node; the second signal maintenance circuit is connected with the reset signal node.
  • the second charging circuit is connected in parallel, and the second signal maintaining circuit is connected to the setting signal node; the first signal maintaining circuit is used to maintain the setting signal state when the induction is completed and the second transition of the differential input signal occurs; the second signal maintaining circuit is used to When the sensing is completed and the first transition occurs in the differential input signal, the reset signal state is maintained.
  • the first charging circuit includes a first switch unit
  • the first signal maintenance circuit includes a second switch unit; the first switch unit and the second switch unit are connected in parallel; the first end of the first switch unit is connected to the power supply, and the second end is connected to the setting signal node; the first end of the second switch unit is connected to the power supply, and the second end is connected to the set signal node; the control end of the first switch unit is used to receive the clock signal; the control end of the second switch unit is used to receive the reset of the reset signal node signal; the second charging circuit includes a fourth switch unit; the second signal maintaining circuit includes a third switch unit; the third switch unit is connected in parallel with the fourth switch unit; the first end of the third switch unit is connected to the power supply, and the second end is connected to the setting signal node; the first end of the fourth switch unit is connected to the power supply, and the second end is connected to the setting signal node; the control end of the fourth switch unit is used to receive the clock signal; the control end of the third switch unit is used to the first
  • the first input signal amplification circuit includes a first switching device; the first transfer circuit includes a seventh switching device; the first end of the first switching device and the first end of the seventh switching device are both configured with The signal node is connected; the second end of the first switching device and the second end of the seventh switching device are both connected to the first end of the first clock signal sensing amplifier circuit; the control end of the seventh switching device is connected a second terminal of the second clock signal sensing amplifier circuit; the second input signal amplifier circuit includes a second switching device; the second transfer circuit includes an eighth switching device; the first terminal of the second switching device and the The first end of the eighth switching device is connected to the reset signal node; the second end of the second switching device and the second end of the eighth switching device are both connected to the third end of the second clock signal sensing amplifier circuit.
  • One end; the control end of the eighth switching device is connected to the second end of the first clock signal sensing amplifier circuit; the control end of the first switching device is used to receive the original data signal; the control end of the second switching device is used to for
  • the first clock signal sensing amplifier circuit includes a third switching device; the first end of the third switching device is connected to the second end of the first switching device; the second end of the third switching device is connected to the first ground The first end of the amplifier circuit; the control end of the third switching device is used to receive the clock signal; the second clock signal sensing amplifier circuit includes a fourth switching device; the first end of the fourth switching device is connected to the second switching device The second terminal; the second terminal of the fourth switching device is connected to the second terminal of the second grounded amplifier circuit; the control terminal of the fourth switching device is used to receive the clock signal.
  • the first grounded amplifier circuit includes a fifth switching device; the first end of the fifth switching device is connected to the second end of the third switching device; the second end of the fifth switching device is grounded; and the control end of the fifth switching device is for receiving the reset signal of the reset signal node;
  • the second grounded amplifier circuit includes a sixth switching device; the first end of the sixth switching device is connected to the second end of the fourth switching device; the second end of the sixth switching device is grounded; The control end of the six-switch device is used to receive the setting signal of the setting signal node.
  • a second aspect of the present disclosure provides a trigger including:
  • the sense amplifier circuit and latch described in the first aspect is used to receive a clock signal, a differential input signal and a setting signal from the sense amplifier circuit, and to latch a target data signal.
  • the latch includes a charge and discharge circuit and a feedback circuit; the charge and discharge circuit receives the clock signal, the differential input signal and the setting signal, and outputs the target data signal; the feedback circuit receives the target data signal and the clock signal, and when the clock signal When inactive, the target data signal is latched.
  • the charge and discharge circuit includes a fifth switch unit, a ninth switch device, a tenth switch device and an eleventh switch device connected in series in sequence; wherein the first end of the fifth switch unit is connected to the power supply, and the second end of the fifth switch unit is connected in series.
  • the terminal is connected to the first terminal of the ninth switching device; the control terminal of the fifth switching unit is used to receive the setting signal; the differential input signal includes the original data signal and the inverted data signal; the control terminal of the ninth switching device is used to receive The inverted data signal; the second end of the ninth switching device is connected to the first end of the tenth switching device; the control end of the tenth switching device is used to receive the clock signal; the second end of the tenth switching device is connected to the first end of the tenth switching device.
  • the first end of the eleventh switching device is connected; the second end of the eleventh switching device is grounded; the control end of the eleventh switching device is used to receive the setting signal; the second end of the fifth switching unit is used to output the target data signal ;
  • the fifth switching unit and the eleventh switching device are configured such that at most one of them is turned on at the same time.
  • the feedback circuit includes a sixth switch unit, a seventh switch unit, a twelfth switch device and an inverter connected in series; the first end of the sixth switch unit is connected to the power supply; the second end of the sixth switch unit is connected to the seventh switch unit.
  • the sixth switching unit and the twelfth switching device are configured such that at most one of them is turned on at the same time.
  • the sensing amplifier circuit and flip-flop proposed in this disclosure can avoid mutual interference of currents on both sides of the differential structure, improve the stability and accuracy of the amplifier output, and when applied to the flip-flop, data sampling is fast and energy consumption is low. Moreover, using the optimized latch of the present disclosure can reduce the number of charging and discharging nodes, further reduce energy consumption and improve efficiency.
  • Figure 1 shows a schematic diagram of the overall structure of a sense amplifier circuit according to an embodiment of the present disclosure
  • Figure 2a shows a schematic circuit structure diagram of a sense amplifier circuit according to an embodiment of the present disclosure
  • Figure 2b shows a schematic circuit structure diagram of the secondary of a flip-flop according to an embodiment of the present disclosure
  • Figure 3a shows a schematic current path diagram of a sensing stage of a sense amplifier circuit according to an embodiment of the present disclosure
  • Figure 3b shows a schematic diagram of the current path in the transition stage of a sense amplifier circuit according to an embodiment of the present disclosure
  • Figure 4 shows a schematic structural diagram of a SAFF according to the prior art
  • Figure 5 shows a schematic structural diagram of a main-stage fast differential sense amplifier of a SAFF according to the prior art
  • Figure 6 shows a schematic structural diagram of a secondary latch of a SAFF according to the prior art
  • Figure 7 shows a signal waveform diagram of a SAFF according to the prior art
  • Figure 8 shows a schematic diagram comparing the setting signal pull-down speed of SAFF according to an embodiment of the present disclosure and SAFF of the prior art
  • FIG. 9 shows a comparison of the mutual current interference effects of a SAFF according to an embodiment of the present disclosure and a SAFF of the prior art.
  • An embodiment of the present disclosure provides a sensing amplifier circuit, including: a charging module and a sensing module.
  • the charging module is configured to charge the setting signal node and the reset signal node according to the clock signal;
  • the sensing module is coupled to the charging module and is configured to sense and amplify the differential input signal according to the clock signal; wherein, sensing
  • the module includes a first amplification circuit, a second amplification circuit, and a cross-jump transfer circuit cross-connected between the first amplification circuit and the second amplification circuit;
  • the cross-jump transfer circuit includes a first transfer circuit and a second transfer circuit;
  • a transfer circuit is used to transfer the effective signal of the second amplification circuit to the first amplification circuit when the induction is completed and the first transition of the differential input signal occurs, so that the setting signal of the setting signal node and the reset signal of the reset signal node are maintained.
  • the setting signal of the setting signal node continues to be discharged through the pull-down path of the induction stage, and the reset signal of the reset signal node continues to be charged through the pull-up path of the charging module; the second transfer circuit is used to complete the sensing and the second jump of the differential input signal occurs
  • the effective signal of the first amplification circuit is transferred to the second amplification circuit, so that the setting signal of the setting signal node and the reset signal of the reset signal node remain unchanged, and the reset signal of the reset signal node continues to be discharged through the pull-down path of the induction stage.
  • the setting signal of the setting signal node continues to be charged through the pull-up path of the charging module.
  • the charging module and the sensing module are connected through the setting signal node and the reset signal node.
  • the first transition refers to the original data signal of the differential input signal transitioning from a valid signal (eg, high level) to an invalid signal (eg, low level).
  • the second transition refers to the transition of the inverted data signal of the differential input signal from a valid signal to an invalid signal.
  • the original data signal and the inverted data signal are a set of complementary signals.
  • the sense amplifier circuit of the embodiment of the present disclosure is implemented as a single-ended high-speed and low-power sense amplifier (Sense Amplifier, SA for short), specifically an improved NMOS (N-Metal-Oxide-Semiconductor) Sensitive amplifier.
  • SA high-speed and low-power sense amplifier
  • NMOS N-Metal-Oxide-Semiconductor
  • the charging module of the sense amplifier circuit includes a first charging circuit and a second charging circuit; the first charging circuit is used to charge the set signal node according to the clock signal (CLK); the second charging circuit The circuit is used to charge the reset signal node according to the clock signal (CLK).
  • the charging module also includes a first signal maintenance circuit and a second signal maintenance circuit.
  • the first signal maintenance circuit is connected in parallel with the first charging circuit, the first signal maintenance circuit is connected to the reset signal node, and the first signal maintenance circuit is used to maintain the set signal state when the induction is completed and the first transition of the differential input signal occurs;
  • the second signal maintenance circuit is connected in parallel with the second charging circuit, and the second signal maintenance circuit is connected to the set signal node. The second signal maintenance circuit is used to maintain the reset signal state when the induction is completed and the differential input signal undergoes a second transition.
  • the sensing module includes two symmetrically coupled amplification circuits, namely a first amplification circuit and a second amplification circuit.
  • the first amplifying circuit includes a first input signal amplifying circuit and a first clock signal sensing amplifying circuit connected in series; the second amplifying circuit includes a second input signal amplifying circuit and a second clock signal sensing amplifying circuit connected in series; the second clock signal
  • the sensing amplifying circuit and the first input signal amplifying circuit are connected through a first transfer circuit; the first clock signal sensing amplifying circuit and the second input signal amplifying circuit are connected through a second transfer circuit.
  • the first input signal amplification circuit and the second input signal amplification circuit are used to receive differential input signals.
  • the differential input signal includes the original data signal (signal D) and the inverted data signal (DB).
  • the inverted data signal is the complementary signal of the original data signal.
  • the first input signal amplification circuit is used to trigger actions in response to the original data signal (signal D).
  • the second input signal amplifier circuit is used to trigger an action in response to the inverted data signal (signal DB, which is the inverted signal of the original data signal).
  • the inverted data signal DB is the inverted signal of the original data signal D. For example, when the original data signal is a high-level signal, the inverted data signal is a low-level signal; when the original data signal is a low-level signal, the inverted data signal is a high-level signal.
  • the circuit operating in response to the corresponding signal means that the switching device or switching unit in the circuit is turned on or off in response to the specified electrical signal. For example, when the specified electrical signal is a valid signal, the corresponding switching device or switching unit is turned on. For example, for a high-level triggered switching unit or switching device, when a high-level signal is received, it is triggered to conduct. Then the high-level signal is a valid signal for the switching unit or switching device.
  • the first amplification circuit also includes a first ground amplification circuit; wherein the first input signal amplification circuit, the first clock signal sensing amplification circuit and the first ground amplification circuit are connected in series in sequence, and the first end of the first input signal amplification circuit is connected to the set The signal node is connected, the second end of the first input signal amplifying circuit is connected to the first end of the first clock signal sensing amplifying circuit, the second end of the first clock signal sensing amplifying circuit is connected to the second end of the first grounded amplifying circuit.
  • the second amplifying circuit also includes a second grounded amplifying circuit ;
  • the second input signal amplification circuit, the second clock signal sensing amplification circuit and the second ground amplification circuit are connected in series in sequence; the second end of the second input signal amplification circuit is connected to the set signal node, and the second input signal amplification circuit is The second terminal is connected to the first terminal of the second clock signal sensing amplifier circuit.
  • the second terminal of the second clock signal sensing amplifier circuit is connected to the second terminal of the first grounded amplifier circuit.
  • the second terminal of the second grounded amplifier circuit is connected to the first terminal of the second clock signal sensing amplifier circuit.
  • the control terminal of the second grounded amplifier circuit is connected to the setting signal node, and is used to turn on or off under the action of the setting signal.
  • the first amplifying circuit receives the original data signal and is used to conduct during the sensing stage and pull down the setting signal to a low level through the first pull-down path.
  • the second amplifier circuit receives the inverted data signal and is used to conduct during the sensing phase and pull the reset signal down to a low level through the second pull-down path.
  • the first charging circuit, the first input signal amplifying circuit, the first clock signal sensing amplifying circuit and the first ground amplifying circuit are connected in series in sequence;
  • the circuit and the second grounded amplifier circuit are connected in series in turn.
  • the cross-hopping transfer branch can always discharge (pull-down) through the original pull-down path during the transition process of the setting signal or the reset signal, which has high efficiency, low power consumption, and can avoid differential input. Error output caused by signal transition.
  • the completion of the sensing phase means that when the original data signal is high level, the setting signal has been pulled down to low level, that is, a logic "0" signal, and the reset signal has been pulled up to a high level, that is, a logic "1” signal; or , when the original data signal is low level, the setting signal has been pulled up to high level, which is a logic "1” signal, and the reset signal has been pulled down to a low level, which is a logic "0" signal.
  • the first drop-down path and the second drop-down path will be described in detail below.
  • the first input signal amplifying circuit and the first clock signal sensing amplifying circuit are connected through a first node (node A); the second input signal amplifying circuit and the second clock signal sensing amplifying circuit are connected through a second node (node A). B) connection; the first clock signal sensing amplifier circuit and the first ground amplifier circuit are connected through the third node (node C); the second clock signal sensing amplifier circuit and the second ground amplifier circuit are connected through the fourth node (Node D) connection.
  • the first terminals of the first charging circuit and the second charging circuit are both connected to the power supply; the second terminal of the first charging circuit is connected to the sensing module by setting a signal node; the second terminal of the second charging circuit is connected to the sensing module. are connected through the reset signal node.
  • the first charging circuit and the first input signal amplifying circuit are connected through a setting signal node (SB node, used to collect the setting signal); the second charging circuit and the second input signal amplifying circuit are connected through a reset signal node (RB node, used to collect reset signals) connection.
  • the first grounded amplifier circuit and the second grounded amplifier circuit are both grounded through the grounding point.
  • a first pull-down path for pulling down the setting signal is formed; the conduction between the reset signal node, the second node, the fourth node and the ground point is formed.
  • a second pull-down path is formed for the pull-down reset signal.
  • the first clock signal sensing amplifier circuit and the second clock signal sensing amplifier circuit are respectively used to receive the clock signal and are turned on when the clock signal is at a high level.
  • the first grounded amplifying circuit and the second grounded amplifying circuit are both high-level trigger circuits, that is, triggering an action when a high level is collected.
  • the triggering action in the embodiment of the present disclosure includes turning on the switching device (or switching unit) in the circuit.
  • the cross-jump transfer circuit is used to transfer the effective signal of the amplifier circuit that is turned on when the differential input signal jumps after the sensing stage is completed to another amplifier circuit that is turned on before the differential input signal jumps (in the sensing stage).
  • the amplifier circuit (the first amplifier circuit or the second amplifier circuit) that is turned on during the sensing stage will be temporarily disconnected, and the other amplifier circuit is triggered to turn on when the differential input signal jumps.
  • the amplification circuit that was turned on in the sensing stage can be turned on again through the cross-jump transfer branch, thereby continuing to pull down the signal (setting signal or reset signal) through the original pull-down path in the sensing stage.
  • the first transfer circuit is connected in parallel with the first input signal amplification circuit.
  • the first end of the first transfer circuit and the first end of the first input signal amplification circuit are both connected to a signal node.
  • the second end of the first transfer circuit is connected to the first input signal
  • the second terminals of the amplifier circuit are both connected to the first terminal of the first clock signal sensing amplifier circuit;
  • the control terminal of the first transfer circuit is connected to the second terminal of the second clock signal sensing amplifier circuit;
  • the signal amplifier circuit is connected in parallel, the first end of the second transfer circuit and the first end of the second input signal amplification circuit are both connected to the reset signal node, and the second end of the second transfer circuit and the second end of the second input signal amplification circuit are both connected
  • the control terminal of the second transfer circuit is connected to the second terminal of the first clock signal sensing amplifier circuit.
  • the first transfer circuit is used to transfer the effective signal of the second amplification circuit to the first amplification circuit when the sensing is completed and the differential input signal transitions, so that the setting signal continues to be discharged through the pull-down path of the sensing stage.
  • the second transfer circuit is used to transfer the signal when the sensing is completed and the differential input signal jumps.
  • the effective signal of the first amplifier circuit is transferred to the second amplifier circuit, so that the reset signal continues to be amplified through the pull-down path of the sensing stage (in the sensing stage, if the original data signal is low level, the reset signal passes through the second pull-down path of the second amplifier circuit discharge, that is, pull down).
  • the cross-jump transfer circuit allows that when the differential input signal (such as the original data signal) transitions after the sensing phase is completed, it is still discharged through the pull-down path of the data signal sensing phase.
  • the pull-down speed is fast, avoiding differential input signal jump interference, and has high safety and efficiency.
  • the charging module includes a first charging circuit and a first signal maintaining circuit connected in parallel, and a second charging circuit and a second signal maintaining circuit connected in parallel.
  • the first charging circuit includes a first switch unit, and the first signal maintaining circuit includes a second switch unit; the first switch unit and the second switch unit are connected in parallel; the first end of the first switch unit is connected to the power supply, and the second end is connected to the set signal node ; The first end of the second switch unit is connected to the power supply, and the second end is connected to the setting signal node; the control end of the first switch unit is used to receive the clock signal; the control end of the second switch unit is used to receive the reset signal of the reset signal node;
  • the second charging circuit includes a fourth switch unit; the second signal maintaining circuit includes a third switch unit; the third switch unit is connected in parallel with the fourth switch unit; the first end of the third switch unit is connected to the power supply, and the second end is connected to the set signal node ; The first end of the fourth switch unit is connected to the power supply
  • the switch unit (such as the first switch unit, the second switch unit, etc.) can select a low-level trigger electronic device. In other embodiments, the switch unit (such as a first switch unit, a second switch unit, etc.) can also select a high-level trigger electronic device and a reverse It is realized by combining the director.
  • the first charging circuit includes a first PMOS transistor P1, the first signal maintaining circuit includes a second PMOS transistor P2; the second charging circuit includes a third PMOS transistor P3, and the second signal maintaining circuit includes a fourth PMOS transistor P4.
  • the sources of P1, P2, P3, and P4 are all connected to the power supply.
  • the gates of P1 and P4 are used to receive the clock signal (CLK).
  • the drains of P1 and P2 are connected to form the first signal node, which is the setting signal node.
  • the drains of P3 and P4 are connected to form the second signal node, which is the reset signal node.
  • the drains of P1 and P2, which set the signal node are also connected to the gate of P3.
  • the drains of P3 and P4, that is, the reset signal node are also connected to the gate of P2.
  • the first input signal amplification circuit includes a first switching device; the first transfer circuit includes a seventh switching device; the first end of the first switching device and the first end of the seventh switching device are both connected to the set signal node; The second end of the first switching device and the second end of the seventh switching device are both connected to the first end (first node) of the first clock signal sensing amplifier circuit; the control end of the seventh switching device Connect the second end (fourth node) of the second clock signal sensing amplification circuit; the second input signal amplification circuit includes a second switching device; the second transfer circuit includes an eighth switching device; the first end of the second switching device and The first end of the eighth switching device is connected to the reset signal node; the second end of the second switching device and the second end of the eighth switching device are both connected to the third end of the second clock signal sensing amplifier circuit.
  • One end (second node); the control end of the eighth switching device is connected to the second end (third node) of the first clock signal sensing amplifier circuit; the control end of the first switching device is used to receive the original data signal; The control end of the second switching device is used to receive an inverted data signal.
  • the switching device (such as the first switching device, the seventh switching device, etc.) can be a high-level triggering electronic device. In other embodiments, a low-level triggering electronic device and an inverse switching device can also be selected. It is realized by combining the director. The embodiments of the present disclosure place no restrictions on device selection.
  • the first clock signal sensing amplifier circuit includes a third switching device; the first terminal of the third switching device is connected to the second terminal (first node) of the first switching device; the second terminal of the third switching device is connected to the first ground amplifier The first end (third node) of the circuit; the control end of the third switching device is used to receive the clock signal; the second clock signal sensing amplifier circuit includes a fourth switching device; the first end of the fourth switching device is connected to the second switch The second end of the device (second node); the second end of the fourth switching device is connected to the second end (fourth node) of the second grounded amplifier circuit; the control end of the fourth switching device is used to receive a clock signal.
  • the first clock signal sensing amplifier circuit includes a third NMOS transistor N3 (N-Metal-Oxide-Semiconductor).
  • the gate of N3 is used to receive the clock signal and is turned on when the clock signal is high level.
  • the drain of N3 is connected to the first node (node A).
  • the drain of N3 is connected to the source of N1 to form the first node (node A).
  • the source of N3 is connected to the third node (node C).
  • the second clock signal sensing amplifier circuit includes a fourth NMOS transistor N4.
  • the gate of N4 is used to receive the clock signal and is turned on when the clock signal is high level.
  • the drain of N4 is connected to the second node (node B).
  • the drain of N4 is connected to the source of N2 to form the second node (node B).
  • the source of N4 is connected to the fourth node (node D).
  • the first input signal amplification circuit includes a first NMOS transistor N1, and the first transfer circuit includes a seventh NMOS transistor N7.
  • the gate of N1 is used to receive the original data signal (D).
  • the drain of N1 is connected to the drain of P1 (and P2), which is the set signal node.
  • the source of N1 is connected to the first node (node A).
  • the drain of N7 is connected to the drain of N1, and the source of N7 is connected to the source of N1.
  • the second input signal amplification circuit includes a second NMOS transistor N2, and the second transfer circuit includes an eighth NMOS transistor N8.
  • the gate of N2 is used to receive the inverted data signal DB.
  • the drain of N2 is connected to the drain of P3 (and P4), which is the reset signal node.
  • the source of N2 is connected to the second node (node B).
  • the drain of N8 is connected to the drain of N2, and the source of N8 is connected to the source of N2.
  • the gate of N7 is connected to the source of N4.
  • the gate of N8 is connected to the source of N3.
  • the first grounded amplifier circuit includes a fifth switching device; the first end of the fifth switching device is connected to the second end (third node) of the third switching device; the second end of the fifth switching device is grounded; The control end is used to receive the reset signal of the reset signal node; the second ground amplifier circuit includes a sixth switching device; the first end of the sixth switching device is connected to the second end (third node) of the fourth switching device; the sixth The second terminal of the switching device is grounded; the control terminal of the sixth switching device is used to receive the setting signal of the setting signal node.
  • the first grounded amplification circuit includes a fifth NMOS transistor N5.
  • the gate of N5 is connected to the reset signal node (RB).
  • the drain of N5 is connected to the third node (node C).
  • the source of N5 is connected to ground.
  • the second ground amplification circuit includes a sixth NMOS transistor N6.
  • the gate connection of N6 sets the signal node (SB).
  • the drain of N6 is connected to the fourth node (node C).
  • the source of N6 is connected to ground.
  • Embodiments of the present disclosure also provide a flip-flop based on a sense amplifier circuit.
  • the above-mentioned improved main-stage flip-flop of the sense amplifier is used to sample the data on the rising edge of the clock signal, and then the data is latched through the latch, and is applied to the rising edge of the high-speed circuit system. along the sampled data.
  • the latch is used to receive the clock signal, the differential input signal and the setting signal from the sense amplifier circuit, and latch the target data signal.
  • the structure of the latch according to the embodiment of the present disclosure is exemplarily described below.
  • the slave-stage latch is an SR latch, including a charge-discharge circuit and a feedback circuit.
  • the charge and discharge circuit and the feedback circuit are coupled.
  • the charge and discharge circuit receives the clock signal, the differential input signal and the setting signal, and outputs the target data signal;
  • the feedback circuit receives the target data signal and the clock signal, and latches the target data signal when the clock signal is invalid.
  • the charging and discharging circuit includes a fifth switching unit, a ninth switching device, a tenth switching device and an eleventh switching device connected in series; wherein, the first end of the fifth switching unit is connected to the power supply, and the second end of the fifth switching unit is connected to the power supply.
  • the first end of the ninth switching device is connected; the control end of the fifth switching unit is used to receive the setting signal; the differential input signal includes the original data signal and the inverted data signal; the control end of the ninth switching device is used to receive the inverted data signal ;
  • the second end of the ninth switching device is connected to the first end of the tenth switching device; the control end of the tenth switching device is used to receive the clock signal; the second end of the tenth switching device is connected to the first end of the eleventh switching device terminal is connected; the second terminal of the eleventh switching device is grounded; the control terminal of the eleventh switching device is used to receive the setting signal; the second terminal of the fifth switching unit is used for the target data signal.
  • the fifth switching unit and the eleventh switching device are configured not to be turned on at the same time, that is, at most one of them is turned on at the same time.
  • the charge and discharge circuit includes a fifth PMOS transistor P5, a ninth NMOS transistor N9, a tenth NMOS transistor N10, and an eleventh NMOS transistor N11 connected in series in sequence.
  • the source of P5 is connected to the power supply
  • the drain of P5 is connected to the drain of N9
  • the gate of P5 is used to receive the setting signal (SB).
  • the source of N9 is connected to the drain of N10, and the gate of N9 is used to collect the inverted data signal (DB).
  • the source of N10 is connected to the drain of N11, and the gate of N10 is used to collect the clock signal (CLK).
  • the source of N11 is grounded, and the gate of N11 is used to collect the setting signal (SB).
  • the connection point between the drain of P5 and the drain of N9 is used as the output sampling point for collecting the target data signal Q.
  • the feedback circuit includes a sixth switch unit, a seventh switch unit, a twelfth switch device and an inverter connected in series; the first end of the sixth switch unit is connected to the power supply; the second end of the sixth switch unit is connected to the seventh switch unit The first end of the inverter; the input end of the inverter is used to receive the target data signal, and the output end of the inverter is connected to the control end of the sixth switch unit; the output end of the inverter is used to output the inverted signal of the target data signal; The second end of the seventh switching unit is connected to the first end of the twelfth switching device; the control end of the seventh switching unit is used to receive the clock signal; the second end of the twelfth switching device is connected to the second end of the tenth switching device connection; the control end of the twelfth switching device is connected to the output end of the inverter; the second end of the seventh switching unit is connected to the first end of the twelfth switching device.
  • the sixth switching unit
  • the feedback circuit includes a sixth PMOS transistor P6, a seventh PMOS transistor P7, and a twelfth NMOS transistor N12.
  • the source of P6 is connected to the power supply, and the drain of P6 is connected to the source of P7.
  • the gate of P6 is connected to the charge and discharge circuit through an inverter.
  • the input terminal of the inverter (INV1) is connected to the output sampling point, and the output terminal of the inverter is connected to the gate of P6.
  • the drain of P7 is connected to the drain of N12, and the gate of P7 is used to receive the clock signal (CLK).
  • the source of N12 is connected to the source of N10, and the gate of N12 is connected to the output terminal of the inverter.
  • the output terminal of the inverter is used to output the inverted signal of the target data signal Q.
  • the connection between P7 and N12 forms the sixth node, and the sixth node is connected to the output sampling point.
  • the slave-level latch exchanges the positions of the transistors controlled by DB and CLK, avoiding node charging and discharging between the two tubes, and further optimizing power consumption.
  • Sensing stage The sensitive amplifier collects the rising edge of the clock signal, that is, when the clock signal jumps from low level to high level, it enters the sensing stage. At this time, if the original data signal is high level, the setting signal (SB) is pulled down to low level through the first amplification circuit. Exemplarily, the set signal (SB) is pulled down to a low level through the first pull-down path.
  • the first pull-down path is to set the signal path from the signal node, the first node, the third node to the ground point. As shown in FIG. 3a, the first pull-down path is formed by the first input signal amplification circuit, the first clock signal sensing amplification circuit and the first ground amplification circuit in the first amplification circuit.
  • Transition stage After the sensing stage, when the clock signal continues to be at a high level and the data signal jumps to a low level, the first pull-down path is temporarily disconnected and the second amplification circuit is partially turned on (including the second input signal amplification circuit and The second clock signal sensing amplifier circuit) forms an effective signal, which is transferred to the first amplifier circuit through the first transfer circuit, and the first pull-down path is turned on again.
  • the set signal continues to discharge through the first pull-down path of low potential, and the discharge speed is fast.
  • N2 and N4 are turned on, and node D is charged to 1, causing N7 to turn on.
  • the drop-down paths of the SB nodes are N7, N3, and N5.
  • the N8 opening process is the same. In other scenarios, the charging stage is consistent with the above.
  • the circuit action mode is symmetrical to the above process, as follows.
  • the sensitive amplifier collects the rising edge of the clock signal, that is, when the clock signal jumps from low level to high level, it enters the sensing stage. At this time, if the original data signal is low level, the reset signal (RB) is pulled down to low level through the second amplification circuit. Exemplarily, the reset signal (RB) is pulled down to a low level through the second pull-down path.
  • the second pull-down path is the signal path from the reset signal node, the second node, the fourth node to the ground point.
  • the second pull-down path is formed by the second input signal amplifying circuit, the second clock signal sensing amplifying circuit and the second ground amplifying circuit in the second amplifying circuit.
  • the inverted data signal DB is 1
  • the RB node ie, the reset signal node
  • N2 is pulled down to 0 by N2, N4, and N6, then P2 is turned on, and SB maintains the original 1.
  • the second pull-down path is temporarily disconnected, and the first The amplifying circuit is partially turned on (including the first input signal amplifying circuit and the first clock signal sensing amplifying circuit being turned on), forming an effective signal, and the effective signal (such as the high level that turns on the circuit) is turned on through the second transfer circuit. signal) is transferred to the second amplification circuit, and the second pull-down path is turned on again.
  • the reset signal continues to discharge through the second pull-down path of low potential, and the discharge speed is fast.
  • N1 and N3 are turned on, and node C is charged to 1, causing N8 to turn on.
  • the drop-down paths of the RB nodes are N8, N4, and N6.
  • the flip-flop implemented using the sensitive amplifier of the embodiment of the present disclosure can reduce power consumption, and has faster data capture speed and higher accuracy.
  • the feedback circuit can latch the last data when the clock signal is low.
  • the flip-flop implemented using the latch in the embodiment of the present disclosure reduces the number of charging and discharging nodes and reduces energy consumption.
  • the sense amplifier circuit and flip-flop of the present disclosure can be applied to high-speed circuit systems to implement data sampling on the rising edge of the clock.
  • the following takes an amplifier circuit in the prior art as an example to compare and describe the technical effects of the sense amplifier circuit in the embodiment of the present disclosure, but does not limit the usage scenarios of the sense amplifier circuit in the embodiment of the present disclosure.
  • FIG 4 shows the structure diagram of SAFF (sense-amplifier-based flip-flop, sense amplifier flip-flop) proposed by Heng You et al.
  • SAFF sense-amplifier-based flip-flop, sense amplifier flip-flop
  • the output Q is pulled up to 1 by MP5; if D is low level, RN is discharged to a low level, the output Q is pulled down to 0 by MN8, MN9, MN11, Feedback inverter (feedback inverter) and INV1 can be in CLK When it is low level, the last data is latched.
  • the SAFF structure mainly has the following problems:
  • the main stage SA and differential circuits have an asymmetric structure on both sides. Because the SAFF slave stage only uses the SN signal, the pull-up path and pull-down path of SN in the left box are larger than the RN in the right box. The tube sizes in the pull-up path and pull-down path are larger to improve the driving capability of the SN node.
  • the trigger SAFF of the disclosed embodiment is used to complete the measurement of the delay and power consumption on the HSPICE software.
  • the flip-flop of the embodiment of the present disclosure is faster on the rising and falling edges of the level transition of the signal Q and has lower power consumption.
  • the sensing phase SB of the SAFF of the improved embodiment of the present disclosure can capture input data faster at the rising edge of CLK.
  • the improved SAFF pull-down delay from sensing data to low level is shorter than the Heng You SAFF pull-down delay from sensing data to low level, and the sensing delay is optimized by 21.6%.
  • the sensing amplifier circuit and trigger provided by the embodiments of the present disclosure can avoid mutual interference of currents on both sides of the differential structure and improve the stability and accuracy of the amplifier output.
  • data sampling is fast and energy consumption is high. Low.
  • using the optimized latch of the present disclosure can reduce the number of charging and discharging nodes, further reduce energy consumption and improve efficiency.

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Abstract

本公开提供一种感测放大器电路及触发器，其中，感测放大器电路，包括：充电模块，被配置为根据时钟信号，对设置信号节点和复位信号节点进行充电；感测模块，被配置为根据时钟信号，感测并放大差分输入信号；其中，感测模块包括第一放大电路、第二放大电路、交叉连接在第一放大电路和第二放大电路之间的交叉跳变转移电路。交叉跳变转移电路用于在感应完成、差分输入信号发生跳变时，将一个新出发的放大电路的有效信号转移到另一个放大电路，使得设置信号/复位信号维持不变。

Description

一种感测放大器电路及触发器
本公开基于申请号为202210813423.X、申请日为2022年07月11日、申请名称为“一种感测放大器电路及触发器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种感测放大器电路及触发器。
背景技术
触发器(Flip-Flop)，简称FF是构成数字系统，如高速电路系统的基本逻辑单元电路之一。触发器(Flip-Flop)，简称FF是构成数字系统基本逻辑单元电路之一。其具有触发翻转特性，在输入信号的作用下，能够在两个稳定状态之间互相转换。触发器的性能对数字系统特别是高速数字系统的性能具有重要的影响。
现有触发器的类型多样，各有特点。
传输门触发器(Transmission Gate Flip-Flop，TGFF)作为主从式双相时钟触发器的一种，其由对低电平敏感的主级锁存器和对高电平敏感的从级锁存器前后相连组成，如果建立时间不够，那么数据将不能在时钟信号CLK上升沿被触发器稳定地锁存。
脉冲触发器(Pulse Triggered Flip Flop，PTFF)很好地改善了TGFF建立时间较大的缺点，但需要额外电路产生时钟树，增加了功耗和面积开销。
半动态触发器(Semi-Dynamic Flip-Flop，SDFF)虽然具有较短的D-Q延迟，但它不具备容时钟偏斜和时间借用的能力。
基于灵敏放大器的触发器由快速差分灵敏放大器的主级和SR锁存器的从级组成，具有较小的建立时间和保持时间，相对不受上述问题的困扰，是一种适用于低供电电压的解决方案。现有技术中差分灵敏放大器存在充放电节点多、容易导致数据采集错误的问题。
因此，亟需一种灵敏度高、稳定性强且功耗低的触发器。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种感测放大器电路及触发器。
本公开的第一方面提供了一种感测放大器电路，包括：
充电模块，被配置为根据时钟信号，对设置信号节点和复位信号节点进行充电；感测模块，与所述充电模块耦接，被配置为根据时钟信号，感测并放大差分输入信号；其中，感测模块包括第一放大电路、第二放大电路、交叉连接在第一放大电路和第二放大电路之间的交叉跳变转移电路；所述交叉跳变转移电路包括第一转移电路和第二转移电路；第一转移电路用于在感应完成、差分输入信号发生第一跳变时，将第二放大电路的有效信号转移到第一放大电路，使得设置信号节点的设置信号和复位信号节点的复位信号维持不变；第二转移电路用于在感应完成、差分输入信号发生第二跳变时，将第一放大电路的有效信号转移到第二放大电路，使得设置信号节点的设置信号和复位信号节点的复位信号维持不变。
其中，所述第一放大电路包括串联的第一输入信号放大电路和第一时钟信号感测放大电路；所述第二放大电路包括串联的第二输入信号放大电路和第二时钟信号感测放大电路；所述第二时钟信号感测放大电路与所述第一输入信号放大电路通过第一转移电路连接；所述第一时钟信号感测放大电路与所述第二输入信号放大电路通过第二转移电路 连接。
其中，第一转移电路与第一输入信号放大电路并联，第一转移电路的第一端和第一输入信号放大电路的第一端均连接设置信号节点，第一转移电路第二端和第一输入信号放大电路的第二端均连接第一时钟信号感测放大电路的第一端；第一转移电路的控制端连接第二时钟信号感测放大电路的第二端；第二转移电路与第二输入信号放大电路并联，第二转移电路的第一端和第二输入信号放大电路的第一端均连接复位信号节点，第二转移电路第二端和第二输入信号放大电路的第二端均连接第二时钟信号感测放大电路的第一端；第二转移电路的控制端连接第一时钟信号感测放大电路的第二端。
其中，所述差分输入信号包括原始数据信号和反相数据信号；第一放大电路接收原始数据信号，用于在感应阶段导通，将设置信号通过第一下拉路径下拉为低电平；第二放大电路接收反相数据信号，用于在感应阶段导通，将复位信号通过第二下拉路径下拉为低电平。
其中，第一放大电路还包括第一接地放大电路；其中，第一输入信号放大电路、第一时钟信号感测放大电路和第一接地放大电路依次串联，第一输入信号放大电路的第一端与设置信号节点连接，第一接地放大电路的第二端接地；第一接地放大电路的控制端与复位信号节点连接，用于在复位信号的作用下导通或关断；第二放大电路还包括第二接地放大电路；其中，第二输入信号放大电路、第二时钟信号感测放大电路和第二接地放大电路依次串联，第二输入信号放大电路的第一端与复位信号节点连接，第二接地放大电路的第二端接地；第二接地放大电路的控制端与设置信号节点连接，用于在设置信号的作用下导通或关断。
其中，充电模块包括第一充电电路和第二充电电路；第一充电电路用于根据时钟信号，对设置信号节点进行充电；第二充电电路用于根据时钟信号，对复位信号节点进行充电；第一充电电路与第二充电电路的第一端均连接电源；第一充电电路的第二端和感测模块之间通过设置信号节点连接；第二充电电路的第二端和感测模块之间通过复位信号节点连接。
其中，充电模块还包括第一信号维持电路和第二信号维持电路；第一信号维持电路与所述第一充电电路并联，第一信号维持电路与复位信号节点连接；第二信号维持电路与所述第二充电电路并联，第二信号维持电路与设置信号节点连接；第一信号维持电路用于在感应完成、差分输入信号发生第二跳变时，维持设置信号状态；第二信号维持电路用于在感应完成、差分输入信号发生第一跳变时，维持复位信号状态。
其中，第一充电电路包括第一开关单元，第一信号维持电路包括第二开关单元；第一开关单元与第二开关单元并联；第一开关单元的第一端连接电源，第二端连接设置信号节点；第二开关单元的第一端连接电源，第二端连接设置信号节点；第一开关单元的控制端用于接收时钟信号；第二开关单元的控制端用于接收复位信号节点的复位信号；第二充电电路包括第四开关单元；第二信号维持电路包括第三开关单元；第三开关单元与第四开关单元并联；第三开关单元的第一端连接电源，第二端连接设置信号节点；第四开关单元的第一端连接电源，第二端连接设置信号节点；第四开关单元的控制端用于接收时钟信号；第三开关单元的控制端用于接收设置信号节点的设置信号。
其中，所述第一输入信号放大电路包括第一开关器件；第一转移电路包括第七开关器件；所述第一开关器件的第一端和所述第七开关器件的第一端均与设置信号节点连接；所述第一开关器件的第二端和所述第七开关器件的第二端均连接所述第一时钟信号感测放大电路的第一端；第七开关器件的控制端连接第二时钟信号感测放大电路的第二端；所述第二输入信号放大电路包括第二开关器件；第二转移电路包括第八开关器件；所述第二开关器件的第一端和所述第八开关器件的第一端均与复位信号节点连接；所述第二开关器件的第二端和所述第八开关器件的第二端均连接所述第二时钟信号感测放大 电路的第一端；第八开关器件的控制端连接第一时钟信号感测放大电路的第二端；所述第一开关器件的控制端用于接收原始数据信号；所述第二开关器件的控制端用于接收反相数据信号。
其中，第一时钟信号感测放大电路包括第三开关器件；第三开关器件的第一端连接所述第一开关器件的第二端；第三开关器件的第二端连接所述第一接地放大电路的第一端；第三开关器件的控制端用于接收时钟信号；第二时钟信号感测放大电路包括第四开关器件；第四开关器件的第一端连接所述第二开关器件的第二端；第四开关器件的第二端连接所述第二接地放大电路的第二端；第四开关器件的控制端用于接收时钟信号。
其中，第一接地放大电路包括第五开关器件；第五开关器件的第一端与第三开关器件的第二端连接；第五开关器件的第二端接地；第五开关器件的控制端用于接收复位信号节点的复位信号；第二接地放大电路包括第六开关器件；第六开关器件的第一端与第四开关器件的第二端连接；第六开关器件的第二端接地；第六开关器件的控制端用于接收设置信号节点的设置信号。
本公开的第二方面提供了一种触发器，包括：
上述第一方面所述的感测放大器电路和锁存器；所述锁存器用于从所述感测放大器电路接收时钟信号、差分输入信号和设置信号，并锁存目标数据信号。
其中，所述锁存器包括充放电电路和反馈电路；充放电电路接收时钟信号、差分输入信号和设置信号，输出目标数据信号；反馈电路，接收所述目标数据信号和时钟信号，在时钟信号无效时，锁存目标数据信号。
其中，充放电电路包括依次串联的第五开关单元、第九开关器件、第十开关器件和第十一开关器件；其中，第五开关单元的第一端与电源连接，第五开关单元第二端与第九开关器件的第一端连接；第五开关单元的控制端用于接收设置信号；所述差分输入信号包括原始数据信号和反相数据信号；第九开关器件的控制端用于接收所述反相数据信号；所述第九开关器件的第二端与第十开关器件的第一端连接；第十开关器件的控制端用于接收时钟信号；第十开关器件的第二端与第十一开关器件的第一端连接；第十一开关器件的第二端接地；第十一开关器件的控制端用于接收设置信号；第五开关单元的第二端用于输出目标数据信号；第五开关单元和第十一开关器件被配置为在同一时间最多只有其中一个导通。
其中，反馈电路包括依次串联的第六开关单元、第七开关单元、第十二开关器件和反向器；第六开关单元的第一端连接电源；第六开关单元的第二端连接第七开关单元的第一端；反向器的输入端接收目标数据信号，反向器的输出端连接第六开关单元的控制端；第七开关单元的第二端连接第十二开关器件的第一端；第七开关单元的控制端用于接收时钟信号；第十二开关器件的第二端连接第十开关单元的第二端；第十二开关器件的控制端与反向器的输出端连接；第六开关单元和第十二开关器件被配置为在同一时间最多只有其中一个导通。
本公开提出的感测放大器电路及触发器能够避免差分结构两侧的电流相互干扰，提高放大器输出的稳定性和准确性，应用在触发器时，数据采样快，耗能低。而且，采用本公开优化的锁存器，能够减少充放电节点数量，进一步降低耗能、提高效率。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1示出了根据本公开实施例的一种感测放大器电路的整体结构示意图；
图2a示出了根据本公开实施例的一种感测放大器电路的电路结构示意图；
图2b示出了根据本公开实施例的一种触发器的次级的电路结构示意图；
图3a示出了根据本公开实施例的一种感测放大器电路的感应阶段的电流通路示意图；
图3b示出了根据本公开实施例的一种感测放大器电路的跳变阶段的电流通路示意图；
图4示出了根据现有技术的一种SAFF结构示意图；
图5示出了根据现有技术的一种SAFF的主级快速差分灵敏放大器的结构示意图；
图6示出了根据现有技术的一种SAFF的次级锁存器的结构示意图；
图7示出了根据现有技术的一种SAFF的信号波形图；
图8示出了根据本公开实施例的SAFF与现有技术的SAFF的设置信号下拉速度对比示意图；
图9示出了根据本公开实施例的SAFF与现有技术的SAFF的电流相互干扰效果对比示意。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开实施例提供一种感测放大器电路，包括：充电模块和感测模块。充电模块，被配置为根据时钟信号，对设置信号节点和复位信号节点进行充电；感测模块，与充电模块耦接，被配置为根据时钟信号，感测并放大差分输入信号；其中，感测模块包括第一放大电路、第二放大电路、交叉连接在第一放大电路和第二放大电路之间的交叉跳变转移电路；交叉跳变转移电路包括第一转移电路和第二转移电路；第一转移电路用于在感应完成、差分输入信号发生第一跳变时，将第二放大电路的有效信号转移到第一放大电路，使得设置信号节点的设置信号和复位信号节点的复位信号维持不变，设置信号节点的设置信号继续通过感应阶段的下拉路径放电，复位信号节点的复位信号继续通过充电模块的上拉路径充电；第二转移电路用于在感应完成、差分输入信号发生第二跳变时，将第一放大电路的有效信号转移到第二放大电路，使得设置信号节点的设置信号和复位信号节点的复位信号维持不变，复位信号节点的复位信号继续通过感应阶段的下拉路径放电，设置信号节点的设置信号继续通过充电模块的上拉路径充电。充电模块和感测模块通过设置信号节点和复位信号节点连接。
示例性地，第一跳变是指差分输入信号的原始数据信号从有效信号(如高电平)跳变为无效信号(如低电平)。第二跳变是指差分输入信号的反相数据信号从有效信号跳变为无效信号。其中，原始数据信号和反相数据信号为一组互补的信号。
示例性地，本公开实施例的感测放大器电路实现为一种单端型高速低功耗灵敏放大器(Sense Amplifier，简称SA)，具体为一种改进的NMOS(N-Metal-Oxide-Semiconductor)灵敏放大器。下面对感测放大器电路的模块结构以及相应的工作过程进行详细说明。
如图1、图2a所示，感测放大器电路的充电模块包括第一充电电路和第二充电电路；第一充电电路用于根据时钟信号(CLK)，对设置信号节点进行充电；第二充电电路用于根据时钟信号(CLK)，对复位信号节点进行充电。
充电模块还包括第一信号维持电路和第二信号维持电路。第一信号维持电路与第一充 电电路并联，第一信号维持电路与复位信号节点连接，第一信号维持电路用于在感应完成、差分输入信号发生第一跳变时，维持设置信号状态；第二信号维持电路与第二充电电路并联，第二信号维持电路与设置信号节点连接，第二信号维持电路用于在感应完成、差分输入信号发生第二跳变时，维持复位信号状态。
如图1、图2a所示，感测模块包括对称耦合的两个放大电路，分别为第一放大电路和第二放大电路。
第一放大电路包括串联的第一输入信号放大电路和第一时钟信号感测放大电路；第二放大电路包括串联的第二输入信号放大电路和第二时钟信号感测放大电路；第二时钟信号感测放大电路与第一输入信号放大电路通过第一转移电路连接；第一时钟信号感测放大电路与第二输入信号放大电路通过第二转移电路连接。第一输入信号放大电路与第二输入信号放大电路用于接收差分输入信号。
差分输入信号包括原始数据信号(信号D)和反相数据信号(DB)，反相数据信号为原始数据信号的互补信号。不失一般性地，第一输入信号放大电路用于响应原始数据信号(信号D)而触发动作。第二输入信号放大电路用于响应反相数据信号(信号DB，为原始数据信号的反向信号)而触发动作。其中，反相数据信号DB为原始数据信号D的反相信号。例如，原始数据信号为高电平信号时，反相数据信号为低电平信号；原始数据信号为低电平信号时，反相数据信号为高电平信号。
本公开实施例中，电路响应于相应的信号而动作是指：电路中的开关器件或开关单元响应于指定的电信号而导通或关断。示例性地，当指定的电信号为有效信号时，相应的开关器件或开关单元导通。例如，对于高电平触发的开关单元或开关器件，当接收到高电平信号时，被触发导通。则高电平信号对于该开关单元或开关器件为有效信号。
第一放大电路还包括第一接地放大电路；其中，第一输入信号放大电路、第一时钟信号感测放大电路和第一接地放大电路依次串联，第一输入信号放大电路的第一端与设置信号节点连接，第一输入信号放大电路的第二端与第一时钟信号感测放大电路的第一端连接，第一时钟信号感测放大电路的第二端与第一接地放大电路的第二端连接，第一接地放大电路的第二端接地；第一接地放大电路与复位信号节点连接，用于在复位信号的作用下导通或关断；第二放大电路还包括第二接地放大电路；其中，第二输入信号放大电路、第二时钟信号感测放大电路和第二接地放大电路依次串联；第二输入信号放大电路的第二端与设置信号节点连接，第二输入信号放大电路的第二端与第二时钟信号感测放大电路的第一端连接，第二时钟信号感测放大电路的第二端与第一接地放大电路的第二端连接，第二接地放大电路的第二端接地；第二接地放大电路的控制端与设置信号节点连接，用于在设置信号的作用下导通或关断。
第一放大电路接收原始数据信号，用于在感应阶段导通，将设置信号通过第一下拉路径下拉为低电平。第二放大电路接收反相数据信号，用于在感应阶段导通，将复位信号通过第二下拉路径下拉为低电平。
其中，第一充电电路、第一输入信号放大电路、第一时钟信号感测放大电路和第一接地放大电路依次串联；第二充电电路、第二输入信号放大电路、第二时钟信号感测放大电路和第二接地放大电路依次串联。
本公开实施例中，通过交叉跳变转移支路能够在设置信号或者复位信号发生跳变过程中，始终使其通过原始下拉路径被放电(下拉)，效率高，功耗低，能够避免差分输入信号跳变导致的错误输出。
感应阶段完成是指，原始数据信号为高电平时，设置信号已经被下拉为低电平，即逻辑“0”信号，复位信号已经被上拉为高电平，即逻辑“1”信号；或者，原始数据信号为低电平时，设置信号已经被上拉为高电平，即逻辑“1”信号，复位信号已经被下拉为低电平，即逻辑“0”信号。
下面对第一下拉路径和第二下拉路径进行详细说明。
第一输入信号放大电路和第一时钟信号感测放大电路之间通过第一节点(节点A)连接；第二输入信号放大电路和第二时钟信号感测放大电路之间通过第二节点(节点B)连接；第一时钟信号感测放大电路与第一接地放大电路之间通过第三节点(节点C)连接；第二时钟信号感测放大电路与第二接地放大电路之间通过第四节点(节点D)连接。
第一充电电路与第二充电电路的第一端均连接电源；第一充电电路的第二端和感测模块之间通过设置信号节点连接；第二充电电路的第二端和感测模块之间通过复位信号节点连接。示例性地，第一充电电路和第一输入信号放大电路之间通过设置信号节点(SB节点，用于采集设置信号)连接；第二充电电路和第二输入信号放大电路之间通过复位信号节点(RB节点，用于采集复位信号)连接。
第一接地放大电路和第二接地放大电路均通过接地点接地。
设置信号节点、第一节点、第三节点和接地点之间导通时，形成用于下拉设置信号的第一下拉路径；复位信号节点、第二节点、第四节点和接地点之间导通时，形成用于下拉复位信号的第二下拉路径。
第一时钟信号感测放大电路和第二时钟信号感测放大电路分别用于接收时钟信号，并在时钟信号为高电平时导通。第一接地放大电路和第二接地放大电路均为高电平触发电路，即在采集到高电平时触发动作。
本公开实施例的中的触发动作包括电路中的开关器件(或开关单元)导通。
下面对感测模块的工作原理进行说明。
交叉跳变转移电路用于将感应阶段完成后，差分输入信号发生跳变时导通的放大电路的有效信号，转移到差分输入信号跳变之前(感应阶段)导通的另一个放大电路中。当差分输入信号发生跳变时，感应阶段导通的放大电路(第一放大电路或第二放大电路)会暂时断开，而另一个放大电路在差分输入信号跳变的情况下被触发导通。此时，通过交叉跳变转移支路能够再次导通感应阶段的导通的放大电路，从而继续通过感应阶段原始的下拉路径实现信号(设置信号或复位信号)下拉。
第一转移电路与第一输入信号放大电路并联，第一转移电路的第一端和第一输入信号放大电路的第一端均连接设置信号节点，第一转移电路第二端和第一输入信号放大电路的第二端均连接第一时钟信号感测放大电路的第一端；第一转移电路的控制端连接第二时钟信号感测放大电路的第二端；第二转移电路与第二输入信号放大电路并联，第二转移电路的第一端和第二输入信号放大电路的第一端均连接复位信号节点，第二转移电路第二端和第二输入信号放大电路的第二端均连接第二时钟信号感测放大电路的第一端；第二转移电路的控制端连接第一时钟信号感测放大电路的第二端。
示例性地，第一转移电路用于在感应完成、差分输入信号发生跳变时，将第二放大电路的有效信号转移到第一放大电路，使得设置信号继续通过感应阶段的下拉路径放电。(感应阶段，若原始数据信号为高电平，设置信号通过第一放大电路的第一下拉路径放电，即下拉)第二转移电路用于在感应完成、差分输入信号发生跳变时，将第一放大电路的有效信号转移到第二放大电路，使得复位信号继续通过感应阶段的下拉路径放大(感应阶段，若原始数据信号为低电平，复位信号通过第二放大电路的第二下拉路径放电，即下拉)。
交叉跳变转移电路使得，在感应阶段完成后，差分输入信号(如原始数据信号)发生跳变时，仍然通过数据信号感应阶段的下拉路径放电。下拉速度快，避免差分输入信号跳变干扰，安全性和效率高。
下面对组成对充电模块中的各个电路进行示例性说明。
充电模块包括并联的第一充电电路和第一信号维持电路，以及并联的第二充电电路和第二信号维持电路。第一充电电路包括第一开关单元，第一信号维持电路包括第二开关单元；第一开关单元与第二开关单元并联；第一开关单元的第一端连接电源，第二端连接设 置信号节点；第二开关单元的第一端连接电源，第二端连接设置信号节点；第一开关单元的控制端用于接收时钟信号；第二开关单元的控制端用于接收复位信号节点的复位信号；第二充电电路包括第四开关单元；第二信号维持电路包括第三开关单元；第三开关单元与第四开关单元并联；第三开关单元的第一端连接电源，第二端连接设置信号节点；第四开关单元的第一端连接电源，第二端连接设置信号节点；第四开关单元的控制端用于接收时钟信号；第三开关单元的控制端用于接收设置信号节点的设置信号。
本公开实施例中，开关单元(如第一开关单元、第二开关单元等)可以选择低电平触发的电子器件，在另外的实施例中，也可以选在高电平触发电子器件与反向器相结合的方式实现。
示例性地，第一充电电路包括第一PMOS晶体管P1，第一信号维持电路包括第二PMOS晶体管P2；第二充电电路包括第三PMOS晶体管P3，第二信号维持电路包括第四PMOS晶体管P4。其中，P1、P2、P3、P4的源极均与电源连接。P1、P4的栅极用于接收时钟信号(CLK)。P1和P2的漏极连接，形成第一信号节点，即设置信号节点。P3和P4的漏极连接，形成第二信号节点，即复位信号节点。P1和P2的漏极，即设置信号节点还与P3的栅极连接。P3和P4的漏极，即复位信号节点还与P2的栅极连接。
下面对组成对感测模块中的各个电路进行示例性说明。
第一输入信号放大电路包括第一开关器件；第一转移电路包括第七开关器件；所述第一开关器件的第一端和所述第七开关器件的第一端均与设置信号节点连接；所述第一开关器件的第二端和所述第七开关器件的第二端均连接所述第一时钟信号感测放大电路的第一端(第一节点)；第七开关器件的控制端连接第二时钟信号感测放大电路的第二端(第四节点)；第二输入信号放大电路包括第二开关器件；第二转移电路包括第八开关器件；第二开关器件的第一端和所述第八开关器件的第一端均与复位信号节点连接；第二开关器件的第二端和所述第八开关器件的第二端均连接所述第二时钟信号感测放大电路的第一端(第二节点)；第八开关器件的控制端连接第一时钟信号感测放大电路的第二端(第三节点)；所述第一开关器件的控制端用于接收原始数据信号；所述第二开关器件的控制端用于接收反相数据信号。
本公开实施例中，开关器件(如第一开关器件、第七开关器件等)可以选择高电平触发的电子器件，在另外的实施例中，也可以选在低电平触发电子器件与反向器相结合的方式实现。本公开实施例对于器件选择不做限制。
第一时钟信号感测放大电路包括第三开关器件；第三开关器件的第一端连接第一开关器件的第二端(第一节点)；第三开关器件的第二端连接第一接地放大电路的第一端(第三节点)；第三开关器件的控制端用于接收时钟信号；第二时钟信号感测放大电路包括第四开关器件；第四开关器件的第一端连接第二开关器件的第二端(第二节点)；第四开关器件的第二端连接第二接地放大电路的第二端(第四节点)；第四开关器件的控制端用于接收时钟信号。
示例性地，第一时钟信号感测放大电路包括第三NMOS晶体管N3(N-Metal-Oxide-Semiconductor)。N3的栅极用于接收时钟信号，并在时钟信号为高电平时导通。N3的漏极连接第一节点(节点A)，示例性地，N3的漏极与N1的源极连接，形成第一节点(节点A)。N3的源极连接第三节点(节点C)。第二时钟信号感测放大电路包括第四NMOS晶体管N4。N4的栅极用于接收时钟信号，并在时钟信号为高电平时导通。N4的漏极连接第二节点(节点B)，示例性地，N4的漏极与N2的源极连接，形成第二节点(节点B)。N4的源极连接第四节点(节点D)。
第一输入信号放大电路包括第一NMOS晶体管N1，第一转移电路包括第七NMOS晶体管N7。N1的栅极用于接收原始数据信号(D)。N1的漏极与P1(和P2)的漏极，即设置信号节点连接。N1的源极连接第一节点(节点A)。N7的漏极与N1的漏极连接，N7的源极与 N1的源极连接。第二输入信号放大电路包括第二NMOS晶体管N2，第二转移电路包括第八NMOS晶体管N8。N2的栅极用于接收反相数据信号DB。N2的漏极与P3(和P4)的漏极，即复位信号节点连接。N2的源极连接第二节点(节点B)。N8的漏极与N2的漏极连接，N8的源极与N2的源极连接。N7的栅极连接N4的源极。N8的栅极连接N3的源极。
第一接地放大电路包括第五开关器件；第五开关器件的第一端与第三开关器件的第二端(第三节点)连接；第五开关器件的第二端接地；第五开关器件的控制端用于接收复位信号节点的复位信号；第二接地放大电路包括第六开关器件；第六开关器件的第一端与第四开关器件的第二端连接(第三节点)连接；第六开关器件的第二端接地；第六开关器件的控制端用于接收设置信号节点的设置信号。
示例性地，第一接地放大电路包括第五NMOS晶体管N5。N5的栅极连接复位信号节点(RB)。N5的漏极连接第三节点(节点C)。N5的源极接地。第二接地放大电路包括第六NMOS晶体管N6。N6的栅极连接设置信号节点(SB)。N6的漏极连接第四节点(节点C)。N6的源极接地。
如图2a所示，在CLK为低电平时只对结点RB，SB，A(或B)充电，大大降低了其他结点电路充放的浪费。与此同时，改进后的SA可以在CLK上升沿更快地捕获输入数据。这主要是由于放电过程中内部节点(下拉路径上的节点)保持低电平，减少了内部结点的放电时间，获得更优的保持时间和功耗的降低。
本公开实施例还提供一种基于感测放大器电路的触发器，利用上述改进的灵敏放大器主级触发器采样时钟信号上升沿的数据，然后通过锁存器锁存数据，应用于高速电路系统上升沿采样数据。其中，锁存器用于从所述感测放大器电路接收时钟信号、差分输入信号和设置信号，并锁存目标数据信号。
下面对本公开实施例的锁存器的结构进行示例性地说明。
如图2b，从级的锁存器(Latch)为SR锁存器，包括充放电电路和反馈电路。充放电电路和反馈电路耦接。充放电电路接收时钟信号、差分输入信号和设置信号，输出目标数据信号；反馈电路，接收所述目标数据信号和时钟信号，在时钟信号无效时，对目标数据信号进行锁存。
充放电电路包括依次串联的第五开关单元、第九开关器件、第十开关器件和第十一开关器件；其中，第五开关单元的第一端与电源连接，第五开关单元第二端与第九开关器件的第一端连接；第五开关单元的控制端用于接收设置信号；差分输入信号包括原始数据信号和反相数据信号；第九开关器件的控制端用于接收反相数据信号；第九开关器件的第二端与第十开关器件的第一端连接；第十开关器件的控制端用于接收时钟信号；第十开关器件的第二端与第十一开关器件的第一端连接；第十一开关器件的第二端接地；第十一开关器件的控制端用于接收设置信号；第五开关单元的第二端用于目标数据信号。其中，第五开关单元和第十一开关器件被配置为不会同时导通，即在同一时间最多只有其中一个导通。
示例性地，充放电电路包括依次串联的第五PMOS晶体管P5、第九NMOS晶体管N9、第十NMOS晶体管N10和第十一NMOS晶体管N11。其中，P5的源极连接电源，P5的漏极与N9的漏极连接，P5的栅极用于接收设置信号(SB)。N9的源极与N10的漏极连接，N9的栅极用于采集反相数据信号(DB)。N10的源极与N11的漏极连接，N10的栅极用于采集时钟信号(CLK)。N11的源极接地，N11的栅极用于采集设置信号(SB)。P5的漏极和N9的漏极的连接点作为输出采样点，用于采集目标数据信号Q。
反馈电路包括依次串联的第六开关单元、第七开关单元、第十二开关器件和反向器；第六开关单元的第一端连接电源；第六开关单元的第二端连接第七开关单元的第一端；反向器的输入端用于接收目标数据信号，反向器的输出端连接第六开关单元的控制端；反向器的输出端用于输出目标数据信号的反相信号；第七开关单元的第二端连接第十二开关器 件的第一端；第七开关单元的控制端用于接收时钟信号；第十二开关器件的第二端与第十开关器件的第二端连接；第十二开关器件的控制端与反向器的输出端连接；第七开关单元的第二端和第十二开关器件的第一端连接。其中，第六开关单元和第十二开关器件被配置为不会同时导通，即在同一时间最多只有其中一个导通。
示例性地，反馈电路包括第六PMOS晶体管P6、第七PMOS晶体管P7和第十二NMOS晶体管N12。P6的源极连接电源，P6的漏极与P7的源极连接。P6的栅极经过反向器与充放电电路连接。示例性地，反向器(INV1)的输入端连接输出采样点，反向器的输出端连接P6的栅极。P7的漏极与N12的漏极连接，P7的栅极用于接收时钟信号(CLK)。N12的源极连接N10的源极，N12的栅极与反向器的输出端连接。反向器的输出端用于输出目标数据信号Q的反相信号。P7和N12的连接之处形成第六节点，第六节点与输出采样点连接。
与现有技术的SAFF相比，从级的锁存器把DB和CLK控制的晶体管互换位置，避免了两个管子间的节点充放电电，更进一步优化了功耗。
下面对主级的灵敏放大器的工作过程进行示例性说明。
充电阶段：在时钟信号为低电平时，对设置信号节点和复位信号节点进行充电到高电平(1)，交叉跳变转移电路放电为低电平(0)。如图2a所示，当CLK为0时，P1，P4导通，设置信号节点(SB)和复位信号节点(RB)被充电为为高电平，即1；N5，N6导通，节点C，D被放电为0，N7，N8被关闭。
感应阶段:灵敏放大器采集到时钟信号上升沿，即时钟信号从低电平跳变为高电平时，进入感应阶段。此时，如果原始数据信号为高电平，则通过第一放大电路将设置信号(SB)下拉为低电平。示例性地，设置信号(SB)通过第一下拉路径下拉为低电平。
第一下拉路径为设置信号节点、第一节点、第三节点到接地点的信号通路。如图3a所示，第一下拉路径通过第一放大电路中的第一输入信号放大电路、第一时钟信号感测放大电路和第一接地放大电路形成。
如图3a所示，如果D为1，SB节点(即设置信号节点)由N1，N3，N5下拉为0，然后P3导通，RB维持原来的1。
跳变阶段：感应阶段后，时钟信号持续在高电平而数据信号跳变为低电平时，第一下拉路径暂时断开，第二放大电路部分导通(包括第二输入信号放大电路和第二时钟信号感测放大电路)，形成有效信号，通过第一转移电路将有效信号转移到第一放大电路，再次导通第一下拉路径。设置信号继续通过低电位的第一下拉路径放电，放电速度快。
如图3b所示，感应完成后，当CLK依然为高时，D突然发生跳变为0，此时N2，N4导通，节点D被充为1，使N7导通。SB节点的下拉路径则为N7、N3、N5。
N8开启过程同理。在另外的场景中，充电阶段与上述一致，感应阶段的数据信号为低电平时，电路动作方式与上述过程对称，具体如下。
感应阶段:灵敏放大器采集到时钟信号上升沿，即时钟信号从低电平跳变为高电平时，进入感应阶段。此时，如果原始数据信号为低电平，则通过第二放大电路将复位信号(RB)下拉为低电平。示例性地，复位信号(RB)通过第二下拉路径下拉为低电平。
第二下拉路径为复位信号节点、第二节点、第四节点到接地点的信号通路。第二下拉路径通过第二放大电路中的第二输入信号放大电路、第二时钟信号感测放大电路和第二接地放大电路形成。
示例性地，如果原始数据信号D为0，则反相数据信号DB为1，RB节点(即复位信号节点)由N2，N4，N6下拉为0，然后P2导通，SB维持原来的1。
感应阶段后，时钟信号持续在高电平而原始数据信号跳变为高电平(相应地，反相数据信号跳变为低电平无效信号)时，第二下拉路径暂时断开，第一放大电路部分导通(包括第一输入信号放大电路和第一时钟信号感测放大电路导通)，形成有效信号，通过第二 转移电路将有效信号(如使电路导通的高电平导通信号)转移到第二放大电路，再次导通第二下拉路径。复位信号继续通过低电位的第二下拉路径放电，放电速度快。
感应完成后，当CLK依然为高时，D突然发生跳变为1，此时N1，N3导通，节点C被充为1，使N8导通。RB节点的下拉路径则为N8、N4、N6。
采用本公开实施例的灵敏放大器实现的触发器，能够降低功耗，并且数据捕获速度更快、准确性更高。
如图2b所示，当触发器采集到时钟信号(CLK)为上升沿时，若原始数据信号为1，则设置信号(SB)下拉为低电平(0)时，P5导通，Q被上拉为高电平。此时，反相数据信号(DB)为0，N9断开，N9和N10之间的连接节点不会被充电，避免了不必要的充放电过程。
当主级采集到时钟信号(CLK)为上升沿时，若原始数据信号为0，则反相数据信号(DB)为1，N9导通；复位信号(RB)下拉为低电平，设置信号(SB)保持高电平，P5断开，N11导通；时钟信号为高电平，则N10导通；Q通过N9、N10和N11被下拉为低电平。
反馈电路能够在时钟信号为低电平时锁存上一次的数据。
当时钟信号CLK为低电平时，若目标数据信号Q为1，QB＝0，P6，P7导通，目标数据信号保持1；若目标数据信号Q为0，QB＝1，N12，N11导通，目标数据信号保持0。
采用本公开实施例的锁存器实现的触发器，由于减少了充放电节点数量，能耗降低。
本公开的感测放大器电路及触发器能够应用于高速电路系统，实现是时钟上升沿采样数据。
下面示例性地以现有技术中的一种放大器电路为例，对本公开实施例的感测放大器电路的技术效果进行对比说明，但不限制本公开实施例的感测放大器电路的使用场景。
图4示出了Heng You等人提出SAFF(sense-amplifier-based flip-flop，灵敏放大器触发器)结构图，这种单端型SAFF主级差分灵敏放大器在时钟上升沿感应输入数据，一旦时钟信号CLK发生由低到高的跳变，其采样窗口就会关闭，由从级输出。如图4所示，主级CLK为低电平时，对电路中SN，RN进行预充到高电平，CLK为高电平时，如果D为高电平，SN则被放电到低电平，输出Q被MP5上拉为1；如果D为低电平，RN则被放电到低电平，输出Q被MN8，MN9，MN11下拉为0，Feedback inverter(反馈逆变器)和INV1能够在CLK为低电平时锁存上一次数据。该SAFF结构主要存在以下问题：
(1)对于主级SA，CLK为低电平时，需要对SN，RN，n1，n2，n3，n4节点充电，然后CLK上升沿时要对SN，n3，n1或RN，n4，n2节点放电，能耗较高。
(2)当CLK为高电平时，如果数据D由“1”变化“0”MN3截止，MN4导通，RN，n4，n2节点放电。但是，由于MN7是一直导通的弱晶体管，MN4导通后给SN提供下拉电路接地(MN1，MN5，MN7，MN4)。MN7管降低了SAFF在低电源电压下的稳定性，在CLK上升沿的SA阶段过程中，Vn1和Vn2(即节点n1和n2的电压)的差值应该足够大，才能够快速、正确得到RN，SN。
如图5所示，主级SA，差分电路是两边不对称的结构，因为SAFF从级只利用SN信号，左侧方框中SN的上拉路径和下拉路径都要比右侧方框中RN的上拉路径和下拉路径中的管子尺寸更大，以提升SN节点的驱动能力。
当VDD较低时，Vn1和Vn2的差值变小，同时该电路两边管子不匹配对Vn1和Vn2的差值影响严重，SA阶段可能锁存错误数据。如果D为0，DN为1，由于MN4管尺寸小，n2点电压缓慢降低，同时n1点电压也会通过MN7管小幅度降低。n1点电压降低会导致不必要的功耗，甚至使SN点电压拉低为0。
3)如图6、图7所示，在第一时刻，当CLK上升沿来临时D＝1时，SN为0，MP5，MN8管导通，目标数据信号节点Q和A会被充为高电平。
如图6、图7所示，在第二时刻，当CLK上升沿来临时D＝0时，SN为1，MN8，MN9，MN11管导通，目标数据信号节点Q和A会被充为低电平。如此，不必要的节点A反复充放电会带来功耗增加。
将公开实施例的触发器SAFF在HSPICE软件上完成该延时、功耗的测量。仿真条件设定如下:室温25摄氏度，1.2V电源电压TT工艺角，时钟频率fclk＝500MHz，输入数据信号频率fd＝250MHz(α＝1)，α表示数据活动因子，其计算公式
Figure PCTCN2022117319-appb-000001
其中，fd代表输入信号的频率，fclk代表时钟信号的频率。
对比现有技术中的Heng You SAFF和改进后SAFF仿真图的输出波形，发现，本公开实施例的触发器在信号Q的电平转变的上升沿和下降沿更加迅速，功耗也更低。如图8所示，改进后的本公开实施例的SAFF的感应阶段SB可以在CLK上升沿更快地捕获输入数据。改进后的SAFF从感应数据下拉到低电平延时比Heng You SAFF从感应数据下拉到低电平延时更短，感应延迟优化21.6％。
如图9所示，改进后的SAFF所提供的调节下拉电路差分两边没有电流相互干扰，需要保持不被下拉的信号能够稳定在高电平，相对比Heng You SAFF则受一直导通的管子影响，SB下拉路径不导通的情况下，SB电压还是有所下降，多余的动作不仅带来功耗的浪费甚至导致SB出错。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的一种感测放大器电路及触发器，能够避免差分结构两侧的电流相互干扰，提高放大器输出的稳定性和准确性，应用在触发器时，数据采样快，耗能低。而且，采用本公开优化的锁存器，能够减少充放电节点数量，进一步降低耗能、提高效率。

Claims (15)

  1. 一种感测放大器电路，包括：
    充电模块，被配置为根据时钟信号，对设置信号节点和复位信号节点进行充电；感测模块，与所述充电模块耦接，被配置为根据时钟信号，感测并放大差分输入信号；其中，感测模块包括第一放大电路、第二放大电路、交叉连接在第一放大电路和第二放大电路之间的交叉跳变转移电路；所述交叉跳变转移电路包括第一转移电路和第二转移电路；第一转移电路用于在感应完成、差分输入信号发生第一跳变时，将第二放大电路的有效信号转移到第一放大电路，使得设置信号节点的设置信号和复位信号节点的复位信号维持不变；第二转移电路用于在感应完成、差分输入信号发生第二跳变时，将第一放大电路的有效信号转移到第二放大电路，使得设置信号节点的设置信号和复位信号节点的复位信号维持不变。
  2. 根据权利要求1所述的感测放大器电路，其中，
    所述第一放大电路包括串联的第一输入信号放大电路和第一时钟信号感测放大电路；所述第二放大电路包括串联的第二输入信号放大电路和第二时钟信号感测放大电路；所述第二时钟信号感测放大电路与所述第一输入信号放大电路通过第一转移电路连接；所述第一时钟信号感测放大电路与所述第二输入信号放大电路通过第二转移电路连接。
  3. 根据权利要求2所述的感测放大器电路，其中，
    第一转移电路与第一输入信号放大电路并联，第一转移电路的第一端和第一输入信号放大电路的第一端均连接设置信号节点，第一转移电路第二端和第一输入信号放大电路的第二端均连接第一时钟信号感测放大电路的第一端；第一转移电路的控制端连接第二时钟信号感测放大电路的第二端；第二转移电路与第二输入信号放大电路并联，第二转移电路的第一端和第二输入信号放大电路的第一端均连接复位信号节点，第二转移电路第二端和第二输入信号放大电路的第二端均连接第二时钟信号感测放大电路的第一端；第二转移电路的控制端连接第一时钟信号感测放大电路的第二端。
  4. 根据权利要求1所述的感测放大器电路，其中，
    所述差分输入信号包括原始数据信号和反相数据信号；第一放大电路接收原始数据信号，用于在感应阶段导通，将设置信号通过第一下拉路径下拉为低电平；第二放大电路接收反相数据信号，用于在感应阶段导通，将复位信号通过第二下拉路径下拉为低电平。
  5. 根据权利要求2所述的感测放大器电路，其中，
    第一放大电路还包括第一接地放大电路；其中，第一输入信号放大电路、第一时钟信号感测放大电路和第一接地放大电路依次串联，第一输入信号放大电路的第一端与设置信号节点连接，第一接地放大电路的第二端接地；第一接地放大电路的控制端与复位信号节点连接，用于在复位信号的作用下导通或关断；第二放大电路还包括第二接地放大电路；其中，第二输入信号放大电路、第二时钟信号感测放大电路和第二接地放大电路依次串联，第二输入信号放大电路的第一端与复位信号节点连接，第二接地放大电路的第二端接地；第二接地放大电路的控制端与设置信号节点连接，用于在设置信号的作用下导通或关断。
  6. 根据权利要求1所述的感测放大器电路，其中，
    充电模块包括第一充电电路和第二充电电路；第一充电电路用于根据时钟信号，对设置信号节点进行充电；第二充电电路用于根据时钟信号，对复位信号节点进行充电；第一充电电路与第二充电电路的第一端均连接电源；第一充电电路的第二端和感测模块之间通过设置信号节点连接；第二充电电路的第二端和感测模块之间通过复位信号节点连接。
  7. 根据权利要求6所述的感测放大器电路，其中，
    充电模块还包括第一信号维持电路和第二信号维持电路；第一信号维持电路与所述第一充电电路并联，第一信号维持电路与复位信号节点连接；第二信号维持电路与所述第二充电电路并联，第二信号维持电路与设置信号节点连接；第一信号维持电路用于在感应完成、差分输入信号发生第二跳变时，维持设置信号状态；第二信号维持电路用于在感应完成、差分输入信号发生第一跳变时，维持复位信号状态。
  8. 根据权利要求7所述的感测放大器电路，其中，
    第一充电电路包括第一开关单元，第一信号维持电路包括第二开关单元；第一开关单元与第二开关单元并联；第一开关单元的第一端连接电源，第二端连接设置信号节点；第二开关单元的第一端连接电源，第二端连接设置信号节点；第一开关单元的控制端用于接收时钟信号；第二开关单元的控制端用于接收复位信号节点的复位信号；第二充电电路包括第四开关单元；第二信号维持电路包括第三开关单元；第三开关单元与第四开关单元并联；第三开关单元的第一端连接电源，第二端连接设置信号节点；第四开关单元的第一端连接电源，第二端连接设置信号节点；第四开关单元的控制端用于接收时钟信号；第三开关单元的控制端用于接收设置信号节点的设置信号。
  9. 根据权利要求5所述的感测放大器电路，其中，
    所述第一输入信号放大电路包括第一开关器件；第一转移电路包括第七开关器件；所述第一开关器件的第一端和所述第七开关器件的第一端均与设置信号节点连接；所述第一开关器件的第二端和所述第七开关器件的第二端均连接所述第一时钟信号感测放大电路的第一端；第七开关器件的控制端连接第二时钟信号感测放大电路的第二端；所述第二输入信号放大电路包括第二开关器件；第二转移电路包括第八开关器件；所述第二开关器件的第一端和所述第八开关器件的第一端均与复位信号节点连接；所述第二开关器件的第二端和所述第八开关器件的第二端均连接所述第二时钟信号感测放大电路的第一端；第八开关器件的控制端连接第一时钟信号感测放大电路的第二端；所述第一开关器件的控制端用于接收原始数据信号；所述第二开关器件的控制端用于接收反相数据信号。
  10. 根据权利要求9所述的感测放大器电路，其中，
    第一时钟信号感测放大电路包括第三开关器件；第三开关器件的第一端连接所述第一开关器件的第二端；第三开关器件的第二端连接所述第一接地放大电路的第一端；第三开关器件的控制端用于接收时钟信号；第二时钟信号感测放大电路包括第四开关器件；第四开关器件的第一端连接所述第二开关器件的第二端；第四开关器件的第二端连接所述第二接地放大电路的第二端；第四开关器件的控制端用于接收时钟信号。
  11. 根据权利要求10所述的感测放大器电路，其中，
    第一接地放大电路包括第五开关器件；第五开关器件的第一端与第三开关器件的第二端连接；第五开关器件的第二端接地；第五开关器件的控制端用于接收复位信号节点的复位信号；第二接地放大电路包括第六开关器件；第六开关器件的第一端与第四开关 器件的第二端连接；第六开关器件的第二端接地；第六开关器件的控制端用于接收设置信号节点的设置信号。
  12. 一种触发器，包括：
    基于1-11中任一项所述的感测放大器电路和锁存器；所述锁存器用于从所述感测放大器电路接收时钟信号、差分输入信号和设置信号，并锁存目标数据信号。
  13. 根据权利要求12所述的触发器，其中，
    所述锁存器包括充放电电路和反馈电路；充放电电路接收时钟信号、差分输入信号和设置信号，输出目标数据信号；反馈电路，接收所述目标数据信号和时钟信号，在时钟信号无效时，锁存目标数据信号。
  14. 根据权利要求13所述的触发器，其中，
    充放电电路包括依次串联的第五开关单元、第九开关器件、第十开关器件和第十一开关器件；其中，第五开关单元的第一端与电源连接，第五开关单元第二端与第九开关器件的第一端连接；第五开关单元的控制端用于接收设置信号；所述差分输入信号包括原始数据信号和反相数据信号；第九开关器件的控制端用于接收所述反相数据信号；所述第九开关器件的第二端与第十开关器件的第一端连接；第十开关器件的控制端用于接收时钟信号；第十开关器件的第二端与第十一开关器件的第一端连接；第十一开关器件的第二端接地；第十一开关器件的控制端用于接收设置信号；第五开关单元的第二端用于输出目标数据信号；第五开关单元和第十一开关器件被配置为在同一时间最多只有其中一个导通。
  15. 根据权利要求14所述的触发器，其中，
    反馈电路包括依次串联的第六开关单元、第七开关单元、第十二开关器件和反向器；第六开关单元的第一端连接电源；第六开关单元的第二端连接第七开关单元的第一端；反向器的输入端接收目标数据信号，反向器的输出端连接第六开关单元的控制端；第七开关单元的第二端连接第十二开关器件的第一端；第七开关单元的控制端用于接收时钟信号；第十二开关器件的第二端连接第十开关单元的第二端；第十二开关器件的控制端与反向器的输出端连接；第六开关单元和第十二开关器件被配置为在同一时间最多只有其中一个导通。
PCT/CN2022/117319 2022-07-11 2022-09-06 一种感测放大器电路及触发器 WO2024011738A1 (zh)

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CN108233896A (zh) * 2018-01-31 2018-06-29 电子科技大学 一种低功耗灵敏放大器型d触发器
CN111092612A (zh) * 2018-10-24 2020-05-01 爱思开海力士有限公司 包括感测放大器和锁存器的半导体集成电路
CN114583925A (zh) * 2022-03-11 2022-06-03 长鑫存储技术有限公司 放大电路

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Publication number Priority date Publication date Assignee Title
US20150311875A1 (en) * 2014-04-24 2015-10-29 Qualcomm Incorporated Sense amplifier with improved resolving time
CN108233896A (zh) * 2018-01-31 2018-06-29 电子科技大学 一种低功耗灵敏放大器型d触发器
CN111092612A (zh) * 2018-10-24 2020-05-01 爱思开海力士有限公司 包括感测放大器和锁存器的半导体集成电路
CN114583925A (zh) * 2022-03-11 2022-06-03 长鑫存储技术有限公司 放大电路

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