WO2024007945A1 - 光电封装结构和光子计算系统 - Google Patents

光电封装结构和光子计算系统 Download PDF

Info

Publication number
WO2024007945A1
WO2024007945A1 PCT/CN2023/103885 CN2023103885W WO2024007945A1 WO 2024007945 A1 WO2024007945 A1 WO 2024007945A1 CN 2023103885 W CN2023103885 W CN 2023103885W WO 2024007945 A1 WO2024007945 A1 WO 2024007945A1
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
substrate
optical
packaging structure
optical waveguide
Prior art date
Application number
PCT/CN2023/103885
Other languages
English (en)
French (fr)
Inventor
吴建华
卢正观
孟怀宇
塞蒂亚迪达迪
斯沃岑特鲁伯罗恩
苏湛
斯坦曼莫
陈俊杰
彭博
沈亦晨
Original Assignee
南京光智元科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 南京光智元科技有限公司 filed Critical 南京光智元科技有限公司
Publication of WO2024007945A1 publication Critical patent/WO2024007945A1/zh

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
    • G02B6/4236—Fixing or mounting methods of the aligned elements
    • G02B6/4237—Welding
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4296—Coupling light guides with opto-electronic elements coupling with sources of high radiant energy, e.g. high power lasers, high temperature light sources
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06E—OPTICAL COMPUTING DEVICES; COMPUTING DEVICES USING OTHER RADIATIONS WITH SIMILAR PROPERTIES
    • G06E1/00—Devices for processing exclusively digital data
    • G06E1/02—Devices for processing exclusively digital data operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2113/00—Details relating to the application field
    • G06F2113/18—Chip packaging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/06—Structured ASICs

Definitions

  • the present disclosure relates to the field of semiconductors, and more specifically, to an optoelectronic packaging structure and a photonic computing system.
  • the present disclosure provides an optoelectronic packaging structure and a photonic computing system that greatly expands computing and interconnection with higher bandwidth per unit area and a more fully connected topology that is not limited by silicon adjacency by using optical signals on the substrate. Even ability.
  • a first aspect of the present disclosure provides an optoelectronic packaging structure, including: a substrate including a core layer, an optical interconnection network, and an electrical interconnection network; and a chip array arranged on a first surface of the substrate, including at least one A photonic integrated circuit chip and at least one electronic integrated circuit chip; the photonic integrated circuit chip is optically interconnected through the optical interconnection network, and the electronic integrated circuit chip is The circuit chips are electrically interconnected through the electrical interconnection network.
  • the at least one photonic integrated circuit chip and the at least one electronic integrated circuit chip form an electronic-photonic hybrid chip including a photonic integrated circuit chip and an electronic integrated circuit chip, and the electronic integrated circuit chip
  • the interconnect network includes one or more second conductive vias extending through the substrate, the second surface of the substrate having a solder structure for soldering to a printed circuit board, the solder structure being electrically connected to the electrical interconnect network. connect.
  • a photonic integrated circuit chip in the electronic-photonic hybrid chip has one or more first conductive vias therethrough, the one or more first conductive vias being in connection with the electrical interconnect The network is electrically connected, and the electronic integrated circuit chip in the electronic-photonic hybrid chip is arranged on the upper surface of the photonic integrated circuit chip and is electrically connected to the one or more first conductive vias.
  • a first optical waveguide is arranged in the photonic integrated circuit chip, the optical interconnection network includes a second optical waveguide, and the photonic integrated circuit chip and the optical interconnection network are connected by The first optical waveguide and the second optical waveguide are optically coupled.
  • the first optical waveguide and the second optical waveguide are stacked and separated by a predetermined distance in a direction perpendicular to the first surface of the substrate, such that the first optical waveguide and the second optical waveguide are Two optical waveguides realize adiabatic coupling of light.
  • the optoelectronic package structure further includes: an array of beam redirecting elements disposed in the substrate, each beam redirecting element in the array of beam redirecting elements being configured to modify the light beam direction so that it enters the optical coupler of the second/first optical waveguide.
  • the photonic integrated circuit chip further includes an edge coupler connected to the first optical waveguide, and the edge coupler of the first optical waveguide and the second optical waveguide are bonded by a photonic wire Optical coupling is performed in a combined manner.
  • the second optical waveguide includes at least one of the following: a. one or more layers of optical waveguide embedded in the core layer of the substrate; b. a third optical waveguide formed in the core layer of the substrate. One or more layers of optical waveguides on a surface; and c. A three-dimensional waveguide network formed within a core layer of said substrate.
  • the photonic integrated circuit chip further includes a grating coupler connected to the first optical waveguide, the first optical waveguide Coupled to the three-dimensional waveguide network through the grating coupler.
  • the optoelectronic packaging structure further includes: a light source configured to provide light to the photonic integrated circuit chip.
  • the light source is disposed on the first surface of the substrate, and the light source is aligned with an edge coupler of a first optical waveguide in the photonic integrated circuit chip, thereby directing the light source to the photonic integrated circuit chip.
  • Integrated circuit chips provide light.
  • the light source is disposed in a groove in the first surface of the substrate, and the light source is aligned with an edge coupler of a second optical waveguide in the optical interconnect network and directed toward The photonic integrated circuit chip provides light.
  • the light source is disposed on the first surface of the substrate, and the light source couples light to the light of the first optical waveguide in the photonic integrated circuit chip by photonic wire bonding. In the coupler, light is then provided to the photonic integrated circuit chip.
  • the light source is disposed in a groove on the first surface of the substrate, and the light source couples light to a second light source in the optical interconnect network by means of photonic wire bonding. In the optical coupler of the waveguide, light is then provided to the photonic integrated circuit chip.
  • the light source is disposed on the first surface of the substrate
  • the optoelectronic packaging structure further includes: a beam shaping element disposed on the first surface of the substrate, located on the between the light source and the photonic integrated circuit chip, wherein the light source couples light into the optical coupler of the first optical waveguide of the photonic integrated circuit chip through the beam shaping element, and then to the photonic integrated circuit chip.
  • the chip provides the light.
  • the light source is disposed in a groove on the first surface of the substrate
  • the optoelectronic packaging structure further includes: a beam shaping element disposed in the groove and located on the between the light source and the second optical waveguide in the optical interconnection network, wherein the light source couples light into the optical coupler of the second optical waveguide through the beam shaping element, thereby integrating the light into the photon
  • the circuit chip provides the light.
  • the light source includes: a laser configured to emit light; a temperature controller disposed below the laser and configured to control the temperature emitted by the laser by adjusting the temperature of the laser wavelength of light.
  • the electrical interconnection network includes one or more electrical wiring layers disposed on the second surface of the core layer of the substrate.
  • the electrical interconnection network further includes a core layer disposed on the substrate One or more electrical wiring layers on the first surface.
  • the chips in the chip array are disposed over and covering a groove on the first surface of the substrate, and the electrical interconnection network further includes disposed in the groove one or more electrical wiring layers, and the optical interconnection network is disposed in an area of the first surface of the substrate not occupied by the grooves.
  • the chip array includes one or more memory chips.
  • the material of the core layer of the substrate is glass, silicon or ceramic.
  • a second aspect of the present disclosure provides a photonic computing system, which includes the optoelectronic packaging structure as described above.
  • the photonic computing system further includes: a light source configured to provide light to the optoelectronic packaging structure; and a printed circuit board.
  • a circuit board is configured to carry the optoelectronic packaging structure and is electrically connected to the soldering structure on the second surface of the substrate.
  • a third aspect of the present disclosure provides a photonic computing system, which includes an optoelectronic packaging structure as described above.
  • the photonic computing system further includes: a printed circuit board configured to carry the optoelectronic packaging structure, and with The soldering structure on the second surface of the substrate is electrically connected.
  • the optoelectronic packaging structure proposed in this disclosure provides power for next-generation high-performance AI computing tasks by leveraging the speed, power, efficiency and chip array layout of light, providing a platform for a new computing paradigm.
  • the platform is panel-based and scalable, overcoming wafer scribing limitations and wafer size limitations. It will bring a major breakthrough in chip bandwidth, superior to all existing CPU/GPU bandwidth.
  • the panel substrate proposed in this disclosure can be expanded to 310 ⁇ 310mm2, 510 ⁇ 510mm2, or even larger. In contrast, current chips can only be expanded to 100 ⁇ 100mm2, and wafers can only be expanded to 12 inches.
  • the optoelectronic packaging structure proposed in this disclosure will provide ultra-high-speed, low-latency and low-power AI computing, which will be several orders of magnitude better than traditional electronic architectures.
  • FIG. 1 shows a schematic diagram of the overall configuration of an optoelectronic packaging structure according to an embodiment of the present disclosure.
  • Figure 2 shows a schematic diagram of an optical waveguide in an optical interconnection network in an optoelectronic packaging structure according to an embodiment of the present disclosure.
  • FIG. 3 shows a schematic diagram of the first optical coupling method in the optoelectronic packaging structure according to the embodiment of the present disclosure.
  • FIG. 4 shows a schematic diagram of the second optical coupling method in the optoelectronic packaging structure according to the embodiment of the present disclosure.
  • FIG. 5 shows a schematic diagram of the third optical coupling method in the optoelectronic packaging structure according to the embodiment of the present disclosure.
  • FIG. 6 shows a schematic diagram of the fourth optical coupling method in the optoelectronic packaging structure according to the embodiment of the present disclosure.
  • FIG. 7 shows a schematic diagram of the first light source coupling method in the optoelectronic packaging structure according to the embodiment of the present disclosure.
  • FIG. 8 shows a schematic diagram of the second light source coupling method in the optoelectronic packaging structure according to the embodiment of the present disclosure.
  • FIG. 9 shows a schematic diagram of the third light source coupling method in the optoelectronic packaging structure according to the embodiment of the present disclosure.
  • FIG. 10 shows a schematic diagram of the fourth light source coupling method in the optoelectronic packaging structure according to the embodiment of the present disclosure.
  • FIG. 11 shows a schematic diagram of the fifth light source coupling method in the optoelectronic packaging structure according to the embodiment of the present disclosure.
  • FIG. 12 shows a schematic diagram of the sixth light source coupling method in the optoelectronic packaging structure according to the embodiment of the present disclosure.
  • FIG. 13 shows a schematic diagram of the structure of a light source in an optoelectronic packaging structure according to an embodiment of the present disclosure.
  • Figure 14 shows a schematic diagram of a photonic computing system of an embodiment of the present disclosure.
  • Figure 15 shows a schematic diagram of another photonic computing system according to an embodiment of the present disclosure.
  • FIG. 1 shows a schematic diagram of the overall configuration of an optoelectronic packaging structure 100 according to an embodiment of the present disclosure.
  • FIG. 1 shows in (a) a top view of the optoelectronic packaging structure 100 of the embodiment of the present disclosure, and in (b) shows a cross-section of the optoelectronic packaging structure 100 in the first direction.
  • Figure 1 shows a cross-sectional view of the optoelectronic packaging structure 100 in the second direction in (c), and a partial detail cross-sectional view of the optoelectronic packaging structure 100 is shown in (d).
  • the optoelectronic packaging structure 100 includes a substrate 110 and a chip array 120 .
  • Substrate 110 is a panel that carries and interconnects chip array 120 and is used for mounting to a printed circuit board (PCB).
  • the size of the substrate 110 can be made larger, for example, it can be expanded to 310 ⁇ 310mm2, 510 ⁇ 510mm2, or even larger, thereby overcoming the wafer scribing limit and the wafer size limit, and providing a larger packaging area for the packaging of optoelectronic chips.
  • the substrate 110 of the embodiment of the present disclosure can directly use an existing glass plate, ceramic plate or silicon substrate, thereby reaching a larger area, and can be directly installed on a PCB.
  • the thickness of the substrate thus formed mainly depends on the process of preparing the conductive via hole.
  • the process of conducting the conductive via hole can be made to 1 micron. Therefore, preferably, such a substrate can be formed to have a larger thickness, such as equal to or Greater than 1 micron to achieve adequate strength. As the process technology for preparing conductive vias matures, the thickness of the substrate can be made larger. A thicker substrate has the advantages of high rigidity and is not easy to warp.
  • the substrate 110 may structurally include a core layer 111 , an optical interconnection network 112 and an electrical interconnection network 113 .
  • the material of the core layer 111 may be, for example, glass, silicon or ceramics.
  • a layer of optical capping material can be first laid on the core layer 111 and then the waveguide material can be laid, thereby forming the optical interconnection network 112 .
  • at least one electrical wiring layer may also be disposed on the lower surface of the core layer 111 to form the electrical interconnection network 113 .
  • the chip array 120 in the optoelectronic packaging structure 100 may include at least one photonic integrated circuit (PIC) chip and at least one electronic integrated circuit (EIC) chip, which are arranged on a first side of the substrate 110 On the surface (for example, the upper surface), a two-dimensional array of chips is formed.
  • PIC photonic integrated circuit
  • EIC electronic integrated circuit
  • the multiple photonic integrated circuit chips may be optically interconnected through the optical interconnection network 112 as described above. Furthermore, where the chip array 120 includes a plurality of electronic integrated circuit chips, the plurality of electronic integrated circuit chips may be electrically interconnected through the electrical interconnection network 113 as described above.
  • At least one photonic integrated circuit chip and at least one electronic integrated circuit chip in the chip array 120 may form an electronic-photonic hybrid chip including a photonic integrated circuit chip and an electronic integrated circuit chip, for example , the EPIC shown in Figure 1, (d) in Figure 1 shows a partial cross-sectional view of an EPIC and the corresponding substrate part.
  • the photonic integrated circuit chip PIC in the electronic-photonic hybrid chip EPIC has one or more conductive vias TDV running through it, and the one or more conductive vias TDV are connected to the electrical interconnection network 113 (e.g., via TGVs in core layer 111). Furthermore, as shown in the figure, the electronic integrated circuit chip EIC in the electronic-photonic hybrid chip EPIC is arranged on the upper surface of the photonic integrated circuit chip PIC and is electrically connected with one or more conductive vias TDV.
  • the term "electronic-photonic hybrid chip” here does not mean the use of other chips besides the photonic integrated circuit chip and electronic integrated circuit chip as mentioned above, but means that the photonic integrated circuit chip
  • the PIC and the electronic integrated circuit chip EIC may be stacked and connected to each other to form an integral structure, such as a chip-let, such that the integral structure is arranged on the substrate 110 as some or all of the chips in the chip array 120 .
  • the "electron-photonic hybrid chip” itself can be formed in a variety of different ways.
  • a plurality of first electrical connectors may be arranged on the upper surface of the PIC chip, and a plurality of second electrical connectors may be correspondingly arranged on the lower surface of the EIC chip, and the PIC chip and the EIC chip pass through the first electrical connectors. It is directly bonded with the second electrical connector to form the overall structure of the "electron-photon hybrid chip".
  • the electronic-photonic hybrid chip may also be an overall structure including a PIC chip and multiple EIC chips (for example, a digital electronic integrated circuit chip (D-EIC) and an analog electronic integrated circuit chip (A-EIC)),
  • D-EIC digital electronic integrated circuit chip
  • A-EIC analog electronic integrated circuit chip
  • the D-EIC chip, the A-EIC chip and the PIC chip may also be directly bonded through the first electrical connector and the second electrical connector as described above.
  • flip-chip bonding can also be used to flip the EIC chip onto the PIC chip, thereby forming an electronic-photonic hybrid chip as described above.
  • Forming an "electron-photon hybrid chip" is not limited to the above methods. Various other methods can also be used to form the overall structure of the "electron-photon hybrid chip", which will not be discussed in detail here.
  • the lower surface of the substrate 110 also has a soldering structure 114 for soldering to the printed circuit board, and the soldering structure 114 is electrically connected to the electrical interconnection network 113 .
  • the solder structure 114 may be a plurality of LGA pads or BGA solder balls.
  • the chip array in the optoelectronic packaging structure 100 shown in FIG. 1 may also include other types of chips.
  • the optoelectronic packaging structure 100 may also include one or more memory chips, such as a high-bandwidth memory chip HBM chip as shown in FIG. 1 .
  • HBM chip high-bandwidth memory chip
  • the EIC chip, PIC chip, EPIC chip and HBM chip shown in Figure 1 are just some examples of numerous chips, and the optoelectronic packaging structure 100 according to the embodiment of the present disclosure may also include other chips according to specific needs.
  • Various types of chips including but not limited to temperature control chips, power control chips, light source chips, etc.
  • Each chip of the chip array 120 is electrically interconnected through an electrical interconnection network 113 and optically interconnected through an optical interconnection network 112 .
  • the electrical interconnection network 113 also includes one or more conductive vias extending through the core layer 111 of the substrate.
  • one or more conductive vias are through glass vias (TGV) as shown in the figure.
  • the one or more conductive vias may be through-ceramic vias (TCVs).
  • the core layer material is silicon
  • the one or more conductive vias may be through silicon vias (TSVs).
  • multiple photonic integrated circuit chips PIC arranged on the substrate 110 may be optically interconnected through the optical interconnection network 112 .
  • the specific implementation of optical interconnection between multiple PIC chips through an optical interconnection network will be described in detail below with reference to FIGS. 2 to 6 .
  • a first optical waveguide for light transmission is arranged in the photonic integrated circuit chip PIC, and the optical interconnection network on the substrate usually includes a second optical waveguide.
  • the photonic integrated circuit chip PIC and the optical interconnection network can be optically coupled through the first optical waveguide and the second optical waveguide, and then multiple photonic integrated circuit chips PIC are interconnected together through the optical interconnection network.
  • second optical waveguide may represent part or all of the optical interconnection network.
  • the second optical waveguide in the optical interconnect network on the substrate may include each types of optical waveguides.
  • Figure 2 shows a schematic diagram of an optical waveguide in an optical interconnection network in an optoelectronic packaging structure according to an embodiment of the present disclosure.
  • FIG. 2 shows an embedded optical waveguide embedded in the core layer of the substrate, and (b) in Figure 2 shows a combined optical waveguide formed on the first surface of the core layer of the substrate, And (c) in FIG. 2 shows a three-dimensional (3D) inscribed waveguide formed within the core layer of the substrate.
  • the second optical waveguide in the optical interconnection network on the substrate may be a single-layer waveguide as shown in (a)-(c) of Figure 2, or may be (as shown in Figure 2
  • the multilayer waveguide shown in d) can also be a combination of the above types of optical waveguides.
  • the photonic integrated circuit chip PIC and optical interconnection network arranged on the substrate can be optically coupled in various ways.
  • the electrical interconnection network and optical interconnection network in the optoelectronic packaging structure can be arranged or arranged in various ways.
  • FIG. 3 shows a schematic diagram of the first optical coupling method in the optoelectronic packaging structure 300 according to the embodiment of the present disclosure.
  • FIG. 3 only shows a schematic diagram of coupling between an EPIC chip including an EIC chip and a PIC chip and an optical interconnection network on a substrate.
  • the photonic integrated circuit chip PIC in the EPIC chip includes a plurality of first optical waveguides WG-1 embedded therein.
  • the optical interconnection network on the substrate includes a second optical waveguide WG-2 arranged on the core layer of the substrate as shown in FIG. 3 .
  • the material of the optical waveguides WG-1 and WG-2 may be silicon or silicon nitride.
  • the first optical waveguide WG-1 may include a first optical coupling part
  • the second optical waveguide may include a second optical coupling part (not shown in the figure).
  • the first optical waveguide WG-1 may be, for example, 1 and the end portions of the second optical waveguide WG-2 are regarded as respective optical coupling portions.
  • the photonic integrated circuit chip PIC is bonded to the upper surface of the substrate, so that the first optical waveguide WG-1 in the PIC chip and the second optical waveguide WG-2 on the core layer of the substrate are close to each other, for example, the first optical waveguide
  • the optical coupling portions of WG-1 and the second optical waveguide WG-2 are stacked in a direction perpendicular to the upper surface of the substrate and separated by a predetermined distance H (for example, less than 600 nm), so that the first optical waveguide WG-1 and the second
  • H for example, less than 600 nm
  • light from the second optical waveguide WG-2 on the left can be coupled through WG-2 into the first optical waveguide WG-1 in the PIC chip, and then, after being transmitted and processed in the PIC chip, again by the right
  • the first optical waveguide WG-1 is coupled to the second optical waveguide on the core layer of the substrate In WG-2, it is then coupled to other PIC chips in a similar manner to achieve optical interconnection between different PIC chips.
  • the adiabatic coupling between the PIC chip and the optical interconnect network is applicable to both embedded waveguide and combined waveguide types as described above with respect to Figure 2.
  • the adiabatic coupling when the adiabatic coupling method is used for optical coupling between the photonic integrated circuit chip PIC and the optical interconnection network, the adiabatic coupling requires the photonic integrated circuit chip and the optical interconnection network.
  • the networks fit closely together, and the electrical interconnection network is usually not arranged on the upper surface of the substrate, but only on the lower surface of the substrate.
  • the electrical interconnection network includes as shown in Figure 3 One or more electrical wiring layers 113-1.
  • FIG. 4 shows a schematic diagram of the second optical coupling method in the optoelectronic packaging structure 400 according to the embodiment of the present disclosure.
  • the optoelectronic packaging structure 400 shown in FIG. 4 may also include an array of beam redirecting elements 130 (for example, the two beam redirecting elements 130 shown in FIG. 4 ), which are is arranged in the substrate, and the height of the beam redirecting element 130 is appropriately adjusted (for example, by cutting a groove on the surface of the substrate) so that it is aligned with the second optical waveguide WG-2 in the optical interconnection network, thereby causing the beam to Each beam redirecting element in the array of redirecting elements 130 is configured to change the direction of the beam into the optical coupler of the second/first optical waveguide.
  • an array of beam redirecting elements 130 for example, the two beam redirecting elements 130 shown in FIG. 4
  • the height of the beam redirecting element 130 is appropriately adjusted (for example, by cutting a groove on the surface of the substrate) so that it is aligned with the second optical waveguide WG-2 in the optical interconnection network, thereby causing the beam to
  • Each beam redirecting element in the array of redirecting elements 130 is configured to change the direction
  • beam redirecting element 130 may be a prism as shown.
  • the prism is arranged in a groove on the upper surface of the core layer of the substrate, and its position and height are adjusted so that the light from the first optical waveguide WG-1 can enter the second optical waveguide WG-2 through refraction or reflection, or from The light of the second optical waveguide WG-2 can enter the first optical waveguide WG-1 through refraction or reflection, thereby realizing optical coupling between the PIC chip and the optical interconnection network.
  • the first optical waveguide WG- The optical coupling part of 1 and/or the second optical waveguide WG-2 can be configured with a grating coupler GC, so as to utilize the diffraction effect of the grating for optical coupling, thereby changing the direction of the light and achieving vertical coupling of the light.
  • FIG. 4 shows an example in which a grating coupler GC is arranged at the end of the first optical waveguide WG-1.
  • an optical interconnection network (for example, including the second optical waveguide WG-2 in FIG. 3) is arranged on the upper surface of the substrate, and an electrical interconnection network (for example, including a second optical waveguide WG-2 in FIG. 3) is arranged on the upper surface of the substrate.
  • a layer or layers of electrical wiring 113-1) are arranged on the lower surface of the substrate opposite the upper surface.
  • Figure 4 illustrates a different arrangement of the optical and electrical interconnection networks.
  • one or more electrical wiring layers 113-2 can also be arranged on the upper surface of the substrate as part of the electrical interconnection network.
  • the electrical interconnection network may include simultaneously one or more electrical wiring layers 113-1 on the lower surface of the core layer of the substrate, and one or more layers on the upper surface of the core layer of the substrate. Electrical wiring layer 113-2.
  • an optical interconnection network (for example, including the second optical waveguide WG-2 in FIG. 4) may be arranged on the upper surface of the substrate, and the second optical waveguide WG-2 is electrically interconnected in the network. Covered by one or more electrical wiring layers 113-2.
  • FIG. 5 shows a schematic diagram of an optical coupling method using photonic wire bonding in the optoelectronic packaging structure 500 according to an embodiment of the present disclosure.
  • an edge coupler EC is provided at the end of the first optical waveguide WG-1 of the photonic integrated circuit chip PIC, and the edge coupler EC of the first optical waveguide WG-1 and the second optical waveguide WG- 2 are optically coupled through photonic wire bonding (PWB).
  • PWB photonic wire bonding
  • metal wires are usually used to interconnect electronic integrated circuit chips.
  • optical wire bonding can be used to realize the interconnection between different photonic integrated circuit chips, photonic integrated circuit chips and optical networks.
  • the "wire" that plays the role of connection is no longer metal, but an optical waveguide.
  • the light outlet in the EC of the first optical waveguide WG-1 of the PIC chip can be optically connected to the entrance of the second optical waveguide WG-2 in the optical interconnection network through PWB.
  • the vertical coupling approach and photonic wire bonding approach as described above may also be applied to the embedded waveguide and modular waveguide types as described above with respect to Figure 2.
  • the electrical interconnection network can also be arranged at the same time. on the upper and lower surfaces of the substrate.
  • the optical interconnection network for example, including the first layer in FIG. 5
  • the two optical waveguides WG-2) and one or more electrical wiring layers 113-2 on the upper surface of the substrate are arranged at different positions on the upper surface of the substrate, instead of covering the electrical wiring layer on the upper surface of the substrate as shown in Figure 4. Above the two optical waveguides.
  • one or more electrical wiring layers 113-2 on the upper surface of the substrate may be disposed under and covered by the PIC chip, while an optical interconnect network is disposed on the remaining areas of the upper surface of the substrate where no electrical wiring layers are disposed.
  • the optical interconnection network is not covered by the electrical interconnection network as shown in Figure 4, and both are arranged side by side on the upper surface of the substrate.
  • the second optical waveguide in the optical interconnect network on the substrate may also comprise a 3D-written waveguide as described above with respect to Figure 2, for example, as a three-dimensional waveguide network formed in a glass layer, in which case Under this condition, grating couplers can also be used directly to achieve optical coupling between photonic integrated circuit chips and optical interconnection networks.
  • FIG. 6 shows a schematic diagram of the fourth optical coupling method in the optoelectronic packaging structure 600 according to the embodiment of the present disclosure.
  • the second optical waveguide WG-2 in the optical interconnection network on the substrate is a three-dimensional waveguide network.
  • the three-dimensional waveguide network is formed by inducing local glass inside the glass to increase the refractive index of the local glass.
  • Network structure For example, an ultrafast (e.g., femtosecond) laser inscription process can be used to create an embedded three-dimensional waveguide network inside the glass.
  • the photonic integrated circuit chip PIC further includes a grating coupler GC connected to the first optical waveguide, and the first optical waveguide is coupled to the three-dimensional waveguide network through the grating coupler GC.
  • the three-dimensional waveguide network shown in Figure 6 formed in a glass layer appended to the core layer of the substrate is schematic only.
  • a femtosecond laser can also be used directly in the core layer of the substrate to irradiate a preset position in the core layer to increase the refractive index at the preset position, so that the core layer
  • the three-dimensional waveguide network is formed within the layer.
  • three-dimensional waveguide networks is conducive to the formation of more abundant and efficient three-dimensional optical waveguide paths, which can further compress the volume of optoelectronic packaging structures.
  • the optical interconnection network (for example, including the one in Figure 6 The three-dimensional waveguide WG-2) and one or more electrical wiring layers 113-2 in the electrical interconnection network are arranged at different locations on the upper surface of the substrate.
  • the optical interconnection network and the electrical interconnection network are also arranged side by side at different positions on the upper surface of the substrate.
  • the above describes various optical coupling methods between the photonic integrated circuit chip and the optical interconnection network in the optoelectronic packaging structure, as well as the arrangement methods of various optical interconnection networks and electrical interconnection networks.
  • Each coupling method has its own obvious advantages. Different coupling methods can be used at different locations in the same package as needed, or different coupling methods can be used in different packages.
  • adiabatic coupling has the advantage of compressing the packaging volume due to the tight fit between the photonic integrated circuit chip and the substrate.
  • the vertical coupling method using beam redirection elements can change the propagation direction of light, and the chip layout can be more flexible.
  • the photonic wire bonding method has low insertion loss and relatively low requirements for device alignment, saving lenses required for beam shaping.
  • the preparation is simple and fast, which is conducive to large-scale production.
  • Grating coupling using a three-dimensional waveguide network is conducive to forming a richer and more efficient three-dimensional optical waveguide path, which can further compress the volume of the optoelectronic packaging structure.
  • Those skilled in the art can select appropriate optical coupling methods or combinations thereof as needed, and various combination methods also fall within the protection scope of the present disclosure.
  • the electrical interconnection network and the optical interconnection network are described above in conjunction with various optical coupling methods between the photonic integrated circuit chip and the optical interconnection network, this is only exemplary. In practice, the electrical interconnection network and the optical interconnection network can be rationally arranged in combination with other factors, thereby further compressing the volume of the optoelectronic package and improving the processing efficiency while realizing the optical interconnection and electrical interconnection.
  • the specific structure of the electrical interconnection network can also be rationally designed based on specific applications. For example, whether one or multiple electrical wiring layers need to be arranged, whether it should be arranged on one side or both sides of the substrate, and between multiple wiring layers. Whether interconnect structures are required and so on.
  • the electrical interconnection network may also include simultaneous connections.
  • One or more blind vias of a multilayer electrical wiring layer used to electrically interconnect the multilayer electrical wiring layers on one side surface.
  • one or more grooves may be provided on the upper surface of the core layer of the substrate for arranging some chips in the chip array therein or on it.
  • the light source LS as shown in FIG. 10 may be arranged in a groove on the upper surface of the core layer of the substrate, which will be described in detail later.
  • one or more electrical wiring layers may be disposed in some grooves as part or all of the electrical interconnection network.
  • the electrical interconnection network may also include one or more electrical wiring layers 113-3 disposed in grooves in the core layer of the substrate as shown in FIG. 10 .
  • the optical interconnection network can be arranged, for example, in an area not occupied by the grooves on the first surface (upper surface) of the substrate.
  • the photonic integrated circuit chip PIC may be disposed over and covering the groove in which one or more electrical wiring layers 113 - 3 are disposed.
  • the purpose of providing such a groove is that the first optical waveguide WG-1 in the PIC and the second optical waveguide WG-2 on the core layer need to be in close contact to achieve adiabatic coupling of light, while the conductive conductivity of the EIC above the PIC
  • the via is usually located on the lower surface of the PIC, and the upper surface of the substrate needs to form electrical connection structures such as conductive bumps.
  • the conductive bumps are usually thicker after bonding, which will affect the first optical waveguide WG-1 and the second optical waveguide WG-2
  • the distance between them, forming a groove under the PIC can accommodate the conductive bumps in the groove, thereby solving the problem of the excessive distance between the first waveguide WG-1 and the second waveguide WG-2, and can Electrical wiring is carried out in the grooves, thereby increasing the electrical wiring density.
  • the electrical interconnection network may include one or more electrical wiring layers in the upper surface, the lower surface, and the grooves of the upper surface of the core layer of the substrate, the arrangement of the electrical interconnection network need not be Choose from a variety of arrangements and their combinations.
  • the electrical interconnection network may include only one or more electrical wiring layers on the lower surface of the core layer of the substrate, as shown in 2.
  • the electrical interconnection network may include one or more electrical wiring layers on a lower surface of the core layer of the substrate and one or more electrical wiring layers on an upper surface of the core layer of the substrate, as shown in FIG. 4 .
  • the electrical interconnection network may include one or more electrical wiring layers on a lower surface of the core layer of the substrate and one or more electrical wiring layers in recesses on an upper surface of the core layer of the substrate, such as As shown in Figure 10.
  • an electrical interconnection network can also consist only of The one or more electrical wiring layers on the upper surface of the core layer of the substrate may only include one or more electrical wiring layers in the grooves on the upper surface of the core layer of the substrate, or may include the above three electrical wiring layers at the same time combination of layers.
  • the optoelectronic packaging structure can also include various other types of chips according to specific needs, including but not limited to temperature control chips, power control chips, light source chips, and so on.
  • the optical coupling method between the light source and the photonic integrated circuit chip when the optoelectronic package structure includes a light source chip (hereinafter referred to as "light source”) will be described below with reference to the accompanying drawings.
  • the optoelectronic packaging structure of embodiments of the present disclosure includes a light source
  • the light source is configured to provide light to a photonic integrated circuit chip in the optoelectronic packaging structure.
  • 7 to 12 illustrate schematic diagrams of various light source coupling methods in the optoelectronic packaging structure according to embodiments of the present disclosure.
  • the coupling methods of light sources in this disclosure can be roughly divided into three categories, namely self-aligned coupling methods, photonic wire bonding methods and free space optical coupling methods. Depending on whether the light from the light source is directly coupled to the photonic integrated circuit chip or directly coupled to the optical interconnection network, the coupling method of the light source of the present disclosure can be divided into six specific methods as shown in Figures 7-12.
  • FIG. 7 shows a schematic diagram of the first light source coupling method in the optoelectronic packaging structure 700 according to the embodiment of the present disclosure, that is, coupling the light source into the photonic integrated circuit chip in a self-aligned manner.
  • the light source LS is arranged on the upper surface of the substrate and is located near the photonic integrated circuit chip PIC.
  • the light emitted by the light source LS is self-aligned into the edge coupler EC of the photonic integrated circuit chip PIC, thereby making the light source LS Provides light to the photonic integrated circuit chip PIC.
  • FIG. 8 shows a schematic diagram of the second light source coupling method in the optoelectronic packaging structure 800 of the embodiment of the present disclosure, that is, coupling the light of the light source into the optical interconnection network in a self-aligned manner, and then through adiabatic coupling. Coupled again into the photonic integrated circuit chip, thereby providing light to the photonic integrated circuit chip.
  • the light source LS is also arranged on the upper surface of the substrate, but there is also a second optical waveguide WG-2 in the optical interconnection network between the light source LS and the photonic integrated circuit chip PIC.
  • the light emitted by the light source LS is self-aligned into the second optical waveguide WG-2.
  • the second optical waveguide WG-2 is used with the first optical waveguide WG-1 in the photonic integrated circuit chip Optical coupling is performed in an adiabatic coupling manner, so that the light source LS provides light to the photonic integrated circuit chip PIC.
  • the light source alignment coupling method as shown in Figure 7-8 has high requirements on device alignment, requiring precise design and layout of the height of each chip, the height of the optical interconnection network, and the plane layout. Its advantage is that it saves lenses required for beam shaping and has a compact structure, which is conducive to further compression of the volume of the optoelectronic packaging structure.
  • FIG. 9 shows a schematic diagram of the third light source coupling method in the optoelectronic packaging structure 900 according to the embodiment of the present disclosure, that is, coupling the light of the light source into the photonic integrated circuit chip through photonic wire bonding.
  • the light source LS is also arranged on the upper surface of the substrate and is located near the photonic integrated circuit chip.
  • the light emitted by the light source LS is directly coupled into the edge coupler EC of the photonic integrated circuit chip PIC, so that the light source LS provides light to the photonic integrated circuit chip PIC.
  • FIG. 10 shows a schematic diagram of the fourth light source coupling method in the optoelectronic packaging structure 1000 according to the embodiment of the present disclosure, that is, the light of the light source is coupled into the optical interconnection network through photonic wire bonding, and then through thermal insulation. The coupling is coupled again into the photonic integrated circuit chip, thereby providing light to the photonic integrated circuit chip.
  • the light source in order to keep the light source LS and the second optical waveguide WG-2 in the optical interconnection network at approximately the same height, the light source can be arranged in a groove on the upper surface of the substrate, and the light source can be connected by using a PWB.
  • the light emitted by the LS is directly coupled to the second optical waveguide WG-2 in the optical interconnection network, and then the second optical waveguide WG-2 and the first optical waveguide WG-1 in the photonic integrated circuit chip use an adiabatic coupling method to conduct light transmission. Coupling, so that the light source LS provides light to the photonic integrated circuit chip PIC.
  • the adiabatic coupling method between the second optical waveguide WG-2 shown in Figure 10 and the first optical waveguide WG-1 in the photonic integrated circuit chip is only exemplary, and may also be adopted. Vertical coupling, photonic wire bonding and other methods as mentioned above realize optical coupling between the optical interconnect network and the photonic integrated circuit chip.
  • FIG. 11 shows a schematic diagram of the fifth light source coupling method in the optoelectronic packaging structure 1100 of the embodiment of the present disclosure, that is, using a beam shaping element to couple the light of the light source into the photonic integrated circuit chip.
  • the light source LS is also arranged on the upper surface of the substrate and is located near the photonic integrated circuit chip.
  • the beam shaping element 140 is arranged between the light source LS and the photonic integrated circuit chip.
  • FIG. 12 shows a schematic diagram of the sixth light source coupling method in the optoelectronic packaging structure 1200 of the embodiment of the present disclosure, that is, using a beam shaping element to couple the light of the light source into the optical interconnection network, and then again through adiabatic coupling. Coupled into the photonic integrated circuit chip, thereby providing light to the photonic integrated circuit chip.
  • the light source LS and the beam shaping element 140 can be arranged on the upper surface of the substrate.
  • the light emitted by the light source LS is aligned into the second optical waveguide WG-2 in the optical interconnection network by using the beam shaping element 140, and then the second optical waveguide WG-2 is connected to the photonic integrated circuit chip
  • the first optical waveguide WG-1 uses adiabatic coupling for optical coupling, so that the light source LS provides light to the photonic integrated circuit chip PIC.
  • the light sources LS may be light sources with a temperature control function as shown in FIG. 13 .
  • the light source LS may include a laser LS-1 configured to emit light; a light source substrate LS-2 for arranging or carrying the laser LS-1; and a temperature controller TEC arranged between the laser LS-1 and the light source. underneath the substrate LS-2, and is configured to control the wavelength of light emitted by the laser LS-1 by adjusting the temperature of the laser LS-1.
  • the light source with a temperature control function as described above is only exemplary and not restrictive.
  • the optoelectronic packaging structure in the embodiments of the present disclosure may also include various other types of light sources.
  • FIG 14 shows a schematic diagram of a photonic computing system 1400 according to an embodiment of the present disclosure.
  • Figure 15 shows a schematic diagram of another photonic computing system 1500 in accordance with an embodiment of the present disclosure.
  • Figure 14 when the photonic computing system 1400 adopts the aforementioned optoelectronic packaging structure that does not include a built-in light source chip (for example, the optoelectronic packaging structure shown in Figures 1-4), Figure 14 can be used An external light source LS is shown providing light to the optoelectronic package structure 1410.
  • the printed circuit board PCB is configured to carry the optoelectronic packaging structure 1410 and other components. As shown, the printed circuit board PCB is electrically connected to solder structures on the lower surface of the substrate of the optoelectronic package structure 1410 .
  • the light source LS and other components are also arranged on the printed circuit board PCB.
  • the external light source LS is arranged near the optoelectronic packaging structure 1410 to provide light for the optoelectronic packaging structure 1410 .
  • the external light source LS and the optoelectronic packaging structure 1410 can also be arranged with similar beam shaping elements 140 to collimate the light emitted by the external light source LS so that it can be coupled into the optoelectronic packaging structure 1410 with higher coupling efficiency. .
  • the manner in which the beam shaping element is used to couple the light from the external light source LS to the PIC in the optoelectronic packaging structure 1410 shown in FIG. 14 is only exemplary. In the case of using an external light source LS, optical coupling between the light source and the optoelectronic packaging structure 1410 can also be achieved in a manner similar to any of the methods shown in Figures 7 to 12, which will not be described again.
  • the photonic computing system 1400 may also include other optical components. chemical or electronic components.
  • the photonic computing system 1400 may also include a power controller PC as shown in FIG. 14 to control the power consumption of the entire photonic computing system 1400.
  • the photonic computing system 1500 shown in Figure 15 can adopt an optoelectronic packaging structure including a built-in light source chip (for example, the optoelectronic packaging structure shown in Figures 7-13).
  • the printed circuit board PCB is configured to carry the optoelectronic packaging structure 1510 and other components. As shown, the printed circuit board PCB is electrically connected to solder structures on the lower surface of the substrate of the optoelectronic package structure 1510 .
  • the optoelectronic packaging structure 1510 itself includes a built-in light source, no additional external light source is needed to provide it with light.
  • other components can also be arranged on the printed circuit board PCB.
  • the photonic computing system 1500 may also include a power controller PC as shown in FIG. 15 to control the power consumption of the entire photonic computing system 1500.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • General Engineering & Computer Science (AREA)
  • Optics & Photonics (AREA)
  • Architecture (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Optical Integrated Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

一种光电封装结构（100/300/400/500/600/700/800/900/1000/1100/1200/1410/1510）和光子计算系统（1400/1500）。光电封装结构（100/300/400/500/600/700/800/900/1000/1100/1200/1410/1510）包括：基板（110），包括核心层（111）、光互连网络（112）以及电互连网络（113）；以及芯片阵列（120），布置在基板（110）的第一表面上，包括至少一个光芯片和至少一个电芯片；光芯片通过光互连网络（112）进行光互连，电芯片通过电互连网络（113）进行电互连。至少一个光芯片和至少一个电芯片中部分或全部光芯片和电芯片形成包括光芯片和电芯片的电子-光子混合芯片，并且电互连网络（113）包括贯穿基板（110）的一个或多个第二导电通孔，基板的第二表面具有用于焊接到印刷电路板的焊接结构（114），焊接结构（114）与电互连网络（113）电连接。

Description

光电封装结构和光子计算系统
相关申请的交叉引用
本申请要求于2022年7月6日提交的申请号为202210796603.1的中国专利申请的优先权。
技术领域
本公开涉及半导体领域，更具体而言，涉及一种光电封装结构和光子计算系统。
背景技术
硅电子集成电路的发展得益于几十年来在光刻技术和其他制造创新方面的一代又一代改进，其中的晶体管的性能和互连密度在不断增加。随着时间的推移，硅电子集成电路的性能越来越接近技术的物理极限，改进的步伐已经放缓。行业专家已经使用先进的封装技术来克服这一限制，通过扩展可用面积或体积来电连接多个硅集成电路，或者将多个硅集成电路并排放置，或者将多个硅集成电路堆叠在一起，或者将这两种技术进行各种组合。虽然这些技术通过聚合更多的硅为可扩展性注入了新的活力，但它们仍然受到芯片尺寸和用于芯片间通信的可用相邻表面或边缘的限制，并存在组装模块在冷却和供电方面的问题。
发明内容
鉴于上述问题，本公开提供一种光电封装结构和光子计算系统，通过在基板上使用光信号，以更高的单位面积带宽以及不受硅邻接限制的更完全连接的拓扑，大幅扩展计算和互连能力。
本公开的第一方面提供了一种光电封装结构，包括：基板，包括核心层、光互连网络以及电互连网络；以及芯片阵列，布置在所述基板的第一表面上，包括至少一个光子集成电路芯片和至少一个电子集成电路芯片；所述光子集成电路芯片通过所述光互连网络进行光互连，所述电子集成电 路芯片通过所述电互连网络进行电互连。所述至少一个光子集成电路芯片和至少一个电子集成电路芯片中部分或全部光子集成电路芯片和电子集成电路芯片形成包括光子集成电路芯片和电子集成电路芯片的电子-光子混合芯片，并且所述电互连网络包括贯穿所述基板的一个或多个第二导电通孔，所述基板的第二表面具有用于焊接到印刷电路板的焊接结构，所述焊接结构与所述电互连网络电连接。
在一些实施例中，所述电子-光子混合芯片中的光子集成电路芯片具有贯穿其中的一个或多个第一导电通孔，所述一个或多个第一导电通孔与所述电互连网络电连接，所述电子-光子混合芯片中的电子集成电路芯片布置在所述光子集成电路芯片的上表面上并且与所述一个或多个第一导电通孔电连接。
在一些实施例中，所述光子集成电路芯片中布置有第一光波导，所述光互连网络包括第二光波导，并且所述光子集成电路芯片与所述光互连网络之间通过所述第一光波导和所述第二光波导进行光耦合。
在一些实施例中，所述第一光波导与所述第二光波导在垂直于所述基板的第一表面的方向上叠置且间隔预定距离，使得所述第一光波导和所述第二光波导实现光的绝热耦合。
在一些实施例中，该光电封装结构还包括：光束重定向元件的阵列，其被布置在所述基板中，所述光束重定向元件的阵列中的每个光束重定向元件被配置为改变光束的方向以使其进入第二/第一光波导的光耦合器中。
在一些实施例中，所述光子集成电路芯片还包括连接到所述第一光波导的边缘耦合器，所述第一光波导的边缘耦合器和所述第二光波导之间通过光子引线键合的方式进行光耦合。
在一些实施例中，所述第二光波导包括以下至少之一：a.嵌入在所述基板的核心层中的一层或多层光波导；b.形成在所述基板的核心层的第一表面上的一层或多层光波导；和c.形成在所述基板的核心层内的三维波导网络。
在一些实施例中，在所述第二光波导包括所述三维波导网络的情况下，所述光子集成电路芯片还包括连接到所述第一光波导的光栅耦合器，所述第一光波导通过所述光栅耦合器耦合到所述三维波导网络。
在一些实施例中，所述光电封装结构，还包括：光源，其被配置为向所述光子集成电路芯片提供光。
在一些实施例中，所述光源被设置在所述基板的第一表面上，并且所述光源通过与所述光子集成电路芯片中的第一光波导的边缘耦合器对齐，进而向所述光子集成电路芯片提供光。
在一些实施例中，所述光源被设置在所述基板的第一表面的凹槽中，并且所述光源通过与所述光互连网络中的第二光波导的边缘耦合器对齐，进而向所述光子集成电路芯片提供光。
在一些实施例中，所述光源被设置在所述基板的第一表面上，并且所述光源通过光子引线键合的方式将光耦合到所述光子集成电路芯片中的第一光波导的光耦合器中，进而向所述光子集成电路芯片提供光。
在一些实施例中，所述光源被设置在所述基板的第一表面的凹槽中，并且所述光源通过光子引线键合的方式将光耦合到所述光互连网络中的第二光波导的光耦合器中，进而向所述光子集成电路芯片提供光。
在一些实施例中，所述光源被设置在所述基板的第一表面上，并且所述光电封装结构还包括：光束整形元件，其被布置在所述基板的第一表面上，位于所述光源和所述光子集成电路芯片之间，其中，所述光源通过所述光束整形元件将光耦合到所述光子集成电路芯片的第一光波导的光耦合器中，进而向所述光子集成电路芯片提供光。
在一些实施例中，所述光源被设置在所述基板的第一表面的凹槽中，并且所述光电封装结构还包括：光束整形元件，其被布置在所述凹槽中，位于所述光源和所述光互连网络中的第二光波导之间，其中，所述光源通过所述光束整形元件将光耦合到所述第二光波导的光耦合器中，进而向所述光子集成电路芯片提供光。
在一些实施例中，所述光源包括：激光器，其被配置为发射光；温度控制器，其布置在所述激光器下方，并且被配置为通过调节所述激光器的温度来控制所述激光器发射的光的波长。
在一些实施例中，所述电互连网络包括布置在所述基板的核心层的第二表面上的一层或多层电布线层。
在一些实施例中，所述电互连网络还包括布置在所述基板的核心层 的第一表面上的一层或多层电布线层。
在一些实施例中，所述芯片阵列中的至少一些芯片被设置在基板的第一表面上的凹槽上方并覆盖所述凹槽，所述电互连网络还包括布置在所述凹槽中的一层或多层电布线层，并且所述光互连网络被布置在所述基板的第一表面上未被所述凹槽占据的区域中。
在一些实施例中，所述芯片阵列包括一个或多个存储芯片。
在一些实施例中，所述基板的核心层的材料为玻璃、硅或陶瓷。
本公开的第二方面提供了一种光子计算系统，其包括如前所述的光电封装结构，所述光子计算系统还包括：光源，其被配置为向所述光电封装结构提供光；以及印制电路板，其被配置为承载所述光电封装结构，并且与所述基板的第二表面上的焊接结构电连接。
本公开的第三方面提供了一种光子计算系统，其包括如前所述光电封装结构，所述光子计算系统还包括：印制电路板，其被配置为承载所述光电封装结构，并且与所述基板的第二表面上的焊接结构电连接。
本公开提出的光电封装结构通过利用光的速度、功率、效率以及芯片阵列版式为下一代高性能AI计算任务提供动力，为新的计算范式提供平台。该平台基于面板式可扩展，克服了晶圆刻线限制和晶圆尺寸限制。它将在芯片带宽方面带来重大突破，优于所有现有的CPU/GPU带宽。本公开中提出的面板式基板可扩展至310×310mm2、510×510mm2，甚至更大，相比之下，当前的芯片仅可扩展至100×100mm2，晶圆也仅可扩展至12英寸。通过光处理信息，本公开中提出的光电封装结构将提供超高速、低延迟和低功耗的AI计算，与传统电子架构相比，将有几个数量级的改进。
附图说明
图1示出了本公开的实施例的光电封装结构的整体配置的示意图。
图2示出了本公开的实施例的光电封装结构中光互连网络中的光波导的示意图。
图3示出了本公开的实施例的光电封装结构中第一种光耦合方式的示意图。
图4示出了本公开的实施例的光电封装结构中第二种光耦合方式的示意图。
图5示出了本公开的实施例的光电封装结构中第三种光耦合方式的示意图。
图6示出了本公开的实施例的光电封装结构中第四种光耦合方式的示意图。
图7示出了本公开的实施例的光电封装结构中第一种光源耦合方式的示意图。
图8示出了本公开的实施例的光电封装结构中第二种光源耦合方式的示意图。
图9示出了本公开的实施例的光电封装结构中第三种光源耦合方式的示意图。
图10示出了本公开的实施例的光电封装结构中第四种光源耦合方式的示意图。
图11示出了本公开的实施例的光电封装结构中第五种光源耦合方式的示意图。
图12示出了本公开的实施例的光电封装结构中第六种光源耦合方式的示意图。
图13示出了本公开的实施例的光电封装结构中光源的结构的示意图。
图14示出了本公开的实施例的光子计算系统的示意图。
图15示出了本公开的实施例的另一光子计算系统的示意图。
具体实施方式
下面将参照附图详细地描述本公开的实施例。虽然附图中示出了本公开的一些实施例，然而，应当理解的是，本公开不应该被解释为限于这里阐述的实施例，相反地，提供这些实施例是为了更加透彻和完整地理解本公开。应当理解的是，本公开的附图及实施例仅用于示例性作用，并非用于限制本公开的保护范围。
应当理解的是，本公开的实施方式中记载的各个元件、组件在一些 情况下可以省略，并且本公开的实施例可以包括其它的元件、组件。此外，应当理解的是，各个实施例中描述的各种元件、组件或耦合方式可以相互组合，除非上下文明确表示相反或明显不适用。
本公开的实施例提供了一种光电封装结构。图1示出了本公开的实施例的光电封装结构100的整体配置的示意图。为了更清楚地理解本公开，图1在(a)中示出了本公开的实施例的光电封装结构100的俯视图，在(b)中示出了光电封装结构100在第一方向上的剖面图，在(c)中示出了光电封装结构100在第二方向上的剖面图，并且(d)中示出了光电封装结构100的局部细节剖面图。
如图1中的(a)至(c)所示，光电封装结构100包括基板110和芯片阵列120。
基板110是承载和互连芯片阵列120并用于安装到印刷电路板(PCB)上的面板。基板110的尺寸可以制作得较大，例如可扩展至310×310mm2、510×510mm2，甚至更大，从而克服晶圆刻线限制和晶圆尺寸限制，为光电芯片的封装提供更大的封装面积。本公开实施例的基板110可以直接使用现有的玻璃板、陶瓷板或硅基板，从而达到较大的面积，并可以直接安装到PCB上。而由此形成的基板的厚度主要取决于制备导电通孔的工艺，目前导电通孔的工艺可以做得1微米，因此优选地，可以将这样的基板形成为具有较大的厚度，例如等于或大于1微米，以实现足够的强度。随着制备导电通孔的工艺技术的成熟，基板的厚度可以做得更加大，厚度较大的基板具有刚性大、不容易翘曲等优点。
如图1中的(d)所示，基板110在结构上可以包括核心层111、光互连网络112以及电互连网络113。核心层111的材料可以例如为玻璃、硅或陶瓷等。例如，可以在核心层111上先布设一层光学盖层材料，再布设波导材料，从而形成光互连网络112。例如，还可以在核心层111的下表面上布置至少一层电布线层，从而形成电互连网络113。
如图1的(a)中所示，光电封装结构100中的芯片阵列120可以包括至少一个光子集成电路(PIC)芯片和至少一个电子集成电路(EIC)芯片，它们布置在基板110的第一表面(例如，上表面)上，形成芯片的二维阵列。
在芯片阵列120包括多个光子集成电路芯片的情况下，多个光子集成电路芯片之间可以通过如上所述的光互连网络112进行光互连。此外，在芯片阵列120包括多个电子集成电路芯片的情况下，多个电子集成电路芯片可以通过如上所述的电互连网络113进行电互连。
在一些实施例中，为了进一步压缩封装体积，芯片阵列120中的至少一个光子集成电路芯片和至少一个电子集成电路芯片可以形成包括光子集成电路芯片和电子集成电路芯片的电子-光子混合芯片，例如，如图1中所示的EPIC，图1中的(d)示出了一个EPIC以及对应的基板部分的局部剖面图。
如图1中的(d)所示，电子-光子混合芯片EPIC中的光子集成电路芯片PIC具有贯穿其中的一个或多个导电通孔TDV，一个或多个导电通孔TDV与电互连网络113(例如，通过核心层111中的TGV)电连接。此外，如图所示，电子-光子混合芯片EPIC中的电子集成电路芯片EIC布置在光子集成电路芯片PIC的上表面上并且与一个或多个导电通孔TDV电连接。
需要说明的是，这里的术语“电子-光子混合芯片”并不意味着要采用除了如前所述的光子集成电路芯片和电子集成电路芯片之外的其它芯片，而是意味着光子集成电路芯片PIC和电子集成电路芯片EIC可以相互堆叠并连接形成整体结构，例如小芯片(chip-let)，从而将该整体结构布置在基板110上，作为芯片阵列120中的部分或全部芯片。
“电子-光子混合芯片”本身可以采用各种不同的方式形成。例如，可以在PIC芯片的上表面上布置多个第一电连接件，并且在EIC芯片的下表面上可以对应地布置多个第二电连接件，PIC芯片和EIC芯片通过第一电连接件和第二电连接件直接键合，从而形成“电子-光子混合芯片”的整体结构。可选地，电子-光子混合芯片也可以是包含一个PIC芯片和多个EIC芯片(例如，数字电子集成电路芯片(D-EIC)和模拟电子集成电路芯片(A-EIC))的整体结构，D-EIC芯片、A-EIC芯片和PIC芯片之间也可以通过如上所述第一电连接件和第二电连接件直接键合。此外，还可以利用倒装焊的连接方式键合将EIC芯片倒装到PIC芯片之上，从而形成如上所述的电子-光子混合芯片。形成“电子-光子混合芯片”不限于以上方式， 还可以采用各种其他方式形成“电子-光子混合芯片”的整体结构，再此不再详细展开。
此外，如图1的(d)所示，基板110的下表面上还具有用于焊接到印刷电路板的焊接结构114，焊接结构114与电互连网络113电连接。例如，焊接结构114可以是多个LGA焊盘或BGA焊球。
图1示出的光电封装结构100中的芯片阵列除了包括如上所述的EIC芯片、PIC芯片、或EPIC芯片之外，还可以包括其他类型的芯片。例如，光电封装结构100还可以包括一个或多个存储芯片，例如，如图1所示的高带宽存储芯片HBM芯片。应当理解的是，如图1所示的EIC芯片、PIC芯片、EPIC芯片和HBM芯片仅仅是众多芯片中的一些示例，根据本公开的实施例的光电封装结构100还可以根据具体需要包含其他各种类型的芯片，包括但不限于温度控制芯片、功率控制芯片、光源芯片等等。
芯片阵列120的各个芯片之间通过电互连网络113进行电互连，并且通过光互连网络112进行光互连。在一些实施例中，电互连网络113还包括贯穿基板的核心层111的一个或多个导电通孔。
例如，如图1中的(d)所示，当核心层材料为玻璃的情况下，一个或多个导电通孔为如图所示的贯穿玻璃通孔(TGV)。或者，当核心层材料为陶瓷的情况下，一个或多个导电通孔可以是贯穿陶瓷通孔(TCV)。或者，当核心层材料为硅的情况下，一个或多个导电通孔可以是贯穿硅通孔(TSV)。
如上所述，布置在基板110上的多个光子集成电路芯片PIC之间可以通过光互连网络112进行光互连。以下将结合图2至图6详细描述多个PIC芯片之间通过光互连网络进行光互连的具体实现方式。
通常情况下，光子集成电路芯片PIC中布置有用于进行光传输的第一光波导，并且基板上的光互连网络通常包括第二光波导。光子集成电路芯片PIC与光互连网络之间可以通过第一光波导和第二光波导进行光耦合，进而通过光互连网络将多个光子集成电路芯片PIC互连在一起。
需要说明的是，在下文中提到的术语“第二光波导”可以表示光互连网络的一部分或全部。
在一些实施例中，基板上的光互连网络中的第二光波导可以包括各 种类型的光波导。图2示出了本公开的实施例的光电封装结构中光互连网络中的光波导的示意图。
图2中的(a)示出了嵌入在基板的核心层中的嵌入式光波导，图2中的(b)示出了形成在基板的核心层的第一表面上的组合式光波导，并且图2中的(c)示出了形成在基板的核心层内的三维(3D)刻写波导。
在一些实施例中，基板上的光互连网络中的第二光波导可以是如图2中的(a)-(c)中所示的单层波导，也可以是如图2中的(d)中所示的多层波导，也可以是以上各种类型的光波导的组合。
取决于不同的光波导类型和不同的设计需求，布置在基板上的光子集成电路芯片PIC和光互连网络可以通过各种方式进行光耦合。取决于不同的光耦合方式，又可以有多种方式排列或布置光电封装结构中的电互连网络和光互连网络。
图3示出了本公开的实施例的光电封装结构300中第一种光耦合方式的示意图。简单起见，图3仅示出了一个包含EIC芯片和PIC芯片的EPIC芯片与基板上的光互连网络之间进行耦合的示意图。
如图3所示，EPIC芯片中的光子集成电路芯片PIC包括嵌入其中的多个第一光波导WG-1。基板上的光互连网络包括如图3所示的布置在基板的核心层上的第二光波导WG-2。在一些示例中，光波导WG-1和WG-2的材料可以为硅或者氮化硅。
具体地，第一光波导WG-1可包括第一光耦合部，并且第二光波导可包括第二光耦合部(图中未示出)，简单起见，可将例如第一光波导WG-1和第二光波导WG-2的端部视为各自的光耦合部。光子集成电路芯片PIC被贴合到基板的上表面上，使得PIC芯片中的第一光波导WG-1与基板的核心层上的第二光波导WG-2彼此靠近，例如，第一光波导WG-1和第二光波导WG-2的光耦合部在垂直于基板的上表面的方向上叠置且间隔预定距离H(例如，小于600nm)，使得第一光波导WG-1和第二光波导WG-2的光耦合部之间能够实现光的绝热耦合。
例如，来自左侧第二光波导WG-2的光可以通过WG-2耦合到PIC芯片中的第一光波导WG-1中，然后在PIC芯片中进行传输和处理之后，再次由右侧的第一光波导WG-1耦合到基板的核心层上的第二光波导 WG-2中，进而以类似的方式再耦合到其他PIC芯片中，从而实现不同PIC芯片之间的光互连。
PIC芯片和光互连网络之间的绝热耦合方式可适用于如上关于图2所述的嵌入式波导和组合式波导类型。
此外，还需要说明的是，如图3所示，当采用绝热耦合方式进行光子集成电路芯片PIC与光互连网络之间的光耦合的情况下，由于绝热耦合要求光子集成电路芯片和光互连网络之间紧密贴合，通常不会在基板的上表面上布置电互连网络，而是仅将电互连网络布置在基板的下表面上，例如，电互连网络包括如图3所示的一层或多层电布线层113-1。
以上结合图3描述了PIC芯片和光互连网络之间的绝热耦合方式的各种配置，通过该耦合方式可以实现多个光子集成电路芯片之间的光互连。这种使用绝热耦合的技术对多个光子集成电路芯片进行光互连的封装结构由于光子集成电路芯片和基板之间的紧密贴合，有益于压缩封装结构的整体体积。
除了如上所述的绝热耦合方式之外，还可以采用光束重定向元件实现PIC芯片和光互连网络之间的光耦合。图4示出了本公开的实施例的光电封装结构400中第二种光耦合方式的示意图。
相比图3中的光电封装结构300，如图4所示的光电封装结构400还可以包括光束重定向元件130的阵列(例如，图4示出的两个光束重定向元件130)，其被布置在基板中，并且光束重定向元件130的高度被适当调整(例如，通过在基板上表面开槽)，使其与光互连网络中的第二光波导WG-2对准，进而使得光束重定向元件130的阵列中的每个光束重定向元件被配置为改变光束的方向以使其进入第二/第一光波导的光耦合器中。
在一些实施例中，光束重定向元件130可以是如图所示的棱镜。该棱镜被布置在基板的核心层上表面的凹槽中，并且其位置和高度被调整使得来自第一光波导WG-1的光可以通过折射或反射进入第二光波导WG-2，或者来自第二光波导WG-2的光可以通过折射或反射进入第一光波导WG-1，从而实现PIC芯片和光互连网络之间的光耦合。
在采用光束重定向元件130进行光耦合的情况下，第一光波导WG- 1和/或第二光波导WG-2的光耦合部可以配置光栅耦合器GC，从而利用光栅的衍射效应进行光耦合，进而改变光的方向，实现光的垂直耦合。图4示出了第一光波导WG-1的端部配置有光栅耦合器GC的示例。
相比与图3中将光互连网络(例如，包括图3中的第二光波导WG-2)布置在基板的上表面上，并且将电互连网络(例如，包括图3中的一层或多层电布线层113-1)布置在与上表面相对的基板的下表面上，图4示出了光互连网络和电互连网络的另一种不同布置方式。
例如，如图4所示，由于光子集成电路芯片PIC和光互连网络之间没有采用绝热耦合方式进行光耦合，在这种情况下，不需要控制使得光子集成电路芯片PIC中的第一光波导和光互连网络距离很近，因此基板的上表面上也可以布置一层或多层电布线层113-2，作为电互连网络的一部分。例如，如图所示，电互连网络可以同时包括基板的核心层的下表面上的一层或多层电布线层113-1、以及基板的核心层的上表面上的一层或多层电布线层113-2。
在这种情况下，可以将光互连网络(例如，包括图4中的第二光波导WG-2)布置在基板的上表面上，并且第二光波导WG-2被电互连网络中的一层或多层电布线层113-2覆盖。
除了如上所述的绝热耦合和采用光束重定向元件垂直耦合方式之外，还可以采用光子引线键合(又称为PWB)的方式实现PIC和光互连网络之间的光耦合。图5示出了本公开的实施例的光电封装结构500中采用光子引线键合的光耦合方式的示意图。
如图5所示，光子集成电路芯片PIC的第一光波导WG-1的端部设置有边缘耦合器EC，所述第一光波导WG-1的边缘耦合器EC和第二光波导WG-2之间通过光子引线键合(PWB)的方式进行光耦合。
在集成电路中，通常使用金属打线的方法实现电子集成电路芯片间的互连。借鉴金属打线的思路，光学引线键合可以用于实现不同光子集成电路芯片、光子集成电路芯片与光网络之间的互连。相比金属打线，起到连接作用的“线”不再是金属，而是光波导。例如，如图5所示，可以通过PWB将PIC芯片的第一光波导WG-1的EC中的出光口与光互连网络中的第二光波导WG-2的入口光相连。该方案避免了传统方案中耗时较多的 对准调节，节省了光束整形所需的透镜等，并且制备简单快捷，利于大规模的生产。
如上所述的垂直耦合方式和光子引线键合方式也可适用于如上关于图2所述的嵌入式波导和组合式波导类型。
此外，如图5所示，当采用光子引线键合进行光子集成电路芯片PIC与光互连网络之间的光耦合(稍后会详细描述)的情况下，电互连网络也可以同时布置在基板的上下两个表面上。在上表面上布置有电互连网络的一层或多层电布线层113-2的情况下，为了使光子引线键合易于操作，可以将光互连网络(例如，包括图5中的第二光波导WG-2)和基板上表面上的一层或多层电布线层113-2布置在基板的上表面上的不同位置处，而不是如图4所示将电布线层覆盖在第二光波导的上方。例如，可以将基板上表面上的一层或多层电布线层113-2布置在PIC芯片下方并且由PIC芯片覆盖，同时在基板上表面上其余未布置电布线层的区域布置光互连网络。在这种情况下，光互连网络并是如图4中被电互连网络覆盖，二者是并列布置在基板的上表面上。
在一些实施例中，基板上的光互连网络中的第二光波导还可以包括如上关于图2所述的3D刻写波导，例如，作为形成在玻璃层中的三维波导网络，在这种情况下，还可以直接使用光栅耦合器实现光子集成电路芯片和光互连网络的光耦合。
图6示出了本公开的实施例的光电封装结构600中第四种光耦合方式的示意图。
如图6所示，基板上的光互连网络中的第二光波导WG-2是三维波导网络，例如，三维波导网络是通过在玻璃内部诱导局部玻璃使局部玻璃的折射率提高而构成的网络结构。例如，可以使用超快(例如，飞秒)激光刻写工艺在玻璃内部创建嵌入式的三维波导网络。光子集成电路芯片PIC还包括连接到第一光波导的光栅耦合器GC，第一光波导通过光栅耦合器GC耦合到所述三维波导网络。
图6示出的三维波导网络形成于附加在基板的核心层的玻璃层中，这仅仅是示意性的。在一些示例中，也可以直接在基板的核心层中采用飞秒激光照射核心层内的预设位置，以提高预设位置的折射率，从而在核心 层内形成所述三维波导网络。
利用三维波导网络有利于形成更为丰富和高效的三维立体光波导通路，从而可以进一步压缩光电封装结构的体积。
此外，如图6所示，当采用光栅耦合器结合三维波导网络进行光子集成电路芯片PIC与光互连网络之间的光耦合的情况下，可以将光互连网络(例如，包括图6中的三维波导WG-2)和电互连网络中的一层或多层电布线层113-2布置在基板的上表面上的不同位置处。在这种情况下，光互连网络与电互连网络也是并列布置在基板的上表面上的不同位置处。
以上描述了光电封装结构中光子集成电路芯片和光互连网络之间的各种光耦合方式、以及各种光互连网络和电互连网络的布置方式。各种耦合方式都具有各自的明显优势，可以根据需要在同一个封装的不同位置处采用不同的耦合方式，或者在不同的封装中分别采用不同的耦合方式。例如，绝热耦合由于光子集成电路芯片和基板之间的紧密贴合，有利用压缩封装的体积。采用光束重定向元件的垂直耦合方式能够改变光的传播方向，芯片的布置方式可以更加灵活。光子引线键合的方式插入损耗小，而且对器件对准的要求相对较低，节省了光束整形所需的透镜等，并且制备简单快捷，有利于大规模的生产。利用三维波导网络的光栅耦合有利于形成更为丰富和高效的三维立体光波导通路，从而可以进一步压缩光电封装结构的体积。本领域技术人员可以根据需要选择合适的光耦合方式或其组合，各种组合方式同样落入本公开的保护范围内。
此外，需要说明的是，以上虽然结合光子集成电路芯片和光互连网络之间的各种光耦合方式描述了电互连网络和光互连网络的各种布置方式，这仅仅是示例性的。在实践中可以结合其他因素合理布置电互连网络和光互连网络，从而在实现光互连和电互连的同时，进一步压缩光电封装的体积，并且提高处理的效率。
同时，也可以结合具体应用合理设计电互连网络的具体结构，例如，需要布置一层还是多层电布线层、是布置在基板的一侧表面还是两侧表面上、多层布线层之间是否需要互连结构等等。
例如，当电互连网络包括位于基板核心层的一侧表面(例如，上表面或下表面)上的多层电布线层的情况下，电互连网络还可包括同时连接 多层电布线层的一个或多个盲孔，用于对一侧表面上的多层电布线层进行电互连。
此外，在一些实施例中，基板的核心层的上表面上可以设置一个或多个凹槽，用于在其中或其上布置芯片阵列中的一些芯片。例如，如图10所述的光源LS可以布置在基板的核心层上表面的凹槽中，这将在后文中详细描述。此外，一些凹槽中也可以布置一层或多层电布线层，作为电互连网络的部分或全部。例如，电互连网络还可以包括如图10所示的布置在基板的核心层的凹槽中一层或多层电布线层113-3。
在核心层上布置有凹槽的情况下，可以将芯片阵列中的至少一些芯片布置在凹槽上方并覆盖所述凹槽。需要注意的是，在基板的核心层上设置有凹槽的情况下，可以将光互连网络布置在例如基板的第一表面(上表面)上未被凹槽占据的区域中。
例如，如图10所示，可以将光子集成电路芯片PIC布置在凹槽上方并且覆盖凹槽，凹槽中布置有一层或多层电布线层113-3。设置这种凹槽的作用在于，因为PIC中的第一光波导WG-1和核心层上的第二光波导WG-2需要紧密贴合以实现光的绝热耦合，而PIC上方的EIC的导电通路通常位于PIC下表面，而基板的上表面需要形成导电凸块等电连接结构，导电凸块键合之后通常厚度比较厚，会影响第一光波导WG-1和第二光波导WG-2之间的距离，在PIC的下方形成凹槽可以把导电凸块容纳在凹槽里，从而解决第一波导WG-1和第二波导WG-2之间的距离过大的问题，并且可以在凹槽中进行电布线，从而增加电布线密度。
应当理解的是，虽然电互连网络可以包括基板的核心层上表面、下表面以及上表面的凹槽中的一层或多层电布线层，但电互连网络的布置方式并不一定是从其中择一，还可以包括各种布置方式及其组合。
例如，电互连网络可以仅包括基板的核心层的下表面上的一层或多层电布线层，如2所示。或者，电互连网络可以包括基板的核心层的下表面上的一层或多层电布线层和基板的核心层的上表面上的一层或多层电布线层，如图4所示。可选地，电互连网络可以包括基板的核心层的下表面上的一层或多层电布线层和基板的核心层的上表面的凹槽中的一层或多层电布线层，如图10所示。显而易见的是，电互连网络也可以仅包含 基板的核心层的上表面上的一层或多层电布线层，可以仅包含基板的核心层的上表面的凹槽中的一层或多层电布线层，或者同时包括以上三种电布线层的组合。
如前所述，根据本公开的实施例的光电封装结构还可以根据具体需要包含其他各种类型的芯片，包括但不限于温度控制芯片、功率控制芯片、光源芯片等等。下面将结合附图描述光电封装结构在包括光源芯片(以下称为“光源”)的情况下光源与光子集成电路芯片之间的光耦合方式。
在本公开的实施例的光电封装结构包括光源的情况下，该光源被配置为向光电封装结构中的光子集成电路芯片提供光。图7至图12示出了本公开的实施例的光电封装结构中各种光源耦合方式的示意图。
本公开中的光源的耦合方式大致可分为三类，分别为自对准耦合方式、光子引线键合方式和自由空间光学耦合方式。取决于将来自光源的光直接耦合到光子集成电路芯片，还是直接耦合到光互连网络中，本公开的光源的耦合方式又可分为如图7-12所示的六种具体方式。
图7示出了本公开的实施例的光电封装结构700中第一种光源耦合方式的示意图，即将光源以自对准的方式耦合到光子集成电路芯片中。
如图7所示，光源LS被布置在基板的上表面上，并且位于光子集成电路芯片PIC附近。通过调整光源LS和光子集成电路芯片PIC的安装高度和其在基板上表面上的相对位置，使得光源LS发出的光自对准到光子集成电路芯片PIC的边缘耦合器EC中，从而使光源LS向光子集成电路芯片PIC提供光。
类似地，图8示出了本公开的实施例的光电封装结构800中第二种光源耦合方式的示意图，即将光源的光以自对准的方式耦合到光互连网络中，继而通过绝热耦合再次耦合到光子集成电路芯片中，从而为光子集成电路芯片提供光。
如图8所示，光源LS同样布置在基板的上表面上，但是光源LS与光子集成电路芯片PIC之间还存在光互连网络中的第二光波导WG-2。通过调整光源LS的高度，以及光源LS和第二光波导WG-2在基板上表面上的相对位置，使得光源LS发出的光自对准到第二光波导WG-2中。然后第二光波导WG-2与光子集成电路芯片中的第一光波导WG-1采用 绝热耦合方式进行光耦合，从而使光源LS向光子集成电路芯片PIC提供光。
应当理解的是，图8所示的第二光波导WG-2与光子集成电路芯片中的第一光波导WG-1采用绝热耦合方式仅仅是示例性的，也可以采取如上所述的垂直耦合、光子引线键合等其他方式实现光互连网络和光子集成电路芯片之间的光耦合。
如图7-8所述的光源自对准耦合方式对器件对准的要求很高，需要对各个芯片的高度、光互连网络的高度以及平面布局等进行精密设计和布局。其优势在于节省了光束整形所需的透镜等，结构紧凑，有利于实现光电封装结构的体积的进一步压缩。
对于器件对准精度较低的场合，可以采用光子引线键合的方式进行光源耦合。图9示出了本公开的实施例的光电封装结构900中第三种光源耦合方式的示意图，即将光源的光以光子引线键合的方式耦合到光子集成电路芯片中。
如图9所示，光源LS同样布置在基板的上表面上，并且位于光子集成电路芯片附近。通过使用PWB将光源LS发出的光直接耦合到光子集成电路芯片PIC的边缘耦合器EC中，从而使光源LS向光子集成电路芯片PIC提供光。
类似地，图10示出了本公开的实施例的光电封装结构1000中第四种光源耦合方式的示意图，即将光源的光以光子引线键合的方式耦合到光互连网络中，继而通过绝热耦合再次耦合到光子集成电路芯片中，从而为光子集成电路芯片提供光。
如图10所示，为了使光源LS与光互连网络中的第二光波导WG-2保持大致同样的高度，可以将光源布置在基板的上表面上的凹槽中，通过使用PWB将光源LS发出的光直接耦合到光互连网络中的第二光波导WG-2中，然后第二光波导WG-2与光子集成电路芯片中的第一光波导WG-1采用绝热耦合方式进行光耦合，从而使光源LS向光子集成电路芯片PIC提供光。
应当理解的是，图10所示的第二光波导WG-2与光子集成电路芯片中的第一光波导WG-1采用绝热耦合方式仅仅是示例性的，也可以采取 如上所述的垂直耦合、光子引线键合等其他方式实现光互连网络和光子集成电路芯片之间的光耦合。
此外，还可以采用自由空间光学耦合方式进行光源的光耦合。图11示出了本公开的实施例的光电封装结构1100中第五种光源耦合方式的示意图，即利用光束整形元件将光源的光耦合到光子集成电路芯片中。
如图11所示，光源LS同样布置在基板的上表面上，并且位于光子集成电路芯片附近。光束整形元件140被布置在光源LS和光子集成电路芯片之间。通过调整光源LS、光束整形元件140和光子集成电路芯片PIC的安装高度和其在基板上表面上的相对位置，使得光源LS发出的光通过光束整形元件140对准到光子集成电路芯片PIC的边缘耦合器中，从而使光源LS向光子集成电路芯片PIC提供光。
类似地，图12示出了本公开的实施例的光电封装结构1200中第六种光源耦合方式的示意图，即利用光束整形元件将光源的光耦合到光互连网络中，继而通过绝热耦合再次耦合到光子集成电路芯片中，从而为光子集成电路芯片提供光。
如图12所示，为了使光源LS、光束整形元件140与光互连网络中的第二光波导WG-2保持大致同样的高度，可以将光源LS和光束整形元件140布置在基板的上表面上的凹槽中，通过使用光束整形元件140将光源LS发出的光对准到光互连网络中的第二光波导WG-2中，然后第二光波导WG-2与光子集成电路芯片中的第一光波导WG-1采用绝热耦合方式进行光耦合，从而使光源LS向光子集成电路芯片PIC提供光。
应当理解的是，图12所示的第二光波导WG-2与光子集成电路芯片中的第一光波导WG-1采用绝热耦合方式仅仅是示例性的，也可以采取如上所述的垂直耦合、光子引线键合等其他方式实现光互连网络和光子集成电路芯片之间的光耦合。
如图11-12所示的采用自由空间光学耦合方式耦合光源的方式虽然也要求各个器件进行高度和水平位置上的对准，但是由于采用了光束整形元件(例如，透镜)，其对对准精度的要求相对如上关于图7-8所述的自对准方式要低一些，并且由于采用光束整形元件，光耦合效率也大大提高了。
在以上关于图7至图12描述的光源耦合方式的实施例中，其中的光源LS都可以是如图13所示的带有温控功能的光源。例如，光源LS可以包括激光器LS-1，其被配置为发射光；光源基板LS-2，其用于布置或承载激光器LS-1；以及温度控制器TEC，其布置在激光器LS-1和光源基板LS-2的下方，并且被配置为通过调节激光器LS-1的温度来控制激光器LS-1发射的光的波长。
应当理解的是，如上所述的带有温控功能的光源仅仅是示例性的，而非限制性的。本公开的实施例中的光电封装结构还可以包括其他各种类型的光源。
通过采用如上所述的各种光电封装结构，可以实现各种光子计算系统，例如，用于实现AI计算的光子计算系统。图14示出了本公开的实施例的光子计算系统1400的示意图。图15示出了本公开的实施例的另一光子计算系统1500的示意图。
如图14所示，当光子计算系统1400采用如前所述的不包括内置光源芯片的光电封装结构(例如，如图1-4所示的光电封装结构)的情况下，可以采用如图14所示的外置光源LS为光电封装结构1410提供光。
在图14所示的光子计算系统1400中，印制电路板PCB被配置为承载光电封装结构1410和其他组件。如图所示，印制电路板PCB与光电封装结构1410的基板的下表面上的焊接结构电连接。
另外，光源LS以及其他组件也被布置在印制电路板PCB上。例如，外置光源LS被布置在光电封装结构1410附近，用于为光电封装结构1410提供光。可选地，外置光源LS和光电封装结构1410还可以布置类似的光束整形元件140，从而对外置光源LS发出的光进行准直，使其以更高的耦合效率耦合到光电封装结构1410中。
需要说明的是，图14所示的利用光束整形元件将外置光源LS的光耦合到光电封装结构1410中的PIC中的方式仅仅是示例性的。在采用外置光源LS的情况下，同样可以采用与如图7至12所示的任何一种方式类似的方式实现光源与光电封装结构1410的光耦合，在此不再赘述。
光子计算系统1400除了包括如上所述的光电封装结构1410、外置光源LS、光束整形元件140和印制电路板PCB之外，还可以包括其他光 学元件或电子元件。例如，光子计算系统1400还可以包括如图14所示的功率控制器PC，用以控制整个光子计算系统1400的功率消耗。
相比图14所示的光子计算系统1400，图15所示的光子计算系统1500可以采用包括内置光源芯片的光电封装结构(例如，如图7-13所示的光电封装结构)。
在图15所示的光子计算系统1500中，印制电路板PCB被配置为承载光电封装结构1510和其他组件。如图所示，印制电路板PCB与光电封装结构1510的基板的下表面上的焊接结构电连接。
另外，由于光电封装结构1510自身包括内置光源，可以不需要额外的外置光源为其提供光。另外，其他组件也可以被布置在印制电路板PCB上。例如，光子计算系统1500还可以包括如图15所示的功率控制器PC，用以控制整个光子计算系统1500的功率消耗。
在上述描述中，已经结合附图描述了本公开的实施例。应当理解的是，上述实施例仅仅是说明性的，并且本领域技术人员应当理解，可以以各种方式修改或组合本实施例的构成元素，并且这种修改合组合也落入本公开的范围内。

Claims (23)

  1. 一种光电封装结构，包括：
    基板，包括核心层、光互连网络以及电互连网络；以及
    芯片阵列，布置在所述基板的第一表面上，包括至少一个光子集成电路芯片和至少一个电子集成电路芯片，所述光子集成电路芯片通过所述光互连网络进行光互连，所述电子集成电路芯片通过所述电互连网络进行电互连，其中，
    所述至少一个光子集成电路芯片和至少一个电子集成电路芯片中部分或全部光子集成电路芯片和电子集成电路芯片形成包括光子集成电路芯片和电子集成电路芯片的电子-光子混合芯片，并且
    所述电互连网络包括贯穿所述基板的一个或多个第二导电通孔，所述基板的第二表面具有用于焊接到印刷电路板的焊接结构，所述焊接结构与所述电互连网络电连接。
  2. 如权利要求1所述的光电封装结构，其中，
    所述电子-光子混合芯片中的光子集成电路芯片具有贯穿其中的一个或多个第一导电通孔，所述一个或多个第一导电通孔与所述电互连网络电连接，所述电子-光子混合芯片中的电子集成电路芯片布置在所述光子集成电路芯片的上表面上并且与所述一个或多个第一导电通孔电连接。
  3. 如权利要求1所述的光电封装结构，其中，
    所述光子集成电路芯片中布置有第一光波导，
    所述光互连网络包括第二光波导，并且
    所述光子集成电路芯片与所述光互连网络之间通过所述第一光波导和所述第二光波导进行光耦合。
  4. 如权利要求3所述的光电封装结构，其中，所述第一光波导与所述第二光波导在垂直于所述基板的第一表面的方向上叠置且间隔预定距离，使得所述第一光波导和所述第二光波导实现光的绝热耦合。
  5. 如权利要求3所述的光电封装结构，还包括：
    光束重定向元件的阵列，其被布置在所述基板中，所述光束重定向元件的阵列中的每个光束重定向元件被配置为改变光束的方向以使其进入第二/第一光波导的光耦合器中。
  6. 如权利要求3所述的光电封装结构，其中，所述光子集成电路芯片还包括连接到所述第一光波导的边缘耦合器，所述第一光波导的边缘耦合器和所述第二光波导之间通过光子引线键合的方式进行光耦合。
  7. 如权利要求3所述的光电封装结构，其中，所述第二光波导包括以下至少之一：
    a.嵌入在所述基板的核心层中的一层或多层光波导；
    b.形成在所述基板的核心层的第一表面上的一层或多层光波导；和
    c.形成在所述基板的核心层内的三维波导网络。
  8. 如权利要求7所述的光电封装结构，其中，在所述第二光波导包括所述三维波导网络的情况下，所述光子集成电路芯片还包括连接到所述第一光波导的光栅耦合器，所述第一光波导通过所述光栅耦合器耦合到所述三维波导网络。
  9. 如权利要求3所述的光电封装结构，还包括：
    光源，其被配置为向所述光子集成电路芯片提供光。
  10. 如权利要求9所述的光电封装结构，其中，
    所述光源被设置在所述基板的第一表面上，并且
    所述光源通过与所述光子集成电路芯片中的第一光波导的边缘耦合器对齐，进而向所述光子集成电路芯片提供光。
  11. 如权利要求9所述的光电封装结构，其中，
    所述光源被设置在所述基板的第一表面的凹槽中，并且
    所述光源通过与所述光互连网络中的第二光波导的边缘耦合器对齐，进而向所述光子集成电路芯片提供光。
  12. 如权利要求9所述的光电封装结构，其中，
    所述光源被设置在所述基板的第一表面上，并且
    所述光源通过光子引线键合的方式将光耦合到所述光子集成电路芯片中的第一光波导的光耦合器中，进而向所述光子集成电路芯片提供光。
  13. 如权利要求9所述的光电封装结构，其中，
    所述光源被设置在所述基板的第一表面的凹槽中，并且
    所述光源通过光子引线键合的方式将光耦合到所述光互连网络中的第二光波导的光耦合器中，进而向所述光子集成电路芯片提供光。
  14. 如权利要求9所述的光电封装结构，其中，
    所述光源被设置在所述基板的第一表面上，并且
    所述光电封装结构还包括：
    光束整形元件，其被布置在所述基板的第一表面上，位于所述光源和所述光子集成电路芯片之间，
    其中，所述光源通过所述光束整形元件将光耦合到所述光子集成电路芯片的第一光波导的光耦合器中，进而向所述光子集成电路芯片提供光。
  15. 如权利要求9所述的光电封装结构，其中，
    所述光源被设置在所述基板的第一表面的凹槽中，并且
    所述光电封装结构还包括：
    光束整形元件，其被布置在所述凹槽中，位于所述光源和所述光互连网络中的第二光波导之间，
    其中，所述光源通过所述光束整形元件将光耦合到所述第二光波导的光耦合器中，进而向所述光子集成电路芯片提供光。
  16. 如权利要求9至15中任一项所述的光电封装结构，其中，所述光源包括：
    激光器，其被配置为发射光；
    温度控制器，其布置在所述激光器下方，并且被配置为通过调节所述激光器的温度来控制所述激光器发射的光的波长。
  17. 如权利要求1所述的光电封装结构，其中，所述电互连网络包括布置在所述基板的核心层的第二表面上的一层或多层电布线层。
  18. 如权利要求17所述的光电封装结构，其中，所述电互连网络还包括布置在所述基板的核心层的第一表面上的一层或多层电布线层。
  19. 如权利要求1或17所述的光电封装结构，其中，
    所述芯片阵列中的至少一些芯片被设置在基板的第一表面上的凹槽上方并覆盖所述凹槽，
    所述电互连网络还包括布置在所述凹槽中的一层或多层电布线层，并且
    所述光互连网络被布置在所述基板的第一表面上未被所述凹槽占据的区域中。
  20. 如权利要求1所述的光电封装结构，其中，所述芯片阵列包括一个或多个存储芯片。
  21. 如权利要求1所述的光电封装结构，其中，所述基板的核心层的材料为玻璃、硅或陶瓷。
  22. 一种光子计算系统，其包括如权利要求1至8或权利要求17至21中任一项所述光电封装结构，所述光子计算系统还包括：
    光源，其被配置为向所述光电封装结构提供光；
    印制电路板，其被配置为承载所述光电封装结构，并且与所述基板的第二表面上的焊接结构电连接。
  23. 一种光子计算系统，其包括如权利要求9至16中任一项所述光电封装结构，所述光子计算系统还包括：
    印制电路板，其被配置为承载所述光电封装结构，并且与所述基板的第二表面上的焊接结构电连接。
PCT/CN2023/103885 2022-07-06 2023-06-29 光电封装结构和光子计算系统 WO2024007945A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210796603.1 2022-07-06
CN202210796603.1A CN117408210A (zh) 2022-07-06 2022-07-06 光电封装结构和光子计算系统

Publications (1)

Publication Number Publication Date
WO2024007945A1 true WO2024007945A1 (zh) 2024-01-11

Family

ID=89454789

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/103885 WO2024007945A1 (zh) 2022-07-06 2023-06-29 光电封装结构和光子计算系统

Country Status (3)

Country Link
CN (1) CN117408210A (zh)
TW (1) TW202403372A (zh)
WO (1) WO2024007945A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106980159A (zh) * 2017-03-07 2017-07-25 中国科学院微电子研究所 基于光电混合集成的光电模块封装结构
CN110890349A (zh) * 2019-12-20 2020-03-17 华进半导体封装先导技术研发中心有限公司 一种带有光互连接口的光电芯片三维封装结构及其制造方法
US20210183773A1 (en) * 2019-12-12 2021-06-17 International Business Machines Corporation Multi-chip package structure having high density chip interconnect bridge with embedded power distribution network
CN113241329A (zh) * 2021-04-30 2021-08-10 杭州光智元科技有限公司 光电芯片的三维封装方法及封装结构
CN114063229A (zh) * 2021-09-30 2022-02-18 上海曦智科技有限公司 半导体装置
CN219625758U (zh) * 2023-05-24 2023-09-01 盛合晶微半导体(江阴)有限公司 高密度光电集成的2.5维扇出型封装结构

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106980159A (zh) * 2017-03-07 2017-07-25 中国科学院微电子研究所 基于光电混合集成的光电模块封装结构
US20210183773A1 (en) * 2019-12-12 2021-06-17 International Business Machines Corporation Multi-chip package structure having high density chip interconnect bridge with embedded power distribution network
CN110890349A (zh) * 2019-12-20 2020-03-17 华进半导体封装先导技术研发中心有限公司 一种带有光互连接口的光电芯片三维封装结构及其制造方法
CN113241329A (zh) * 2021-04-30 2021-08-10 杭州光智元科技有限公司 光电芯片的三维封装方法及封装结构
CN114063229A (zh) * 2021-09-30 2022-02-18 上海曦智科技有限公司 半导体装置
CN219625758U (zh) * 2023-05-24 2023-09-01 盛合晶微半导体(江阴)有限公司 高密度光电集成的2.5维扇出型封装结构

Also Published As

Publication number Publication date
TW202403372A (zh) 2024-01-16
CN117408210A (zh) 2024-01-16

Similar Documents

Publication Publication Date Title
US11824029B2 (en) Semiconductor package structure
US8330262B2 (en) Processes for enhanced 3D integration and structures generated using the same
US20220181264A1 (en) Electronic device package and method for manufacturing the same
US20080008477A1 (en) Optical transmission between devices on circuit board
US20080023804A1 (en) High-speed electrical interconnects and method of manufacturing
CN114759012A (zh) 基于tsv工艺晶上系统与pcb板互连结构及制造方法
TWI283490B (en) Circuit board structure of integrated optoelectronic component
CN105321929A (zh) 一种三维光电集成结构及其制作方法
WO2015096641A1 (zh) 光互连系统和方法
TWI517433B (zh) 自動對準之晶片載具與其封裝結構
WO2024007945A1 (zh) 光电封装结构和光子计算系统
CN219625758U (zh) 高密度光电集成的2.5维扇出型封装结构
WO2023193780A1 (zh) 转接板、光芯片封装、计算加速器及其制造方法
CN218767433U (zh) 一种光模块
JP2000269545A (ja) 光電子集積回路装置
US11677472B2 (en) Hybrid integration of microLED interconnects with ICs
WO2014141458A1 (ja) 光モジュールおよび伝送装置
WO2021139200A1 (zh) 一种光模块
CN102074555A (zh) 倒装芯片构造中的器件和互连
WO2022133801A1 (zh) 光电装置以及光电集成结构
WO2024022113A1 (zh) 片上光互连结构及其制作方法
WO2018157314A1 (zh) 光电混合封装组件
CN117913084A (zh) 基于2.5d封装技术的光电芯片混合封装结构及封装方法
WO2024066360A1 (zh) 光模块
US20240063184A1 (en) Perpendicular semiconductor device assemblies and associated methods

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23834712

Country of ref document: EP

Kind code of ref document: A1