WO2023193780A1 - 转接板、光芯片封装、计算加速器及其制造方法 - Google Patents

转接板、光芯片封装、计算加速器及其制造方法 Download PDF

Info

Publication number
WO2023193780A1
WO2023193780A1 PCT/CN2023/086785 CN2023086785W WO2023193780A1 WO 2023193780 A1 WO2023193780 A1 WO 2023193780A1 CN 2023086785 W CN2023086785 W CN 2023086785W WO 2023193780 A1 WO2023193780 A1 WO 2023193780A1
Authority
WO
WIPO (PCT)
Prior art keywords
optical
chips
conductive
chip
glass substrate
Prior art date
Application number
PCT/CN2023/086785
Other languages
English (en)
French (fr)
Inventor
塞蒂亚迪达迪
苏湛
吴建华
孙可烨
贾亚钱德兰苏森德兰
孟怀宇
沈亦晨
Original Assignee
南京光智元科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 南京光智元科技有限公司 filed Critical 南京光智元科技有限公司
Publication of WO2023193780A1 publication Critical patent/WO2023193780A1/zh

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12035—Materials
    • G02B2006/12038—Glass (SiO2 based materials)
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12083—Constructional arrangements
    • G02B2006/12085—Integrated

Definitions

  • the present disclosure relates to the field of semiconductor packaging, and specifically relates to an adapter plate for optical chip packaging, an optical chip packaging structure, a computing accelerator, and a manufacturing method of the adapter plate and optical chip packaging structure.
  • PICs photonic integrated circuits
  • EICs electronic integrated circuits
  • electrical chips also known as electrical chips
  • hybrid chip to form an optoelectronic hybrid system to achieve computing acceleration.
  • electrical connections can be delivered to the substrate or printed circuit board (PCB) via vertical interconnects, such as through silicon vias (TSVs).
  • TSVs through silicon vias
  • silicon interposer boards with embedded TSVs also present cost challenges because silicon wafers are semiconductor substrates with low resistivity and high dielectric constant. Thin silicon wafers are difficult to handle and manufacturing TSVs is still expensive. Because drilling and filling the vias with electroplated copper takes a long time. In addition, in the existing technology, additional optical fibers are usually required to realize optical interconnection between different optical chips, which also causes the problem of excessive packaging size of the optoelectronic hybrid module.
  • the present disclosure aims to provide an adapter plate based on a glass substrate (such as a glass wafer) and a manufacturing method thereof, as well as an optical chip packaging structure using the adapter plate and a manufacturing method thereof. Since the glass substrate has high resistivity, low electrical loss, and has an adjustable coefficient of thermal expansion and good mechanical strength, the glass substrate-based adapter board has low manufacturing cost and can be effectively used for packaging optical chips.
  • the present disclosure also aims to provide an optical chip package that uses adiabatic coupling to couple optical signals between the optical waveguide on the adapter board and the optical waveguide on the optical chip. Installation structure and manufacturing method thereof. This coupling method occupies a small area, enables close-connected waveguide layout, improves integration, and thereby reduces package size.
  • a first aspect of the present disclosure provides an adapter plate for optical chip packaging, including: a glass substrate including one or more conductive through holes, the conductive through holes including through holes penetrating the glass substrate and the The conductive material filled in the through hole; and an optical waveguide structure arranged on the first surface of the glass substrate, wherein the optical waveguide structure includes one or more layers of optical waveguides and a coating covering the one or more layers of optical waveguides.
  • the cladding layer of a layer of optical waveguides, the one or more layers of optical waveguides are used to optically interconnect multiple optical chips packaged on the adapter board, and the refraction of the one or more layers of optical waveguides
  • the refractive index is greater than the refractive index of the cladding layer and the glass substrate
  • the optical waveguide structure also includes one or more first conductive structures penetrating the optical waveguide structure, which are in contact with the one or more conductive structures. The holes are electrically connected respectively.
  • the one or more layers of optical waveguides are silicon nitride optical waveguides, and the material of the cladding layer is silicon dioxide.
  • the adapter board further includes: a dielectric layer arranged on the second surface of the glass substrate; one or more conductive bumps arranged on a side of the dielectric layer away from the glass substrate on the surface, wherein the dielectric layer includes one or more second conductive structures penetrating the dielectric layer, which are electrically connected to the one or more conductive vias respectively, and the one or more conductive bumps electrically connected to the one or more second conductive structures respectively.
  • a second aspect of the present disclosure provides another adapter plate for optical chip packaging, including: a glass substrate including one or more conductive vias, the conductive vias including via holes penetrating the glass substrate; Conductive material filled in the through hole; and an optical coupling structure arranged on the first surface of the glass substrate, wherein the glass substrate further includes a three-dimensional waveguide network for packaging on the adapter board A plurality of optical chips are optically interconnected, the optical coupling structure includes a coupling optical waveguide covering the optical input and output ports of the three-dimensional waveguide network and a coating layer covering the coupling optical waveguide, and the optical coupling structure It also includes one or more first conductive structures penetrating the optical coupling structure, which are electrically connected to the one or more conductive vias respectively.
  • the coupling optical waveguide has a refractive index lower than the refractive index of the three-dimensional waveguide network and higher than the refractive index of the cladding layer.
  • the coupling optical waveguide is a silicon nitride optical waveguide
  • the material of the cladding layer is silicon dioxide
  • the adapter board further includes: a dielectric layer arranged on the second surface of the glass substrate; one or more conductive bumps arranged on a side of the dielectric layer away from the glass substrate on the surface, wherein the dielectric layer includes one or more second conductive structures penetrating the dielectric layer, which are electrically connected to the one or more conductive vias respectively, and the one or more conductive bumps electrically connected to the one or more second conductive structures respectively.
  • the three-dimensional waveguide network is a network structure formed by inducing local glass inside the glass substrate to increase the refractive index of the local glass.
  • a third aspect of the present disclosure provides another adapter plate for optical chip packaging, including: a glass substrate including one or more first conductive vias, the first conductive vias penetrating the glass substrate a through hole and a conductive material filled in the through hole; and an electrical interconnection structure arranged on the first surface of the glass substrate, wherein the electrical interconnection structure includes one or more wiring layers and a package A coating layer covering the one or more wiring layers.
  • the coating layer is a dielectric material.
  • the one or more wiring layers are used to protect the optical chip packaged on the adapter board.
  • a plurality of electrical chips are electrically interconnected, and the electrical interconnection structure further includes one or more first conductive structures penetrating the electrical interconnection structure, which are electrically connected to the one or more first conductive vias respectively. connect.
  • At least two wiring layers in the multi-layer wiring layers are electrically connected through a second conductive structure.
  • the cladding layer is a multi-layer structure formed by alternately stacking silicon nitride layers and silicon dioxide layers.
  • the adapter board further includes: an optical waveguide structure arranged on a surface of the electrical interconnection structure away from the glass substrate, wherein the optical waveguide structure includes one or more layers of optical waveguides.
  • the waveguide and the surrounding layer surrounding the one or more layers of optical waveguides, the one or more layers of optical waveguides are used to optically interconnect multiple optical chips packaged on the adapter board, and their refractive index is greater than The refractive index of the surrounding layer, and the optical waveguide structure further includes one or more third conductive structures penetrating the optical waveguide structure, which are electrically connected to the one or more first conductive structures respectively.
  • the one or more layers of optical waveguides are silicon nitride optical waveguides, and the material of the cladding layer is silicon dioxide.
  • the adapter board further includes: a dielectric layer arranged on the second surface of the glass substrate; one or more conductive bumps arranged on the dielectric layer away from the glass substrate. on the surface of one side of the glass substrate, wherein the dielectric layer includes one or more fourth conductive structures penetrating the dielectric layer, which are electrically connected to the one or more first conductive vias respectively, and the One or more conductive bumps are electrically connected to the one or more fourth conductive structures respectively.
  • a fourth aspect of the present disclosure provides a method for manufacturing an adapter plate for optical chip packaging, including: providing a glass substrate, and forming one or more conductive vias in the glass substrate; An optical waveguide structure is arranged on the first surface of the substrate, wherein the optical waveguide structure includes one or more layers of optical waveguides and a cladding layer covering the one or more layers of optical waveguides; and in the cladding layer Form one or more first conductive structures penetrating the optical waveguide structure, and electrically connect them to the one or more conductive through holes respectively, wherein the refractive index of the one or more layers of optical waveguides is greater than The refractive index of the cladding layer.
  • the one or more layers of optical waveguides are silicon nitride optical waveguides, and the material of the cladding layer is silicon dioxide.
  • arranging an optical waveguide structure on the first surface of the glass substrate includes: a. Using wafer-level nanoimprint lithography technology to form a network of optical waveguides on the first surface of the glass substrate ; b. Deposit cladding material above the optical waveguide.
  • the manufacturing method of the adapter plate further includes: arranging a dielectric layer on the second surface of the glass substrate; forming one or more second layers in the dielectric layer that penetrate the dielectric layer. a conductive structure and electrically connect it to the one or more conductive vias respectively; and arrange one or more conductive bumps on the surface of the dielectric layer away from the side of the glass substrate, wherein the one or A plurality of conductive bumps are respectively electrically connected to the one or more second conductive structures.
  • forming one or more conductive vias in the glass substrate includes: forming one or more vias in the glass substrate by etching; and forming one or more conductive vias on the inner surface of the one or more vias. A layer of conductive material is disposed thereon to form the one or more conductive vias.
  • disposing a layer of conductive material on the inner surface of the one or more through holes to form the one or more conductive through holes includes: using an electroplating method to form a layer of conductive material in the one or more through holes. The surface is filled with conductive metal.
  • the fifth aspect of the present disclosure provides another method for manufacturing an adapter plate for optical chip packaging, including: providing a glass substrate, and forming a three-dimensional waveguide network in the glass substrate, which is used for packaging in the Multiple optical chips on the adapter board are optically interconnected; on the glass substrate forming one or more conductive through holes in the glass substrate; arranging a coupling optical waveguide on the first surface of the glass substrate to cover the light input and output ports of the three-dimensional waveguide network; covering the coupling optical waveguide with a cladding layer to cover the coupling optical waveguide; and form one or more first conductive structures penetrating the cladding layer in the cladding layer, and electrically connect them to the one or more conductive via holes respectively .
  • the coupling optical waveguide has a refractive index lower than the refractive index of the three-dimensional waveguide network and higher than the refractive index of the cladding layer.
  • the coupling optical waveguide is a silicon nitride optical waveguide
  • the material of the cladding layer is silicon dioxide
  • the manufacturing method of the adapter plate further includes: arranging a dielectric layer on the second surface of the glass substrate; forming one or more second layers in the dielectric layer that penetrate the dielectric layer. a conductive structure and electrically connect it to the one or more conductive vias respectively; and arrange one or more conductive bumps on the surface of the dielectric layer away from the side of the glass substrate, wherein the one or A plurality of conductive bumps are respectively electrically connected to the one or more second conductive structures.
  • forming one or more conductive vias in the glass substrate includes: forming one or more vias in the glass substrate by etching; and forming one or more conductive vias on the inner surface of the one or more vias. A layer of conductive material is disposed thereon to form the one or more conductive vias.
  • disposing a layer of conductive material on the inner surface of the one or more through holes to form the one or more conductive through holes includes: using an electroplating method to form a layer of conductive material in the one or more through holes. The surface is filled with conductive metal.
  • forming a three-dimensional waveguide network in the glass substrate includes: irradiating a preset position of the glass substrate with a femtosecond laser to increase the refractive index of the preset position of the glass substrate, wherein the The preset position is the position where the three-dimensional waveguide network structure is formed.
  • a sixth aspect of the present disclosure provides another method of manufacturing an adapter plate for optical chip packaging, including: providing a glass substrate, and forming one or more first conductive vias in the glass substrate; An electrical interconnection structure is arranged on the first surface of the glass substrate, wherein the electrical interconnection structure includes one or more wiring layers and a coating layer covering the one or more wiring layers, The cladding layer is a dielectric material, and the one or more wiring layers are used to package the package in the transfer A plurality of electrical chips above the connection board are electrically interconnected; and one or more first conductive structures penetrating the electrical interconnection structure are formed in the electrical interconnection structure, which are connected with the one or more first conductive structures.
  • the conductive via holes are electrically connected respectively.
  • arranging an electrical interconnect structure on the first surface of the glass substrate includes: arranging a first wiring layer on the first surface of the glass substrate; forming a first wiring layer around the first wiring layer. a silicon nitride sub-layer; and covering the first silicon nitride sub-layer with a first silicon oxide sub-layer.
  • arranging the electrical interconnection structure on the first surface of the glass substrate further includes: arranging a second wiring layer on the first surface of the first silicon oxide sub-layer; forming a second silicon nitride sub-layer around the second silicon nitride sub-layer; and covering the second silicon oxide sub-layer on the second silicon nitride sub-layer.
  • arranging an electrical interconnection structure on the first surface of the glass substrate further includes: forming a second conductive structure between the first wiring layer and the second wiring layer to connect the The first wiring layer and the second wiring layer are electrically connected.
  • the manufacturing method of the adapter board further includes: arranging an optical waveguide structure on a surface of the electrical interconnection structure away from the glass substrate, wherein the optical waveguide structure includes a layer or A multi-layer optical waveguide and a surrounding layer surrounding the one or more layers of optical waveguides, the one or more layers of optical waveguides are used to optically interconnect multiple optical chips packaged on the adapter board, wherein The refractive index is greater than the refractive index of the surrounding layer; and forming one or more third conductive structures penetrating the optical waveguide structure in the optical waveguide structure and connecting them with the one or more first conductive structures electrically connected respectively.
  • the one or more layers of optical waveguides are silicon nitride optical waveguides, and the material of the cladding layer is silicon dioxide.
  • the manufacturing method of the adapter plate further includes: arranging a dielectric layer on the second surface of the glass substrate; forming one or more fourth fourth layers penetrating the dielectric layer in the dielectric layer. a conductive structure, and are electrically connected to the one or more first conductive vias respectively; and one or more conductive bumps are arranged on the surface of the dielectric layer away from the side of the glass substrate, wherein the one or A plurality of conductive bumps are electrically connected to the one or more fourth conductive structures respectively.
  • forming one or more conductive vias in the glass substrate includes: One or more through holes are formed in the glass substrate by etching; and a conductive material layer is provided on the inner surface of the one or more through holes to form the one or more conductive through holes.
  • disposing a layer of conductive material on the inner surface of the one or more through holes to form the one or more conductive through holes includes: using an electroplating method to form a layer of conductive material in the one or more through holes. The surface is filled with conductive metal.
  • a seventh aspect of the present disclosure provides an optical chip packaging structure, which includes an adapter plate as described above, and a plurality of optical chips arranged on the adapter plate.
  • the adapter plate is used to package the adapter plate arranged on the adapter plate.
  • the multiple optical chips on the adapter board are optically interconnected.
  • the optical chip packaging structure further includes: one or more electrical chips disposed on the plurality of optical chips; the optical chip includes one or more interconnect structures, and the interconnect structures including a through hole that runs through the optical chip and a conductive material filled in the through hole; the one or more interconnect structures and the one or more first conductive structures or electrical interconnect structures on the adapter board electrically connected respectively.
  • An eighth aspect of the present disclosure provides an optical chip packaging structure, including: an adapter plate including one or more first optical waveguides embedded therein; and a plurality of optical chips, each optical chip including one or more first optical waveguides embedded therein.
  • a plurality of second optical waveguides wherein the plurality of optical chips are attached to different positions on the upper surface of the adapter plate and optically interconnected through the one or more first optical waveguides, each Each of the first optical waveguides includes a first optical coupling part, each of the second optical waveguides includes a second optical coupling part, and the first optical coupling part and the second optical coupling part are located perpendicular to the
  • the upper surface of the adapter plate is stacked in a direction and spaced apart by a predetermined distance, so that the first optical coupling part and the second optical coupling part achieve adiabatic coupling of light.
  • the first light coupling part and the second light coupling part are each in a tapered shape.
  • the first light coupling portion and the second light coupling portion each have a shape formed by a cascade of two tapered shapes of different sizes.
  • the predetermined distance is less than or equal to 600 nm.
  • the optical chip packaging structure further includes: a plurality of electrical chips arranged on a plurality of first optical chips among the plurality of optical chips, wherein the upper surface of each first optical chip has a One or more first electrical connectors, each electrical chip has one or more second electrical connectors on the lower surface, and the one or more first electrical connectors are respectively connected to the one or more The second electrical connector is electrically connected.
  • the first optical chip further includes one or more second conductive vias extending therethrough, and the one or more second conductive vias are connected to one or more of the adapter boards.
  • the conductive structures are electrically connected respectively.
  • the first optical chip and the electrical chip are directly bonded; or the first optical chip and the electrical chip are bonded together through flip-chip.
  • the plurality of optical chips are separate optical chips obtained by dividing the photonic wafer, which are spaced apart from each other on the upper surface of the adapter plate and the gaps between them are filled with injection molding materials, and A dielectric layer for blocking outward transmission of light in the adapter plate is disposed between the injection molding material and the upper surface of the adapter plate.
  • the plurality of optical chips are multiple undivided optical chips in the same photonic wafer.
  • the plurality of optical chips are undivided optical chips in the same photonic wafer.
  • the plurality of optical chips include a plurality of first optical chips, and each first optical chip is disposed with electrical circuits. Chip, the plurality of electrical chips on the plurality of first optical chips are undivided electrical chips in the same electronic wafer, and the photonic wafer is directly bonded to the electronic wafer.
  • corresponding electrical chips are arranged on all optical chips in the plurality of optical chips, and the corresponding electrical chips on all optical chips are multiple undivided electrical chips in the same electronic wafer. , and wherein the plurality of optical chips have the same structure, and the plurality of electrical chips also have the same structure.
  • the adapter plate is an adapter plate as described above, and the one or more first optical waveguides are a layer or layer in the optical waveguide structure of the adapter plate as described above. Multilayer optical waveguide.
  • the adapter plate is an adapter plate as described above
  • the one or more first optical waveguides are a three-dimensional waveguide network in the adapter plate as described above and cover the Coupling optical waveguides at the optical input and output ports of a three-dimensional waveguide network.
  • a ninth aspect of the present disclosure provides a computing accelerator, including: one or more light sources, which are arranged on the first surface of the adapter plate in the optical chip packaging structure as described above, and are configured to Provide light waves to the computing accelerator; one or more computing units, which are implemented by the optical chip in the optical chip packaging structure as mentioned above, or are implemented by the optical chip packaging structure as mentioned above.
  • the optical chip and the electrical chip are implemented in the structure, or are implemented by the electrical chip in the optical chip packaging structure as mentioned above, and are configured to perform computing functions; one or more storage units, which are composed of the above mentioned optical chip packaging structure
  • the electrical chip is implemented in an optical chip packaging structure and is configured to perform storage functions.
  • the adapter board is the adapter board as described above.
  • a ninth aspect of the present disclosure provides a computing accelerator, including: one or more edge optical couplers configured to optically interconnect the computing accelerator with other devices; one or more light sources configured to Provide light waves to the computing accelerator, and the light waves are coupled to the one or more edge light couplers through the light guide structure; one or more computing units, which are composed of the aforementioned optical chip packaging structure.
  • the optical chip is implemented, or is implemented by the optical chip and the electrical chip in the optical chip packaging structure as mentioned above, or is implemented by the electrical chip in the optical chip packaging structure as mentioned above, and is configured to perform computing functions ;
  • one or more storage units which are implemented by electrical chips in the optical chip packaging structure as described above, and are configured to perform storage functions.
  • each computing unit and the corresponding storage unit are implemented by each optical chip and the corresponding electrical chip in the optical chip packaging structure as described above, as a computing-storage unit.
  • the adapter board in the optical chip packaging structure is the adapter board as described above.
  • the computing accelerator further includes: a plurality of high bandwidth memory (HBM) chips stacked on the optical chip in the optical chip packaging structure, configured to perform in-memory computing functions.
  • HBM high bandwidth memory
  • a tenth aspect of the present disclosure provides a method for manufacturing an optical chip packaging structure, including: providing an adapter board including one or more first optical waveguides embedded therein, each of the first optical waveguides including a third optical waveguide. an optical coupling part; and attaching multiple optical chips to different positions on the upper surface of the adapter plate, each optical chip including one or more second optical waveguides embedded therein, each of the first The two optical waveguides include a second optical coupling part, wherein the first optical coupling part and the second optical coupling part are overlapped in a direction perpendicular to the upper surface of the adapter plate and separated by a predetermined distance, so that the The first optical coupling part and the second optical coupling part realize adiabatic coupling of light, and the plurality of optical chips are optically interconnected through the one or more first optical waveguides.
  • the first light coupling part and the second light coupling part are each in a tapered shape.
  • the first light coupling portion and the second light coupling portion each have a shape formed by a cascade of two tapered shapes of different sizes.
  • the predetermined distance is less than or equal to 600 nm.
  • the method before attaching the plurality of optical chips to different positions on the upper surface of the adapter plate, the method further includes: arranging an electrical chip on the first optical chip of the plurality of optical chips. , so that the first optical chip and the electrical chip on it form an electronic-photon hybrid chip, wherein the upper surface of the first optical chip has one or more first electrical connectors, and the lower surface of the electrical chip There are one or more second electrical connectors on the surface, and the one or more first electrical connectors are electrically connected to the one or more second electrical connectors respectively.
  • arranging an electrical chip on a first optical chip among the plurality of optical chips includes: preparing a photonic wafer and an electronic wafer, the photonic wafer includes a plurality of first optical chips, and the electronic wafer The wafer includes a plurality of electrical chips; the electronic wafer is directly bonded to the photonic wafer, so that the plurality of first optical chips are bonded to the plurality of electrical chips to obtain an electronic-photonic hybrid wafer. circular; removing the substrate of the photonic wafer; and cutting the electron-photonic hybrid wafer into a plurality of electron-photonic hybrid chips.
  • arranging an electrical chip on a first optical chip among the plurality of optical chips includes: preparing a photonic wafer and an electronic wafer, the photonic wafer including the plurality of optical chips, and the electronic wafer.
  • the wafer includes a plurality of electrical chips; the electronic wafer is cut into the plurality of electrical chips; one or more of the plurality of electrical chips are directly bonded or flip-chip welded to the on the first optical chip in the photonic wafer to obtain an electron-photon hybrid wafer; fill the gaps on the photonic wafer that are not occupied by the electronic chip with injection molding material; remove the lining of the photonic wafer bottom; and cutting the electron-photon hybrid wafer into the electron-photon hybrid chip.
  • the method further includes: after removing the substrate of the photonic wafer and before cutting the electronic-photonic hybrid wafer into the electronic-photonic hybrid chip, thinning the photonic wafer Buried oxide layer on the bottom surface to a predetermined thickness.
  • the method further includes: after removing the substrate of the photonic wafer, thinning the buried oxide layer on the bottom surface of the photonic wafer, on a surface of the photonic wafer away from the electrical chip A connection waveguide is formed on the photonic wafer, and the connection waveguide, the second optical coupling portion of the second optical waveguide, and the first optical coupling portion of the first waveguide are stacked in the vertical direction of the lower surface of the photonic wafer. placed and spaced apart; and covering the connection waveguide with a dielectric to encapsulate the connection waveguide.
  • the method further includes: after preparing the photonic wafer, forming one or more second conductive holes in the photonic wafer; and after removing the substrate of the photonic wafer, The buried oxide layer on the bottom surface of the photonic wafer is thinned to a predetermined thickness, so that the one or more second conductive holes penetrate up and down to form one or more second conductive via holes.
  • attaching the plurality of optical chips to different positions on the upper surface of the adapter plate further includes: connecting the one or more second conductive vias with the adapter plate.
  • One or more conductive structures are electrically connected respectively.
  • the plurality of electronic-photonic hybrid chips are spaced apart from each other on the upper surface of the adapter plate, and the method further includes: on the upper surface of the adapter plate and on the A dielectric layer for blocking the outward transmission of light in the adapter plate is formed in the gap between the plurality of electronic-photonic hybrid chips; and on the dielectric layer and on the electronic-photonic chiplet The gap is filled with injection molding material.
  • arranging an electrical chip on a first optical chip among the plurality of optical chips includes: preparing a photonic wafer and an electronic wafer, the photonic wafer includes a plurality of first optical chips, and the electronic wafer The wafer includes a plurality of electrical chips, and the electronic wafer is directly bonded to the photonic wafer such that the plurality of first optical chips are bonded to the plurality of electrical chips to obtain an electron-photon hybrid wafer; and attaching multiple optical chips to different positions on the upper surface of the adapter plate includes: directly bonding the electron-photon hybrid wafer to the upper surface of the adapter plate.
  • the adapter plate is an adapter plate manufactured by the aforementioned method
  • the one or more first optical waveguides are optical waveguides in the adapter plate manufactured by the aforementioned method.
  • One or more layers of optical waveguide in a waveguide structure are provided.
  • the adapter plate is an adapter plate manufactured by a method as described above, and the one or more first optical waveguides are three-dimensional components in the adapter plate manufactured by a method as described above.
  • FIG. 1 shows a cross-sectional view of a first example of an interposer board for optical chip packaging according to an embodiment of the present disclosure.
  • FIG. 2 shows a cross-sectional view of a second example of an interposer board for optical chip packaging according to an embodiment of the present disclosure.
  • FIG 3 shows a cross-sectional view of a third example of an interposer board for optical chip packaging according to an embodiment of the present disclosure.
  • FIG. 4 shows a cross-sectional view of a fourth example of an interposer board for optical chip packaging according to an embodiment of the present disclosure.
  • FIG. 5 shows a process flow diagram of a manufacturing method of an adapter board in a first example of an embodiment of the present disclosure.
  • FIG. 6 shows a process flow diagram of a manufacturing method of an adapter board in a second example of an embodiment of the present disclosure.
  • FIG. 7A shows a process flow diagram of a manufacturing method of an adapter board in a third example of embodiments of the present disclosure.
  • FIG. 7B shows a process flow diagram of a method of manufacturing an adapter board in a fourth example of embodiments of the present disclosure.
  • FIG 8 shows a cross-sectional view of an optical chip packaging structure integrating the adapter board in the first example of embodiments of the present disclosure.
  • FIG. 9 shows a cross-sectional view of an optical chip packaging structure integrating an adapter board in a second example of embodiments of the present disclosure.
  • FIG. 10 shows a cross-sectional view of an optical chip packaging structure integrating an adapter board in a third example of embodiments of the present disclosure.
  • FIG. 11 shows a cross-sectional view of an optical chip packaging structure integrating an adapter board in a fourth example of embodiments of the present disclosure.
  • 12A and 12B respectively illustrate a cross-sectional view and a top view of an optical chip packaging structure according to an embodiment of the present disclosure.
  • FIG. 13 and 14 respectively show a schematic side view and a top view of the optical coupling part in the optical chip packaging structure according to the embodiment of the present disclosure, as well as a corresponding diagram of the optical mode field.
  • FIG. 15 shows a graph of the optical transmission rate of the optical coupling part in the optical chip packaging structure at different lengths according to the embodiment of the present disclosure.
  • FIG. 16 shows a graph of the optical transmission rate of the optical coupling part in the optical chip packaging structure at different spacings according to the embodiment of the present disclosure.
  • FIG. 17 shows a graph of the optical transmission rate of the optical coupling part in the optical chip packaging structure at different thicknesses according to the embodiment of the present disclosure.
  • FIG. 22 shows a cross-sectional view of an optical chip and an electrical chip in the optical chip packaging structure of an embodiment of the present disclosure.
  • FIG. 23 shows a cross-sectional view of an optical chip and an electrical chip in the optical chip packaging structure of an embodiment of the present disclosure.
  • FIG. 24 shows a cross-sectional view of an optical chip packaging structure of an embodiment of the present disclosure.
  • Figure 25 shows a cross-sectional view of an optical chip packaging structure of an embodiment of the present disclosure.
  • 26 and 27 respectively show a cross-sectional view and a top view of the optical chip packaging structure of the embodiment of the present disclosure.
  • 28 and 29A-29B respectively show a cross-sectional view and a top view of the optical chip packaging structure of the embodiment of the present disclosure.
  • Figure 30 shows a schematic diagram of a computing accelerator of an embodiment of the present disclosure.
  • Figure 31A shows a schematic diagram of another computing accelerator of an embodiment of the present disclosure.
  • Figure 31B shows a schematic diagram of yet another computing accelerator according to an embodiment of the present disclosure.
  • 32-37 illustrate a flow chart of a method for manufacturing an optical chip packaging structure according to an embodiment of the present disclosure.
  • Embodiments of the present disclosure provide an adapter board for optical chip packaging.
  • Figure 1 shows A cross-sectional view of an interposer board 100 for optical chip packaging according to an embodiment of the present disclosure.
  • FIG. 5 shows a process flow diagram of the manufacturing method of the adapter board 100 according to the embodiment of the present disclosure.
  • the specific structure and manufacturing method of the adapter plate 100 will be described below with reference to FIGS. 1 and 5 respectively.
  • the overall structure of the adapter plate 100 can be divided into three layers. From bottom to top, they are the dielectric layer 103 , the glass substrate 101 and the optical waveguide structure 102 .
  • the material of the glass substrate 101 is usually silicon dioxide, which includes one or more conductive via holes.
  • the conductive via 101-1 includes a through hole penetrating the glass substrate 101 and a conductive material filled in the through hole (indicated by lateral shading in the figure).
  • the optical waveguide structure 102 is arranged on the first surface (upper surface as shown) of the glass substrate 101.
  • the optical waveguide structure 102 includes one or more layers of optical waveguides and a cladding layer covering one or more layers of optical waveguides.
  • FIG. 1 for convenience of description, only one layer of optical waveguide 102 - 1 and a cladding layer 102 - 2 covering the optical waveguide are shown.
  • one or more layers of optical waveguides in the optical waveguide structure 102 may be used to optically interconnect the multiple optical chips packaged thereon.
  • the refractive index of one or more layers of optical waveguides in the optical waveguide structure 102 is greater than the refractive index of the cladding layer 102-2 and the glass substrate 101.
  • one or more layers of optical waveguides may be silicon nitride with a higher refractive index.
  • the optical waveguide, and the materials of the cladding layer 102-2 and the glass substrate 101 may be silicon dioxide with a relatively low refractive index.
  • the optical waveguide structure 102 also includes one or more first conductive structures 102 - 3 penetrating the optical waveguide structure, which are electrically connected to the above-mentioned one or more conductive through holes 101 - 1 in the glass substrate respectively.
  • One or more first conductive structures 102-3 as shown in the figure can be used to make vertical electrical connections to optical chips or electrical chips packaged on the adapter board.
  • the first conductive structure 102-3 may be a plug structure, such as a copper plug, and of course may also include other metal materials or conductive materials.
  • a dielectric layer 103 is disposed on the second surface (lower surface as shown) of the glass substrate 101 and includes one or more second conductive structures extending through the dielectric layer.
  • One or more conductive bumps 104 are arranged on the surface of the dielectric layer 103 away from the glass substrate 101 (ie, the lower surface as shown in the figure), which are electrically connected to the one or more second conductive structures respectively.
  • the second conductive structure may include a rewiring layer as shown in the figure 103-3 and the conductive hole structure 103-2 below.
  • the conductive bumps 104 may be controlled collapse chip connection (C4) bumps, ball grid array (BGA) connections, solder balls, metal pillars, micro-bumps, etc.
  • Conductive bumps 104 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, conductive bumps 104 may be formed by first forming a solder layer by common methods such as evaporation, electroplating, printing, or the like. In some embodiments, conductive bumps 104 are metal pillars, such as copper pillars, formed by sputtering, electroplating, electroless plating, or the like.
  • the adapter board 100 may not include the dielectric layer 103 and the conductive bumps 104 .
  • the specific structure of the adapter plate 100 for optical chip packaging is described above with reference to FIG. 1 .
  • the manufacturing method of the adapter plate 100 will be described in detail below with reference to FIG. 5 .
  • a glass substrate 101 is first provided, and one or more conductive via holes 101 - 1 are formed in the glass substrate 101 .
  • the conductive via 101-1 can be formed in the glass substrate 101 by etching and electroplating.
  • one or more through holes may be first formed in a glass substrate by laser drilling and etching, and then a layer of conductive material may be disposed on the inner surface of the one or more through holes to form the one or more conductive through holes.
  • a bottom-up electroplating method may be used to fill the inner surface of one or more through holes with conductive metal, thereby forming the conductive through holes.
  • an optical waveguide structure may be arranged on the first surface (the upper surface as shown) of the glass substrate 101.
  • the optical waveguide structure includes one or more layers of optical waveguides 102-1 and a cladding layer 102-2 covering the one or more layers of optical waveguides.
  • the optical waveguide structure includes one or more layers of optical waveguides 102-1 and a cladding layer 102-2 covering the one or more layers of optical waveguides.
  • FIG. 5 only an example of a single-layer optical waveguide is shown in FIG. 5 .
  • step (b) wafer-level nanoimprint photolithography technology may be used to form the optical waveguide 102-1 on the first surface of the glass substrate 101.
  • the wafer-level nanoimprint lithography technology used in the present disclosure has made the following improvements.
  • wafer-level maskless lithography techniques such as electron beam or laser writing.
  • an imprint master can first be made using an oxide, nitride stack that is patterned using electron beam lithography. Then, by using this imprint master, a step-and-repeat operation is performed to generate polymer-based (e.g., PDMS, polyethylene) polymers. Dimethylsiloxane) nano-stamp.
  • the nano-stamp is at the wafer level, that is, through the step-and-repeat operation as described above, the entire optical waveguide pattern is completely and coherently formed in the same nano-stamp.
  • the resist pattern is transferred to the glass wafer in one go. Helps form a one-piece nitride waveguide.
  • Traditional non-wafer-level stamps need to be imprinted multiple times for waveguide splicing. Misalignment problems are prone to occur during the multiple imprinting processes, which affects the quality of the optical waveguide and leads to optical signal loss.
  • the optical waveguide formed is continuous throughout the entire glass wafer, without the need for waveguide splicing in the middle, which can avoid optical signal loss to the greatest extent.
  • step (c) a cladding layer material is deposited over the optical waveguide 102-1 to form the cladding layer 102-2.
  • steps (b)-(c) can be repeated, so that an optical waveguide structure having a multi-layer optical waveguide can be formed.
  • one or more first conductive structures 102-3 penetrating the optical waveguide structure can also be formed in the cladding layer 102-2 and connected with one or more conductive structures in the glass substrate 101.
  • the through holes 101-1 are electrically connected respectively.
  • the refractive index of the optical waveguide 102-1 is greater than the refractive index of the cladding layer 102-2 and the glass substrate 101.
  • the optical waveguide 102-1 can be a silicon nitride optical waveguide with a higher refractive index and is clad
  • the material of layer 102-2 and glass substrate 101 may be silicon dioxide with a relatively low refractive index.
  • the manufacturing method of the adapter plate 100 may further include: arranging the dielectric layer 103 on the second surface of the glass substrate 101, forming one or more second conductive structures in the dielectric layer 103 that penetrate the dielectric layer, and They are electrically connected to one or more conductive vias 101 - 1 respectively, and one or more conductive bumps 104 are arranged on the surface of the dielectric layer 103 away from the glass substrate.
  • Steps (d)-(f) in FIG. 5 show exemplary detailed steps of the above process flow.
  • a rewiring layer 103-3 may be formed on the bottom surface of the glass substrate 101 for electrical connection.
  • the dielectric layer 103 is arranged on the bottom surface of the glass substrate 101 and covers a part of the rewiring layer 103-3 formed in (d). At the same time, it is necessary to form a corresponding layer in the dielectric layer 103.
  • the conductive hole structure 103-2 is formed by filling the conductive material in the gap 103-4, so that the conductive hole structure 103-2 is connected with the redistribution layer 103 -3 and the conductive via 101-1 in the glass substrate are electrically connected.
  • the conductive hole structure 103-2 and the redistribution layer 103-3 together form the above-mentioned second conductive structure, which penetrates the dielectric layer 103 and is electrically connected to the conductive via hole 101-1 in the glass substrate 101.
  • step (f) one or more conductive bumps 104 are arranged on the surface of the dielectric layer 103 away from the glass substrate, and the conductive bumps 104 are connected to the second conductive structure (ie, the conductive hole structure 103-2 and the second conductive structure). Wiring layer 103-3) electrical connection.
  • the specific structure and manufacturing method of the adapter board 100 used in the first example of optical chip packaging have been described with reference to FIGS. 1 and 5 .
  • optical interconnections can be achieved between the optical chips packaged on the adapter board, thereby avoiding the cost problems and process difficulties of manufacturing silicon adapter boards for embedded TSVs. question.
  • the optical waveguide is formed in the glass substrate using the wafer-level nanoimprinting method as described above, the formed optical waveguide is continuous throughout the entire glass wafer, and does not require waveguide splicing in the middle, which can minimize the need for Optical signal loss.
  • FIG. 2 shows a cross-sectional view of an adapter plate 200 for optical chip packaging according to an embodiment of the present disclosure.
  • FIG. 6 shows a process flow diagram of the manufacturing method of the adapter board 200 according to the embodiment of the present disclosure.
  • the overall structure of the adapter board 200 can be similarly divided into three layers, from bottom to top, the dielectric layer 203 , the glass substrate 201 and the optical coupling structure 202 .
  • the material of the glass substrate 201 is usually silicon dioxide, which includes one or more conductive via holes.
  • silicon dioxide which includes one or more conductive via holes.
  • the conductive via 201-1 includes a through hole penetrating the glass substrate 201 and a conductive material filled in the through hole (indicated by lateral shading in the figure).
  • the glass substrate 201 also includes a three-dimensional waveguide network 201-2 (curve as shown in the figure) for optical interconnection of multiple optical chips packaged on the adapter board 201.
  • the three-dimensional waveguide network 201-2 is formed by inducing local glass inside the glass substrate 201 to increase the refractive index of the local glass, and has a three-dimensional network structure formed by multiple pathways distributed throughout the interior of the glass substrate 201.
  • ultrafast (e.g., femtosecond) laser inscription processes can be used Art creates an embedded three-dimensional waveguide network inside a glass substrate.
  • the light coupling structure 202 is arranged on the first surface (eg, upper surface) of the glass substrate 201 .
  • the optical coupling structure 202 includes a coupling optical waveguide 202-1 covering the optical input and output ports of the three-dimensional waveguide network 201-2 and a coating layer 202-2 covering the coupling optical waveguide 202-1.
  • the optical coupling structure 202 also includes one or more first conductive structures 202-3 penetrating the optical coupling structure, which are respectively electrically connected to one or more conductive through holes 201-1 in the glass substrate 201.
  • the refractive index of the coupling optical waveguide 202-1 may be lower than the refractive index of the three-dimensional waveguide network 201-2, but higher than the refractive index of the cladding layer 202-2.
  • the coupling optical waveguide 202-1 may be a silicon nitride optical waveguide, and the material of the cladding layer 202-2 may be silicon dioxide.
  • the adapter board 200 includes an embedded optical waveguide 202-1 similar to the adapter board 100 shown in FIG. 1, their functions are different. In the adapter plate 100 shown in FIG. 1 , the optical waveguide 102 - 1 in the optical waveguide structure 102 is used for optical interconnection between different optical chips. However, in the adapter plate 200 shown in FIG.
  • the optical waveguide 102 - 1 in the optical waveguide structure 102 is used for optical interconnection between different optical chips.
  • the coupling optical waveguide 202-1 in the coupling structure 202 is used for optical "coupling", which can improve the optical coupling efficiency between the three-dimensional waveguide network and the optical chip.
  • the dielectric layer 203 in the adapter board 200 is arranged on the second surface (the lower surface as shown) of the glass substrate 201, which includes one or more second second surfaces penetrating the dielectric layer.
  • Conductive structure One or more conductive bumps 204 are arranged on the surface of the dielectric layer 203 away from the glass substrate 201 (ie, the lower surface as shown in the figure), which are electrically connected to the one or more second conductive structures respectively.
  • the second conductive structure may include a redistribution layer 203-3 as shown in the figure and an underlying conductive hole structure 203-2.
  • Conductive bumps 204 may be controlled collapse chip connection (C4) bumps, ball grid array (BGA) connections, solder balls, metal pillars, micro-bumps, etc., similar to conductive bumps 104 as described in FIG. 1 , which will not be described in detail here.
  • C4 controlled collapse chip connection
  • BGA ball grid array
  • the adapter board 200 may not include the dielectric layer 203 and the conductive bumps 204 .
  • the specific structure of the adapter plate 200 for optical chip packaging is described above with reference to FIG. 2 .
  • the manufacturing method of the adapter plate 200 will be described in detail below with reference to FIG. 6 .
  • a glass substrate 201 is provided, and a three-dimensional waveguide network 201-2 is formed in the glass substrate 201, which is used to connect multiple optical cores packaged on the adapter board. Chips are optically interconnected.
  • an ultrafast (eg, femtosecond) laser writing process can be used to create an embedded three-dimensional waveguide network inside a glass substrate.
  • a femtosecond laser can be used to irradiate a preset position of the glass substrate 201 to increase the refractive index of the preset position of the glass substrate 201, thereby forming a three-dimensional waveguide network 201-2.
  • the preset position may be a position where the three-dimensional waveguide network structure is formed.
  • one or more conductive vias 201-1 are formed in the glass substrate 201.
  • the conductive via 201-1 can be formed in the glass substrate 201 by etching and electroplating.
  • one or more through holes may be first formed in a glass substrate by laser drilling and etching, and then a layer of conductive material may be disposed on the inner surface of the one or more through holes to form the one or more conductive through holes.
  • a bottom-up electroplating method may be used to fill the inner surface of one or more through holes with conductive metal, thereby forming the conductive through holes.
  • an optical coupling structure may be arranged on the first surface (the upper surface as shown) of the glass substrate 201.
  • the optical coupling structure includes a coupling optical waveguide 202-1 and a cladding layer 202-2 covering the coupling optical waveguide.
  • photolithography technology can be used to form the coupling optical waveguide 202-1 on the first surface of the glass substrate 201, so that it covers the optical input and output ports of the three-dimensional waveguide network 201-2.
  • a cladding layer material is deposited over coupling optical waveguide 202-1 to form cladding layer 202-2.
  • one or more first conductive structures 202-3 penetrating the optical coupling structure may also be formed in the cladding layer 202-2 and connected with one or more conductive structures in the glass substrate 201.
  • the through holes 201-1 are electrically connected respectively.
  • the refractive index of the coupling optical waveguide 202-1 may be greater than the refractive index of the cladding layer 202-2 and the glass substrate 201.
  • the coupling optical waveguide 202-1 may be a silicon nitride optical waveguide with a higher refractive index.
  • the materials of the cladding layer 202-2 and the glass substrate 201 may be silicon dioxide with a relatively low refractive index.
  • the manufacturing method of the adapter plate 200 may further include: arranging a dielectric layer 203 on the second surface of the glass substrate 201, forming one or more second conductive structures penetrating the dielectric layer in the dielectric layer 203, and They are electrically connected to one or more conductive vias 201 - 1 respectively, and one or more conductive bumps 204 are arranged on the surface of the dielectric layer 203 away from the glass substrate.
  • Steps (e)-(g) in Figure 6 show example detailed steps of the above process flow.
  • a rewiring layer 203-3 may be formed on the bottom surface of the glass substrate 201 for electrical connection.
  • the dielectric layer 203 is arranged on the bottom surface of the glass substrate 201 and covers a part of the rewiring layer 203-3 formed in (e). At the same time, it is necessary to form a corresponding layer in the dielectric layer 203.
  • the gap 203-4 in the rewiring layer 203-3 and the conductive via 201-1 is filled with conductive material in the gap 203-4 to form the conductive hole structure 203-2 in step (g), so that the conductive hole structure 203-2 is electrically connected to the rewiring layer 203-3 and the conductive via 201-1 in the glass substrate.
  • the conductive hole structure 203-2 and the redistribution layer 203-3 together form the above-mentioned second conductive structure, which penetrates the dielectric layer 203 and is electrically connected to the conductive via hole 201-1 in the glass substrate 201.
  • step (g) one or more conductive bumps 204 are arranged on the surface of the dielectric layer 203 away from the glass substrate, and the conductive bumps 204 are connected with the second conductive structure (ie, the conductive hole structure 203-2 is connected with the second conductive structure). Wiring layer 203-3) electrical connection.
  • the adapter plate 200 interconnects multiple optical chips packaged above the adapter plate 200 by forming a three-dimensional optical waveguide network inside the glass substrate. Therefore, a richer optical chip can be formed without increasing the thickness of the adapter plate. and efficient three-dimensional optical waveguide paths, which can effectively compress the volume of optical chip packaging.
  • the silicon nitride coupling optical waveguides as described above are also arranged at the optical input and output of the three-dimensional optical waveguide network, the optical coupling efficiency between the optical chip and the adapter board can be greatly improved.
  • FIGS. 3 and 7A illustrate the specific structure and manufacturing method of another example of an adapter board for optical chip packaging according to an embodiment of the present disclosure.
  • 3 illustrates a cross-sectional view of an adapter plate 300 for optical chip packaging according to an embodiment of the present disclosure.
  • FIG. 7A shows a process flow diagram of a manufacturing method of the adapter board 300 according to an embodiment of the present disclosure.
  • the overall structure of the adapter board 300 can be divided into three layers. From bottom to top, they are the dielectric layer 303 , the glass substrate 301 and the electrical interconnection structure 302 .
  • the material of the glass substrate 301 is usually silicon dioxide, which includes one or more conductive via holes.
  • the conductive via 301-1 includes a through hole penetrating the glass substrate 301 and a conductive material filled in the through hole (indicated by lateral shading in the figure).
  • Electrical interconnect structure 302 is disposed on a first surface of glass substrate 301 (as shown on the surface).
  • electrical interconnect structure 302 may include one or more wiring layers 302-1a, 302-1b, 302-1c and a cladding layer 302-2 covering one or more wiring layers.
  • the cladding layer 302-2 may be a dielectric material, and one or more wiring layers 302-1a, 302-1b, 302-1c may be used to connect multiple electrical circuits on the optical chip packaged on the adapter board. The chips are electrically interconnected.
  • the electrical chip can be vertically packaged with the optical chip, that is, the electrical chip is packaged on the optical chip, so that the electrical chip can be electrically connected to the above-mentioned wiring layer through the conductive vias in the optical chip to achieve electrical interconnection of the electrical chip.
  • the optical chips arranged on the adapter board may be active optical chips, and the active optical chips may also be electrically connected through the above-mentioned electrical interconnection structure 302.
  • FIG. 3 shows an example of an electrical interconnect structure 302 having three wiring layers (302-1a, 302-1b, 302-1c). As shown in the figure, each wiring layer is covered by its own cladding layer. For example, for the wiring layer 302-1a, it is covered by a multi-layer structure formed by alternately stacking silicon nitride layers 302-2a and silicon dioxide layers 302-2b. The wiring layer 302-1b and the wiring layer 302-1c are also covered by a similar multi-layer structure formed by alternately stacking silicon nitride layers and silicon dioxide layers. It should be understood that the three wiring layers shown in FIG. 3 are only exemplary, and more (for example, four or more layers) or fewer (for example, two or one layer) wiring layers can be selected as needed. layer.
  • the electrical interconnection structure 302 further includes one or more first conductive structures 302-3 extending throughout the electrical interconnection structure and one or more first conductive vias 301-1 in the glass substrate. electrically connected respectively.
  • FIG. 3 also shows a second conductive structure 302-4 for electrically connecting at least two of the multi-layer wiring layers.
  • the second conductive structure 302-4 may be formed using a method or material similar to the first conductive structure 302-3. For example, it may be a conductive via or a copper plug, or may include other metal materials or conductive materials.
  • a dielectric layer 303 is disposed on the second surface (lower surface as shown) of the glass substrate 301 and includes one or more second conductive structures extending through the dielectric layer.
  • One or more conductive bumps 305 are arranged on the surface of the dielectric layer 303 away from the glass substrate 301 (ie, the lower surface as shown in the figure), which are electrically connected to the one or more second conductive structures respectively.
  • the second conductive structure may include a redistribution layer 303-3 as shown in the figure and an underlying conductive hole structure 303-2.
  • Conductive bumps 305 may be controlled collapse chip connection (C4) bumps, ball grid array (BGA) connections, solder balls, metal pillars, micro-bumps, etc.
  • Conductive bumps 305 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. Material. In some embodiments, conductive bumps 305 may be formed by first forming a solder layer by common methods such as evaporation, electroplating, printing, or the like. In some embodiments, conductive bumps 305 are metal pillars, such as copper pillars, formed by sputtering, electroplating, electroless plating, or the like.
  • the adapter board 300 may not include the dielectric layer 303 and the conductive bumps 305 .
  • the specific structure of the adapter plate 300 for optical chip packaging is described above with reference to FIG. 3 .
  • the manufacturing method of the adapter plate 300 will be described in detail below with reference to FIG. 7A .
  • a glass substrate 301 is first provided, and one or more conductive via holes 301 - 1 are formed in the glass substrate 301 .
  • the conductive via 301-1 can be formed in the glass substrate 301 by etching and electroplating.
  • one or more through holes may be first formed in a glass substrate by laser drilling and etching, and then a layer of conductive material may be disposed on the inner surface of the one or more through holes to form the one or more conductive through holes.
  • a bottom-up electroplating method may be used to fill the inner surface of one or more through holes with conductive metal, thereby forming the conductive through holes.
  • an electrical interconnection structure 302 is arranged on the first surface (ie, the upper surface as shown) of the glass substrate 301 .
  • electrical interconnect structure 302 includes one or more wiring layers (302-1a, 302-1b, 302-1c) and a cladding layer covering one or more wiring layers.
  • the cladding layer may be a dielectric material, and one or more wiring layers (302-1a, 302-1b, 302-1c) are used to provide support for multiple electrical chips packaged above the optical chips on the interposer board. Make electrical interconnections.
  • FIG. 7A shows an example of an electrical interconnect structure 302 having three wiring layers (302-1a, 302-1b, 302-1c). As shown in the figure, each wiring layer is covered by its own cladding layer. For example, for the wiring layer 302-1a, it is covered by a multi-layer structure formed by alternately stacking silicon nitride layers 302-2a and silicon dioxide layers 302-2b. The wiring layer 302-1b and the wiring layer 302-1c are also covered by a similar multi-layer structure formed by alternately stacking silicon nitride layers and silicon dioxide layers. It should be understood that the three wiring layers shown in FIG. 3 are only exemplary, and more (for example, four or more layers) or fewer (for example, two or one layer) wiring layers can be selected as needed. layer.
  • arranging the electrical interconnection structure 302 on the first surface of the glass substrate 301 may include the following specific steps: first, arranging a first wiring layer on the upper surface of the glass substrate 301 302-1a; Then, a first silicon nitride sub-layer 302-2a is formed around the first wiring layer 302-1a, and the thickness of the first silicon nitride sub-layer 302-2a is smaller than the first wiring layer 302-1a.
  • the above steps can be repeated, and the second wiring layer 302-1b is sequentially arranged on the first silicon oxide sub-layer 302-2b, a second silicon nitride sub-layer is formed around the second wiring layer 302-1b, and The second silicon nitride sub-layer overlies the second silicon oxide sub-layer, and so on, thereby forming an electrical interconnect structure having a plurality of wiring layers.
  • arranging the electrical interconnection structure 302 on the first surface of the glass substrate 301 may further include: forming a second conductive structure 302-4 between the first wiring layer 302-1a and the second wiring layer 302-1b, To electrically connect the first wiring layer 302-1a and the second wiring layer 302-1b.
  • one or more vias may be first formed by laser drilling etching at locations including the wiring layer in the electrical interconnect structure 302, and then a layer of conductive material may be disposed on the inner surface of the one or more vias to form a or a plurality of second conductive structures 302-4.
  • a bottom-up electroplating method may be used to fill the inner surface of one or more through holes with conductive metal, thereby forming the second conductive structure 302-4.
  • the second conductive structure 302-4 also exists in the second wiring layer 302 -1b and the third wiring layer 302-1c, thereby electrically connecting the second wiring layer 302-1b and the third wiring layer 302-1c.
  • arranging the electrical interconnection structure 302 on the first surface of the glass substrate 301 may further include forming one or more first conductive structures 302 - 3 in the electrical interconnection structure 302 penetrating the electrical interconnection structure, wherein They are respectively electrically connected to one or more first conductive vias 301-1 in the glass substrate 301.
  • the manufacturing method of the adapter plate 300 may further include: arranging a dielectric layer 303 on the second surface of the glass substrate 301, and forming one or more holes in the dielectric layer 303 that penetrate the dielectric layer.
  • a fourth conductive structure is electrically connected to one or more conductive vias 301 - 1 respectively, and one or more conductive bumps 305 are arranged on the surface of the dielectric layer 303 away from the glass substrate.
  • Steps (b)-(d) in FIG. 7A show detailed steps of the above process flow.
  • a rewiring layer 303-3 may be formed on the second surface of the glass substrate 301 for electrical connection.
  • the dielectric layer 303 is arranged on the bottom surface of the glass substrate 301 and covers the rewiring layer formed in (b) A part of 303-3, and at the same time, a gap 303-4 corresponding to the rewiring layer 303-3 and the conductive via 301-1 needs to be formed in the dielectric layer 303, so that in step (d), by filling in the gap 303-4 Conductive material is used to form the conductive hole structure 303-2, so that the conductive hole structure 303-2 is electrically connected to the redistribution layer 303-3 and the conductive via 301-1 in the glass substrate.
  • the conductive hole structure 303-2 and the redistribution layer 303-3 together form the above-mentioned fourth conductive structure, which penetrates the dielectric layer 303 and is electrically connected to the conductive via hole 301-1 in the glass substrate 301.
  • step (d) one or more conductive bumps 305 are arranged on the surface of the dielectric layer 303 away from the glass substrate, and the conductive bumps 305 are connected to the fourth conductive structure (ie, the conductive hole structure 303-2 and the conductive hole structure 303-2). Wiring layer 303-3) electrical connection.
  • the specific structure and manufacturing method of the adapter plate 300 used in the first example of optical chip packaging have been described with reference to FIGS. 3 and 7A .
  • electrical interconnection structure By arranging the electrical interconnection structure on the surface of the glass substrate, electrical interconnection can be achieved between the electrical chips packaged above the optical chip on the adapter board.
  • FIGS. 4 and 7A-7B illustrate a cross-sectional view of an adapter plate 400 for optical chip packaging according to an embodiment of the present disclosure.
  • 7A-7B illustrate a process flow diagram of a method of manufacturing the adapter board 400 according to an embodiment of the present disclosure.
  • the overall structure of the adapter plate 400 can be divided into four layers. From bottom to top, they are the dielectric layer 303, the glass substrate 301, the electrical interconnection layer 302 and the optical waveguide structure 304.
  • the dielectric layer 303, The arrangement and functions of the glass substrate 301 and the electrical interconnection layer 302 are similar to those of the adapter plate 300 shown in FIG. 3 and will not be described again here.
  • the adapter plate 400 shown in FIG. 4 additionally includes an optical waveguide structure 304 .
  • the optical waveguide structure 304 is disposed on the surface (ie, the upper surface) of the electrical interconnection structure 302 on the side away from the glass substrate 301 .
  • optical waveguide structure 304 may include one or more layers of optical waveguides 304-1 and a surrounding layer 304-2 surrounding one or more layers of optical waveguides 304-1.
  • FIG. 4 only an example of the optical waveguide structure with one layer of optical waveguide 304-1 is shown in FIG. 4, but this is only exemplary, and two layers, three layers, or More layers of optical waveguides.
  • the optical waveguide 304-1 as shown in the figure is used to optically interconnect multiple optical chips packaged on the adapter board 400, and the refractive index of the optical waveguide 304-1 is greater than the refractive index of the surrounding layer 304-2.
  • the optical waveguide structure 304 also includes a One or more third conductive structures 304 - 3 are electrically connected to one or more first conductive structures in the electrical interconnect structures 302 respectively.
  • the manufacturing method of the adapter plate 400 shown in FIG. 4 also includes step (f) shown in FIG. 7B . Steps (a)-(e) have been described in detail in the manufacturing method of the adapter board 300 and will not be described again here.
  • the manufacturing method of the adapter board 400 further includes: in step (f), placing the electrical interconnection structure 302 away from the An optical waveguide structure 304 is arranged on the surface of one side of the glass substrate 301.
  • the optical waveguide structure 304 may include one or more layers of optical waveguides 304-1 and a surrounding layer 304-2 surrounding the one or more layers of optical waveguides 304-1.
  • Optical waveguide structure 304 may be formed using similar techniques as described with respect to FIG. 5.
  • a surround layer material may first be deposited over electrical interconnect structure 302, and then wafer-scale nanoimprint lithography may be used to deposit the surrounding layer material on the electrical interconnect structure 302.
  • the optical waveguide 304-1 is formed on the optical waveguide 304-1, and then the surrounding layer material is deposited again on the optical waveguide 304-1 to completely surround the optical waveguide 304-1 to form the surrounding layer 304-2.
  • FIG. 7B only an example of the optical waveguide structure with one layer of optical waveguide 304-1 is shown in FIG. 7B, but this is only exemplary, and two, three or more layers of optical waveguides can be arranged as needed. .
  • the one or more layers of optical waveguides 304-1 are used to optically interconnect multiple optical chips packaged on the adapter board, and the refractive index of the optical waveguide 304-1 is greater than the refractive index of the surrounding layer 304-2.
  • one or more layers of optical waveguide 304-1 may be a silicon nitride optical waveguide, and the material of surrounding layer 304-2 may be silicon dioxide.
  • the wafer-level nanoimprint lithography technology used in the present disclosure has made the following improvements .
  • the present disclosure uses wafer-level maskless lithography techniques such as electron beam or laser writing.
  • an imprint master can first be made using an oxide, nitride stack that is patterned using electron beam lithography.
  • a step-and-repeat operation is performed to generate polymer-based (eg, PDMS, polydimethylsiloxane) nanostamps on the polymer.
  • the nano-stamp is at the wafer level, that is, through the step-and-repeat operation as described above, the entire optical waveguide pattern is completely and coherently formed in the same nano-stamp.
  • the resist pattern is transferred to the glass wafer in one pass. on, helping to form a one-piece nitride waveguide.
  • Traditional non-wafer-level stamps need to be imprinted multiple times for waveguide splicing. Misalignment problems are prone to occur during the multiple imprinting processes, which affects the quality of the optical waveguide and leads to optical signal loss.
  • the optical waveguide formed is continuous throughout the entire glass wafer, without the need for waveguide splicing in the middle, which can avoid optical signal loss to the greatest extent.
  • the manufacturing method of the adapter plate 400 may further include: in step (f), forming one or more third conductive structures 304-3 penetrating the optical waveguide structure 304 in the optical waveguide structure 304, and connecting them with One or more first conductive structures in the electrical interconnect structure 302 are electrically connected respectively.
  • the specific structure and manufacturing method of the adapter plate 400 used in the first example of optical chip packaging have been described with reference to FIGS. 4 and 7A-7B.
  • electrical interconnection can be achieved between the electrical chips packaged on the adapter board, and the package can be placed on the adapter board.
  • Optical interconnection is achieved between the optical chips on the connecting board.
  • the optical waveguide formed is continuous throughout the entire glass wafer, without the need for waveguide splicing in the middle, which can avoid optical signal loss to the greatest extent.
  • the corresponding conductive structure and its manufacturing method are described for each layer of the adapter board (such as the optical waveguide structure 102 and the dielectric layer 103 in Figure 1) , such as the first conductive structure 102-3 in the optical waveguide structure 102 and the second conductive structure 103-2 in the dielectric layer 103 in Figure 1, but in some embodiments, these conductive structures do not have to be separated, and can
  • the first conductive structure 102 - 3 and the second conductive structure 103 - 2 in the dielectric layer 103 may be integrally formed copper plugs that run through the entire adapter board 100 . This one-piece copper plug is also suitable for other adapter boards as shown in Figure 2-4.
  • glass wafer-based interposer plate of the present disclosure Compared with silicon adapter boards with embedded TSVs, glass wafer-based adapter boards have a simple structure, low manufacturing cost and are easy to implement, and can be effectively used for optical interconnection of optical chips.
  • the electrical interconnection of electrical and electronic chips provides a good platform for the integration of optoelectronic chips.
  • a compact, three-dimensional, three-dimensional packaging structure including an optical chip and an electrical chip can be realized.
  • 8-11 illustrate cross-sectional views of various optical chip packaging structures integrating an adapter board in embodiments of the present disclosure.
  • the packaging structure 800 includes an adapter board 100 and an optical chip 500 .
  • the adapter board 100 may be an adapter board 100 with an embedded optical waveguide as shown in FIG. 1 , and the adapter board 100 may be used to perform optical chip processing on an optical chip among a plurality of photonic-electronic hybrid chips arranged thereon.
  • the optical chip is prepared on an SOI substrate.
  • the underlying silicon substrate in the SOI substrate is removed, the thickness of the buried oxide layer is controlled, and the optical chip is bonded to the adapter plate 100
  • the optical signal is adiabatically coupled to the optical waveguide on the optical chip through the embedded optical waveguide on the adapter board 100, and vice versa, thereby realizing on-chip optical network communication.
  • the optical chip 500 is shown in FIG. 8 .
  • two or more optical chips can be arranged on the adapter board 100 , and they are connected through the adapter board 100 .
  • Embedded optical waveguides enable optical interconnections.
  • the optical chip 500 also includes one or more interconnect structures 501.
  • the interconnect structures 501 include through holes penetrating the optical chip and conductive materials filled in the through holes.
  • the interconnection structure 501 is electrically connected to the aforementioned one or more first conductive structures 102-3 on the adapter board 100 respectively.
  • the packaging structure 800 may also include one or more optical chips, each of which is provided with one or more electrical chips (EIC in Figures 8-11).
  • EIC electrical chips
  • one or more electrical chips EIC are arranged above the optical chip 500, and are connected to the adapter board through a conductive structure in the electrical chip (UBM as shown in the figure or other connection structures, such as direct bonding, etc.) Conductive structures in the conductor make vertical electrical connections.
  • FIGS. 9 to 11 respectively show example structures in which the adapter board corresponding to FIGS. 2 to 4 is applied to the packaging of optical chips.
  • the optical chip 500 is similar to the optical chip in FIG. 8 and will not be described again here. It should be noted that, as shown in FIG. 10 , when the adapter board 300 with the electrical interconnection structure shown in FIG. 3 is applied to the packaging structure 1000 , the interconnection structure 501 in the optical chip 500 can be connected with the interconnection structure 1000 . Conductive structures 302-3 in the electrical interconnect layer of board 300 make electrical connections.
  • the conductive structures in each layer of the adapter board are not necessarily separated, but can be integrally formed.
  • the conductive structures in each layer can run through the entire adapter board.
  • the integrated copper plug facilitates the electrical connection between the adapter board and the electrical chip.
  • optical waveguides for optical interconnection of multiple optical chips arranged on the adapter board are arranged, for example, Figure 1 Optical waveguide 102-1 in Figure 2, 202-1 and 202-2 in Figure 2, and 304-1 in Figure 4.
  • the optical coupling between the optical waveguide and the optical chip in the adapter board can be achieved by, for example, using an external optical fiber.
  • this method takes up a lot of space and is not conducive to miniaturization of the packaging structure.
  • Embodiments of the present disclosure propose a method of coupling an optical chip to an optical waveguide in an adapter board using adiabatic coupling to achieve miniaturization of the product.
  • the adapter board used for adiabatic coupling is not limited to the aforementioned adapter board in this disclosure, but may be any adapter board that can realize optical interconnection of optical chips.
  • 12A and 12B respectively illustrate a cross-sectional view and a top view of the optical chip packaging structure 1200 of an embodiment of the present disclosure.
  • the optical chip packaging structure 1200 includes an adapter board 1210 and a plurality of optical chips (PICs) arranged on the adapter board 1210.
  • the optical chips are made of SOI substrates, and the optical waveguides in the optical chips Set on the buried oxide layer of the SOI substrate.
  • FIG. 12A shows a cross-sectional view cut from a specific position, only two optical chips PIC 1 and PIC 2 can be seen in FIG. 12A.
  • the optical chip packaging structure 1200 may include six optical chips PIC 1-PIC 6. It should be understood that the above-mentioned six optical chips are only exemplary and not limiting. In practical applications, the optical chip packaging structure 1200 may include more or fewer optical chips.
  • the adapter plate 1200 includes one or more first optical waveguides embedded therein, such as the optical waveguide WG1-1 and the optical waveguide WG1-2 shown in Figure 12A, where the optical waveguide WG1-1 and the optical waveguide WG1 -2 can be a waveguide network composed of multiple optical waveguides arranged in an array.
  • the optical waveguide WG1-1 and the optical waveguide WG1-2 can be the optical waveguides in the adapter board as mentioned above, such as the optical waveguide 102-1 in Figure 1, the optical waveguides 202-1 and 202-2 in Figure 2, Or optical waveguide 304-1 in Figure 4.
  • the material of the optical waveguide WG1-1 and the optical waveguide WG1-2 may be silicon nitride as mentioned above, and the silicon nitride is covered with a cladding layer of silicon oxide.
  • Each of the optical chips PIC 1 and PIC 2 includes one or more second optical waveguides embedded therein (for simplicity of illustration, only a single optical waveguide is shown in Figure 12A for each PIC), i.e. Optical waveguide WG2-1 and optical waveguide WG2-2.
  • the material of the optical waveguide WG2-1 and the optical waveguide WG2-2 may be silicon.
  • FIG. 12B multiple optical chips (PIC 1,..., PIC 6) are attached to different positions on the upper surface of the adapter board 1210. As shown, PIC 1 -PIC 6 are fitted to different locations in the square area R1 on the adapter board 1210 and are spaced apart from each other.
  • Waveguides carry out optical interconnections. For example, as shown by the dashed arrowed line in Figure 12A, light can originate from PIC 1 and then be coupled through WG2-1 into optical waveguide WG1-1 in adapter board 1210, and then through other optical waveguide networks (not shown). out) is transmitted to the optical waveguide WG1-2, and then coupled to the optical waveguide WG2-1 in PIC 2.
  • each first optical waveguide may include a first optical coupling part
  • each second optical waveguide may include a second optical coupling part (not shown in the figure).
  • the optical waveguide WG2-1 and the ends of WG1-1 are regarded as respective optical coupling parts.
  • the optical coupling portions of the optical waveguides WG2-1 and WG1-1 are stacked in a direction perpendicular to the upper surface of the adapter plate 1210 and are separated by a predetermined distance (for example, less than 600 nm), such that the optical waveguides WG2-1 and WG1- Adiabatic coupling of light can be achieved between the optical coupling parts of 1.
  • the optical chip PIC1 and the optical chip PIC2 can also be optically interconnected through a first optical waveguide.
  • the optical waveguide WG1-1 and the optical waveguide WG1-2 in Figure 12A can be different parts of a first optical waveguide. .
  • different first optical waveguides can realize optical interconnection between different optical chips.
  • one first optical waveguide can be used to connect PIC 1 and PIC 2
  • another first optical waveguide can be used to connect PIC 1 and PIC 3 or PIC 3 and PIC4.
  • FIG. 13 and 14 respectively show a schematic side view and a top view of the optical coupling part in the optical chip packaging structure 1200 according to the embodiment of the present disclosure, as well as a corresponding diagram of the optical mode field.
  • the coupling portion of the optical waveguide WG2-1 in the optical chip PIC 1 and the coupling portion of the optical waveguide WG1-1 in the adapter board are stacked one above the other and are separated by a predetermined distance H.
  • the coupling portion of the optical waveguide WG2-1 in the optical chip PIC 1 and the coupling portion of the optical waveguide WG1-1 in the adapter board may have a tapered shape.
  • the coupling part of the optical waveguide WG2-1 in the optical chip PIC 1 and the coupling part of the optical waveguide WG1-1 in the adapter board are horizontally and vertically All should be aligned to achieve maximum coupling efficiency.
  • Optical waveguide WG1 in the adapter board The width W4 of -1, the length L of the coupling portion of the optical waveguide WG2-1 and the coupling portion of the optical waveguide WG1-1, the above-mentioned distance H, and the thickness tSiN of the optical waveguide WG1-1.
  • W4 of the optical waveguide WG1-1 in the adapter plate on the basis of ensuring that the optical waveguide WG1-1 is a single-mode waveguide, the wider W4 is, the better the coupling effect will be.
  • W4 ⁇ 1 ⁇ m can be selected, because larger than 1 ⁇ m easily becomes a multi-mode waveguide.
  • the coupling loss can be controlled within 1dB.
  • the coupling portion of the optical waveguide of the optical chip and the coupling portion of the optical waveguide of the adapter plate may have a shape formed by a cascade of two tapered shapes of different sizes.
  • Figures 18 and 19 respectively show a schematic diagram of such a coupling portion having a shape formed by a cascade of two tapered shapes of different sizes and a diagram of the corresponding optical mode field.
  • the coupling part of the optical waveguide of the optical chip and the coupling part of the optical waveguide of the adapter plate both have an additional tapered transition structure with a length of L_taper, that is, the optical coupling part It evolves from a single cone-shaped structure to a structure formed by a cascade of two-level cone-shaped structures.
  • the reason why the above-mentioned tapered transition structure is added is that there is a gap between the silicon waveguide WG2-1 and the silicon nitride waveguide WG1-1.
  • the length of the silicon waveguide WG2-1 is about 700nm and the length of the silicon nitride waveguide WG1-1 is about 300nm.
  • the two can couple quickly at this coincidence point, and the coupling length L_trans of this structure can be greatly reduced compared to the previous tapered structure. Small, it can be about 10 ⁇ m to complete optical coupling.
  • silicon waveguide WG2-1 and silicon nitride waveguide WG1-1 can also allow longitudinal alignment misalignment at a larger angle (the previous tapered structure required the two waveguides to have a small angular alignment in the parallel direction) error) and lateral misalignment.
  • optical chip packaging structure according to the present disclosure with reference to FIGS. 12A to 19 .
  • this embodiment by controlling the spacing between the optical waveguide in the optical chip and the optical waveguide on the adapter board, and changing the above-mentioned With the structure of the coupling part of the two waveguides, multiple optical chips can be optically connected to the adapter board through adiabatic coupling, and then the optical interconnection between multiple optical chips can be achieved through the optical waveguide network on the adapter board.
  • this packaging structure that uses adiabatic coupling technology to optically interconnect multiple optical chips can greatly reduce the volume of the packaging structure.
  • electrical chips can also be arranged in the packaging structure as described above, thereby forming an optical chip packaging structure capable of realizing electrical operations (such as logical calculation, storage, etc.).
  • 20 and 21 respectively illustrate a cross-sectional view and a top view of an optical chip packaging structure 2000 including an electrical chip according to an embodiment of the present disclosure.
  • the packaging structure 2000 also includes a plurality of first optical chips arranged on a plurality of optical chips.
  • a plurality of electrical chips for example, EIC 1 and EIC 2 are arranged on PIC 1 and PIC 2 respectively.
  • EIC 1, EIC 2, EIC 5, and EIC 6 are respectively arranged on PIC 1, PIC 2, PIC 5, and PIC 6.
  • FIG. 20 can be viewed as a cross-sectional view cut from a position penetrating EIC 1 and EIC 2 of the package structure 2000 shown in FIG. 21 .
  • PIC 1, PIC 2, PIC 5, and PIC 6 have been covered by the corresponding EIC 1, EIC 2, EIC 5, and EIC 6 respectively, so they are not shown.
  • PIC 3 and PIC 4 do not need to be arranged as needed. EIC.
  • each first optical chip (for example, PIC 1 and PIC 2 as shown in Figure 20) may have one or more first electrical connectors on the upper surface, and each electrical chip (for example, as shown in Figure 20) There may be one or more second electrical connectors on the lower surface of the EIC 1 and EIC 2) shown, and the one or more first electrical connectors are electrically connected to the one or more second electrical connectors respectively, thereby achieving PIC and EIC connections.
  • 22 and 23 illustrate cross-sectional views of optical chips and electrical chips in the optical chip packaging structure of embodiments of the present disclosure.
  • the upper surface of the PIC has a plurality of first electrical connectors C1
  • the lower surface of the EIC has a plurality of second electrical connectors C2.
  • the PIC and the EIC pass through the first electrical connectors C1 and the second electrical connector C2 are directly bonded.
  • the above-mentioned first optical chip (ie, the PIC on which the EIC is disposed) also includes one or more second conductive vias running therethrough, for example, a TDV as shown in (a) of Figure 22,
  • the electrical connection between the EIC and the adapter board can be made through these TDVs.
  • the TDV shown is connected to the conductive structure of the adapter board as shown before, which will be introduced later for Figures 24-25. described in detail.
  • FIG. 22 shows a schematic diagram of a single EIC arranged on a PIC.
  • multiple EICs may be deployed on one PIC.
  • the analog electrical chip A-EIC can be arranged on the PIC while the digital electrical chip D-EIC is arranged.
  • Chip D-EIC In the case where multiple EICs are arranged on the same PIC, each EIC is connected to the conductive structure of the adapter board through the TDV as mentioned above to achieve electrical connection between the two.
  • the optical chip PIC and the electrical chip EIC can also be connected by flip-chip soldering.
  • Figure 23 shows the optical chip PIC and the electrical chip EIC bonded using flip-chip soldering.
  • a traditional flip-chip process is used to connect the EIC and PIC through copper pillars and use an underfill between the EIC and PIC for curing.
  • (a) of Figure 23 shows an example of flipping only one EIC on one PIC, and
  • each EIC is connected to the conductive structure of the adapter board through the TDV as mentioned above to achieve electrical connection between the two.
  • FIGS. 24-25 show cross-sectional views of the optical chip packaging structure of embodiments of the present disclosure. It should be noted, however, that in order to present further details, only one PIC and one EIC are shown in Figures 24-25. Specifically, FIG. 24 shows a cross-sectional view of an optical chip packaging structure using the adapter plate shown in FIG. 1 . FIG. 25 shows a cross-sectional view of an optical chip packaging structure using the adapter plate shown in FIG. 4 .
  • the entire package structure can be divided into three layers from bottom to top, namely the layer where the adapter board 1210 is located, the layer where the PIC is located, and the layer where the EIC is located. layer.
  • two parallel dotted lines are used to divide the entire package structure into three layers.
  • the dotted line between the EIC and the PIC defines the connection interface IF1 of the EIC and the PIC, and the connection interface between the PIC and the adapter board 1210
  • the dotted line defines the connection interface IF2 between the PIC and the adapter board 1210.
  • the EIC arranged thereon corresponds to EIC 1 as shown in Figure 20.
  • the optical waveguide WG2-1 in the optical chip PIC is located near the lower surface of the optical chip PIC and is covered by a transparent dielectric layer (eg, a buried silicon oxide layer).
  • the optical waveguide WG1-1 in the adapter plate 1210 is located on the upper surface of the adapter plate 1210 and is also covered by a cladding layer (for example, a silicon oxide layer).
  • the optical chip PIC has a conductive via TDV running through it, and the conductive via TDV in the optical chip PIC and the conductive structure CC in the adapter board 1210 are electrically connected to each other.
  • the optical waveguide WG1 - 1 may correspond to the optical waveguide in the adapter plate 100 shown in FIG. 1 102-1
  • the conductive structure CC may correspond to the first conductive structure 102-3 in the adapter board 100 as shown in FIG. 1 .
  • the entire package structure can also be divided into three layers from bottom to top, namely the layer where the adapter board 1210 is located, the layer where the PIC is located.
  • two parallel dotted lines are also used to divide the entire package structure into three layers.
  • the dotted line between the EIC and the PIC defines the connection interface IF1 of the EIC and the PIC, and the connection between the PIC and the adapter board 1210
  • the dotted line between defines the connection interface IF2 between the PIC and the adapter board 1210.
  • the EIC arranged thereon corresponds to EIC 1 as shown in Figure 20.
  • the optical waveguide WG2-1 in the optical chip PIC is located near the lower surface of the optical chip PIC and is covered by a dielectric layer (for example, a silicon oxide layer).
  • the optical waveguide WG1-1 in the adapter plate 1210 is located on the upper surface of the adapter plate 1210 and is also covered by a cladding layer (for example, a silicon oxide layer).
  • the optical chip PIC has a conductive via TDV running through it, and the conductive via TDV in the optical chip PIC and the conductive structure CC in the adapter board 1210 are electrically connected to each other.
  • the optical waveguide WG1 - 1 may correspond to the optical waveguide in the adapter plate 400 shown in FIG. 4 304-1
  • the conductive structure CC may correspond to the third conductive structure 304-3 in the adapter plate 400 as shown in FIG. 4 .
  • the multiple optical chips shown are separate optical chips obtained after splitting the photonic wafer, and are attached to different positions on the upper surface of the adapter board. , and are spaced apart from each other (as shown in Figures 12A-12B and Figure 20-21), so after the optical chip is attached to the adapter board, in order to further package it to enhance the stability and strength of the structure, it is necessary to The gaps between different optical chips and different electrical chips on the upper surface of the connecting board are filled with injection molding material.
  • a dielectric layer for blocking the outward transmission of light in the adapter board can be first placed on the connection interface between the optical chip and the adapter board, and then on the dielectric layer Injection molding is performed to form a layer of injection molded material.
  • the dielectric layer e.g., oxide The silicon layer
  • the dielectric layer is very thin.
  • Optical signals are transmitted in waveguides between different optical chips.
  • the thin silicon oxide layer will cause light to overflow during the transmission process and cause optical loss. Therefore, before injection molding, a dielectric layer can be prepared in the gap where the optical chip is not attached to the adapter plate.
  • the dielectric layer is made of the same material and preparation process as the dielectric layer covering the waveguide.
  • the material can also be silicon oxide to ensure that the light transmitted in the waveguide between different optical chips does not leak outward.
  • a dielectric layer may be prepared with a thickness on the order of several microns.
  • the package structures shown in Figures 24 and 25 both show a layer of injection molded material and a dielectric layer for blocking light as described above.
  • the injection molded material layer MLD and the dielectric layer SHD in Figure 24 or 25 are located between the adapter board and the injection molding material layer MLD, and has a greater thickness than the thin silicon oxide layer above the optical waveguide WG1-1, thereby ensuring that the light transmitted between different optical chips can be maximized
  • the ground is limited to the adapter board.
  • optical chip packaging structures using the adapter boards shown in FIGS. 1 and 4 are shown in FIGS. 24 and 25 respectively, this is only exemplary and does not mean that this The publicly described optical chip packaging structure can only use adapter boards as shown in Figures 1 and 4.
  • the optical chip packaging structure described in the present disclosure can also use an adapter plate 200 with a three-dimensional waveguide network as shown in Figure 2, and in the case of using an adapter plate 200 with a three-dimensional waveguide network as shown in Figure 2
  • the optical waveguide (for example, the optical waveguide WG1-1) in the adapter board as described above may correspond to the three-dimensional waveguide network 201-2 in the adapter board 200 as shown in Figure 2 and the three-dimensional waveguide network covering the three-dimensional waveguide network.
  • the coupling optical waveguide 202-1 of the optical input and output port may also be used, which will not be listed here one by one.
  • FIGS. 12A to 25 What is described above with reference to FIGS. 12A to 25 is the situation where multiple optical chips are bonded on the adapter board as separate optical chips obtained after dividing the photonic wafer. It should be noted that the multiple optical chips bonded on the adapter board may also be multiple undivided optical chips in the same photonic wafer.
  • Figures 26-27 show schematic diagrams of the optical chip packaging structure 2600 when multiple optical chips bonded on the adapter board are located on the same photonic wafer.
  • the optical chip packaging structure 2600 includes an adapter board 1210 and a plurality of optical chips (PICs) arranged on the adapter board 1210 .
  • PICs optical chips
  • FIG. 26 shows a cross-sectional view cut from a specific position, only two optical chips PIC 1 and PIC 2 can be seen in FIG. 26 .
  • the optical chip packaging structure 2600 may include six optical chips PIC 1-PIC 6. It should be understood that the above-mentioned six optical chips are only exemplary and not limiting. In practical applications, the optical chip packaging structure 2600 may include more optical chips.
  • the adapter plate 2600 includes a plurality of first optical waveguides embedded therein, such as optical waveguides WG1 - 1 and optical waveguides WG1 - 2 as shown in FIG. 26 .
  • the optical waveguide WG1-1 and the optical waveguide WG1-2 can be the optical waveguides in the adapter board as mentioned above, such as the optical waveguide 102- in Figure 1 1, 202-1 and 202-2 in Figure 2, or 304-1 in Figure 4.
  • the material of the optical waveguide WG1-1 and the optical waveguide WG1-2 may be silicon nitride as described above.
  • Each of the optical chips PIC 1 and PIC 2 includes one or more second optical waveguides embedded therein (for simplicity of illustration, only a single optical waveguide is shown in FIG. 26 for each PIC), namely optical waveguide WG2-1 and optical waveguide WG2-1. Waveguide WG2-2.
  • the material of the optical waveguide WG2-1 and the optical waveguide WG2-2 may be silicon.
  • the photonic wafer PWF including multiple optical chips (PIC 1,..., PIC 6) is attached to the upper surface of the adapter board 1210, and the multiple optical chips (PIC 1,..., PIC 6 ) are located at different locations on the adapter plate 1210 and are spaced apart from each other.
  • Multiple adapter boards 1210 can be used between any two of the optical chips PIC 1 and PIC 2 as shown in Figure 26, or the multiple optical chips (PIC 1,..., PIC 6) as shown in Figure 27
  • the first optical waveguide in the optical interconnection is performed.
  • light can originate from PIC 1 and then be coupled through WG2-1 into the optical waveguide WG1-1 in the adapter board 1210, and then pass through a series of optical waveguide networks (not yet shown) is transmitted to the optical waveguide WG1-2, and then coupled to the optical waveguide WG2-1 in PIC 2.
  • each first optical waveguide may include a first optical coupling part
  • each second optical waveguide may include a second optical coupling part (not shown in the figure).
  • the optical waveguide WG2-1 and the ends of WG1-1 are regarded as respective optical coupling parts.
  • the optical coupling portions of the optical waveguides WG2-1 and WG1-1 are stacked in a direction perpendicular to the upper surface of the adapter plate 1210 and are separated by a predetermined distance (for example, less than 600 nm), such that the optical waveguides WG2-1 and WG1- Adiabatic coupling of light can be achieved between the optical coupling parts of 1.
  • optical coupling portion of the first optical waveguide in the adapter board and the optical coupling portion of the second optical waveguide in the optical chip please refer to Figures 13 to 19 and their descriptions.
  • the design of the optical waveguide is applicable to the case of separate optical chips.
  • the design of the optical coupling section also applies to the case of unsingled photonic wafers, unless otherwise stated or clearly unsuitable.
  • the optical coupling part of the first optical waveguide (for example, WG1-1 or WG1-2) in the adapter board and the optical coupling part of the second optical waveguide (for example, WG2-1 or WG2-2) in the optical chip It may have a tapered shape as shown in Figure 14, or a shape formed by cascading two tapered shapes of different sizes as shown in Figure 19.
  • the gap between PIC 1 and PIC 2 in the optical chip packaging structure 2600 shown in FIG. 26 is shown as not filled with hatching lines, as shown in This means that PIC 1 and PIC 2 are on the same uncut wafer, rather than being filled with injection molding material as shown in Figure 12A.
  • the electrical chips can also be arranged accordingly on specific optical chips or all optical chips in the photonic wafer.
  • Figures 28-29 show schematic diagrams of a photonic chip packaging structure 2600 in which electrical chips are simultaneously arranged using unsegmented photonic wafers.
  • the packaging structure 2800 in addition to including an adapter board 1210 similar to Figures 26-27 and a photonic wafer PWF including optical chips PIC 1 and PIC 2, the packaging structure 2800 also includes multiple optical chips arranged in multiple optical chips.
  • a plurality of electrical chips on a first optical chip for example, PIC 1 and PIC 2
  • EIC 1 and EIC 2 respectively arranged on PIC 1 and PIC 2.
  • the package structure 2800 may include EIC 1, EIC 2, EIC 5, and EIC 6 respectively arranged on PIC 1, PIC 2, PIC 5, and PIC 6.
  • FIG. 28 can be viewed as a cross-sectional view cut through the position of EIC 1 and EIC 2 of the package structure 2000 shown in FIG.
  • an EIC can be placed above each PIC.
  • Figure 29B shows a schematic diagram in which EICs (EIC 1-EIC 6 as shown in the figure) are arranged on each optical chip PIC.
  • the corresponding electrical chips on all the optical chips may be multiple undivided electrical chips in the same electronic wafer, and the multiple optical chips may have the same structure, and the multiple electrical chips ( For example, EIC 1-EIC 6) as shown in the figure can also have the same structure, so that each PIC-EIC pair stacked one above the other forms the same PIC-EIC hybrid chip.
  • the plurality of first optical chips are equivalent to all optical chips.
  • the plurality of electrical chips on the plurality of first optical chips are multiple undivided electronic chips in the same electronic wafer EWF, and in this case, as shown in Figure 29A- Figure 29B, the photonic wafer PWF and the electronic wafer The EWFs are connected together by direct bonding, and then jointly arranged on the adapter board 1210 .
  • a flip-chip soldering method similar to that shown in Figure 23 is no longer suitable for connecting photonic wafers and electronic wafers.
  • the optical coupling part in 2) may have a tapered shape as shown in Figure 14, or may be a shape formed by a cascade of two tapered shapes of different sizes as shown in Figure 19, which will not be described again here.
  • the optical chip packaging structure shown in Figures 26-29 can also use the adapter boards 100 and 400 previously described with respect to Figures 1 and 4.
  • the adapter plate 200 with the three-dimensional waveguide network as shown in Figure 2 can also be used.
  • the adapter as described in 26 or 28 The optical waveguide (for example, optical waveguide WG1-1) in the board may correspond to the three-dimensional waveguide network 201-2 in the adapter board 200 as shown in Figure 2 and the coupling optical waveguide covering the optical input and output ports of the three-dimensional waveguide network. 202-1.
  • various variations or modified adapter boards based on the various adapter boards discussed in this disclosure may also be used, which will not be listed here one by one.
  • optical chip packaging structure described in Figures 12A-12B and Figures 20-21 uses a separate optical chip, and the waveguide of the optical chip and the waveguide of the adapter board are coupled in an adiabatic manner.
  • This packaging structure The degree of freedom in chip layout is extremely high, which greatly reduces the size of the packaging structure.
  • the optical chip packaging structure shown in Figures 26-29 it uses unseparated optical chips on the same photonic wafer.
  • the layout flexibility is not as good as that of a separate optical chip, due to the use of a direct bonding process from wafer to glass adapter board, the process is simple and the alignment accuracy is higher. Therefore, the optical chip and adapter board The coupling efficiency between optical waveguides is also higher.
  • Those skilled in the art can select appropriate implementations according to actual needs, or combine various implementations with each other, and this combination also falls within the protection scope of the present disclosure.
  • FIG 30 shows a schematic diagram of a computing accelerator 3000 of an embodiment of the present disclosure.
  • Figure 31A shows a schematic diagram of another computing accelerator 3100A of an embodiment of the present disclosure.
  • Figure 31B shows a schematic diagram of yet another computing accelerator 3100B according to an embodiment of the present disclosure.
  • the computing accelerator 3000 shown in Figure 30 can be implemented using a separate optical chip packaging structure as shown in Figures 12A-12B or Figures 20-21.
  • the computing accelerator 3000 may include one or more light sources LS, one or more computing units CL, and one or more storage units MO.
  • the computing accelerator 3000 may include one or more light sources LS, one or more computing units CL, and one or more storage units MO.
  • different fill patterns are used to distinguish different functional units.
  • a pure white filled cell (a square as shown in the figure) represents a memory unit MO
  • a grid filled cell represents a computing unit CL
  • a scatter filled cell represents a computing unit CL.
  • the unit represents the light source LS.
  • Some units in the computing accelerator 3000 may be implemented in an optical chip package as previously shown with respect to FIGS. 12A-12B and/or with respect to FIGS. 20-21.
  • one or more computing units CL are configured to perform computing functions, which may be implemented by the optical chip in the optical chip package structure 1200 as previously described with respect to FIGS. 12A-12B.
  • matrix multiplication operations can be implemented using Mach-Zehnder MZI interferometers in optical chips.
  • one or more computing units CL may be implemented by an electrical chip in the optical chip packaging structure 1200 as previously described with respect to FIGS. 20-21.
  • the optical chip in the optical chip packaging structure 1200 mainly performs communication functions, and the electrical chip performs Computing function; alternatively, one or more computing units CL can be jointly implemented by an optical chip and an electrical chip in the optical chip packaging structure 1200 as described above with respect to Figures 20-21, for example, the optical chip in the optical chip packaging structure 1200 It performs communication functions and part of the computing functions at the same time, and the electrical chip performs additional computing functions.
  • One or more memory units MO are configured to perform storage functions and may be implemented by electrical chips in the optical chip package structure 1200 as previously described with respect to FIGS. 20-21.
  • one or more light sources LS may to be integrated into the chip packaging structure.
  • one or more light sources LS may be attached to the first surface of the adapter board 1210 in a manner similar to the PIC 1 or PIC 2 in the optical chip package structure 1200 or 2000 as described above, and be configured to Light waves are provided to the computing accelerator 3000 through the waveguide WG in the adapter board. More specifically, light waves are provided to each optical chip in the computing accelerator 3000 .
  • this light source arrangement method also helps to further compress the volume of the computing accelerator.
  • the computing accelerator 3000 may also include one or more edge optical couplers, that is, edge optical couplers CP located around the square as shown in FIG. 30 , which are configured to optically connect the computing accelerator with other devices. interconnection.
  • edge optical couplers CP located around the square as shown in FIG. 30 , which are configured to optically connect the computing accelerator with other devices. interconnection.
  • the edge light coupler CP in the computing accelerator 3000 can be used to connect the light source.
  • the adapter board 1210 in the computing accelerator shown in FIG. 30 may be various types of adapter boards as described above.
  • it can be the adapter boards 100 and 200 as shown in Figures 1-2, or it can be the adapter board 400 as shown in Figure 4.
  • various variations or modified adapter boards based on the various adapter boards discussed in this disclosure may also be used, which will not be listed here one by one.
  • FIG. 30 the computing accelerator is shown to be implemented in different chips of the same optical chip package structure, this is only schematic. In practical applications, multiple different optical chip packaging structures can be interconnected through the edge optical coupler CP as described above, and various computing units, storage units or light sources can be implemented or arranged in multiple optical chip packaging structures. , thus forming large or ultra-large computing accelerators.
  • the computing accelerator 3100A shown in Figure 31A can be implemented using the photonic wafer level packaging structure shown in Figures 26-29B.
  • the computing accelerator 3100A may include one or more light sources LS, one or more computing units CL, and one or more storage units MO.
  • different filling patterns are used to distinguish different functional units.
  • pure white filled cells squares as shown in the figure
  • grid-filled cells represent computing units CL.
  • Some units in the computing accelerator 3100A may be implemented as described above with respect to Figures 26-29B In the optical chip packaging structure shown.
  • one or more computing units CL are configured to perform computing functions, which may be implemented by the optical chip in the optical chip package structure 2600 as previously described with respect to FIGS. 26-27.
  • matrix multiplication operations can be implemented using Mach-Zehnder MZI interferometers in optical chips.
  • one or more computing units or storage units may be implemented by optical chips or electrical chips in the optical chip package structure 2800 as previously described with respect to FIGS. 28-29A.
  • the optical chip in the optical chip package structure 2800 mainly performs communications.
  • the electrical chip performs computing and storage functions; alternatively, one or more computing units CL can be jointly implemented by an optical chip and an electrical chip in the optical chip packaging structure 2800 as described above with respect to Figures 28-29A, for example, an optical chip
  • the optical chip in the package structure 2800 simultaneously performs communication functions and part of the computing and storage functions, and the electrical chip performs additional computing and storage functions.
  • Figure 31A adopts a packaging structure using photonic wafers, there are redundant optical chips outside the square area shown in Figure 30. When bonding the photonic wafer to the transfer Before boarding, redundant optical chips need to be cut and removed.
  • a packaging structure as shown in Figure 29B can also be used to implement the above computing unit and storage unit.
  • the packaging structure 2900 as shown in Figure 29B is used to implement the computing unit and the storage unit in the computing accelerator, since each EIC in the packaging structure 2900 is the same, and each PIC is also the same, you can use
  • Each PIC and corresponding EIC (such as PIC 1 and EIC 1) jointly implement each computing unit and corresponding storage unit and treat it as a computing-storage unit.
  • FIG. 31B shows an example of a compute accelerator 3100B that implements each compute unit and corresponding storage unit as a corresponding compute-storage unit.
  • each computing unit and the corresponding storage unit can be implemented by each optical chip and the corresponding electrical chip in the optical chip packaging structure 2900 as shown in FIG. 29B, so that each computing unit and the corresponding storage unit can be regarded as Compute-memory unit CL-MO.
  • each computing-storage unit CL-MO in FIG. 31B is shown filled with a checkerboard pattern, thereby indicating that each computing-storage unit CL-MO may have the same hardware resources, that is, have the same Storage resources, computing resources, communication resources, etc.
  • a plurality of computing-memory units CL-MO as shown are implemented by the optical chip package structure 2900 as previously described with respect to FIG.
  • the optical chip in the chip package structure 2900 mainly performs communication functions, and the corresponding electrical chip performs computing and storage functions; alternatively, the optical chip can perform communication functions and part of the computing and storage functions at the same time, and the corresponding electric chip performs other computing and storage functions. .
  • each optical chip, an electrical chip, or a combination of an optical chip and an electrical chip in an optical chip package can also be used to implement other functions besides computing, storage, or computing-storage, such as data transmission.
  • the light source LS (for example, a laser chip) cannot be directly bonded to the adapter board and needs to be bonded through an optical fiber array or Other light guide structures couple light into the computational accelerator, and the light source LS is configured to provide light waves to the computational accelerator 3100A or 3100B through the waveguide WG in the adapter board, and more precisely, to the respective optical chips in the computational accelerator 3100A or 3100B. Provides light waves.
  • the computing accelerator 3100A or 3100B may also include one or more edge optical couplers, that is, the edge optical couplers CP located around the square as shown in FIG. 31A or 31B, which are configured to connect the computing accelerator with other devices for optical interconnection.
  • the edge light coupler CP in the computational accelerator 3100A or 3100B may be used to connect the light source LS.
  • the adapter board 1210 in the computing accelerator shown in FIG. 31A or 31B may be various types of adapter boards as described above.
  • it can be the adapter boards 100 and 200 as shown in Figures 1-2, or it can be the adapter board 400 as shown in Figure 4.
  • various variations or modified adapter boards based on the various adapter boards discussed in this disclosure may also be used, which will not be listed here one by one.
  • FIG. 31A or FIG. 31B the computing accelerator is shown to be implemented in different chips of the same optical chip packaging structure, this is only schematic. In practical applications, multiple different optical chip packaging structures can be interconnected through the edge optical coupler CP as described above, and various computing units, storage units or light sources can be implemented or arranged in multiple optical chip packaging structures. , thus forming large or ultra-large computing accelerators.
  • the computing accelerator as described above with respect to Figures 30-31 may also include a plurality of high bandwidth memory (HBM) chips stacked on the optical chip in the optical chip packaging structure, which are Configured to perform in-memory computing functions.
  • HBM high bandwidth memory
  • optical chip packaging structure in various embodiments of the present disclosure and the computing accelerator implemented using various optical chip packaging structures.
  • the waveguide of the optical chip and the waveguide of the adapter board are coupled in an adiabatic manner.
  • This kind of packaging The degree of freedom of chip arrangement in the structure is extremely high, which greatly reduces the size of the packaging structure.
  • the computing accelerator implemented through this packaging structure can further integrate the light source inside the optical chip packaging structure, which is beneficial to further compressing the product volume.
  • optical chip packaging structure shown in Figure 26-29B it uses unseparated optical chips on the same photonic wafer.
  • layout flexibility is not as good as that of separate optical chips, due to Using a direct bonding process from wafer to glass adapter plate, the process is simpler and the alignment accuracy is higher. Therefore, the coupling efficiency between the optical chip and the optical waveguide of the adapter plate is also higher.
  • Those skilled in the art can select appropriate implementations according to actual needs, or combine various implementations with each other, and this combination also falls within the protection scope of the present disclosure.
  • 32-36 illustrate a flow chart of a method for manufacturing an optical chip packaging structure according to an embodiment of the present disclosure.
  • Figure 32 shows a flow chart 3200 corresponding to a method of manufacturing the optical chip packaging structure 1200 shown in Figures 12A-12B.
  • method 3200 includes: providing an adapter board (S3210) and attaching multiple optical chips to different positions on the upper surface of the adapter board (S3220).
  • the adapter board can be the adapter board 1210 as shown in Figure 12A, and the plurality of optical chips can be as shown in Figure 12B. PIC 1 to PIC 6 shown.
  • the adapter board may include one or more first optical waveguides (WG1-1, WG1-2 as shown in FIG. 12A) embedded therein, and each first optical waveguide includes a first optical coupling part.
  • Each optical chip may include one or more second optical waveguides (WG2-1, WG2-2 as shown in FIG. 12A) embedded therein, and each of the second optical waveguides includes a second optical coupling part.
  • first light coupling part and the second light coupling part respectively have a tapered shape as shown in FIG. 14 .
  • first light coupling part and the second light coupling part may each have a shape formed by a cascade of two tapered shapes of different sizes as shown above with respect to FIG. 19 .
  • the first light coupling part and the second light coupling part are overlapped in a direction perpendicular to the upper surface of the adapter plate and separated by a predetermined distance (for example, less than or equal to 600 nm), so that the first light coupling part
  • the coupling part and the second optical coupling part realize adiabatic coupling of light, and a plurality of optical chips are optically interconnected through a plurality of the first optical waveguides.
  • 33-35 show flowcharts corresponding to the manufacturing method of the optical chip packaging structure 2000 shown in FIGS. 20-21.
  • the manufacturing method 3300 includes: providing an adapter board (S3310), arranging an electrical chip on a first optical chip among a plurality of optical chips, so that the first optical chip and the electrical chip thereon form an electronic- Photonic hybrid chip (S3320), and attaching multiple optical chips to different positions on the upper surface of the adapter board (S3330).
  • the manufacturing method 3300 shown in FIG. 33 has an additional step S3320 of forming an electron-photon hybrid chip.
  • the term "electronic-photonic hybrid chip” here does not mean to use other chips besides the optical chip and electrical chip as mentioned above, but can correspond to the PIC 1 shown in Figure 20
  • a PIC together with an EIC disposed thereon may be called an electron-photon hybrid chip or an electron-photon hybrid chiplet.
  • the upper surface of the PIC has a plurality of first electrical connectors C1
  • the lower surface of the EIC has a plurality of second electrical connectors C2.
  • the PIC and the EIC pass through the first electrical connectors C1 and the second electrical connector C2 are directly bonded.
  • the electron-photon hybrid chip may also include a chip as shown in (b) in Figure 22 In the overall structure of one PIC and two EICs (D-EIC and A-EIC), D-EIC, A-EIC and PIC are also directly bonded through the first electrical connector C1 and the second electrical connector C2.
  • Figures 34 and 35 respectively illustrate two different methods of arranging an electrical chip on a first optical chip among the plurality of optical chips to form an electron-photon hybrid chip.
  • the process steps in Figures 34 and 35 can be respectively regarded as subdivided steps of step S3320 in Figure 33.
  • arranging an electrical chip on the first optical chip among the plurality of optical chips includes: preparing a photonic wafer and an electronic wafer (S3410), and directly bonding the electronic wafer to the photonic wafer. wafer (3420), remove the substrate of the photonic wafer (S3430) and cut the electron-photonic hybrid wafer into a plurality of electron-photonic hybrid chips (S3440).
  • the photonic wafer prepared in step S3410 may be similar to the photonic wafer PWF described with respect to FIG. 29A , which includes a plurality of optical chips PIC 1 -PIC 6, and a plurality of optical chips PIC 1 -PIC 6 Contains a plurality of first optical chips for arranging corresponding electrical chips thereon.
  • the electronic wafer prepared in step S3410 may be similar to the electronic wafer EWF described with respect to FIG. 29A, including a plurality of electrical chips (e.g., EIC 1, EIC 2, EIC 5, EIC 6).
  • an electron-photon hybrid wafer can be obtained by bonding (eg, direct bonding) the plurality of first optical chips with the plurality of electrical chips, and then in step S3440, the electron-photon hybrid wafer can be obtained. Photonic hybrid wafers are cut into multiple electron-photonic hybrid chips.
  • Figure 29A shows that PWF and EWF do not need to be divided into separate electron- For photonic hybrid chips, they are directly bonded and arranged as a whole on the adapter board.
  • the bonded PWF and EWF do not need to be cut into independent electronic-photonic hybrid chips, the redundant chips at the edges need to be cut off to facilitate packaging, for example, cut as shown in Figure 31A or 31B Internal square shape shown.
  • Figure 35 shows another method of forming an electron-photon hybrid chip.
  • arranging an electrical chip on the first optical chip among the plurality of optical chips may specifically include: preparing a photonic wafer and an electronic wafer (S3510), cutting the electronic wafer into the plurality of electronic wafers (S3510). chip (S3520), Directly bond or flip-chip one or more of the plurality of electrical chips to the first optical chip in the photonic wafer to obtain an electron-photonic hybrid wafer (S3530).
  • the gaps on the photonic wafer not occupied by the electronic chip are filled with injection molding material (S3540), the substrate of the photonic wafer is removed (S3550), and the electronic-photonic hybrid wafer is cut into the Electronic-photon hybrid chip (S3560).
  • the photonic wafer prepared in step S3510 may be similar to the photonic wafer PWF described with respect to FIG. 29A, which includes a plurality of optical chips PIC1-PIC6, and the plurality of optical chips PIC1-PIC6 include multiple A first optical chip is used to arrange a corresponding electrical chip thereon.
  • the electronic wafer prepared in step S3510 may be similar to the electronic wafer EWF described with respect to FIG. 29A, including a plurality of electrical chips (e.g., EIC 1, EIC 2, EIC 5, EIC 6).
  • the electronic wafer including multiple electrical chips is not integrally bonded to the photonic wafer, but is first cut into multiple separate electrical chips in step S3520, and then In step S3530, each of the electrical chips obtained by cutting is directly bonded or flip-chip welded to the first optical chip in the photonic wafer to obtain an electron-photon hybrid wafer.
  • each electrical chip is a separate electrical chip and is not located on the same electronic wafer as described in method 3400, it is also necessary to arrange the corresponding electrical chip on the first optical chip.
  • the gap occupied by the electronic chip is filled with injection molding material to enhance the mechanical strength and stability of the photonic wafer.
  • Figure 29A shows that PWF and EWF do not need to be divided into separate electronic wafers.
  • - Photonic hybrid chip they are directly bonded and arranged as a whole on the adapter board.
  • the bonded PWF and EWF do not need to be cut into independent electronic-photonic hybrid chips, the redundant chips at the edges need to be cut off to facilitate packaging, for example, cut as shown in Figure 31A or 31B Internal square shape shown.
  • the above method 3400 or 3500 may further include: after removing the substrate of the photonic wafer and before cutting the electronic-photonic hybrid wafer into the electronic-photonic hybrid chip, thinning the photonic wafer
  • the buried oxide layer on the round bottom surface is to a predetermined thickness (not shown in the figure).
  • the thinning operation as described above is to make The thickness of the buried oxide layer on the bottom surface of the optical waveguide in the optical chip is reduced, so that the optical waveguide in the optical chip can be as close as possible to the optical waveguide in the adapter plate, thereby increasing the coupling efficiency.
  • the spacing between the optical waveguide in the optical chip and the optical waveguide in the adapter board can be made less than or equal to 600 nm through the thinning operation as described above, as described with respect to FIG. 13 .
  • the above method 3400 or 3500 may also include: after removing the substrate of the photonic wafer, thinning the buried oxide layer on the bottom surface of the photonic wafer, and placing the photonic wafer away from the electrical chip. forming a connection waveguide on the surface; and covering the connection waveguide with a dielectric to cover the connection waveguide, the connection waveguide and the second optical coupling part of the second optical waveguide in the optical chip, the first optical coupling part in the adapter plate.
  • the first optical coupling portion of the optical waveguide is stacked and spaced apart in the vertical direction of the lower surface of the photonic wafer (not shown in the figure), the first optical waveguide, the connecting waveguide, and the second connecting waveguide Optical communication via adiabatic coupling of light.
  • connection waveguide is formed in the photonic wafer in the above manner, and then a dielectric is covered on the connection waveguide to cover the connection waveguide.
  • the purpose is also to add a connecting waveguide between the optical waveguide in the optical chip and the optical waveguide in the adapter board, thereby increasing the coupling efficiency.
  • the above method 3400 or 3500 may further include: after preparing the photonic wafer, forming one or more second conductive holes in the photonic wafer; and removing the liner of the photonic wafer. After that, the buried oxide layer on the bottom surface of the photonic wafer is thinned to a predetermined thickness, so that the one or more second conductive holes penetrate up and down to form one or more second conductive vias (not shown in the figure) ).
  • the second conductive via formed by the method described above may be a TDV on the PIC as shown in Figure 22 or 23, which is used to electrically connect the electronic chip EIC to the adapter board.
  • attaching the plurality of optical chips to different positions on the upper surface of the adapter board further includes: connecting the one or more second conductive vias with one of the adapter boards.
  • multiple conductive structures are electrically connected respectively.
  • One or more conductive structures in the adapter board may be the first conductive structure 102-3 in the adapter board 100 as shown in Figure 1, or may be the first conductive structure 102-3 in the adapter board 200 as shown in Figure 2.
  • the specific details of the electrical connection between one or more second conductive vias in the optical chip and one or more conductive structures in the adapter board can also refer to the connection method between the TDV and the conductive structure CC in Figure 24 or 25. Here, No longer.
  • the plurality of electron-photon hybrid chips are spaced apart from each other on the upper surface of the adapter plate.
  • the gaps there are still gaps between different electronic-photonic hybrid chips, and it is necessary to fill the gaps with injection molding materials to enhance the stability and mechanical strength of the package.
  • the dielectric layer (e.g., silicon oxide layer) covering the waveguide in the adapter board (e.g., WG1-1 as shown in Figure 24 or 25) is very thin, the optical signal cannot be transmitted through the waveguide between different optical chips. In medium transmission, a very thin silicon oxide layer will cause light to overflow during transmission and cause light loss. Therefore, before injection molding, a dielectric layer can be prepared in the gap where the optical chip is not attached to the adapter plate to block the outward transmission of light in the adapter plate.
  • the material of the dielectric layer is different from that of the adapter plate.
  • the dielectric layer covering the waveguide in the connecting board is made of the same material and uses the same process.
  • the method 3300 may further include: before filling the gaps between the optical chips with the injection molding material, forming on the upper surface of the adapter plate and in the gaps between the plurality of electronic-photonic hybrid chips for blocking the The dielectric layer (not shown in the figure) through which light in the adapter board is transmitted outwards.
  • the material of the dielectric layer may also be silicon oxide, and may have a predetermined thickness, such as several microns, to ensure that the light transmitted in the waveguide between different optical chips does not leak outward.
  • optical chip packaging structure shown in Figures 12A-12B and Figures 20-21 has been described above with reference to Figures 33-35, in which the multiple optical chips and multiple electrical chips packaged are separated from each other, that is, Not on the same wafer.
  • the manufacturing method corresponding to the optical chip packaging structure shown in Figures 26-29 will be described below with reference to the accompanying drawings.
  • chip packaging structure shown in Figures 26-29 multiple optical chips or multiple electrical chips are located in the same photon wafer or within the same electronic wafer.
  • the method shown in FIG. 36 corresponds to the manufacturing method of the optical chip packaging structure 2600 shown in FIGS. 26-27.
  • method 3600 includes: providing an adapter plate (S3610), preparing a photonic wafer (S3620), and directly bonding the photonic wafer to the upper surface of the adapter plate (S3630).
  • the adapter board may be similar to any of the previously described adapter boards and will not be described again here.
  • the prepared photonic wafer includes multiple optical chips, and the photonic wafer is connected to the adapter board through direct bonding.
  • the method shown in FIG. 37 corresponds to the manufacturing method of the optical chip packaging structure 2800 shown in FIGS. 28-29.
  • method 3700 includes: providing an adapter board (S3710), preparing a photonic wafer and an electronic wafer (S3720), and directly bonding the electronic wafer to the photonic wafer, so that multiple first optical chips Bonding with multiple electrical chips to obtain an electron-photonic hybrid wafer (S3730), and directly bonding the photonic wafer to the upper surface of the adapter board (S3740).
  • transfer The board can be similar to any of the adapter boards previously described.
  • the prepared photonic wafer includes a plurality of optical chips
  • the prepared electronic wafer may include a plurality of electrical chips
  • the electronic wafer is directly bonded to the photonic wafer such that a specific optical chip in the photonic wafer (i.e., as described above The first optical chip) is bonded to multiple electrical chips to obtain an electron-photon hybrid wafer.
  • the photonic wafer is connected to the adapter board through direct bonding.
  • the steps of removing the substrate of the photonic wafer described above with respect to Figures 32-35, thinning the buried oxide layer on the bottom surface of the photonic wafer to a predetermined thickness, arranging the connection waveguide in the photonic wafer and covering the connection waveguide are also applicable to the method described with respect to Figures 36-37, unless otherwise stated or clearly inappropriate.
  • each step in the manufacturing method described above in conjunction with the flow chart is only exemplary, and the order of the steps shown in each flow chart is not necessarily fixed.
  • the order of each step can be adjusted, and additional steps can also be omitted or added. Methods obtained through such adjustments, omissions, and added steps also fall within the protection scope of the present application.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Optical Integrated Circuits (AREA)
  • Optical Couplings Of Light Guides (AREA)

Abstract

一种转接板、光芯片封装、计算加速器及其制造方法。转接板（100）包括：玻璃基板（101），其包括一个或多个导电通孔（101-1），导电通孔（101-1）包括贯穿玻璃基板（101）的通孔以及通孔内填充的导电材料；以及光波导结构（102），布置在玻璃基板（101）的第一表面上，其中，光波导结构（102）包括一层或多层光波导（102-1）以及包覆一层或多层光波导的包覆层（102-2），一层或多层光波导（102-1）用于对封装在转接板（100）上的多个光芯片进行光互连，并且一层或多层光波导（102-1）的折射率大于包覆层（102-2）以及玻璃基板（101）的折射率，并且光波导结构（102）还包括贯穿光波导结构（102）的一个或多个第一导电结构（102-3），其与一个或多个导电通孔（101-1）分别电连接。

Description

转接板、光芯片封装、计算加速器及其制造方法
相关申请的交叉引用
本申请要求于2022年4月8日提交的申请号为202210369385.3的中国专利申请的优先权。
技术领域
本公开涉及半导体封装领域，具体涉及一种用于光芯片封装的转接板、光芯片封装结构、计算加速器、以及转接板及光芯片封装结构的制造方法。
背景技术
在对光子集成电路(PIC，也称为光芯片)进行封装时，通常通过在光子集成电路上堆叠电子集成电路(EIC，也称为电芯片)，形成光子-电子混合集成电路(光子-电子混合芯片)，以形成光电混合系统，实现计算加速。为了压缩芯片体积，可以通过垂直互连(例如通过硅通孔(TSV))将电气连接传递到基板或印刷电路板(PCB)。
然而，带有嵌入式TSV的硅转接板还存在成本挑战，因为硅晶圆是具有低电阻率和高介电常数的半导体基板，薄的硅晶圆很难处理，制造TSV仍然很昂贵，因为钻孔和用电镀铜填充过孔的工作时间很长。另外，现有技术中通常需要额外的光纤实现不同光芯片之间的光互连，这也造成了光电混合模块的封装尺寸过大的问题。
发明内容
鉴于上述问题，本公开旨在提供一种基于玻璃基板(例如玻璃晶圆)的转接板及其制造方法、以及使用该转接板的光芯片封装结构及其制造方法。由于玻璃基板具有高电阻率、低电损耗，并且具有可调系数的热膨胀和良好的机械强度，基于玻璃基板的转接板制造成本低，并且能够有效地用于光芯片的封装。另外，本公开还旨在提供一种采用绝热耦合的方式实现光信号在转接板上的光波导与光芯片上的光波导进行耦合的光芯片封 装结构及其制造方法。该耦合方式占用面积小，可以实现波导密接布设，提高集成度，从而减小封装尺寸。
本公开的第一方面提供了一种用于光芯片封装的转接板，包括：玻璃基板，包括一个或多个导电通孔，所述导电通孔包括贯穿所述玻璃基板的通孔以及所述通孔内填充的导电材料；以及光波导结构，布置在所述玻璃基板的第一表面上，其中，所述光波导结构包括一层或多层光波导以及包覆所述一层或多层光波导的包覆层，所述一层或多层光波导用于对封装在所述转接板上的多个光芯片进行光互连，并且所述一层或多层光波导的折射率大于所述包覆层以及所述玻璃基板的折射率，并且所述光波导结构还包括贯穿所述光波导结构的一个或多个第一导电结构，其与所述一个或多个导电通孔分别电连接。
在一些实施例中，所述一层或多层光波导为氮化硅光波导，并且所述包覆层的材料为二氧化硅。
在一些实施例中，该转接板还包括：电介质层，布置在所述玻璃基板的第二表面上；一个或多个导电凸块，布置在所述电介质层远离所述玻璃基板一侧的表面上，其中，所述电介质层包括贯穿所述电介质层的一个或多个第二导电结构，其与所述一个或多个导电通孔分别电连接，并且所述一个或多个导电凸块与所述一个或多个第二导电结构分别电连接。
本公开的第二方面提供了另一种用于光芯片封装的转接板，包括：玻璃基板，包括一个或多个导电通孔，所述导电通孔包括贯穿所述玻璃基板的通孔以及所述通孔内填充的导电材料；以及光耦合结构，布置在所述玻璃基板的第一表面上，其中，所述玻璃基板还包括三维波导网络，用于对封装在所述转接板上的多个光芯片进行光互连，所述光耦合结构包括覆盖所述三维波导网络的光输入输出口的耦合光波导以及包覆所述耦合光波导的包覆层，并且所述光耦合结构还包括贯穿所述光耦合结构的一个或多个第一导电结构，其与所述一个或多个导电通孔分别电连接。
在一些实施例中，所述耦合光波导的折射率低于所述三维波导网络的折射率且高于所述包覆层的折射率。
在一些实施例中，所述耦合光波导为氮化硅光波导，并且所述包覆层的材料为二氧化硅。
在一些实施例中，该转接板还包括：电介质层，布置在所述玻璃基板的第二表面上；一个或多个导电凸块，布置在所述电介质层远离所述玻璃基板一侧的表面上，其中，所述电介质层包括贯穿所述电介质层的一个或多个第二导电结构，其与所述一个或多个导电通孔分别电连接，并且所述一个或多个导电凸块与所述一个或多个第二导电结构分别电连接。
在一些实施例中，所述三维波导网络是通过在所述玻璃基板内部诱导局部玻璃使所述局部玻璃的折射率提高而构成的网络结构。
本公开的第三方面提供了另一种用于光芯片封装的转接板，包括：玻璃基板，包括一个或多个第一导电通孔，所述第一导电通孔包括贯穿所述玻璃基板的通孔以及所述通孔内填充的导电材料；以及电互连结构，布置在所述玻璃基板的第一表面上，其中，所述电互连结构包括一层或多层布线层以及包覆所述一层或多层布线层的包覆层，所述包覆层为介电材料，所述一层或多层布线层用于对封装在所述转接板上的光芯片上方的多个电芯片进行电互连，并且所述电互连结构还包括贯穿所述电互连结构的一个或多个第一导电结构，其与所述一个或多个第一导电通孔分别电连接。
在一些实施例中，所述多层布线层中至少两层布线层之间通过第二导电结构电连接。
在一些实施例中，所述包覆层是由氮化硅层和二氧化硅层交替堆叠形成的多层结构。
在一些实施例中，该转接板还包括：光波导结构，布置在所述电互连结构远离所述玻璃基板一侧的表面上，其中，所述光波导结构包括一层或多层光波导以及包围所述一层或多层光波导的包围层，所述一层或多层光波导用于对封装在所述转接板上的多个光芯片进行光互连，其折射率大于所述包围层的折射率，并且所述光波导结构还包括贯穿所述光波导结构的一个或多个第三导电结构，其与所述一个或多个第一导电结构分别电连接。
在一些实施例中，所述一层或多层光波导为氮化硅光波导，并且所述包覆层的材料为二氧化硅。
在一些实施例中，该转接板还包括：电介质层，布置在所述玻璃基板的第二表面上；一个或多个导电凸块，布置在所述电介质层远离所述玻 璃基板一侧的表面上，其中，所述电介质层包括贯穿所述电介质层的一个或多个第四导电结构，其与所述一个或多个第一导电通孔分别电连接，并且所述一个或多个导电凸块与所述一个或多个第四导电结构分别电连接。
本公开的第四方面提供了一种用于光芯片封装的转接板的制造方法，包括：提供一玻璃基板，并在所述玻璃基板中形成一个或多个导电通孔；在所述玻璃基板的第一表面上布置光波导结构，其中，所述光波导结构包括一层或多层光波导以及包覆所述一层或多层光波导的包覆层；以及在所述包覆层中形成贯穿所述光波导结构的一个或多个第一导电结构，并将其与所述一个或多个导电通孔分别电连接，其中，所述一层或多层光波导的折射率大于所述包覆层的折射率。
在一些实施例中，所述一层或多层光波导为氮化硅光波导，并且所述包覆层的材料为二氧化硅。
在一些实施例中，在所述玻璃基板的第一表面上布置光波导结构包括：a.采用晶圆级纳米压印光刻技术，在所述玻璃基板的第一表面上形成光波导的网络；b.在所述光波导上方沉积包覆层材料。
在一些实施例中，所述转接板的制造方法还包括：在所述玻璃基板的第二表面上布置电介质层；在所述电介质层中形成贯穿所述电介质层的一个或多个第二导电结构，并且将其与所述一个或多个导电通孔分别电连接；以及在所述电介质层远离所述玻璃基板一侧的表面上布置一个或多个导电凸块，其中所述一个或多个导电凸块与所述一个或多个第二导电结构分别电连接。
在一些实施例中，在玻璃基板中形成一个或多个导电通孔包括：在所述玻璃基板中通过刻蚀形成一个或多个通孔；以及在所述一个或多个通孔的内表面上设置导电材料层以形成所述一个或多个导电通孔。
在一些实施例中，在所述一个或多个通孔的内表面上设置导电材料层以形成所述一个或多个导电通孔包括：采用电镀的方法在所述一个或多个通孔内表面填充导电金属。
本公开的第五方面提供了另一种用于光芯片封装的转接板的制造方法，包括：提供一玻璃基板，并在所述玻璃基板内形成三维波导网络，其用于对封装在所述转接板上的多个光芯片进行光互连；在所述玻璃基板 中形成一个或多个导电通孔；在所述玻璃基板的第一表面上布置耦合光波导，使其覆盖所述三维波导网络的光输入输出口；在所述耦合光波导上覆盖包覆层以包覆所述耦合光波导；以及在所述包覆层中形成贯穿所述包覆层的一个或多个第一导电结构，并将其与所述一个或多个导电通孔分别电连接。
在一些实施例中，所述耦合光波导的折射率低于所述三维波导网络的折射率且高于所述包覆层的折射率。
在一些实施例中，所述耦合光波导为氮化硅光波导，并且所述包覆层的材料为二氧化硅。
在一些实施例中，所述转接板的制造方法还包括：在所述玻璃基板的第二表面上布置电介质层；在所述电介质层中形成贯穿所述电介质层的一个或多个第二导电结构，并且将其与所述一个或多个导电通孔分别电连接；以及在所述电介质层远离所述玻璃基板一侧的表面上布置一个或多个导电凸块，其中所述一个或多个导电凸块与所述一个或多个第二导电结构分别电连接。
在一些实施例中，在玻璃基板中形成一个或多个导电通孔包括：在所述玻璃基板中通过刻蚀形成一个或多个通孔；以及在所述一个或多个通孔的内表面上设置导电材料层以形成所述一个或多个导电通孔。
在一些实施例中，在所述一个或多个通孔的内表面上设置导电材料层以形成所述一个或多个导电通孔包括：采用电镀的方法在所述一个或多个通孔内表面填充导电金属。
在一些实施例中，在所述玻璃基板内形成三维波导网络包括：采用飞秒激光照射所述玻璃基板的预设位置，以提高所述玻璃基板的所述预设位置的折射率，其中所述预设位置为形成所述三维波导网络结构所在的位置。
本公开的第六方面提供了另一种用于光芯片封装的转接板的制造方法，包括：提供一玻璃基板，并在所述玻璃基板中形成一个或多个第一导电通孔；在所述玻璃基板的第一表面上布置电互连结构，其中，所述电互连结构包括一层或多层布线层以及包覆所述一层或多层布线层的包覆层，所述包覆层为介电材料，所述一层或多层布线层用于对封装在所述转 接板上方的多个电芯片进行电互连；以及在所述电互连结构中形成贯穿所述电互连结构的一个或多个第一导电结构，其与所述一个或多个第一导电通孔分别电连接。
在一些实施例中，在所述玻璃基板的第一表面上布置电互连结构包括：在所述玻璃基板的第一表面上布置第一布线层；在所述第一布线层周围形成第一氮化硅子层；以及在所述第一氮化硅子层上覆盖第一氧化硅子层。
在一些实施例中，在所述玻璃基板的第一表面上布置电互连结构还包括：在所述第一氧化硅子层的第一表面上布置第二布线层；在所述第二布线层周围形成第二氮化硅子层；以及在所述第二氮化硅子层上覆盖第二氧化硅子层。
在一些实施例中，在所述玻璃基板的第一表面上布置电互连结构还包括：在所述第一布线层和所述第二布线层之间形成第二导电结构，以将所述第一布线层和所述第二布线层进行电连接。
在一些实施例中，所述转接板的制造方法还包括：在所述电互连结构远离所述玻璃基板一侧的表面上布置光波导结构，其中，所述光波导结构包括一层或多层光波导以及包围所述一层或多层光波导的包围层，所述一层或多层光波导用于对封装在所述转接板上的多个光芯片进行光互连，其折射率大于所述包围层的折射率；以及在所述光波导结构中形成贯穿所述光波导结构的一个或多个第三导电结构，并将其与所述一个或多个第一导电结构分别电连接。
在一些实施例中，所述一层或多层光波导为氮化硅光波导，并且所述包覆层的材料为二氧化硅。
在一些实施例中，所述转接板的制造方法还包括：在所述玻璃基板的第二表面上布置电介质层；在所述电介质层中形成贯穿所述电介质层的一个或多个第四导电结构，并且与所述一个或多个第一导电通孔分别电连接；以及在所述电介质层远离所述玻璃基板一侧的表面上布置一个或多个导电凸块，其中所述一个或多个导电凸块与所述一个或多个第四导电结构分别电连接。
在一些实施例中，在玻璃基板中形成一个或多个导电通孔包括：在 所述玻璃基板中通过刻蚀形成一个或多个通孔；以及在所述一个或多个通孔的内表面上设置导电材料层以形成所述一个或多个导电通孔。
在一些实施例中，在所述一个或多个通孔的内表面上设置导电材料层以形成所述一个或多个导电通孔包括：采用电镀的方法在所述一个或多个通孔内表面填充导电金属。
本公开的第七方面提供了一种光芯片封装结构，其包括如上所述的转接板，以及布置在所述转接板上的多个光芯片，所述转接板用于对布置在所述转接板上的所述多个光芯片进行光互连。
在一些实施例中，所述光芯片封装结构还包括：设置在所述多个光芯片上的一个或多个电芯片；所述光芯片包括一个或多个互连结构，所述互连结构包括贯穿所述光芯片的通孔以及通孔内填充的导电材料；所述一个或多个互连结构与所述转接板上的所述一个或多个第一导电结构或电互连结构分别电连接。
本公开的第八方面提供了一种光芯片封装结构，包括：转接板，包括嵌入其中的一个或多个第一光波导；以及多个光芯片，每个光芯片包括嵌入其中的一个或多个第二光波导，其中，所述多个光芯片贴合到所述转接板的上表面上的不同位置处，并通过所述一个或多个第一光波导进行光互连，每个所述第一光波导包括第一光耦合部，每个所述第二光波导包括第二光耦合部，并且所述第一光耦合部与所述第二光耦合部在垂直于所述转接板的上表面的方向上叠置且间隔预定距离，使得所述第一光耦合部与所述第二光耦合部实现光的绝热耦合。
在一些实施例中，所述第一光耦合部和所述第二光耦合部分别为锥形形状。
在一些实施例中，所述第一光耦合部和所述第二光耦合部分别具有由两个不同尺寸的锥形形状级联形成的形状。
在一些实施例中，所述预定距离小于或等于600nm。
在一些实施例中，该光芯片封装结构还包括：布置在所述多个光芯片中的多个第一光芯片上的多个电芯片，其中，每个第一光芯片的上表面上具有一个或多个第一电连接件，每个电芯片的下表面上具有一个或多个第二电连接件，并且所述一个或多个第一电连接件分别与所述一个或多个 第二电连接件电连接。
在一些实施例中，所述第一光芯片还包括贯穿其中的一个或多个第二导电通孔，所述一个或多个第二导电通孔与所述转接板中的一个或多个导电结构分别电连接。
在一些实施例中，所述第一光芯片与所述电芯片直接键合；或者所述第一光芯片与所述电芯片之间通过倒装焊(flip-chip)贴合。
在一些实施例中，所述多个光芯片为分割光子晶圆后所得的分离光芯片，其在所述转接板的上表面上相互间隔开且互相之间的间隙由注塑材料填充，并且所述注塑材料与所述转接板的上表面之间布置有用于阻挡所述转接板中的光向外传输的介电层。
在一些实施例中，所述多个光芯片为同一个光子晶圆中未分割的多个光芯片。
在一些实施例中，所述多个光芯片为同一个光子晶圆中未分割的光芯片，所述多个光芯片中具有多个第一光芯片，每个第一光芯片上布置有电芯片，所述多个第一光芯片上的多个电芯片为同一个电子晶圆中未分割的多个电芯片，并且所述光子晶圆与所述电子晶圆直接键合。
在一些实施例中，所述多个光芯片中的全部光芯片上都布置有对应的电芯片，并且全部光芯片上的对应的电芯片为同一个电子晶圆中未分割的多个电芯片，并且其中所述多个光芯片具有相同的结构，并且所述多个电芯片也具有相同的结构。
在一些实施例中，所述转接板是如前所述的转接板，并且所述一个或多个第一光波导是如前所述的转接板的光波导结构中的一层或多层光波导。
在一些实施例中，所述转接板是如前所述的转接板，并且所述一个或多个第一光波导是如前所述的转接板中的三维波导网络及覆盖所述三维波导网络的光输入输出口的耦合光波导。
本公开的第九方面提供了一种计算加速器，包括：一个或多个光源，其布置在如前所述的光芯片封装结构中的所述转接板的第一表面上，并且被配置为向所述计算加速器提供光波；一个或多个计算单元，其由如前所述的光芯片封装结构中的所述光芯片实现，或由如前所述的光芯片封装结 构中的所述光芯片和电芯片实现，或由如前所述的光芯片封装结构中的电芯片实现，并且被配置为执行计算功能；一个或多个存储单元，其由如前所述的光芯片封装结构中的电芯片实现，并且被配置为执行存储功能。
在一些实施例中，所述转接板是如前所述的转接板。
本公开的第九方面提供了一种计算加速器，包括：一个或多个边缘光耦合器，其被配置为将所述计算加速器与其它装置进行光互连；一个或多个光源，被配置为向所述计算加速器提供光波，所述光波通过导光结构耦合到所述一个或多个边缘光耦合器；一个或多个计算单元，其由如前所述的光芯片封装结构中的所述光芯片实现，或由如前所述的光芯片封装结构中的所述光芯片和电芯片实现，或由如前所述的光芯片封装结构中的电芯片实现，并且被配置为执行计算功能；以及一个或多个存储单元，其由如前所述的光芯片封装结构中的电芯片实现，并且被配置为执行存储功能。
在一些实施例中，由如前所述的光芯片封装结构中的每个光芯片及对应的电芯片实现每个计算单元和对应的存储单元，作为计算-存储单元。
在一些实施例中，所述的光芯片封装结构中的转接板是如前所述的转接板。
在一些实施例中，该计算加速器还包括：叠置在所述的光芯片封装结构中的所述光芯片上的多个高带宽内存(HBM)芯片，其被配置为执行内存计算功能。
本公开的第十方面提供了一种光芯片封装结构的制造方法，包括：提供一转接板，其包括嵌入其中的一个或多个第一光波导，每个所述第一光波导包括第一光耦合部；以及将多个光芯片贴合到所述转接板的上表面上的不同位置处，每个光芯片包括嵌入其中的一个或多个第二光波导，每个所述第二光波导包括第二光耦合部，其中所述第一光耦合部与所述第二光耦合部在垂直于所述转接板的上表面的方向上叠置且间隔预定距离，使得所述第一光耦合部与所述第二光耦合部实现光的绝热耦合，并且所述多个光芯片通过所述一个或多个第一光波导进行光互连。
在一些实施例中，所述第一光耦合部和所述第二光耦合部分别为锥形形状。
在一些实施例中，所述第一光耦合部和所述第二光耦合部分别具有由两个不同尺寸的锥形形状级联形成的形状。
在一些实施例中，所述预定距离小于或等于600nm。
在一些实施例中，在将多个光芯片贴合到所述转接板的上表面上的不同位置处之前，还包括：在所述多个光芯片中的第一光芯片上布置电芯片，使得所述第一光芯片和其上的电芯片形成电子-光子混合芯片，其中，所述第一光芯片的上表面上具有一个或多个第一电连接件，所述电芯片的下表面上具有一个或多个第二电连接件，并且所述一个或多个第一电连接件分别与所述一个或多个第二电连接件电连接。
在一些实施例中，在所述多个光芯片中的第一光芯片上布置电芯片包括：制备光子晶圆和电子晶圆，所述光子晶圆包括多个第一光芯片，所述电子晶圆包括多个电芯片；将所述电子晶圆直接键合到所述光子晶圆，使得所述多个第一光芯片与所述多个电芯片键合，以得到电子-光子混合晶圆；去除所述光子晶圆的衬底；以及将所述电子-光子混合晶圆切割成多个电子-光子混合芯片。
在一些实施例中，在所述多个光芯片中的第一光芯片上布置电芯片包括：制备光子晶圆和电子晶圆，所述光子晶圆包括所述多个光芯片，所述电子晶圆包括多个电芯片；将所述电子晶圆切割成所述多个电芯片；将所述多个电芯片中的一个或多个直接键合或者倒装焊(flip-chip)到所述光子晶圆中的第一光芯片上，以得到电子-光子混合晶圆；在所述光子晶圆上未被所述电子芯片占据的间隙中填充注塑材料；去除所述光子晶圆的衬底；以及将所述电子-光子混合晶圆切割成所述电子-光子混合芯片。
在一些实施例中，该方法还包括：在去除所述光子晶圆的衬底之后，将所述电子-光子混合晶圆切割成所述电子-光子混合芯片之前，减薄所述光子晶圆底面的埋置氧化层至预定的厚度。
在一些实施例中，该方法还包括：在去除所述光子晶圆的衬底之后，减薄所述光子晶圆底面的埋置氧化层，在所述光子晶圆远离所述电芯片的表面上形成连接波导，所述连接波导与所述第二光波导的所述第二光耦合部、所述第一波导的所述第一光耦合部在光子晶圆的下表面的垂直方向上叠置且间隔开；以及在所述连接波导上覆盖电介质以包覆所述连接波导。 在一些实施例中，该方法还包括：在制备所述光子晶圆之后，在所述光子晶圆中形成一个或多个第二导电孔；以及在去除所述光子晶圆的衬底之后，减薄所述光子晶圆底面的埋置氧化层至预定厚度，使所述一个或多个第二导电孔上下贯通以形成一个或多个第二导电通孔。
在一些实施例中，将所述多个光芯片贴合到所述转接板的上表面上的不同位置处还包括：将所述一个或多个第二导电通孔与所述转接板中的一个或多个导电结构分别电连接。
在一些实施例中，所述多个电子-光子混合芯片在所述转接板的上表面上相互间隔开，并且所述方法还包括：在所述转接板的上表面上且在所述多个电子-光子混合芯片之间的间隙中形成用于阻挡所述转接板中的光向外传输的介电层；以及在所述介电层上且在所述电子-光子小芯片的间隙中填充注塑材料。
在一些实施例中，在所述多个光芯片中的第一光芯片上布置电芯片包括：制备光子晶圆和电子晶圆，所述光子晶圆包括多个第一光芯片，所述电子晶圆包括多个电芯片，以及将所述电子晶圆直接键合到所述光子晶圆，使得所述多个第一光芯片与所述多个电芯片键合，以得到电子-光子混合晶圆；以及将多个光芯片贴合到所述转接板的上表面上的不同位置处包括：将所述电子-光子混合晶圆直接键合到所述转接板的上表面上。
在一些实施例中，所述转接板是如前所述的方法制造的转接板，并且所述一个或多个第一光波导是如前所述的方法制造的转接板中的光波导结构中的一层或多层光波导。
在一些实施例中，所述转接板是如前所述的方法制造的转接板，并且所述一个或多个第一光波导是如前所述的方法制造的转接板中的三维波导网络及覆盖所述三维波导网络的光输入输出口的耦合光波导。
附图说明
图1示出了本公开的实施例的用于光芯片封装的转接板的第一示例的横截面图。
图2示出了本公开的实施例的用于光芯片封装的转接板的第二示例的横截面图。
图3示出了本公开的实施例的用于光芯片封装的转接板的第三示例的横截面图。
图4示出了本公开的实施例的用于光芯片封装的转接板的第四示例的横截面图。
图5示出了本公开的实施例的第一示例中的转接板的制造方法的工艺流程图。
图6示出了本公开的实施例的第二示例中的转接板的制造方法的工艺流程图。
图7A示出了本公开的实施例的第三示例中的转接板的制造方法的工艺流程图。
图7B示出了本公开的实施例的第四示例中的转接板的制造方法的工艺流程图。
图8示出了集成了本公开的实施例的第一示例中的转接板的光芯片封装结构的横截面图。
图9示出了集成了本公开的实施例的第二示例中的转接板的光芯片封装结构的横截面图。
图10示出了集成了本公开的实施例的第三示例中的转接板的光芯片封装结构的横截面图。
图11示出了集成了本公开的实施例的第四示例中的转接板的光芯片封装结构的横截面图。
图12A和图12B分别示出了本公开的实施例的光芯片封装结构的横截面图和俯视图。
图13和图14分别示出了本公开的实施例的光芯片封装结构中的光耦合部的示意侧视图和俯视图、以及对应的光模场的图。
图15示出了本公开的实施例的光芯片封装结构中的光耦合部在不同长度下的光传输率的图表。
图16示出了本公开的实施例的光芯片封装结构中的光耦合部在不同间距下的光传输率的图表。
图17示出了本公开的实施例的光芯片封装结构中的光耦合部在不同厚度下的光传输率的图表。
图18和图19分别示出了本公开的实施例的光芯片封装结构中的光耦合部的另一示意侧视图和俯视图、以及对应的光模场的图。
图20和图21分别示出了本公开的实施例的光芯片封装结构的横截面图和俯视图。
图22示出了本公开的实施例的光芯片封装结构中的光芯片和电芯片的横截面图。
图23示出了本公开的实施例的光芯片封装结构中的光芯片和电芯片的横截面图。
图24示出了本公开的实施例的光芯片封装结构的横截面图。
图25示出了本公开的实施例的光芯片封装结构的横截面图。
图26和图27分别示出了本公开的实施例的光芯片封装结构的横截面图和俯视图。
图28、和图29A-图29B分别示出了本公开的实施例的光芯片封装结构的横截面图和俯视图。
图30示出了本公开的实施例的计算加速器的示意图。
图31A示出了本公开的实施例的另一计算加速器的示意图。
图31B示出了本公开的实施例的又一计算加速器的示意图。
图32-37示出了本公开的实施例的光芯片封装结构的制造方法的流程图。
具体实施方式
下面将参照附图更详细地描述本公开的实施例。虽然附图中示出了本公开的一些实施例，然而，应当理解的是，本公开不应该被解释为限于这里阐述的实施例，相反地，提供这些实施例是为了更加透彻和完整地理解本公开。应当理解的是，本公开的附图及实施例仅用于示例性作用，并非用于限制本公开的保护范围。
应当理解的是，本公开的方法实施方式中记载的各个步骤可以按照不同的顺序执行，和/或并行执行。此外，方法实施例可以包括其它的步骤和/或省略某些步骤。
本公开的实施例提供了一种用于光芯片封装的转接板。图1示出了 本公开的实施例的用于光芯片封装的转接板100的横截面图。图5示出了本公开的实施例的转接板100的制造方法的工艺流程图。为了更清楚地描述本公开，以下将结合图1和5分别描述转接板100的具体结构和制造方法。
如图1所示，转接板100在总体结构上可以划分为三层，从下往上依次是电介质层103、玻璃基板101以及光波导结构102。
玻璃基板101的材料通常为二氧化硅，其中包括一个或多个导电通孔，为了便于描述，图1中仅仅示出了一个导电通孔101-1。如图所示，导电通孔101-1包括贯穿玻璃基板101的通孔以及通孔内填充的导电材料(图中用横向阴影表示)。
光波导结构102布置在玻璃基板101的第一表面(如图所示的上表面)上。通常情况下，光波导结构102包括一层或多层光波导以及包覆一层或多层光波导的包覆层。在图1中，为了便于描述，仅仅示出了一层光波导102-1以及包覆该光波导的包覆层102-2。在转接板100上封装了多个光芯片的情况下，光波导结构102中的一层或多层光波导可以用于对封装在其上的多个光芯片进行光互连。光波导结构102中的一层或多层光波导的折射率大于包覆层102-2以及玻璃基板101的折射率，例如，一层或多层光波导可以是折射率较高的氮化硅光波导，并且包覆层102-2和玻璃基板101的材料可以是折射率相对较低的二氧化硅。
如图1所示，光波导结构102中还包括贯穿光波导结构的一个或多个第一导电结构102-3，其与玻璃基板中的上述一个或多个导电通孔101-1分别电连接。如图所示的一个或多个第一导电结构102-3可用于对封装在转接板上的光芯片或电芯片进行垂直的电气连接。第一导电结构102-3可以是插塞(plug)结构，例如铜插塞，当然也可以包括其它金属材料或导电材料。
电介质层103布置在玻璃基板101的第二表面(如图所示的下表面)上，其包括贯穿所述电介质层的一个或多个第二导电结构。在电介质层103远离玻璃基板101一侧的表面(即如图所示的下表面)上布置有一个或多个导电凸块104，其与所述一个或多个第二导电结构分别电连接。例如，根据电连接的需要，第二导电结构可以包括如图所示的再布线层 103-3和下方的导电孔结构103-2。导电凸块104可以是可控塌陷芯片连接(C4)凸块、球栅阵列(BGA)连接件、焊球、金属柱、微凸块等。导电凸块104可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合的导电材料。在一些实施例中，可以通过首先由诸如蒸发、电镀、印刷等常用的方法形成焊料层来形成导电凸块104。在一些实施例中，导电凸块104是通过溅射、电镀、化学镀等形成的金属柱，诸如铜柱。
需要说明的是，转接板100也可以不包括电介质层103以及导电凸块104。
以上结合图1描绘了用于光芯片封装的转接板100的具体结构，下面将结合图5来详细说明转接板100的制造方法。
如图5所示，在步骤(a)中，首先提供玻璃基板101，并在玻璃基板101中形成一个或多个导电通孔101-1。在一些实施例中，可以通过刻蚀加电镀的方法在玻璃基板101中形成导电通孔101-1。例如，可以首先玻璃基板中通过激光钻孔刻蚀形成一个或多个通孔，然后在一个或多个通孔的内表面上设置导电材料层以形成所述一个或多个导电通孔。具体地，例如可以使用自下而上的电镀的方法在一个或多个通孔内表面填充导电金属，从而形成导电通孔。
在玻璃基板101中形成导电通孔101-1之后，在步骤(b)-(c)中，可以在玻璃基板101的第一表面(如图所示的上表面)上布置光波导结构。例如，如(b)-(c)所示，光波导结构包括一层或多层光波导102-1以及包覆所述一层或多层光波导的包覆层102-2。为了便于描述，图5中仅示出了单层光波导的示例。
具体地，在步骤(b)中，例如可以采用晶圆级纳米压印光刻技术，在玻璃基板101的第一表面上形成光波导102-1。
需要说明的是，相比于与现有技术中的纳米压印技术，本公开采用的晶圆级纳米压印光刻技术做出了如下改善。为了实现晶圆级波导布线而不需典型步进光刻的标线尺寸限制，本公开使用了晶圆级无掩模光刻技术，例如电子束或激光写入。例如，首先可以使用氧化物、氮化物叠层制造压印母版，该叠层是使用电子束光刻图案化形成的。然后，通过使用该压印母版，进行步进-重复操作，在聚合物上生成基于聚合物(例如PDMS，聚 二甲基硅氧烷)的纳米印章。需要说明的是，该纳米印章是晶圆级的，也就是说，通过如上所述的步进-重复操作，将整个光波导图案完整地、连贯地形成在同一个纳米印章中。与传统的非晶圆级的印章相比，当使用生成的晶圆级纳米印章在氮化物沉积的玻璃晶片上进行纳米压印时，会将将抗蚀剂图案一次性转移到玻璃晶片上，有助于形成一体成型的氮化物波导。传统的非晶圆级的印章则需要多次进行压印以进行波导拼接，在多次压印的过程中容易出现不对准的问题，从而影响光波导的质量，进而导致光信号损失。
通过如上所述的晶圆级的纳米压印方法，所形成的光波导在整个玻璃晶圆都是连续的，中间不需要波导拼接，能够最大程度地避免光信号损失。
然后在步骤(c)中，在光波导102-1上方沉积包覆层材料从而形成包覆层102-2。取决于具体需要，可以重复以上步骤(b)-(c)，从而能够形成具有多层光波导的光波导结构。此外，在步骤(c)中，还可以在包覆层102-2中形成贯穿光波导结构的一个或多个第一导电结构102-3，并将其与玻璃基板101中一个或多个导电通孔101-1分别电连接。
如上所述，光波导102-1的折射率大于包覆层102-2以及玻璃基板101的折射率，例如，光波导102-1可以是折射率较高的氮化硅光波导，并且包覆层102-2和玻璃基板101的材料可以是折射率相对较低的二氧化硅。
可选地，转接板100的制造方法还可以包括：在玻璃基板101的第二表面上布置电介质层103、在电介质层103中形成贯穿所述电介质层的一个或多个第二导电结构并将其与一个或多个导电通孔101-1分别电连接、以及在电介质层103远离玻璃基板一侧的表面上布置一个或多个导电凸块104。
图5中的步骤(d)-(f)示出了上述处理流程的示例性详细步骤。
例如，可以首先在步骤(d)中，在玻璃基板101的底面形成再布线层103-3，用于进行电气连接。接着，在步骤(e)中，在玻璃基板101的底面上布置电介质层103，并且使其覆盖在(d)中形成的再布线层103-3的一部分，同时需要在电介质层103中形成对应于再布线层103-3和导 电通孔101-1的缺口103-4，从而在步骤(f)中通过在缺口103-4中填充导电材料以形成导电孔结构103-2，使得导电孔结构103-2与再布线层103-3以及玻璃基板中的导电通孔101-1电连接。在这种情况下，导电孔结构103-2与再布线层103-3共同构成上述第二导电结构，其贯穿电介质层103并与玻璃基板101中的导电通孔101-1电连接。
在步骤(f)中，在电介质层103远离玻璃基板一侧的表面上布置一个或多个导电凸块104，并且使导电凸块104与第二导电结构(即导电孔结构103-2与再布线层103-3)电连接。
至此，结合图1和图5描绘了用于光芯片封装第一示例中的转接板100的具体结构和制造方法。通过在玻璃基板的表面上布置光波导结构，可以使得封装在该转接板上的光芯片之间实现光互连，从而避免了制造嵌入式TSV的硅转接板存在的成本问题和工艺难度问题。此外，由于使用如上所述的晶圆级的纳米压印方法在玻璃基板中形成光波导，所形成的光波导在整个玻璃晶圆都是连续的，中间不需要波导拼接，能够最大程度地避免光信号损失。
以下将结合图2和6分别描述用于光芯片封装的转接板另一示例的具体结构和制造方法。图2示出了本公开的实施例的用于光芯片封装的转接板200的横截面图。图6示出了本公开的实施例的转接板200的制造方法的工艺流程图。
如图2所示，转接板200在总体结构上可以类似地划分为三层，从下往上依次是电介质层203、玻璃基板201以及光耦合结构202。
玻璃基板201的材料通常为二氧化硅，其中包括一个或多个导电通孔，为了便于描述，图2中仅仅示出了一个导电通孔201-1。如图所示，导电通孔201-1包括贯穿玻璃基板201的通孔以及通孔内填充的导电材料(图中用横向阴影表示)。
此外，玻璃基板201中还包括三维波导网络201-2(如图所示的曲线)，用于对封装在转接板201上的多个光芯片进行光互连。三维波导网络201-2是通过在玻璃基板201内部诱导局部玻璃，使局部玻璃的折射率提高而构成的，并且其具有分布在整个玻璃基板201的内部的多条通路形成的三维立体网络结构。例如，可以使用超快(例如，飞秒)激光刻写工 艺在玻璃基板内部创建嵌入式的三维波导网络。
光耦合结构202布置在玻璃基板201的第一表面(例如，上表面)上。如图所示，光耦合结构202包括覆盖三维波导网络201-2的光输入输出口的耦合光波导202-1以及包覆耦合光波导202-1的包覆层202-2。此外，光耦合结构202还包括贯穿光耦合结构的一个或多个第一导电结构202-3，其与所述玻璃基板201中的一个或多个导电通孔201-1分别电连接。
需要说明的是，耦合光波导202-1的折射率可以低于三维波导网络201-2的折射率，但是高于包覆层202-2的折射率。例如，耦合光波导202-1可以是氮化硅光波导，并且包覆层202-2的材料可以是二氧化硅。另外，需要说明的是，转接板200中虽然包括与图1中所示的转接板100中类似的嵌入式光波导202-1，但二者的作用是不一样的。在图1所示的转接板100中，光波导结构102中的光波导102-1用于不同光芯片之间的光互连，但是在如图2所示的转接板200中，光耦合结构202中的耦合光波导202-1用于光“耦合”的作用，其可以提高三维波导网络和光芯片之间的光耦合效率。
与转接板100类似，转接板200中的电介质层203布置在玻璃基板201的第二表面(如图所示的下表面)上，其包括贯穿所述电介质层的一个或多个第二导电结构。在电介质层203远离玻璃基板201一侧的表面(即如图所示的下表面)上布置有一个或多个导电凸块204，其与所述一个或多个第二导电结构分别电连接。根据电连接的需要，第二导电结构可以包括如图所示的再布线层203-3和下方的导电孔结构203-2。导电凸块204可以是可控塌陷芯片连接(C4)凸块、球栅阵列(BGA)连接件、焊球、金属柱、微凸块等，其类似于如图1所述的导电凸块104，在此不再赘述。
需要说明的是，转接板200也可以不包括电介质层203以及导电凸块204。
以上结合图2描绘了用于光芯片封装的转接板200的具体结构，下面将结合图6来详细说明转接板200的制造方法。
如图6所示，首先在步骤(a)中，提供玻璃基板201，并在玻璃基板201内形成三维波导网络201-2，其用于对封装在转接板上的多个光芯 片进行光互连。在一些示例中，可以使用超快(例如，飞秒)激光刻写工艺在玻璃基板内部创建嵌入式的三维波导网络。例如，可以采用飞秒激光照射玻璃基板201的预设位置，以提高玻璃基板201的预设位置的折射率，从而形成三维波导网络201-2。例如，预设位置可以是形成三维波导网络结构所在的位置。
然后，在步骤(b)中，在玻璃基板201中形成一个或多个导电通孔201-1。在一些实施例中，可以通过刻蚀加电镀的方法在玻璃基板201中形成导电通孔201-1。例如，可以首先玻璃基板中通过激光钻孔刻蚀形成一个或多个通孔，然后在一个或多个通孔的内表面上设置导电材料层以形成所述一个或多个导电通孔。具体地，例如可以使用自下而上的电镀的方法在一个或多个通孔内表面填充导电金属，从而形成导电通孔。
在玻璃基板201中形成导电通孔201-1之后，在步骤(c)-(d)中，可以在玻璃基板201的第一表面(如图所示的上表面)上布置光耦合结构。例如，如图所示，光耦合结构包括耦合光波导202-1以及包覆耦合光波导的包覆层202-2。具体地，在步骤(c)中，可以采用光刻技术，在玻璃基板201的第一表面上形成耦合光波导202-1，使其覆盖三维波导网络201-2的光输入输出口。然后在步骤(d)中，在耦合光波导202-1上方沉积包覆层材料从而形成包覆层202-2。此外，在步骤(d)中，还可以在包覆层202-2中形成贯穿光耦合结构的一个或多个第一导电结构202-3，并将其与玻璃基板201中一个或多个导电通孔201-1分别电连接。
需要说明的是，耦合光波导202-1的折射率可以大于包覆层202-2以及玻璃基板201的折射率，例如，耦合光波导202-1可以是折射率较高的氮化硅光波导，并且包覆层202-2和玻璃基板201的材料可以是折射率相对较低的二氧化硅。
可选地，转接板200的制造方法还可以包括：在玻璃基板201的第二表面上布置电介质层203、在电介质层203中形成贯穿所述电介质层的一个或多个第二导电结构并将其与一个或多个导电通孔201-1分别电连接、以及在电介质层203远离玻璃基板一侧的表面上布置一个或多个导电凸块204。
图6中的步骤(e)-(g)示出了上述处理流程的示例详细步骤。
例如，可以首先在步骤(e)中，在玻璃基板201的底面形成再布线层203-3，用于进行电气连接。接着，在步骤(f)中，在玻璃基板201的底面上布置电介质层203，并且使其覆盖在(e)中形成的再布线层203-3的一部分，同时需要在电介质层203中形成对应于再布线层203-3和导电通孔201-1的缺口203-4，从而在步骤(g)中通过在缺口203-4中填充导电材料以形成导电孔结构203-2，使得导电孔结构203-2与再布线层203-3以及玻璃基板中的导电通孔201-1电连接。在这种情况下，导电孔结构203-2与再布线层203-3共同构成上述第二导电结构，其贯穿电介质层203并与玻璃基板201中的导电通孔201-1电连接。
在步骤(g)中，在电介质层203远离玻璃基板一侧的表面上布置一个或多个导电凸块204，并且使导电凸块204与第二导电结构(即导电孔结构203-2与再布线层203-3)电连接。
至此，结合图2和图6描绘了用于光芯片封装第二示例中的转接板200的具体结构和制造方法。转接板200通过在玻璃基板内部形成三维光波导网络，对封装在转接板200上方的多个光芯片进行互连，因此，可以在不增加转接板的厚度的情况下形成更为丰富和高效的三维立体光波导通路，从而可以有效地压缩光芯片封装的体积。另外，由于三维光波导网络的光输入和输出处还布置了如上所述的氮化硅耦合光波导，从而能够大大提高光芯片和转接板之间的光耦合效率。
以下将结合图3和图7A分别描述用于光芯片封装的转接板另一示例的具体结构和制造方法。图3示出了本公开的实施例的用于光芯片封装的转接板300的横截面图。图7A示出了本公开的实施例的转接板300的制造方法的工艺流程图。
如图3所示，转接板300在总体结构上可以划分为三层，从下往上依次是电介质层303、玻璃基板301以及电互连结构302。
类似地，玻璃基板301的材料通常为二氧化硅，其中包括一个或多个导电通孔，为了便于描述，图3中仅仅示出了一个导电通孔301-1。如图所示，导电通孔301-1包括贯穿玻璃基板301的通孔以及通孔内填充的导电材料(图中用横向阴影表示)。
电互连结构302被布置在玻璃基板301的第一表面(如图所示的上 表面)上。在一些示例中，电互连结构302可以包括一层或多层布线层302-1a、302-1b、302-1c以及包覆一层或多层布线层的包覆层302-2。例如，包覆层302-2可以是介电材料，并且一层或多层布线层302-1a、302-1b、302-1c用于对封装在转接板上的光芯片上的多个电芯片进行电互连。电芯片可以与光芯片进行垂直封装，即电芯片封装在光芯片上，从而电芯片可以通过光芯片中的导电通孔与上述布线层电连接以实现电芯片的电互连。此外，布置在转接板上的光芯片可以是有源光芯片，各个有源光芯片之间也可以通过上述电互连结构302进行电连接。
图3示出了具有三层布线层(302-1a，302-1b，302-1c)的电互连结构302的示例。如图所示，每个布线层都被各自的包覆层所包覆。例如，对于布线层302-1a，其被由氮化硅层302-2a和二氧化硅层302-2b交替堆叠形成的多层结构包覆。对于布线层302-1b和布线层302-1c，其同样由类似的氮化硅层和二氧化硅层交替堆叠形成的多层结构包覆。应当理解的是，图3示出的三层布线层仅仅是示例性的，根据需要可以选择更多(例如，四层或更多层)或更少(例如，两层或一层)的布线层。
此外，如图所示，电互连结构302还包括贯穿电互连结构的一个或多个第一导电结构302-3，其与玻璃基板中的一个或多个第一导电通孔301-1分别电连接。
图3还示出了用于对多层布线层中至少两层布线层之间进行电连接的第二导电结构302-4。第二导电结构302-4可以用类似于第一导电结构302-3的方法或材料形成，例如，可以是导电通孔或铜插塞，也可以包括其它金属材料或导电材料。
电介质层303布置在玻璃基板301的第二表面(如图所示的下表面)上，其包括贯穿所述电介质层的一个或多个第二导电结构。在电介质层303远离玻璃基板301一侧的表面(即如图所示的下表面)上布置有一个或多个导电凸块305，其与所述一个或多个第二导电结构分别电连接。根据电连接的需要，第二导电结构可以包括如图所示的再布线层303-3和下方的导电孔结构303-2。导电凸块305可以是可控塌陷芯片连接(C4)凸块、球栅阵列(BGA)连接件、焊球、金属柱、微凸块等。导电凸块305可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合的导电 材料。在一些实施例中，可以通过首先由诸如蒸发、电镀、印刷等常用的方法形成焊料层来形成导电凸块305。在一些实施例中，导电凸块305是通过溅射、电镀、化学镀等形成的金属柱，诸如铜柱。
需要说明的是，转接板300也可以不包括电介质层303以及导电凸块305。
以上结合图3描绘了用于光芯片封装的转接板300的具体结构，下面将结合图7A来详细说明转接板300的制造方法。
如图7A所示，在步骤(a)中，首先提供玻璃基板301，并在玻璃基板301中形成一个或多个导电通孔301-1。在一些实施例中，可以通过刻蚀加电镀的方法在玻璃基板301中形成导电通孔301-1。例如，可以首先玻璃基板中通过激光钻孔刻蚀形成一个或多个通孔，然后在一个或多个通孔的内表面上设置导电材料层以形成所述一个或多个导电通孔。具体地，例如可以使用自下而上的电镀的方法在一个或多个通孔内表面填充导电金属，从而形成导电通孔。
在步骤(e)中，在玻璃基板301的第一表面(即，如图所示的上表面)上布置电互连结构302。如图所示，电互连结构302包括一层或多层布线层(302-1a，302-1b，302-1c)以及包覆一层或多层布线层的包覆层。例如，包覆层可以是介电材料，并且一层或多层布线层(302-1a，302-1b，302-1c)用于对封装在转接板上的光芯片上方的多个电芯片进行电互连。
图7A示出了具有三层布线层(302-1a，302-1b，302-1c)的电互连结构302的示例。如图所示，每个布线层都被各自的包覆层包覆。例如，对于布线层302-1a，其被由氮化硅层302-2a和二氧化硅层302-2b交替堆叠形成的多层结构包覆。对于布线层302-1b和布线层302-1c，其同样由类似的氮化硅层和二氧化硅层交替堆叠形成的多层结构包覆。应当理解的是，图3示出的三层布线层仅仅是示例性的，根据需要可以选择更多(例如，四层或更多层)或更少(例如，两层或一层)的布线层。
具体地，以图7A中的(e)为例，在玻璃基板301的第一表面上布置电互连结构302可包括以下具体步骤：首先，在玻璃基板301的上表面上布置第一布线层302-1a；然后，在第一布线层302-1a的周围形成第一氮化硅子层302-2a，第一氮化硅子层302-2a的厚度小于第一布线层302- 1a的厚度；接着，在第一氮化硅子层302-2a上覆盖第一氧化硅子层302-2b，并且使得第一氮化硅子层302-2a加第一氧化硅子层302-2b的总厚度等于第一布线层302-1a的厚度。之后，根据具体需要，可以重复以上步骤，再次在第一氧化硅子层302-2b上依次布置第二布线层302-1b、在第二布线层302-1b周围形成第二氮化硅子层、在第二氮化硅子层上覆盖第二氧化硅子层，等等，从而形成具有多个布线层的电互连结构。
此外，在玻璃基板301的第一表面上布置电互连结构302还可包括：在第一布线层302-1a和所述第二布线层302-1b之间形成第二导电结构302-4，以将第一布线层302-1a和所述第二布线层302-1b进行电连接。例如，可以首先在电互连结构302中包括布线层的位置处通过激光钻孔刻蚀形成一个或多个通孔，然后在一个或多个通孔的内表面上设置导电材料层以形成一个或多个第二导电结构302-4。具体地，例如可以使用自下而上的电镀的方法在一个或多个通孔内表面填充导电金属，从而形成第二导电结构302-4。此外，如图所示，在电互连结构302包括三层布线层(302-1a，302-1b，302-1c)的情况下，第二导电结构302-4同样存在于第二布线层302-1b和第三布线层302-1c之间，从而将第二布线层302-1b和第三布线层302-1c也进行电连接。
此外，在玻璃基板301的第一表面上布置电互连结构302还可包括：在电互连结构302中形成贯穿所述电互连结构的一个或多个第一导电结构302-3，其与玻璃基板301中的一个或多个第一导电通孔301-1分别电连接。
可选地，在一些实施例中，转接板300的制造方法还可以包括：在玻璃基板301的第二表面上布置电介质层303、在电介质层303中形成贯穿所述电介质层的一个或多个第四导电结构并将其与一个或多个导电通孔301-1分别电连接、以及在电介质层303远离玻璃基板一侧的表面上布置一个或多个导电凸块305。
图7A中的步骤(b)-(d)示出了上述处理流程的详细步骤。
例如，可以首先在步骤(b)中，在玻璃基板301的第二表面形成再布线层303-3，用于进行电气连接。接着，在步骤(c)中，在玻璃基板301的底面上布置电介质层303，并且使其覆盖在(b)中形成的再布线层 303-3的一部分，同时需要在电介质层303中形成对应于再布线层303-3和导电通孔301-1的缺口303-4，从而在步骤(d)中通过在缺口303-4中填充导电材料以形成导电孔结构303-2，使得导电孔结构303-2与再布线层303-3以及玻璃基板中的导电通孔301-1电连接。在这种情况下，导电孔结构303-2与再布线层303-3共同构成上述第四导电结构，其贯穿电介质层303并与玻璃基板301中的导电通孔301-1电连接。
在步骤(d)中，在电介质层303远离玻璃基板一侧的表面上布置一个或多个导电凸块305，并且使导电凸块305与第四导电结构(即导电孔结构303-2与再布线层303-3)电连接。
至此，已经结合图3和图7A描绘了用于光芯片封装第一示例中的转接板300的具体结构和制造方法。通过在玻璃基板的表面上布置电互连结构，可以使得封装在该转接板上的光芯片上方的电芯片之间实现电互连。
以下将结合图4和图7A-7B分别描述用于光芯片封装的转接板另一示例的具体结构和制造方法。图4示出了本公开的实施例的用于光芯片封装的转接板400的横截面图。图7A-7B示出了本公开的实施例的转接板400的制造方法的工艺流程图。
如图4所示，转接板400在总体结构上可以划分为四层，从下往上依次是电介质层303、玻璃基板301、电互连层302以及光波导结构304，其中电介质层303、玻璃基板301和电互连层302的布置和功能类似于图3所示的转接板300的布置和功能，在此不再赘述。
与图3所示的转接板300相比，图4所示的转接板400附加地包括光波导结构304。如图所示，光波导结构304布置在电互连结构302的远离玻璃基板301一侧的表面(即，上表面)上。在一些示例中，光波导结构304可以包括一层或多层光波导304-1以及包围一层或多层光波导304-1的包围层304-2。应当注意的是，为了简化说明，在图4中仅示出了具有一层光波导304-1的光波导结构的示例，但这仅仅是示例性的，可以根据需要布置两层、三层或更多层光波导。如图所示的光波导304-1用于对封装在转接板400上的多个光芯片进行光互连，并且光波导304-1的折射率大于包围层304-2的折射率。
此外，如图所示，光波导结构304还包括贯穿所述光波导结构的一 个或多个第三导电结构304-3，其与电互连结构302中的一个或多个第一导电结构分别电连接。
如图4所示的转接板400的制造方法除了包括如图7A所示的步骤(a)-(e)之外，还包括如图7B所示的步骤(f)。步骤(a)-(e)已经在关于转接板300的制造方法中详细描述，在此不再赘述。
在形成了如图7A中的(e)所示的包括电互连结构302的转接板之后，转接板400的制造方法还包括：在步骤(f)中，在电互连结构302远离玻璃基板301一侧的表面上布置光波导结构304。如上关于图4所述，光波导结构304可以包括一层或多层光波导304-1以及包围一层或多层光波导304-1的包围层304-2。可以使用如关于图5所述的类似技术来形成光波导结构304.例如，可以首先在电互连结构302上沉积包围层材料，然后采用晶圆级纳米压印光刻技术，在沉积的包围层材料上形成光波导304-1，然后在光波导304-1上再次沉积包围层材料使其完全包围光波导304-1，以形成包围层304-2。为了简化说明，在图7B中仅示出了具有一层光波导304-1的光波导结构的示例，但这仅仅是示例性的，可以根据需要布置两层、三层或更多层光波导。所述一层或多层光波导304-1用于对封装在转接板上的多个光芯片进行光互连，并且光波导304-1的折射率大于包围层304-2的折射率。例如，一层或多层光波导304-1可以是氮化硅光波导，并且包围层304-2的材料为二氧化硅。
同样地，需要说明的是，关于形成光波导304-1的方法，相比于与现有技术中的纳米压印技术，本公开采用的晶圆级纳米压印光刻技术做出了如下改善。为了实现晶圆级波导布线而不需典型步进光刻的标线尺寸限制，本公开使用了晶圆级无掩模光刻技术，例如电子束或激光写入。例如，首先可以使用氧化物、氮化物叠层制造压印母版，该叠层是使用电子束光刻图案化形成的。然后，通过使用该压印母版，进行步进-重复操作，在聚合物上生成基于聚合物(例如PDMS，聚二甲基硅氧烷)的纳米印章。需要说明的是，该纳米印章是晶圆级的，也就是说，通过如上所述的步进-重复操作，将整个光波导图案完整地、连贯地形成在同一个纳米印章中。与传统的非晶圆级的印章相比，当使用生成的晶圆级纳米印章在氮化物沉积的玻璃晶片上进行纳米压印时，会将将抗蚀剂图案一次性转移到玻璃晶片 上，有助于形成一体成型的氮化物波导。传统的非晶圆级的印章则需要多次进行压印以进行波导拼接，在多次压印的过程中容易出现不对准的问题，从而影响光波导的质量，进而导致光信号损失。
通过如上所述的晶圆级的纳米压印方法，所形成的光波导在整个玻璃晶圆都是连续的，中间不需要波导拼接，能够最大程度地避免光信号损失。
此外，转接板400的制造方法还可包括：在步骤(f)中，在光波导结构304中形成贯穿所述光波导结构的一个或多个第三导电结构304-3，并将其与电互连结构302中一个或多个第一导电结构分别电连接。
至此，已经结合图4和图7A-7B描绘了用于光芯片封装第一示例中的转接板400的具体结构和制造方法。通过在玻璃基板的表面上布置电互连结构，并且在电互连结构上布置光波导结构，可以使得封装在该转接板上的电芯片之间实现电互连，并且使封装在该转接板上的光芯片之间实现光互连。此外，通过如上所述的晶圆级的纳米压印方法，所形成的光波导在整个玻璃晶圆都是连续的，中间不需要波导拼接，能够最大程度地避免光信号损失。
应当理解的是，本公开的方法实施方式和附图中记载的各个步骤可以根据需要按照不同的顺序执行，和/或并行执行。此外，方法实施例可以包括其它的步骤和/或省略某些步骤。
需要说明的是，在以上针对转接板的描述中，虽然针对转接板的每一层(例如图1中的光波导结构102以及电介质层103)都描述了对应的导电结构及其制造方法，例如图1中的光波导结构102中的第一导电结构102-3以及电介质层103中的第二导电结构103-2，但是在一些实施例中，这些导电结构不必是分离的，并且可以是一体成型的，例如第一导电结构102-3和电介质层103中的第二导电结构103-2可以是贯穿整个转接板100的一体成型的铜插塞。这种一体成型的铜插塞同样适用于如图2-4所示的其他转接板。
以上描述了本公开的基于玻璃晶圆的转接板的结构和制造方法的一些实施例。相比于带有嵌入式TSV的硅转接板，基于玻璃晶圆的转接板结构简单、制造成本低且容易实现，并且能够有效地用于光芯片的光互 连和电芯片的电互连，为光电芯片的集成提供了很好的平台。
通过使用如上所述的各种实施例中的转接板，可以实现包括光芯片和电芯片的紧凑的、立体的三维封装结构。图8-11示出了集成了本公开的实施例中的转接板的各种光芯片封装结构的横截面图。
如图8所示，封装结构800包括转接板100和光芯片500。例如，转接板100可以是如图1所示的具有嵌入式光波导的转接板100，该转接板100可用于对布置在其上的多个光子-电子混合芯片中的光芯片进行光互连、多个光子-电子混合芯片中的电芯片进行电互连。优选的，光芯片制备在SOI衬底上，完成光芯片的前端制备工艺之后，去除SOI衬底中的底层硅基板，并控制埋置氧化层的厚度，将光芯片键合到转接板100上，光信号通过转接板100上的嵌入式光波导绝热耦合到光芯片上的光波导中，反之依然，从而实现片上的光网络通信。应当理解的是，为了简化说明，图8中仅仅示出了一个光芯片500，在实际应用中，转接板100上可以布置两个或更多个光芯片，其通过转接板100中的嵌入式光波导实现光互连。此外，如图所示，光芯片500还包括一个或多个互连结构501，该互连结构501包括贯穿光芯片的通孔以及通孔内填充的导电材料。如图所示，互连结构501与转接板100上的如前所述一个或多个第一导电结构102-3分别电连接。
在一些示例中，封装结构800还可以包括一个或多个光芯片，每个光芯片上设置一个或多个电芯片(图8-11中的EIC)。通常情况下，一个或多个电芯片EIC被布置在光芯片500的上方，并且通过电芯片中的导电结构(如图所示的UBM或其它连接结构，如直接键合等)与转接板中的导电结构进行垂直电连接。
图9至图11分别示出了对应于图2至图4的转接板被应用于光芯片的封装的示例结构。其中，光芯片500类似于图8中的光芯片，在此不再赘述。需要注意的是，如图10所示，在将如图3所示的具有电互连结构的转接板300应用于封装结构1000中时，光芯片500中的互连结构501可以与转接板300的电互连层中的导电结构302-3进行电连接。
此外，如上所述，转接板的各个层中的导电结构不一定是分离的，而可以是一体成型的，例如各个层中的导电结构可以是贯穿整个转接板的 一体成型的铜插塞，从而便于将转接板和电芯片之间进行电连接。
需要说明的是，在以上结合附图1-2和4描述的转接板中，都布置了用于对布置在转接板上的多个光芯片进行光互连的光波导，例如图1中的光波导102-1，图2中的202-1和202-2，以及图4中的304-1。将转接板中光波导与光芯片进行光学耦合的方式可以采用例如外接光纤的方式实现，然而这种方式占用空间大不利于封装结构的小型化。本公开的实施例提出采用绝热耦合实现光芯片与转接板中的光波导进行耦合的方式，以实现产品的小型化。以下将详细描述采用这种光波导的绝热耦合技术的光芯片封装结构及其制造方法的各种实施例。需要说明的是，在本公开中，用于绝热耦合的转接板不限于本公开前述的转接板，而可以是任何能够实现光芯片光互连的转接板。
图12A和图12B分别示出了本公开的实施例的光芯片封装结构1200的横截面图和俯视图。
如图12A所示，光芯片封装结构1200包括转接板1210以及布置在转接板1210上的多个光芯片(PIC)，通常的，光芯片采用SOI衬底制备，光芯片中的光波导设置在SOI衬底的埋氧层上。例如，由于图12A示出的是从特定位置切割开的剖面图，在图12A中仅仅可以看到两个光芯片PIC 1和PIC 2。但是实际上，如图12B的俯视图所示，光芯片封装结构1200可以包括PIC 1-PIC 6六个光芯片。应当理解的是，上述六个光芯片仅仅是示例性的而非限制，在实际应用中，光芯片封装结构1200可以包括更多或更少的光芯片。
如图12A所示，转接板1200包括嵌入其中的一个或多个第一光波导，例如图12A所示的光波导WG1-1和光波导WG1-2，其中，光波导WG1-1和光波导WG1-2可以是多根光波导排列成的阵列而构成的波导网络。光波导WG1-1和光波导WG1-2可以是如前所述的转接板中的光波导，例如图1中的光波导102-1，图2中的光波导202-1和202-2，或图4中的光波导304-1。此外，光波导WG1-1和光波导WG1-2的材料可以是如前所述的氮化硅，并且氮化硅上方覆盖氧化硅的包覆层。
光芯片PIC 1和PIC 2中的每一个包括嵌入其中的一个或多个第二光波导(为了简化说明，图12A中针对每个PIC仅示出单个光波导)，即 光波导WG2-1和光波导WG2-2。在一些示例中，光波导WG2-1和光波导WG2-2的材料可以为硅。如图12B所示，多个光芯片(PIC 1，…,PIC 6)贴合到转接板1210的上表面上的不同位置处。如图所示，PIC 1-PIC 6贴合到转接板1210上的正方形区域R1中的不同位置处并且彼此间隔。
光芯片PIC 1和PIC 2、或者如图12B所示的多个光芯片(PIC 1，…,PIC 6)中的任何两个之间可通过转接板1210中的一个或多个第一光波导进行光互连。例如，如图12A中的带箭头的虚线所示，光可以从PIC 1出发，然后通过WG2-1耦合到转接板1210中的光波导WG1-1中，然后经由其他光波导网络(未示出)传输到光波导WG1-2，进而再耦合到PIC 2中的光波导WG2-1中。具体地，每个第一光波导可包括第一光耦合部，并且每个第二光波导可包括第二光耦合部(图中未示出)，简单起见，可将例如光波导WG2-1和WG1-1的端部视为各自的光耦合部。例如，光波导WG2-1和WG1-1的光耦合部在垂直于转接板1210的上表面的方向上叠置且间隔预定距离(例如，小于600nm)，使得光波导WG2-1和WG1-1的光耦合部之间能够实现光的绝热耦合。当然，光芯片PIC1与光芯片PIC2之间也可以通过一个第一光波导进行光互连，例如，图12A中的光波导WG1-1和光波导WG1-2可以是一个第一光波导的不同部分。在存在多个第一光波导的情况下，不同的第一光波导可以实现不同光芯片之间的光互连。例如，一个第一光波导可以用于连接PIC 1和PIC 2，另一个第一光波导可以用于连接PIC 1和PIC 3或者PIC 3和PIC4。
图13和图14分别示出了本公开的实施例的光芯片封装结构1200中的光耦合部的示意侧视图和俯视图、以及对应的光模场的图。
如图13所示，光芯片PIC 1中的光波导WG2-1的耦合部与转接板中的光波导WG1-1的耦合部上下叠置且间隔预定距离H。
另外，为了实现高耦合效率，如图14所示，光芯片PIC 1中的光波导WG2-1的耦合部与转接板中的光波导WG1-1的耦合部可以具有锥形形状。理想情况下，光芯片PIC 1中的光波导WG2-1的耦合部与转接板中的光波导WG1-1的耦合部(即如图14所示的两个锥形)在横向和纵向上均应对齐，从而获得最大的耦合效率。然而，在现实制造中，由于工艺的限制，无法做到使光芯片PIC 1中的光波导WG2-1的耦合部与转接 板中的光波导WG1-1的耦合部在横向和纵向上均完全对齐，通常情况下，会存在如图14所示的横向错位LM和纵向错位TM。
以光芯片的衬底为SOI、转接板上的光波导为SiN为例，对光芯片和转接板之间的耦合效率影响较大的主要有如下参数：转接板中的光波导WG1-1的宽度W4、光波导WG2-1的耦合部与光波导WG1-1的耦合部的长度L、上述距离H、以及光波导WG1-1的厚度tSiN。
对于转接板中的光波导WG1-1的宽度W4，在保证光波导WG1-1为单模波导的基础上，W4越宽越耦合效果越好。优选地，可以选择W4<1μm，因为大于1μm容易变成多模波导。
对于耦合部的长度L，L越长，耦合效果越好，图15是W4＝1μm、H＝200nm的情况下，不同L的耦合效率与横向错位的关系图，当L＝200μm时，当横向错位为1μm，耦合损耗可以控制在1dB以内，而当L＝1800μm时，横向错位1.5μm，耦合损耗也可以控制在1dB以内。
对于光波导WG2-1的耦合部与光波导WG1-1的耦合部之间的距离H，H越小耦合效果越好，但是H包括光芯片的SOI中埋氧层减薄之后的厚度加上转接板中的氮化硅波导上方覆盖的氧化硅的厚度之和，如果设置的H太小，则需要SOI中的埋氧层也较薄，受减薄工艺限制，会导致埋氧层厚度不均匀而影响耦合效率，因此，优选地，H＝100nm-600nm。图16是W4＝1μm、L＝200μm，tSiN＝200nm的情况下，不同H的耦合效率与横向错位的关系图。可见，H＝200nm左右耦合效果最佳，在大于200nm的情况下，间距越大，相同横向错位的情况下耦合效率下降越多。
对于光波导WG1-1的厚度tSiN，tSiN厚度过小会导致光波导的厚度不均匀，厚度过大会因为内部应力导致裂开，因此，优选地，tSiN＝100nm-300nm。图17是W4＝1μm、L＝200μm，H＝200nm的情况下，不同tSiN的耦合效率与横向错位的关系图。从图中可知，tSiN＝200nm时，耦合效果最佳。
除了如上所述的锥形耦合部，在一些实施例中，光芯片的光波导的耦合部和转接板的光波导的耦合部可以具有由两个不同尺寸的锥形形状级联形成的形状。图18和图19分别示出了这种具有由两个不同尺寸的锥形形状级联形成的形状的耦合部的示意图以及对应的光模场的图。
如图19所示，与先前的锥形结构相比，光芯片的光波导的耦合部和转接板的光波导的耦合部都多了一个长度为L_taper锥形过渡结构，即，光耦合部由单一的锥形结构演变为两级锥形结构级联形成的结构。之所以添加上述锥形过渡结构，是因为由硅波导WG2-1和氮化硅波导WG1-1存在一个在硅波导WG2-1为约700nm、氮化硅波导WG1-1为约300nm长度处的重合点，例如在图19所示的虚线位置处，介电系数neff_Si≈neff_SiN，在该重合点处两者能够快速耦合，并且，该结构耦合长度L_trans可以比先前的锥形结构大大减小，可以为约10μm就能完成光耦合。并且，相同情况下，硅波导WG2-1和氮化硅波导WG1-1还可以允许更大角度上的纵向对准错位(先前的锥形结构需要两波导在平行方向具有很小的角度对准误差)和横向对准错位。
以上结合图12A-图19描述了根据本公开的光芯片封装结构的实施例，在该实施例中，通过控制光芯片中的光波导与转接板上光波导之间的间距，并改变上述两波导的耦合部的结构，多个光芯片可通过绝热耦合与转接板进行光连接，进而通过转接板上的光波导网络实现多个光芯片之间的光互连。相比使用光纤阵列等外接互连方式，这种使用绝热耦合的技术对多个光芯片进行光互连的封装结构能够大大压缩封装结构的体积。
可选地，如上所述的封装结构中还可以布置电芯片，从而形成能够实现电操作(如逻辑计算、存储等)功能的光芯片封装结构。
图20和图21分别示出了本公开的实施例的包含电芯片的光芯片封装结构2000的横截面图和俯视图。
如图20所示，除了包括与图12A-12B类似的转接板1210和光芯片PIC 1和PIC 2之外，封装结构2000还包括布置在多个光芯片中的多个第一光芯片上的多个电芯片，例如，分别布置在PIC 1和PIC 2上的EIC 1和EIC 2。或者，如图21所示，分别布置在PIC 1、PIC 2、PIC 5、PIC 6上的EIC 1、EIC 2、EIC 5、EIC 6。需要说明的是，可以将图20看作从图21所示的封装结构2000的贯穿EIC 1和EIC 2的位置处切开的剖面图。在图21中，PIC 1、PIC 2、PIC 5、PIC 6已经被对应的EIC 1、EIC 2、EIC 5、EIC 6分别覆盖，因此没有示出。此外，如图21所示，不必为每个PIC设置对应的EIC，例如，PIC 3和PIC 4上方根据需要可以不布置 EIC。
具体地，每个第一光芯片(例如如图20所示的PIC 1和PIC 2)的上表面上可以具有一个或多个第一电连接件，并且每个电芯片(例如如图20所示的EIC 1和EIC 2)的下表面上可以具有一个或多个第二电连接件，并且一个或多个第一电连接件分别与一个或多个第二电连接件电连接，从而实现PIC和EIC的连接。
图22和23示出了本公开的实施例的光芯片封装结构中的光芯片和电芯片的横截面图。
如图22中的(a)所示，PIC的上表面具有多个第一电连接件C1，并且EIC的下表面上具有多个第二电连接件C2，PIC和EIC通过第一电连接件C1和第二电连接件C2直接键合。
在一些示例中，上述第一光芯片(即其上布置了EIC的PIC)还包括贯穿其中的一个或多个第二导电通孔，例如，如图22中的(a)所示的TDV，通过这些TDV可以实现EIC和转接板之间的电连接，例如，将所示的TDV连接到如前所示的转接板的导电结构中，这在将稍后针对图24-25的介绍中详细描述。
图22中的(a)示出了一个PIC上布置单个EIC的示意图。在其它实施例中，可以在一个PIC上布置多个EIC。例如，如图22中的(b)所示，可以在PIC上布置模拟电芯片A-EIC，同时布置数字电芯片D-EIC。根据需要，也可以在一个PIC布置多个模拟电芯片A-EIC，或者在一个PIC布置多个数字电芯片D-EIC，或者在一个PIC布置多个模拟电芯片A-EIC和多个数字电芯片D-EIC。在同一个PIC上布置了多个EIC的情况下，每个EIC都通过如上所述的TDV连接到转接板的导电结构上，以实现二者之间的电连接。
光芯片PIC和电芯片EIC之间除了可以通过如上所述的直接键合的方法连接，还可以采用倒装焊(flip-chip)的方式进行贴合。图23示出了采用倒装焊(flip-chip)的方式进行贴合的光芯片PIC和电芯片EIC。在这个例子中，不是使用直接键合技术，而是使用传统的倒装芯片工艺，通过铜柱连接EIC和PIC，并在EIC和PIC之间使用底部填充物进行固化。图23的(a)示出了一个PIC上仅倒装一个EIC的示例，并且(b) 示出了一个PIC上倒装一个D-EIC和一个A-EIC的示例。类似的，可以在一个PIC倒装多个模拟电芯片A-EIC，可以在一个PIC倒装多个数字电芯片D-EIC，或者在一个PIC倒装多个模拟电芯片A-EIC和多个数字电芯片D-EIC。在同一个PIC上倒装了多个EIC的情况下，每个EIC都通过如上所述的TDV连接到转接板的导电结构上，以实现二者之间的电连接。
为了更清楚地公开本公开的光芯片封装结构，图24-25示出了本公开的实施例的光芯片封装结构的横截面图。然而需要注意的是，为了进一步呈现细节，图24-25中仅示出了一个PIC和一个EIC。具体地，图24示出了采用如图1所示的转接板的光芯片封装结构的横截面图。图25示出了采用如图4所示的转接板的光芯片封装结构的横截面图。
如图24所示，在采用如图1所示的转接板的情况下，整个封装结构从下往上可以分为三层，即转接板1210所在的层、PIC所在的层以及EIC所在的层。例如，在图24中，用两条平行的虚线来将整个封装结构划分为三层，EIC和PIC之间的虚线限定的是EIC和PIC的连接界面IF1，并且PIC和转接板1210之间的虚线限定的是PIC和转接板1210之间的连接界面IF2。应当理解的是，上述划分方式仅仅是为了更清楚地描述本发明，而不是为了将本发明限制为如上所述的三层结构。
假设图24示出的光芯片PIC是如图20中所示的PIC 1，则布置在其上的EIC则对应于如图20所示的EIC 1。在这种情况下，可以看到光芯片PIC中的光波导WG2-1位于光芯片PIC的下表面附近，并且被透明介电层(例如，埋置氧化硅层)覆盖。转接板1210中的光波导WG1-1位于转接板1210的上表面并且也被包覆层(例如，氧化硅层)覆盖。光芯片PIC中具有贯穿其中的导电通孔TDV，并且光芯片PIC中的该导电通孔TDV与转接板1210中的导电结构CC相互电连接。例如，在图24中的转接板1210是类似于如图1所示的转接板100的情况下，光波导WG1-1可对应于如图1所示的转接板100中的光波导102-1，并且导电结构CC可以对应于如图1所示的转接板100中的第一导电结构102-3。
类似的，如图25所示，在采用如图4所示的转接板的情况下，整个封装结构从下往上也可以分为三层，即转接板1210所在的层、PIC所 在的层以及EIC所在的层。例如，在图25中，同样用两条平行的虚线来将整个封装结构划分为三层，EIC和PIC之间的虚线限定的是EIC和PIC的连接界面IF1，并且PIC和转接板1210之间的虚线限定的是PIC和转接板1210之间的连接界面IF2。同样应当理解的是，上述划分方式仅仅是为了更清楚地描述本发明，而不是为了将本发明限制为如上所述的三层结构。
同样地，假设图25示出的光芯片PIC是如图20中所示的PIC 1，则布置在其上的EIC则对应于如图20所示的EIC 1。在这种情况下，可以看到光芯片PIC中的光波导WG2-1位于光芯片PIC的下表面附近，并且被介电层(例如，氧化硅层)覆盖。转接板1210中的光波导WG1-1位于转接板1210的上表面并且也被包覆层(例如，氧化硅层)覆盖。光芯片PIC中具有贯穿其中的导电通孔TDV，并且光芯片PIC中的该导电通孔TDV与转接板1210中的导电结构CC相互电连接。例如，在图25中的转接板1210是类似于如图4所示的转接板400的情况下，光波导WG1-1可对应于如图4所示的转接板400中的光波导304-1，并且导电结构CC可以对应于如图4所示的转接板400中的第三导电结构304-3。
在如图12A-图25描述的示例中，所示出的多个光芯片都是分割光子晶圆后所得的分离的光芯片，并且被贴合在转接板的上表面上的不同位置处，并且彼此间隔开(如图12A-12B以及图20-21所示)，因此在将光芯片贴合到转接板的上之后，为了进一步封装以增强结构的稳定性和强度，需要在转接板的上表面上不同光芯片和不同的电芯片之间的间隙中填充注塑材料。
可选地，在填充注塑材料之前，可以首先在光芯片和转接板的连接界面上布置用于阻挡所述转接板中的光向外传输的介电层，然后在该介电层上进行注塑以形成注塑材料层。之所以在转接板和光芯片之间布置这样的介电层，是由于转接板中的波导(例如，如图24或25所示的WG1-1)上方覆盖的介电层(例如，氧化硅层)很薄，光信号在不同光芯片之间的波导中传输，很薄的氧化硅层会导致光在传输过程中外溢而导致光损耗。因此，在注塑之前可以先在转接板上未贴合光芯片的间隙中制备一介电层，优选该介电层与波导上方覆盖的介电层的材料及制备工艺相同，例如，其 材料也可为氧化硅，从而保证不同光芯片之间的波导中传输的光不向外泄露。可选地，例如，可以制备厚度约为数微米的介电层。
图24和25所示的封装结构均示出了如上所述的注塑材料层和用于阻挡光的介电层。例如，图24或25中的注塑材料层MLD和介电层SHD。介电层SHD位于转接板和注塑材料层MLD之间，并且相比光波导WG1-1上方的薄氧化硅层具有更大的厚度，从而保证能将不同光芯片之间传输的光最大程度地限制在转接板内。
应当理解的是，虽然在图24和25中分别示出了采用如图1和4所示的转接板的光芯片封装结构的示例，这仅仅是示例性的，并且这并不意味着本公开所述的光芯片封装结构只能采用如图1和4所示的转接板。例如，本公开所述的光芯片封装结构也可以采用如图2所示的具有三维波导网络的转接板200，并且在采用如图2所示的具有三维波导网络的转接板200的情况下，如上所述的转接板中的光波导(例如，光波导WG1-1)可以对应于如图2所示的转接板200中的三维波导网络201-2及覆盖该三维波导网络的光输入输出口的耦合光波导202-1。另外，也可以采用基于本公开讨论的各种转接板的各种变型或修改后的转接板，在此不再一一列举。
以上结合附图12A-图25描述的是转接板上贴合的多个光芯片作为分割光子晶圆后所得的分离的光芯片的情形。需要说明的是，转接板上贴合的多个光芯片也可以是同一个光子晶圆中未分割的多个光芯片。
图26-27示出了转接板上贴合的多个光芯片位于同一光子晶圆的情况下的光芯片封装结构2600的示意图。
如图26所示，光芯片封装结构2600包括转接板1210以及布置在转接板1210上的多个光芯片(PIC)。例如，由于图26示出的是从特定位置切割开的剖面图，在图26中仅仅可以看到两个光芯片PIC 1和PIC 2。但是实际上，如图27的俯视图所示，光芯片封装结构2600可以包括PIC 1-PIC 6六个光芯片。应当理解的是，上述六个光芯片仅仅是示例性的而非限制，在实际应用中，光芯片封装结构2600可以包括更多的光芯片。
如图26所示，转接板2600包括嵌入其中的多个第一光波导，例如如图26所示的光波导WG1-1和光波导WG1-2。光波导WG1-1和光波导WG1-2可以是如前所述的转接板中的光波导，例如图1中的光波导102- 1，图2中的202-1和202-2，或图4中的304-1。此外，光波导WG1-1和光波导WG1-2的材料可以是如前所述的氮化硅。
光芯片PIC 1和PIC 2中的每一个包括嵌入其中的一个或多个第二光波导(为了简化说明，图26中针对每个PIC仅示出单个光波导)，即光波导WG2-1和光波导WG2-2。在一些示例中，光波导WG2-1和光波导WG2-2的材料可以为硅。如图27所示，包括多个光芯片(PIC 1，…,PIC 6)的光子晶圆PWF贴合到转接板1210的上表面上，并且多个光芯片(PIC 1，…,PIC 6)位于转接板1210上的不同位置处并且彼此间隔。
如图26所示的光芯片PIC 1和PIC 2、或者如图27所示的多个光芯片(PIC 1，…,PIC 6)中的任何两个之间都可通过多个转接板1210中的第一光波导进行光互连。例如，如图26中的带箭头的虚线所示，光可以从PIC 1出发，然后通过WG2-1耦合到转接板1210中的光波导WG1-1中，然后经由一系列光波导网络(未示出)传输到光波导WG1-2，进而再耦合到PIC 2中的光波导WG2-1中。具体地，每个第一光波导可包括第一光耦合部，并且每个第二光波导可包括第二光耦合部(图中未示出)，简单起见，可将例如光波导WG2-1和WG1-1的端部视为各自的光耦合部。例如，光波导WG2-1和WG1-1的光耦合部在垂直于转接板1210的上表面的方向上叠置且间隔预定距离(例如，小于600nm)，使得光波导WG2-1和WG1-1的光耦合部之间能够实现光的绝热耦合。
关于转接板中的第一光波导的光耦合部以及光芯片中的第二光波导的光耦合部的设计请参照图13至图19及其描述，适用于分离光芯片情形的光波导的光耦合部的设计同样适用于未分割的光子晶圆的情形，除非另有说明或明显不适合。例如，转接板中的第一光波导(例如，WG1-1或WG1-2)的光耦合部以及光芯片中的第二光波导(例如，WG2-1或WG2-2)的光耦合部可以具有如图14所示的锥形，也可以是如图19所示的由两个不同尺寸的锥形形状级联形成的形状。
需要说明的是，为了与图12A中的光芯片封装结构1200进行区分，图26所示的光芯片封装结构2600中的PIC 1和PIC 2之间的间隙被示为未被阴影线填充，由此表示PIC 1和PIC 2位于同一个未切割的晶圆中，而不是如图12A所示的PIC 1和PIC 2之间由注塑材料填充。
类似于采用分离光芯片的情形，在采用未分割的光子晶圆的情况下，也可以在光子晶圆中的特定光芯片或全部光芯片上相应地布置电芯片。
图28-29示出了在采用未分割的光子晶圆的情况下同时布置电芯片的光芯片封装结构2600的示意图。
如图28所示，除了包括与图26-27类似的转接板1210和包括光芯片PIC 1和PIC 2的光子晶圆PWF之外，封装结构2800还包括布置在多个光芯片中的多个第一光芯片(例如，PIC 1和PIC 2)上的多个电芯片，例如，分别布置在PIC 1和PIC 2上的EIC 1和EIC 2。或者，如图29A所示，封装结构2800可包括分别布置在PIC 1、PIC 2、PIC 5、PIC 6上的EIC 1、EIC 2、EIC 5、EIC 6。需要说明的是，可以将图28看作从图29A所示的封装结构2000的贯穿EIC 1和EIC 2的位置处切开的剖面图。在图29A中，PIC 1、PIC 2、PIC 5、PIC 6已经被对应的EIC 1、EIC 2、EIC 5、EIC 6分别覆盖，因此没有示出。此外，如图29A所示，不必为每个PIC设置对应的EIC，例如，PIC 3和PIC 4上方根据需要可以不布置EIC。需要说明的是，在这里，PIC 3和PIC 4上方不布置EIC并不是意味着PIC 3和PIC 4上方不被电子晶圆覆盖，相反地，可以理解为覆盖在PIC 3和PIC 4上方的电子晶圆的对应位置处是不具有具体结构的“伪芯片(dummy chip)”，而不是如EIC 1、EIC 2、EIC 5、EIC 6等指代的具有具体结构并且能够执行特定功能的晶片或芯片。
或者，在一些示例中，可以在每个PIC上方都布置EIC。例如，图29B示出了每个光芯片PIC上都布置EIC(如图所示的EIC 1-EIC 6)的示意图。在这种情况下，例如，全部光芯片上的对应的电芯片可以是同一个电子晶圆中未分割的多个电芯片，并且多个光芯片可以具有相同的结构，并且多个电芯片(例如，如图所示的EIC 1-EIC 6)也可以具有相同的结构，使得上下叠置的每个PIC-EIC对都形成相同的PIC-EIC混合芯片。在这种情况下，多个第一光芯片等同于所有光芯片。
需要注意的是，在采用未分割的光子晶圆的情况下，如上所述的多个第一光芯片上的多个电芯片(例如，图29B中的EIC 1、EIC 2、EIC3、EIC4、EIC 5、EIC 6)为同一个电子晶圆EWF中未分割的多个电芯片，并且在这中情况下，如如图29A-图29B所示的光子晶圆PWF与电子晶圆 EWF采用直接键合的方式连接在一起，然后共同布置在转接板1210上。在这种情况下，类似于图23所示的倒装焊的方式不再适用于光子晶圆和电子晶圆的连接。
另外，需要说明的是，为了与为了图20中的光芯片封装结构2000进行区分，图28所示的光芯片封装结构2800中的PIC 1和PIC 2之间以及EIC 1和EIC 2之间的间隙被示为未被阴影线填充，由此表示PIC 1和PIC 2位于同一个光子晶圆中，并且EIC 1和EIC 2位于同一个电子晶圆中，而不是如图20所示的PIC 1和PIC 2之间以及EIC 1和EIC 2之间的间隙由注塑材料填充。
同样地，对于图28-29所示的实施例，关于转接板中的第一光波导的光耦合部以及光芯片中的第二光波导的光耦合部的设计也可参照图13至图19及其描述，适用于分离光芯片情形的光波导的光耦合部的设计同样适用于未分割的光子晶圆的情形，除非另有说明或明显不适合。例如，如图28所示的转接板中的第一光波导(例如，WG1-1或WG1-2)的光耦合部以及光芯片中的第二光波导(例如，WG2-1或WG2-2)的光耦合部可以具有如图14所示的锥形，也可以是如图19所示的由两个不同尺寸的锥形形状级联形成的形状，在此不再赘述。
另外，需要说明的是，在采用未分割的光子晶圆的情况下，如图26-29所示的光芯片封装结构同样可以采用先前关于图1和4所述的转接板100和400，也可以采用如图2所示的具有三维波导网络的转接板200，并且在采用如图2所示的具有三维波导网络的转接板200的情况下，如26或28所述的转接板中的光波导(例如，光波导WG1-1)可以对应于如图2所示的转接板200中的三维波导网络201-2及覆盖该三维波导网络的光输入输出口的耦合光波导202-1。另外，也可以采用基于本公开讨论的各种转接板的各种变型或修改后的转接板，在此不再一一列举。
如上描述了本公开所涉及的光芯片封装的各种实施例。综合来看，对于图12A-12B以及图20-21所描述的光芯片封装结构，其采用的是分离的光芯片，光芯片的波导和转接板的波导以绝热方式耦合，这种封装结构中的芯片布置的自由度极高，大大压缩了封装结构的尺寸。而对于图26-29所示的光芯片封装结构，其采用的是同一光子晶圆上未分离的光芯片， 虽然在布设的灵活性方面不如分离的光芯片的方案，但是由于使用了晶圆到玻璃转接板的直接键合工艺，工艺简单，对准精度要更高，因此光芯片和转接板的光波导之间的耦合效率也更高。本领域技术人员可以根据实际需要选择合适的实施方式，或者将各个实施方式相互组合，并且该组合方式同样落入本公开的保护范围内。
通过采用如上所述的各种光芯片封装结构，可以实现各种计算加速器，例如用于实现神经网络中的矩阵乘法等计算。图30示出了本公开的实施例的计算加速器3000的示意图。图31A示出了本公开的实施例的另一计算加速器3100A的示意图。图31B示出了本公开的实施例的又一计算加速器3100B的示意图。
图30所示的计算加速器3000可以是采用如图12A-12B或如图20-21所示的具有分离的光芯片封装结构实现的。例如，如图30所示，计算加速器3000可以包括一个或多个光源LS、一个或多个计算单元CL以及一个或多个存储单元MO。清楚起见，使用不同的填充图案来区分不同的功能单元，例如，纯白色填充的单元(如图所示的方块)表示存储单元MO，网格填充的单元表示计算单元CL，并且散点填充的单元表示光源LS。
计算加速器3000中的部分单元可以实现在如前关于图12A-12B和/或关于图20-21所示的光芯片封装中。例如，一个或多个计算单元CL被配置为执行计算功能，其可以由如前关于图12A-12B所述的光芯片封装结构1200中的光芯片实现。例如，可以用光芯片中的马赫曾德尔MZI干涉仪等实现矩阵乘法运算。或者，一个或多个计算单元CL可以由如前关于图20-21所述的光芯片封装结构1200中电芯片实现，例如，光芯片封装结构1200中的光芯片主要执行通信功能，电芯片执行计算功能；或者，一个或多个计算单元CL可以由如前关于图20-21所述的光芯片封装结构1200中的光芯片和电芯片共同实现，例如，光芯片封装结构1200中的光芯片同时执行通信功能和部分计算功能，电芯片执行另外的计算功能。一个或多个存储单元MO被配置为执行存储功能，并且可以由如前关于图20-21所述的光芯片封装结构1200中的电芯片实现。
此外，优选地，在采用如前关于图12A-12B和/或关于图20-21所示的光芯片封装实现计算加速器3000的情况下，一个或多个光源LS可 以被集成到所述芯片封装结构中。例如，一个或多个光源LS可以以类似于如前所述的光芯片封装结构1200或2000中的PIC 1或PIC 2的方式贴合在转接板1210的第一表面上，并且被配置为通过转接板中的波导WG向计算加速器3000提供光波，更确切地，向计算加速器3000中的各个光芯片提供光波。
例如，可以用类似于光芯片和转接板之间绝热耦合的方法，将光源LS中的光也绝热耦合到转接板中的相应光波导中，从而避免通过其他中间链路(例如，光纤等)耦合光所需的额外接口，这种光源布置方法也有助于进一步压缩计算加速器的体积。
可选地，计算加速器3000还可以包括一个或多个边缘光耦合器，即，如图30所示的位于正方形的四周的边缘光耦合器CP，其被配置为将计算加速器与其它装置进行光互连。例如，如果光源LS不是以如上所述的方法贴合在转接板上，而是作为外接光源，则可以使用计算加速器3000中的边缘光耦合器CP来连接光源。
图30中示出计算加速器中的转接板1210可以是如前所述的各种类型的转接板。例如，其可以是如图1-2所述的转接板100和200，也可以是如图4所述的转接板400。另外，也可以采用基于本公开讨论的各种转接板的各种变型或修改后的转接板，在此不再一一列举。
此外，还需要说明书的是，虽然在图30中，计算加速器被示为实施在同一个光芯片封装结构的不同芯片中，这仅仅是示意性的。在实际应用中，可以通过如上所述的边缘光耦合器CP将多个不同的光芯片封装结构进行互连，并且将各种计算单元、存储单元或光源实施或布置在多个光芯片封装结构中，从而形成大型或超大型的计算加速器。
相比图30所示的计算加速器3000，图31A所示的计算加速器3100A可以是采用如图26-29B所示的光子晶圆级封装结构实现的。例如，如图31A所示，计算加速器3100A可以包括一个或多个光源LS、一个或多个计算单元CL以及一个或多个存储单元MO。清楚起见，使用不同的填充图案来区分不同的功能单元，例如，纯白色填充的单元(如图所示的方块)表示存储单元MO，网格填充的单元表示计算单元CL。
计算加速器3100A中的部分单元可以实现在如前关于图26-29B所 示的光芯片封装结构中。例如，一个或多个计算单元CL被配置为执行计算功能，其可以由如前关于图26-27所述的光芯片封装结构2600中的光芯片实现。例如，可以用光芯片中的马赫曾德尔MZI干涉仪等实现矩阵乘法运算。或者，一个或多个计算单元或存储单元可以由如前关于图28-29A所述的光芯片封装结构2800中光芯片或电芯片实现，例如，光芯片封装结构2800中的光芯片主要执行通信功能，电芯片执行计算及存储功能；或者，一个或多个计算单元CL可以由如前关于图28-29A所述的光芯片封装结构2800中的光芯片和电芯片共同实现，例如，光芯片封装结构2800中的光芯片同时执行通信功能和部分计算及存储功能，电芯片执行另外的计算及存储功能。
与图30不同的是，由于图31A采用的是使用光子晶圆的封装结构在如图30所示的方形区域之外，还存在冗余的光芯片，在将光子晶圆键合到转接板之前，需要切割去除冗余的光芯片。
可选地，还可以采用如图29B所示的封装结构来实现上述计算单元和存储单元。例如，当采用如图29B所示的封装结构2900来实现计算加速器中的计算单元和存储单元时，由于封装结构2900中的每个EIC都是相同的，并且每个PIC也是相同的，可以使用每个PIC及对应的EIC(例如PIC 1和EIC 1)来共同实现每个计算单元和对应的存储单元，并将其视为计算-存储单元。
图31B示出了将每个计算单元和对应的存储单元实现为对应的计算-存储单元的计算加速器3100B的示例。例如，可以由如图29B所示的光芯片封装结构2900中的每个光芯片及对应的电芯片实现每个计算单元和对应的存储单元，从而将每个计算单元和对应的存储单元视为计算-存储单元CL-MO。
在这种情况下，如图31B所示，可以将计算单元和对应的存储单元的组合视为同一个计算-存储单元CL-MO。为了便于理解，将图31B中的每个计算-存储单元CL-MO都示出为用棋盘格图案填充，从而表示每个计算-存储单元CL-MO可以具有相同的硬件资源，即具有相同的存储资源、计算资源、通信资源等。例如，在由如前关于图29B所述的光芯片封装结构2900实现如图所示的多个计算-存储单元CL-MO的情况下，可由光芯 片封装结构2900中的光芯片主要执行通信功能，对应的电芯片执行计算及存储功能；或者，可由光芯片同时执行通信功能和部分计算及存储功能，对应的电芯片执行另外的计算及存储功能。
此外，应当理解的是，不论是如上所述的计算单元、存储单元还是计算-存储单元，都旨在描述计算加速器中的功能单元，而不是意图将光芯片封装中的各个光芯片、电芯片或光芯片和电芯片的组合限定为仅用于计算、仅用于存储、或仅用于计算-存储。例如，光芯片封装中的各个光芯片、电芯片或光芯片和电芯片的组合还可以用于实现除了计算、存储、或计算-存储之外的其它功能，例如数据传输等。
此外，需要说明的是，计算加速器3100A或3100B中由于是电子晶圆到光子晶圆的直接键合，光源LS(例如，激光芯片)不能直接键合到转接板上，需要通过光纤阵列或其他导光结构把光耦合到计算加速器中，并且光源LS被配置为通过转接板中的波导WG向计算加速器3100A或3100B提供光波，更确切地，向计算加速器3100A或3100B中的各个光芯片提供光波。
另外，计算加速器3100A或3100B还可以包括一个或多个边缘光耦合器，即，如图31A或图31B所示的位于正方形的四周的边缘光耦合器CP，其被配置为将计算加速器与其它装置进行光互连。例如，可以使用计算加速器3100A或3100B中的边缘光耦合器CP来连接光源LS。
图31A或图31B中示出计算加速器中的转接板1210可以是如前所述的各种类型的转接板。例如，其可以是如图1-2所述的转接板100和200，也可以是如图4所述的转接板400。另外，也可以采用基于本公开讨论的各种转接板的各种变型或修改后的转接板，在此不再一一列举。
此外，还需要说明的是，虽然在图31A或图31B中，计算加速器被示为实施在同一个光芯片封装结构的不同芯片中，这仅仅是示意性的。在实际应用中，可以通过如上所述的边缘光耦合器CP将多个不同的光芯片封装结构进行互连，并且将各种计算单元、存储单元或光源实施或布置在多个光芯片封装结构中，从而形成大型或超大型的计算加速器。
可选的，如上关于图30-31所述的计算加速器还可以包括叠置在所述的光芯片封装结构中的光芯片上的多个高带宽内存(HBM)芯片，其被 配置为执行内存计算功能。
以上描述了本公开的各种实施例中的光芯片封装结构和使用各种光芯片封装结构实现的计算加速器。综合来看，对于图12A-12B以及图20-21所描述的光芯片封装结构，由于其采用的是分离的光芯片，光芯片的波导和转接板的波导以绝热方式耦合，这种封装结构中的芯片布置的自由度极高，大大压缩了封装结构的尺寸。并且通过这种封装结构实施的计算加速器可以进一步将光源集成在光芯片封装结构的内部，有利于进一步压缩产品体积。
相比之下，对于图26-29B所示的光芯片封装结构，其采用的是同一光子晶圆上未分离的光芯片，虽然在布设的灵活性方面不如分离的光芯片的方案，但是由于使用了晶圆到玻璃转接板的直接键合工艺，工艺更加简单，对准精度也更高，因此光芯片和转接板的光波导之间的耦合效率也更高。本领域技术人员可以根据实际需要选择合适的实施方式，或者将各个实施方式相互组合，并且该组合方式同样落入本公开的保护范围内。
以下将结合附图32-36来描述如上所述的各种光芯片封装结构的具体制造方法。图32-36示出了本公开的实施例的光芯片封装结构的制造方法的流程图。
需要说明的是，以下所述的制造方法中所提及的类似于转接板、光芯片、电芯片等的结构及其特征均类似于如上关于各种光芯片封装结构的实施例描述的各种结构或特征。为了简化说明，在一些情况下会省略对这些结构或特征的重复描述，在这种情况下，不应由此狭义地解释如下所述的制造方法中涉及的各种结构或特征。
此外，在以下关于光芯片封装结构的制造方法的描述中，为了避免重复描述，会在某些流程中引用其他附图中示出的流程步骤，在这种情况下，不应由此狭义地解释如下所述的制造方法中涉及的各种步骤。
图32示出了对应于如图12A-12B所示的光芯片封装结构1200的制造方法的3200流程图。
如图32所示，方法3200包括：提供一转接板(S3210)以及将多个光芯片贴合到转接板的上表面上的不同位置处(S3220)。例如，转接板可以是如图12A中的转接板1210，并且多个光芯片可以是如图12B所 示的PIC 1至PIC 6。
例如，转接板可以包括嵌入其中的一个或多个第一光波导(如图12A所示的WG1-1，WG1-2)，并且每个第一光波导包括第一光耦合部。每个光芯片可以包括嵌入其中的一个或多个第二光波导(如图12A所示的WG2-1，WG2-2)，每个所述第二光波导包括第二光耦合部。
例如，上述第一光耦合部和第二光耦合部分别为如前关于图14所示的锥形形状。可选地，所述第一光耦合部和所述第二光耦合部也可以分别具有如上关于图19所示由两个不同尺寸的锥形形状级联形成的形状。
如前关于图13所述，第一光耦合部与第二光耦合部在垂直于转接板的上表面的方向上叠置且间隔预定距离(例如，小于或等于600nm)，使得第一光耦合部与所述第二光耦合部实现光的绝热耦合，并且多个光芯片通过多个所述第一光波导进行光互连。
图33-35示出了对应于如图20-21所示的光芯片封装结构2000的制造方法的流程图。
如图33所示，制造方法3300包括：提供一转接板(S3310)、在多个光芯片中的第一光芯片上布置电芯片，使得第一光芯片和其上的电芯片形成电子-光子混合芯片(S3320)，以及将多个光芯片贴合到转接板的上表面上的不同位置处(S3330)。
与图32所示的制造方法相比，图33所示的制造方法3300多了形成电子-光子混合芯片的步骤S3320。需要说明的是，这里的术语“电子-光子混合芯片”并不意味着要采用除了如前所述的光芯片和电芯片之外的其它芯片，而是可以对应于图20所示的PIC 1和EIC 1相互连接形成的整体结构，或者PIC 1和EIC 1相互连接形成的整体结构。更贴切的，术语“电子-光子混合芯片”可以对应于如图关于22-23所示的各个芯片结构。
例如，如图22中的(a)所示，PIC与布置在其上的EIC一起可称为电子-光子混合芯片或电子-光子混合小芯片(chiplet)。如图22中的(a)所示，PIC的上表面具有多个第一电连接件C1，并且EIC的下表面上具有多个第二电连接件C2，PIC和EIC通过第一电连接件C1和第二电连接件C2直接键合。
此外，电子-光子混合芯片也可以是如图22中的(b)所示的包含 一个PIC和两个EIC(D-EIC和A-EIC)的整体结构，D-EIC、A-EIC和PIC之间也通过第一电连接件C1和第二电连接件C2直接键合。
同样地，如图23所示的利用倒装焊的连接方式键合的EIC和PIC的整体结构也可以视为如上所述的电子-光子混合芯片，在此不再赘述。
图34和35分别示出了两种在所述多个光芯片中的第一光芯片上布置电芯片以形成电子-光子混合芯片的两种不同方法。图34和35中的流程步骤可分别视为图33中步骤S3320的细分步骤。
如图34所示，在所述多个光芯片中的第一光芯片上布置电芯片包括：制备光子晶圆和电子晶圆(S3410)，将所述电子晶圆直接键合到所述光子晶圆(3420)，去除所述光子晶圆的衬底(S3430)以及将所述电子-光子混合晶圆切割成多个电子-光子混合芯片(S3440)。
在一些示例中，在步骤S3410中制备的光子晶圆可类似于关于图29A所述的光子晶圆PWF，其包括多个光芯片PIC 1-PIC 6,并且多个光芯片PIC 1-PIC 6中包含多个第一光芯片，用于在其上布置对应的电芯片。类似的，在步骤S3410中制备的电子晶圆可类似于关于图29A所述的电子晶圆EWF，其中包括多个电芯片(例如，EIC 1，EIC 2，EIC 5，EIC 6)。
在一些示例中，例如，通过将所述多个第一光芯片与所述多个电芯片键合(例如，直接键合)可以得到电子-光子混合晶圆，然后在步骤S3440中将电子-光子混合晶圆切割成多个电子-光子混合芯片。
需要说明的是，以上虽然结合图29A说明了光子晶圆和电子晶圆的具体结构，但这仅仅是为了方便描述，实际上，图29A示出了PWF和EWF是无需分割成单独的电子-光子混合芯片的，他们二者直接键合后以整体的方式布置在转接板之上。然而，需要提及的是，虽然不需要将键合后的PWF和EWF切割成独立的电子-光子混合芯片，但是需要切除边缘的冗余芯片以便于封装，例如，切割成如图31A或31B所示的内部的方形形状。
图35示出了另一种形成电子-光子混合芯片的方法。如图35所示，在多个光芯片中的第一光芯片上布置电芯片具体可以包括：制备光子晶圆和电子晶圆(S3510)，将所述电子晶圆切割成所述多个电芯片(S3520)， 将所述多个电芯片中的一个或多个直接键合或者倒装焊(flipchip)到所述光子晶圆中的第一光芯片上，以得到电子-光子混合晶圆(S3530)，在所述光子晶圆上未被所述电子芯片占据的间隙中填充注塑材料(S3540)，去除所述光子晶圆的衬底(S3550)，以及将所述电子-光子混合晶圆切割成所述电子-光子混合芯片(S3560)。
类似地，在步骤S3510中制备的光子晶圆可类似于关于图29A所述的光子晶圆PWF，其包括多个光芯片PIC 1-PIC 6,并且多个光芯片PIC1-PIC 6中包含多个第一光芯片，用于在其上布置对应的电芯片。类似的，在步骤S3510中制备的电子晶圆可类似于关于图29A所述的电子晶圆EWF，其中包括多个电芯片(例如，EIC 1，EIC 2，EIC 5，EIC 6)。
与方法3400不同的是，在方法3500中，包括多个电芯片的电子晶圆不是整体键合到光子晶圆上，而是首先在步骤S3520中将其切割成多个分离的电芯片，然后在步骤S3530中将切割所得的各个电芯片直接键合或者倒装焊(flip-chip)到光子晶圆中的第一光芯片上，以得到电子-光子混合晶圆。
由于各个电芯片是分离的电芯片，而不是如方法3400中所述位于同一电子晶圆上，还需要在第一光芯片上布置了相应的电芯片之后，在所述光子晶圆上未被所述电子芯片占据的间隙中填充注塑材料，从而增强光子晶圆的机械强度和稳定性。
同样需要说明的是，以上虽然结合图29A说明了光子晶圆和电子晶圆的具体结构，但这仅仅是为了方便描述，实际上，图29A示出了PWF和EWF是无需分割成单独的电子-光子混合芯片的，他们二者直接键合后以整体的方式布置在转接板之上。然而，需要提及的是，虽然不需要将键合后的PWF和EWF切割成独立的电子-光子混合芯片，但是需要切除边缘的冗余芯片以便于封装，例如，切割成如图31A或31B所示的内部的方形形状。
此外，上述方法3400或3500还可包括：在去除所述光子晶圆的衬底之后并且在将所述电子-光子混合晶圆切割成所述电子-光子混合芯片之前，减薄所述光子晶圆底面的埋置氧化层至预定的厚度(图中未示出)。在光子晶圆中已经制备了光波导的情况下，如上所述的减薄操作是为了使 得光芯片中的光波导底面的埋置氧化层的厚度减小，从而使光芯片中的光波导能够与转接板中的光波导尽可能地靠近，从而增大耦合效率。
可以通过如上所述的减薄操作使得光芯片中的光波导与转接板中的光波导之间的间距小于或等于600nm，如关于图13所述。
另外，上述方法3400或3500还可包括：在去除所述光子晶圆的衬底之后，减薄所述光子晶圆底面的埋置氧化层，并且在所述光子晶圆远离所述电芯片的表面上形成连接波导；以及在所述连接波导上覆盖电介质以包覆所述连接波导，所述连接波导与光芯片中的第二光波导的第二光耦合部、转接板中的第一光波导的第一光耦合部在光子晶圆的下表面的垂直方向上叠置且间隔开(图中未示出)，所述第一光波导、所述连接波导、所述第二连接波导通过光的绝热耦合进行光通信。通过如上方式向在光子晶圆中形成连接波导，然后在连接波导上覆盖电介质以包覆该连接波导。其目的同样是为了使光芯片中的光波导能够与转接板中的光波导尽中间增加一个连接波导，从而增大耦合效率。
在一些示例中，上述方法3400或3500还可包括：在制备所述光子晶圆之后，在所述光子晶圆中形成一个或多个第二导电孔；以及在去除所述光子晶圆的衬底之后，减薄所述光子晶圆底面的埋置氧化层至预定厚度，使所述一个或多个第二导电孔上下贯通以形成一个或多个第二导电通孔(图中未示出)。例如，如上所述的方法形成的第二导电通孔可以是如图22或23中所示的PIC上的TDV，其用于将电芯片EIC电连接到转接板。
例如，在一些示例中，将多个光芯片贴合到转接板的上表面上的不同位置处还包括：将所述一个或多个第二导电通孔与所述转接板中的一个或多个导电结构分别电连接。转接板中的一个或多个导电结构可以是如图1所示的转接板100中的第一导电结构102-3，也可以是如图2所示的转接板200中的第一导电结构202-3，或者是如图4所示的转接板400中的第三导电结构304-3。光芯片中一个或多个第二导电通孔与转接板中的一个或多个导电结构分别电连接的具体细节也可以参照图24或25中的TDV与导电结构CC的连接方式，在此不再赘述。
回到方法3300，在将多个光芯片贴合到转接板的上表面上的不同位置处之后，多个电子-光子混合芯片在转接板的上表面上相互间隔开。由 于此时不同的电子-光子混合芯片仍然存在间隙，需要通过在该间隙中填充注塑材料以增强封装的稳定性和机械强度。
然而，由于转接板中的波导(例如，如图24或25所示的WG1-1)上方覆盖的介电层(例如，氧化硅层)很薄，光信号在不同光芯片之间的波导中传输，很薄的氧化硅层会导致光在传输过程中外溢而导致光损耗。因此，在注塑之前可以先在转接板上未贴合光芯片的间隙中制备一介电层，用于阻挡转接板中的光向外传输，优选地，该介电层的材料与转接板中波导上方覆盖的介电层材料相同，且采用相同的工艺。
因此，方法3300还可包括：在光芯片之间的间隙中填充注塑材料之前，在转接板的上表面上且在所述多个电子-光子混合芯片之间的间隙中形成用于阻挡所述转接板中的光向外传输的介电层(图中未示出)。该介电层的材料也可为氧化硅，并且可以具有预定厚度，例如数微米，从而保证不同光芯片之间的波导中传输的光不向外泄露。
以上结合附图33-35描述了对应于图12A-12B以及图20-21所示的光芯片封装结构的制造方法，其中封装的多个光芯片和多个电芯片都是彼此分离的，即不在同一个晶圆上。以下将结合附图描述对应于图26-29所示的光芯片封装结构的制造方法，在图26-29所示的芯片封装结构中，多个光芯片或多个电芯片都位于同一个光子晶圆或同一个电子晶圆中。
图36所示的方法对应于图26-27所示的光芯片封装结构2600的制造方法。
如图36所示，方法3600包括：提供一转接板(S3610)，制备光子晶圆(S3620)，以及将光子晶圆直接键合到转接板的上表面上(S3630)。转接板可类似于前面所述的任一转接板，在此不再赘述。制备的光子晶圆中包括多个光芯片，并且光子晶圆是通过直接键合的方法连接到转接板上。
图37所示的方法对应于图28-29所示的光芯片封装结构2800的制造方法。
如图37所示，方法3700包括：提供一转接板(S3710)，制备光子晶圆和电子晶圆(S3720)，将电子晶圆直接键合到光子晶圆，使得多个第一光芯片与多个电芯片键合，以得到电子-光子混合晶圆(S3730)，以及将光子晶圆直接键合到转接板的上表面上(S3740)。同样地，转接 板可类似于前面所述的任一转接板。制备的光子晶圆中包括多个光芯片，制备的电子晶圆可包括多个电芯片，电子晶圆直接键合到光子晶圆使得光子晶圆中的特定光芯片(即，如前所述的第一光芯片)与多个电芯片键合，以得到电子-光子混合晶圆。并且光子晶圆是通过直接键合的方法连接到转接板上。
以上关于图32-35所述的去除光子晶圆的衬底的步骤、减薄光子晶圆底面的埋置氧化层至预定的厚度的步骤、在光子晶圆中布置连接波导并且覆盖该连接波导的步骤、以及在光子晶圆中形成一个或多个第二导电孔等步骤同样适用于关于图36-37所述的方法，除非另有说明或明显不适合。
以上描述了本公开实施例中的各种光芯片封装结构的制造方法。需要说明的是，以上结合流程图描述的制造方法中的各个步骤仅仅是示例性的，并且各个流程图中所示的步骤的顺序不一定是固定不变的，本领域技术人员可以在知晓了本申请的设计构思的基础上，调整各个步骤的顺序，也可以省略或者增加附加的步骤。对于通过这种调整、省略、增加步骤获得的方法同样落入本申请的保护范围内。
在上述描述中，已经结合附图描述了本公开的实施例。应当理解的是，上述实施例仅仅是说明性的，并且本领域技术人员应当理解，可以以各种方式修改本实施例的构成元素和处理的组合，并且这种修改也落入本公开的范围内。

Claims (72)

  1. 一种用于光芯片封装的转接板，包括：
    玻璃基板，包括一个或多个导电通孔，所述导电通孔包括贯穿所述玻璃基板的通孔以及所述通孔内填充的导电材料；以及
    光波导结构，布置在所述玻璃基板的第一表面上，
    其中，所述光波导结构包括一层或多层光波导以及包覆所述一层或多层光波导的包覆层，
    所述一层或多层光波导用于对封装在所述转接板上的多个光芯片进行光互连，并且所述一层或多层光波导的折射率大于所述包覆层以及所述玻璃基板的折射率，并且
    所述光波导结构还包括贯穿所述光波导结构的一个或多个第一导电结构，其与所述一个或多个导电通孔分别电连接。
  2. 如权利要求1所述的转接板，其中
    所述一层或多层光波导为氮化硅光波导，并且所述包覆层的材料为二氧化硅。
  3. 如权利要求1所述的转接板，还包括：
    电介质层，布置在所述玻璃基板的第二表面上；以及
    一个或多个导电凸块，布置在所述电介质层远离所述玻璃基板一侧的表面上，
    其中，所述电介质层包括贯穿所述电介质层的一个或多个第二导电结构，其与所述一个或多个导电通孔分别电连接，并且
    所述一个或多个导电凸块与所述一个或多个第二导电结构分别电连接。
  4. 一种用于光芯片封装的转接板，包括：
    玻璃基板，包括一个或多个导电通孔，所述导电通孔包括贯穿所述玻璃基板的通孔以及所述通孔内填充的导电材料；以及
    光耦合结构，布置在所述玻璃基板的第一表面上，
    其中，所述玻璃基板还包括三维波导网络，用于对封装在所述转接板上的多个光芯片进行光互连，
    所述光耦合结构包括覆盖所述三维波导网络的光输入输出口的耦合光波 导以及包覆所述耦合光波导的包覆层，并且
    所述光耦合结构还包括贯穿所述光耦合结构的一个或多个第一导电结构，其与所述一个或多个导电通孔分别电连接。
  5. 如权利要求4所述的转接板，其中
    所述耦合光波导的折射率低于所述三维波导网络的折射率且高于所述包覆层的折射率。
  6. 如权利要求5所述的转接板，其中
    所述耦合光波导为氮化硅光波导，并且所述包覆层的材料为二氧化硅。
  7. 如权利要求4所述的转接板，还包括：
    电介质层，布置在所述玻璃基板的第二表面上；
    一个或多个导电凸块，布置在所述电介质层远离所述玻璃基板一侧的表面上，
    其中，所述电介质层包括贯穿所述电介质层的一个或多个第二导电结构，其与所述一个或多个导电通孔分别电连接，并且
    所述一个或多个导电凸块与所述一个或多个第二导电结构分别电连接。
  8. 如权利要求4所述的转接板，其中：
    所述三维波导网络是通过在所述玻璃基板内部诱导局部玻璃使所述局部玻璃的折射率提高而构成的网络结构。
  9. 一种用于光芯片封装的转接板，包括：
    玻璃基板，包括一个或多个第一导电通孔，所述第一导电通孔包括贯穿所述玻璃基板的通孔以及所述通孔内填充的导电材料；以及
    电互连结构，布置在所述玻璃基板的第一表面上，
    其中，所述电互连结构包括一层或多层布线层以及包覆所述一层或多层布线层的包覆层，所述包覆层为介电材料，所述一层或多层布线层用于对封装在所述转接板上方的多个电芯片进行电互连，并且
    所述电互连结构还包括贯穿所述电互连结构的一个或多个第一导电结构，其与所述一个或多个第一导电通孔分别电连接。
  10. 如权利要求9所述的转接板，其中
    所述多层布线层中至少两层布线层之间通过第二导电结构电连接。
  11. 如权利要求9所述的转接板，其中
    所述包覆层是由氮化硅层和二氧化硅层交替堆叠形成的多层结构。
  12. 如权利要求9所述的转接板，还包括：
    光波导结构，布置在所述电互连结构的远离所述玻璃基板一侧的表面上，
    其中，所述光波导结构包括一层或多层光波导以及包围所述一层或多层光波导的包围层，
    所述一层或多层光波导用于对封装在所述转接板上的多个光芯片进行光互连，其折射率大于所述包围层的折射率，并且
    所述光波导结构还包括贯穿所述光波导结构的一个或多个第三导电结构，其与所述一个或多个第一导电结构分别电连接。
  13. 如权利要求12所述的转接板，其中
    所述一层或多层光波导为氮化硅光波导，并且所述包围层的材料为二氧化硅。
  14. 如权利要求9所述的转接板，还包括：
    电介质层，布置在所述玻璃基板的第二表面上；
    一个或多个导电凸块，布置在所述电介质层远离所述玻璃基板一侧的表面上，
    其中，所述电介质层包括贯穿所述电介质层的一个或多个第四导电结构，其与所述一个或多个第一导电通孔分别电连接，并且
    所述一个或多个导电凸块与所述一个或多个第四导电结构分别电连接。
  15. 一种用于光芯片封装的转接板的制造方法，包括：
    提供一玻璃基板，并在所述玻璃基板中形成一个或多个导电通孔；
    在所述玻璃基板的第一表面上布置光波导结构，其中，所述光波导结构包括一层或多层光波导以及包覆所述一层或多层光波导的包覆层；以及
    在所述包覆层中形成贯穿所述光波导结构的一个或多个第一导电结构，并将其与所述一个或多个导电通孔分别电连接，
    其中，所述一层或多层光波导的折射率大于所述包覆层的折射率。
  16. 如权利要求15所述的转接板的制造方法，其中
    所述一层或多层光波导为氮化硅光波导，并且所述包覆层的材料为二氧化硅。
  17. 如权利要求16所述的转接板的制造方法，其中，在所述玻璃基板的 第一表面上布置光波导结构包括：
    a.采用晶圆级纳米压印光刻技术，在所述玻璃基板的第一表面上形成光波导的网络；以及
    b.在所述光波导上方沉积包覆层材料。
  18. 如权利要求15所述的转接板的制造方法，还包括：
    在所述玻璃基板的第二表面上布置电介质层；
    在所述电介质层中形成贯穿所述电介质层的一个或多个第二导电结构，并且将其与所述一个或多个导电通孔分别电连接；以及
    在所述电介质层远离所述玻璃基板一侧的表面上布置一个或多个导电凸块，
    其中所述一个或多个导电凸块与所述一个或多个第二导电结构分别电连接。
  19. 如权利要求15所述的转接板的制造方法，其中，在玻璃基板中形成一个或多个导电通孔包括：
    在所述玻璃基板中通过刻蚀形成一个或多个通孔；以及
    在所述一个或多个通孔的内表面上设置导电材料层以形成所述一个或多个导电通孔。
  20. 如权利要求19所述的转接板的制造方法，其中，在所述一个或多个通孔的内表面上设置导电材料层以形成所述一个或多个导电通孔包括：
    采用电镀的方法在所述一个或多个通孔内表面填充导电金属。
  21. 一种用于光芯片封装的转接板的制造方法，包括：
    提供一玻璃基板，并在所述玻璃基板内形成三维波导网络，其用于对封装在所述转接板上的多个光芯片进行光互连；
    在所述玻璃基板中形成一个或多个导电通孔；
    在所述玻璃基板的第一表面上布置耦合光波导，使其覆盖所述三维波导网络的光输入输出口；
    在所述耦合光波导上覆盖包覆层以包覆所述耦合光波导；以及
    在所述包覆层中形成贯穿所述包覆层的一个或多个第一导电结构，并将其与所述一个或多个导电通孔分别电连接。
  22. 如权利要求21所述的转接板的制造方法，其中，
    其中，所述耦合光波导的折射率低于所述三维波导网络的折射率且高于所述包覆层的折射率。
  23. 如权利要求22所述的转接板的制造方法，其中
    所述耦合光波导为氮化硅光波导，并且所述包覆层的材料为二氧化硅。
  24. 如权利要求21所述的转接板的制造方法，还包括：
    在所述玻璃基板的第二表面上布置电介质层；
    在所述电介质层中形成贯穿所述电介质层的一个或多个第二导电结构，并且将其与所述一个或多个导电通孔分别电连接；以及
    在所述电介质层远离所述玻璃基板一侧的表面上布置一个或多个导电凸块，
    其中所述一个或多个导电凸块与所述一个或多个第二导电结构分别电连接。
  25. 如权利要求21所述的转接板的制造方法，其中，在玻璃基板中形成一个或多个导电通孔包括：
    在所述玻璃基板中通过刻蚀形成一个或多个通孔；以及
    在所述一个或多个通孔的内表面上设置导电材料层以形成所述一个或多个导电通孔。
  26. 如权利要求25所述的转接板的制造方法，其中，在所述一个或多个通孔的内表面上设置导电材料层以形成所述一个或多个导电通孔包括：
    采用电镀的方法在所述一个或多个通孔内表面填充导电金属。
  27. 如权利要求21所述的转接板的制造方法，其中，在所述玻璃基板内形成三维波导网络包括：
    采用飞秒激光照射所述玻璃基板的预设位置，以提高所述玻璃基板的所述预设位置的折射率，其中所述预设位置为形成所述三维波导网络结构所在的位置。
  28. 一种用于光芯片封装的转接板的制造方法，包括：
    提供一玻璃基板，并在所述玻璃基板中形成一个或多个第一导电通孔；
    在所述玻璃基板的第一表面上布置电互连结构，其中，所述电互连结构包括一层或多层布线层以及包覆所述一层或多层布线层的包覆层，所述包覆层为介电材料，所述一层或多层布线层用于对封装在所述转接板上方的多个 电芯片进行电互连；以及
    在所述电互连结构中形成贯穿所述电互连结构的一个或多个第一导电结构，其与所述一个或多个第一导电通孔分别电连接。
  29. 如权利要求28所述的转接板的制造方法，其中，在所述玻璃基板的第一表面上布置电互连结构包括：
    在所述玻璃基板的第一表面上布置第一布线层；
    在所述第一布线层周围形成第一氮化硅子层；以及
    在所述第一氮化硅子层上覆盖第一氧化硅子层。
  30. 如权利要求29所述的转接板的制造方法，其中，在所述玻璃基板的第一表面上布置电互连结构还包括：
    在所述第一氧化硅子层的第一表面上布置第二布线层；
    在所述第二布线层周围形成第二氮化硅子层；以及
    在所述第二氮化硅子层上覆盖第二氧化硅子层。
  31. 如权利要求30所述的转接板的制造方法，其中，在所述玻璃基板的第一表面上布置电互连结构还包括：
    在所述第一布线层和所述第二布线层之间形成第二导电结构，以将所述第一布线层和所述第二布线层进行电连接。
  32. 如权利要求28所述的转接板的制造方法，还包括：
    在所述电互连结构远离所述玻璃基板一侧的表面上布置光波导结构，其中，所述光波导结构包括一层或多层光波导以及包围所述一层或多层光波导的包围层，所述一层或多层光波导用于对封装在所述转接板上的多个光芯片进行光互连，其折射率大于所述包围层的折射率；以及
    在所述光波导结构中形成贯穿所述光波导结构的一个或多个第三导电结构，并将其与所述一个或多个第一导电结构分别电连接。
  33. 如权利要求32所述的转接板的制造方法，其中
    所述一层或多层光波导为氮化硅光波导，并且所述包覆层的材料为二氧化硅。
  34. 如权利要求28所述的转接板的制造方法，还包括：
    在所述玻璃基板的第二表面上布置电介质层；
    在所述电介质层中形成贯穿所述电介质层的一个或多个第四导电结构， 并且与所述一个或多个第一导电通孔分别电连接；以及
    在所述电介质层远离所述玻璃基板一侧的表面上布置一个或多个导电凸块，
    其中所述一个或多个导电凸块与所述一个或多个第四导电结构分别电连接。
  35. 如权利要求28所述的转接板的制造方法，其中，在玻璃基板中形成一个或多个导电通孔包括：
    在所述玻璃基板中通过刻蚀形成一个或多个通孔；以及
    在所述一个或多个通孔的内表面上设置导电材料层以形成所述一个或多个导电通孔。
  36. 如权利要求35所述的转接板的制造方法，其中，在所述一个或多个通孔的内表面上设置导电材料层以形成所述一个或多个导电通孔包括：
    采用电镀的方法在所述一个或多个通孔内表面填充导电金属。
  37. 一种光芯片封装结构，包括如权利要求1-14中任一权利要求所述的转接板，以及布置在所述转接板上的多个光芯片，所述转接板用于对布置在所述转接板上的所述多个光芯片进行光互连和/或电互连。
  38. 如权利要求37所述的光芯片封装结构，还包括：
    设置在所述多个光芯片上的一个或多个电芯片；
    所述光芯片包括一个或多个互连结构，所述互连结构包括贯穿所述光芯片的通孔以及通孔内填充的导电材料；
    所述一个或多个互连结构与所述转接板上的所述一个或多个第一导电结构和/或所述一个或多个电互连结构分别电连接。
  39. 一种光芯片封装结构，包括：
    转接板，包括嵌入其中的一个或多个第一光波导；以及
    多个光芯片，每个光芯片包括嵌入其中的一个或多个第二光波导，
    其中，所述多个光芯片贴合到所述转接板的上表面上的不同位置处，并通过所述一个或多个所述第一光波导进行光互连，
    每个所述第一光波导包括第一光耦合部，
    每个所述第二光波导包括第二光耦合部，并且
    所述第一光耦合部与所述第二光耦合部在垂直于所述转接板的上表面的 方向上叠置且间隔预定距离，使得所述第一光耦合部与所述第二光耦合部实现光的绝热耦合。
  40. 如权利要求39所述的光芯片封装结构，其中，
    所述第一光耦合部和所述第二光耦合部分别为锥形形状。
  41. 如权利要求39所述的光芯片封装结构，其中，
    所述第一光耦合部和所述第二光耦合部分别具有由两个不同尺寸的锥形形状级联形成的形状。
  42. 如权利要求39至41中任一项所述的光芯片封装结构，其中，
    所述预定距离小于或等于600nm。
  43. 如权利要求39所述的光芯片封装结构，还包括：
    布置在所述多个光芯片中的多个第一光芯片上的多个电芯片，
    其中，每个第一光芯片的上表面上具有一个或多个第一电连接件，
    每个电芯片的下表面上具有一个或多个第二电连接件，并且
    所述一个或多个第一电连接件分别与所述一个或多个第二电连接件电连接。
  44. 如权利要求43所述的光芯片封装结构，其中，
    所述第一光芯片还包括贯穿其中的一个或多个第二导电通孔，所述一个或多个第二导电通孔与所述转接板中的一个或多个导电结构分别电连接。
  45. 如权利要求43或44所述的光芯片封装结构，其中，
    所述第一光芯片与所述电芯片直接键合；或者
    所述第一光芯片与所述电芯片之间通过倒装焊(flip-chip)贴合。
  46. 如权利要求39至44中的任一项所述的光芯片封装结构，其中，
    所述多个光芯片为分割光子晶圆后所得的分离光芯片，其在所述转接板的上表面上相互间隔开且互相之间的间隙由注塑材料填充，并且
    所述注塑材料与所述转接板的上表面之间布置有用于阻挡所述转接板中的光向外传输的介电层。
  47. 如权利要求39至44中任一项所述的光芯片封装结构，其中，
    所述多个光芯片为同一个光子晶圆中未分割的多个光芯片。
  48. 如权利要求43或44所述的光芯片封装结构，其中，
    所述多个光芯片为同一个光子晶圆中未分割的光芯片，
    所述多个光芯片中具有多个第一光芯片，每个第一光芯片上布置有电芯片，
    所述多个第一光芯片上的多个电芯片为同一个电子晶圆中未分割的多个电芯片，并且
    所述光子晶圆与所述电子晶圆直接键合。
  49. 如权利要求48所述的光芯片封装结构，其中，
    所述多个光芯片中的全部光芯片上都布置有对应的电芯片，并且全部光芯片上的对应的电芯片为同一个电子晶圆中未分割的多个电芯片，并且
    其中所述多个光芯片具有相同的结构，并且所述多个电芯片也具有相同的结构。
  50. 如权利要求39至49中任一项所述的光芯片封装结构，其中，
    所述转接板是如权利要求1-3和权利要求12-14中任一项所述的转接板，并且所述一个或多个第一光波导是如权利要求1-3和权利要求12-14中任一项所述的转接板的光波导结构中的一层或多层光波导。
  51. 如权利要求39至49中任一项所述的光芯片封装结构，其中，
    所述转接板是如权利要求4-8中任一项所述的转接板，并且所述一个或多个第一光波导是如权利要求4-8中任一项所述的转接板中的三维波导网络及覆盖所述三维波导网络的光输入输出口的耦合光波导。
  52. 一种计算加速器，包括：
    一个或多个光源，其布置在如权利要求43-46中任一项所述的光芯片封装结构中的所述转接板的第一表面上，并且被配置为向所述计算加速器提供光波；
    一个或多个计算单元，其由如权利要求39-42中任一项所述的光芯片封装结构中的所述光芯片实现，或由如权利要求43-46中任一项所述的光芯片封装结构中的所述光芯片及电芯片实现，或由如权利要求43-46中任一项所述的光芯片封装结构中的所述电芯片实现，并且被配置为执行计算功能；
    一个或多个存储单元，其由如权利要求43-46中任一项所述的光芯片封装结构中的电芯片实现，并且被配置为执行存储功能。
  53. 如权利要求52所述的计算加速器，其中，
    所述转接板是如权利要求1-8和权利要求12-14中任一项所述的转接板。
  54. 一种计算加速器，包括：
    一个或多个边缘光耦合器，其被配置为将所述计算加速器与其它装置进行光互连；
    一个或多个光源，被配置为向所述计算加速器提供光波，所述光波通过导光结构耦合到所述一个或多个边缘光耦合器；
    一个或多个计算单元，其由如权利要求39-42中任一项所述的光芯片封装结构中的所述光芯片实现，或由如权利要求47-49中任一项所述的光芯片封装结构中的所述光芯片及电芯片实现，或由如权利要求47-49中任一项所述的光芯片封装结构中的所述电芯片实现，并且被配置为执行计算功能；以及
    一个或多个存储单元，其由如权利要求47-49中任一项所述的光芯片封装结构中的电芯片实现，并且被配置为执行存储功能。
  55. 如权利要求54所述的计算加速器，其中，
    由如权利要求49所述的光芯片封装结构中的每个光芯片及对应的电芯片实现每个计算单元和对应的存储单元，作为计算-存储单元。
  56. 如权利要求54或55所述的计算加速器，其中，
    所述的光芯片封装结构中的转接板是如权利要求1-8和权利要求12-14中任一项所述的转接板。
  57. 如权利要求52至56中任一项所述的计算加速器，还包括：
    叠置在所述的光芯片封装结构中的所述光芯片上的多个高带宽内存(HBM)芯片，其被配置为执行内存计算功能。
  58. 一种光芯片封装结构的制造方法，包括：
    提供一转接板，其包括嵌入其中的一个或多个第一光波导，每个所述第一光波导包括第一光耦合部；以及
    将多个光芯片贴合到所述转接板的上表面上的不同位置处，每个光芯片包括嵌入其中的一个或多个第二光波导，每个所述第二光波导包括第二光耦合部，其中
    所述第一光耦合部与所述第二光耦合部在垂直于所述转接板的上表面的方向上叠置且间隔预定距离，使得所述第一光耦合部与所述第二光耦合部实现光的绝热耦合，并且所述多个光芯片通过所述一个或多个第一光波导进行 光互连。
  59. 如权利要求58所述的光芯片封装结构的制造方法，其中，
    所述第一光耦合部和所述第二光耦合部分别为锥形形状。
  60. 如权利要求58所述的光芯片封装结构的制造方法，其中，
    所述第一光耦合部和所述第二光耦合部分别具有由两个不同尺寸的锥形形状级联形成的形状。
  61. 如权利要求58至60中任一项所述的光芯片封装结构的制造方法，其中，
    所述预定距离小于或等于600nm。
  62. 如权利要求58所述的光芯片封装结构的制造方法，在将多个光芯片贴合到所述转接板的上表面上的不同位置处之前，还包括：
    在所述多个光芯片中的第一光芯片上布置电芯片，使得所述第一光芯片和其上的电芯片形成电子-光子混合芯片，
    其中，所述第一光芯片的上表面上具有一个或多个第一电连接件，
    所述电芯片的下表面上具有一个或多个第二电连接件，并且
    所述一个或多个第一电连接件分别与所述一个或多个第二电连接件电连接。
  63. 如权利要求62所述的光芯片封装结构的制造方法，其中，在所述多个光芯片中的第一光芯片上布置电芯片包括：
    制备光子晶圆和电子晶圆，所述光子晶圆包括多个第一光芯片，所述电子晶圆包括多个电芯片；
    将所述电子晶圆直接键合到所述光子晶圆，使得所述多个第一光芯片与所述多个电芯片键合，以得到电子-光子混合晶圆；
    去除所述光子晶圆的衬底；以及
    将所述电子-光子混合晶圆切割成多个电子-光子混合芯片。
  64. 如权利要求62所述的光芯片封装结构的制造方法，其中，在所述多个光芯片中的第一光芯片上布置电芯片包括：
    制备光子晶圆和电子晶圆，所述光子晶圆包括所述多个光芯片，所述电子晶圆包括多个电芯片；
    将所述电子晶圆切割成所述多个电芯片；
    将所述多个电芯片中的一个或多个直接键合或者倒装焊(flip-chip)到所述光子晶圆中的第一光芯片上，以得到电子-光子混合晶圆；
    在所述光子晶圆上未被所述电子芯片占据的间隙中填充注塑材料；
    去除所述光子晶圆的衬底；以及
    将所述电子-光子混合晶圆切割成所述电子-光子混合芯片。
  65. 如权利要求59或64所述的光芯片封装结构的制造方法，还包括：
    在去除所述光子晶圆的衬底之后，将所述电子-光子混合晶圆切割成所述电子-光子混合芯片之前，减薄所述光子晶圆底面的埋置氧化层至预定的厚度。
  66. 如权利要求63或64所述的光芯片封装结构的制造方法，还包括：
    在去除所述光子晶圆的衬底之后，减薄所述光子晶圆底面的埋置氧化层，在所述光子晶圆远离所述电芯片的表面上形成连接波导，所述连接波导与所述第二光波导的所述第二光耦合部、所述第一波导的所述第一光耦合部在光子晶圆的下表面的垂直方向上叠置且间隔开；以及
    在所述连接波导上覆盖电介质以包覆所述连接波导。
  67. 如权利要求63或64所述的光芯片封装结构的制造方法，还包括：
    在制备所述光子晶圆之后，在所述光子晶圆中形成一个或多个第二导电孔；以及在去除所述光子晶圆的衬底之后，减薄所述光子晶圆底面的埋置氧化层至预定厚度，使所述一个或多个第二导电孔上下贯通以形成一个或多个第二导电通孔。
  68. 如权利要求66所述的光芯片封装结构的制造方法，其中，将所述多个光芯片贴合到所述转接板的上表面上的不同位置处还包括：
    将所述一个或多个第二导电通孔与所述转接板中的一个或多个导电结构分别电连接。
  69. 如权利要求62所述的光芯片封装结构的制造方法，其中，所述多个电子-光子混合芯片在所述转接板的上表面上相互间隔开，并且所述方法还包括：
    在所述转接板的上表面上且在所述多个电子-光子混合芯片之间的间隙中形成用于阻挡所述转接板中的光向外传输的介电层；以及
    在所述介电层上且在所述电子-光子小芯片的间隙中填充注塑材料。
  70. 如权利要求62所述的光芯片封装结构的制造方法，其中，
    在所述多个光芯片中的第一光芯片上布置电芯片包括：
    制备光子晶圆和电子晶圆，所述光子晶圆包括多个第一光芯片，所述电子晶圆包括多个电芯片，以及
    将所述电子晶圆直接键合到所述光子晶圆，使得所述多个第一光芯片与所述多个电芯片键合，以得到电子-光子混合晶圆；以及
    将多个光芯片贴合到所述转接板的上表面上的不同位置处包括：
    将所述电子-光子混合晶圆直接键合到所述转接板的上表面上。
  71. 如权利要求58至70中任一项所述的光芯片封装结构的制造方法，其中，
    所述转接板是如权利要求15-20和权利要求28-36中任一项所述的方法制造的转接板，并且所述一个或多个第一光波导是如15-20和权利要求28-36中任一项所述的方法制造的转接板中的光波导结构中的一层或多层光波导。
  72. 如权利要求58至70中任一项所述的光芯片封装结构的制造方法，其中，
    所述转接板是如权利要求21-27中任一项所述的方法制造的转接板，并且所述一个或多个第一光波导是如权利要求21-27中任一项所述的方法制造的转接板中的三维波导网络及覆盖所述三维波导网络的光输入输出口的耦合光波导。
PCT/CN2023/086785 2022-04-08 2023-04-07 转接板、光芯片封装、计算加速器及其制造方法 WO2023193780A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210369385.3A CN116931167A (zh) 2022-04-08 2022-04-08 转接板、光芯片封装、计算加速器及其制造方法
CN202210369385.3 2022-04-08

Publications (1)

Publication Number Publication Date
WO2023193780A1 true WO2023193780A1 (zh) 2023-10-12

Family

ID=88244107

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/086785 WO2023193780A1 (zh) 2022-04-08 2023-04-07 转接板、光芯片封装、计算加速器及其制造方法

Country Status (3)

Country Link
CN (1) CN116931167A (zh)
TW (1) TW202340774A (zh)
WO (1) WO2023193780A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117096039A (zh) * 2023-10-20 2023-11-21 盛合晶微半导体(江阴)有限公司 光电互连封装结构及其制备方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103760635A (zh) * 2014-01-28 2014-04-30 华进半导体封装先导技术研发中心有限公司 玻璃基三维光电同传器件及其制作方法
US20140270629A1 (en) * 2013-03-15 2014-09-18 Apic Corporation Optical waveguide network of an interconnecting ic module
CN107431064A (zh) * 2015-03-19 2017-12-01 国际商业机器公司 具有用于封装组件之间的高速通信的集成波导的封装结构
CN107817562A (zh) * 2016-09-13 2018-03-20 格罗方德半导体公司 在光波导之间用于光信号传输的具有垂直对准光栅耦合器的多芯片模块
CN110648974A (zh) * 2018-06-27 2020-01-03 台湾积体电路制造股份有限公司 光子器件和形成光子器件方法
CN110911373A (zh) * 2018-09-18 2020-03-24 台湾积体电路制造股份有限公司 封装结构及其制造方法
US20210041649A1 (en) * 2018-04-03 2021-02-11 Corning Incorporated Integrated circuit packages having electrical and optical connectivity and methods of making the same
CN112530925A (zh) * 2019-09-19 2021-03-19 台湾积体电路制造股份有限公司 封装件及其形成方法
CN115840269A (zh) * 2021-09-20 2023-03-24 英特尔公司 光耦合附接到玻璃衬底的管芯的玻璃衬底内的光波导

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140270629A1 (en) * 2013-03-15 2014-09-18 Apic Corporation Optical waveguide network of an interconnecting ic module
CN103760635A (zh) * 2014-01-28 2014-04-30 华进半导体封装先导技术研发中心有限公司 玻璃基三维光电同传器件及其制作方法
CN107431064A (zh) * 2015-03-19 2017-12-01 国际商业机器公司 具有用于封装组件之间的高速通信的集成波导的封装结构
CN107817562A (zh) * 2016-09-13 2018-03-20 格罗方德半导体公司 在光波导之间用于光信号传输的具有垂直对准光栅耦合器的多芯片模块
US20210041649A1 (en) * 2018-04-03 2021-02-11 Corning Incorporated Integrated circuit packages having electrical and optical connectivity and methods of making the same
CN110648974A (zh) * 2018-06-27 2020-01-03 台湾积体电路制造股份有限公司 光子器件和形成光子器件方法
CN110911373A (zh) * 2018-09-18 2020-03-24 台湾积体电路制造股份有限公司 封装结构及其制造方法
CN112530925A (zh) * 2019-09-19 2021-03-19 台湾积体电路制造股份有限公司 封装件及其形成方法
CN115840269A (zh) * 2021-09-20 2023-03-24 英特尔公司 光耦合附接到玻璃衬底的管芯的玻璃衬底内的光波导

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117096039A (zh) * 2023-10-20 2023-11-21 盛合晶微半导体(江阴)有限公司 光电互连封装结构及其制备方法
CN117096039B (zh) * 2023-10-20 2024-01-30 盛合晶微半导体(江阴)有限公司 光电互连封装结构及其制备方法

Also Published As

Publication number Publication date
TW202340774A (zh) 2023-10-16
CN116931167A (zh) 2023-10-24

Similar Documents

Publication Publication Date Title
US9391708B2 (en) Multi-substrate electro-optical interconnection system
US11703639B2 (en) Photonic semiconductor device and method
CN114830003A (zh) 用于封装内光互连的垂直集成光子小芯片
WO2013086047A1 (en) Integrated multi-chip module optical interconnect platform
CN112687672B (zh) 一种硅基光电子异质集成互连模组
US20080023804A1 (en) High-speed electrical interconnects and method of manufacturing
US11605621B2 (en) Hybrid integrated circuit package and method
WO2023193780A1 (zh) 转接板、光芯片封装、计算加速器及其制造方法
US20220158736A1 (en) Optical Module and Method of Fabrication
US11747563B2 (en) Photonic semiconductor device and method of manufacture
TW202316608A (zh) 半導體裝置
KR20230075333A (ko) 도파관을 갖는 인터포저 및 포토닉 패키지를 포함하는 패키지 구조물
US20230384538A1 (en) Structures and process flow for integrated photonic-electric ic package by using polymer waveguide
TWI813229B (zh) 封裝及其製造方法
CN112736073B (zh) 一种硅基光计算异质集成模组
US20240097796A1 (en) Photonic chiplet packaging
CN112687673B (zh) 一种不同厚度芯片嵌入载片结构及其制备方法
WO2024022113A1 (zh) 片上光互连结构及其制作方法
CN115542478B (zh) 一种基于光电芯片双面工艺的三维封装结构及封装方法
US20240192439A1 (en) Heterogeneous package structures with photonic devices
CN117784324A (zh) 光电互连结构及其制作方法
Li et al. 48-channel matrix optical transmitter on a single direct fiber connector
US20230377907A1 (en) Package structure including photonic package having embedded optical glue
US20240111106A1 (en) Photonic glass layer substrate with embedded optical structures for communicating with an electro optical integrated circuit
CN117913084A (zh) 基于2.5d封装技术的光电芯片混合封装结构及封装方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23784343

Country of ref document: EP

Kind code of ref document: A1