WO2024007543A1 - 存储单元、存储器及其控制方法 - Google Patents

存储单元、存储器及其控制方法 Download PDF

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Publication number
WO2024007543A1
WO2024007543A1 PCT/CN2022/140774 CN2022140774W WO2024007543A1 WO 2024007543 A1 WO2024007543 A1 WO 2024007543A1 CN 2022140774 W CN2022140774 W CN 2022140774W WO 2024007543 A1 WO2024007543 A1 WO 2024007543A1
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WIPO (PCT)
Prior art keywords
transistor
word line
gate
electrically connected
electrode
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PCT/CN2022/140774
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English (en)
French (fr)
Inventor
朱正勇
康卜文
赵超
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北京超弦存储器研究院
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Publication of WO2024007543A1 publication Critical patent/WO2024007543A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of semiconductor technology. Specifically, the present application relates to a storage unit, a memory and a control method thereof.
  • the storage unit of mainstream DRAM is usually a 1T (Transistor, transistor) 1C (Capacitor, capacitor) structure.
  • This application proposes a storage unit, a memory and a control method thereof, which are at least used to improve the deficiencies in the background technology.
  • a storage unit including:
  • the first transistor which is a write transistor, includes: a first electrode configured to be electrically connected to the first bit line, a second electrode, a first main gate configured to be electrically connected to the first word line, and a first auxiliary gate;
  • the second transistor which is a read transistor, includes: a fourth electrode, a second main gate configured to be electrically connected to the second word line, and a second auxiliary gate;
  • the third transistor which is a write transistor, includes: a fifth electrode, a sixth electrode electrically connected to the first auxiliary gate, and a third gate configured to be electrically connected to the third word line;
  • the fourth transistor which is a write transistor, includes: a seventh electrode, an eighth electrode electrically connected to the second auxiliary gate, and a fourth gate configured to be electrically connected to the fourth word line; the seventh electrode, the second The electrode, the fourth electrode and the fifth electrode are all electrically connected to the first node;
  • a first capacitor and a second capacitor one electrode of the first capacitor is the first auxiliary gate, and one electrode of the second capacitor is the second auxiliary gate.
  • embodiments of the present application provide a memory, including: a plurality of first bit lines, a plurality of first word lines, a plurality of second word lines, a plurality of third word lines, and a plurality of fourth word lines. lines and multiple storage units;
  • the first bit line extends along the first direction on the substrate, the first word line, the second word line, the third word line and the fourth word line all extend along the second direction on the substrate, and the second direction is perpendicular to the first word line. one direction;
  • the memory unit includes: a first transistor that is a write transistor, a second transistor that is a read transistor, a third transistor that is a write transistor, a fourth transistor that is a write transistor, a first capacitor and a second capacitor;
  • the first electrode of the first transistor is electrically connected to the first bit line, the first main gate of the first transistor is electrically connected to the first word line; the second main gate of the second transistor is electrically connected to the second word line; The third gate of the three transistors is electrically connected to the third word line; the fourth gate of the fourth transistor is electrically connected to the fourth word line; one electrode of the first capacitor is the first auxiliary gate of the first transistor, and the second One electrode of the capacitor is the second auxiliary gate of the second transistor.
  • embodiments of the present application provide a memory control method, including:
  • a first level is applied to the second main gate of the second transistor of the memory cell to be read through the second word line, and the first level is applied to the first transistor of the memory cell to be read through the first word line.
  • the first main gate applies a second level, so that the first bit line senses the stored data of the first capacitance of the memory cell to be read; the first level is higher than the second level.
  • the second transistor since the first electrode of the first transistor is configured to be electrically connected to the first bit line and the first main gate is configured to be electrically connected to the first word line, the second transistor The second main gate is configured to be electrically connected to the second word line, the third gate of the third transistor is configured to be electrically connected to the third word line, and the fourth gate of the fourth transistor is configured to be electrically connected to the fourth word line. Therefore, it is possible to avoid the electrical connection between the word line for reading and the electrodes of each transistor except the gate electrode among the above-mentioned word lines. Furthermore, when the transistor is in a conductive state, it is possible to avoid the need for reading.
  • the word line is electrically connected to the first bit line, which can avoid crosstalk between the word line for reading and the first bit line, thus ensuring the operation of the memory cell.
  • the memory unit by setting the first auxiliary gate of the first transistor as an electrode of the first capacitor and the second auxiliary gate of the second transistor as an electrode of the second capacitor, the memory unit has Two capacitors used to store data enable the memory cell to store two bits of data.
  • Figure 1 is a schematic circuit diagram of a memory unit provided by an embodiment of the present application.
  • Figure 2 is a schematic circuit diagram of another memory unit provided by an embodiment of the present application.
  • Figure 3 is a schematic circuit diagram of another memory unit provided by an embodiment of the present application.
  • Figure 4a is a schematic circuit diagram of a memory according to an embodiment of the present application.
  • Figure 4b is an enlarged schematic diagram of point A in the circuit principle schematic diagram of a memory shown in Figure 4a according to the embodiment of the present application;
  • Figure 5a is a schematic circuit diagram of another memory according to an embodiment of the present application.
  • Figure 5b is an enlarged schematic diagram of point B in the circuit principle schematic diagram of another memory shown in Figure 5a according to the embodiment of the present application;
  • Figure 6a is a schematic circuit diagram of another memory according to an embodiment of the present application.
  • Figure 6b is an enlarged schematic diagram of position C in the circuit principle schematic diagram of another memory shown in Figure 6a according to the embodiment of the present application;
  • Figure 7 is a schematic diagram of the frame structure of an electronic device provided by an embodiment of the present application.
  • FIG. 8 is a graph showing transfer characteristics of the first transistor in the memory when writing different data.
  • 70-second bit line 80-reference potential terminal; 90-reference potential line;
  • connection may include wireless connections or wireless couplings.
  • the term “and/or” used herein refers to at least one of the items defined by the term. For example, “A and/or B” can be realized as “A”, or as “B”, or as “A and B” ".
  • the 2T structure refers to the use of two transistors to achieve data access.
  • the 2T structure includes a write transistor and a read transistor.
  • the gate of the write transistor is electrically connected to the write word line
  • the source of the write transistor is electrically connected to the write bit line
  • the drain of the write transistor is electrically connected to the write word line.
  • the gate of the read transistor is connected, the source of the read transistor is electrically connected to the read word line, the drain of the read transistor is electrically connected to the read bit line, and data is stored in the drain of the write transistor and the gate of the read transistor. between.
  • the memory cells of mainstream DRAM are usually 1T1C structure.
  • 1T1C structure In order to reduce the refresh rate of the 1T1C structure, reduce power consumption, and avoid setting up capacitors with large capacitance values, some manufacturers use 2T structure memory units.
  • the source of the read transistor is electrically connected to the read word line and the drain of the read transistor is electrically connected to the read bit line
  • storage is stored between the drain of the write transistor and the gate of the read transistor.
  • the high-level signal can easily cause the gate of the read transistor to turn on, that is, cause the read transistor to be turned on.
  • a DRAM including a 2T structure arranged in an array it can easily cause the read word line and read bit to be turned on. The problem of crosstalk occurs in the lines, which causes the DRAM to not work properly.
  • the existing technology In order to reduce the probability of crosstalk between the read word line and the read bit line, the existing technology often requires setting up a separate control circuit, which increases the difficulty of DRAM design and increases the manufacturing cost of DRAM. Moreover, the control circuit takes up a large amount of space. Peripheral area, thereby reducing the number of memory cells per unit area in DRAM.
  • the storage of data requires a write transistor, and the reading of data requires a read transistor.
  • Each transistor needs to be equipped with a word line and a bit line.
  • the 2T structure stores and reads one bit of data. , two word lines and two bit lines are required, which will increase the number of wires in the DRAM, leading to an increase in the design difficulty, manufacturing difficulty and manufacturing cost of the DRAM.
  • the storage unit, memory and control method provided by this application are intended to solve the above technical problems of the prior art.
  • FIG. 1 An embodiment of the present application provides a memory unit.
  • the schematic circuit diagram of the memory unit 10 is shown in FIG. 1 , including: a first transistor 11 , a second transistor 12 , a third transistor 13 and a fourth transistor 14 .
  • the first transistor 11 which is a write transistor includes: a first electrode 111 configured to be electrically connected to the first bit line 20 and a second electrode 112 configured to be electrically connected to the first bit line 20 .
  • the word line 30 is electrically connected to the first main gate 113 and the first auxiliary gate 114 .
  • the second transistor 12 which is a read transistor, includes a fourth electrode 122 , a second main gate 123 configured to be electrically connected to the second word line 40 , and a second auxiliary gate 124 .
  • the third transistor 13 which is a write transistor includes: a fifth electrode 131 , a sixth electrode 132 electrically connected to the first auxiliary gate 114 , and a third transistor 13 configured to be electrically connected to the third word line 50 .
  • Tri-Gate 133 Tri-Gate 133
  • the fourth transistor 14 which is a write transistor includes: a seventh electrode 141 , an eighth electrode 142 electrically connected to the second auxiliary gate 124 , and a third electrode configured to be electrically connected to the fourth word line 60 .
  • the fourth gate 143; the seventh electrode 141, the second electrode 112, the fourth electrode 122 and the fifth electrode 131 are all electrically connected to the first node.
  • one electrode of the first capacitor 115 is the first auxiliary gate 114, and one electrode of the second capacitor 125 is the second auxiliary gate 124.
  • the second main gate 123 of the second transistor 12 is configured to be electrically connected to the second word line 40
  • the third gate 133 of the third transistor 13 is configured to be electrically connected to the third word line 50
  • the fourth gate electrode 143 of 14 is configured to be electrically connected to the fourth word line 60, so as to avoid the electrical connection between the read word line and the electrodes of each transistor except the gate electrode among the above word lines, and further When the transistor is in a conductive state, the electrical connection between the read word line and the first bit line 20 can be avoided, and the crosstalk between the read word line and the first bit line 20 can be avoided, thereby ensuring the stability of the memory cell 10 . Work.
  • the first auxiliary gate 114 of the first transistor 11 is set as an electrode of the first capacitor 115 and the second auxiliary gate 124 of the second transistor 12 is set as the second capacitor.
  • An electrode of 125 enables the memory unit 10 to have two capacitors for storing data, so that the memory unit 10 can store two bits of data.
  • the memory unit 10 includes four transistors.
  • the first transistor 11 , the second transistor 12 , the third transistor 13 and the fourth transistor 14 are all MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistor, Metal-Oxide-Semiconductor Field-Effect Transistor).
  • the first transistor 11 one of the first electrode 111 and the second electrode 112 is the source and the other is the drain; for the second transistor 12 , the third electrode 121 One of the fifth electrode 131 and the sixth electrode 132 is a source electrode, and the other is a drain electrode; for the third transistor 13, one of the fifth electrode 131 and the sixth electrode 132 is a source electrode, and the other one is a drain electrode; for the third transistor 13, For the four-transistor 14, one of the seventh electrode 141 and the eighth electrode 142 is the source electrode, and the other one is the drain electrode.
  • those skilled in the art can determine whether each electrode is a source or a drain according to whether each transistor is an N-type transistor or a P-type transistor.
  • the first electrode 111 is configured to be electrically connected to the first bit line 20
  • the first main gate 113 is configured to be electrically connected to the first word line 30, and the second electrode 112
  • the first auxiliary gate 114 is electrically connected to the fifth electrode 131 of the third transistor 13;
  • the third gate 133 of the third transistor 13 is configured to be connected to the third word line.
  • 50 is electrically connected, so that the turn-on level of the first transistor 11 and the third transistor 13 can be controlled through the turn-on level applied by the first word line 30 and the third word line 50, so that the first capacitor 115 can be supplied to the first capacitor 115 through the first bit line 20.
  • the storage signal is transmitted to write the storage signal into the first capacitor 115 as storage data.
  • the first auxiliary gate 114 since the first auxiliary gate 114 has a back-gate effect, that is, the potential of the first auxiliary gate 114 will affect the threshold voltage of the first transistor 11, it is used to turn on the first transistor 11 when reading stored data.
  • the value range of the voltage of a transistor 11 is between the threshold voltage when the first transistor 11 stores "1" and the threshold voltage when the first transistor 11 stores "0".
  • the storage signal can be written into the second capacitor 125 as storage data.
  • the specific control method will be explained later and will not be described again here.
  • the second electrode 112, the fourth electrode 122, the fifth electrode 131 and the seventh electrode 141 are electrically connected to the first node 17.
  • they are shown in black.
  • the dot represents the first node 17.
  • the first main gate 113 is configured to be electrically connected to the first word line 30 and the second main gate 123 is configured to be electrically connected to the second word line 40 .
  • the third gate 133 of the third transistor 13 is configured to be electrically connected to the third word line 50 and the fourth gate 143 of the fourth transistor 14 is configured to be electrically connected to the fourth word line 60, the above-mentioned word line can be avoided.
  • the lines are electrically connected to the source and drain of each transistor, so that during the operation of the memory unit 10, especially during the reading stage of the memory unit 10, it is possible to avoid the first word line 30, the second word line 40, the third word line At least one of the word lines 50 and the fourth word lines 60 is electrically connected to the first bit line 20, thereby avoiding crosstalk problems between the above word lines and the first bit line 20. In particular, it is possible to avoid reading The crosstalk problem between the taken word line and the first bit line 20 can ensure the operation of the memory unit 10 .
  • the first auxiliary gate 114 of the first transistor 11 is a back gate, and the first auxiliary gate 114 is an electrode of the first capacitor 115 .
  • at least one of the first electrode 111 , the second electrode 112 and other conductive parts forms another electrode of the first capacitor 115 , and the film layer between the two electrodes, especially the insulating film layer, forms the first capacitor 115
  • the dielectric layer enables the first transistor 11 and the first capacitor 115 to be integrated, thereby reducing the volume of the memory unit 10 .
  • the second auxiliary gate 124 of the second transistor 12 is a back gate and multiplexed as an electrode of the second capacitor 125. At least one of its conductive parts in the second transistor 12 forms another electrode of the second capacitor 125. One electrode allows the second transistor 12 and the second capacitor 125 to be integrated, thereby further reducing the size of the memory unit 10 .
  • the memory unit 10 can store two bits of data, thereby avoiding Providing a capacitor structure can reduce the structural volume of the memory unit 10 and facilitate the integrated development of the memory unit 10 .
  • the memory cell 10 only needs to be configured with a first bit line 20 , a first word line 30 , a second word line 40 , a third word line 50 and a fourth word line.
  • There are a total of five wires 60 which can realize the access of two-bit data.
  • the number of wire routing can be greatly reduced, thereby reducing the difficulty of design and manufacturing, and thus The manufacturing cost of the memory unit 10 can be reduced.
  • the first word line 30 electrically connected to the first main gate 113 and the third word line 50 electrically connected to the third gate 133 are configured to be electrically connected to the first control terminal 15; the second word line 40 electrically connected to the second main gate 123 and the fourth word line 60 electrically connected to the fourth gate 143 are configured to be electrically connected to the second control terminal 16 Electrical connection.
  • the first word line 30 and the third word line 50 are configured to be electrically connected to the first control terminal 15 , that is, the first main gate 113 and the third gate 133 Both are electrically connected to the first control terminal 15 . Therefore, the same control voltage can be applied to the first main gate 113 and the gate 133 of the third transistor 13 through the first control terminal 15 .
  • the first auxiliary gate 114 Since the first auxiliary gate 114 has a backgate effect, that is, the potential of the first auxiliary gate 114 will affect the threshold voltage of the first transistor 11, the voltage used to turn on the first transistor 11 when reading stored data is The numerical range is between the threshold voltage when the first transistor 11 stores "1" and the threshold voltage when the first transistor 11 stores "0", so that the first main gate 113 and the third gate are supplied through the first control terminal 15.
  • the first transistor 11 can be controlled to be in an on state, and the third transistor 13 cannot be on, so that the first capacitor 115 can store data. Read.
  • the second word line 40 and the fourth word line 60 are configured to be electrically connected to the second control terminal 16 , that is, the second main gate 123 and the fourth gate 143 Both are electrically connected to the second control terminal 16 . Therefore, the same control voltage can be applied to the second main gate 123 and the fourth gate 143 through the second control terminal 16 .
  • the same control voltage is applied to the second main gate 123 and the fourth gate 143 through the second control terminal 16, and the control voltage is less than the threshold voltage of the fourth transistor 14, so that the second transistor 12 can be controlled to turn on, The fourth transistor 14 is not turned on, so that the data stored in the second capacitor 125 can be read.
  • the number of wire traces configured in the memory unit 10 can be further reduced, thereby reducing the design difficulty, reducing the manufacturing difficulty, and further reducing the manufacturing cost of the memory unit 10 .
  • the materials of the semiconductor layer of the third transistor 13 and the semiconductor layer of the fourth transistor 14 each include a metal oxide semiconductor.
  • the semiconductor layer of the third transistor 13 and the semiconductor layer of the fourth transistor 14 are made of metal oxide semiconductors, so that the leakage current of the third transistor 13 and the fourth transistor 14 can be reduced, thereby It can reduce the refresh rate of the storage unit and reduce the power consumption of the storage unit.
  • the metal oxide semiconductor includes IGZO (Indium Gallium Zinc Oxide, indium gallium zinc oxide), IWO (Indium Wolfram Oxide, tungsten-doped indium oxide), ITO (indium tin oxide), ZnOx (zinc oxide), InOx (oxide Indium), In2O3 (indium trioxide), InWO (indium tungsten oxide), SnO2 (tin dioxide), TiOx (titanium oxide), InSnOx (indium tin oxide), ZnxOyNz (nitrogen-doped zinc oxide), MgxZnyOz (magnesium oxide Zinc), InxZnyOz (indium zinc oxide), InxGayZnzOa (indium gallium zinc oxide), ZrxInyZnzOa (zirconium indium zinc oxide), HfxInyZnzOa (hafnium indium zinc oxide), SnxInyZnzOa (tin indium zinc oxide), Alx
  • the third transistor 13 and the fourth transistor 14 may be VGAA (Vertical gate-all-around) transistors, thereby reducing the structural volume of the memory unit 10 and improving Storage density per unit area.
  • VGAA Very gate-all-around
  • the third electrode 121 of the second transistor 12 is configured to be electrically connected to the second bit line 70 ; the first bit line 20 and the second bit line 70 is connected to different consoles.
  • the third electrode 121 of the second transistor 12 is configured to be electrically connected to the second bit line 70 .
  • the turn-on of the second transistor 12 and the fourth transistor 14 can be controlled, thereby passing
  • the second bit line 70 transmits the storage signal to the second capacitor 125 to write the storage signal into the second capacitor 125 as storage data.
  • one bit of data can be stored through the first transistor 11 and the third transistor 13, and the second transistor 12 and the fourth transistor 14 can be used to store one bit of data.
  • the storage of another bit of data can be realized, so that the storage unit 10 can store two bits of data.
  • the first bit line 20 and the second bit line 70 are connected to different control terminals, so as to facilitate independent control of the stored data of the first capacitor 115 and the second capacitor 125, and to facilitate independent reading of the first capacitor 115. and the stored data in the second capacitor 125 .
  • the third electrode 121 of the second transistor 12 is configured to be electrically connected to the reference potential terminal 80 .
  • the third electrode 121 of the second transistor 12 is configured to be electrically connected to the reference potential terminal 80, which can be equivalent to the circuit shown in Figure 2.
  • the reference potential terminal 80 provides a reference potential Vrefn. During the operation of the memory unit 10, the reference potential Vrefn is stable.
  • the turn-on levels applied by the first word line 30 and the fourth word line 60 can control the first transistor 11 and the fourth transistor 14 . Turn on, thereby transmitting the storage signal to the second capacitor 125 through the first bit line 20, so as to write the storage signal into the second capacitor 125 as storage data.
  • one bit of data can be stored through the first transistor 11 and the third transistor 13, and through the first transistor 11 and the fourth transistor 14
  • the storage of another bit of data can be realized, so that the storage unit 10 can store two bits of data.
  • the third electrode 121 is electrically connected to the reference potential terminal 80 so that the second transistor 12 only participates in the reading phase.
  • the specific working principle of the memory unit 10 shown in Figure 2 will be controlled later. This is explained in the method and will not be repeated here.
  • an embodiment of the present application provides a memory.
  • the schematic circuit diagram of the memory is shown in Figure 4a, including: a plurality of first bit lines 20, a plurality of first word lines 30, and a plurality of second word lines. lines 40 , a plurality of third word lines 50 , a plurality of fourth word lines 60 and a plurality of memory cells 10 .
  • the first bit line 20 extends along the first direction on the substrate, and the first word line 30, the second word line 40, the third word line 50 and the fourth word line 60 all extend along the substrate.
  • the second direction extends, and the second direction is perpendicular to the first direction.
  • the memory unit 10 includes: a first transistor 11 that is a write transistor, a second transistor 12 that is a read transistor, a third transistor 13 that is a write transistor, a fourth transistor 14 that is a write transistor, a first capacitor 115 and the second capacitor 125; the first electrode 111 of the first transistor 11 is electrically connected to the first bit line 20, and the first main gate 113 of the first transistor 11 is electrically connected to the first word line 30; The second main gate 123 is electrically connected to the second word line 40; the third gate 133 of the third transistor 13 is electrically connected to the third word line 50; the fourth gate 143 of the fourth transistor 14 is electrically connected to the fourth word line 60 Electrically connected; one electrode of the first capacitor 115 is the first auxiliary gate 114 of the first transistor 11 , and one electrode of the second capacitor 125 is the second auxiliary gate 124 of the second transistor 12 .
  • multiple memory cells 10 are arranged in an array; in each memory cell 10 located in the same column, each first transistor 11 The first electrode 111 is electrically connected to the same first bit line 20; in each memory cell 10 located in the same row, the first main gate 113 of each first transistor 11 is electrically connected to the same first word line 30, and each The second main gate 123 of the second transistor 12 is electrically connected to the same second word line 40 , the third gate 133 of each third transistor 13 is electrically connected to the same third word line 50 , and the third gate electrode 133 of each third transistor 13 is electrically connected to the same third word line 50 .
  • the fourth gate 143 is electrically connected to the same fourth word line 60 .
  • a plurality of memory cells 10 are arranged in an array, forming a plurality of memory cell columns parallel to the first direction and a plurality of memory cells parallel to the second direction. cell column.
  • each memory cell 10 located in the same column the first electrode 111 of each first transistor 11 is electrically connected to the same first bit line 20 .
  • each memory cell 10 located in the same row the first main gate 113 of each first transistor 11 is electrically connected to the same first word line 30 , and the second main gate 123 of each second transistor 12 is electrically connected to the same second word line 30 .
  • the word line 40 is electrically connected, the third gate electrode 133 of each third transistor 13 is electrically connected to the same third word line 50 , and the fourth gate electrode 143 of each fourth transistor 14 is electrically connected to the same fourth word line 60 .
  • the memory further includes: a plurality of second bit lines 70, the second bit lines 70 extend along the first direction on the substrate; located on In each memory cell 10 in the same column, the third electrode 121 of each second transistor 12 is electrically connected to the same second bit line 70 .
  • the memory includes a plurality of memory cells 10 arranged in an array as shown in Figure 4b. Please refer to Figure 1 for the specific structure of the memory cells 10 shown in Figure 4b.
  • the first electrode 111 of each first transistor 11 is electrically connected to the same first bit line 20
  • the third electrode 121 of each second transistor 12 is electrically connected to the same second bit line 20.
  • Bit lines 70 are electrically connected.
  • the first bit line 20 is used to store data in the first capacitor 115, and the second bit line 70 is used to store data in the second capacitor 125; similarly,
  • the first bit line 20 is used to refresh the stored data of the first capacitor 115
  • the second bit line 70 is used to refresh the stored data of the second capacitor 125 .
  • the reading phase will be explained in detail in the control method later and will not be described again here.
  • each memory cell 10 in the memory only needs to be configured with a first bit line 20, a second bit line 70, a first word line 30, a second word line 40, and a third word line.
  • 50 and the fourth word line 60 only require a total of six traces.
  • the number of wire traces can be greatly reduced, thereby reducing the difficulty of design and manufacturing, thereby reducing the manufacturing difficulty of memory. cost.
  • the first word line 30 and the third word line 50 are merged to be electrically connected to the first control terminal 15
  • the fifth word line 35 , the second word line 40 and the fourth word line 60 are combined into a sixth word line 46 that is electrically connected to the second control terminal 16 .
  • the memory includes a plurality of memory cells 10 arranged in an array as shown in Figure 5b. Please refer to Figure 3 for the specific structure of the memory cells 10 shown in Figure 5b.
  • the first electrode 111 of each first transistor 11 is electrically connected to the same first bit line 20
  • the third electrode 121 of each second transistor 12 is electrically connected to the same second bit line 20.
  • Bit lines 70 are electrically connected.
  • the first bit line 20 is used to store data in the first capacitor 115, and the second bit line 70 is used to store data in the second capacitor 125; similarly,
  • the first bit line 20 is used to refresh the stored data of the first capacitor 115
  • the second bit line 70 is used to refresh the stored data of the second capacitor 125 .
  • the reading phase will be explained in detail in the control method later and will not be described again here.
  • each memory cell 10 in the memory only needs to be configured with a total of four wiring lines: the first bit line 20, the second bit line 70, the fifth word line 35 and the sixth word line 46.
  • the number of traces can be further reduced, thereby reducing the design difficulty, reducing the manufacturing difficulty, and thus reducing the manufacturing cost of the memory.
  • the memory further includes: a reference potential line 90 , and the third electrode 121 of the second transistor 12 in each memory unit 10 is electrically connected to the reference potential line 90 .
  • the memory includes a plurality of memory cells 10 arranged in an array as shown in Figure 6b. Please refer to Figure 2 for the specific structure of the memory cells 10 shown in Figure 6b.
  • the first electrode 111 of each first transistor 11 is electrically connected to the same first bit line 20.
  • the third electrode 121 of the second transistor 12 in each memory cell 10 is electrically connected to the reference potential line 90.
  • the reference potential line 90 provides a reference potential Vrefn. During the operation of the memory cell 10 , the reference potential Vrefn is stable.
  • each memory cell 10 in the memory only needs to be configured with a first bit line 20, a first word line 30, a second word line 40, a third word line 50 and a fourth word line.
  • 60 A total of five traces is enough.
  • the number of traces can be reduced, thereby reducing the difficulty of design and manufacturing, thereby reducing the manufacturing cost of the memory unit 10 .
  • the first bit line 20 is used to store data in the first capacitor 115 and the second capacitor 125; similarly, during the refresh phase, the first bit line 20 is used to store data in the first capacitor 115 and the second capacitor 125.
  • the bit line 20 is used to refresh the stored data of the first capacitor 115 and the second capacitor 125, that is, the second transistor 12 will not participate in the work during the writing phase and the refreshing phase, and the second transistor 12 will participate in the reading phase.
  • the reading phase will be explained in detail in the control method later and will not be described again here.
  • the memory includes a row decoder 101 electrically connected to the bit line and a column decoder 102 electrically connected to the word line.
  • an embodiment of the present application provides an electronic device.
  • a schematic diagram of the frame structure of the electronic device is shown in Figure 7.
  • the electronic device includes any memory as provided in the above embodiments.
  • the electronic device includes a smartphone, computer, tablet, artificial intelligence device, wearable device or power bank.
  • the electronic equipment is not limited to the above-mentioned types. Persons skilled in the art can install any of the memories provided by the above embodiments of the present application in different devices according to actual application requirements, thereby obtaining the results of the present application.
  • the electronic device provided by the embodiment provided by the embodiment.
  • control method includes: in the first reading stage, through the second word line 40 to the second transistor 12 of the memory cell 10 to be read.
  • the second main gate 123 applies a first level, and the second level is applied to the first main gate 113 of the first transistor 11 of the memory cell 10 to be read through the first word line 30, so that the first bit line 20 senses
  • the stored data of the first capacitor 115 of the memory unit 10 to be read is measured; the first level is higher than the second level.
  • the level applied to the first main gate 113 of the first transistor 11 is controlled through the first word line 30, and the level applied to the second transistor 12 is controlled through the second word line 40.
  • level of the second main gate 123, and at the same time, data is read by detecting the change in current or voltage on the first bit line 20.
  • the memory control method provided by the embodiment of the present application can be used for any memory provided by the above embodiments.
  • the threshold voltage used to turn on the first transistor 11 will decrease.
  • the second transistor 12 After a higher first level is applied to the second main gate 123, the second transistor 12 will be in a conductive state, and then after a lower second level is applied to the first main gate 113 through the first word line 30, The first transistor 11 will also be in a conductive state, so that a relatively obvious current can be measured on the first bit line 20.
  • the read data is "1"
  • the first bit line 20 senses that it is to be read. Get the data “1” stored in the first capacitor 115 of the memory unit 10 .
  • the first capacitor 115 in the memory unit 10 previously stored data “0”, when a lower second level is applied to the first main gate 113 through the first word line 30, the first transistor 11 will still be in the state of In the closed state, no obvious current can be measured on the first bit line 20. In this case, the read data is judged to be “0”, that is, the first bit line 20 senses the first capacitance of the memory cell 10 to be read. 115 stores data "0".
  • the threshold voltage of the transistor is related to the potential on the auxiliary gate.
  • the potential on the auxiliary gate is higher. The higher, the smaller the threshold voltage; the lower the potential on the auxiliary gate, the larger the threshold voltage.
  • the first transistor 11 , the second transistor 12 , the third transistor 13 and the fourth transistor 14 in the embodiment of the present application are all N-type field effect transistors.
  • FIG. 8 is used to illustrate the back gate effect including the first transistor 11 .
  • the abscissa in FIG. 8 is the voltage applied to the first main gate 113
  • the ordinate is the output current of the first transistor 11 .
  • the level of the voltage on the first auxiliary gate 124 that is, whether the data written by the first transistor 11 is “1” or "0"
  • the level of the voltage on the first auxiliary gate 124 will make a significant difference in the magnitude of the output current of the first transistor 11 (ie, the current measured through the bit line 20).
  • Data can be read from the memory cell 10 by detecting the change in current on the first bit line 20.
  • the transistor writes data "1"
  • the output current of the transistor is larger, so the read data is also "1”.
  • the output current of the transistor is extremely weak, so the data read is also "0".
  • the value of the lower second level may be determined according to the parameters of the transistor and the magnitude of the voltage applied to the first auxiliary gate 124 during the writing operation. Those skilled in the art can determine the most appropriate value of the second level through experiments or simulations to maximize the difference in output current when the first transistor 11 performs read operations in different states to improve read performance.
  • the memory control method further includes: in the second reading stage, applying a third main gate electrode 123 of the second transistor 12 in the memory cell 10 to be read through the second word line 40 .
  • the first level is applied to the first main gate 113 of the first transistor 11 in the memory cell 10 to be read through the first word line 30, so that the first bit line 20 or the second bit line 70 senses The stored data of the second capacitor 125 of the memory unit 10 is to be read.
  • the second level is applied to the second main gate 123 of the memory cell 10 to be read through the second word line 40, and the second level is applied to the second main gate 123 of the memory cell 10 to be read through the first
  • the word line 30 applies a first level to the first main gate 113 of the memory cell 10 to be read, so that the first bit line 20 senses the stored data of the second capacitor 125 of the memory cell 10 to be read.
  • the first transistor 11 and the second transistor 12 are read transistors.
  • the second level is applied to the second main gate 123 of the memory cell 10 to be read through the second word line 40, and the second level is applied to the second main gate 123 of the memory cell 10 to be read through the first
  • the word line 30 applies a first level to the first main gate 113 of the memory cell 10 to be read, so that the second bit line 70 senses the stored data of the second capacitor 125 of the memory cell 10 to be read.
  • the first transistor 11 and the second transistor 12 are read transistors.
  • the memory control method in the first reading stage includes: passing the sixth word line 46 to the second transistor 12 in the memory cell 10 to be read.
  • the second main gate 123 and the fourth gate 143 of the fourth transistor 14 apply a first level through the fifth word line 35 to the first main gate 113 and the first transistor 11 of the memory cell 10 to be read.
  • the third gate 133 of the third transistor 13 applies a second level, so that the first bit line 20 senses the stored data of the first capacitor 115 of the memory cell 10 to be read; the first level is smaller than that of the fourth transistor 14
  • the threshold voltage, the second level is less than the threshold voltage of the third transistor 13 .
  • the control method also includes: in the second read stage, applying a third main gate 123 of the second transistor 12 and the fourth gate 143 of the fourth transistor 14 in the memory cell 10 to be read through the sixth word line 46 .
  • Two levels the first level is applied to the first main gate 113 of the first transistor 11 and the third gate 133 of the third transistor 13 in the memory cell 10 to be read through the fifth word line 35, so that the second The bit line 70 senses the stored data of the second capacitor 125 of the memory cell 10 to be read; the first level is less than the threshold voltage of the third transistor 13 , and the second level is less than the threshold voltage of the fourth transistor 14 .
  • the reading is not affected.
  • the first capacitor 115 and the second capacitor 125 store data.
  • the memory control method further includes: in the first writing stage, applying a first main gate 113 of the first transistor 11 in the memory unit 10 to be written through the first word line 30 . three levels to turn on the first transistor 11, and apply a fourth level to the third gate 133 of the third transistor 13 in the memory cell 10 to be written through the third word line 50 to turn on the third transistor 13,
  • the storage signal is transmitted to the first capacitor 115 of the memory cell 10 to be written through the first bit line 20, so that the storage signal is written into the first capacitor 115 of the memory cell 10 to be written as storage data.
  • the fifth level is applied to the second main gate 123 of the second transistor 12 in the memory cell 10 to be written through the second word line 40 so that the second transistor 12 is turned on.
  • the line 60 applies a sixth level to the fourth gate 143 of the fourth transistor 14 in the memory cell 10 to be written, so that the fourth transistor 14 is turned on.
  • the capacitor 125 transmits the storage signal, so that the storage signal is written into the second capacitor 125 to be written into the memory unit 10 as storage data.
  • the first transistor 11 and the third transistor 13 can be controlled to turn on, and the first bit line 20 can be used to write to the memory cell 10 to be written.
  • the first capacitor 115 transmits the storage signal, so that the storage signal is written into the first capacitor 115 to be written into the memory unit 10 as storage data.
  • the first transistor 11 and the third transistor 13 are write transistors.
  • the storage signal can be written by controlling the turn-on of the second transistor 12 and the fourth transistor 14 and transmitting the storage signal through the second capacitor 125 of the memory cell 10 to be written through the second bit line 70. into the second capacitor 125 of the memory unit 10 to be written as the stored data.
  • the second transistor 12 and the fourth transistor 14 are write transistors.
  • the control method further includes: in the first writing stage, using the first control terminal 15 to combine the first word line 30 and the third word line 50 to form a fifth word.
  • the line 35 applies a turn-on level (at this time, the third level is equal to the fourth level), so that the first transistor 11 and the third transistor 13 are turned on, and the first bit of the memory cell 10 to be written is supplied to the first bit line 20 through the first bit line 20 .
  • a capacitor 115 transmits a storage signal, so that the storage signal is written into the first capacitor 115 of the memory unit 10 to be written as storage data.
  • the first transistor 11 and the third transistor 13 are write transistors.
  • the turn-on level is applied to the sixth word line 46 formed by combining the second word line 40 and the fourth word line 60 through the second control terminal 16 (at this time, the fifth level is equal to the sixth word line 46 ). level), so that the second transistor 12 and the fourth transistor 14 are turned on, and the storage signal is transmitted to the second capacitor 125 of the memory cell 10 to be written through the second bit line 70, so as to write the storage signal into the memory to be written.
  • the second capacitor 125 of unit 10 serves as storage data.
  • the second transistor 12 and the fourth transistor 14 are write transistors.
  • the memory control method further includes: in the first writing stage, through the first word line 30 to the first transistor in the memory unit 10 to be written.
  • a third level is applied to the first main gate 113 of 11 to turn on the first transistor 11, and a fourth voltage is applied to the third gate 133 of the third transistor 13 in the memory cell 10 to be written through the third word line 50. level so that the third transistor 13 is turned on, and the storage signal is transmitted to the first capacitor 115 of the memory unit 10 to be written through the first bit line 20, so as to write the storage signal to the first capacitor 115 of the memory unit 10 to be written as Storing data.
  • a third level is applied to the first main gate 113 of the first transistor 11 in the memory cell 10 to be written through the first word line 30 so that the first transistor 11 is turned on.
  • the line 60 applies a sixth level to the fourth gate 143 of the fourth transistor 14 in the memory cell 10 to be written, so that the fourth transistor 14 is turned on.
  • the capacitor 125 transmits the storage signal, so that the storage signal is written into the second capacitor 125 to be written into the memory unit 10 as storage data.
  • the first transistor 11 and the third transistor 13 can be controlled to turn on, and the first bit line 20 can be used to write to the memory cell 10 to be written.
  • the first capacitor 115 transmits the storage signal, so that the storage signal is written into the first capacitor 115 to be written into the memory unit 10 as storage data.
  • the first transistor 11 and the third transistor 13 are write transistors.
  • the first transistor 11 and the fourth transistor 14 can be controlled to turn on, and the storage signal can be transmitted to the second capacitor 125 of the memory cell 10 to be written through the first bit line 20, so that the storage signal can be Write the second capacitor 125 of the memory cell 10 to be written as the storage data.
  • the first transistor 11 and the fourth transistor 14 are write transistors.
  • the second transistor 12 does not participate in the first writing stage and the second writing stage of the memory unit 10, that is, the second transistor 12 is only a read transistor.
  • the second main gate 123 of the second transistor 12 is configured to be electrically connected to the second word line 40
  • the third gate 133 of the third transistor 13 is configured to be electrically connected to the third word line 50
  • the fourth gate electrode 143 of 14 is configured to be electrically connected to the fourth word line 60, so as to avoid the electrical connection between the read word line and the electrodes of each transistor except the gate electrode among the above word lines, and further When the transistor is in a conductive state, the electrical connection between the read word line and the first bit line 20 can be avoided, and the crosstalk between the read word line and the first bit line 20 can be avoided, thereby ensuring the stability of the memory cell 10 . Work.
  • the first auxiliary gate 114 of the first transistor 11 is set as an electrode of the first capacitor 115 and the second auxiliary gate 124 of the second transistor 12 is set as the second capacitor 125 An electrode of , so that the memory unit 10 has two capacitors for storing data, so that the memory unit 10 can store two bits of data.
  • steps, measures, and solutions in the various operations, methods, and processes that have been discussed in this application can be alternated, changed, combined, or deleted.
  • steps, measures, and solutions in the various operations, methods, and processes that have been discussed in this application can also be alternated, changed, rearranged, decomposed, combined, or deleted.
  • steps, measures, and solutions in the prior art with various operations, methods, and processes disclosed in this application can also be replaced, changed, rearranged, decomposed, combined, or deleted.
  • first and second are used for descriptive purposes only and shall not be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of this application, unless otherwise stated, “plurality” means two or more.
  • connection should be understood in a broad sense.
  • connection or integral connection; it can be directly connected, or indirectly connected through an intermediary, or it can be internal connection between two components.
  • connection or integral connection; it can be directly connected, or indirectly connected through an intermediary, or it can be internal connection between two components.

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Abstract

本申请实施例提供了一种存储单元、存储器及其控制方法。在本申请实施例提供的存储单元中，由于第一晶体管的第一电极被配置为与第一位线电连接以及第一主栅极被配置为与第一字线电连接、第二晶体管的第二主栅极被配置为与第二字线电连接、第三晶体管的第三栅极被配置为与第三字线电连接和第四晶体管的第四栅极被配置为与第四字线电连接，从而能够避免上述字线中读取用的字线与各晶体管的除栅极之外的电极出现电连接的情况，进而在晶体管处于导通的状态下，能够避免读取用的字线与第一位线电连接，能够避免读取用的字线和第一位线的串扰，进而能够保障存储单元的工作。

Description

存储单元、存储器及其控制方法 技术领域
本申请涉及半导体技术领域，具体而言，本申请涉及一种存储单元、存储器及其控制方法。
背景技术
主流的DRAM(Dynamic Random Access Memory，动态随机存取存储器)的存储单元通常为1T(Transistor，晶体管)1C(Capacitor，电容器)结构。
对于1T1C结构的DRAM而言，为了降低刷新率以及保障读取准确度，电容的电容值需要足够大，这会使得DRAM的结构不紧凑、集成度较低。目前，部分厂商采用2T结构的存储单元，以避免在存储单元中设置电容器。
但是，目前2T结构的DRAM中，在工作过程中，由于读取用的字线、位线分别与同一个晶体管的源极、漏极电连接，从而导致字线和位线容易发生串扰的问题。
发明内容
本申请提出一种存储单元、存储器及其控制方法，至少用以改善背景技术中的不足。
第一个方面，本申请实施例提供了一种存储单元，包括：
第一晶体管，为写晶体管，包括：被配置为与第一位线电连接的第一电极、第二电极、被配置为与第一字线电连接的第一主栅极、以及第一辅助栅极；
第二晶体管，为读晶体管，包括：第四电极、被配置为与第二字线电连接的第二主栅极、以及第二辅助栅极；
第三晶体管，为写晶体管，包括：第五电极、与第一辅助栅极电连接的第六电极、以及被配置为与第三字线电连接的第三栅极；
第四晶体管，为写晶体管，包括：第七电极、与第二辅助栅极电连接的第八电极、以及被配置为与第四字线电连接的第四栅极；第七电极、第二电极、第四电极和第五电极均与第一节点电连接；
第一电容和第二电容，第一电容的一电极为第一辅助栅极，第二电容的一电极为第二辅助栅极。
第二个方面，本申请实施例提供了一种存储器，包括：多条第一位线、多条第一字线、多条第二字线、多条第三字线、多条第四字线和多个存储单元；
第一位线在衬底上沿第一方向延伸，第一字线、第二字线、第三字线和第四字线均在衬底上沿第二方向延伸，第二方向垂直于第一方向；
存储单元包括：为写晶体管的第一晶体管、为读晶体管的第二晶体管、为写晶体管的第三晶体管、为写晶体管的第四晶体管、第一电容和第二电容；
第一晶体管的第一电极与第一位线电连接，第一晶体管的第一主栅极与第一字线电连接；第二晶体管的第二主栅极与第二字线电连接；第三晶体管的第三栅极与第三字线电连接；第四晶体管的第四栅极与第四字线电连接；第一电容的一电极为第一晶体管的第一辅助栅极，第二电容的一电极为第二晶体管的第二辅助栅极。
第二个方面，本申请实施例提供了一种存储器的控制方法，包括：
在第一读取阶段，通过第二字线向待读取存储单元的第二晶体管的第二主栅极施加第一电平，通过第一字线向待读取存储单元的第一晶体管的第一主栅极施加第二电平，以使得第一位线感测待读取存储单元的第一电容的存储数据；第一电平高于第二电平。
本申请实施例提供的技术方案带来的有益技术效果包括：
在本申请实施例提供的存储单元中，由于第一晶体管的第一电极被配置为与第一位线电连接以及第一主栅极被配置为与第一字线电连接、第二 晶体管的第二主栅极被配置为与第二字线电连接、第三晶体管的第三栅极被配置为与第三字线电连接和第四晶体管的第四栅极被配置为与第四字线电连接，从而能够避免上述字线中读取用的字线与各晶体管的除栅极之外的电极出现电连接的情况，进而在晶体管处于导通的状态下，能够避免读取用的字线与第一位线电连接，能够避免读取用的字线和第一位线的串扰，进而能够保障存储单元的工作。
而且，本申请实施例提供的存储单元中，通过设置第一晶体管的第一辅助栅极为第一电容的一电极以及第二晶体管的第二辅助栅极为第二电容的一电极，使得存储单元具有两个用于存储数据的电容，使得存储单元能够存储两位数据。
本申请附加的方面和优点将在下面的描述中部分给出，这些将从下面的描述中变得明显，或通过本申请的实践了解到。
附图说明
本申请上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1为本申请实施例提供的一种存储单元的电路原理示意图；
图2为本申请实施例提供的另一种存储单元的电路原理示意图；
图3为本申请实施例提供的又一种存储单元的电路原理示意图；
图4a为本申请实施例的一种存储器的电路原理示意图；
图4b为本申请实施例的图4a所示一种存储器的电路原理示意图中的A处放大示意图；
图5a为本申请实施例的另一种存储器的电路原理示意图；
图5b为本申请实施例的图5a所示另一种存储器的电路原理示意图中的B处放大示意图；
图6a为本申请实施例的又一种存储器的电路原理示意图；
图6b为本申请实施例的图6a所示另一种存储器的电路原理示意图中的C处放大示意图；
图7为本申请实施例提供的一种电子设备的框架结构示意图；
图8为在写入不同的数据时存储器中第一晶体管的转移特性曲线图。
附图标记说明：
10-存储单元；
11-第一晶体管；111-第一电极；112-第二电极；113-第一主栅极；114-第一辅助栅极；115-第一电容；
12-第二晶体管；121-第三电极；122-第四电极；123-第二主栅极；124-第二辅助栅极；125-第二电容；
13-第三晶体管；131-第五电极；132-第六电极；133-第三栅极；
14-第四晶体管；141-第七电极；142-第八电极；143-第四栅极；
15-第一控制端；16-第二控制端；17-第一节点；
20-第一位线；
30-第一字线；40-第二字线；50-第三字线；60-第四字线；35-第五字线；46-第六字线；
70-第二位线；80-参考电位端；90-参考电位线；
101-行解码器；102-列解码器。
具体实施方式
下面结合本申请中的附图描述本申请的实施例。应理解，下面结合附图所阐述的实施方式，是用于解释本申请实施例的技术方案的示例性描述，对本申请实施例的技术方案不构成限制。
本技术领域技术人员可以理解，除非特意声明，这里使用的单数形式“一”、“一个”、“所述”和“该”也可包括复数形式。应该进一步理解的是，本申请的说明书中使用的措辞“包括”是指存在所述特征、整数、步骤、操作、元件和/或组件，但不排除实现为本技术领域所支持其他特征、信息、数据、步骤、操作、元件、组件和/或它们的组合等。应该理解，当我们称一个元件被“连接”或“耦接”到另一元件时，该一个元件可以直接连接或耦接到另一元件，也可以指该一个元件和另一元件通过中间元件建立连接关系。此外，这里使用的“连接”或“耦接”可以包括无线连接或无线耦接。这里使用的术语“和/或”指该术语所限定的项目中 的至少一个，例如“A和/或B”可以实现为“A”，或者实现为“B”，或者实现为“A和B”。
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
首先对本申请涉及的几个名词进行介绍和解释：
2T结构，指的是采用两个晶体管实现数据的存取。具体的，2T结构，包括一个写入晶体管和一个读取晶体管，写入晶体管的栅极电连接写入字线，写入晶体管的源极电连接写入位线，写入晶体管的漏极电连接读取晶体管的栅极，读取晶体管的源极电连接读取字线，读取晶体管的漏极电连接读取位线，数据存储于写入晶体管的漏极和读取晶体管的栅极之间。
目前主流DRAM的存储单元通常为1T1C结构。为了降低1T1C结构的刷新率，降低功耗，以及避免设置电容值较大的电容，部分厂商采用2T结构的存储单元。
对于目前的2T结构，由于读取晶体管的源极电连接读取字线，读取晶体管的漏极电连接读取位线，在写入晶体管的漏极和读取晶体管的栅极之间存储高电平信号时，高电平信号容易导致读取晶体管的栅极开启，即导致读取晶体管导通，在包括阵列排布的2T结构的DRAM中，容易导致读取字线和读取位线发生串扰的问题，进而导致DRAM不能正常工作。
为了降低读取字线和读取位线发生串扰的几率，现有技术往往需要设置单独的控制电路，导致DRAM设计难度的增加，导致DRAM制造成本的增加，而且，控制电路会占用较大的外围面积，从而降低DRAM中单位面积内存储单元的数量。
而且，对于目前的2T结构，数据的存储需要一个写入晶体管，数据的读取需要一个读取晶体管，每个晶体管需要配制一条字线和一条位线，2T结构中存储和读取一位数据，需要两条字线和两条位线，这会增大DRAM中走线的数量，导致DRAM的设计难度、制造难度以及制造成本的增加。
本申请提供的存储单元、存储器及其控制方法，旨在解决现有技术的 如上技术问题。
下面以具体地实施例对本申请的技术方案进行详细说明。
本申请实施例提供了一种存储单元，该存储单元10的电路原理示意图如图1所示，包括：第一晶体管11、第二晶体管12、第三晶体管13和第四晶体管14。
本申请实施例中，如图1所示，为写晶体管的第一晶体管11包括：被配置为与第一位线20电连接的第一电极111、第二电极112、被配置为与第一字线30电连接的第一主栅极113、以及第一辅助栅极114。
如图1所示，为读晶体管的第二晶体管12包括：第四电极122、被配置为与第二字线40电连接的第二主栅极123、以及第二辅助栅极124。
如图1所示，为写晶体管的第三晶体管13包括：第五电极131、与第一辅助栅极114电连接的第六电极132、以及被配置为与第三字线50电连接的第三栅极133，
如图1所示，为写晶体管的第四晶体管14包括：第七电极141、与第二辅助栅极124电连接的第八电极142、以及被配置为与第四字线60电连接的第四栅极143；第七电极141、第二电极112、第四电极122和第五电极131均与第一节点电连接。
本申请实施例中，第一电容115和第二电容125，第一电容115的一电极为第一辅助栅极114，第二电容125的一电极为第二辅助栅极124。
在本申请实施例提供的存储单元10中，由于第一晶体管11的第一电极111被配置为与第一位线20电连接以及第一主栅极113被配置为与第一字线30电连接、第二晶体管12的第二主栅极123被配置为与第二字线40电连接、第三晶体管13的第三栅极133被配置为与第三字线50电连接和第四晶体管14的第四栅极143被配置为与第四字线60电连接，从而能够避免上述字线中读取用的字线与各晶体管的除栅极之外的电极出现电连接的情况，进而在晶体管处于导通的状态下，能够避免读取用的字线与第一位线20电连接，能够避免读取用的字线和第一位线20的串扰，进而能够保障存储单元10的工作。
而且，本申请实施例提供的存储单元10中，通过设置第一晶体管11 的第一辅助栅极114为第一电容115的一电极以及第二晶体管12的第二辅助栅极124为第二电容125的一电极，使得存储单元10具有两个用于存储数据的电容，使得存储单元10能够存储两位数据。
本申请实施例中，如图1-图3所示，存储单元10包括四个晶体管。可选地，第一晶体管11、第二晶体管12、第三晶体管13和第四晶体管14均为MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor，金属-氧化物半导体场效应晶体管)。
本领域技术人员理解的是，对于第一晶体管11而言，第一电极111和第二电极112中的一个为源极，另一个为漏极；对于第二晶体管12而言，第三电极121和第四电极122中的一个为源极，另一个为漏极；对于第三晶体管13而言，第五电极131和第六电极132中的一个为源极，另一个为漏极；对于第四晶体管14而言，第七电极141和第八电极142中的一个为源极，另一个为漏极。可选地，本领域技术人员可以根据各晶体管是N型晶体管还是P型晶体管，来确定各电极是源极还是漏极。
本申请实施例中，第一晶体管11中，第一电极111被配置为与第一位线20电连接，第一主栅极113被配置为与第一字线30电连接，第二电极112与第三晶体管13的第五电极131电连接，第一辅助栅极114与第三晶体管13的第六电极132电连接；第三晶体管13的第三栅极133被配置为与第三字线50电连接，从而通过第一字线30和第三字线50施加的开启电平，能够控制第一晶体管11和第三晶体管13的开启，从而能够通过第一位线20向第一电容115传输存储信号，以将存储信号写入第一电容115作为存储数据。
本申请实施例中，由于第一辅助栅极114存在背栅效应，即第一辅助栅极114的电位会对第一晶体管11的阈值电压产生影响，因此在读取存储数据时用于开启第一晶体管11的电压的数值范围在第一晶体管11存储“1”时的阈值电压以及第一晶体管11存储“0”时的阈值电压之间。
同理，第二晶体管12中，通过控制第一晶体管11或第二晶体管12的开启，以及控制第四晶体管14的开启，能够将存储信号写入第二电容125作为存储数据。具体的控制方法会在后文中进行说明，此处不再赘述。
本申请实施例中，如图1、图2和图3所示，第二电极112、第四电极122、第五电极131和第七电极141电连接于第一节点17，图1中用黑点表示第一节点17。
本申请实施例中，如图1和图2所示，由于第一主栅极113被配置为与第一字线30电连接、第二主栅极123被配置为与第二字线40电连接、第三晶体管13的第三栅极133被配置为与第三字线50电连接以及第四晶体管14的第四栅极143被配置为与第四字线60电连接，能够避免上述字线与各晶体管的源极、漏极电连接，从而在存储单元10的工作过程中，特别是在存储单元10的读取阶段，能够避免第一字线30、第二字线40、第三字线50以及第四字线60中的至少一条字线与第一位线20的电连接，从而能够避免上述各字线和第一位线20之间出现串扰问题，特别是，能够避免读取用的字线与第一位线20出现的串扰问题，进而能够保障存储单元10的工作。
本申请实施例中，第一晶体管11的第一辅助栅极114为背栅极，第一辅助栅极114为第一电容115的一电极。可选地，第一电极111、第二电极112以及其它导电部位中的至少一个形成第一电容115的另一电极，位于两电极之间的膜层、特别是绝缘膜层形成第一电容115的介质层，从而使得第一晶体管11与第一电容115集成一体，从而能够减小存储单元10的体积。
同理，第二晶体管12的第二辅助栅极124为背栅极，复用为第二电容125的一电极，第二晶体管12中的它导电部位中的至少一个形成第二电容125的另一电极，从而使得第二晶体管12与第二电容125集成一体，从而能够进一步减小存储单元10的体积。
本申请实施例中，通过设置包括第一辅助栅极114的第一晶体管11和包括第二辅助栅极124的第二晶体管12，使得存储单元10能够存储两bit(位)数据，从而能够避免设置电容结构，能够减小存储单元10的结构体积，便于存储单元10的集成化发展。
而且，本申请实施例中，如图1和图2所示，存储单元10只需要配 置第一位线20、第一字线30、第二字线40、第三字线50以及第四字线60共五条走线，即可实现两位数据的存取，相较于相关2T结构的存储单元，能够大大减小导线走线的设置数量，从而能够降低设计难度，能够降低制造难度，进而能够降低存储单元10的制造成本。
同时，相较于相关2T结构的存储单元，能够避免设置单独的抗串扰控制电路，从而能够进一步降低设计难度，能够进一步降低制造难度以及制造成本，能够提高存储器中单位面积内存储单元10的数量。
可选地，如图3所示，在本申请的一个实施例中，与第一主栅极113电连接的第一字线30和与第三栅极133电连接的第三字线50被配置为与第一控制端15电连接；与第二主栅极123电连接的第二字线40和与第四栅极143电连接的第四字线60被配置为与第二控制端16电连接。
本申请实施例中，如图3所示，第一字线30和第三字线50被配置为与第一控制端15电连接，也即，第一主栅极113和第三栅极133均与第一控制端15电连接。从而通过第一控制端15能够向第一主栅极113和第三晶体管13的栅极133施加相同的控制电压。
由于第一辅助栅极114存在背栅效应，即第一辅助栅极114的电位会对第一晶体管11的阈值电压产生影响，因此在读取存储数据时用于开启第一晶体管11的电压的数值范围在第一晶体管11存储“1”时的阈值电压以及第一晶体管11存储“0”时的阈值电压之间，从而通过第一控制端15向第一主栅极113和第三的栅极133施加相同的控制电压，且该控制电压小于第三晶体管13的阈值电压时，能够控制第一晶体管11处于开启状态，而第三晶体管13不开启，从而能够实现第一电容115存储数据的读取。
本申请实施例中，如图3所示，第二字线40和第四字线60被配置为与第二控制端16电连接，也即，第二主栅极123和第四栅极143均与第二控制端16电连接。从而通过第二控制端16能够向第二主栅极123和第四栅极143施加相同的控制电压。
同理，通过第二控制端16向第二主栅极123和第四栅极143施加相 同的控制电压，且该控制电压小于第四晶体管14的阈值电压，从而能够控制第二晶体管12开启，而第四晶体管14不开启，从而能够实现第二电容125存储数据的读取。
本申请实施例中，如图3所示，能够进一步减小存储单元10配置的导线走线的数量，从而能够降低设计难度，能够降低制造难度，进而能够降低存储单元10的制造成本。
可选地，在本申请的一个实施例中，第三晶体管13的半导体层和第四晶体管14的半导体层的材料均包括金属氧化物半导体。
本申请实施例中，第三晶体管13的半导体层和第四晶体管14的半导体层的制备材料均包括金属氧化物半导体，从而能够减小第三晶体管13和第四晶体管14的漏电流，由此能够降低存储单元的刷新率，能够降低存储单元的功耗。
可选地，金属氧化物半导体包括IGZO(Indium Gallium Zinc Oxide，氧化铟镓锌)、IWO(Indium Wolfram Oxide，掺钨氧化铟)、ITO(氧化铟锡)、ZnOx(氧化锌)、InOx(氧化铟)、In2O3(三氧化二铟)、InWO(氧化铟钨)、SnO2(二氧化锡)、TiOx(氧化钛)、InSnOx(氧化铟锡)、ZnxOyNz(掺氮氧化锌)、MgxZnyOz(氧化镁锌)、InxZnyOz(氧化铟锌)、InxGayZnzOa(氧化铟镓锌)、ZrxInyZnzOa(氧化锆铟锌)、HfxInyZnzOa(氧化铪铟锌)、SnxInyZnzOa(氧化锡铟锌)、AlxZnO(氧化铝锌)、AlxSnyInzZnaOd(氧化铝锡铟锌)、SixInyZnzOa(氧化硅铟锌)、ZnxSnyOz(氧化锌锡)、AlxZnySnzOa(氧化铝锌锡)、GaxZnySnzOa(氧化镓锌锡)、ZrxZnySnzOa(氧化锆锌锡)以及InGaSiO(氧化铟镓硅)等材料。本领域技术人员可以根据实际情况进行调整，只要保证三晶体管13和第四晶体管14的漏电流能满足要求即可。
应该说明的是，上述各个材料的化学式中，下标字母x、y、z、a以及d表示对应原子的数目。上述材料的粒径均为纳米级。
可选地，本申请实施例中，第三晶体管13和第四晶体管14可以是VGAA(Vertical gate-all-around，垂直全环栅)晶体管，从而能够减小存 储单元10的结构体积，能够提高单位面积内的存储密度。
可选地，如图1所示，在本申请的一个实施例中，第二晶体管12的第三电极121被配置为与第二位线70电连接；第一位线20和第二位线70与不同的控制端连接。
本申请实施例中，如图1所示，第二晶体管12的第三电极121被配置为与第二位线70电连接。在如图1所示存储单元10的写入阶段中，通过控制第二字线40和第四字线60施加的开启电平，能够控制第二晶体管12和第四晶体管14的开启，从而通过第二位线70向第二电容125传输存储信号，以将存储信号写入第二电容125作为存储数据。
本申请实施例中，对于如图1所示存储单元10，在写入阶段中，通过第一晶体管11和第三晶体管13能够实现一位数据的存储，通过第二晶体管12和第四晶体管14能够实现另一位数据的存储，使得存储单元10能够存储两位数据。
本申请实施例中，第一位线20和第二位线70与不同的控制端连接，从而便于单独控制第一电容115以及第二电容125的存储数据，同时便于单独读取第一电容115以及第二电容125中的存储数据。
可选地，如图2所示，在本申请的一个实施例中，第二晶体管12的第三电极121被配置为与参考电位端80电连接。
本申请实施例中，第二晶体管12的第三电极121被配置为与参考电位端80电连接，则可以等价为如图2所示的电路，参考电位端80提供一参考电位Vrefn，在存储单元10的工作过程中，该参考电位Vrefn稳定不变。
本申请实施例，在如图2所示存储单元10的写入阶段中，通过第一字线30和第四字线60施加的开启电平，能够控制第一晶体管11和第四晶体管14的开启，从而通过第一位线20向第二电容125传输存储信号，以将存储信号写入第二电容125作为存储数据。
本申请实施例中，对于如图2所示存储单元10，在写入阶段中，通过第一晶体管11和第三晶体管13能够实现一位数据的存储，通过第一晶 体管11和第四晶体管14能够实现另一位数据的存储，使得存储单元10能够存储两位数据。
本申请实施例中，通过设置第三电极121与参考电位端80电连接，使得第二晶体管12只在读取阶段参与工作，图2所示存储单元10具体的工作原理会在后文的控制方法中进行说明，此处不再赘述。
基于同一发明构思，本申请实施例提供了一种存储器，该存储器的电路原理示意图如图4a所示，包括：多条第一位线20、多条第一字线30、多条第二字线40、多条第三字线50、多条第四字线60和多个存储单元10。
本申请实施例中，第一位线20在衬底上沿第一方向延伸，第一字线30、第二字线40、第三字线50和第四字线60均在衬底上沿第二方向延伸，第二方向垂直于第一方向。
本申请实施例中，存储单元10包括：为写晶体管的第一晶体管11、为读晶体管的第二晶体管12、为写晶体管的第三晶体管13、为写晶体管的第四晶体管14、第一电容115和第二电容125；第一晶体管11的第一电极111与第一位线20电连接，第一晶体管11的第一主栅极113与第一字线30电连接；第二晶体管12的第二主栅极123与第二字线40电连接；第三晶体管13的第三栅极133与第三字线50电连接；第四晶体管14的第四栅极143与第四字线60电连接；第一电容115的一电极为第一晶体管11的第一辅助栅极114，第二电容125的一电极为第二晶体管12的第二辅助栅极124。
可选地，本申请实施例中，存储单元10的结构、原理和技术效果请参阅前述各实施例，在此不再赘述。因此，存储器的原理和技术效果请参阅前述各实施例，在此不再赘述。
可选地，如图4a、图5a和图6a所示，在本申请的一个实施例中，多个存储单元10呈阵列排布；位于同一列的各存储单元10中，各第一晶体管11的第一电极111与同一条第一位线20电连接；位于同一行的各存储单元10中，各第一晶体管11的第一主栅极113与同一条第一字线30 电连接，各第二晶体管12的第二主栅极123与同一条第二字线40电连接，各第三晶体管13的第三栅极133与同一条第三字线50电连接，各第四晶体管14的第四栅极143与同一条第四字线60电连接。
本申请实施例中，如图4a、图5a和图6a所示，多个存储单元10呈阵列排布，形成多个平行于第一方向的存储单元列和多个平行于第二方向的存储单元列。
本申请实施例中，如图4a所示，位于同一列的各存储单元10中，各第一晶体管11的第一电极111与同一条第一位线20电连接。
位于同一行的各存储单元10中，各第一晶体管11的第一主栅极113与同一条第一字线30电连接，各第二晶体管12的第二主栅极123与同一条第二字线40电连接，各第三晶体管13的第三栅极133与同一条第三字线50电连接，各第四晶体管14的第四栅极143与同一条第四字线60电连接。
可选地，如图4a和图5a所示，在本申请的一个实施例中，存储器还包括：多条第二位线70，第二位线70在衬底上沿第一方向延伸；位于同一列的各存储单元10中，各第二晶体管12的第三电极121与同一条第二位线70电连接。
本申请实施例中，如图4a所示，存储器包括多个阵列排布的如图4b所示的存储单元10，图4b所示的存储单元10的具体结构请参照图1。该存储器中，对于位于同一列的各存储单元10，各第一晶体管11的第一电极111与同一条第一位线20电连接，各第二晶体管12的第三电极121与同一条第二位线70电连接。
对于图4a所示的存储器而言，在写入阶段，第一位线20用于向第一电容115中存储数据，第二位线70用于向第二电容125中存储数据；同理，在刷新阶段，第一位线20用于刷新第一电容115的存储数据，第二位线70用于刷新第二电容125的存储数据。关于读取阶段，会在后文控制方法中详细说明，此处不再赘述。
本申请实施例中，如图4a所示，存储器中每个存储单元10只需要配 置第一位线20、第二位线70、第一字线30、第二字线40、第三字线50和第四字线60共计六条走线即可，相较于相关2T结构的DRAM，能够大大减小导线走线的数量，从而能够降低设计难度，能够降低制造难度，进而能够降低存储器的制造成本。
可选地，如图5a所示，在本申请的一个实施例中，位于同一行的各存储单元10中，第一字线30与第三字线50合并为与第一控制端15电连接的第五字线35，第二字线40与第四字线60合并为与第二控制端16电连接的第六字线46。
本申请实施例中，如图5a所示，存储器包括多个阵列排布的如图5b所示的存储单元10，图5b所示的存储单元10的具体结构请参照图3。该存储器中，对于位于同一列的各存储单元10，各第一晶体管11的第一电极111与同一条第一位线20电连接，各第二晶体管12的第三电极121与同一条第二位线70电连接。
对于图5a所示的存储器而言，在写入阶段，第一位线20用于向第一电容115中存储数据，第二位线70用于向第二电容125中存储数据；同理，在刷新阶段，第一位线20用于刷新第一电容115的存储数据，第二位线70用于刷新第二电容125的存储数据。关于读取阶段，会在后文控制方法中详细说明，此处不再赘述。
本申请实施例中，如图5a所示，存储器中每个存储单元10只需要配置第一位线20、第二位线70、第五字线35和第六字线46共计四条走线即可，相较于相关2T结构的DRAM，能够进一步减小走线的数量，从而能够降低设计难度，能够降低制造难度，进而能够降低存储器的制造成本。
可选地，如图5a所示，在本申请的一个实施例中，存储器还包括：参考电位线90，各存储单元10中第二晶体管12的第三电极121与参考电位线90电连接。
本申请实施例中，如图6a所示，存储器包括多个阵列排布的如图6b所示的存储单元10，图6b所示的存储单元10的具体结构请参照图2。该存储器中，对于位于同一列的各存储单元10，各第一晶体管11的第一电 极111与同一条第一位线20电连接。
如图6a所示，该存储器中，各存储单元10中第二晶体管12的第三电极121与参考电位线90电连接，参考电位线90提供一参考电位Vrefn，在存储单元10的工作过程中，该参考电位Vrefn稳定不变。
本申请实施例中，如图6a所示，存储器中每个存储单元10只需要配置第一位线20、第一字线30、第二字线40、第三字线50和第四字线60共计五条走线即可，相较于相关2T结构的DRAM，能够减小走线的数量，从而能够降低设计难度，能够降低制造难度，进而能够降低存储单元10的制造成本。
本申请实施例中，对于图6a所示的存储器而言，在写入阶段，第一位线20用于向第一电容115和第二电容125中存储数据；同理，在刷新阶段，第一位线20用于刷新第一电容115和第二电容125的存储数据，即在写入阶段和刷新阶段，第二晶体管12均不会参与工作，第二晶体管12在读取阶段参与工作。关于读取阶段，会在后文控制方法中详细说明，此处不再赘述。
本申请实施例中，如图4a-图6a所示，存储器均包括与位线电连接的行解码器101和与字线电连接的列解码器102。
基于同一发明构思，本申请实施例提供了一种电子设备，该电子设备的框架结构示意图如图7所示，该电子设备，包括：如上述各个实施例所提供的任一存储器。
本申请实施例中，由于电子设备采用了前述各实施例提供的任一种存储器，其原理和技术效果请参阅前述各实施例，在此不再赘述。
可选地，电子设备包括智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源。
应该说明的是，电子设备并不局限于上述几种，本领域技术人员可以根据实际的应用需求，在不同的设备中设置本申请上述各个实施例所提供的任一种存储器，从而得到本申请实施例所提供的电子设备。
本技术领域技术人员可以理解，本申请实施例提供的电子设备可以为 所需的目的而专门设计和制造，或者也可以包括通用计算机中的已知设备。这些设备具有上述各个实施例所提供的任一存储器。
基于同一发明构思，本申请实施例提供了一种存储器的控制方法，该控制方法包括：在第一读取阶段，通过第二字线40向待读取存储单元10的第二晶体管12的第二主栅极123施加第一电平，通过第一字线30向待读取存储单元10的第一晶体管11的第一主栅极113施加第二电平，以使得第一位线20感测待读取存储单元10的第一电容115的存储数据；第一电平高于第二电平。
本申请实施例中，在存储器的读取阶段，通过第一字线30控制施加于第一晶体管11的第一主栅极113的电平，通过第二字线40控制施加于第二晶体管12的第二主栅极123电平，同时，通过检测第一位线20上电流或电压的变化大小，实现数据的读取。
可选地，本申请实施例提供了的存储器的控制方法，用于上述各个实施例所提供的任一存储器。
本申请实施例，对于图4a所示的存储器而言，以检测电连接于一个存储单元10的第一位线20的电流变化来说明读取阶段的具体原理。
具体的，当存储单元10中第一电容115之前存储的是数据“1”时，由于背栅效应，用于开启第一晶体管11的阈值电压会减小，当通过第二字线40向第二主栅极123施加较高的第一电平后，第二晶体管12会处于导通状态，然后通过第一字线30向第一主栅极113施加于较低的第二电平后，第一晶体管11也会处于导通状态，从而能在第一位线20测得较为明显的电流，此种情况判断读取的数据为“1”，也即第一位线20感测待读取存储单元10的第一电容115存储的数据“1”。
如果存储单元10中第一电容115之前存储的是数据“0”，当通过第一字线30向第一主栅极113施加于较低的第二电平后，第一晶体管11还会处于关闭状态，从而不能在第一位线20测得较为明显的电流，此种情况判断读取的数据为“0”，也即第一位线20感测待读取存储单元10的第一电容115存储的数据“0”。
同理，可以根据第二位线70感测待读取存储单元10的第二电容125存储的数据是“1”还是“0”。
需要说明的是，晶体管的阈值电压的大小和辅助栅极上电位的大小相关，可选地，对于N型场效应晶体管(晶体管导通时载流子为电子)，辅助栅极上的电位越高，阈值电压越小；辅助栅极上的电位越低，阈值电压越大。可选地，本申请实施例中的第一晶体管11、第二晶体管12、第三晶体管13和第四晶体管14均为N型场效应晶体管。
可选地，本申请实施例中，以图8来说明包括第一晶体管11的背栅效应。图8中的横坐标为施加在第一主栅极113上的电压，纵坐标为第一晶体管11的输出电流。当施加在第一主栅极113的电压为某一特定值(图8中虚线位置)时，第一辅助栅极124上电压的高低(即第一晶体管11写入的数据是“1”还是“0”)会使第一晶体管11的输出电流(即通过位线20所测的电流)的大小具有显著的差别。通过检测第一位线20上电流的变化即可实现将数据从存储单元10中读出，当晶体管写入数据“1”时，晶体管的输出电流较大，因此读取的数据也是“1”；当晶体管写入的数据是“0”时，晶体管的输出电流极为微弱，因此读取的数据也是“0”。
本申请实施例中，较低的第二电平的数值可根据晶体管的参数以及在进行写操作时施加给第一辅助栅极124上电压的大小确定。本领域技术人员可通过实验或者模拟的方法确定最合适的第二电平的值，以使第一晶体管11在不同的状态下进行读操作时输出电流的差异最大，以提高读取性能。
在本申请的一个实施例中，存储器的控制方法还包括：在第二读取阶段，通过第二字线40向待读取存储单元10中第二晶体管12的第二主栅极123施加第二电平，通过第一字线30向待读取存储单元10中第一晶体管11的第一主栅极113施加第一电平，以使得第一位线20或第二位线70感测待读取存储单元10的第二电容125的存储数据。
可选地，对于图4a所示的存储器而言，在第二读取阶段，通过第二字线40向待读取存储单元10的第二主栅极123施加第二电平，通过第一字线30向待读取存储单元10的第一主栅极113施加第一电平，以使得第一 位线20感测待读取存储单元10的第二电容125的存储数据。在第二读取阶段，第一晶体管11和第二晶体管12为读晶体管。
可选地，对于图6a所示的存储器而言，在第二读取阶段，通过第二字线40向待读取存储单元10的第二主栅极123施加第二电平，通过第一字线30向待读取存储单元10的第一主栅极113施加第一电平，以使得第二位线70感测待读取存储单元10的第二电容125的存储数据。在第二读取阶段，第一晶体管11和第二晶体管12为读晶体管。
在本申请的一个实施例中，对于图5a所示的存储器而言，存储器的控制方法中在第一读取阶段包括：通过第六字线46向待读取存储单元10中第二晶体管12的第二主栅极123和第四晶体管14的第四栅极143施加第一电平，通过第五字线35向待读取存储单元10中第一晶体管11的第一主栅极113和第三晶体管13的第三栅极133施加第二电平，以使得第一位线20感测待读取存储单元10的第一电容115的存储数据；第一电平小于第四晶体管14的阈值电压，第二电平小于第三晶体管13的阈值电压。
控制方法还包括：在第二读取阶段，通过第六字线46向待读取存储单元10中第二晶体管12的第二主栅极123和第四晶体管14的第四栅极143施加第二电平，通过第五字线35向待读取存储单元10中第一晶体管11的第一主栅极113和第三晶体管13的第三栅极133施加第一电平，以使得第二位线70感测待读取存储单元10的第二电容125的存储数据；第一电平小于第三晶体管13的阈值电压，第二电平小于第四晶体管14的阈值电压。
本申请实施例中，对于图5a所示的存储器而言，在第一读取阶段和第二读取阶段，由于第三晶体管13和第四晶体管14均不会被开启，从而不影响读取第一电容115、第二电容125的存储数据。
在本申请的一个实施例中，存储器的控制方法还包括：在第一写入阶段，通过第一字线30向待写入存储单元10中第一晶体管11的第一主栅极113施加第三电平以使得第一晶体管11导通，通过第三字线50向待写入存储单元10中第三晶体管13的第三栅极133施加第四电平以使得第三 晶体管13导通，通过第一位线20向待写入存储单元10的第一电容115传输存储信号，以将存储信号写入待写入存储单元10的第一电容115作为存储数据。
在第二写入阶段，通过第二字线40向待写入存储单元10中第二晶体管12的第二主栅极123施加第五电平以使得第二晶体管12导通，通过第四字线60向待写入存储单元10中第四晶体管14的第四栅极143施加第六电平以使得第四晶体管14导通，通过第二位线70向待写入存储单元10的第二电容125传输存储信号，以将存储信号写入待写入存储单元10的第二电容125作为存储数据。
可选地，对于图4a所示的存储器而言，在第一写入阶段，可以通过控制第一晶体管11和第三晶体管13的开启，并通过第一位线20向待写入存储单元10的第一电容115传输存储信号，以将存储信号写入待写入存储单元10的第一电容115作为存储数据。在第一写入阶段，第一晶体管11和第三晶体管13为写晶体管。
以及，在第二写入阶段可以通过控制第二晶体管12和第四晶体管14的开启，并通过第二位线70待写入存储单元10的第二电容125传输存储信号，以将存储信号写入待写入存储单元10的第二电容125作为存储数据。在第二写入阶段，第二晶体管12和第四晶体管14为写晶体管。
可选地，对于图5a所示的存储器而言，控制方法还包括：在第一写入阶段，通过第一控制端15向第一字线30与第三字线50合并形成的第五字线35施加开启电平(此时，第三电平等于第四电平)，以使得第一晶体管11和第三晶体管13导通，通过第一位线20向待写入存储单元10的第一电容115传输存储信号，以将存储信号写入待写入存储单元10的第一电容115作为存储数据。在第一写入阶段，第一晶体管11和第三晶体管13为写晶体管。
以及，在第二写入阶段，通过第二控制端16向第二字线40与第四字线60合并形成的第六字线46施加开启电平(此时，第五电平等于第六电平)，以使得第二晶体管12和第四晶体管14导通，通过第二位线70向 待写入存储单元10的第二电容125传输存储信号，以将存储信号写入待写入存储单元10的第二电容125作为存储数据。在第二写入阶段，第二晶体管12和第四晶体管14为写晶体管。
在本申请的一个实施例中，对于图6a所示的存储器而言，存储器的控制方法还包括：在第一写入阶段，通过第一字线30向待写入存储单元10中第一晶体管11的第一主栅极113施加第三电平以使得第一晶体管11导通，通过第三字线50向待写入存储单元10中第三晶体管13的第三栅极133施加第四电平以使得第三晶体管13导通，通过第一位线20向待写入存储单元10的第一电容115传输存储信号，以将存储信号写入待写入存储单元10的第一电容115作为存储数据。
在第二写入阶段，通过第一字线30向待写入存储单元10中第一晶体管11的第一主栅极113施加第三电平以使得第一晶体管11导通，通过第四字线60向待写入存储单元10中第四晶体管14的第四栅极143施加第六电平以使得第四晶体管14导通，通过第一位线20向待写入存储单元10的第二电容125传输存储信号，以将存储信号写入待写入存储单元10的第二电容125作为存储数据。
可选地，对于图6a所示的存储器而言，在第一写入阶段，可以通过控制第一晶体管11和第三晶体管13的开启，并通过第一位线20向待写入存储单元10的第一电容115传输存储信号，以将存储信号写入待写入存储单元10的第一电容115作为存储数据。在第一写入阶段，第一晶体管11和第三晶体管13为写晶体管。
以及，在第二写入阶段可以通过控制第一晶体管11和第四晶体管14的开启，并通过第一位线20向待写入存储单元10的第二电容125传输存储信号，以将存储信号写入待写入存储单元10的第二电容125作为存储数据。在第二写入阶段，第一晶体管11和第四晶体管14为写晶体管。
本申请实施例中，对于图6a所示的存储器而言，第二晶体管12并不参与存储单元10的第一写入阶段和第二写入阶段，即第二晶体管12只为读晶体管。
本申请实施例中，控制方法中刷新阶段的具体步骤可以参考写入阶段，此处不再赘述。
应用本申请实施例，至少能够实现如下有益效果：
在本申请实施例提供的存储单元10中，由于第一晶体管11的第一电极111被配置为与第一位线20电连接以及第一主栅极113被配置为与第一字线30电连接、第二晶体管12的第二主栅极123被配置为与第二字线40电连接、第三晶体管13的第三栅极133被配置为与第三字线50电连接和第四晶体管14的第四栅极143被配置为与第四字线60电连接，从而能够避免上述字线中读取用的字线与各晶体管的除栅极之外的电极出现电连接的情况，进而在晶体管处于导通的状态下，能够避免读取用的字线与第一位线20电连接，能够避免读取用的字线和第一位线20的串扰，进而能够保障存储单元10的工作。
在本申请实施例提供的存储单元10中，通过设置第一晶体管11的第一辅助栅极114为第一电容115的一电极以及第二晶体管12的第二辅助栅极124为第二电容125的一电极，使得存储单元10具有两个用于存储数据的电容，使得存储单元10能够存储两位数据。
本技术领域技术人员可以理解，本申请中已经讨论过的各种操作、方法、流程中的步骤、措施、方案可以被交替、更改、组合或删除。进一步地，具有本申请中已经讨论过的各种操作、方法、流程中的其他步骤、措施、方案也可以被交替、更改、重排、分解、组合或删除。进一步地，现有技术中的具有与本申请中公开的各种操作、方法、流程中的步骤、措施、方案也可以被交替、更改、重排、分解、组合或删除。
在本申请的描述中，词语“中心”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方向或位置关系，为基于附图所示的示例性的方向或位置关系，是为了便于描述或简化描述本申请的实施例，而不是指示或暗示所指的装置或部件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示 相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述仅是本申请的部分实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请的方案技术构思的前提下，采用基于本申请技术思想的其他类似实施手段，同样属于本申请实施例的保护范畴。

Claims (15)

  1. 一种存储单元，其特征在于，包括：
    第一晶体管，为写晶体管，包括：被配置为与第一位线电连接的第一电极、第二电极、被配置为与第一字线电连接的第一主栅极、以及第一辅助栅极；
    第二晶体管，为读晶体管，包括：第四电极、被配置为与第二字线电连接的第二主栅极、以及第二辅助栅极；
    第三晶体管，为写晶体管，包括：第五电极、与所述第一辅助栅极电连接的第六电极、以及被配置为与第三字线电连接的第三栅极；
    第四晶体管，为写晶体管，包括：第七电极、与所述第二辅助栅极电连接的第八电极、以及被配置为与第四字线电连接的第四栅极；所述第七电极、所述第二电极、所述第四电极和所述第五电极均与第一节点电连接；
    第一电容和第二电容，所述第一电容的一电极为所述第一辅助栅极，所述第二电容的一电极为所述第二辅助栅极。
  2. 根据权利要求1所述的存储单元，其特征在于，与所述第一主栅极电连接的所述第一字线和与所述第三栅极电连接的所述第三字线被配置为与第一控制端电连接；
    与所述第二主栅极电连接的所述第二字线和与所述第四栅极电连接的所述第四字线被配置为与第二控制端电连接。
  3. 根据权利要求1所述的存储单元，其特征在于，所述第三晶体管的半导体层和所述第四晶体管的半导体层的材料均包括金属氧化物半导体。
  4. 根据权利要求1所述的存储单元，其特征在于，所述第二晶体管的第三电极被配置为与第二位线电连接；所述第一位线和所述第二位线与 不同的控制端连接。
  5. 根据权利要求1所述的存储单元，其特征在于，所述第二晶体管的第三电极被配置为与参考电位端电连接。
  6. 一种存储器，其特征在于，包括：多条第一位线、多条第一字线、多条第二字线、多条第三字线、多条第四字线和多个存储单元；
    所述第一位线在衬底上沿第一方向延伸，所述第一字线、所述第二字线、所述第三字线和所述第四字线均在衬底上沿第二方向延伸，所述第二方向垂直于所述第一方向；
    所述存储单元包括：为写晶体管的第一晶体管、为读晶体管的第二晶体管、为写晶体管的第三晶体管、为写晶体管的第四晶体管、第一电容和第二电容；
    所述第一晶体管的第一电极与所述第一位线电连接，所述第一晶体管的第一主栅极与所述第一字线电连接；所述第二晶体管的第二主栅极与所述第二字线电连接；所述第三晶体管的第三栅极与所述第三字线电连接；所述第四晶体管的第四栅极与所述第四字线电连接；所述第一电容的一电极为所述第一晶体管的第一辅助栅极，所述第二电容的一电极为所述第二晶体管的第二辅助栅极。
  7. 根据权利要求6所述的存储器，其特征在于，多个所述存储单元呈阵列排布；
    位于同一列的各所述存储单元中，各所述第一晶体管的第一电极与同一条所述第一位线电连接；
    位于同一行的各所述存储单元中，各所述第一晶体管的第一主栅极与同一条所述第一字线电连接，各所述第二晶体管的第二主栅极与同一条所述第二字线电连接，各所述第三晶体管的第三栅极与同一条所述第三字线电连接，各所述第四晶体管的第四栅极与同一条所述第四字线电连接。
  8. 根据权利要求7所述的存储器，其特征在于，还包括：多条第二位线，所述第二位线在衬底上沿所述第一方向延伸；
    位于同一列的各所述存储单元中，各所述第二晶体管的第三电极与同一条所述第二位线电连接。
  9. 根据权利要求8所述的存储器，其特征在于，位于同一行的各所述存储单元中，所述第一字线与所述第三字线合并为与第一控制端电连接的第五字线，所述第二字线与所述第四字线合并为与第二控制端电连接的第六字线。
  10. 根据权利要求6所述的存储器，其特征在于，还包括：参考电位线，各所述存储单元中所述第二晶体管的第三电极与所述参考电位线电连接。
  11. 一种存储器的控制方法，其特征在于，包括：
    在第一读取阶段，通过第二字线向待读取存储单元的第二晶体管的第二主栅极施加第一电平，通过第一字线向所述待读取存储单元的第一晶体管的第一主栅极施加第二电平，以使得第一位线感测所述待读取存储单元的第一电容的存储数据；所述第一电平高于所述第二电平。
  12. 根据权利要求11所述的控制方法，其特征在于，还包括：
    在第二读取阶段，通过所述第二字线向所述待读取存储单元中所述第二晶体管的所述第二主栅极施加所述第二电平，通过所述第一字线向所述待读取存储单元中所述第一晶体管的所述第一主栅极施加所述第一电平，以使得所述第一位线或第二位线感测所述待读取存储单元的第二电容的存储数据。
  13. 根据权利要求11所述的控制方法，其特征在于，所述在第一读取阶段，包括：通过第六字线向所述待读取存储单元中所述第二晶体管的所述第二主栅极和第四晶体管的第四栅极施加所述第一电平，通过第五字线向所述待读取存储单元中所述第一晶体管的所述第一主栅极和第三晶体管的第三栅极施加所述第二电平，以使得所述第一位线感测所述待读取存储单元的所述第一电容的存储数据；所述第一电平小于所述第四晶体管的阈值电压，所述第二电平小于所述第三晶体管的阈值电压；
    所述控制方法还包括：在第二读取阶段，通过所述第六字线向所述待读取存储单元中所述第二晶体管的所述第二主栅极和所述第四晶体管的第四栅极施加所述第二电平，通过所述第五字线向所述待读取存储单元中所述第一晶体管的所述第一主栅极和所述第三晶体管的第三栅极施加所述第一电平，以使得第二位线感测所述待读取存储单元的第二电容的存储数据；所述第一电平小于所述第三晶体管的阈值电压，所述第二电平小于所述第四晶体管的阈值电压。
  14. 根据权利要求11所述的控制方法，其特征在于，还包括：
    在第一写入阶段，通过第一字线向待写入存储单元中所述第一晶体管的第一主栅极施加第三电平以使得所述第一晶体管导通，通过第三字线向所述待写入存储单元中第三晶体管的第三栅极施加第四电平以使得所述第三晶体管导通，通过第一位线向所述待写入存储单元的第一电容传输存储信号，以将存储信号写入所述待写入存储单元的所述第一电容作为存储数据；
    在第二写入阶段，通过第二字线向所述待写入存储单元中所述第二晶体管的第二主栅极施加第五电平以使得所述第二晶体管导通，通过第四字线向所述待写入存储单元中第四晶体管的第四栅极施加第六电平以使得所述第四晶体管导通，通过第二位线向所述待写入存储单元的第二电容传输存储信号，以将存储信号写入所述待写入存储单元的所述第二电容作为存储数据。
  15. 根据权利要求11所述的控制方法，其特征在于，还包括：
    在第一写入阶段，通过第一字线向待写入存储单元中所述第一晶体管的第一主栅极施加第三电平以使得第一晶体管导通，通过第三字线向所述待写入存储单元中第三晶体管的第三栅极施加第四电平以使得所述第三晶体管导通，通过第一位线向所述待写入存储单元的第一电容传输存储信号，以将存储信号写入所述待写入存储单元的所述第一电容作为存储数据；
    在第二写入阶段，通过第一字线向待写入存储单元中所述第一晶体管的第一主栅极施加第三电平以使得所述第一晶体管导通，通过第四字线向所述待写入存储单元中第四晶体管的第四栅极施加第六电平以使得所述第四晶体管导通，通过第一位线向所述待写入存储单元的第二电容传输存储信号，以将存储信号写入所述待写入存储单元的第二电容作为存储数据。
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