WO2022261827A1 - 存储器及其制造方法 - Google Patents

存储器及其制造方法 Download PDF

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Publication number
WO2022261827A1
WO2022261827A1 PCT/CN2021/100146 CN2021100146W WO2022261827A1 WO 2022261827 A1 WO2022261827 A1 WO 2022261827A1 CN 2021100146 W CN2021100146 W CN 2021100146W WO 2022261827 A1 WO2022261827 A1 WO 2022261827A1
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dielectric
oxide semiconductor
gate
semiconductor channel
forming
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PCT/CN2021/100146
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English (en)
French (fr)
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范人士
侯朝昭
许俊豪
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华为技术有限公司
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Priority to PCT/CN2021/100146 priority Critical patent/WO2022261827A1/zh
Priority to CN202180097299.5A priority patent/CN117337621A/zh
Publication of WO2022261827A1 publication Critical patent/WO2022261827A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of electronics, and more particularly to memories and methods of manufacturing the same.
  • CMOS complementary metal-oxide-semiconductor
  • the processing temperature of the conventional CMOS memory based on the silicon channel material often exceeds 1000°C, which makes the manufacturing process of the CMOS memory difficult to cooperate with the back-end process that requires a relatively low temperature (for example, less than 500°C). (back end of line, BEOL) compatible.
  • embodiments of the present disclosure aim to provide a memory, a chip, an electronic component and an electronic device including the chip, and a method of manufacturing the semiconductor device.
  • the semiconductor device may be BEOL compatible.
  • a memory includes a first transistor and a second transistor.
  • the first transistor includes a first oxide semiconductor channel; a first gate coupled to the first word line; a first dielectric located between the first oxide semiconductor channel and the first gate; a first drain coupled to the first bit line; and the first source.
  • the second transistor includes a second oxide semiconductor channel; a second gate coupled to the first source; a second dielectric located between the second oxide semiconductor channel and the second gate; a second drain, coupled to the second bit line; and a second source coupled to the second word line.
  • This memory does not include capacitors as in conventional memories.
  • the memory according to the present disclosure adopts a structure of 2 transistors and does not have a structure of a capacitor (one transistors and zero capacitor, 2T0C) , so there is no need to use a capacitor in a conventional memory cell.
  • Capacitors typically have a larger footprint than transistors. Therefore, the memory according to the present disclosure can significantly reduce the size of the memory and increase the integration degree of the chip.
  • the manufacturing process of the memory according to the present disclosure can be compatible with BEOL, and the memory according to the present disclosure can be arranged above a logic device, such as a CMOS-based logic device In the upper interconnection layer, thereby further reducing the occupied area of the memory and improving the integration level of the chip.
  • a conventional memory based on 1T1C architecture stores data by using current to charge and discharge a capacitor, which usually consumes considerable energy.
  • the memory according to the present disclosure stores data in the form of voltage, that is, the stored data is characterized by the voltage of the node between the first source and the second gate, which significantly reduces the power consumption of the memory .
  • transistors in conventional memories usually use silicon material as a conduction channel, and even when the transistor is turned off, there is a certain degree of leakage current. Due to the existence of leakage current, a conventional memory based on the 1T1C architecture usually needs to refresh each storage unit of the memory at intervals, such as 64ms, even if some storage units are not selected for reading or writing operations. Refreshing ensures that the data of the storage unit of the memory is not lost or does not generate errors, but the refreshing operation also consumes relatively much energy. According to the two transistors of the memory cell based on the 2TOC architecture of the present disclosure, a channel of OS material is used.
  • the transistor using OS material as a conductive channel has excellent driving performance, And has a very small leakage current.
  • the stored data can thus be maintained for a relatively long time.
  • the refresh frequency of the memory based on the 2TOC architecture according to the present disclosure is much lower than that of the conventional memory based on the 1T1C architecture, and the power supply voltage can be further reduced, thus further reducing the power consumption of the memory.
  • the first transistor further includes a third dielectric, the third dielectric and the first dielectric are located on opposite sides of the first oxide semiconductor channel; and a third gate, coupled to the first gate line, the third dielectric is located between the third gate and the first oxide semiconductor channel.
  • double gates that is, two gates located on both sides of the first oxide semiconductor channel, the first oxide semiconductor channel can be more effectively controlled to be turned on or off, and the leakage current can be further reduced, thereby further reducing the memory power consumption.
  • the second transistor further includes a fourth dielectric, the fourth dielectric and the second dielectric are located on opposite sides of the second oxide semiconductor channel; and a fourth gate is coupled to the first source electrode, and the fourth dielectric is located between the fourth gate and the second oxide semiconductor channel.
  • double gates that is, two gates located on both sides of the second oxide semiconductor channel, it is possible to more effectively control the turn-on or turn-off of the second oxide semiconductor channel, and further reduce the leakage current, thereby further reducing the memory power consumption.
  • the first transistor and the second transistor are fin transistors.
  • the first dielectric covers the upper surface and both side surfaces of a part of the first oxide semiconductor channel
  • the first gate covers the upper surface and both side surfaces of the first dielectric.
  • the second dielectric covers the upper surface and both side surfaces of a part of the second oxide semiconductor channel
  • the second gate covers the upper surface and both side surfaces of the second dielectric.
  • the first dielectric surrounds at least a part of side surfaces of the first oxide semiconductor channel; and the first gate surrounds the first dielectric.
  • a gate-all-around transistor may be formed by forming a first dielectric to surround at least a portion of a side surface of the first oxide semiconductor channel and surrounding the first gate by the first dielectric. Compared with the double-gate transistor, the gate-around transistor can further enhance the control of turning on or off the first oxide semiconductor channel, thereby further reducing the leakage current and further reducing the power consumption of the memory.
  • the second dielectric surrounds at least a part of the side surface of the second oxide semiconductor channel; and the second gate surrounds the second dielectric.
  • the gate-around transistor can further enhance the control of turning on or off the second oxide semiconductor channel, thereby further reducing the leakage current and further reducing the power consumption of the memory.
  • the first source and the second gate are integrally formed as a single region.
  • process steps can be saved and memory manufacturing costs can be reduced.
  • the first oxide semiconductor channel is configured to extend along the first direction; the first gate is configured to extend along the first direction between the first source and the first drain; The first dielectric covers the lower surface and both side surfaces of the first gate; the second oxide semiconductor channel is configured to extend along a second direction, and the second direction is perpendicular to the first direction; the second gate is configured to extending along the second direction between the second source and the second drain; and the second dielectric covers the upper surface, the lower surface and the side surface of the second gate.
  • the first oxide semiconductor channel is set to extend along the first direction; the first source and the first drain are set on the same side of the first oxide semiconductor channel; the second An oxide semiconductor channel is provided to extend in the first direction; and a second source and a second drain are provided on opposite sides of the second oxide semiconductor channel.
  • the memory in this implementation can reduce the occupied area of the memory and improve the integration of the chip.
  • the first transistor further includes a first embedded dielectric located inside the first oxide semiconductor channel; and the second transistor further includes a second embedded dielectric located inside the second oxide semiconductor channel.
  • a transistor with an OS channel is a nodal transistor, and the OS channel also has a certain doping concentration, such as n-type doping.
  • the switching characteristics of transistor devices are sensitive to the channel thickness.
  • the OS channel with a solid structure is used, the variation of the hole size (the diameter of the OS channel) will cause fluctuations between devices, for example, the switching threshold voltage of different transistors may be different, which is important for the control of transistors. Words are very unfavorable.
  • the thickness of the OS channel can be precisely controlled by atomic layer deposition. Therefore, for each transistor, its electrical performance can have continuity and consistency, thereby simplifying chip circuit design and control.
  • the two ends of the first oxide semiconductor channel are respectively embedded in the first source and the first drain; and the two ends of the second oxide semiconductor channel are embedded embedded in the second source and the second drain respectively.
  • the ends of the OS channel embedded in the source and drain respective surfaces of the source and drain are in contact with the OS channel. This increases the contact area of the OS channel with the source and drain, thereby significantly reducing the contact resistance of the transistor.
  • the driving ability and the response speed of the transistor are also improved by the source And the contact area between the drain and the OS channel is significantly improved.
  • the memory is disposed above the CMOS circuit. Since the memory is arranged above the lower CMOS circuit, circuits with different functions can be realized in the vertical direction, thereby increasing the function and integration of the chip and correspondingly reducing the occupied area of the chip.
  • the memory is disposed in the metal interconnection layer. Since a CMOS circuit usually has a metal interconnection layer above the CMOS circuit to enable the CMOS circuit to communicate with the outside, by disposing the memory in the metal interconnection layer, additional areas can be avoided to implement the memory. In this regard, the integration level of the chip can be further improved.
  • a chip includes a substrate and a memory according to the first aspect.
  • the substrate includes complementary metal oxide transistor circuitry, and memory disposed over the substrate.
  • an electronic component is provided.
  • the electronic assembly includes a circuit board, and the chip according to the second aspect is mounted on the circuit board.
  • an electronic device includes a power supply unit and a circuit board in the third aspect, and the power supply unit supplies power to the circuit board.
  • a method for manufacturing a memory includes forming a first transistor on the insulating layer and forming a second transistor on the insulating layer.
  • Forming the first transistor on the insulating layer includes forming a first oxide semiconductor channel above the insulating layer; forming a first dielectric on the first oxide semiconductor channel; forming a first gate on the first dielectric, the first gate coupled to a first word line; forming a first drain over the insulating layer, the first drain being coupled to a first bit line; and a first source over the insulating layer.
  • Forming the second transistor on the insulating layer includes forming a second oxide semiconductor channel above the insulating layer; forming a second dielectric on the second oxide semiconductor channel; forming a second gate on the second dielectric, the second gate coupled to the first source; forming a second drain over the insulating layer, the second drain coupled to the second bit line; and forming a second source over the insulating layer, the second source coupled to the second word line.
  • the method does not include forming capacitors as in conventional memory. Compared with the conventional memory based on the 1T1C structure, since the memory formed according to the method of the present disclosure adopts the 2T0C structure, there is no need to use the capacitor in the conventional memory unit. Capacitors typically have a larger footprint than transistors.
  • the memory formed according to the method of the present disclosure can significantly reduce the size of the memory and increase the integration degree of the chip. Furthermore, due to the use of OS material as the conductive channel of the transistor, the method according to the present disclosure can be compatible with BEOL, and the memory formed according to the method of the present disclosure can be arranged on top of a logic device, such as a CMOS-based logic In the interconnection layer above the device, the occupied area of the memory is further reduced and the integration degree of the chip is improved.
  • a conventional memory based on 1T1C architecture stores data by using current to charge and discharge a capacitor, which usually consumes considerable energy.
  • the memory fabricated according to the method of the present disclosure stores data in the form of voltage, that is, the stored data is characterized by the voltage of the node between the first source and the second gate, which significantly reduces memory power consumption.
  • transistors in conventional memories usually use silicon material as a conduction channel, and even when the transistor is turned off, there is a certain degree of leakage current. Due to the existence of leakage current, a conventional memory based on the 1T1C architecture usually needs to refresh each storage unit of the memory at intervals, such as 64ms, even if some storage units are not selected for reading or writing operations. Refreshing ensures that the data of the storage unit of the memory is not lost or does not generate errors, but the refreshing operation also consumes relatively much energy.
  • the two transistors of the memory cell based on the 2TOC architecture formed according to the method of the present disclosure use the channel of OS material.
  • the transistor using the OS material as the conductive channel has excellent performance. driving performance, and has a very small leakage current.
  • the stored data can thus be maintained for a relatively long time.
  • the refresh frequency of the memory based on the 2TOC architecture formed according to the method of the present disclosure is much lower than that of the conventional memory based on the 1T1C architecture, and the power supply voltage can be further reduced, thereby further reducing the power consumption of the memory.
  • forming the first transistor on the insulating layer further includes forming a third dielectric on the first oxide semiconductor channel, and the third dielectric and the first dielectric are located on opposite sides of the first oxide semiconductor channel. Both sides; a third gate is formed on the third dielectric, the third gate is coupled to the first word line, and the third dielectric is located between the third gate and the first oxide semiconductor channel.
  • Forming the second transistor on the insulating layer further includes forming a fourth dielectric on the second oxide semiconductor channel, the fourth dielectric and the second dielectric are located on opposite sides of the second oxide semiconductor channel; and on the fourth dielectric A fourth gate is formed, the fourth gate is coupled to the first source, and a fourth dielectric is located between the fourth gate and the second oxide semiconductor channel.
  • the first oxide semiconductor channel can be more effectively controlled.
  • the channel and the second oxide semiconductor channel are turned on or off to further reduce the leakage current, thereby further reducing the power consumption of the memory.
  • forming the first transistor and the second transistor includes forming a first fin transistor and a second fin transistor.
  • the first dielectric covers the upper surface and both side surfaces of a part of the first oxide semiconductor channel
  • the first gate covers the upper surface and both side surfaces of the first dielectric.
  • the second dielectric covers the upper surface and both side surfaces of a part of the second oxide semiconductor channel
  • the second gate covers the upper surface and both side surfaces of the second dielectric.
  • forming a first dielectric on the first oxide semiconductor channel includes forming a first dielectric on the first oxide semiconductor channel surrounding at least a part of side surfaces of the first oxide semiconductor channel;
  • Forming the second dielectric on the second oxide semiconductor channel includes: forming a second dielectric on the second oxide semiconductor channel surrounding at least a part of side surfaces of the second oxide semiconductor channel; forming a first dielectric on the first dielectric.
  • the gate includes: forming a first gate on the first dielectric surrounding a side surface of the first dielectric; and forming a second gate on the second dielectric includes forming a gate on the second dielectric surrounding a side surface of the second dielectric. second gate.
  • the gate-around transistor can further enhance the control of turning on or off the first oxide semiconductor channel, thereby further reducing the leakage current and further reducing the power consumption of the memory.
  • forming the first source and forming the second gate may include integrally forming the first source and the second gate as a single region.
  • forming the first oxide semiconductor channel includes forming a first oxide semiconductor channel extending along a first direction; forming the first gate includes forming The first gate extending along the first direction between them; forming the first dielectric includes forming the first dielectric covering the lower surface and the side surfaces on both sides of the first gate; forming the second oxide semiconductor channel includes forming the second oxide semiconductor channel along the first gate.
  • a second oxide semiconductor channel extending in two directions, the second direction being perpendicular to the first direction.
  • forming the second gate includes forming a second gate extending in the second direction between the second source and the second drain; and forming the second dielectric includes forming an upper surface, a lower surface and side surface of the second dielectric.
  • forming the first oxide semiconductor channel includes forming a first oxide semiconductor channel extending along a first direction; forming the first source includes forming a first oxide semiconductor channel in the first oxide semiconductor channel. The first source on one side, and forming the first drain includes forming the first drain on the first side of the first oxide semiconductor channel; forming the second oxide semiconductor channel includes forming a the second oxide semiconductor channel; and forming the second source includes forming the second source on the first side of the second oxide semiconductor channel, and forming the second drain includes forming the second drain on the second oxide semiconductor channel the second drain on the second side.
  • the memory in this implementation can reduce the occupied area of the memory and improve the integration of the chip.
  • forming the first oxide semiconductor channel over the insulating layer further includes forming a first embedded dielectric inside the first oxide semiconductor channel; and forming the first oxide semiconductor channel over the insulating layer
  • the channel further includes forming a second embedded dielectric inside the second oxide semiconductor channel.
  • a transistor with an OS channel is a nodal transistor, and the OS channel also has a certain doping concentration, such as n-type doping.
  • the switching characteristics of transistor devices are sensitive to the channel thickness.
  • the OS channel with a solid structure the variation of the hole size (the diameter of the OS channel) will cause fluctuations between devices, for example, the switching threshold voltage of different transistors may be different, which is important for the control of transistors. Words are very unfavorable.
  • the thickness of the OS channel can be precisely controlled by atomic layer deposition. Therefore, for each transistor, its electrical performance can have continuity and consistency, thereby simplifying chip circuit design and control.
  • forming the first oxide semiconductor channel includes forming two ends of the first oxide semiconductor channel to be embedded in the first source and the first drain, respectively; and forming The second oxide semiconductor channel includes forming both ends of the second oxide semiconductor channel to be embedded in the second source and the second drain, respectively.
  • the driving ability and the response speed of the transistor are also improved by the source And the contact area between the drain and the OS channel is significantly improved.
  • the memory is formed above the CMOS circuit. Since the memory is arranged above the CMOS circuit located below, circuits with different functions can be implemented in the vertical direction, thereby increasing the function and integration of the chip and correspondingly reducing the occupied area of the chip.
  • forming the first transistor on the insulating layer includes forming the first transistor in a metal interconnection layer on the insulating layer.
  • Forming the second transistor on the insulating layer includes forming the second transistor in the metal interconnection layer on the insulating layer.
  • the memory is disposed above the CMOS circuit. Since the memory is arranged above the lower CMOS circuit, circuits with different functions can be realized in the vertical direction, thereby increasing the function and integration of the chip and correspondingly reducing the occupied area of the chip.
  • FIG. 1 shows a schematic diagram of an electronic device according to an embodiment of the present disclosure
  • Figure 2 shows a simplified block diagram of an electronic assembly according to one embodiment of the present disclosure
  • Fig. 3 shows a schematic block diagram of a memory according to an embodiment of the present disclosure
  • Figure 4 shows a schematic circuit diagram of a portion of a memory according to one embodiment of the present disclosure
  • Figure 5 shows a schematic circuit diagram of a memory cell according to an embodiment of the present disclosure
  • FIG. 6 shows a schematic timing diagram of a storage unit according to an embodiment of the present disclosure
  • FIG. 7 shows a signal simulation diagram of a write operation of a memory cell according to an embodiment of the present disclosure
  • FIG. 8 shows a signal simulation diagram of a read operation of a memory cell according to an embodiment of the present disclosure
  • FIG. 9 shows a signal simulation diagram of a write operation of a memory cell according to another embodiment of the present disclosure.
  • FIG. 10 shows a signal simulation diagram of a read operation of a memory cell according to another embodiment of the present disclosure
  • Fig. 11 shows a schematic structural diagram of a storage unit according to an embodiment of the present disclosure
  • Fig. 12 shows a schematic structural diagram of a storage unit according to another embodiment of the present disclosure.
  • Fig. 13 shows a schematic structural diagram of a storage unit according to yet another embodiment of the present disclosure
  • FIG. 14 shows a flowchart of a method for fabricating a memory according to one embodiment of the present disclosure.
  • the term “comprising” and its similar expressions should be interpreted as an open inclusion, that is, “including but not limited to”.
  • the term “based on” should be understood as “based at least in part on”.
  • the term “one embodiment” or “the embodiment” should be read as “at least one embodiment”.
  • the terms “first”, “second”, etc. may refer to different or the same object.
  • the term “and/or” means at least one of the two items associated with it.
  • a and/or B means A, B, or A and B.
  • Other definitions, both express and implied, may also be included below.
  • “At least one (item)” means one or more, and “multiple” means two or more.
  • At least one of the following or similar expressions refer to any combination of these items, including any combination of single or plural items.
  • at least one item (piece) of a, b or c can mean: a, b, c, "a and b", “a and c", “b and c", or "a and b and c ", where a, b, c can be single or multiple.
  • end surface means a surface that is outermost in the direction in which the end extends and that is at an angle to the direction in which the end extends and is not parallel (for example, perpendicular).
  • the "upper surface of the end part” means the surface of the upper part of the end part in the direction in which it extends, for example, the surface on the upper side of the end part in the drawing and perpendicular to the plane of the drawing.
  • the side surface of the end means a surface in the direction in which the end extends that is at an angle to the upper surface and the end surface and is non-parallel (for example, perpendicular).
  • the section of the end portion transverse to the direction of extension of the end portion is circular, elliptical or other smooth continuous shape, there may be only the end portion side surface and the end portion surface without the upper surface.
  • the processing temperature of CMOS devices based on silicon channel materials is often as high as thousands of degrees Celsius, which makes it difficult for the manufacturing process of this CMOS device to meet the requirements of relatively low temperatures such as lower than 500 degrees Celsius. compatible with the BEOL process.
  • the channel region in the FET is often doped by, for example, high-energy particle implantation to form various conductive channels.
  • this doping will cause the temperature of at least a part of the FET to be as high as thousands of degrees Celsius, for example, 1050°C.
  • the temperature that metal lines such as copper (Cu) lines used for interconnection can withstand is often lower than 1000°C, for example, BEOL processes usually require lower than 450°C .
  • High-energy ion implantation will cause ions or other elements to diffuse into interconnect lines under high temperature conditions, affecting the performance of interconnect lines, thereby affecting the performance of devices. Therefore, it is difficult to grow and stack CMOS devices over regions formed by the BEOL process after using the BEOL process.
  • the temperature of the processing process of the FET can be controlled at a relatively low temperature, for example, lower than 500° C. or 450°C.
  • OS material refers to a class of metal oxides containing metal ions with electronic structure (n-1)d10ns0, such as In2O3[In3+:(Kr)(4d)10(5s)0(5p)0], Ga2O3 [Ga3+:(Ar)(3d)10(4s)0(4p)0], SnO2[Sn4+:(Kr)(4d)10(5s)0(5p)0], ZnO[Zn2+:(Ar)(3d ) 10(4s)0], and corresponding doped oxides, such as Sn-doped In2O3 (ITO), W-doped In2O3, InGaZnOx, InAlZnOx, etc.
  • ITO Sn-doped In2O3
  • n represents the principal quantum number
  • s, p and d represent different electron orbits
  • Kr and Ar represent the atomic realities in the electronic arrangement.
  • OS Due to the existence of s-orbital metal ions that are not filled by electrons in OS, the mobility of OS materials can reach 10-100 cm2/(V-s) even in the amorphous state.
  • the electron mobility of OS is comparable to that of polysilicon.
  • band gap of OS is above 3 electron volts (eV), much larger than the band gap of 1.1 eV of polysilicon, the leakage of OS FET is much smaller than that of polysilicon FET under the same size.
  • the driving capability of OS FET can reach or even exceed that of polysilicon FET.
  • the uniformity of the device is much better than that of polysilicon.
  • the process temperature of the OS FET can be controlled below 400°C, so that the manufacturing process of the OS FET can be compatible with the BEOL process.
  • memories containing OS FETs can be fabricated after the BEOL process.
  • DRAM dynamic random access memory
  • a voltage-based 2TOC type memory is proposed. Since 2TOC-based memories do not use capacitors as data storage devices, the device size can be greatly reduced.
  • the memory according to the embodiments of the present disclosure can also be integrated with logic devices for performing logic operations, for example, stacked above the logic devices, for example, in the interconnection layer, so that the chip can be improved. The level of integration and reduce the footprint of the chip (footprint).
  • a logic device is a unit or module for performing logic operations, for example, a logic device may include an AND gate, a NOT gate, an OR gate, a NAND gate, and the like.
  • the logic device may also be referred to as a logic element or a logic circuit or a gate circuit, and various logic function circuits required by an electronic computer may be formed by using the logic device.
  • the 2TOC type memory of the embodiments of the present disclosure does not write or read data by charging and discharging the memory with current, but uses voltage to represent stored data. Compared to the charging and discharging of current, the voltage representing the stored data can greatly reduce the power consumption of the memory.
  • the memory of the embodiments of the present disclosure uses OS material as the conduction channel of the FET, the leakage current of the FET can be reduced, thereby further reducing the refresh frequency of the memory and correspondingly reducing the power consumption of the memory.
  • FIG. 1 shows a schematic diagram of an electronic device 100 according to an embodiment of the present disclosure.
  • the electronic device 100 is, for example, a smart phone. Other electronic devices are also possible, such as computers, tablet computers or other intelligent terminal devices.
  • the electronic device 100 includes an integrated circuit assembly 10 and other components not shown, such as other chips, sensors, and the like.
  • Integrated circuit package 10 may be formed as at least part of an integrated circuit system.
  • the integrated circuit assembly 10 may include a plurality of packaged chips on a circuit board, such as a printed circuit board (PCB) or a flexible circuit board (flexbile printed circuit (FPC). One or more chips can be packaged inside each packaged chip.
  • the integrated circuit assembly 10 itself is a single chip, for example, a system in a package (SiP) chip that integrates multiple chips inside.
  • SiP system in a package
  • FIG. 2 shows a simplified block diagram of an electronic assembly 10 according to one embodiment of the present disclosure.
  • integrated circuit package 10 may include, for example, a printed circuit board with a chip mounted thereon.
  • the integrated circuit package 10 may include a first chip 12 , a second chip 14 and a third chip 16 .
  • the integrated circuit assembly 10 may also include other chips or components not shown.
  • the first chip 12 may communicate with the second chip 14 to communicate commands and/or data, and may also communicate with the third chip 16 to communicate commands and/or data. It can be understood that the first chip 12 , the second chip 14 and the third chip 16 can also respectively communicate with other chips or components. This disclosure does not impose any restrictions on this.
  • At least one of the first chip 12 , the second chip 14 and the third chip 16 is, for example, a monolithic three-dimension integration (M3D) chip.
  • M3D chips can significantly improve chip performance and reduce power consumption by stacking components with different functions, such as logic units, storage units, sensor units, RF units, etc., in the vertical direction.
  • at least a part of the M3D chip can include OS FETs to form different circuit components, and the different circuit components can be integrated through the BEOL process without bonding of different wafers, thus effectively Reduce device cost.
  • the first chip 12 may be an M3D chip.
  • the underlying circuit 12-1 may be formed by a CMOS process, and then an interconnection layer 12-2 including interconnection lines is formed over the CMOS device layer 12-1, and then an interconnection layer 12-2 is formed over the interconnection layer 12-2.
  • a logic device layer 12-3 compatible with the back-end process is formed.
  • the memory 30 may be formed in the interconnection layer 12 - 2 because the manufacturing process of the memory is compatible with the back-end process.
  • the memory 30 may also be formed in the logic device layer 12-3. It can be understood that there may be more interconnection layers and/or circuit layers above the logic device layer, which is not limited in the present disclosure.
  • the underlying circuitry can also include OS FETs instead of CMOS FETs.
  • FIG. 3 shows a schematic block diagram of a memory 30 according to an embodiment of the present disclosure.
  • Memory 20 includes word decoder 22 , bit decoder 24 , sense amplifier 26 , memory array 30 and input/output circuitry 28 .
  • the input/output circuit 28 controls the word decoder 22 and the bit decoder 24 , thereby controlling the read and write operations of the memory array 30 .
  • the sense amplifier 26 is configured to read the corresponding logic value from the memory array 30 in the read operation mode.
  • Memory array 30 includes a plurality of memory cells sharing word lines and bit lines. The memory can address memory cells for read or write operations by applying corresponding voltages to word lines and bit lines. It should be understood that in some MOS transistors, the line connected to the drain is a bit line, and the line connected to the gate is a word line, and the word line can be used to control the turn-on or turn-off of the MOS transistor.
  • Figure 4 shows a schematic circuit diagram of a portion of a memory according to one embodiment of the present disclosure.
  • the circuit shown in FIG. 4 may be a part of the memory array 30 in FIG. 3 and includes four memory cells C1, C2, C3 and C4.
  • the storage array 30 may include more storage units.
  • the memory cells C1, C2, C3, and C4 have substantially the same structure, and each memory cell is coupled to a word line and a bit line, respectively, to perform a read or write operation according to voltages on the word line and the bit line.
  • the storage unit C1 is selected for writing or reading.
  • the word line to which the memory cell is coupled is represented by symbols “WWL” and “RWL”, respectively
  • the bit line of the memory cell is represented by symbols “WBL” and “RBL” respectively
  • WWL denotes a write word line
  • RWL denotes a read word line
  • WBL denotes a write bit line
  • RBL denotes a read bit line (read bit line).
  • FIG. 5 shows a schematic circuit diagram of a memory cell C1 according to an embodiment of the present disclosure.
  • the memory cell C1 shows a 2T0C type memory cell.
  • the memory cell C1 includes a first transistor T1 and a second transistor T2. Both the first transistor T1 and the second transistor T2 include an oxide transistor channel, so the manufacturing process of the memory cell C1 can be compatible with the BEOL process.
  • the first transistor T1 includes a first gate coupled to the first word line WWL, a first drain coupled to the first bit line WBL, and a first source.
  • the second transistor T2 includes a second gate coupled to the first source of the first transistor T1, a second drain coupled to the second bit line RBL, and a second source coupled to the second word line RWL.
  • the node SP between the first source of the first transistor T1 and the second gate of the second transistor T2 is a storage node of the memory cell C1 for storing data.
  • the potentials of the second word line RWL and the second bit line RBL are set to the power supply voltage Vdd to suppress the leakage current of the writing operation. Further, when writing logic "0", the first word line WWL is set to the power supply voltage Vdd, and the first bit line WBL is set to 0V, the voltage Vsp of the storage node SP is therefore 0V, and at this time the A logic "0" is passed to the storage node SP, that is, a state in which the storage unit is written as "0".
  • both the first word line WWL and the first bit line WBL are set to the power supply voltage Vdd, and the voltage Vsp of the storage node SP is therefore equal to the ratio of Vdd and the conduction threshold voltage Vth of the first transistor.
  • the difference Vdd-Vth at this time, a logic "1" is transmitted to the storage node SP, that is, the state of the storage unit is written as "1".
  • the threshold voltage of the first transistor is consistent with that of the second transistor.
  • the power supply voltage Vdd can be greater than twice the threshold voltage, that is, the voltage Vsp of the storage node SP when "1" is written is greater than that of the transistor. Threshold voltage Vth.
  • the memory cells When reading data, the memory cells may be precharged prior to the read operation.
  • the first word line WWL is set to 0V
  • the first bit line WBL is set to 1 ⁇ 2 Vdd
  • both the second word line RWL and the second bit line RBL are set to Vdd.
  • both the first word line WWL and the second word line RWL are set to 0V
  • the first bit line WBL is set to 1/2Vdd. If the data of the storage node SP is "0", the second transistor T2 is not turned on, only a slight leakage current exists, and the Vdd voltage at the second bit line RBL remains basically unchanged.
  • the relevant logic circuit can read out the stored data by comparing the voltage. In one embodiment, if the read data is logic "1", an additional write-back operation may be performed, that is, rewrite logic "1" into the storage unit after the read operation. Table 1 below provides example values of levels of each bit line and word line in FIG. 4 in each read and write operation.
  • the memory cell according to the embodiment of the present disclosure adopts the 2T0C structure, there is no need to use the capacitor in the conventional memory cell.
  • Capacitors typically have a larger footprint than transistors. Therefore, the memory according to the embodiments of the present disclosure can significantly reduce the size of the memory and increase the integration degree of the chip.
  • conventional 1T1C architecture-based memory cells store data by using current to charge and discharge capacitors, which generally consume considerable energy.
  • the memory according to the embodiments of the present disclosure stores data in the form of voltage, which significantly reduces the power consumption of the memory cells.
  • FIG. 6 shows a timing diagram of a memory unit according to an embodiment of the present disclosure.
  • the timing diagram may be, for example, a timing diagram of various operations of the storage unit C1.
  • the timing diagram respectively includes the first word line WWL, the first bit line during the write “0" operation, precharge operation, read “0” operation, standby operation, write “1” operation, precharge operation and read “1” operation.
  • the setting voltages of WBL, the second word line RWL, and the second bit line RBL, wherein the standby operation represents an operation phase in which the memory cell is neither read nor written. In one embodiment, there may also be a write-back operation phase.
  • an additional write-back operation can be performed, that is, the logic "1" is rewritten into the storage unit after the read operation, so as to improve the accuracy of the stored data.
  • a precharge operation can also be performed before the read operation to improve the accuracy of data read.
  • FIG. 7 shows a signal simulation diagram of a write operation of a memory cell according to an embodiment of the present disclosure.
  • the writing operation is, for example, writing a logic "1" into the memory cell C1.
  • the first bit line WBL is set to "1" during 1 ns-19 ns
  • the first word line WWL is set to "1" during 2 ns-18 ns, thereby writing logic "1" into the storage node SP.
  • FIG. 8 shows a signal simulation diagram of a read operation of a memory cell according to an embodiment of the present disclosure.
  • the read operation is, for example, reading a logic "1" from the memory cell C1.
  • the second word line RWL is set to "0" for read operation, and the voltage of the second word line RWL is 20mV, which is logic "1".
  • FIG. 9 shows a signal simulation diagram of a write operation of a memory cell according to another embodiment of the present disclosure.
  • the writing operation is, for example, writing logic "0" into the memory cell C1.
  • the first bit line WBL is set to "0" during 1 ns-19 ns, and the first word line WWL is set to "1" during 2 ns-18 ns, thereby writing logic "0" into the storage node SP.
  • FIG. 10 shows a signal simulation diagram of a read operation of a memory cell according to another embodiment of the present disclosure.
  • the read operation is, for example, reading a logic "0" from the memory cell C1.
  • the second word line RWL is set to "0" for read operation, and the voltage of the second word line RWL is 1.02V, which is logic "0".
  • FIG. 11 shows a schematic structure diagram of a memory cell C11 according to an embodiment of the present disclosure.
  • the storage unit C11 is, for example, a specific implementation of the storage unit C1 in FIG. 5 . Accordingly, various aspects described with respect to FIGS. 5-10 may be applied to memory cell C11 of FIG. 11 .
  • the memory cell C11 may be formed in the interconnection layer 12-2 in a BEOL process. Alternatively, the memory cell C11 may be formed in the logic device layer 12-3. This disclosure is not limited in this regard.
  • the storage unit C11 includes a first transistor and a second transistor, for example, the first transistor T1 and the second transistor T2 in FIG. 5 .
  • the first transistor includes a first OS channel OSC1, a first gate G12, a first dielectric D12, a first drain SD11, and a first source.
  • the first gate G12 is coupled to the first word line WWL.
  • the first dielectric D12 is located between the first OS channel OSC1 and the first gate G12. Further, in one embodiment, the first dielectric D12 may surround a lower surface and two side surfaces of the first gate G12.
  • a side surface of a part or a region means a surface substantially parallel to the extending direction of the part or a region
  • an upper surface and a lower surface of a part or a region mean surfaces of an upper part and a lower part in the extending direction of a part or a region, respectively. .
  • the side surface of the first gate G12 represents a surface extending in the vertical direction in FIG. The vertically extending lower surface in FIG. 11 .
  • a lower surface of the first gate G12 faces the first OS channel OSC1, and an upper surface of the first gate G12 faces the first dielectric D21.
  • the first drain SD11 is coupled to the first bit line WBL.
  • the second transistor includes a second OS channel OSC2, a second gate, a second dielectric D21, a second drain SD21, and a second source SD22.
  • the second gate and the first source are integrally formed as a region GSD to reduce the size and cost of the memory cell, and correspondingly improve the integration degree of the semiconductor chip.
  • a is integrally formed with B means that both A and B are formed as a single part or region. In other words, functionally, that single component or region can operate both as A and as B at the same time.
  • the second gate and the first source may be formed separately and electrically coupled to each other directly.
  • the second dielectric D21 is located between the second OS channel OSC2 and the second gate.
  • the second drain SD21 is coupled to the second bit line RBL.
  • the second source SD22 is coupled to the second word line RWL.
  • the first transistor further includes a third dielectric D11 and a third gate G11.
  • the third dielectric D11 and the first dielectric D12 are located on opposite sides of the first OS channel OSC1.
  • the third gate G11 is coupled to the first word line WWL.
  • the third dielectric D11 is located between the third gate G11 and the first OS channel OSC1.
  • the second transistor also includes a fourth dielectric D22 and a fourth gate G22.
  • the fourth dielectric D22 and the second dielectric D21 are located on opposite sides of the second OS channel OSC2.
  • the fourth gate G22 is coupled to the first source, for example, through a conductive connection or a conductive region not shown in the figure.
  • the fourth dielectric D22 is located between the fourth gate G22 and the second OS channel OSC2.
  • the first transistor and the second transistor may be a dual-gate architecture, wherein the second transistor is at least partially stacked above the first transistor.
  • the back gates G11 and G22 of the first transistor and the second transistor are relatively distributed, and the top gate G12 and the region GSD are in the same layer, for example, the top gate G12 and the region GSD are both located in the first OS channel OSC1 and the second OS channel in the horizontal layer between OSC2.
  • the drain SD21 of the second transistor and its back gate G22 are in the same layer, for example, the drain SD21 of the second transistor and its back gate G22 are both located in the horizontal layer above the second OS channel OSC2.
  • the source SD22 and the region GSD can also be in the same layer, for example, the source SD22 and the region GSD can also be located in a horizontal layer between the first OS channel OSC1 and the second OS channel OSC2 .
  • the source of the first transistor is connected to or integrally formed with the gate of the second transistor, so the storage unit C1 has a small footprint and good scaling capability.
  • double-gate transistors By using double-gate transistors, the turn-on and turn-off of the transistors can be controlled more effectively to further reduce the leakage current, and thus have lower refresh frequency and power consumption.
  • a double-gate transistor structure is shown in FIG. 11, other types of transistors or other arrangements of double-gate transistors are possible.
  • a single gate transistor, a fin field effect transistor (FinFET) or a gate-all-around (GAA) transistor may be used.
  • FIG. 12 shows a schematic structural diagram of a memory cell C12 according to another embodiment of the present disclosure.
  • the storage unit C12 is, for example, another specific implementation of the storage unit C1 in FIG. 5 . Accordingly, various aspects described with respect to FIGS. 5-10 may be applied to memory cell C12 of FIG. 12 .
  • the memory cell C12 may be formed in the interconnection layer 12-2 in a BEOL process. Alternatively, the memory cell C12 may be formed in the logic device layer 12-3. This disclosure is not limited in this regard.
  • the storage unit C12 includes a first transistor and a second transistor, such as the first transistor T1 and the second transistor T2 in FIG. 5 .
  • the first transistor may be, for example, a GAA transistor, and includes a first OS channel OSC1 extending in the horizontal direction, a first source SD12, a first drain SD11, a first drain between the first source SD12 and the first drain SD11
  • the first gate G13, and the first dielectric D13 wherein the end surface of the first OS channel OSC1 is in contact with the first source SD12 and the first drain SD11.
  • the ends of the first OS channel OSC1 may be respectively embedded in the first source SD12 and the first drain SD11, that is, the end surface and the side surface of the first OS channel OSC1 It is in contact with the first source SD12 and the first drain SD11.
  • the end surface represents the direction in which the OS channel extends (in FIG.
  • the extension direction of the part is the outermost surface on the longitudinal direction) and forms a certain angle with the extension direction of the OS channel and is non-parallel (for example, vertical) surface
  • the side surface refers to the surface with a certain angle with the end surface in the extension direction of the OS channel and non-parallel (eg perpendicular) surfaces.
  • the end surface and the side surface below have the same meaning and will not be described again.
  • the inset means that the end surface and the side surface of the OS channel are in contact with the end surface in full contact with the drain and the source. No exposed parts.
  • the first gate G13 is coupled to the first word line WWL.
  • the first dielectric D13 is located between the first OS channel OSC1 and the first gate G13. Further, in one embodiment, the first dielectric D13 may surround the lower surface and both side surfaces of the first gate G13.
  • the first drain SD11 is coupled to the first bit line WBL. In one embodiment, the first dielectric D13 surrounds at least a portion of side surfaces of the first OS channel OSC1, and the first gate G13 surrounds the first dielectric D13.
  • the second transistor may be, for example, a GAA transistor, and includes a second OS channel OSC2 extending in the vertical direction, a second drain SD21, a second source SD22, and a second drain SD21 located between the second source SD22.
  • the ends of the second OS channel OSC2 may be respectively embedded in the second drain SD21 and the second source SD22, that is, the end surface and the side surface of the second OS channel OSC2 It is in contact with the second drain SD21 and the second source SD22.
  • the second gate G23 and the first source SD12 may be formed separately and electrically coupled to each other directly.
  • the second gate G23 is integrally formed with the first source SD12 as a single region to reduce the size and cost of the memory cell, and correspondingly improve the integration degree of the semiconductor chip.
  • the second dielectric D23 is located between the second OS channel OSC2 and the second gate G23. Further, in one embodiment, the second dielectric D23 may surround the upper surface, lower surface and side surfaces of the second gate G23.
  • the side surface of a part or a region means a surface in the extending direction of a part or a region or a surface substantially parallel to the extending direction of a part or a region
  • the upper surface and the lower surface of a part or a region respectively mean a surface in the part or a region.
  • the upper and lower surfaces in the direction of extension of the area For example, in FIG.
  • the upper surface of the second grid G23 is the surface of the second grid G23 opposite to a part of the second drain SD21
  • the lower surface of the second grid G23 is the surface of the second grid G23 and
  • the side surface of the second gate G23 is a surface between the upper surface and the lower surface of the second gate G23 in the extending direction (vertical direction).
  • the second drain SD21 is coupled to the second bit line RBL.
  • the second source SD22 is coupled to the second word line RWL.
  • a second dielectric surrounds at least a portion of a side surface of the second oxide semiconductor channel; and a second gate surrounds the second dielectric.
  • the first transistor has a gate-around structure of a horizontal OS channel
  • the second transistor has a gate-around structure of a vertical OS channel.
  • the turn-on and turn-off of the transistor can be controlled more effectively to further reduce the leakage current, and thus have lower refresh frequency and power consumption.
  • a GAA transistor structure is shown in FIG. 12, other types of transistors or other arrangements of GAA transistors are possible.
  • double-gate transistors can be used, for example, the surrounding gates shown in Figure 12 can be an upper striped gate and a lower striped gate electrically coupled to each other, and the OS channel is a striped trench with a longitudinal cross-section. road.
  • the end surface of the first OS channel OSC1 is two surfaces in contact with the first source electrode SD12 and the first drain electrode SD11, and the upper surface and the lower surface of the first OS channel OSC1 are in contact with the first dielectric D13 is in contact, and the side surface of the first OS channel OSC1 is a surface that forms an angle and is non-parallel (eg, perpendicular) to the end surface, the upper surface, and the lower surface.
  • End surfaces of the second OS channel OSC2 are two surfaces in contact with the second source electrode SD22 and the second drain electrode SD21, the upper surface of the second OS channel OSC2 faces a part of the second drain electrode SD21, The lower surface of the second OS channel OSC2 faces a part of the second source electrode SD22, and the side surfaces of the second OS channel OSC2 form a certain angle with the end surface, the upper surface and the lower surface and are non-parallel. (e.g. vertical) surfaces.
  • FIG. 13 shows a schematic structural diagram of a storage unit C13 according to yet another embodiment of the present disclosure.
  • the storage unit C13 is, for example, another specific implementation of the storage unit C1 in FIG. 5 . Accordingly, various aspects described with respect to FIG. 5 may be applied to the memory cell C13 of FIG. 13 .
  • the memory cell C13 has a substantially similar architecture to that of the memory cell C12 of FIG. 7 , and thus descriptions about various aspects of the memory cell C12 may be applied to the memory cell C13.
  • One difference between the memory cell C13 and the memory cell C12 is that: the two ends of the first OS channel OSC1 are respectively embedded in the first source SD11 and the first drain SD12, and the ends of the second OS channel OSC2 Both ends are embedded in the second source SD21 and the second drain 22, respectively.
  • the end surfaces and side surfaces of both ends of the first OS channel OSC1 are in direct contact with the corresponding source or drain
  • the end surfaces and side surfaces of both ends of the second OS channel OSC2 Both surfaces are in direct contact with the corresponding source or drain.
  • OS materials are generally n-type doped from the nature of the material itself.
  • the channel region cannot be doped by methods such as ion implantation, and the ion implantation method is not compatible with the BEOL process. Therefore, the OS FET is a junctionless device, that is, the doping concentration of the channel and the source and drain is basically the same. In order to ensure the normal switching characteristics of the device, the doping concentration of the channel should not be too high, otherwise the FET cannot be effectively turned off. It is found through research that due to the limitation of channel doping, the driving ability and response speed of OS FETs are not ideal, especially in FETs with small channel sizes such as nanometers.
  • a fully or partially covered contact structure to effectively increase the contact area between the source and the drain and the channel, thereby improving the driving capability and response speed of the OS FET.
  • the larger the contact area of the source and drain the smaller the contact resistance.
  • the smaller the total resistance of the OS FET device the greater the current at the same voltage, thereby improving the drive capability and response speed.
  • the first transistor further includes a first embedded dielectric DF1 located inside the first OS channel OSC1; and the second transistor further includes a dielectric dielectric DF1 located inside the second OS channel OSC2.
  • the embedding means that the end surface and the side surface of the OS channel, where the portion contacting the end surface, is in full contact with the drain and the source without an exposed portion.
  • a transistor with an OS channel is a nodal transistor, and the OS channel also has a certain doping concentration, such as n-type doping. For doped OS channels, the switching characteristics of transistor devices are sensitive to the channel thickness.
  • the variation of the hole size (the diameter of the OS channel) will cause fluctuations between devices, for example, the switching threshold voltage of different transistors may be different, which is important for the control of transistors. Words are very unfavorable.
  • the thickness of the OS channel can be precisely controlled by atomic layer deposition. Therefore, for each transistor, its electrical performance can have continuity and consistency, thereby simplifying chip circuit design and control.
  • FIG. 14 shows a flowchart of a method 1400 for fabricating a memory according to one embodiment of the present disclosure.
  • the method can be used to manufacture the semiconductor device shown in FIGS. 3-13 , so the various aspects described above with respect to FIGS. 3-13 can be applied to the method 1400 , which will not be repeated here.
  • a first transistor is formed on an insulating layer.
  • the insulating layer is, for example, the insulating layer at the interface between the underlying circuit layer 12-1 and the interconnection layer 12-2, wherein the interconnection line can pass through part of the insulating layer to realize electrical coupling with the underlying circuit.
  • the insulating layer is, for example, an insulating layer at the interface between the interconnection layer 12-2 and the logic device layer 12-3, wherein the interconnection line may pass through part of the insulating layer to realize electrical coupling with the logic device.
  • "forming" refers to a collection of one or more process steps for fabricating one or more device structures or regions.
  • “forming” may include using process steps such as coating photoresist, exposing, implanting, depositing, and etching.
  • One or more specific processes can be selected to form specific regions or structures as required.
  • forming the first transistor on the insulating layer includes: forming a first oxide semiconductor channel over the insulating layer; forming a first dielectric on the first oxide semiconductor channel; forming a first dielectric on the first dielectric. a gate, the first gate is coupled to the first word line; a first drain is formed over the insulating layer, the first drain is coupled to the first bit line; and a first source is formed over the insulating layer.
  • forming the first transistor on the insulating layer further includes: forming a third dielectric on the first oxide semiconductor channel, the third dielectric and the first dielectric are located on opposite sides of the first oxide semiconductor channel ; forming a third gate on the third dielectric, the third gate is coupled to the first word line, and the third dielectric is located between the third gate and the first oxide semiconductor channel.
  • Forming the first dielectric on the first oxide semiconductor channel includes forming the first dielectric surrounding at least a portion of a side surface of the first oxide semiconductor channel on the first oxide semiconductor channel.
  • Forming the first gate on the first dielectric includes forming the first gate on the first dielectric surrounding a side surface of the first dielectric.
  • forming the first oxide semiconductor channel over the insulating layer further includes: forming a first embedded dielectric inside the first oxide semiconductor channel. Forming the first transistor on the insulating layer includes forming the first transistor in the interconnection layer on the insulating layer.
  • a second transistor is formed on the insulating layer.
  • forming the second transistor on the insulating layer includes: forming a second oxide semiconductor channel over the insulating layer; forming a second dielectric on the second oxide semiconductor channel; forming a second transistor on the second dielectric. gate, the second gate is coupled to the first source; a second drain is formed over the insulating layer, the second drain is coupled to the second bit line; and a second source is formed over the insulating layer, the second source Coupled to the second word line.
  • forming the second transistor on the insulating layer further includes: forming a fourth dielectric on the second oxide semiconductor channel, the fourth dielectric and the second dielectric are located on opposite sides of the second oxide semiconductor channel and forming a fourth gate on the fourth dielectric, the fourth gate is coupled to the first source, and the fourth dielectric is located between the fourth gate and the second oxide semiconductor channel.
  • Forming the second dielectric on the second oxide semiconductor channel includes forming a second dielectric surrounding at least a portion of a side surface of the second oxide semiconductor channel on the second oxide semiconductor channel.
  • Forming the second gate on the second dielectric includes forming the second gate on the second dielectric surrounding a side surface of the second dielectric.
  • forming the first oxide semiconductor channel over the insulating layer further includes: forming a second embedded dielectric inside the second oxide semiconductor channel. Forming the second transistor on the insulating layer includes forming the second transistor in the interconnection layer on the insulating layer.

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Abstract

一种存储器及其制造方法。存储器包括第一晶体管（T1）和第二晶体管（T2）。第一晶体管（T1）和第二晶体管（T2）分别包括栅极、漏极、源极和氧化物半导体沟道。第一晶体管（T1）的源极耦合至第二晶体管（T2）的栅极。第一晶体管（T1）和第二晶体管（T2）一起形成基于2T0C架构的存储器中的存储器单元。通过使用氧化物半导体材料形成第一晶体管（T1）和第二晶体管（T2）的沟道，存储器可以与半导体器件的后端工艺兼容。存储器因此可以被堆叠在底层电路上方，例如被堆叠在互连层中，从而提高芯片的集成度。

Description

存储器及其制造方法 技术领域
本公开涉及电子领域，更具体而言涉及存储器及其制造方法。
背景技术
随着半导体技术的发展，使用半导体材料制造的芯片的集成度越来越高。例如，芯片中所容纳的场效应晶体管(field-effect transistor,FET)的数量越来越多。另一方面，芯片的尺寸也越来越小，以适应电子设备小型化的趋势。例如，在使用硅材料作为导电沟道的互补型金属氧化物半导体(complementary metal-oxide-semiconductor,CMOS)FET中，沟道长度越来越小。CMOS FET的尺寸也相应变小，因此单位面积的芯片可以集成更多的CMOS FET。
在常规芯片制造过程中，诸如基于硅沟道材料的常规CMOS存储器的加工工艺温度往往超过1000℃，这导致该CMOS存储器的制造工艺难于与要求相对低温(例如低于500℃)的后端工艺(back end of line,BEOL)兼容。
发明内容
鉴于上述问题，本公开的实施例旨在提供一种存储器、芯片、包括该芯片的电子组件和电子设备、以及制造该半导体器件的方法。该半导体器件可以与BEOL兼容。
根据本公开的第一方面，提供一种存储器。存储器包括第一晶体管和第二晶体管。第一晶体管包括第一氧化物半导体沟道；第一栅极，耦合至第一字线；第一电介质，位于第一氧化物半导体沟道和第一栅极之间；第一漏极，耦合至第一位线；以及第一源极。第二晶体管，包括第二氧化物半导体沟道；第二栅极，耦合至第一源极；第二电介质，位于第二氧化物半导体沟道和第二栅极之间；第二漏极，耦合至第二位线；以及第二源极，耦合至第二字线。该存储器不包括常规存储器中的电容器。相比于具有一个晶体管和一个电容器(one transitor and one capacitor,1T1C)的架构的常规存储器，由于根据本公开的存储器采用了2个晶体管并且不具有电容器(one transistors and zero capacitor,2T0C)的架构，因此无需使用常规存储单元中的电容器。相比于晶体管，电容器通常具有较大的占用面积。因此，根据本公开的存储器可以显著减少存储器的尺寸并且提高芯片的集成度。此外，由于使用OS材料作为晶体管的导电沟道，根据本公开的存储器的制造工艺可以与BEOL相兼容，并且根据本公开的存储器可以被设置在逻辑器件上方，例如被设置在基于CMOS的逻辑器件上方的互连层中，从而进一步减少存储器的占用面积并且提高芯片的集成度。另一方面，基于1T1C架构的常规存储器通过使用电流对电容器的充电和放电来存储数据，电容器的充电和放电通常会消耗相当的能量。相比而言，根据本公开的存储器以电压的方式存储数据，即，通过第一源极和第二栅极之间的节点的电压来表征所存储的数据，这显著降低了存储器的功率消耗。进一步地，常规存储器中的晶体管通常使用硅材料作为导电沟道，即使在晶体管被关断时，也会存在一定程度的泄露电流。由于泄露电流的存在，基于1T1C架构的常规存储器通常每隔一段时间，例如64ms，就需要对存储器的各个存储单元刷新一次，即使某些存储单元未被选中进行读取或写入操作。刷新使得该存储器的存储单元的数据不被丢失或不产生错误，但是刷新操作也消耗了比较多的能量。根据本公开的基于2T0C架构的存储单元的两个晶体管使用了OS材料 的沟道，相比于具有硅材料形成的沟道的晶体管，使用OS材料作为导电沟道的晶体管具有优异的驱动性能，并且具有非常小的泄露电流。因此能够相对长时间地维持所存储的数据。对应地，根据本公开的基于2T0C架构的存储器的刷新频率远小于基于1T1C架构的常规存储器的刷新频率，并且电源电压也可以进一步降低，因此进一步降低了存储器的功耗。
在一种可能的实现方式中，第一晶体管还包括第三电介质，第三电介质和第一电介质位于第一氧化物半导体沟道的相对的两侧；以及第三栅极，耦合至第一字线，第三电介质位于第三栅极和第一氧化物半导体沟道之间。通过使用双栅，即位于第一氧化物半导体沟道两侧的两个栅极，可以更为有效地控制第一氧化物半导体沟道的导通或关断，进一步降低泄露电流，从而进一步降低存储器的功耗。
在一种可能的实现方式中，第二晶体管还包括第四电介质，第四电介质和第二电介质位于第二氧化物半导体沟道的相对的两侧；以及第四栅极，耦合至第一源极，第四电介质位于第四栅极和第二氧化物半导体沟道之间。通过使用双栅，即位于第二氧化物半导体沟道两侧的两个栅极，可以更为有效地控制第二氧化物半导体沟道的导通或关断，进一步降低泄露电流，从而进一步降低存储器的功耗。
在一种可能的实现方式中，第一晶体管和第二晶体管为鳍式晶体管。在第一晶体管中，第一电介质包覆第一氧化物半导体沟道的一部分的上表面和两个侧表面，并且第一栅极包覆第一电介质的上表面和两个侧表面。在第二晶体管中，第二电介质包覆第二氧化物半导体沟道的一部分的上表面和两个侧表面，并且第二栅极包覆第二电介质的上表面和两个侧表面。通过使用鳍式晶体管，可以更为有效地控制第一氧化物半导体沟道的导通或关断，进一步降低泄露电流，从而进一步降低存储器的功耗。
在一种可能的实现方式中，第一电介质围绕第一氧化物半导体沟道的至少一部分的侧表面；以及第一栅极围绕第一电介质。通过将第一电介质形成为围绕第一氧化物半导体沟道的至少一部分的侧表面并且将第一栅极围绕第一电介质，可以形成环栅晶体管。相比于双栅晶体管，环栅晶体管可以进一步增强对于第一氧化物半导体沟道的导通或关断的控制，从而进一步降低泄露电流，并且进一步降低存储器的功耗。
在一种可能的实现方式中，第二电介质围绕第二氧化物半导体沟道的至少一部分的侧表面；以及第二栅极围绕第二电介质。相比于双栅晶体管，环栅晶体管可以进一步增强对于第二氧化物半导体沟道的导通或关断的控制，从而进一步降低泄露电流，并且进一步降低存储器的功耗。
在一种可能的实现方式中，第一源极和第二栅极一体形成为单个区域。通过将第一源极和第二栅极一体形成，可以节省工艺步骤并且降低存储器制造成本。
在一种可能的实现方式中，第一氧化物半导体沟道被设置为沿第一方向延伸；第一栅极被设置为在第一源极和第一漏极之间沿第一方向延伸；第一电介质包覆第一栅极的下表面和两侧侧表面；第二氧化物半导体沟道被设置为沿第二方向延伸，第二方向与第一方向垂直；第二栅极被设置为在第二源极和第二漏极之间沿第二方向延伸；以及第二电介质包覆第二栅极的上表面、下表面和侧表面。通过将第一晶体管和第二晶体管的氧化物半导体沟道设置为沿不同方向延伸，第一晶体管和第二晶体管可以被并排地设置在相同的层中，从而节省制造工艺和步骤，并且降低制造成本。
在一种可能的实现方式中，第一氧化物半导体沟道被设置为沿第一方向延伸；第一源极和第一漏极被设置在第一氧化物半导体沟道的相同侧；第二氧化物半导体沟道被设置为沿 第一方向延伸；以及第二源极和第二漏极被设置在第二氧化物半导体沟道的相对侧。在该实现方式中的存储器可以降低存储器的占用面积并且提供芯片的集成度。
在一种可能的实现方式中，第一晶体管还包括位于第一氧化物半导体沟道内部的第一嵌入电介质；以及第二晶体管还包括位于第二氧化物半导体沟道内部的第二嵌入电介质。具有OS沟道的晶体管是无节型晶体管，并且OS沟道也是具有一定的掺杂浓度，例如n型掺杂。对于掺杂的OS沟道，晶体管器件的开关特性对沟道厚度比较敏感。当采用实心结构的OS沟道时，孔洞尺寸(OS沟道的直径)的变化会导致器件与器件之间的波动，例如不同晶体管的开关阈值电压可能会因此而不同，这对于晶体管的控制而言非常不利。相比之下，当在OS沟道中嵌入电介质时，OS沟道的厚度可以通过原子层沉积精确控制。因此，对于各个晶体管而言，其电学性能可以具有连续性和一致性，从而可以简化芯片电路设计和控制。
在一种可能的实现方式中，第一氧化物半导体沟道的两个端部被分别嵌入在第一源极和第一漏极中；以及第二氧化物半导体沟道的两个端部被分别嵌入在第二源极和第二漏极中。通过使得OS沟道的端部被嵌入在源极和漏极中，源极和漏极的相应多个表面与OS沟道接触。这增加了OS沟道与源极和漏极的接触面积，从而显著降低了晶体管的接触电阻。与通过仅增加OS沟道与源极和漏极的相应单个表面接触的情形相比，可以在不影响具有OS沟道的晶体管的小型化的同时，晶体管的驱动能力和响应速度也因源极和漏极与OS沟道的接触面积增加而显著提升。
在一种可能的实现方式中，存储器被设置在CMOS电路的上方。由于在位于下方的CMOS电路的上方设置存储器，可以在竖直方向上实现不同功能的电路，从而增加了芯片的功能和集成度并且相应地减小了芯片的占用面积。
在一种可能的实现方式中，存储器被设置在金属互连层中。由于CMOS电路通常原本就具有位于CMOS电路上方的金属互连层以使得CMOS电路与外部进行通信，因此通过将存储器设置在金属互连层中，可以避免额外地增设区域来实现存储器。就此而言，可以进一步地提升芯片的集成度。
根据本公开的第二方面，提供一种芯片。芯片包括衬底和根据第一方面的存储器。衬底包括互补型金属氧化物晶体管电路，以及被设置在衬底的上方的存储器。
根据本公开的第三方面，提供一种电子组件。电子组件包括电路板，以及根据第二方面的芯片，被安装在电路板上。
根据本公开的第四方面，提供一种电子设备。电子设备包括电源装置，以及第三方面的电路板，电源装置为电路板供电。
根据本公开的第五方面，一种用于制造存储器的方法。该方法包括在绝缘层上形成第一晶体管和在绝缘层上形成第二晶体管。在绝缘层上形成第一晶体管包括在绝缘层上方形成第一氧化物半导体沟道；在第一氧化物半导体沟道上形成第一电介质；在第一电介质上形成第一栅极，第一栅极耦合至第一字线；在绝缘层上方形成第一漏极，第一漏极耦合至第一位线；以及在绝缘层上方第一源极。在绝缘层上形成第二晶体管包括在绝缘层上方形成第二氧化物半导体沟道；在第二氧化物半导体沟道上形成第二电介质；在第二电介质上形成第二栅极，第二栅极耦合至第一源极；在绝缘层上方形成第二漏极，第二漏极耦合至第二位线；以及在绝缘层上方形成第二源极，第二源极耦合至第二字线。该方法不包括形成常规存储器中的电容器。相比于基于1T1C架构的常规存储器，由于根据本公开的方法形成的存储器采用了2T0C的架构，因此无需使用常规存储单元中的电容器。相比于晶体管，电容器通常具有较大的占 用面积。因此，根据本公开的方法形成的存储器可以显著减少存储器的尺寸并且提高芯片的集成度。此外，由于使用OS材料作为晶体管的导电沟道，根据本公开的方法可以与BEOL相兼容，并且根据本公开的方法所形成的存储器可以被设置在逻辑器件上方，例如被设置在基于CMOS的逻辑器件上方的互连层中，从而进一步减少存储器的占用面积并且提高芯片的集成度。另一方面，基于1T1C架构的常规存储器通过使用电流对电容器的充电和放电来存储数据，电容器的充电和放电通常会消耗相当的能量。相比而言，根据本公开的方法所制造的存储器以电压的方式存储数据，即，以第一源极和第二栅极之间的节点的电压来表征所存储的数据，这显著降低了存储器的功率消耗。进一步地，常规存储器中的晶体管通常使用硅材料作为导电沟道，即使在晶体管被关断时，也会存在一定程度的泄露电流。由于泄露电流的存在，基于1T1C架构的常规存储器通常每隔一段时间，例如64ms，就需要对存储器的各个存储单元刷新一次，即使某些存储单元未被选中进行读取或写入操作。刷新使得该存储器的存储单元的数据不被丢失或不产生错误，但是刷新操作也消耗了比较多的能量。根据本公开的方法所形成的基于2T0C架构的存储单元的两个晶体管使用了OS材料的沟道，相比于具有硅材料形成的沟道的晶体管，使用OS材料作为导电沟道的晶体管具有优异的驱动性能，并且具有非常小的泄露电流。因此能够相对长时间地维持所存储的数据。对应地，根据本公开的方法所形成的基于2T0C架构的存储器的刷新频率远小于基于1T1C架构的常规存储器的刷新频率，并且电源电压也可以进一步降低，因此进一步降低了存储器的功耗。
在一种可能的实现方式中，在绝缘层上形成第一晶体管还包括在第一氧化物半导体沟道上形成第三电介质，第三电介质和第一电介质位于第一氧化物半导体沟道的相对的两侧；在第三电介质上形成第三栅极，第三栅极耦合至第一字线，第三电介质位于第三栅极和第一氧化物半导体沟道之间。在绝缘层上形成第二晶体管还包括在第二氧化物半导体沟道上形成第四电介质，第四电介质和第二电介质位于第二氧化物半导体沟道的相对的两侧；以及在第四电介质上形成第四栅极，第四栅极耦合至第一源极，第四电介质位于第四栅极和第二氧化物半导体沟道之间。通过使用双栅，即位于第一氧化物半导体沟道两侧的两个栅极和位于第二氧化物半导体沟道两侧的两个栅极，可以更为有效地控制第一氧化物半导体沟道和第二氧化物半导体沟道的导通或关断，进一步降低泄露电流，从而进一步降低存储器的功耗。
在一种可能的实现方式中，形成第一晶体管和第二晶体管包括形成第一鳍式晶体管和第二鳍式晶体管。在第一鳍式晶体管中，第一电介质包覆第一氧化物半导体沟道的一部分的上表面和两个侧表面，并且第一栅极包覆第一电介质的上表面和两个侧表面。在第二鳍式晶体管中，第二电介质包覆第二氧化物半导体沟道的一部分的上表面和两个侧表面，并且第二栅极包覆第二电介质的上表面和两个侧表面。通过使用鳍式晶体管，可以更为有效地控制第一氧化物半导体沟道的导通或关断，进一步降低泄露电流，从而进一步降低存储器的功耗。
在一种可能的实现方式中，在第一氧化物半导体沟道上形成第一电介质包括在第一氧化物半导体沟道上形成围绕第一氧化物半导体沟道的至少一部分的侧表面的第一电介质；在第二氧化物半导体沟道上形成第二电介质包括：在第二氧化物半导体沟道上形成围绕第二氧化物半导体沟道的至少一部分的侧表面的第二电介质；在第一电介质上形成第一栅极包括：在第一电介质上形成围绕第一电介质的侧表面的第一栅极；以及在第二电介质上形成第二栅极包括：在第二电介质上形成围绕第二电介质的侧表面的第二栅极。通过将第一电介质形成为围绕第一氧化物半导体沟道的至少一部分的侧表面并且将第一栅极围绕第一电介质，并且通过将第二电介质形成为围绕第二氧化物半导体沟道的至少一部分的侧表面并且将第二栅极围 绕第二电介质，可以分别形成第一环栅晶体管和第二环栅晶体管。相比于双栅晶体管，环栅晶体管可以进一步增强对于第一氧化物半导体沟道的导通或关断的控制，从而进一步降低泄露电流，并且进一步降低存储器的功耗。
在一种可能的实现方式中，形成第一源极和形成第二栅极可以包括将第一源极和第二栅极一体地形成为单个区域。通过将第一源极和第二栅极一体形成，可以节省工艺步骤并且降低存储器制造成本。
在一种可能的实现方式中，形成第一氧化物半导体沟道包括形成沿第一方向延伸的第一氧化物半导体沟道；形成第一栅极包括形成在第一源极和第一漏极之间沿第一方向延伸的第一栅极；形成第一电介质包括形成包覆第一栅极的下表面和两侧侧表面的第一电介质；形成第二氧化物半导体沟道包括形成沿第二方向延伸的第二氧化物半导体沟道，第二方向与第一方向垂直。形成第二栅极包括形成在第二源极和第二漏极之间沿第二方向延伸的第二栅极；以及形成第二电介质包括形成包覆第二栅极的上表面、下表面和侧表面的第二电介质。通过将第一晶体管和第二晶体管的氧化物半导体沟道设置为沿不同方向延伸，第一晶体管和第二晶体管可以被并排地设置在相同的层中，从而节省制造工艺和步骤，并且降低制造成本。
在一种可能的实现方式中，形成第一氧化物半导体沟道包括形成沿第一方向延伸的第一氧化物半导体沟道；形成第一源极包括形成在第一氧化物半导体沟道的第一侧的第一源极，并且形成第一漏极包括形成在第一氧化物半导体沟道的第一侧的第一漏极；形成第二氧化物半导体沟道包括形成沿第一方向延伸的第二氧化物半导体沟道；以及形成第二源极包括形成在第二氧化物半导体沟道的第一侧的第二源极，形成第二漏极包括形成在第二氧化物半导体沟道的第二侧的第二漏极。在该实现方式中的存储器可以降低存储器的占用面积并且提供芯片的集成度。
在一种可能的实现方式中，在绝缘层上方形成第一氧化物半导体沟道还包括在第一氧化物半导体沟道内部形成第一嵌入电介质；以及在绝缘层上方形成第一氧化物半导体沟道还包括：在第二氧化物半导体沟道内部形成第二嵌入电介质。具有OS沟道的晶体管是无节型晶体管，并且OS沟道也是具有一定的掺杂浓度，例如n型掺杂。对于掺杂的OS沟道，晶体管器件的开关特性对沟道厚度比较敏感。当采用实心结构的OS沟道时，孔洞尺寸(OS沟道的直径)的变化会导致器件与器件之间的波动，例如不同晶体管的开关阈值电压可能会因此而不同，这对于晶体管的控制而言非常不利。相比之下，当在OS沟道中嵌入电介质时，OS沟道的厚度可以通过原子层沉积精确控制。因此，对于各个晶体管而言，其电学性能可以具有连续性和一致性，从而可以简化芯片电路设计和控制。
在一种可能的实现方式中，形成第一氧化物半导体沟道包括将第一氧化物半导体沟道的两个端部分别形成为被嵌入在第一源极和第一漏极中；以及形成第二氧化物半导体沟道包括将第二氧化物半导体沟道的两个端部分别形成为被嵌入在第二源极和第二漏极中。通过使得OS沟道的端部被嵌入在源极和漏极中，源极和漏极的相应多个表面与OS沟道接触。这增加了OS沟道与源极和漏极的接触面积，从而显著降低了晶体管的接触电阻。与通过仅增加OS沟道与源极和漏极的相应单个表面接触的情形相比，可以在不影响具有OS沟道的晶体管的小型化的同时，晶体管的驱动能力和响应速度也因源极和漏极与OS沟道的接触面积增加而显著提升。
在一种可能的实现方式中，存储器被形成在CMOS电路的上方。由于在位于下方的CMOS电路的上方设置存储器，可以在竖直方向上实现不同功能的电路，从而增加了芯片的功能和 集成度并且相应地减小了芯片的占用面积。
在一种可能的实现方式中，在绝缘层上形成第一晶体管包括在绝缘层上的金属互连层中形成第一晶体管。在绝缘层上形成第二晶体管包括在绝缘层上的金属互连层中形成第二晶体管。在一种可能的实现方式中，存储器被设置在CMOS电路的上方。由于在位于下方的CMOS电路的上方设置存储器，可以在竖直方向上实现不同功能的电路，从而增加了芯片的功能和集成度并且相应地减小了芯片的占用面积。
应当理解，发明内容部分中所描述的内容并非旨在限定本公开的实施例的关键或重要特征，亦非用于限制本公开的范围。本公开的其它特征将通过以下的描述变得容易理解。
附图说明
结合附图并参考以下详细说明，本公开各实施例的上述和其他特征、优点及方面将变得更加明显。在附图中，相同或相似的附图标记表示相同或相似的元素，其中：
图1示出了根据本公开的一个实施例的电子设备的示意图；
图2示出了根据本公开的一个实施例的电子组件的简化框图；
图3示出了根据本公开的一个实施例的存储器的示意框图；
图4示出了根据本公开的一个实施例的存储器的一部分的示意电路图；
图5示出了根据本公开的一个实施例的存储单元的示意电路图；
图6示出了根据本公开的一个实施例的存储单元的时序示意图；
图7示出了根据本公开的一个实施例的存储单元的写入操作的信号仿真图；
图8示出了根据本公开的一个实施例的存储单元的读取操作的信号仿真图；
图9示出了根据本公开的另一实施例的存储单元的写入操作的信号仿真图；
图10示出了根据本公开的另一实施例的存储单元的读取操作的信号仿真图；
图11示出了根据本公开的一个实施例的存储单元的示意结构图；
图12示出了根据本公开的另一实施例的存储单元的示意结构图；
图13示出了根据本公开的又一实施例的存储单元的示意结构图；
图14示出了根据本公开的一个实施例的用于制造存储器的方法的流程图。
具体实施方式
下面将参照附图更详细地描述本公开的实施例。虽然附图中显示了本公开的某些实施例，然而应当理解的是，本公开可以通过各种形式来实现，而且不应该被解释为限于这里阐述的实施例，相反提供这些实施例是为了更加透彻和完整地理解本公开。应当理解的是，本公开的附图及实施例仅用于示例性作用，并非用于限制本公开的保护范围。
在本公开的实施例的描述中，术语“包括”及其类似用语应当理解为开放性包含，即“包括但不限于”。术语“基于”应当理解为“至少部分地基于”。术语“一个实施例”或“该实施例”应当理解为“至少一个实施例”。术语“第一”、“第二”等等可以指代不同的或相同的对象。术语“和/或”表示由其关联的两项的至少一项。例如“A和/或B”表示A、B、或者A和B。下文还可能包括其他明确的和隐含的定义。"至少一个(项)"是指一个或者多个，"多个"是指两个或两个以上。“以下至少一项(个)”或其类似表达，是指这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，“a和b”，“a和c”，“b和c”，或“a和b和c”，其中a，b，c可以是单个，也可以是多个。在本文中，“端部表面”表示在端部延伸方向上最外侧并且与端部的延伸方向成一定角度并且非平行(例如垂直)的表面。“端部的上表面”表示端部在其延伸方向上的上部的表面，例如在图示中的端部上侧并且与图示平面垂直的表面。“端部的侧表面”表示在端部延伸方向上的、与上表面和端部表面成一定角度并且非平行(例如垂直)的表面。在端部的与端部延伸方向横切的截面为圆形、椭圆形或其它光滑连续形状的情形下，可以仅有端部侧表面和端部表面 而无上表面。应理解，本申请实施例提供的技术方案，在以下具体实施例的介绍中，某些重复之处可能不再赘述，但应视为这些具体实施例之间已有相互引用，可以相互结合。
如上所述，在常规芯片制造过程中，基于硅沟道材料的CMOS器件的加工工艺温度往往高达上千摄氏度，这导致该CMOS器件的制造工艺难以与要求诸如低于500摄氏度之类的相对低温的BEOL工艺兼容。例如，在CMOS FET的制造过程中，FET中的沟道区域往往通过诸如高能粒子注入来进行掺杂，以形成各种导电沟道。然而这种掺杂会使得FET中的至少一部分区域的温度高达上千摄氏度，例如1050℃。对于用于诸如互连之类的BEOL工艺而言，互连所使用的诸如铜(Cu)线之类的金属线所能承受的温度往往低于1000℃，例如BEOL工艺通常要求低于450℃。高能离子注入会使得离子或其它元素在高温情形下扩散进入互连线，影响互连线的性能，进而影响器件的性能。因此，难以在使用BEOL工艺之后在BEOL工艺形成的区域上方生长和堆叠CMOS器件。
在本公开的一些实施例中，通过使用氧化物半导体(oxide semiconductor,OS)材料来形成FET中的沟道，可以将FET的加工工艺的温度控制在相对低的温度，例如低于500℃或450℃。在本文中，OS材料表示包含电子结构为(n-1)d10ns0的金属离子的一类金属氧化物，例如In2O3[In3+:(Kr)(4d)10(5s)0(5p)0]，Ga2O3[Ga3+:(Ar)(3d)10(4s)0(4p)0]，SnO2[Sn4+:(Kr)(4d)10(5s)0(5p)0]，ZnO[Zn2+:(Ar)(3d)10(4s)0]，以及相应的掺杂氧化物，例如掺Sn的In2O3(ITO),掺W的In2O3,InGaZnOx,InAlZnOx等。在前面描述的电子结构(n-1)d10ns0中n表示主量子数，s、p和d分别表示不同的电子轨道，Kr和Ar分别表示电子排布式中的原子实。OS由于存在未被电子填充的s轨道金属离子，因此即使在非晶状态下，OS材料的迁移率也可以达到10-100cm2/(V-s)。OS的电子迁移率和多晶硅相当。其次，由于OS的禁带宽度在3电子伏特(eV)以上，远大于多晶硅的禁带宽度1.1eV，因此在相同尺寸下OS FET的漏电远小于多晶硅FET。因此，OS FET的驱动能力可以达到甚至超过多晶硅FET。同时，非晶OS由于不存在晶界，因此器件的均匀性远好于多晶硅。通过使用OS材料来形成FET的沟道，可以将OS FET的工艺温度控制在400℃之下，从而使得OS FET的制造工艺可以与BEOL工艺相兼容。例如，可以在BEOL工艺之后制造包含OS FET的存储器。
另一方面，在一些高性能运算场景中，例如人工智能计算等，数据从单独的动态随机存取存储器(dynamic randon access memory,DRAM)芯片传送到处理器的延时变得非常重要。因此也提出了一些将DRAM和处理器集成在单个芯片内的方案以减小延迟。常规的基于1T1C的DRAM的集成度存在局限性，很难与逻辑电路相集成制造在一起。另外，DRAM的主要原理是利用电容内存储电荷的多寡来代表一个二进制比特(bit)是1还是0，但是电容在晶体管中存在泄漏情况。例如DRAM在读取时，读取数据的原理是电容器放电，这属于破坏性读取；并且即使不读取电位，电荷也会通过晶体管从电容器泄漏出来。因此在常规DRAM中，需要定时(例如每64毫秒)完成一次刷新动作，功耗较大。此外，由于电容器的尺寸难于收缩，因此基于1T1C的常规DRAM的微缩能力受限，这与当前的器件小型化的趋势背道而驰。
在本公开的一些实施例中，提出一种基于电压的2T0C型存储器。由于基于2T0C的存储器不使用电容器作为数据存储器件，因此可以极大地减少器件尺寸。另外，由于使用OS沟道，因此根据本公开的实施例的存储器还可以与用于执行逻辑运算的逻辑器件集成在一起，例如堆叠在逻辑器件上方，例如位于互连层中，从而可以提高芯片的集成度并且减小芯片的占用面积(footprint)。应当理解，逻辑器件为用于执行逻辑运算的单元或模块，例如逻辑器件可以包括与门、非门、或门、与非门等。可选的，逻辑器件还可以称为逻辑元件或逻辑电路或门电路，利用逻辑器件可以组成电子计算机所需的各种逻辑功能电路。
此外，本公开的实施例的2T0C型存储器不通过电流对存储器充放电来写入或读取数据，而是使用电压来表示所存储的数据。相比于电流的充电和放电，电压表示所存储的数据可以极大地减少存储器的功耗。另外，由于本公开的实施例的存储器使用OS材料作为FET的导电沟道，因此可以降低FET的泄露电流，从而进一步地降低存储器的刷新频率并且相应地减少存储器的功耗。
图1示出了根据本公开的一个实施例的电子设备100的示意图。在一个实施例中，电子设备100例如是智能手机。其它电子设备也是可能的，例如计算机、平板电脑或者其他智能终端设备。电子设备100包括集成电路组件10以及其它未示出的部件，诸如其它芯片、传感器等。集成电路组件10可以被形成为集成电路系统的至少一部分。在一个实施例中，集成电路组件10可以包括在诸如印刷电路板(printed circuit board,PCB)或柔性电路板(flexbile printed circuit,FPC)之类的电路板上的多个封装芯片。每个封装芯片内部可以封装有一个或多个芯片。在另一实施例中，集成电路组件10本身就是单个芯片，例如，内部集成了多个芯片的(system in a parckage,SiP)芯片。本公开在此不对集成电路组件10的形式做任何限制。
图2示出了根据本公开的一个实施例的电子组件10的简化框图。在一个实施例中，集成电路组件10例如可以包括其上安装有芯片的印刷电路板。集成电路组件10可以包括第一芯片12、第二芯片14和第三芯片16。集成电路组件10还可以包括其它未被示出的芯片或部件。第一芯片12可以与第二芯片14进行通信以传递命令和/或数据，并且还可以与第三芯片16进行通信以传递命令和/或数据。可以理解，第一芯片12、第二芯片14和第三芯片16还可以分别与其它芯片或部件进行通信。本公开对此不做任何限制。在一个实施例中，第一芯片12、第二芯片14和第三芯片16中的至少一个芯片例如是三维单体集成(monolithic three-dimension integration，M3D)芯片。M3D芯片通过把不同功能的组件，例如逻辑单元、存储单元、传感器单元、RF单元等，在垂直方向堆叠在一起，可以显著提高芯片的性能并降低功耗。同时，在本公开的一些实施例中，M3D芯片中的至少一部分可以包括OS FET以形成不同电路部件，并且该不同电路部件可以通过BEOL工艺集成而无需不同晶圆的键合，因此可以有效的降低器件成本。
在一个实施例中，第一芯片12可以是M3D芯片。在该M3D芯片中，底层电路12-1可以由CMOS工艺形成，随后在CMOS器件层12-1上方形成其中包括互连线的互连层12-2，并且随后在互连层12-2上方形成与后端工艺兼容的逻辑器件层12-3。在一个实施例中，由于存储器的制造工艺与后端工艺兼容，因此可以在互连层12-2中形成存储器30。备选地，还可以在逻辑器件层12-3中形成存储器30。可以理解，在逻辑器件层上方可能还具有更多的互连层和/或电路层，本公开对此不进行限制。在一种可选的情况中，底层电路也可以包括OS FET，而非CMOS FET。
图3示出了根据本公开的一个实施例的存储器30的示意框图。存储器20包括字译码器22、位译码器24、传感放大器26、存储阵列30和输入/输出电路28。输入/输出电路28控制字译码器22和位译码器24，从而控制存储阵列30的读写操作。传感放大器26被配置为在读操作模式下将对应的逻辑值从存储阵列30中读出。存储阵列30包括共用字线和位线的多个存储单元。存储器可以通过对字线和位线施加相应的电压来对存储单元进行寻址以进行读取或写入操作。应当理解，在一些MOS管中，漏极所接的线为位线，栅极所接的线为字线，字线可用于控制MOS管的导通或截止。
图4示出了根据本公开的一个实施例的存储器的一部分的示意电路图。在一个实施例中， 图4所示的电路可以是图3中的存储阵列30的一部分，并且包括4个存储单元C1、C2、C3和C4。可以理解，存储阵列30可以包括更多的存储单元。存储单元C1、C2、C3和C4具有基本上相同的结构，并且每个存储单元被分别耦合至字线和位线，以根据字线和位线上的电压进行读取或写入操作。在一个实施例中，在对存储单元C1进行写入或读取时，存储单元C1被选中进行写入或读取。为了便于描述，当存储单元被选中时，该存储单元所耦合到的字线以标记“WWL”和“RWL”分别表示，并且该存储单元的位线以标记“WBL”和“RBL”分别表示，其中“WWL”表示写字线(write word line)，“RWL”表示读字线(read word line)，“WBL”表示写位线(write bit line)，并且“RBL”表示读位线(read bit line)。而当存储单元未被选中时，该存储单元所耦合的字线或位线中的至少一个加以前缀“Un_”进行表示，例如“Un_WBL”、“Un_RBL”、“Un_WWL”或“Un_RWL”。图4中，存储单元C1被选中，而存储单元C2、C3和C4则未被选中。下面结合图5来描述存储单元的具体操作。
图5示出了根据本公开的一个实施例的存储单元C1的示意电路图。存储单元C1示出了一种2T0C型存储单元。存储单元C1包括第一晶体管T1和第二晶体管T2。第一晶体管T1和第二晶体管T2均包括氧化物晶体管沟道，因此存储单元C1的制造工艺可以与BEOL工艺兼容。第一晶体管T1包括耦合至第一字线WWL的第一栅极，耦合至第一位线WBL的第一漏极，以及第一源极。第二晶体管T2包括耦合至第一晶体管T1的第一源极的第二栅极，耦合至第二位线RBL的第二漏极，以及耦合至第二字线RWL的第二源极。第一晶体管T1的第一源极和第二晶体管T2的第二栅极之间的节点SP为存储单元C1的存储节点，用于存储数据。
在写入数据时，第二字线RWL和第二位线RBL电位被设置为电源电压Vdd，以抑制写操作的泄漏电流。进一步地，在写入逻辑“0”的操作时，第一字线WWL被设置为电源电压Vdd，并且第一位线WBL被设置为0V，存储节点SP的电压Vsp因此为0V，此时将逻辑“0”传入存储节点SP，即存储单元被写入为“0”的状态。在写入逻辑“1”的操作时，第一字线WWL和第一位线WBL均被设置为电源电压Vdd，存储节点SP的电压Vsp因此为Vdd与第一晶体管的导通阈值电压Vth的差值Vdd-Vth，此时将逻辑“1”传入存储节点SP，即存储单元被写入为“1”的状态。第一晶体管与第二晶体管阈值电压一致，为了提高逻辑“1”的准确性，电源电压Vdd可以大于2倍的阈值电压，即存储节点SP在被写入“1”时的电压Vsp大于晶体管的阈值电压Vth。
在读取数据时，可以在读操作之前对存储单元进行预充电。例如，将第一字线WWL设置为0V，将第一位线WBL设置为1/2Vdd，并且将第二字线RWL和第二位线RBL均置为Vdd。在读操作时，对于选中的存储单元，将第一字线WWL和第二字线RWL均设置为0V，并且将第一位线WBL设置为1/2Vdd。如果存储节点SP的数据为“0”时，第二晶体管T2未被导通，仅存在微量漏电流，第二位线RBL处的Vdd电压基本保持不变。如果存储节点SP的数据为“1”(晶体管T2的栅极电压大于晶体管的阈值电压Vth)，则第二晶体管T2被导通，第二位线RBL处的电位将大幅度下降电压差值ΔV从而接近0V。相关逻辑电路通过比较电压大小即可读出存储的数据。在一个实施例中，如果读出的数据为逻辑“1”时，可以进行额外的回写操作，即，在读取操作之后将逻辑“1”重新写入存储单元中。下面在表1中提供了图4中的各个位线和字线在各个读写操作中的电平示例值。
表1氧化物半导体2T0C存储架构读写操作真值表
  WWL WBL RWL RBL Un_WBL Un_RBL Un_WWL Un_RWL
写“0” Vdd 0 Vdd Vdd 0 Vdd 0 Vdd
写“1” Vdd Vdd Vdd Vdd Vdd Vdd 0 Vdd
预充电 0 1/2Vdd Vdd Vdd 1/2Vdd Vdd 0 Vdd
读取 0 1/2Vdd 0 Vdd-ΔV 1/2Vdd Vdd-ΔV 0 Vdd
相比于具有1T1C的架构的常规存储单元，由于根据本公开的实施例的存储单元采用了2T0C的架构，因此无需使用常规存储单元中的电容器。相比于晶体管，电容器通常具有较大的占用面积。因此，根据本公开的实施例的存储器可以显著减少存储器的尺寸并且提高芯片的集成度。此外，常规的基于1T1C架构的存储单元通过使用电流对电容器的充电和放电来存储数据，电容器的充电和放电通常会消耗相当的能量。相比而言，根据本公开的实施例的存储器以电压的方式存储数据，这显著降低了存储单元的功率消耗。进一步地，由于泄露电流的存在，常规的基于1T1C架构的存储单元通常每隔一段时间，例如64ms，就需要对存储单元刷新一次，即使该存储单元未被选中进行读取或写入操作。刷新使得该存储单元的数据不被丢失或不产生错误，但是刷新操作也消耗了比较多的能量。在本公开的实施例中，由于基于2T0C架构的存储单元的两个晶体管使用了OS材料的沟道，因此这两个晶体管T1和T2具有优异的驱动性能，具有非常小的泄露电流，并且存储单元的电源电压Vdd仅需大于晶体管的导通阈值电压Vth的两倍即可。对应地，存储单元C1的刷新频率远小于常规1T1C的存储单元的刷新频率，并且电源电压也可以进一步降低，因此进一步降低了存储器的功耗。
图6示出了根据本公开的一个实施例的存储单元的时序示意图。该时序示意图例如可以是存储单元C1的各个操作的时序示意图。该时序示意图分别包括写“0”操作、预充电操作、读“0”操作、待命操作、写“1”操作、预充电操作和读“1”操作期间第一字线WWL、第一位线WBL、第二字线RWL和第二位线RBL的设置电压，其中待命操作表示存储单元既不读取也不写入的操作阶段。在一个实施例中，还可以具有回写操作阶段。如果读出的数据为逻辑“1”时，可以进行额外进行回写操作，即在读操作后将逻辑“1”重新写入存储单元中，以提升存储的数据的准确性。另外，还可以在读取操作之前进行预充电操作，以提高数据读取的准确性。
图7示出了根据本公开的一个实施例的存储单元的写入操作的信号仿真图。该写入操作例如是向存储单元C1写入逻辑“1”。在1ns-19ns期间，第一位线WBL被置“1”，并且在2ns-18ns期间第一字线WWL被置“1”，从而将逻辑“1”写入存储节点SP。
图8示出了根据本公开的一个实施例的存储单元的读取操作的信号仿真图。该读取操作例如是从存储单元C1读取逻辑“1”。在24ns-36ns期间，第二字线RWL被置“0”，以进行读操作，并且第二字线RWL的电压为20mV，即为逻辑“1”。
图9示出了根据本公开的另一实施例的存储单元的写入操作的信号仿真图。该写入操作例如是向存储单元C1写入逻辑“0”。在1ns-19ns期间，第一位线WBL被置“0”，并且在2ns-18ns期间第一字线WWL被置“1”，从而将逻辑“0”写入存储节点SP。
图10示出了根据本公开的另一实施例的存储单元的读取操作的信号仿真图。该读取操作 例如是从存储单元C1读取逻辑“0”。在24ns-36ns期间，第二字线RWL被置“0”，以进行读操作，并且第二字线RWL的电压为1.02V，即为逻辑“0”。
图11示出了根据本公开的一个实施例的存储单元C11的示意结构图。在一个实施例中，存储单元C11例如是图5中的存储单元C1的一种具体实现方式。因此，关于图5-图10所描述的各个方面可以被应用于图11的存储单元C11。存储单元C11可以在BEOL工艺中形成在互连层12-2中。备选地，存储单元C11可以形成在逻辑器件层12-3中。本公开对此不进行限制。存储单元C11包括第一晶体管和第二晶体管，例如可以是图5中的第一晶体管T1和第二晶体管T2。第一晶体管包括第一OS沟道OSC1、第一栅极G12、第一电介质D12、第一漏极SD11和第一源极。第一栅极G12耦合至第一字线WWL。第一电介质D12位于第一OS沟道OSC1和第一栅极G12之间。进一步地，在一个实施例中，第一电介质D12可以包围第一栅极G12的下表面和两个侧表面。在本文中，部件或区域的侧表面表示与部件或区域的延伸方向基本上平行的表面，部件或区域的上表面和下表面则分别表示在部件或区域的延伸方向上的上部和下部的表面。例如，第一栅极G12的侧表面表示在图11中的竖直方向延伸的表面，两个侧表面分别与第一漏极SD11和区域GSD相面对，第一栅极G12的下表面表示在图11中的竖直延伸的下部的表面。第一栅极G12的下表面与第一OS沟道OSC1相面对，并且第一栅极G12的上表面与第一电介质D21相面对。第一漏极SD11耦合至第一位线WBL。
第二晶体管包括第二OS沟道OSC2、第二栅极、第二电介质D21、第二漏极SD21和第二源极SD22。在一个实施例中，第二栅极与第一源极一体形成为区域GSD以降低存储单元的尺寸和成本，并且相应地提高半导体芯片的集成度。在本文中，“A与B一体形成”表示A和B这两者被形成为单个部件或区域。换言之，从功能上而言，该单个部件或区域既可以作为A进行操作并且也可以同时作为B进行操作。备选地，第二栅极与第一源极可以分别形成，并且彼此直接电耦合。第二电介质D21位于第二OS沟道OSC2和第二栅极之间。第二漏极SD21耦合至第二位线RBL。第二源极SD22耦合至第二字线RWL。
在一个实施例中，第一晶体管还包括第三电介质D11和第三栅极G11。第三电介质D11和第一电介质D12位于第一OS沟道OSC1的相对的两侧。第三栅极G11耦合至第一字线WWL。第三电介质D11位于第三栅极G11和第一OS沟道OSC1之间。第二晶体管还包括第四电介质D22和第四栅极G22。第四电介质D22和第二电介质D21位于第二OS沟道OSC2的相对的两侧。第四栅极G22耦合至第一源极，例如通过图中未示出的导电连线或导电区域。第四电介质D22位于第四栅极G22和第二OS沟道OSC2之间。存储单元C11的读取和写入数据的操作方式可以参见上面针对图5的存储单元C1的描述，在此不再赘述。在图11中，第一晶体管和第二晶体管可以是双栅架构，其中第二晶体管被至少部分地堆叠在第一晶体管上方。第一晶体管和第二晶体管的背部栅极G11和G22相对分布，并且顶部栅极G12和区域GSD在同一层，例如顶部栅极G12和区域GSD均位于第一OS沟道OSC1和第二OS沟道OSC2之间的水平层中。第二晶体管的漏极SD21及其背部栅极G22在同一层，例如第二晶体管的漏极SD21及其背部栅极G22均位于第二OS沟道OSC2上方的水平层中。此外，在一些实施例中，源极SD22和区域GSD也可以在同一层中，例如源极SD22和区域GSD也可以位于第一OS沟道OSC1和第二OS沟道OSC2之间的水平层中。第一晶体管的源极与第二晶体管的栅极相连接或一体形成，因此存储单元C1具有低的占用面积低和良好的微缩能力。通过使用双栅晶体管，可以更为有效地控制晶体管的导通和关断，以进一步减少泄露电流，并且由此可以具有更低的刷新频率和功耗。虽然在图11中示出了双栅晶体管的结构，但是其 它类型的晶体管或其它布置的双栅晶体管是可能的。例如，可以使用单栅晶体管、鳍式晶体管(fin field effect transistor,FinFET)或环栅(gate-all-around,GAA)晶体管。
图12示出了根据本公开的另一实施例的存储单元C12的示意结构图。在一个实施例中，存储单元C12例如是图5中的存储单元C1的另一种具体实现方式。因此，关于图5-图10所描述的各个方面可以被应用于图12的存储单元C12。存储单元C12可以在BEOL工艺中形成在互连层12-2中。备选地，存储单元C12可以形成在逻辑器件层12-3中。本公开对此不进行限制。存储单元C12包括第一晶体管和第二晶体管，例如可以是图5中的第一晶体管T1和第二晶体管T2。第一晶体管例如可以是GAA晶体管，并且包括沿水平方向延伸的第一OS沟道OSC1、第一源极SD12、第一漏极SD11、位于第一源极SD12和第一漏极SD11之间的第一栅极G13、和第一电介质D13，其中第一OS沟道OSC1的端部表面与第一源极SD12和第一漏极SD11接触的端部表面。在另一些实施例中，第一OS沟道OSC1的端部可以分别嵌入在第一源极SD12和第一漏极SD11中，即第一OS沟道OSC1的端部表面和端部的侧表面与第一源极SD12和第一漏极SD11接触。在该实施例中，端部表面表示在OS沟道的延伸方向(在图12中，针对第一OS沟道OSC1的端部延伸方向为水平方向，而针对第二OS沟道的OSC2的端部延伸方向为纵向)上最外侧并且与OS沟道的延伸方向成一定角度并且非平行(例如垂直)的表面，侧表面表示在OS沟道的延伸方向上的、与端部表面成一定角度并且非平行(例如垂直)的表面。下文的端部表面和侧表面具有相同的含义，并且不再赘述。在本文中，在OS沟道为圆柱形或为椭圆柱形的情形下，嵌入表示OS沟道的端部表面和侧表面的与端部表面相接的部分与漏极和源极全接触而无暴露部分。第一栅极G13耦合至第一字线WWL。第一电介质D13位于第一OS沟道OSC1和第一栅极G13之间。进一步地，在一个实施例中，第一电介质D13可以包围第一栅极G13的下表面和两个侧表面。第一漏极SD11耦合至第一位线WBL。在一个实施例中，第一电介质D13围绕第一OS沟道OSC1的至少一部分的侧表面，并且第一栅极G13围绕第一电介质D13。
第二晶体管例如可以是GAA晶体管，并且包括沿竖直方向延伸的第二OS沟道OSC2、第二漏极SD21、第二源极SD22、位于第二漏极SD21和第二源极SD22之间的第二栅极G23、和第二电介质D23，其中第二OS沟道OSC2的端部表面与第二漏极SD21和第二源极SD22接触的端部表面。在另一些实施例中，第二OS沟道OSC2的端部可以分别嵌入在第二漏极SD21和第二源极SD22中，即第二OS沟道OSC2的端部表面和端部的侧表面与第二漏极SD21和第二源极SD22接触。在一个实施例中，第二栅极G23与第一源极SD12可以分别形成，并且彼此直接电耦合。备选地，第二栅极G23与第一源极SD12一体形成为单个区域以降低存储单元的尺寸和成本，并且相应地提高半导体芯片的集成度。第二电介质D23位于第二OS沟道OSC2和第二栅极G23之间。进一步地，在一个实施例中，第二电介质D23可以包围第二栅极G23的上表面、下表面和侧表面。如上文所述，部件或区域的侧表面表示在部件或区域的延伸方向上的表面或与部件或区域的延伸方向基本上平行的表面，部件或区域的上表面和下表面则分别表示在部件或区域的延伸方向上的上部和下部的表面。例如，在图12中，第二栅极G23的上表面为第二栅极G23的与第二漏极SD21的一部分相对的表面，第二栅极G23的下表面为第二栅极G23的与第二源极SD22的一部分相面对的表面，第二栅极G23的侧表面为第二栅极G23在延伸方向(竖直方向)上的位于上表面和下表面之间的表面。第二漏极SD21耦合至第二位线RBL。第二源极SD22耦合至第二字线RWL。第二电介质围绕第二氧化物半导体沟道的至少一部分的侧表面；以及第二栅极围绕第二电介质。在图12中，第 一晶体管具有水平OS沟道的环栅结构，并且第二晶体管具有竖直OS沟道的环栅结构。通过使用GAA晶体管，可以更为有效地控制晶体管的导通和关断，以进一步减少泄露电流，并且由此可以具有更低的刷新频率和功耗。虽然在图12中示出了GAA晶体管的结构，但是其它类型的晶体管或其它布置的GAA晶体管是可能的。例如，可以使用双栅晶体管，例如图12中所示的环绕的栅极可以为彼此电耦合的上部条状栅极和下部条状栅极，并且OS沟道为纵向截面为矩形的条状沟道。在此情形下，第一OS沟道OSC1的端部表面为与第一源极SD12和第一漏极SD11接触的两个表面，第一OS沟道OSC1的上表面和下表面与第一电介质D13接触，而第一OS沟道OSC1的侧表面则是与端部表面、上表面和下表面均成一定角度并且非平行(例如垂直)的表面。第二OS沟道OSC2的端部表面为与第二源极SD22和第二漏极SD21接触的两个表面，第二OS沟道OSC2的上表面与第二漏极SD21的一部分相面对，第二OS沟道OSC2的下表面与第二源极SD22的一部分相面对，而第二OS沟道OSC2的侧表面则是与端部表面、上表面和下表面均成一定角度并且非平行(例如垂直)的表面。
图13示出了根据本公开的又一实施例的存储单元C13的示意结构图。在一个实施例中，存储单元C13例如是图5中的存储单元C1的又一种具体实现方式。因此，关于图5所描述的各个方面可以被应用于图13的存储单元C13。此外，存储单元C13具有与图7的存储单元C12基本上相似的架构，因此关于存储单元C12的各个方面的描述可以被应用于存储单元C13。存储单元C13与存储单元C12的一个不同之处在于：第一OS沟道OSC1的两个端部被分别嵌入在第一源极SD11和第一漏极SD12中，并且第二OS沟道OSC2的两个端部被分别嵌入在第二源极SD21和第二漏极22中。换言之，第一OS沟道OSC1的两个端部的端部表面和侧表面均与相应的源极或漏极直接接触，并且第二OS沟道OSC2的两个端部的端部表面和侧表面均与相应的源极或漏极直接接触。OS材料从材料本身的性质而言一般是n型掺杂。不像Si沟道器件，目前无法通过离子注入等方法对沟道区域进行掺杂，并且离子注入的方式与BEOL工艺不兼容。因此OS FET是无节(junctionless)型器件，即沟道与源极和漏极的掺杂浓度是基本上相同。为了保证器件的正常开关特性，沟道的掺杂浓度不能太高，否则FET无法有效的关断。通过研究发现，由于沟道掺杂的限制，因此导致OS FET的驱动能力和响应速度不甚理想，尤其是在诸如纳米量级之类的小沟道尺寸的FET中。在本公开的一些实施例中，提出使用全包覆或部分包覆的接触结构来有效地增大源极和漏极与沟道接触的接触面积，从而提升OS FET的驱动能力和响应速度。具体而言，源极和漏极的接触面积越大，则接触电阻越小。OS FET器件的总电阻越小，在相同电压下电流会越大，从而提升驱动能力和响应速度。
存储单元C13与存储单元C12的另一不同之处在于：第一晶体管还包括位于第一OS沟道OSC1内部的第一嵌入电介质DF1；以及第二晶体管还包括位于第二OS沟道OSC2内部的第二嵌入电介质DF2。在本文中，嵌入表示OS沟道的端部表面和侧表面的与端部表面相接的部分与漏极和源极全接触而无暴露部分。具有OS沟道的晶体管是无节型晶体管，并且OS沟道也是具有一定的掺杂浓度，例如n型掺杂。对于掺杂的OS沟道，晶体管器件的开关特性对沟道厚度比较敏感。当采用实心结构的OS沟道时，孔洞尺寸(OS沟道的直径)的变化会导致器件与器件之间的波动，例如不同晶体管的开关阈值电压可能会因此而不同，这对于晶体管的控制而言非常不利。相比之下，当在OS沟道中嵌入电介质时，OS沟道的厚度可以通过原子层沉积精确控制。因此，对于各个晶体管而言，其电学性能可以具有连续性和一致性，从而可以简化芯片电路设计和控制。
图14示出了根据本公开的一个实施例的用于制造存储器的方法1400的流程图。该方法可以用于制造图3-图13中所示的半导体器件，因此上文针对图3-图13所述的各个方面可以应用于方法1400，在此不再赘述。在1402，在绝缘层上形成第一晶体管。在一个实施例中，绝缘层例如是底层电路层12-1与互连层12-2的界面处的绝缘层，其中互连线可以穿过部分的绝缘层以实现与底层电路的电学耦合。备选地，绝缘层例如是互连层12-2和逻辑器件层12-3的界面处的绝缘层，其中互连线可以穿过部分的绝缘层以实现与逻辑器件的电学耦合。在图14所示的实施例中，“形成”表示一个或多个工艺步骤的集合，以用于制造一个或多个器件结构或区域。例如“形成”可以包括使用涂覆光刻胶、曝光、注入、沉积、蚀刻等工艺步骤。可以根据需要选择一个或多个具体的工艺来形成特定的区域或结构。
在一些实施例中，在绝缘层上形成第一晶体管包括：在绝缘层上方形成第一氧化物半导体沟道；在第一氧化物半导体沟道上形成第一电介质；在第一电介质上形成第一栅极，第一栅极耦合至第一字线；在绝缘层上方形成第一漏极，第一漏极耦合至第一位线；以及在绝缘层上方第一源极。
在一些实施例中，在绝缘层上形成第一晶体管还包括：在第一氧化物半导体沟道上形成第三电介质，第三电介质和第一电介质位于第一氧化物半导体沟道的相对的两侧；在第三电介质上形成第三栅极，第三栅极耦合至第一字线，第三电介质位于第三栅极和第一氧化物半导体沟道之间。在第一氧化物半导体沟道上形成第一电介质包括：在第一氧化物半导体沟道上形成围绕第一氧化物半导体沟道的至少一部分的侧表面的第一电介质。在第一电介质上形成第一栅极包括：在第一电介质上形成围绕第一电介质的侧表面的第一栅极。
在一些实施例中，在绝缘层上方形成第一氧化物半导体沟道还包括：在第一氧化物半导体沟道内部形成第一嵌入电介质。在绝缘层上形成第一晶体管包括在绝缘层上的互连层中形成第一晶体管。
在1404，在绝缘层上形成第二晶体管。在一些实施例中，在绝缘层上形成第二晶体管包括：在绝缘层上方形成第二氧化物半导体沟道；在第二氧化物半导体沟道上形成第二电介质；在第二电介质上形成第二栅极，第二栅极耦合至第一源极；在绝缘层上方形成第二漏极，第二漏极耦合至第二位线；以及在绝缘层上方形成第二源极，第二源极耦合至第二字线。
在一些实施例中，在绝缘层上形成第二晶体管还包括：在第二氧化物半导体沟道上形成第四电介质，第四电介质和第二电介质位于第二氧化物半导体沟道的相对的两侧；以及在第四电介质上形成第四栅极，第四栅极耦合至第一源极，第四电介质位于第四栅极和第二氧化物半导体沟道之间。在第二氧化物半导体沟道上形成第二电介质包括：在第二氧化物半导体沟道上形成围绕第二氧化物半导体沟道的至少一部分的侧表面的第二电介质。在第二电介质上形成第二栅极包括：在第二电介质上形成围绕第二电介质的侧表面的第二栅极。
在一些实施例中，在绝缘层上方形成第一氧化物半导体沟道还包括：在第二氧化物半导体沟道内部形成第二嵌入电介质。在绝缘层上形成第二晶体管包括在绝缘层上的互连层中形成第二晶体管。
尽管已经采用特定于结构特征和/或方法逻辑动作的语言描述了本主题，但是应当理解所附权利要求书中所限定的主题未必局限于上面描述的特定特征或动作。相反，上面所描述的特定特征和动作仅仅是实现权利要求书的示例形式。

Claims (20)

  1. 一种存储器，包括：
    第一晶体管，包括：
    第一氧化物半导体沟道；
    第一栅极，耦合至第一字线；
    第一电介质，位于所述第一氧化物半导体沟道和第一栅极之间；
    第一漏极，耦合至第一位线；以及
    第一源极；以及
    第二晶体管，包括：
    第二氧化物半导体沟道；
    第二栅极，耦合至所述第一源极；
    第二电介质，位于所述第二氧化物半导体沟道和所述第二栅极之间；
    第二漏极，耦合至第二位线；以及
    第二源极，耦合至第二字线。
  2. 根据权利要求1所述的存储器，其中所述第一晶体管还包括：
    第三电介质，所述第三电介质和所述第一电介质位于所述第一氧化物半导体沟道的相对的两侧；以及
    第三栅极，耦合至所述第一字线，所述第三电介质位于所述第三栅极和所述第一氧化物半导体沟道之间。
  3. 根据权利要求1或2所述的存储器，其中所述第二晶体管还包括：
    第四电介质，所述第四电介质和所述第二电介质位于所述第二氧化物半导体沟道的相对的两侧；以及
    第四栅极，耦合至所述第一源极，所述第四电介质位于所述第四栅极和所述第二氧化物半导体沟道之间。
  4. 根据权利要求1所述的存储器，其中所述第一电介质围绕所述第一氧化物半导体沟道的至少一部分的侧表面；以及
    所述第一栅极围绕所述第一电介质。
  5. 根据权利要求1或4所述的存储器，其中所述第二电介质围绕所述第二氧化物半导体沟道的至少一部分的侧表面；以及
    所述第二栅极围绕所述第二电介质。
  6. 根据权利要求1-5中任一项所述的存储器，其中所述第一源极和所述第二栅极一体形成为单个区域。
  7. 根据权利要求1-6中任一项所述的存储器，其中所述第一氧化物半导体沟道被设置为沿第一方向延伸；
    所述第一栅极被设置为在所述第一源极和所述第一漏极之间沿所述第一方向延伸；
    所述第一电介质包覆所述第一栅极的下表面和两侧侧表面；
    所述第二氧化物半导体沟道被设置为沿第二方向延伸，所述第二方向与所述第一方向垂直；
    所述第二栅极被设置为在所述第二源极和所述第二漏极之间沿所述第二方向延伸；以及
    所述第二电介质包覆所述第二栅极的上表面、下表面和侧表面。
  8. 根据权利要求1-6中任一项所述的存储器，其中所述第一氧化物半导体沟道被设置为沿第一方向延伸；
    所述第一源极和所述第一漏极被设置在所述第一氧化物半导体沟道的相同侧；
    所述第二氧化物半导体沟道被设置为沿所述第一方向延伸；以及
    所述第二源极和所述第二漏极被设置在所述第二氧化物半导体沟道的相对侧。
  9. 根据权利要求1-8中任一项所述的存储器，其中所述第一晶体管还包括位于所述第一氧化物半导体沟道内部的第一嵌入电介质；以及
    所述第二晶体管还包括位于所述第二氧化物半导体沟道内部的第二嵌入电介质。
  10. 根据权利要求1-9中任一项所述的存储器，其中所述第一氧化物半导体沟道的两个端部被分别嵌入在所述第一源极和所述第一漏极中；以及
    所述第二氧化物半导体沟道的两个端部被分别嵌入在所述第二源极和所述第二漏极中。
  11. 根据权利要求1-10中任一项所述的存储器，其中所述存储器被设置在互补型金属氧化物晶体管(CMOS)电路的上方。
  12. 根据权利要求1-11中任一项所述的存储器，其中所述存储器被设置在金属互连层中。
  13. 一种芯片，包括：衬底和根据权利要求1-12中任一项所述的存储器，其中，
    所述衬底包括互补型金属氧化物晶体管电路，以及
    所述存储器被设置在所述衬底的上方。
  14. 一种电子组件，包括：
    电路板，以及
    根据权利要求13所述的芯片，被安装在所述电路板上。
  15. 一种电子设备，包括：
    电源装置，以及
    根据权利要求14所述的电路板，所述电源装置为所述电路板供电。
  16. 一种用于制造存储器的方法，包括：
    在绝缘层上形成第一晶体管，包括：
    在所述绝缘层上方形成第一氧化物半导体沟道；
    在所述第一氧化物半导体沟道上形成第一电介质；
    在所述第一电介质上形成第一栅极，所述第一栅极耦合至第一字线；
    在所述绝缘层上方形成第一漏极，所述第一漏极耦合至第一位线；以及
    在所述绝缘层上方形成第一源极；以及
    在所述绝缘层上形成第二晶体管，包括：
    在所述绝缘层上方形成第二氧化物半导体沟道；
    在所述第二氧化物半导体沟道上形成第二电介质；
    在所述第二电介质上形成第二栅极，所述第二栅极耦合至所述第一源极；
    在所述绝缘层上方形成第二漏极，所述第二漏极耦合至第二位线；以及
    在所述绝缘层上方形成第二源极，所述第二源极耦合至第二字线。
  17. 根据权利要求16所述的方法，其中
    在所述绝缘层上形成第一晶体管还包括：
    在所述第一氧化物半导体沟道上形成第三电介质，所述第三电介质和所述第一 电介质位于所述第一氧化物半导体沟道的相对的两侧；
    在所述第三电介质上形成第三栅极，所述第三栅极耦合至所述第一字线，所述第三电介质位于所述第三栅极和所述第一氧化物半导体沟道之间；以及
    在所述绝缘层上形成第二晶体管还包括：
    在所述第二氧化物半导体沟道上形成第四电介质，所述第四电介质和所述第二电介质位于所述第二氧化物半导体沟道的相对的两侧；以及
    在所述第四电介质上形成第四栅极，所述第四栅极耦合至所述第一源极，所述第四电介质位于所述第四栅极和所述第二氧化物半导体沟道之间。
  18. 根据权利要求16所述的方法，其中
    在所述第一氧化物半导体沟道上形成所述第一电介质包括：在所述第一氧化物半导体沟道上形成围绕所述第一氧化物半导体沟道的至少一部分的侧表面的所述第一电介质；
    在所述第二氧化物半导体沟道上形成所述第二电介质包括：在所述第二氧化物半导体沟道上形成围绕所述第二氧化物半导体沟道的至少一部分的侧表面的所述第二电介质；
    在所述第一电介质上形成所述第一栅极包括：在所述第一电介质上形成围绕所述第一电介质的侧表面的所述第一栅极；以及
    在所述第二电介质上形成所述第二栅极包括：在所述第二电介质上形成围绕所述第二电介质的侧表面的所述第二栅极。
  19. 根据权利要求16-18中任一项所述的方法，其中在所述绝缘层上方形成所述第一氧化物半导体沟道还包括：在所述第一氧化物半导体沟道内部形成第一嵌入电介质；以及
    在所述绝缘层上方形成所述第一氧化物半导体沟道还包括：在所述第二氧化物半导体沟道内部形成第二嵌入电介质。
  20. 根据权利要求16-19中任一项所述的存储器，其中在绝缘层上形成所述第一晶体管包括：在所述绝缘层上的金属互连层中形成所述第一晶体管；以及
    在绝缘层上形成所述第二晶体管包括：在所述绝缘层上的所述金属互连层中形成所述第二晶体管。
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