WO2024007529A1 - 驱动电路、显示模组及显示装置 - Google Patents

驱动电路、显示模组及显示装置 Download PDF

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Publication number
WO2024007529A1
WO2024007529A1 PCT/CN2022/137574 CN2022137574W WO2024007529A1 WO 2024007529 A1 WO2024007529 A1 WO 2024007529A1 CN 2022137574 W CN2022137574 W CN 2022137574W WO 2024007529 A1 WO2024007529 A1 WO 2024007529A1
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Prior art keywords
terminal
signal
terminals
control
switch
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PCT/CN2022/137574
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English (en)
French (fr)
Inventor
周满城
康报虹
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惠科股份有限公司
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Publication of WO2024007529A1 publication Critical patent/WO2024007529A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the present application relates to the field of display technology, and in particular to a driving circuit, a display module having the driving circuit, and a display device having the display module.
  • LED display devices such as Light Emitting Diode (OLED) displays, with the development of display technology, especially the development of small spacing of light-emitting elements, LED display devices have significantly increased requirements for row driving.
  • LED display devices such as Light Emitting Diode (OLED) displays, with the development of display technology, especially the development of small spacing of light-emitting elements, LED display devices have significantly increased requirements for row driving.
  • the driving circuit of the above-mentioned LED display device taking the common anode driving circuit as an example, when the data signal of the control row is low, the anode voltage of the light-emitting element is pulled high. At this time, the width of the data signal of the control column can be used. The light-emitting elements produce light of different brightnesses. At this time, during the row scanning switching process, the residual voltage of the row scanning line generates parasitic capacitance. However, when scanning other rows, due to the short switching interval of row scanning, the charge on the parasitic capacitance has not yet been released. At this time, the parasitic capacitance and other row scanning signals work together to cause the light-emitting element that should be turned off to emit light by mistake. This results in afterglow on the display, that is, abnormal afterglow, which affects the display effect and user experience.
  • the purpose of this application is to provide a driving circuit, a display module and a display device.
  • the driving circuit is provided with the signal control unit and the switch unit to selectively control multiple scanning signal input terminals to receive or stop receiving the scanning signal, effectively preventing parasitic capacitance from continuing to increase during switching time and aggravating the charge.
  • embodiments of the present application provide a driving circuit, which includes at least one signal control unit, a switch unit, a pixel array unit and a charge release unit, wherein,
  • Each of the signal control units includes a plurality of scan input terminals and an output signal terminal, the scan input terminal receives a scan signal, and the signal control unit outputs a control signal from the output signal terminal according to the scan signal;
  • the switch unit includes a switch input terminal, a plurality of first switch output terminals and a plurality of second switch output terminals.
  • the switch input terminal is electrically connected to the output signal terminal and receives the control signal;
  • the pixel array unit includes a plurality of scan signal input terminals and a plurality of charge output terminals, wherein a plurality of the scan signal input terminals are electrically connected to a plurality of the first switch output terminals and a plurality of the second switch output terminals at the same time. terminal, the first switch output terminal or the second switch output terminal is selectively connected to the scanning signal input terminal according to the control signal, so that the scanning signal is selectively transmitted to the pixel array unit;
  • the charge release unit includes a plurality of charge release terminals, each of the charge release terminals is electrically connected to each of the charge output terminals, and the charge release unit releases at least part of the charge of the parasitic capacitance generated by the pixel array unit.
  • the present application also provides a display module.
  • the display module includes a display panel and a plurality of the above-mentioned driving circuits.
  • the driving circuit is electrically connected to the display panel.
  • the driving circuit is used to drive the display panel.
  • the above display panel displays the screen.
  • the present application also provides a display device.
  • the display device includes a power module and the above-mentioned display module.
  • the power module is disposed on the non-display surface of the display module.
  • the power module The group is used to provide power supply voltage for image display by the display module.
  • the signal control unit and the switch unit are provided to selectively control multiple scanning signal input terminals to receive or stop receiving the scanning signal input terminals.
  • Scan signal Effectively control the driving circuit to normally transmit the scanning signal to the pixel array unit during line scanning, and stop transmitting the scanning signal to the pixel array unit during the line scanning switching time, thereby avoiding residual scanning during the line scanning switching time.
  • the signal charge continues to generate parasitic capacitance, which effectively avoids the continued increase in parasitic capacitance during switching time, aggravating the discharge workload of the charge release unit, and the problem of abnormal afterglow caused by insufficient discharge capability of the charge release unit.
  • the signal control unit and the switch unit cooperate to control multiple scan lines to be short-circuited during the switching time, thereby increasing the discharge rate of charges on the capacitors electrically connected to the corresponding scan lines.
  • the charge discharge rate on the capacitance of the corresponding scan line is increased by a factor equal to the number of scan lines compared to when the scan lines are not short-circuited. It greatly reduces the problem of abnormal afterglow caused by the charge on the parasitic capacitance being not discharged cleanly or not being released sufficiently in time, thereby effectively improving the accuracy of the driving circuit and ensuring the display of the display module. Effect.
  • Figure 1 is a schematic structural diagram of a display device disclosed in an embodiment of the present application.
  • Figure 2 is a schematic structural diagram of a display module in the display device shown in Figure 1;
  • Figure 3 is a circuit schematic diagram of a driving circuit of a display module in the display device shown in Figure 1;
  • FIG. 4 is a schematic diagram of the specific circuit structure of the driving circuit of the first embodiment shown in FIG. 3 .
  • Figure 5 is a schematic diagram of the specific circuit structure of the drive circuit of the second embodiment shown in Figure 3;
  • FIG. 6 is a schematic diagram of the specific circuit structure of the driving circuit of the third embodiment shown in FIG. 3 .
  • connection and “connection” mentioned in this application include direct and indirect connections (connections) unless otherwise specified.
  • the directional terms mentioned in this application such as “up”, “down”, “front”, “back”, “left”, “right”, “inside”, “outside”, “side”, etc., are only Reference is made to the direction of the attached drawings.
  • connection should be understood in a broad sense.
  • it can be a fixed connection or a detachable connection.
  • Ground connection, or integral connection can be a mechanical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium; it can be an internal connection between two components.
  • connection should be understood in a broad sense.
  • it can be a fixed connection or a detachable connection.
  • Ground connection, or integral connection can be a mechanical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium; it can be an internal connection between two components.
  • the specific meanings of the above terms in this application can be understood on a case-by-case basis.
  • the terms “first”, “second”, etc. in the description, claims, and drawings of this application are used to distinguish different objects, rather than describing a specific sequence.
  • the terms “include”, “can include”, “include”, or “can include” used in this application indicate the existence of the corresponding disclosed functions, operations, elements, etc., and do not limit other one or more more Functions, operations, components, etc.
  • the term “comprises” or “comprises” indicates the presence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, but does not exclude the presence or addition of one or more other features, numbers, steps, Operations, elements, parts, or combinations thereof, are intended to cover non-exclusive inclusion.
  • a display device may generally include a display panel and a backlight assembly, wherein the display panel is mounted to the light exit side of the backlight assembly, and the backlight assembly is used to provide backlight to the display panel to adjust the display panel display.
  • the backlight assembly is used to provide backlight to the display panel to adjust the display panel display.
  • the backlight assembly is provided with a common electrode, a pixel electrode, a data line and a liquid crystal molecule, where the common electrode voltage is a reference voltage , changing the data signal size of the data line causes the pixel electrode to release capacitance to varying degrees, thereby forming electric fields of different sizes between the common electrode and the pixel electrode, and the electric fields of different sizes control the liquid crystal molecules in the backlight assembly to deflect to varying degrees. , causing the display panel to display different grayscale images.
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • FIG. 1 is a schematic structural diagram of a display device disclosed in an embodiment of the present application.
  • the display device 100 provided by the embodiment of the present application may at least include a display module 10 , a power module 20 and a support frame 30 .
  • the display module 10 is fixed to the support frame 30
  • the power module 20 is fixed to the support frame 30 .
  • the group 20 is disposed on the back of the display module 10 , that is, the non-display surface of the display module 10 , that is, the side of the display module 10 facing away from the user.
  • the display module 10 is used to display images.
  • the power module 20 is electrically connected to the display module 10 and is used to provide power supply voltage for the display module 10 to display images.
  • the support frame 30 is the The display module 10 and the power module 20 provide support and protection.
  • the display module 10 also has a display surface arranged opposite to the non-display surface, that is, the front of the display module 10 , that is, the side of the display module 10 facing the user.
  • the display surface is used to face a user using the display device 100 to display images.
  • FIG. 2 is a schematic structural diagram of the display module 10 in the display device 100 shown in FIG. 1 .
  • the display module 10 may at least include a display panel 13 and a backlight module (BM) 17, wherein the display panel 13 is disposed on the light emitting side of the backlight module 17,
  • the backlight module 17 is used to provide display light to the display panel 13 , and the display panel 13 emits corresponding light according to the image data to be displayed to perform image display.
  • the display module 10 may also include other elements or components, such as a signal processor module, a signal sensing module, etc.
  • the display panel 13 at least includes an array substrate (AS) 131 , a color filter substrate 133 , and a liquid crystal layer 132 sandwiched between the array substrate 131 and the color filter substrate 133 .
  • a corresponding electric field is generated between the array substrate 131 and the color filter substrate 133 according to the image data to be displayed, thereby controlling the liquid crystal molecules in the liquid crystal layer 132 to deflect at a corresponding angle to emit light of corresponding brightness to perform image processing.
  • the display panel 13 may be a Micro-LED display panel, an OLED display panel or a Mini-LED display panel that adopts a passive addressing (PM) driving mode.
  • PM passive addressing
  • FIG. 3 is a schematic circuit diagram of the driving circuit 11 of the display module 10 in the display device 100 shown in FIG. 1 .
  • the display module 10 at least further includes a driving circuit 11.
  • the driving circuit 11 can be disposed in the peripheral area of the display panel 13, and the driving circuit 11 is electrically connected to the display panel 13. Connection for powering the display panel 13 and providing driving signals.
  • the driving circuit 11 is electrically connected to the backlight module 17 , and the driving circuit 11 and the backlight module 17 cooperate to cause the display panel 13 to display images.
  • the driving circuit 11 may include at least one signal control unit 40 , a switch unit 50 , a pixel array unit 60 and a charge release unit 70 .
  • each of the signal control units includes an output signal terminal and a plurality of scan input terminals, the scan input terminals receive scan signals, and the signal control unit outputs a control signal from the output signal terminals according to the scan signals.
  • the switch unit includes a switch input terminal, a plurality of first switch output terminals and a plurality of second switch output terminals.
  • the switch input terminal is electrically connected to the output signal terminal and receives the control signal.
  • the pixel array unit includes a plurality of scan signal input terminals and a plurality of charge output terminals, wherein a plurality of the scan signal input terminals are electrically connected to a plurality of the first switch output terminals and a plurality of the second switch output terminals at the same time. terminal, the first switch output terminal or the second switch output terminal is selectively connected to the scanning signal input terminal according to the control signal, so that the scanning signal is selectively transmitted to the pixel array unit.
  • the charge release unit includes a plurality of charge release terminals, each of the charge release terminals is electrically connected to each of the charge output terminals, and the charge release unit releases at least part of the charge of the parasitic capacitance generated by the pixel array unit.
  • k is an integer greater than 1 and less than or equal to n
  • n is an integer greater than or equal to 2. This is consistent with the quantity “multiple” and “several” explained above, so the limit on the number of k or n does not constitute a restriction on the technical solution. , just to make the technical solution clearer.
  • each of the signal control units 40 includes k scan input terminals 42 and output signal terminals 44 .
  • the k scanning input terminals 42 receive k scanning signals, that is, each of the scanning input terminals 42 receives a corresponding scanning signal.
  • the signal control unit 40 outputs a control signal at the first potential or the second potential from the output signal terminal 44 according to k scan signals.
  • the scan input terminal 42 may use a scan drive circuit or a row drive circuit to receive the scan signal.
  • Each of the switch units 50 includes a switch input terminal 51 , k first switch output terminals 52 and k second switch output terminals 53 .
  • the switch input terminal 51 is electrically connected to the output signal terminal 44 correspondingly.
  • the pixel array unit 60 includes n scanning signal input terminals 61 and n charge output terminals 63 .
  • the charge output terminal 63 is electrically connected to the charge release unit 70 .
  • the k scanning signal input terminals 61 are electrically connected to the k first switch output terminals 52 and the k second switch output terminals 53 at the same time.
  • the switch unit 50 selectively conducts the scanning signal input terminal 61 and the first switch output terminal 52 or the second switch output terminal 53 according to the control signal. Further, the scanning signal input terminal 61 is selectively turned on to transmit the corresponding scanning signal to the pixel array unit 60 through the scanning signal input terminal 61 .
  • the scanning signal is generated by other circuit structures of the driving circuit 11 and can be transmitted to the scanning signal input terminal 61 .
  • the charge release unit 70 includes n charge release terminals 73, each of the charge release terminals 73 is electrically connected to each of the charge output terminals 63, and the charge release unit 70 is used to release the charge generated by the pixel array unit 60. part of the parasitic capacitance charge. Specifically, each of the charge release terminals 73 is used to guide the release of charges generated by the parasitic capacitance of the corresponding scanning line.
  • k is an integer greater than 1 and less than or equal to n
  • n is an integer greater than or equal to 2. It can be understood that the signal control unit 40 and the switch unit 50 can only adjust part of the scan signal input terminals 61 of the pixel array unit 60 to selectively receive the scan signal. For example, the signal control unit 40 and the switch unit 50 can adjust the scanning lines that may affect each other according to the actual situation.
  • the signal control unit 40 and the switch unit 50 are added to the drive circuit 11 so that they stop transmitting signals to the scan signal input terminal 61 through the scan signal input terminal 61 during the time of switching scanning lines.
  • the light emitting unit 65 of the pixel array unit 60 transmits the scanning signal. This can effectively prevent the parasitic capacitance of the pixel array unit 60 from increasing during the switching scan line time, causing the charge release unit 70 to be unable to fully discharge the charge on the parasitic capacitance during the interval time, thereby causing the pixel array unit to 60 abnormal light emission problem. Therefore, the driving accuracy of the driving circuit 11 is effectively improved, thereby eliminating the afterglow phenomenon and ensuring the display effect of the display module 10 .
  • the pixel array unit 60 includes n scan lines (Scan lines) S1 to Sn arranged in a grid shape and extending along the first direction F1 and m extending along the second direction F2. Data lines D1 ⁇ Dm.
  • the first direction F1 and the second direction F2 are perpendicular to each other, and between the plurality of scanning lines S1 to Sn, between the plurality of data lines D1 to Dm, and between the scanning lines S1 to Sn and the The data lines D1 to Dm are all insulated from each other.
  • the plurality of scan lines S1 to Sn are arranged at intervals along the second direction F2 and are insulated from each other, and the plurality of data lines D1 to Dm are arranged at intervals along the first direction F1
  • the plurality of scan lines S1 to Sn and the plurality of data lines D1 to Dm are arranged to be insulated from each other.
  • Each of the scan lines is used to transmit the scan signal to the light emitting unit 65 through the scan signal input terminal 61 .
  • m is a positive integer.
  • Light-emitting units 65 are respectively provided at the intersections of the plurality of scan lines S1-Sn and the data lines D1-Dm. Specifically, the light-emitting unit 65 is disposed between any two adjacent scan lines and any two adjacent data lines, and the light-emitting units 65 located in the same column are connected to the same data line. Lines are electrically connected, and the light-emitting units 65 located in the same row are electrically connected to the same scanning line. In this embodiment of the present application, a plurality of the light-emitting units 65 are distributed in an array. In this embodiment of the present application, each of the data lines is electrically connected to the data signal input terminal, and each of the scan lines is electrically connected to the scan signal input terminal.
  • the pixel array unit 60 includes m data signal input terminals 62, n scanning signal input terminals 61 and n*m light emitting units 65.
  • Each of the scanning signal The input terminal 61 is electrically connected to the first poles of the m light-emitting units 65, and each of the data signal input terminals 62 is electrically connected to the second poles of the n light-emitting units 65.
  • the scanning signal passes through the scanning The signal input terminal is transmitted to the light-emitting unit to control the turning on and off of the light-emitting unit.
  • each of the scanning signal input terminals 61 is electrically connected to the first poles of the m light-emitting units 65 corresponding to one row, and each of the data signal input terminals 62 is connected to the n light-emitting units corresponding to one column.
  • the second pole of 65 is electrically connected. That is, the first pole and the second pole of each light-emitting unit 65 are electrically connected to the scanning signal input terminal 61 and the data signal input terminal 62 .
  • the first pole of the light-emitting unit 65 may be an anode, and the second pole of the light-emitting unit 65 may be a cathode.
  • Figure 5 is a schematic diagram of the specific circuit structure of the driving circuit 12 of the second embodiment shown in Figure 3.
  • Figure 6 is a specific circuit structure of the driving circuit 14 of the third embodiment shown in Figure 3. Schematic diagram.
  • each of the signal control units 40 may be an OR gate circuit.
  • the OR gate circuit includes k scan input terminals 42 and the output signal terminals 44.
  • the k scan input terminals are 42 receives k scan signals.
  • the signal control unit 40 outputs a control signal with a first potential or a second potential from the output signal terminal 44 according to the potential of the k scan signals received.
  • k is a positive integer greater than 1 and less than or equal to n.
  • the scan signal may be at a first potential or a second potential.
  • the scanning signal that needs to be transmitted for row scanning of the scanning line is at the first potential, and the scanning signals corresponding to the other scanning lines that are not row scanned are at the second potential.
  • the first potential may be a high potential, and the second potential may be a low potential.
  • the output signal terminal 44 outputs a control signal with the second potential to the switch unit 50 .
  • the output signal terminal 44 outputs a control signal with the first potential to the switch unit 50 .
  • the number of the signal control units 40 may be 1, 2, 3 or other numbers, and the present application has no specific limitation on this. It can be understood that the number of scan lines used for selectively transmitting scan signals among the k scan lines controlled by the signal control unit 40 can be determined according to the influence of the specific driving circuit.
  • the transmission of scanning signals of multiple scanning lines that may affect each other is adjusted in a targeted manner.
  • the switch unit 50 includes a switch input terminal 51 , k first switch output terminals 52 and k second switch output terminals 53 .
  • the switch input terminal 51 is electrically connected to the output signal terminal 44 , and the switch input terminal 51 receives a control signal at a first potential or a second potential from the output signal terminal 44 .
  • the k first switch output terminals 52 are electrically connected to the k scan signal input terminals 61
  • the k second switch output terminals 53 are electrically connected to the k scan signal input terminals 61 .
  • the switch input terminal 51 receives the control signal at the first potential
  • the k first switch output terminals 52 and the k scan signal input terminals 61 are electrically connected.
  • the k first switch output terminals 52 are electrically connected.
  • the scanning signal input terminal 61 receives k scanning signals, and the k scanning signals correspondingly scan the plurality of light-emitting units 65 in corresponding rows.
  • the switch input terminal 51 When the switch input terminal 51 receives the control signal at the second potential, the k second switch output terminals 53 are electrically connected to the k scan signal input terminals 61. At this time, the k scan signal input terminals 61 are electrically connected. The signal input terminals 61 are electrically connected, that is, the k scanning lines are short-circuited, and the k scanning signal input terminals 61 stop receiving the k scanning signals, that is, the scanning corresponding to the k scanning signal input terminals 61 to stop charging.
  • the output signal terminal 44 outputs the control signal at the second potential to the switch input terminal 51 , indicating that it is within the time of switching scanning lines.
  • the corresponding scan line will not continue to be charged during the switching time of the scan line, and the parasitic capacitance on the scan line will not continue to increase, which is beneficial to improving the performance of the scanning line.
  • the efficiency of discharging the charge on the parasitic capacitance during the scanning line switching time effectively avoids the phenomenon that the light-emitting unit 65 produces abnormal light emission due to the influence between the scanning lines and produces afterglow.
  • the k scan lines controlled to selectively transmit the scan signals are controlled by a signal control unit 40 , and k-1 second transistors 57 are electrically connected between the k scan signal input terminals 61 . Further, k scan signal input terminals 61 are short-circuited through k-1 second transistors 57 during the switching row scan interval.
  • the drive circuit may include a plurality of signal control units 40 combined with the switch unit 50 for controlling multiple scan lines to selectively transmit multiple scan signals. Each of the signal control units 40 and the switch unit 50 is used to control k scanning lines to selectively transmit k scanning signals.
  • the switch unit 50 includes k first transistors 56 and k-1 second transistors 57 .
  • each first transistor 56 includes a control terminal, a first terminal and a second terminal.
  • the control terminal of the first transistor 56 is electrically connected to the switch input terminal 51 for receiving a signal at a first potential or The control signal of the second potential can control the first transistor 56 to be in an on or off state.
  • the first terminal of the first transistor 56 is used to receive the scan signal.
  • the second terminal of the first transistor 56 is electrically connected to the first switch output terminal 52 .
  • the control terminal of the first transistor 56 When the control signal is at the first potential, the control terminal of the first transistor 56 receives the control signal at the first potential, and the first transistor 56 is in a conductive state.
  • the first terminal and the second terminal of the first transistor 56 are electrically conductive.
  • the scanning signal input terminal 61 is connected to the second terminal of the first transistor 56 , and the scanning signal input terminal 61 receives the scanning signal.
  • the control terminal of the first transistor 56 When the control signal is at the second potential, the control terminal of the first transistor 56 receives the control signal with the second potential, and the first transistor 56 is in a cut-off state. The first terminal and the second terminal of the first transistor 56 are electrically cut off. Further, the scan signal input terminal 61 is electrically disconnected from the second terminal of the first transistor 56 , and the scan signal input terminal 61 cannot receive the scan signal, so that the scan line will not continue to generate parasitics. capacitance.
  • the first potential is a high potential
  • the second potential is a low potential
  • Each second transistor 57 includes a control terminal, a first terminal and a second terminal.
  • the control terminal of the second transistor 57 is electrically connected to the switch input terminal 51 , that is, the control terminals of the first transistor 56 and the second transistor 57 are both electrically connected to the switch input terminal 51 .
  • the control terminal of the second transistor 57 is used to receive a control signal at a first potential or a second potential, and the control signal can control the second transistor 57 to be in an on or off state.
  • each second transistor 57 are electrically connected to two adjacent second switch output terminals 53 respectively. Specifically, the first terminal of the i-th second transistor 57 is electrically connected to the i-th second switch output terminal 53, and the second terminal of the i-th second transistor 57 is electrically connected to the i+1-th second switch output terminal 53.
  • i is an integer greater than or equal to 1 and less than or equal to k.
  • the first terminal of the first second transistor 57 is electrically connected to the first second switch output terminal 53, and the second terminal of the first second transistor 57 is electrically connected to the second second switch.
  • the control terminal of the second transistor 57 receives the control signal at the first potential, and the second transistor 57 is in a cut-off state.
  • the control terminal of the second transistor 57 receives the control signal at the second potential, and the second transistor 57 is in a conductive state.
  • the first terminal and the second terminal of the i-th second transistor 57 are electrically connected, so that the i-th second switch output terminal 53 and the i+1-th second switch output terminal 53 are electrically connected. conduction.
  • k scan signal input terminals 61 are electrically connected and k scan lines are short-circuited, so that the discharge rate of the charge release unit 70 is doubled, effectively avoiding charge accumulation on the parasitic capacitance. Sunset's unusual problem.
  • the k scanning input terminals 42 receive the k scanning signals. Because when at least one of the scan signals received by the k scan input terminals 42 is at the first potential, the output signal terminal 44 of the signal control unit 40 will output a control signal at the first potential.
  • the control signal at the first potential is transmitted to the switch unit 50 , the control terminal of the first transistor 56 receives the control signal at the first potential, the first transistor 56 is in a conductive state, and the first transistor 56 is in a conductive state.
  • the first terminal and the second terminal of the transistor 56 are electrically conductive, and the scanning signal is transmitted from the scanning signal input terminal 61 to the pixel array unit 60 .
  • the second transistor 57 is in a cut-off state, so each scan line independently outputs the waveform required for its own row, and the short-circuit function of each scan line is disabled.
  • the k scan input terminals 42 receive k scan signals at the second potential. Because when the scan signals received by the k scan input terminals 42 are all at the second potential, the output signal terminal 44 of the signal control unit 40 will output a control signal with the second potential.
  • the control signal with the second potential is transmitted to the switch unit 50 , and the control signal at the second potential controls k second switch output terminals 53 to be electrically conductive, that is, k scan signal input terminals 61 Electrical conduction, the scan signal cannot be transmitted to the corresponding scan line, that is, the scan line will no longer continue to receive the residual scan signal and generate parasitic capacitance, then each Scan independently outputs the waveform required by its own line. Function failure, short circuit between each scan line.
  • the first transistor 56 may be an N-type metal oxide semiconductor (N-Metal-Oxide-Semiconductor, NMOS) transistor
  • the second transistor 57 may be a P-type metal oxide semiconductor (P -Metal-Oxide-Semiconductor, PMOS) transistor.
  • the charge release unit 70 may include multiple capacitors 71 .
  • the number of capacitors 71 is n.
  • One end of each capacitor 71 is electrically connected to the corresponding charge release terminal 73 , and the other end of each capacitor is electrically connected to the reference ground GND.
  • the capacitor 71 is used to release charges on the parasitic capacitance generated by the corresponding scan line during the row driving scanning process.
  • k scanning signal input terminals 61 are controlled to stop receiving k scanning signals during the row scanning switching time, and at the same time, k scanning signal input terminals 61 are controlled to stop receiving k scanning signals.
  • the scan lines are short-circuited so that the parasitic capacitance will not continue to increase during the switching time.
  • the scanning signal corresponding to the scan line is at the first potential.
  • the potential on the scanning line switches from the first potential to the third potential. Two potentials.
  • the signals of all scanning lines are at the second potential, but parasitic capacitance is generated due to the residual first potential charges on the scanning lines during scanning.
  • the scanning signals during the switching time all have the characteristics of the second potential, and the scanning lines that may affect each other are disconnected.
  • the switching time characteristic of the scanning signals having the second potential is used to short-circuit the scanning lines that may affect each other, so that the charge discharge rate of the charge release unit 70 is doubled. This effectively avoids the problem of abnormal afterglow caused by slow charge discharge on the parasitic capacitance.
  • the driving circuit 11 includes a signal control unit 40 and a switch unit 50 for controlling four scanning lines to selectively receive the scanning signal.
  • the four controlled scan lines may be the scan line S1, the scan line S2, the scan line Sn-1 and the scan line Sn as shown in the figure, and this application does not specifically limit this.
  • the signal control unit 40 includes four scan input terminals 42, and the four scan input terminals 42 receive the four scan input terminals 42 along the scan line S1, the scan line S2, the scan line Sn-1 and the scan line Sn. Scan signal.
  • the switch unit 50 includes four first transistors 56 and three second transistors 57 .
  • the output signal terminal 44 When at least one of the four scanning signals is at the first potential, the output signal terminal 44 outputs the control signal at the first potential to the switch unit 50 .
  • the switch input terminal 51 is electrically connected to the four first switch output terminals 52
  • the scanning signal input terminal 61 is electrically connected to the four first switch output terminals 52
  • the scanning signal transmission To the corresponding four rows of the pixel array unit 60, a plurality of light-emitting units 65 corresponding to the four rows can be further controlled.
  • the output signal terminal 44 outputs the control signal at the second potential to the switch unit 50 .
  • the switch input terminal 51 is electrically connected to the four second switch output terminals 53, and the four scan signal input terminals 61 are electrically connected, that is, the four scan signal input terminals 61 are electrically connected.
  • the scanning signal stops transmitting to the corresponding four rows of the pixel array unit 60.
  • the charge discharge efficiency of the charge release unit 70 is correspondingly increased by 4 times, effectively improving the efficiency of discharging the charge on the parasitic capacitance. efficiency, eliminating the phenomenon of afterglow abnormalities caused by parasitic capacitance due to insufficient timely release of charges.
  • the driving circuit 12 includes a signal control unit 40 and a switch unit 50 for controlling two scanning lines to selectively receive the scanning signal.
  • the two controlled scan lines may be the scan line S1 and the scan line Sn illustrated in the figure, and this application does not specifically limit this.
  • the signal control unit 40 includes two scan input terminals 42, and the two scan input terminals 42 receive two scan signals along the scan line S1 and the scan line Sn.
  • the switch unit 50 includes two first transistors 56 and one second transistor 57 .
  • the output signal terminal 44 When at least one of the two scan signals is at the first potential, the output signal terminal 44 outputs the control signal at the first potential to the switch unit 50 .
  • the switch input terminal 51 is electrically connected to the two first switch output terminals 52, and the two first switch output terminals 52 are electrically connected to the two scanning signal input terminals 61.
  • the scanning The signal is transmitted to the corresponding two rows of the pixel array unit 60, and further can control the plurality of light-emitting units 65 corresponding to the two rows.
  • the output signal terminal 44 When both scanning signals are at the second potential, the output signal terminal 44 outputs the control signal at the second potential to the switch unit 50 .
  • the switch input terminal 51 is electrically connected to the two second switch output terminals 53, and the two scan signal input terminals 61 are electrically connected, that is, the two scan signal input terminals 61 are electrically connected.
  • the scanning signal stops transmitting to the corresponding two rows of the pixel array unit 60.
  • the charge discharge efficiency of the charge release unit 70 is correspondingly increased by 2 times, effectively improving the efficiency of discharging the charge on the parasitic capacitance. efficiency, eliminating the phenomenon of afterglow abnormalities caused by parasitic capacitance due to insufficient timely release of charges.
  • the drive circuit 14 includes two signal control units 40 and two switch units 50.
  • Each signal control unit 40 and each switch unit 50 are combined with Controlling two scan lines to selectively receive the scan signal. That is, a total of 4 scan lines are controlled.
  • the four controlled scan lines may be the scan line S1, the scan line S2, the scan line Sn-1 and the scan line Sn-2 illustrated in the figure, and this application does not impose any specific limitations on this.
  • each of the signal control units 40 includes two scan input terminals 42 , and one of the signal control units 40 receives two scan signals along the scan line S1 and the scan line S2 .
  • the switch unit 50 used in conjunction with the signal control unit 40 includes two first transistors 56 and one second transistor 57 .
  • Another signal control unit 40 receives two scan signals along the scan line Sn-1 and the scan line Sn.
  • the switch unit 50 used in conjunction with the signal control unit 40 includes two first transistors 56 and one second transistor 57 .
  • the output signal terminal 44 When at least one of the two scan signals is at the first potential, the output signal terminal 44 outputs a control signal at the first potential to the switch unit 50 .
  • the switch input terminal 51 is electrically connected to the two first switch output terminals 52
  • the two first switch output terminals 52 are electrically connected to the two scan signal input terminals 61 Electrical conduction
  • the scanning signal is transmitted to the corresponding two rows of the pixel array unit 60, and further can control the plurality of light-emitting units 65 corresponding to the two rows.
  • both scanning signals are at the second potential
  • the output signal terminal 44 outputs the control signal at the second potential to the switch unit 50 .
  • the switch input terminal 51 is electrically connected to the two second switch output terminals 53, and the two scan signal input terminals 61 are electrically connected, that is, two of the scan signal input terminals 61 are electrically connected.
  • the scanning signal stops transmitting to the corresponding two rows of the pixel array unit 60.
  • the charge discharge efficiency of the charge release unit 70 is correspondingly increased by 2 times, effectively improving the efficiency of discharging the charge on the parasitic capacitance. efficiency, eliminating the phenomenon of afterglow abnormalities caused by parasitic capacitance due to insufficient timely release of charges.
  • this application also provides a display module 10.
  • the display module 10 includes the above-mentioned driving circuit and the display panel 13.
  • the driving circuit is electrically connected to the display panel 13.
  • the driving circuit uses The display panel 13 is driven to display different images.
  • the display device 100 includes a display module 10 and a power module 20.
  • the power module 20 is disposed on the non-display surface of the display module 10. , the power module 20 is used to provide power voltage for the display module 10 to display images.
  • the display device 100 provided in the embodiment of the present application can be a notebook computer display screen, a liquid crystal display, an LCD TV, a mobile phone, a tablet computer, or any other product or component with a display function.
  • the display device 100 also includes other necessary components and components such as a high-voltage board and a key control board. Those skilled in the art can supplement accordingly according to the specific type and actual functions of the display device 100. This will not be described again.
  • the display device 100 can also be used for electronic devices including functions such as a personal digital assistant (Personal Digital Assistant, PDA) and/or a music player, such as mobile phones, tablet computers, and wearable electronic devices with wireless communication functions. (Such as smart watches) etc.
  • PDA Personal Digital Assistant
  • the above-mentioned electronic device may also be other electronic devices, such as a laptop computer (Laptop) with a touch-sensitive surface (such as a touch panel).
  • the signal control unit 40 and the switch unit 50 are provided to selectively control the k scanning signal input terminals 61 to receive or stop receiving the scan signal, effectively control the drive circuit to normally transmit the scan signal to the pixel array unit 60 during line scan, and stop transmitting the scan signal to the pixel array unit 60 during the line scan switching time, This avoids the remaining scan signal charges during the row scanning switching time from continuing to generate parasitic capacitance, effectively avoiding the parasitic capacitance from continuing to increase during the switching time, aggravating the discharge workload of the charge release unit 70 and the discharge capacity of the charge release unit 70 The problem caused by insufficient afterglow.
  • the signal control unit 40 and the switch unit 50 cooperate to control the k scan lines to be short-circuited during the switching time, thereby increasing the discharge rate of charges on the capacitor 71 electrically connected to the corresponding scan line. Specifically, if k scan lines are short-circuited, the charge discharge rate on the capacitor 71 of the corresponding scan line is increased by k times compared with when the k scan lines are not short-circuited. This greatly reduces the problem of abnormal afterglow caused by incomplete discharge of charges on parasitic capacitors or insufficient timely release, thereby effectively improving the accuracy of driving of the driving circuit and ensuring the performance of the display module 10 display effect.

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Abstract

一种驱动电路（11）、显示模组(10)及显示装置(100)。开关单元(50)的第一开关输出端(52)或第二开关输出端(53)根据控制信号选择性与扫描信号输入端(61)导通，使扫描信号选择性传输至像素阵列单元(60)。电荷释放单元(70)释放像素阵列单元(60)产生的寄生电容的至少部分电荷。驱动电路（11）控制在行扫描时正常传输扫描信号至像素阵列单元(60)，避免在行扫描切换时间残留的扫描信号电荷继续产生寄生电容造成余晖异常。

Description

驱动电路、显示模组及显示装置
本申请要求于2022年07月07日提交中国专利局，申请号为202210796092.3，申请名称为“驱动电路、显示模组及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种驱动电路、一种具有该驱动电路的显示模组以及一种具有该显示模组的显示装置。
背景技术
在采用被动寻址(Passive Matrix，PM)驱动模式的次毫米发光二极管(Mini Light Emitting Diode，Mini-LED)显示器、微发光二极管(Micro Light Emitting Diode，Micro-LED)显示器和有机发光二极管(Organic Light Emitting Diode，OLED)显示器等LED显示装置中，随着显示技术的发展，尤其是发光元件小间距的发展，LED显示装置对于行驱动的要求明显提高。
目前，上述LED显示装置的驱动电路中，以共阳驱动电路为例，当控制行的数据信号为低时，发光元件的阳极电压拉高，此时根据控制列的数据信号的宽窄即可使发光元件产生不同亮度的光。此时，行扫描切换过程中，行扫描线残留电压生成寄生电容。然而，在进行其他行扫描时，由于行扫描切换间隔时间较短，寄生电容上的电荷尚未释放完毕，此时，寄生电容与其他行行扫描信号共同作用使本应关闭的发光元件误发光，从而导致在显示上产生余晖，即余晖异常的现象，影响显示效果和用户使用体验。
发明内容
本申请的目的是提供一种驱动电路、显示模组和显示装置。所述驱动电路设置所述信号控制单元和所述开关单元，选择性控制多个所述扫描信号输入端接收或停止接收所述扫描信号，有效避免了切换时间寄生电容继续增加，加重所述电荷释放单元的泄放工作量，以及所述电荷释放单元泄放能力不足造成的余晖异常的问题。
为实现本申请的目的，本申请提供了如下的技术方案：
第一方面，本申请实施例提供了一种驱动电路，其包括至少一个信号控制单元、开关单元、像素阵列单元和电荷释放单元，其中，
每个所述信号控制单元包括多个扫描输入端和输出信号端，所述扫描输入端接收扫描信号，所述信号控制单元根据所述扫描信号自所述输出信号端输出控制信号；
所述开关单元包括开关输入端、多个第一开关输出端和多个第二开关输出端，所述开关输入端与所述输出信号端电连接，并接收所述控制信号；
所述像素阵列单元包括多个扫描信号输入端和多个电荷输出端，其中，多个所述扫描信号输入端同时电连接至多个所述第一开关输出端和多个所述第二开关输出端，所述第一开关输出端或所述第二开关输出端根据所述控制信号选择性与所述扫描信号输入端导通，使所述扫描信号选择性传输至所述像素阵列单元；
所述电荷释放单元包括多个电荷释放端，每个所述电荷释放端电连接至每个所述电荷输出端，所述电荷释放单元释放所述像素阵列单元产生的寄生电容的至少部分电荷。
第二方面，本申请还提供了一种显示模组，所述显示模组包括显示面板和若干上述的驱动电路，所述驱动电路与所述显示面板电连接，所述驱动电路用于驱动所述显示面板显示画面。
第三方面，本申请还提供了一种显示装置，所述显示装置包括电源模组和上述的显示模组，所述电源模组设置于所述显示模组的非显示面，所述电源模组用于为所述显示模组进行图像显示提供电源电压。
综上所述，在本申请提供的驱动电路、显示模组和显示装置中，设置所述信号控制单元和所述开关单元，选择性控制多个所述扫描信号输入端接收或停止接收所述扫描信号。有效控制所述驱动电路在进行行扫描时正常传输扫描信号至所述像素阵列单元，在行扫描切换时间停止传输所述扫描信号至所述像素阵列单元，避免了在行扫描切换时间残留的扫描信号电荷继续产生寄生电容，有效避免了切换时间寄生电容继续增加，加重所述电荷释放单元的泄放工作量，以及所述电荷释放单元泄放能力不足造成的余晖异常的问题。
此外，所述信号控制单元和所述开关单元相配合控制多条扫描线在切换时间短接，进而提高了电连接至对应扫描线的电容上电荷的泄放速率。具体地， 多条扫描线短接，则对应扫描线的电容上电荷泄放速率较未短接时提升与扫描线条数相等的倍数。大大降低了由于寄生电容上的电荷泄放不净或得不到及时足够释放而造成的余晖异常的问题，从而有效提高了所述驱动电路驱动的正确性，保证了所述显示模组的显示效果。
附图说明
为了更清楚地说明本申请实施方式或现有技术中的技术方案，下面将对实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例公开的一种显示装置的结构示意图；
图2为图1所示的显示装置中显示模组的结构示意图；
图3为图1所示的显示装置中显示模组的驱动电路的电路示意图；
图4为图3所示第一实施例的驱动电路的具体电路结构示意图。
图5为图3所示第二实施例的驱动电路的具体电路结构示意图；
图6为图3所示第三实施例的驱动电路的具体电路结构示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳实施方式。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施方式。相反地，提供这些实施方式的目的是使对本申请的公开内容理解的更加透彻全面。
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本文中为部件所编序号本身，例如“第一”、“第二”等，仅用于区分所描述的对象，不具有任何顺序或技术含义。而本申请所说“连接”、“联接”，如无特别说明，均包括直接和间接连接(联接)。本申请中所提到的方向用语，例如，“上”、“下”、“前”、“后”、“左”、“右”、“内”、“外”、“侧面”等，仅是参考附加图式的方向，因此，使用的方向用语是为了更好、更清楚地说明及理解本申请，而不是指示或暗指所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸地连接，或者一体地连接；可以是机械连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。需要说明的是，本申请的说明书和权利要求书及所述附图中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。此外，本申请中使用的术语“包括”、“可以包括”、“包含”、或“可以包含”表示公开的相应功能、操作、元件等的存在，并不限制其他的一个或多个更多功能、操作、元件等。此外，术语“包括”或“包含”表示存在说明书中公开的相应特征、数目、步骤、操作、元素、部件或其组合，而并不排除存在或添加一个或多个其他特征、数目、步骤、操作、元素、部件或其组合，意图在于覆盖不排他的包含。还需要理解的是，本文中描述的“至少一个”的含义是一个及其以上，例如一个、两个或三个等，而“多个”的含义是至少两个，例如两个或三个等，除非另有明确具体的限定。本申请的说明书和权利要求书及所述附图中的术语“步骤1”、“步骤2”等是用于区别不同对象，而不是用于描述特定顺序。
在显示技术领域中，显示装置通常可以包括显示面板和背光组件，其中，所述显示面板安装至所述背光组件的出光侧，背光组件用于给所述显示面板提供背光，以调节显示面板显示不同画面。在薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT–LCD)中，所述背光组件中设置有公共电极、像素电极、数据(data)线和液晶分子，其中，公共电极电压为参考电压，改变数据线的数据信号大小使所述像素电极不同程度释放电容，从而在公共电极与像素电极之间形成不同大小的电场，不同大小的电场控制所述背光组件中的液晶分子进行不同程度偏转，使所述显示面板显示不同灰阶画面。
请参阅图1，图1为本申请实施例公开的一种显示装置的结构示意图。如图1所示，本申请实施例提供的显示装置100至少可以包括显示模组10、电源模组20和支撑框架30，其中，所述显示模组10固定于支撑框架30，所述电源模组20设置于所述显示模组10的背面，即所述显示模组10的非显示面，也即所述显示模组10背对用户的一侧。所述显示模组10用于显示图像，所述电源模组20与所述显示模组10电连接，用于为所述显示模组10进行图像显示提供电 源电压，所述支撑框架30为所述显示模组10和所述电源模组20提供支撑与保护作用。
可以理解的是，所述显示模组10还具有与所述非显示面相对设置的显示面，即所述显示模组10的正面，也即所述显示模组10面对用户的一侧。所述显示面用于面对使用所述显示装置100的用户，以显示图像。
请一并参阅图2，图2为图1所示的显示装置100中显示模组10的结构示意图。在本申请实施例中，所述显示模组10至少可以包括显示面板13和背光模组(Backlight Module，BM)17，其中，所述显示面板13设置于所述背光模组17的出光侧，所述背光模组17用于提供显示用的光线至所述显示面板13，所述显示面板13依据待显示的图像数据出射相应的光线以执行图像显示。
在本申请示例性实施例中，所述显示模组10还可以包括其他元件或者组件，例如还包括信号处理器模组、信号感测模组等。
如图2所示，所述显示面板13至少包括有阵列基板(Array Substrate，AS)131、彩膜基板133、以及夹设于阵列基板131与彩膜基板133之间的液晶层132。所述阵列基板131与所述彩膜基板133之间依据待显示的图像数据产生相应的电场，从而控制所述液晶层132中的液晶分子偏转相应的角度以出射相应亮度的光线，以执行图像显示。在本实施例中，所述显示面板13可以为Micro-LED显示面板、OLED显示面板或Mini-LED显示面板等采用被动寻址(PM)驱动模式的显示面板。
请一并参阅图3，图3为图1所示的显示装置100中显示模组10的驱动电路11的电路示意图。在本申请实施例中，所述显示模组10至少还包括驱动电路11，所述驱动电路11可设置于所述显示面板13的周边区域，且所述驱动电路11与所述显示面板13电连接，用于为所述显示面板13供电以及提供驱动信号。所述驱动电路11与所述背光模组17电连接，所述驱动电路11和所述背光模组17相配合使所述显示面板13显示画面。
在本申请实施例中，所述驱动电路11至少可以包括至少一个信号控制单元40、开关单元50、像素阵列单元60和电荷释放单元70。其中，每个所述信号控制单元包括输出信号端和多个扫描输入端，所述扫描输入端接收扫描信号，所述信号控制单元根据所述扫描信号自所述输出信号端输出控制信号。
所述开关单元包括开关输入端、多个第一开关输出端和多个第二开关输出 端，所述开关输入端与所述输出信号端电连接，并接收所述控制信号。
所述像素阵列单元包括多个扫描信号输入端和多个电荷输出端，其中，多个所述扫描信号输入端同时电连接至多个所述第一开关输出端和多个所述第二开关输出端，所述第一开关输出端或所述第二开关输出端根据所述控制信号选择性与所述扫描信号输入端导通，使所述扫描信号选择性传输至所述像素阵列单元。
所述电荷释放单元包括多个电荷释放端，每个所述电荷释放端电连接至每个所述电荷输出端，所述电荷释放单元释放所述像素阵列单元产生的寄生电容的至少部分电荷。
为了清楚的阐述各单元的端口数量关系，下文将设定各个端口及元器件的数量，例如，k个扫描输入端、n个扫描信号输入端、k-1个第二晶体管等，对本申请的技术方案进行进一步的阐述。其中，k为大于1且小于等于n的整数，n为大于等于2的整数，与前文阐述数量为“多个”、“若干”一致，所以k或n的数量限定不构成对技术方案的限制，仅在于使技术方案更加清晰。
在本申请实施例中，每个所述信号控制单元40包括k个扫描输入端42和输出信号端44。k个所述扫描输入端42接收k个扫描信号，也即为，每个所述扫描输入端42接收一个对应的扫描信号。所述信号控制单元40根据k个扫描信号自所述输出信号端44输出处于第一电位或第二电位的控制信号。可以理解的是，所述扫描输入端42可以用扫描驱动电路或行驱动电路接收所述扫描信号。
每个所述开关单元50包括开关输入端51、k个第一开关输出端52和k个第二开关输出端53。所述开关输入端51与所述输出信号端44对应电连接。
所述像素阵列单元60包括n个扫描信号输入端61和n个电荷输出端63。所述电荷输出端63与所述电荷释放单元70电连接。其中k个所述扫描信号输入端61同时电连接至k个所述第一开关输出端52和k个所述第二开关输出端53。所述开关单元50根据所述控制信号选择性导通所述扫描信号输入端61与所述第一开关输出端52或所述第二开关输出端53。进一步地，选择性导通所述扫描信号输入端61，以通过所述扫描信号输入端61向所述像素阵列单元60传输相应的扫描信号。其中，所述扫描信号为所述驱动电路11的其他电路结构生成并可传输至所述扫描信号输入端61。
所述电荷释放单元70包括n个电荷释放端73，每个所述电荷释放端73电 连接至每个所述电荷输出端63，所述电荷释放单元70用于释放所述像素阵列单元60产生的部分寄生电容的电荷。具体地，每个所述电荷释放端73用于引导释放对应扫描行产生的寄生电容的电荷。
在本申请实施例中，k为大于1且小于等于n的整数，n为大于等于2的整数。可以理解的是，所述信号控制单元40和所述开关单元50可以只调节所述像素阵列单元60的部分扫描信号输入端61选择性接收所述扫描信号。例如，可以根据实际情况，对可能相互影响的扫描行通过所述信号控制单元40和所述开关单元50进行调节。
在本申请实施例中，在所述驱动电路11中增设所述信号控制单元40和所述开关单元50，使其在切换扫描行的时间内，停止通过所述扫描信号输入端61向所述像素阵列单元60的发光单元65传输扫描信号。如此可有效避免所述像素阵列单元60的寄生电容在切换扫描行时间内增加，导致所述电荷释放单元70在间隔时间内不能够充分泄放寄生电容上的电荷，进而造成所述像素阵列单元60不正常发光的问题。因此，有效提高了所述驱动电路11驱动的准确性，从而消除了余晖现象，保证了所述显示模组10的显示效果。
请一并参阅图4，图4为图3所示第一实施例的驱动电路11的具体电路结构示意图。在本申请实施例中，所述像素阵列单元60包括互相呈网格状设置且沿着第一方向F1延伸的n条扫描线(Scan line)S1～Sn和沿着第二方向F2延伸的m条数据线(Data line)D1～Dm。其中，第一方向F1与第二方向F2相互垂直，并且多条所述扫描线S1～Sn之间、多条所述数据线D1～Dm之间、以及所述扫描线S1～Sn与所述数据线D1～Dm之间均相互绝缘。也即，多条所述扫描线S1～Sn之间沿着所述第二方向F2间隔排列设置且相互绝缘，多条所述数据线D1～Dm之间沿着所述第一方向F1间隔排列设置且相互绝缘，多条所述扫描线S1～Sn与多条所述数据线D1～Dm之间相互绝缘设置。其中，每个所述扫描线用于通过所述扫描信号输入端61向所述发光单元65传输所述扫描信号。其中，m为正整数。
多条所述扫描线S1～Sn和所述数据线D1～Dm的交叉处均对应设置有发光单元65。具体为，任意相邻的两条所述扫描线和任意相邻的两条所述数据线之间设置有所述发光单元65，位于同一列的所述发光单元65均与同一条所述数据线电连接，位于同一行的所述发光单元65均与同一条所述扫描线电连接。本申 请实施例中，多个所述发光单元65呈阵列分布。在本申请实施例中，每条所述数据线对应与数据信号输入端电连接，每条所述扫描线对应与所述扫描信号输入端电连接。
如图4所示，在本申请实施例中，所述像素阵列单元60包括m个数据信号输入端62、n个扫描信号输入端61和n*m个发光单元65，每个所述扫描信号输入端61与m个所述发光单元65的第一极电连接，每个所述数据信号输入端62与n个所述发光单元65的第二极电连接，所述扫描信号通过所述扫描信号输入端传输至所述发光单元以控制所述发光单元的开启和关闭。也即为，每个所述扫描信号输入端61与对应一行的m个所述发光单元65的第一极电连接，每个所述数据信号输入端62与对应一列的n个所述发光单元65的第二极电连接。也即，每个所述发光单元65的第一极和第二极对应电连接于所述扫描信号输入端61和所述数据信号输入端62。
在本申请示例性实施例中，所述发光单元65的第一极可为阳极，所述发光单元65的第二极可为阴极。
请一并参阅图5和图6，图5为图3所示第二实施例的驱动电路12的具体电路结构示意图，图6为图3所示第三实施例的驱动电路14的具体电路结构示意图。
在本申请实施例中，每个所述信号控制单元40可以为或门电路，所述或门电路包括k个所述扫描输入端42和所述输出信号端44，k个所述扫描输入端42接收k个所述扫描信号。所述信号控制单元40根据接收的k个所述扫描信号的电位情况自所述输出信号端44输出具有第一电位或第二电位的控制信号。其中，k为大于1且小于等于n的正整数。
所述扫描信号可以处于第一电位或第二电位。扫描线进行行扫描需要传输的扫描信号处于第一电位，其余未进行行扫描的扫描线对应的扫描信号处于第二电位。所述第一电位可以为高电位，所述第二电位可以为低电位。具体地，在所述信号控制单元40中，若所述扫描信号均处于第二电位，则所述输出信号端44输出具有第二电位的控制信号至所述开关单元50。
若多个所述扫描信号至少有一个处于第一电位，则所述输出信号端44输出具有第一电位的控制信号至所述开关单元50。
如图5，在本申请其他实施例中，所述信号控制单元40的数量可以为1个、 2个，3个或其他数量，本申请对此没有具体限制。可以理解的是，利用所述信号控制单元40控制的k条扫描线中用于选择性传输扫描信号的扫描线的条数可以根据具体的驱动电路的影响情况确定。
例如，若扫描线S1与扫描线S2之间易产生影响，那么可以在扫描线S1与扫描线S2之间设置所述信号控制单元40，此时被调节的扫描线的数量k＝2。
若扫描线Sn与扫描线Sn-1之间易产生影响，那么可以在扫描线Sn与扫描线Sn-1之间设置所述信号控制单元40，此时被调节的扫描线的数量k＝2。
若扫描线S1与扫描线S2之间，扫描线Sn与扫描线Sn-1之间均易产生影响，可以在扫描线S1与扫描线S2之间和扫描线Sn与扫描线Sn-1之间各设置一个所述信号控制单元40，即扫描线S1与扫描线S2作为一组设置一个信号控制单元40，扫描线Sn与扫描线Sn-1作为一组设置另一个信号控制单元40，此时被调节的每组扫描线的数量k＝2。亦可以在扫描线S1、扫描线S2、扫描线Sn和扫描线Sn-1之间设置一个所述信号控制单元40，此时k＝4。
进一步地，有针对性地调节可能互相影响的多条扫描线的扫描信号的传输。
在本申请实施例中，所述开关单元50包括开关输入端51、k个第一开关输出端52和k个第二开关输出端53。所述开关输入端51与所述输出信号端44电连接，所述开关输入端51自所述输出信号端44接收处于第一电位或第二电位的控制信号。k个所述第一开关输出端52与k个所述扫描信号输入端61电连接，k个所述第二开关输出端53与k个所述扫描信号输入端61电连接。
具体地，当所述开关输入端51接收处于第一电位的控制信号，则k个所述第一开关输出端52与k个所述扫描信号输入端61电性导通，此时，k个所述扫描信号输入端61接收k个所述扫描信号，k个所述扫描信号相应的扫描对应行的多个发光单元65。
当所述开关输入端51接收处于第二电位的控制信号，则k个所述第二开关输出端53与k个所述扫描信号输入端61电性导通，此时，k个所述扫描信号输入端61之间电性导通，即k条扫描线短接，k个所述扫描信号输入端61停止接收k个所述扫描信号，即k个所述扫描信号输入端61对应的扫描行停止充电。
可以理解的是，所述输出信号端44输出处于第二电位的所述控制信号至所述开关输入端51，表征此时正处于切换扫描行的时间内。通过将k个所述扫描信号输入端61之间电性导通，使对应扫描行在切换扫描行的时间内不继续充电， 进而该扫描行上的寄生电容不会继续增加，有利于提升在扫描行切换时间泄放寄生电容上电荷的效率，有效避免了扫描线之间影响造成所述发光单元65不正常发光产生余晖的现象。
可以理解的是，被控制选择性传输所述扫描信号的k条扫描线通过一个信号控制单元40控制，k-1个第二晶体管57电连接于k个所述扫描信号输入端61之间。进一步地，k个所述扫描信号输入端61在切换行扫描间隔时间内通过k-1个第二晶体管57短接。在所述驱动电路中，可以包括多个所述信号控制单元40与所述开关单元50组合，用于控制多条扫描线选择性传输多条扫描信号。每个所述信号控制单元40与所述开关单元50组合中，用于控制k条扫描线选择性传输k条扫描信号。
在本申请实施例中，所述开关单元50包括k个第一晶体管56和k-1个第二晶体管57。具体地，每个所述第一晶体管56包括控制端、第一端和第二端，所述第一晶体管56的控制端电连接至所述开关输入端51，用于接收处于第一电位或第二电位的所述控制信号，所述控制信号可以控制所述第一晶体管56处于导通或截止状态。所述第一晶体管56的第一端用于接收所述扫描信号。所述第一晶体管56的第二端对应电连接至所述第一开关输出端52。
当所述控制信号处于第一电位时，所述第一晶体管56的控制端接收处于第一电位的控制信号，所述第一晶体管56处于导通状态。所述第一晶体管56的第一端和第二端电性导通。进一步地，所述扫描信号输入端61与所述第一晶体管56的第二端导通，所述扫描信号输入端61接收所述扫描信号。
当所述控制信号处于第二电位时，所述第一晶体管56的控制端接收具有第二电位的控制信号，所述第一晶体管56处于截止状态。所述第一晶体管56的第一端和第二端电性截止。进一步地，所述扫描信号输入端61与所述第一晶体管56的第二端电性断开，所述扫描信号输入端61无法接收所述扫描信号，从而所述扫描线不会继续产生寄生电容。
其中，所述第一电位为高电位，所述第二电位为低电位。本申请对此不作具体限制。
每个所述第二晶体管57包括控制端、第一端和第二端。所述第二晶体管57的控制端电连接至所述开关输入端51，即就是所述第一晶体管56的控制端和所述第二晶体管57的控制端均电连接至所述开关输入端51。所述第二晶体管57 的控制端用于接收处于第一电位或第二电位的控制信号，所述控制信号可以控制所述第二晶体管57处于导通或截止状态。
每个所述第二晶体管57的第一端和第二端分别电连接至相邻的两个所述第二开关输出端53。具体地，第i所述第二晶体管57的第一端电连接至第i所述第二开关输出端53，第i所述第二晶体管57的第二端电连接至第i+1所述第二开关输出端53。其中，i为大于等于1小于等于k的整数。例如，第1所述第二晶体管57的第一端电连接至第1所述第二开关输出端53，第1所述第二晶体管57的第二端电连接至第2所述第二开关输出端53；第2所述第二晶体管57的第一端电连接至第2所述第二开关输出端53，第2所述第二晶体管57的第二端电连接至第3所述第二开关输出端53，以此类推。其中，i为大于1小于k的整数。
当所述控制信号处于第一电位时(即高电位时)，所述第二晶体管57的控制端接收处于第一电位的控制信号，所述第二晶体管57处于截止状态。
当所述控制信号处于第二电位时(即低电位时)，所述第二晶体管57的控制端接收处于第二电位的控制信号，所述第二晶体管57处于导通状态。第i个所述第二晶体管57的第一端和第二端电性导通，使得第i个所述第二开关输出端53与第i+1个所述第二开关输出端53电性导通。进而使得k个所述扫描信号输入端61电性导通，k条所述扫描线短接，使得所述电荷释放单元70的泄放速率成倍增长，有效避免了寄生电容上的电荷积累导致余晖异常的问题。
在本申请实施例中，当k个所述扫描信号至少有一个具有第一电位时，k个所述扫描输入端42接收k个所述扫描信号。由于当k个所述扫描输入端42接收到的扫描信号至少有一个处于第一电位时，所述信号控制单元40的输出信号端44则会输出处于第一电位的控制信号。处于第一电位的所述控制信号传输至所述开关单元50，所述第一晶体管56的控制端接收处于第一电位的控制信号，所述第一晶体管56处于导通状态，所述第一晶体管56的第一端和第二端电性导通，所述扫描信号自所述扫描信号输入端61传输至所述像素阵列单元60。此时，所述第二晶体管57处于截止状态，则每条扫描线独自输出自己本行所需波形，各扫描线短路功能失效。
当k个所述扫描信号均处于第二电位时，k个所述扫描输入端42接收k个处于第二电位的k个所述扫描信号。由于当k个所述扫描输入端42接收到的扫 描信号均处于第二电位时，所述信号控制单元40的输出信号端44则会输出具有第二电位的控制信号。具有第二电位的所述控制信号传输至所述开关单元50，处于第二电位的所述控制信号控制k个所述第二开关输出端53电性导通，即k个扫描信号输入端61电性导通，所述扫描信号无法传输至对应所述扫描线上，即所述扫描线不会再继续接收残余的扫描信号而产生寄生电容，则每条Scan独自输出自己本行所需波形功能失效，各扫描线之间短路。
在本申请实施例中，所述第一晶体管56可为N型金属氧化物半导体(N-Metal-Oxide-Semiconductor，NMOS)晶体管，所述第二晶体管57可为P型金属氧化物半导体(P-Metal-Oxide-Semiconductor，PMOS)晶体管。
在本申请实施例中，所述电荷释放单元70可以包括多个电容71。在本申请实施例中，所述电容71的数量为n个。其中，每个所述电容71的一端电连接至相应的所述电荷释放端73，每个所述电容的另一端电连接至参考地GND。所述电容71用于释放对应扫描线在行驱动扫描过程中产生的寄生电容上的电荷。
在本申请实施例中，通过增设所述信号控制单元40和所述开关单元50，行扫描切换的时间中控制k个所述扫描信号输入端61停止接收k个所述扫描信号，同时将k条所述扫描线短接，使得寄生电容在切换时间内不会继续增加。进一步地，所述电容71释放寄生电容上电荷的效率有效提升。具体地，当k＝4时，所述电容71释放寄生电容的效率将提升4倍。
在本申请实施例中，所述驱动电路进行行扫描时，被行扫的扫描线对应的扫描信号处于第一电位，切换扫描行的时间中，扫描线上的电位由第一电位切换至第二电位。此时，所有扫描行的信号均处于第二电位，但由于扫描时扫描线上的第一电位电荷残留，而产生寄生电容。在本申请实施例中，在切换扫描行的时间中，通过增设信号控制单元40和开关单元50，利用切换时间扫描信号均具有第二电位的特性，将可能会互相影响的扫描线之间断开，从而避免了切换扫描行的时间中，由于残余电荷继续为扫描线充电而导致继续增加寄生电容的问题，有效提高了驱动电路驱动发光单元65部分发光的准确性。另外，通过设置开关单元50，将利用切换时间扫描信号均具有第二电位的特性，将可能会互相影响的扫描线进行短接，使得所述电荷释放单元70的电荷泄放速率成倍增长，有效避免了寄生电容上的电荷泄放较慢导致余晖异常的问题。
下面以图4、图5和图6所示的驱动电路的不同的实施例的具体电路结构示 意图为例，阐述所述驱动电路的示例性电路结构。
如图4所示，在本申请其中一个实施例中，所述驱动电路11包括1个信号控制单元40和1个开关单元50，用于控制4条扫描线选择性接收所述扫描信号。4条被控制的扫描线可以是图中示例的扫描线S1、扫描线S2、扫描线Sn-1和扫描线Sn，本申请对此不做具体限制。
此时，所述信号控制单元40包括4个所述扫描输入端42，4个所述扫描输入端42沿扫描线S1、扫描线S2、扫描线Sn-1和扫描线Sn接收4个所述扫描信号。所述开关单元50包括四个第一晶体管56和三个第二晶体管57。
当4个扫描信号至少有一个处于第一电位时，所述输出信号端44输出处于第一电位的控制信号至所述开关单元50。所述开关输入端51与4个所述第一开关输出端52电性导通，所述扫描信号输入端61与4个所述第一开关输出端52电性导通，所述扫描信号传输至所述像素阵列单元60的对应4行，进一步地可以控制对应4行的多个发光单元65。
当4个扫描信号均处于第二电位时，所述输出信号端44输出处于第二电位的控制信号至所述开关单元50。在所述开关单元50中，所述开关输入端51与4个所述第二开关输出端53电性导通，4个所述扫描信号输入端61电性导通，即4条所述扫描线短接，所述扫描信号停止传输至所述像素阵列单元60的对应4行，进一步地，所述电荷释放单元70的电荷泄放效率相应提高4倍，有效提升泄放寄生电容上电荷的效率，消除了寄生电容由于电荷得不到及时足够释放而造成余晖异常的现象。
如图5所示，在本申请其中一个实施例中，所述驱动电路12包括1个信号控制单元40和1个开关单元50，用于控制2条扫描线选择性接收所述扫描信号。2条被控制的扫描线可以是图中示例的扫描线S1和扫描线Sn，本申请对此不做具体限制。
此时，所述信号控制单元40包括2个所述扫描输入端42，2个所述扫描输入端42沿扫描线S1和扫描线Sn接收2个扫描信号。所述开关单元50包括2个第一晶体管56和1个第二晶体管57。
当2个扫描信号至少有一个处于第一电位时，所述输出信号端44输出处于第一电位的控制信号至所述开关单元50。所述开关输入端51与2个所述第一开关输出端52电性导通，2个所述第一开关输出端52与2个所述扫描信号输入端 61电性导通，所述扫描信号传输至所述像素阵列单元60的对应2行，进一步地可以控制对应2行的多个发光单元65。
当2个扫描信号均处于第二电位时，所述输出信号端44输出处于第二电位的控制信号至所述开关单元50。在所述开关单元50中，所述开关输入端51与2个所述第二开关输出端53电性导通，2个所述扫描信号输入端61电性导通，即2条所述扫描线短接，所述扫描信号停止传输至所述像素阵列单元60的对应2行，进一步地，所述电荷释放单元70的电荷泄放效率相应提高2倍，有效提升泄放寄生电容上电荷的效率，消除了寄生电容由于电荷得不到及时足够释放而造成余晖异常的现象。
如图6所示，在本申请其中一个实施例中，所述驱动电路14包括2个信号控制单元40和2个开关单元50，每个信号控制单元40和每个开关单元50组合后分别用于控制2条扫描线选择性接收所述扫描信号。即共控制4条扫描线。4条被控制的扫描线可以是图中示例的扫描线S1、扫描线S2、扫描线Sn-1和扫描线Sn-2，本申请对此不做具体限制。
此时，每个所述信号控制单元40包括2个所述扫描输入端42，其中一个信号控制单元40沿扫描线S1和扫描线S2接收2个扫描信号。与该信号控制单元40配合使用的所述开关单元50包括2个第一晶体管56和1个第二晶体管57。
另一个信号控制单元40沿扫描线Sn-1和扫描线Sn接收两个扫描信号。与该信号控制单元40配合使用的所述开关单元50包括2个第一晶体管56和1个第二晶体管57。
当2个扫描信号至少有一个处于第一电位时，所述输出信号端44输出处于第一电位的控制信号至所述开关单元50。在所述开关单元50中，所述开关输入端51与2个所述第一开关输出端52电性导通，2个所述第一开关输出端52与2个所述扫描信号输入端61电性导通，所述扫描信号传输至所述像素阵列单元60的对应2行，进一步地可以控制对应2行的多个发光单元65。当2个扫描信号均处于第二电位时，所述输出信号端44输出处于第二电位的控制信号至所述开关单元50。在所述开关单元50中，所述开关输入端51与2个所述第二开关输出端53电性导通，2个所述扫描信号输入端61电性导通，即两条所述扫描线短接，所述扫描信号停止传输至所述像素阵列单元60的对应两行，进一步地，所述电荷释放单元70的电荷泄放效率相应提高2倍，有效提升泄放寄生电容上 电荷的效率，消除了寄生电容由于电荷得不到及时足够释放而造成余晖异常的现象。
基于相同的构思，本申请还提供了一种显示模组10，所述显示模组10包括上述驱动电路和显示面板13，所述驱动电路与所述显示面板13电连接，所述驱动电路用于驱动所述显示面板13显示不同画面。
基于相同的构思，本申请还提供了一种显示装置100，所述显示装置100包括显示模组10和电源模组20，所述电源模组20设置于所述显示模组10的非显示面，所述电源模组20用于为所述显示模组10进行图像显示提供电源电压。
可以理解的是，本申请实施方式提供的显示装置100可以是笔记本电脑显示屏、液晶显示器、液晶电视、手机、平板电脑等任何具有显示功能的产品或部件。
在其中一个实施例中，所述显示装置100还包括高压板、按键控制板等其他必要的部件和组成，本领域技术人员可根据该显示装置100的具体类型和实际功能进行相应地补充，在此不再赘述。
可以理解地，所述显示装置100还可用于包含诸如个人数字助理(Personal Digital Assistant，PDA)和/或音乐播放器功能的电子设备，诸如手机、平板电脑、具备无线通讯功能的可穿戴电子设备(如智能手表)等。上述电子设备也可以是其它电子装置，诸如具有触敏表面(例如触控面板)的膝上型计算机(Laptop)等。
综上所述，在本申请提供的驱动电路、显示模组10和显示装置100中，设置所述信号控制单元40和所述开关单元50，选择性控制k个所述扫描信号输入端61接收或停止接收所述扫描信号，有效控制所述驱动电路在进行行扫描时正常传输扫描信号至所述像素阵列单元60，在行扫描切换时间停止传输所述扫描信号至所述像素阵列单元60，避免了在行扫描切换时间残留的扫描信号电荷继续产生寄生电容，有效避免了切换时间寄生电容继续增加，加重所述电荷释放单元70的泄放工作量，以及所述电荷释放单元70泄放能力不足造成的余晖异常的问题。此外，所述信号控制单元40和所述开关单元50相配合控制k条扫描线在切换时间短接，进而提高了电连接至对应扫描线的电容71上电荷的泄放速率。具体地，k条扫描线短接，则对应扫描线的电容71上电荷泄放速率较未短接时提升k倍。大大降低了由于寄生电容上的电荷泄放不净或得不到及时足 够释放而造成的余晖异常的问题，从而有效提高了所述驱动电路驱动的正确性，保证了所述显示模组10的显示效果。
对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”或“一些示例”等的描述意指结合所述实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
应当理解的是，以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种驱动电路，其中，包括至少一个信号控制单元、开关单元、像素阵列单元和电荷释放单元，其中，
    每个所述信号控制单元包括多个扫描输入端和输出信号端，所述扫描输入端接收扫描信号，所述信号控制单元根据所述扫描信号自所述输出信号端输出控制信号；
    所述开关单元包括开关输入端、多个第一开关输出端和多个第二开关输出端，所述开关输入端与所述输出信号端电连接，并接收所述控制信号；
    所述像素阵列单元包括多个扫描信号输入端和多个电荷输出端，其中，多个所述扫描信号输入端同时电连接至多个所述第一开关输出端和多个所述第二开关输出端，所述第一开关输出端或所述第二开关输出端根据所述控制信号选择性与所述扫描信号输入端导通，使所述扫描信号选择性传输至所述像素阵列单元；
    所述电荷释放单元包括多个电荷释放端，每个所述电荷释放端电连接至每个所述电荷输出端，所述电荷释放单元释放所述像素阵列单元产生的寄生电容的至少部分电荷。
  2. 如权利要求1所述的驱动电路，其中，所述信号控制单元为或门电路，所述或门电路包括所述输出信号端和多个所述扫描输入端，多个所述扫描输入端接收多个所述扫描信号，当多个所述扫描信号至少有一个处于第一电位时，所述输出信号端输出处于第一电位的控制信号；当多个所述扫描信号均处于第二电位时，所述输出信号端输出处于第二电位的控制信号。
  3. 如权利要求1所述的驱动电路，其中，所述开关单元包括多个第一晶体管，每个所述第一晶体管包括控制端、第一端和第二端，其中，所述第一晶体管的控制端电连接至所述开关输入端，用于接收所述控制信号，所述第一晶体管的第一端用于接收所述扫描信号，所述第一晶体管的第二端对应电连接至所述第一开关输出端。
  4. 如权利要求3所述的驱动电路，其中，当所述控制端接收的控制信号处于第一电位时，每个所述第一晶体管的第一端和第二端电性导通，多个所述扫描信号自多个所述扫描信号输入端传输至所述像素阵列单元；
    当所述控制端接收的所述控制信号处于第二电位时，每个所述第一晶体管的第一端和第二端电性断开。
  5. 如权利要求4所述的驱动电路，其中，所述开关单元还包括若干第二晶体管，每个所述第二晶体管包括控制端、第一端和第二端，其中，所述第二晶体管的控制端电连接至所述开关输入端，用于接收所述控制信号，每个所述第二晶体管的两端分别电连接至相邻两个所述第二开关输出端。
  6. 如权利要求5所述的驱动电路，其中，当所述控制端接收的所述控制信号处于第一电位时，若干所述第二晶体管的第一端和第二端电性断开；
    当所述控制端接收的所述控制信号处于第二电位时，若干个所述第二晶体管的第一端和第二端电性导通，多个所述扫描信号输入端之间均电性导通，多个扫描信号无法传输至所述像素阵列单元。
  7. 如权利要求6所述的驱动电路，其中，所述第一晶体管为N型金属氧化物半导体晶体管，所述第二晶体管为P型金属氧化物半导体晶体管。
  8. 如权利要求1所述的驱动电路，其中，所述电荷释放单元包括多个电容，每个所述电容的一端电连接至对应所述电荷释放端，每个所述电容的另一端电连接至所述驱动电路的参考地。
  9. 一种显示模组，其中，所述显示模组包括显示面板和若干驱动电路，所述驱动电路与所述显示面板电连接，所述驱动电路用于驱动所述显示面板显示画面，每个所述驱动电路包括至少一个信号控制单元、开关单元、像素阵列单元和电荷释放单元，每个所述信号控制单元包括多个扫描输入端和输出信号端，所述扫描输入端接收扫描信号，所述信号控制单元根据所述扫描信号自所述输出信号端输出控制信号；
    所述开关单元包括开关输入端、多个第一开关输出端和多个第二开关输出端，所述开关输入端与所述输出信号端电连接，并接收所述控制信号；
    所述像素阵列单元包括多个扫描信号输入端和多个电荷输出端，其中，多个所述扫描信号输入端同时电连接至多个所述第一开关输出端和多个所述第二开关输出端，所述第一开关输出端或所述第二开关输出端根据所述控制信号选择性与所述扫描信号输入端导通，使所述扫描信号选择性传输至所述像素阵列单元；
    所述电荷释放单元包括多个电荷释放端，每个所述电荷释放端电连接至每个所述电荷输出端，所述电荷释放单元释放所述像素阵列单元产生的寄生电容的至少部分电荷。
  10. 如权利要求9所述的显示模组，其中，所述信号控制单元为或门电路， 所述或门电路包括所述输出信号端和多个所述扫描输入端，多个所述扫描输入端接收多个所述扫描信号，当多个所述扫描信号至少有一个处于第一电位时，所述输出信号端输出处于第一电位的控制信号；当多个所述扫描信号均处于第二电位时，所述输出信号端输出处于第二电位的控制信号。
  11. 如权利要求9所述的显示模组，其中，所述开关单元包括多个第一晶体管，每个所述第一晶体管包括控制端、第一端和第二端，其中，所述第一晶体管的控制端电连接至所述开关输入端，用于接收所述控制信号，所述第一晶体管的第一端用于接收所述扫描信号，所述第一晶体管的第二端对应电连接至所述第一开关输出端。
  12. 如权利要求11所述的显示模组，其中，当所述控制端接收的控制信号处于第一电位时，每个所述第一晶体管的第一端和第二端电性导通，多个所述扫描信号自多个所述扫描信号输入端传输至所述像素阵列单元；
    当所述控制端接收的所述控制信号处于第二电位时，每个所述第一晶体管的第一端和第二端电性断开。
  13. 如权利要求12所述的显示模组，其中，述开关单元还包括若干第二晶体管，每个所述第二晶体管包括控制端、第一端和第二端，其中，所述第二晶体管的控制端电连接至所述开关输入端，用于接收所述控制信号，每个所述第二晶体管的两端分别电连接至相邻两个所述第二开关输出端。
  14. 如权利要求13所述的显示模组，其中，当所述控制端接收的所述控制信号处于第一电位时，若干所述第二晶体管的第一端和第二端电性断开；
    当所述控制端接收的所述控制信号处于第二电位时，若干个所述第二晶体管的第一端和第二端电性导通，多个所述扫描信号输入端之间均电性导通，多个扫描信号无法传输至所述像素阵列单元。
  15. 如权利要求14所述的显示模组，其中，所述第一晶体管为N型金属氧化物半导体晶体管，所述第二晶体管为P型金属氧化物半导体晶体管。
  16. 如权利要求9所述的显示模组，其中，所述电荷释放单元包括多个电容，每个所述电容的一端电连接至对应所述电荷释放端，每个所述电容的另一端电连接至所述驱动电路的参考地。
  17. 一种显示装置，包括电源模组和显示模组，所述电源模组设置于所述显示模组的非显示面，所述电源模组用于为所述显示模组进行图像显示提供电源电压，所述显示模组包括显示面板和若干驱动电路，所述驱动电路与所述显示 面板电连接，所述驱动电路用于驱动所述显示面板显示画面，其中，每个所述驱动电路包括至少一个信号控制单元、开关单元、像素阵列单元和电荷释放单元，每个所述信号控制单元包括多个扫描输入端和输出信号端，所述扫描输入端接收扫描信号，所述信号控制单元根据所述扫描信号自所述输出信号端输出控制信号；
    所述开关单元包括开关输入端、多个第一开关输出端和多个第二开关输出端，所述开关输入端与所述输出信号端电连接，并接收所述控制信号；
    所述像素阵列单元包括多个扫描信号输入端和多个电荷输出端，其中，多个所述扫描信号输入端同时电连接至多个所述第一开关输出端和多个所述第二开关输出端，所述第一开关输出端或所述第二开关输出端根据所述控制信号选择性与所述扫描信号输入端导通，使所述扫描信号选择性传输至所述像素阵列单元；
    所述电荷释放单元包括多个电荷释放端，每个所述电荷释放端电连接至每个所述电荷输出端，所述电荷释放单元释放所述像素阵列单元产生的寄生电容的至少部分电荷。
  18. 如权利要求17所述的显示装置，其中，所述信号控制单元为或门电路，所述或门电路包括所述输出信号端和多个所述扫描输入端，多个所述扫描输入端接收多个所述扫描信号，当多个所述扫描信号至少有一个处于第一电位时，所述输出信号端输出处于第一电位的控制信号；当多个所述扫描信号均处于第二电位时，所述输出信号端输出处于第二电位的控制信号。
  19. 如权利要求17所述的显示装置，其中，所述开关单元包括多个第一晶体管，每个所述第一晶体管包括控制端、第一端和第二端，其中，所述第一晶体管的控制端电连接至所述开关输入端，用于接收所述控制信号，所述第一晶体管的第一端用于接收所述扫描信号，所述第一晶体管的第二端对应电连接至所述第一开关输出端；
    当所述控制端接收的控制信号处于第一电位时，每个所述第一晶体管的第一端和第二端电性导通，多个所述扫描信号自多个所述扫描信号输入端传输至所述像素阵列单元；
    当所述控制端接收的所述控制信号处于第二电位时，每个所述第一晶体管的第一端和第二端电性断开。
  20. 如权利要求19所述的显示装置，其中，所述开关单元还包括若干第二 晶体管，每个所述第二晶体管包括控制端、第一端和第二端，其中，所述第二晶体管的控制端电连接至所述开关输入端，用于接收所述控制信号，每个所述第二晶体管的两端分别电连接至相邻两个所述第二开关输出端；
    当所述控制端接收的所述控制信号处于第一电位时，若干所述第二晶体管的第一端和第二端电性断开；
    当所述控制端接收的所述控制信号处于第二电位时，若干个所述第二晶体管的第一端和第二端电性导通，多个所述扫描信号输入端之间均电性导通，多个扫描信号无法传输至所述像素阵列单元。
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