WO2024001053A1 - 扫描驱动电路、阵列基板和显示面板 - Google Patents

扫描驱动电路、阵列基板和显示面板 Download PDF

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Publication number
WO2024001053A1
WO2024001053A1 PCT/CN2022/137322 CN2022137322W WO2024001053A1 WO 2024001053 A1 WO2024001053 A1 WO 2024001053A1 CN 2022137322 W CN2022137322 W CN 2022137322W WO 2024001053 A1 WO2024001053 A1 WO 2024001053A1
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Prior art keywords
transistor
electrically connected
node
pull
potential
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PCT/CN2022/137322
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English (en)
French (fr)
Inventor
李阳
李荣荣
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HKC Co Ltd
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HKC Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of display technology, and in particular, to a scan driving circuit, an array substrate and a display panel.
  • LCD Liquid Crystal Display
  • GDL Gate Driver Less
  • the scanning signal output by the GDL circuit converts from high potential to low potential, it requires a certain falling time.
  • the shorter the falling time the closer the waveform of the scanning signal is to the ideal state, and the more stable the GDL circuit will be. Therefore, how to reduce the falling time of the scanning signal output by the GDL circuit is a problem that needs to be solved.
  • the present application provides a scan driving circuit, an array substrate and a display panel, which are used to reduce the falling time of the scan signal output by the GDL circuit and improve the stability of the GDL circuit.
  • an embodiment of the present application provides a scan driving circuit, including: N GDL circuits in cascade, and the nth GDL circuit includes: a pull-up control module, an output module, and a first pull-down control module, the second pull-down control module, the pull-down module, the first node and the second node, N is a positive integer, n ⁇ [1, N];
  • the pull-up control module, the first pull-down control module and the output module are all electrically connected to the first node.
  • the pull-up control module is used to pull up the signal according to the received first target level transmission signal.
  • the potential of the first node is to the first potential;
  • the first pull-down control module is used to pull down the first node to the second potential according to the received second target level transmission signal
  • the output module is configured to output the n-th level transmission signal and the n-th level scanning signal according to the input clock signal when the potential of the first node is the first potential; when the potential of the first node is In the case of the second potential, stop outputting the n-th stage transmission signal and the n-th level scanning signal; the high-potential duration period of the clock signal includes the first period and the second period, and the clock signal is in the The first high potential is maintained during the first period, and the second high potential is maintained during the second period, and the second high potential is higher than the first high potential;
  • the second pull-down control module and the pull-down module are both electrically connected to the second node, and the second pull-down control module is used to pull up the potential of the second node to the first potential;
  • the pull-down module is used to pull down the potential of the output terminal of the output module when the potential of the second node is the first potential.
  • the proportion of the first period of the clock signal relative to the high potential duration period is less than or equal to 1/4.
  • the proportion of the first period of the clock signal relative to the high potential duration period is equal to 1/8.
  • the duty cycle of the high potential duration period of the clock signal is less than 1/2.
  • the first target level transmission signal is the n-5th level transmission signal
  • the second target level transmission signal is the n+6th level transmission signal, 5 ⁇ n ⁇ N-6.
  • the pull-up control module includes: a first transistor, and the control electrode and the first electrode of the first transistor are both connected to the first target level transmission signal, so The second pole of the first transistor is electrically connected to the first node.
  • the output module includes: a second transistor and a third transistor, and the control electrodes of the second transistor and the third transistor are both electrically connected to the first node. , the first pole of the second transistor and the third transistor are connected to the same clock signal, the second pole of the second transistor outputs the n-th level transmission signal, and the second pole of the third transistor Output the nth level scanning signal.
  • the first pull-down control module includes: a fourth transistor, the control electrode of the fourth transistor is connected to the second target stage to transmit a signal, and the fourth transistor The first pole of the transistor is electrically connected to the first low voltage terminal, and the second pole of the fourth transistor is electrically connected to the first node.
  • the first pull-down control module includes a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor;
  • the gate of the fourth transistor is connected to the second target stage to transmit signals, the source of the fourth transistor is electrically connected to the first node of the nth stage, and the drain of the fourth transistor is connected to the first node of the nth stage.
  • the gate of the fifth transistor is connected to the first reset signal, the source of the fifth transistor is electrically connected to the first node of the nth stage, and the drain of the fifth transistor is connected to the first low voltage terminal electrical connection;
  • the gate of the sixth transistor is electrically connected to the second node of the n+1th stage, the source of the sixth transistor is electrically connected to the first node of the nth stage, and the drain of the sixth transistor is electrically connected to the first low voltage terminal electrical connection;
  • the gate of the seventh transistor is electrically connected to the second node of the nth level, the source of the seventh transistor is electrically connected to the first node of the nth level, and the drain of the seventh transistor electrically connected to the first low-voltage terminal.
  • the second pull-down control module includes an eighth transistor, a ninth transistor and a tenth transistor;
  • the source and gate of the eighth transistor are both electrically connected to the power supply voltage, and the drain of the eighth transistor is electrically connected to the gate of the ninth transistor and the source of the tenth transistor T10;
  • the source of the ninth transistor is electrically connected to the power supply voltage, and the drain of the ninth transistor is electrically connected to the second node of the nth stage;
  • the gate of the tenth transistor is electrically connected to the first node of the nth stage, and the drain of the tenth transistor is electrically connected to the first low voltage terminal.
  • the pull-down module includes an eleventh transistor, a twelfth transistor, a thirteenth transistor and a fourteenth transistor;
  • the gate of the eleventh transistor is electrically connected to the second node of the nth stage, the source of the eleventh transistor is electrically connected to the source of the second transistor, and the The drain is electrically connected to the first low-voltage terminal;
  • the gate of the twelfth transistor is electrically connected to the second node of the nth stage, the source of the twelfth transistor is electrically connected to the source of the third transistor, and the source of the twelfth transistor is electrically connected.
  • the drain is electrically connected to the second low-voltage terminal;
  • the gate of the thirteenth transistor is electrically connected to the second node of the n+1th stage, and the source of the thirteenth transistor is electrically connected to the source of the third transistor.
  • the drain of the transistor is electrically connected to the second low voltage terminal;
  • the gate of the fourteenth transistor is electrically connected to the second node of the n+1th stage, and the source of the fourteenth transistor is electrically connected to the source of the second transistor.
  • the drain of the transistor is electrically connected to the first low voltage terminal.
  • the n-th GDL circuit further includes:
  • a pull-down maintenance module is electrically connected to the second node, and is used to maintain the potential of the second node according to the received first target level transmission signal.
  • the pull-down sustain module includes a fifteenth transistor, a sixteenth transistor and a seventeenth transistor
  • the gate of the fifteenth transistor is electrically connected to the first node of the nth stage, and the source of the fifteenth transistor is electrically connected to the second node of the nth stage.
  • the fifteenth transistor The drain is electrically connected to the first low voltage terminal;
  • the gate of the sixteenth transistor is connected to the first target stage to transmit the signal, the drain of the sixteenth transistor is electrically connected to the first low voltage terminal, and the source of the sixteenth transistor is connected to the first low voltage terminal.
  • the second node of level n is electrically connected;
  • the gate of the seventeenth transistor is electrically connected to the first node of the n+1th stage, and the source of the seventeenth transistor is electrically connected to the drain of the ninth transistor.
  • the drain of the transistor is electrically connected to the first low voltage terminal.
  • embodiments of the present application provide an array substrate, including: a scan drive circuit as described in the above first aspect or any one of the first aspects and N scan lines, and N GDLs in the scan drive circuit
  • the circuit is connected to the N scanning lines in one-to-one correspondence, and each scanning line is connected to multiple pixel units.
  • the array substrate further includes: a data drive circuit and a timing control circuit;
  • the data driving circuit is electrically connected to each data line, and the data driving circuit is used to transmit the image data to be displayed to the corresponding pixel unit in the form of data voltage through the data line;
  • the timing control circuit is electrically connected to the data driving circuit and the scan driving circuit respectively, and the timing control circuit is used to output a clock signal to control the working timing of the data driving circuit and the scanning driving circuit.
  • embodiments of the present application provide a display panel.
  • the non-display area of the display panel includes signal lines and a scan driving circuit as described in the above first aspect or any one of the first aspects.
  • the scan drive circuit, array substrate and display panel provided by the embodiment of the present application include N GDL circuits in cascade.
  • the n-th GDL circuit includes: a pull-up control module, an output module, a first pull-down control module, a second pull-down
  • the control module, the pull-down module, the first node and the second node, N is a positive integer, n ⁇ [1, N]; the pull-up control module, the first pull-down control module and the output module are all electrically connected to the first node.
  • the pull control module is used to pull up the potential of the first node to the first potential according to the received first target level transmission signal; the first pull down control module is used to pull down the first node to the first level according to the received second target level transmission signal.
  • the output module is used to output the n-th level transmission signal and the n-th level scanning signal according to the input clock signal when the potential of the first node is the first potential; when the potential of the first node is the second When the potential is high, stop outputting the n-th stage transmission signal and the n-th level scanning signal;
  • the high-potential duration period of the clock signal includes the first period and the second period, and the clock signal maintains the first high-potential in the first period, and in the The second high potential is maintained during the second period, and the second high potential is higher than the first high potential;
  • the second pull-down control module and the pull-down module are both electrically connected to the second node, and the second pull-down control module is used to pull up the potential of the second node to The first potential;
  • the pull-down module is used to pull down the potential of the output terminal of the output module when the potential of the second node is the first potential.
  • the high potential duration period of the clock signal includes a first period and a second period.
  • the clock signal maintains the first high potential in the first period, maintains the second high potential in the second period, and the second high potential is higher than the second period.
  • a high potential so that the potential of each level transmission signal will first maintain the first high potential for a period of time, and then rise to the second high potential, that is, the second target level transmission signal received by the first pull-down control module of each GDL circuit , will also maintain the first high potential for a period of time. Therefore, the potential of the first node of each GDL circuit can not be directly pulled down to the second potential during this period of time, but can be higher than the second potential.
  • each GDL circuit can still output scanning signals during this period, and can quickly reduce the potential of the scanning signals according to the reduction of the input clock signal potential. Therefore, this solution can reduce the falling time of each scanning signal in the GDL circuit. , improve the stability of GDL circuit.
  • Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • Figure 2 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of the connection relationship between the timing control circuit and the scan drive circuit provided by the embodiment of the present application;
  • Figure 4 is a schematic structural diagram of a GDL circuit provided by an embodiment of the present application.
  • Figure 5 is a timing diagram of a clock signal provided by an embodiment of the present application.
  • Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the display panel provided by an embodiment of the present application may include: a display area 1A and a non-display area 1B.
  • the display area 1A is used to display images
  • the non-display area 1A is used to display images.
  • the display area 1B is arranged around the display area 1A and is used for arranging other auxiliary components or modules.
  • the display panel may include: an array substrate 1 , a color filter substrate 2 and a liquid crystal layer 3 .
  • the array substrate 1 and the color filter substrate 2 are arranged oppositely, and the liquid crystal layer 3 is located between the array substrate 1 and the color filter substrate 2 .
  • Figure 2 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • the display area 1A of the array substrate 1 may include: N scanning lines 11, M data lines 12 and a plurality of pixel units P, N and M are positive integers;
  • the non-display area 1B of the array substrate 1 may include: a data driving circuit 13, a timing control circuit 14 and a scan driving circuit 15.
  • the pixel units P can be arranged in an array, and each scan line 11 can be electrically connected to the pixel units P corresponding to one row.
  • Display panels with different resolutions also have different numbers of rows and columns of pixel units P. This embodiment will be described later by taking the pixel unit P in the display panel as 2160 rows as an example.
  • the data driving circuit 13 can be electrically connected to each data line 12, and the data driving circuit 13 is used to transmit the image data to be displayed to the corresponding pixel unit P in the form of data voltage through the data line 12.
  • the timing control circuit 14 is electrically connected to the data driving circuit 13 and the scanning driving circuit 15 respectively, and is used to output a clock signal to control the working timing of the data driving circuit 13 and the scanning driving circuit 15 .
  • the resolution of the display panel is different, and the number of clock signals output by the timing control circuit 14 may also be different.
  • the clock signals output by the timing control circuit 14 may be 4 clock signals, 8 clock signals, or 10 clock signals or 12 clock signals, etc. This embodiment will take the timing control circuit 14 outputting 8 clock signals as an example for illustrative explanation.
  • the scan drive circuit 15 may be electrically connected to the scan line 11 , and the scan drive circuit 15 is used to output a scan signal through the scan line 11 to control the time at which each pixel unit P receives image data.
  • the scan driving circuit 15 can be disposed in the non-display area 1B of the array substrate 1 through GDL technology, which can include multiple GDL circuits to make the frame of the display panel narrower.
  • Figure 3 is a schematic diagram of the connection relationship between the timing control circuit and the scan drive circuit provided by the embodiment of the present application.
  • the scan drive circuit 15 provided by the embodiment of the present application may include 2160 cascaded GDL circuits.
  • 2160 cascaded GDL circuits can be GDL1, GDL2,..., GDL2160 in sequence.
  • Each GDL circuit can receive a ladder-like clock signal in the rising stage and output a scan signal according to the clock signal.
  • 2160 GDL circuits The corresponding output 2160 scanning signals can be G1, G2,..., G2160 in sequence. Each scan signal is used to drive the scan lines 11 of the corresponding pixel row in the display area 1A of the array substrate 1 respectively.
  • the phases of the clock signals received by any two adjacent GDL circuits can be different to output two scanning signals separated by a period of time, so that progressive scanning of pixels can be achieved.
  • the scan driving circuit 15 can also receive the start signal STV, the reset signal Reset, the first low level signal VSSQ, the second low level signal VSSG and the power supply voltage VDD_O output by the timing control circuit 14 .
  • the GDL1, GDL2, GDL3, GDL4 and GDL5 circuits in the scan driver circuit 15 can receive the start signal STV output by the timing control circuit 14, and other GDL circuits can receive the start signal STV through the cascade circuit.
  • the reset signal Reset, the first low-level signal VSSQ and the second low-level signal VSSG are used to pull down the node voltage of each GDL circuit.
  • the power supply voltage VDD_O may be a high potential and is used to provide a stable high potential voltage to each GDL circuit.
  • the display panel may also include other auxiliary circuits for jointly completing image display, such as image receiving and processing circuits, power supply circuits, etc., which will not be described in detail in this embodiment.
  • the following takes two GDL circuits as an example to illustrate the structure of the GDL circuit and the connection relationship between the GDL circuits.
  • Figure 4 is a schematic structural diagram of a GDL circuit provided by an embodiment of the present application.
  • the n-th GDL circuit may include: a pull-up control module 1511, an output module 1512, a first pull-down control module 1513, and a second pull-down control module.
  • the pull-up control module 1511 is electrically connected to the first node Q(n), and accesses the first target stage transmission signal (here, the n-5th stage transmission signal C(n-5)).
  • the pull-up control module 1511 It is used to pull up the potential of the first node Q(n) to the first potential according to the received n-5th level transmission signal C(n-5), where the first potential is a high potential.
  • the first target stage transmission signal may be the start signal STV.
  • the first pull-down control module 1513 is electrically connected to the first node Q(n), and accesses the second target stage transmission signal (here, the n+6th stage stage transmission signal C(n+6)), the first reset signal Reset and the first low level signal VSSQ.
  • the first pull-down control module 1513 is configured to pull down the potential of the first node Q(n) to the second potential through the first low-level signal VSSQ according to the received n+6th stage transmission signal C(n+6).
  • the second potential is a low potential.
  • the first pull-down control module 1513 is also used to pull down the potential of the first node Q(n) according to the first reset signal Reset.
  • the GDL circuit may also include a pull-down signal output unit.
  • the second target stage transmission signal may be a pull-down signal output by the pull-down signal output unit.
  • the first target level transmission signal and the second target level transmission signal can also be other level transmission signals.
  • the first target level transmission signal can be the n-4th level transmission signal
  • the second target level transmission signal can be The signal is transmitted at the n+5th level, and this embodiment does not specifically limit this.
  • the output module 1512 is electrically connected to the first node Q(n), and is connected to the clock signal CLK(n), for when the electric potential of the first node Q(n) is the first electric potential, the output module 1512 is used to output the signal according to the clock signal CLK(n) when the electric potential of the first node Q(n) is the first electric potential.
  • ) outputs the n-th level transmission signal C(n) and the n-th level scanning signal G(n); when the potential of the first node Q(n) is the second potential, stops outputting the n-th level transmission signal C (n) and the nth level scanning signal G(n).
  • the timing relationship of the eight clock signals output by the timing control circuit 14 can be as shown in Figure 5.
  • the phases of each clock signal are different.
  • the high-potential duration period of each clock signal can include a first period and a second period. Each clock signal has a different phase.
  • the clock signal can maintain the first high potential in the first period and the second high potential in the second period.
  • the second high potential is higher than the first high potential. In this way, the potential of the signals transmitted at each level will also maintain the first high potential first. After a period of time, it rises to the second high potential, that is, the second target level transmission signal received by the first pull-down control module 1513 of each GDL circuit will also maintain the first high potential for a period of time.
  • each GDL circuit's The potential of the first node Q(n) can not be directly pulled down to the second potential during this period of time, but can be higher than the second potential.
  • the output module 1512 of each GDL circuit can still output during this period of time. Scan signal, and can quickly reduce the potential of the scan signal according to the reduction of the input clock signal potential. Therefore, this solution can reduce the falling time of each scan signal in the GDL circuit and improve the stability of the GDL circuit.
  • the duty cycle of the high-potential duration period of the clock signal can be 1/2, or can be appropriately adjusted to be smaller, which can also reduce the falling time of the scan signal output by the GDL circuit.
  • the proportion of the first period of the clock signal relative to the high-potential duration period can be less than or equal to 1/4 to ensure that the clock signal maintains the second high-potential time.
  • the first period of the clock signal relative to the high-voltage duration period can be 1/8, so that the potential of the corresponding scanning signal can be quickly pulled down according to the low-level clock signal, and the clock signal can also be ensured to maintain the second highest potential, so that the display panel has sufficient charging time.
  • the second pull-down control module 1514 is electrically connected to the second node Qb(n) and connected to the power supply voltage VDD_O.
  • the second pull-down control module 1514 is used to pull up the potential of the second node Qb(n) to the first potential.
  • the pull-down module 1515 is electrically connected to the second node Qb(n), and is connected to the first low-level signal VSSQ and the second low-level signal VSSG, for when the potential of the second node Qb(n) is the first potential. In this case, the potential of the output terminal of the output module 1512 is pulled down according to the first low-level signal VSSQ and the second low-level signal VSSG.
  • the GDL circuit may also include a pull-down sustain module 1516.
  • the pull-down sustain module 1516 is electrically connected to the first node Q(n) and accesses the n-5th stage transmission signal C(n-5) and the first low-level signal VSSQ.
  • the pull-down maintenance module 1516 is used to maintain the potential of the second node Qb(n) according to the n-5th stage transmission signal C(n-5).
  • the n+1th GDL circuit may include: pull-up control module 1511, output module 1512, first pull-down control module 1513, second pull-down control module 1514, pull-down module 1515, pull-down signal output unit, pull-down maintenance module 1516, first node Q(n+1) and second node Qb(n+1).
  • the pull-up control module 1511 is used to receive the n-4th level transmission signal C(n-4), and pull up the first node Q(n+1) according to the n-4th level transmission signal C(n-4). ) potential to the first potential.
  • the first pull-down control module 1513 is used to receive the n+7th level transmission signal C(n+7), and pull down the first node Q(n+1) according to the n+7th level transmission signal C(n+7). potential to the second potential.
  • the output module 1512 is configured to output the n+1-th stage transmission signal C(n+1) and The n+1th level scanning signal G(n+1); when the potential of the first node Q(n+1) is the second potential, stop outputting the n+1th level scanning signal C(n+1) and the n+1th level scanning signal G(n+1).
  • the pull-up control module 1511 of the n-th GDL circuit may include: a first transistor T1, the gate and drain of the first transistor T1 are both connected to the n-5th level transmission signal C(n-5), The source of the first transistor T1 is electrically connected to the first node Q(n).
  • the output module 1512 may include: a second transistor T2 and a third transistor T3. Gates of the second transistor T2 and the third transistor T3 are both electrically connected to the first node Q(n). The drain is connected to the same clock signal CLK(N), the source of the second transistor T2 outputs the n-th level transmission signal C(n), and the source of the third transistor T3 outputs the n-th level scanning signal G(n).
  • the first pull-down control module 1513 may include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.
  • the gate of the fourth transistor T4 is connected to the n+6th level transmission signal C(n+6)
  • the source is electrically connected to the first node Q(n)
  • the drain is electrically connected to the first low-voltage terminal. Receive the first low level signal VSSQ.
  • the gate of the fifth transistor T5 is connected to the first reset signal Reset, the source is electrically connected to the first node Q(n), and the drain is electrically connected to the first low-voltage terminal to receive the first low-level signal VSSQ.
  • the gate of the sixth transistor T6 is electrically connected to the second node Qb(n+1) of the n+1th GDL circuit, the source is electrically connected to the first node Q(n), and the drain is electrically connected to the first low-voltage terminal. , to receive the first low-level signal VSSQ.
  • the gate of the seventh transistor T7 is electrically connected to the second node Qb(n), the source is electrically connected to the first node Q(n), and the drain is electrically connected to the first low-voltage terminal to receive the first low-level signal VSSQ. .
  • the first low-level signal VSSQ output by the first low-voltage terminal can pull the potential of the first node Q(n) down to a level higher than the first low-voltage terminal.
  • the third potential of the two potentials therefore, the second transistor T2 and the third transistor T3 are still turned on during this period, and the source of the third transistor T3 can still output the n-th level scanning signal G(n), and in the clock
  • the potential of the n-th level scanning signal G(n) can be quickly reduced, thereby reducing the fall time of the n-th level scanning signal G(n).
  • the second pull-down control module 1514 may include an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10.
  • the source and gate of the eighth transistor T8 are both electrically connected to the power supply voltage VDD_O, and the drain is electrically connected to the gate of the ninth transistor T9 and the source of the tenth transistor T10.
  • the source of the ninth transistor T9 is electrically connected to the power supply voltage VDD_O, and the drain is electrically connected to the second node Qb(n).
  • the gate of the tenth transistor T10 is electrically connected to the first node Q(n), and the drain is electrically connected to the first low-voltage terminal to receive the first low-level signal VSSQ.
  • the pull-down module 1515 may include an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14.
  • the gate of the eleventh transistor T11 is electrically connected to the second node Qb(n)
  • the source is electrically connected to the source of the second transistor T2
  • the drain is electrically connected to the first low voltage terminal to receive the first low voltage.
  • Flat signal VSSQ The gate of the twelfth transistor T12 is electrically connected to the second node Qb(n)
  • the source is electrically connected to the source of the third transistor T3, and the drain is electrically connected to the second low-voltage terminal to receive the second low-level signal.
  • VSSG the eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14.
  • the gate of the eleventh transistor T11 is electrically connected to the second node Qb(n)
  • the source is electrically connected
  • the gate of the thirteenth transistor T13 is electrically connected to the second node Qb(n+1) of the n+1th GDL circuit, the source is electrically connected to the source of the third transistor T3, and the drain is electrically connected to the second low-voltage terminal. Connect to receive the second low level signal VSSG.
  • the gate of the fourteenth transistor T14 is electrically connected to the second node Qb(n+1) of the n+1th GDL circuit, the source is electrically connected to the source of the second transistor T2, and the drain is electrically connected to the first low voltage terminal. Connect to receive the first low level signal VSSQ.
  • the pull-down sustain module 1516 may include a fifteenth transistor T15, a sixteenth transistor T16, and a seventeenth transistor T17.
  • the gate of the fifteenth transistor T15 is electrically connected to the first node Q(n)
  • the source is electrically connected to the second node Qb(n)
  • the drain is electrically connected to the first low voltage terminal to receive the first low voltage.
  • Flat signal VSSQ The gate of the sixteenth transistor T16 is connected to the n-5th stage transmission signal C(n-5)
  • the drain is electrically connected to the first low-voltage terminal to receive the first low-level signal VSSQ
  • the source is connected to the second Node Qb(n) is electrically connected.
  • the gate of the seventeenth transistor T17 is electrically connected to the first node Q(n+1) of the n+1th GDL circuit, the source is electrically connected to the drain of the ninth transistor T9, and the drain is electrically connected to the first low voltage terminal. Connect to receive the first low level signal VSSQ.
  • each module in the n+1th GDL circuit is similar to those in the nth GDL circuit, and will not be described again here.
  • connection relationship of each component in the n+1th GDL circuit is similar to that of the nth GDL circuit.
  • the main differences lie in the following points. Among them, unless otherwise specified, the components described below all represent the n+1th Components in GDL circuits.
  • the gate and drain of the first transistor T1 of the pull-up control module 1511 are both connected to the n-4th stage transmission signal C(n-4), and the source is electrically connected to the first node Q(n+1).
  • the gates of the second transistor T2 and the third transistor T3 of the output module 1512 are both electrically connected to the first node Q(n+1), the drain is connected to the clock signal CLK(n+1), and the source of the second transistor T2
  • the n+1th stage transmission signal C(n+1) is output, and the source of the third transistor T3 outputs the n+1th stage scanning signal G(n+1).
  • the gate of the fourth transistor T4 of the first pull-down control module 1513 is connected to the n+7th level transmission signal C(n+7), the source is electrically connected to the first node Q(n+1), and the drain is connected to the n+7th stage transmission signal C(n+7).
  • the first low voltage terminal is electrically connected.
  • the gate of the sixth transistor T6 is electrically connected to the second node Qb(n) of the n-th GDL circuit, the source is electrically connected to the first node Q(n+1), and the drain is electrically connected to the first low-voltage terminal.
  • the gate of the thirteenth transistor T13 of the pull-down module 1515 is electrically connected to the second node Qb(n) of the n-th GDL circuit, the source is electrically connected to the source of the third transistor T3, and the drain is electrically connected to the second low-voltage terminal.
  • the gate of the fourteenth transistor T14 is electrically connected to the second node Qb(n) of the n-th GDL circuit, the source is electrically connected to the source of the second transistor T2, and the drain is electrically connected to the first low-voltage terminal.
  • the gate of the seventeenth transistor T17 of the pull-down holding module 1516 is electrically connected to the first node Q(n) of the n-th GDL circuit, the source is electrically connected to the drain of the ninth transistor T9, and the drain is electrically connected to the first low voltage terminal. Electrical connection.
  • each transistor can be an N-type field effect transistor to reduce the impedance of each transistor in the circuit. This is used as an example in Figure 4. sexual description.
  • each transistor may also be a P-type field effect transistor to reduce costs, which is not particularly limited in this embodiment.
  • the scan drive circuit, array substrate and display panel provided by the embodiment of the present application include N GDL circuits in cascade.
  • the n-th GDL circuit includes: a pull-up control module, an output module, a first pull-down control module, a second pull-down
  • the control module, the pull-down module, the first node and the second node, N is a positive integer, n ⁇ [1, N]; the pull-up control module, the first pull-down control module and the output module are all electrically connected to the first node.
  • the pull control module is used to pull up the potential of the first node to the first potential according to the received first target level transmission signal; the first pull down control module is used to pull down the first node to the first level according to the received second target level transmission signal.
  • the output module is used to output the n-th level transmission signal and the n-th level scanning signal according to the input clock signal when the potential of the first node is the first potential; when the potential of the first node is the second When the potential is high, stop outputting the n-th stage transmission signal and the n-th level scanning signal;
  • the high-potential duration period of the clock signal includes the first period and the second period, and the clock signal maintains the first high-potential in the first period, and in the The second high potential is maintained during the second period, and the second high potential is higher than the first high potential;
  • the second pull-down control module and the pull-down module are both electrically connected to the second node, and the second pull-down control module is used to pull up the potential of the second node to The first potential;
  • the pull-down module is used to pull down the potential of the output terminal of the output module when the potential of the second node is the first potential.
  • the high potential duration period of the clock signal includes a first period and a second period.
  • the clock signal maintains the first high potential in the first period, maintains the second high potential in the second period, and the second high potential is higher than the second period.
  • a high potential so that the potential of each level transmission signal will first maintain the first high potential for a period of time, and then rise to the second high potential, that is, the second target level transmission signal received by the first pull-down control module of each GDL circuit , will also maintain the first high potential for a period of time. Therefore, the potential of the first node of each GDL circuit can not be directly pulled down to the second potential during this period of time, but can be higher than the second potential.
  • each GDL circuit can still output scanning signals during this period, and can quickly reduce the potential of the scanning signals according to the reduction of the input clock signal potential. Therefore, this solution can reduce the falling time of each scanning signal in the GDL circuit. , improve the stability of GDL circuit.
  • A/B can mean A or B; "and/or” in this application only means It is an association relationship that describes associated objects. It means that there can be three relationships.
  • a and/or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. Among them, A and B Can be singular or plural.
  • plural means two or more than two.
  • At least one of the following or similar expressions thereof refers to any combination of these items, including any combination of single or plural items.
  • at least one of a, b, or c can represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c can be single or multiple.
  • the term “if” may be interpreted as “when” or “once” or “in response to determining” or “in response to detecting” depending on the context. ". Similarly, the phrase “if determined” or “if [the described condition or event] is detected” may be interpreted, depending on the context, to mean “once determined” or “in response to a determination” or “once the [described condition or event] is detected ]” or “in response to detection of [the described condition or event]”.

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Abstract

一种扫描驱动电路（15）、阵列基板（1）和显示面板。扫描驱动电路（15）包括级联的N个GDL电路，第n个GDL电路包括:上拉控制模块（1511）、输出模块（1512）、第一下拉控制模块（1513）、第二下拉控制模块（1514）、下拉模块（1515）和第一节点；输出模块（1512）用于在第一节点的电位为第一电位的情况下，根据输入的时钟信号输出第n级级传信号和第n级扫描信号；在第一节点的电位为第二电位的情况下，停止输出第n级级传信号和第n级扫描信号；时钟信号的高电位持续时段包括第一时段和第二时段，时钟信号在第一时段保持第一高电位，在第二时段保持第二高电位，第二高电位高于第一高电位，能够提升GDL电路的稳定性。

Description

扫描驱动电路、阵列基板和显示面板
相关申请的交叉引用
本申请要求享有于2022年06月28日提交的名称为“扫描驱动电路、阵列基板和显示面板”的中国专利申请202210740392X的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本申请涉及显示技术领域，尤其涉及一种扫描驱动电路、阵列基板和显示面板。
背景技术
随着液晶显示技术的不断成熟，液晶显示器(Liquid Crystal Display，LCD)已广泛应用于各个领域。
目前，LCD中普遍采用较少栅极驱动器(Gate Driver Less，GDL)技术，将LCD的栅极扫描驱动电路(也就是GDL电路)制作在阵列基板上，以降低生产成本。
GDL电路输出的扫描信号在由高电位转换为低电位时，需要一定的下降时间，下降时间越短，扫描信号的波形越接近理想状态，GDL电路也就越稳定。因此，如何减小GDL电路输出的扫描信号的下降时间是需要解决的一个问题。
发明内容
有鉴于此，本申请提供一种扫描驱动电路、阵列基板和显示面板，用于减小GDL电路输出的扫描信号的下降时间，提升GDL电路的稳定性。
为了实现上述目的，第一方面，本申请实施例提供一种扫描驱动电路，包括：级联的N个GDL电路，第n个GDL电路包括：上拉控制模块、输出模块、第一下拉 控制模块、第二下拉控制模块、下拉模块、第一节点和第二节点，N为正整数，n∈[1，N]；
所述上拉控制模块、所述第一下拉控制模块和所述输出模块均与所述第一节点电连接，所述上拉控制模块用于根据接收的第一目标级传信号，上拉所述第一节点的电位至第一电位；
所述第一下拉控制模块用于根据接收的第二目标级传信号，下拉所述第一节点至第二电位；
所述输出模块用于在所述第一节点的电位为第一电位的情况下，根据输入的时钟信号输出第n级级传信号和第n级扫描信号；在所述第一节点的电位为第二电位的情况下，停止输出所述第n级级传信号和所述第n级扫描信号；所述时钟信号的高电位持续时段包括第一时段和第二时段，所述时钟信号在所述第一时段保持第一高电位，在所述第二时段保持第二高电位，所述第二高电位高于所述第一高电位；
所述第二下拉控制模块和所述下拉模块均与所述第二节点电连接，所述第二下拉控制模块用于上拉所述第二节点的电位至第一电位；
所述下拉模块用于在所述第二节点的电位为第一电位的情况下，下拉所述输出模块输出端的电位。
作为本申请实施例一种可选的实施方式，所述时钟信号的第一时段相对于所述高电位持续时段的占比小于或等于1/4。
作为本申请实施例一种可选的实施方式，所述时钟信号的第一时段相对于所述高电位持续时段的占比等于1/8。
作为本申请实施例一种可选的实施方式，所述时钟信号的高电位持续时段的占空比小于1/2。
作为本申请实施例一种可选的实施方式，所述第一目标级传信号为第n-5级级传信号，所述第二目标级传信号为第n+6级级传信号，5＜n≤N-6。
作为本申请实施例一种可选的实施方式，所述上拉控制模块包括：第一晶体管，所述第一晶体管的控制极和第一极均接入所述第一目标级传信号，所述第一晶体管的第二极与所述第一节点电连接。
作为本申请实施例一种可选的实施方式，所述输出模块包括：第二晶体管和第三晶体管，所述第二晶体管和所述第三晶体管的控制极均与所述第一节点电连接，所述第二晶体管和所述第三晶体管的第一极接入同一时钟信号，所述第二晶体管的第二极输出所述第n级级传信号，所述第三晶体管的第二极输出所述第n级扫描信号。
作为本申请实施例一种可选的实施方式，所述第一下拉控制模块包括：第四晶体管，所述第四晶体管的控制极接入所述第二目标级传信号，所述第四晶体管的第一极与第一低压端电连接，所述第四晶体管的第二极与所述第一节点电连接。
作为本申请实施例一种可选的实施方式，所述第一下拉控制模块包括第四晶体管、第五晶体管、第六晶体管和第七晶体管；
所述第四晶体管的栅极接入所述第二目标级传信号，所述第四晶体管的源极与第n级的所述第一节点电连接，所述第四晶体管的漏极与第一低压端电连接；
所述第五晶体管的栅极接入第一复位信号，所述第五晶体管的源极与第n级的所述第一节点电连接，所述第五晶体管的漏极与所述第一低压端电连接；
所述第六晶体管的栅极与第n+1级的所述第二节点电连接，所述第六晶体管的源极与第n级的第一节点电连接，漏极与所述第一低压端电连接；
所述第七晶体管的栅极与第n级的所述第二节点电连接，所述第七晶体管的源极与第n级的所述第一节点电连接，所述第七晶体管的漏极与所述第一低压端电连接。
作为本申请实施例一种可选的实施方式，所述第二下拉控制模块包括第八晶体管、第九晶体管和第十晶体管；
所述第八晶体管的源极和栅极均与电源电压电连接，所述第八晶体管的漏极与所述第九晶体管的栅极、所述第十晶体管T10的源极电连接；
所述第九晶体管的源极与电源电压电连接，所述第九晶体管的漏极与第n级的所述第二节电连接；
所述第十晶体管的栅极与第n级的所述第一节点电连接，所述第十晶体管的漏极与第一低压端电连接。
作为本申请实施例一种可选的实施方式，所述下拉模块包括第十一晶体管、第 十二晶体管、第十三晶体管和第十四晶体管；
所述第十一晶体管的栅极与第n级的所述第二节点电连接，所述第十一晶体管的源极与所述第二晶体管的源极电连接，所述第十一晶体管的漏极与第一低压端电连接；
所述第十二晶体管的栅极与第n级的所述第二节点电连接，所述第十二晶体管的源极与所述第三晶体管的源极电连接，所述第十二晶体管的漏极与第二低压端电连接；
所述第十三晶体管的栅极与第n+1级的所述第二节点电连接，所述第十三晶体管的源极与所述第三晶体管的源极电连接，所述第十三晶体管的漏极与所述第二低压端电连接；
所述第十四晶体管的栅极与第n+1级的所述第二节点电连接，所述第十四晶体管的源极与所述第二晶体管的源极电连接，所述第十四晶体管的漏极与所述第一低压端电连接。
作为本申请实施例一种可选的实施方式，所述第n个GDL电路还包括：
下拉维持模块，所述下拉维持模块与第二节点电连接，用于根据接收的第一目标级传信号，维持所述第二节点的电位。
作为本申请实施例一种可选的实施方式，所述下拉维持模块包括第十五晶体管、第十六晶体管和第十七晶体管；
所述第十五晶体管的栅极与第n级的所述第一节点电连接，所述第十五晶体管的源极与第n级的所述第二节点电连接，所述第十五晶体管的漏极与所述第一低压端电连接；
所述第十六晶体管的栅极接入所述第一目标级传信号，所述第十六晶体管的漏极与所述第一低压端电连接，所述第十六晶体管的源极与第n级的所述第二节点电连接；
所述第十七晶体管的栅极与第n+1级的所述第一节点电连接，所述第十七晶体管的源极与所述第九晶体管的漏极电连接，所述第十七晶体管的漏极与所述第一低压端电连接。
第二方面，本申请实施例提供一种阵列基板，包括：如上述第一方面或第一方面任一项所述的扫描驱动电路和N条扫描线，所述扫描驱动电路中的N个GDL电路与所述N条扫描线一一对应连接，每条扫描线连接多个像素单元。
作为本申请实施例一种可选的实施方式，所述阵列基板还包括：数据驱动电路和时序控制电路；
所述数据驱动电路与每条数据线电连接，所述数据驱动电路用于将待显示的图像数据通过所述数据线以数据电压的形式传输至对应的所述像素单元；
所述时序控制电路分别与所述数据驱动电路和所述扫描驱动电路电连接，所述时序控制电路用于输出时钟信号控制所述数据驱动电路和所述扫描驱动电路的工作时序。
第三方面，本申请实施例提供一种显示面板，所述显示面板的非显示区域包括信号线和如上述第一方面或第一方面任一项所述的扫描驱动电路。
本申请实施例提供的扫描驱动电路、阵列基板和显示面板，包括级联的N个GDL电路，第n个GDL电路包括：上拉控制模块、输出模块、第一下拉控制模块、第二下拉控制模块、下拉模块、第一节点和第二节点，N为正整数，n∈[1，N]；上拉控制模块、第一下拉控制模块和输出模块均与第一节点电连接，上拉控制模块用于根据接收的第一目标级传信号，上拉第一节点的电位至第一电位；第一下拉控制模块用于根据接收的第二目标级传信号，下拉第一节点至第二电位；输出模块用于在第一节点的电位为第一电位的情况下，根据输入的时钟信号输出第n级级传信号和第n级扫描信号；在第一节点的电位为第二电位的情况下，停止输出第n级级传信号和第n级扫描信号；时钟信号的高电位持续时段包括第一时段和第二时段，时钟信号在第一时段保持第一高电位，在第二时段保持第二高电位，第二高电位高于第一高电位；第二下拉控制模块和下拉模块均与第二节点电连接，第二下拉控制模块用于上拉第二节点的电位至第一电位；下拉模块用于在第二节点的电位为第一电位的情况下，下拉输出模块输出端的电位。在上述方案中，时钟信号的高电位持续时段包括第一时段和第二时段，时钟信号在第一时段保持第一高电位，在第二时段保持第二高电位，第二高电位高于第一高电位，这样各级级传信号的电位也会先保持第一高电位一段时间，再上升至第二高电位，即各个GDL电路的第一下拉控制模块接收的第二目标级传信号，也会 在一段时间内保持第一高电位，因此，各个GDL电路的第一节点的电位就可以在这段时间内不被直接下拉到第二电位，而是可以高于第二电位，这样各个GDL电路的输出模块在这段时间内仍然能够输出扫描信号，并且能够根据输入的时钟信号电位的降低，迅速降低扫描信号的电位，从而该方案可以减小GDL电路中各个扫描信号的下降时间，提升GDL电路的稳定性。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其它的附图。
图1为本申请实施例提供的显示面板的结构示意图；
图2为本申请实施例提供的阵列基板的结构示意图；
图3为本申请实施例提供的时序控制电路与扫描驱动电路的连接关系示意图；
图4为本申请实施例提供的GDL电路的结构示意图；
图5为本申请实施例提供的时钟信号的时序图。
其中，图中各附图标记：
阵列基板1，彩膜基板2，液晶层3，扫描线11，数据线12，数据驱动电路13，时序控制电路14，扫描驱动电路15，上拉控制模块1511，输出模块1512，第一下拉控制模块1513，第二下拉控制模块1514，下拉模块1515，下拉维持模块1516。
具体实施方式
下面结合本申请实施例中的附图对本申请实施例进行描述。本申请实施例的实施方式部分使用的术语仅用于对本申请的具体实施例进行解释，而非旨在限定本申请。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例不再赘述。
图1为本申请实施例提供的显示面板的结构示意图，如图1所示，本申请实施例提供的显示面板可以包括：显示区1A和非显示区1B，显示区1A用于显示图像，非显示区1B环绕设置于显示区1A周围，用于设置其他辅助部件或者模组。
具体地，显示面板可以包括：阵列基板1、彩膜基板2和液晶层3。
阵列基板1和彩膜基板2相对设置，液晶层3位于阵列基板1和彩膜基板2之间。
图2为本申请实施例提供的阵列基板的结构示意图，如图2所示，阵列基板1的显示区1A可以包括：N条扫描线11、M条数据线12和多个像素单元P，N和M为正整数；阵列基板1的非显示区1B可以包括：数据驱动电路13、时序控制电路14和扫描驱动电路15。
像素单元P可以阵列排布，每条扫描线11都可以与对应一行的像素单元P电连接。
不同分辨率的显示面板，像素单元P的行列数也有差异，本实施例后续以显示面板中的像素单元P为2160行为例，进行示例性说明。
数据驱动电路13可以与每条数据线12电连接，数据驱动电路13用于将待显示的图像数据通过数据线12以数据电压的形式传输至对应的像素单元P。
时序控制电路14分别与数据驱动电路13和扫描驱动电路15电连接，用于输出时钟信号控制数据驱动电路13和扫描驱动电路15的工作时序。
显示面板的分辨率不同，时序控制电路14输出的时钟信号数量也可以不同，例如，根据显示面板不同的分辨率，时序控制电路14输出的时钟信号可以是4个时钟信号、8个时钟信号、10个时钟信号或12个时钟信号等，本实施例后续以时序控制电路14输出8个时钟信号为例，进行示例性说明。
扫描驱动电路15可以与扫描线11电连接，扫描驱动电路15用于通过扫描线11输出扫描信号控制各像素单元P接收图像数据的时间。
扫描驱动电路15可以通过GDL技术设置在阵列基板1的非显示区1B，其可以包括多个GDL电路，以使显示面板的边框更窄。
图3为本申请实施例提供的时序控制电路与扫描驱动电路的连接关系示意图，如图3所示，本申请实施例提供的扫描驱动电路15可以包括2160个级联的GDL电路。
2160个级联的GDL电路可以依次为GDL1、GDL2、……、GDL2160，每个GDL电路可以接收一个在上升阶段呈阶梯状的时钟信号，并根据该时钟信号输出一个扫描信号，2160个GDL电路对应输出的2160个扫描信号可以依次为G1、G2、……、G2160。 每个扫描信号分别用于驱动阵列基板1的显示区1A中对应像素行的扫描线11。
任意两个相邻的GDL电路接收的时钟信号的相位可以不同，以输出两个间隔一段时间的扫描信号，这样就可以实现像素的逐行扫描。
扫描驱动电路15还可以接收时序控制电路14输出的启动信号STV、复位信号Reset、第一低电平信号VSSQ、第二低电平信号VSSG以及电源电压VDD_O。
具体地，扫描驱动电路15中的GDL1、GDL2、GDL3、GDL4和GDL5电路可以接收时序控制电路14输出的启动信号STV，其他GDL电路可以通过级联电路接收启动信号STV。
复位信号Reset、第一低电平信号VSSQ和第二低电平信号VSSG用于下拉各GDL电路的节点电压。
电源电压VDD_O可以是高电位，用于向各GDL电路提供稳定的高电位电压。
可以理解，显示面板还可以包括其他用于共同完成图像显示的辅助电路，例如图像接收处理电路、电源电路等，本实施例对此不再进行赘述。
下面以两个GDL电路为例示例性说明GDL电路的结构和GDL电路之间的连接关系。
图4为本申请实施例提供的GDL电路的结构示意图，如图4所示，第n个GDL电路可以包括：上拉控制模块1511、输出模块1512、第一下拉控制模块1513、第二下拉控制模块1514、下拉模块1515、第一节点Q(n)和第二节点Qb(n)。
上拉控制模块1511与第一节点Q(n)电连接，并接入第一目标级传信号(此处为第n-5级级传信号C(n-5))，上拉控制模块1511用于根据接收的第n-5级级传信号C(n-5)，上拉第一节点Q(n)的电位至第一电位，其中，第一电位为高电位。
可以理解的是，对于前5级GDL电路，第一目标级传信号可以是启动信号STV。
第一下拉控制模块1513与第一节点Q(n)电连接，并接入第二目标级传信号(此处为第n+6级级传信号C(n+6))、第一复位信号Reset以及第一低电平信号VSSQ。第一下拉控制模块1513用于根据接收的第n+6级级传信号C(n+6)，通过第一低电平信号VSSQ下拉第一节点Q(n)的电位至第二电位。其中，第二电位为低电位。第一下拉控制模块1513还用于根据第一复位信号Reset下拉第一节点Q(n)的电位。
GDL电路还可以包括下拉信号输出单元，对于后6级GDL电路，第二目标级传 信号可以是下拉信号输出单元输出的下拉信号。
第一目标级传信号和第二目标级传信号也可以是其他级传信号，例如，第一目标级传信号可以是第n-4级级传信号，对应的，第二目标级传信号可以是第n+5级级传信号，本实施例对此不做具体限制。
输出模块1512与第一节点Q(n)电连接，并接入时钟信号CLK(n)，用于在第一节点Q(n)的电位为第一电位的情况下，根据时钟信号CLK(n)输出第n级级传信号C(n)和第n级扫描信号G(n)；在第一节点Q(n)的电位为第二电位的情况下，停止输出第n级级传信号C(n)和第n级扫描信号G(n)。时序控制电路14输出的8个时钟信号的时序关系可以如图5所示的，各时钟信号的相位均不同，每个时钟信号的高电位持续时段可以包括第一时段和第二时段，每个时钟信号可以在第一时段保持第一高电位，在第二时段保持第二高电位，第二高电位高于第一高电位，这样各级级传信号的电位也会先保持第一高电位一段时间，再上升至第二高电位，即各个GDL电路的第一下拉控制模块1513接收的第二目标级传信号，也会在一段时间内保持第一高电位，因此，各个GDL电路的第一节点Q(n)的电位就可以在这段时间内不被直接下拉到第二电位，而是可以高于第二电位，这样各个GDL电路的输出模块1512在这段时间内仍然能够输出扫描信号，并且能够根据输入的时钟信号电位的降低，迅速降低扫描信号的电位，从而该方案可以减小GDL电路中各个扫描信号的下降时间，提升GDL电路的稳定性。
时钟信号的高电位持续时段的占空比可以是1/2，也可以适当调整的更小，这样也可以减小GDL电路输出的扫描信号的下降时间。
在时钟信号的高电位持续时段固定的情况下，时钟信号的第一时段的时间增加会缩短时钟信号保持第二高电位的第二时段的时间，而时钟信号保持第二高电位的时间过短可能导致显示面板充电不足，显示画面异常等现象。因此，时钟信号的第一时段相对于高电位持续时段的占比可以小于或等于1/4，以保证时钟信号保持第二高电位的时间，例如，时钟信号的第一时段相对于高电位持续时段的占比可以为1/8，这样即能根据低电位的时钟信号迅速下拉对应扫描信号的电位，也能保证时钟信号保持第二高电位的时间，从而让显示面板有充足的充电时间。
第二下拉控制模块1514与第二节点Qb(n)电连接，接入电源电压VDD_O，第二下拉控制模块1514用于上拉第二节点Qb(n)的电位至第一电位。
下拉模块1515与第二节点Qb(n)电连接，并接入第一低电平信号VSSQ和第二低电平信号VSSG，用于在第二节点Qb(n)的电位为第一电位的情况下，根据第一低电平信号VSSQ和第二低电平信号VSSG下拉输出模块1512输出端的电位。
GDL电路还可以包括下拉维持模块1516，下拉维持模块1516与第一节点Q(n)电连接，并接入第n-5级级传信号C(n-5)和第一低电平信号VSSQ，下拉维持模块1516用于根据第n-5级级传信号C(n-5)维持第二节点Qb(n)的电位。
与第n个GDL电路类似，第n+1个GDL电路可以包括：上拉控制模块1511、输出模块1512、第一下拉控制模块1513、第二下拉控制模块1514、下拉模块1515、下拉信号输出单元、下拉维持模块1516、第一节点Q(n+1)和第二节点Qb(n+1)。
其中，上拉控制模块1511用于接收第n-4级级传信号C(n-4)，根据第n-4级级传信号C(n-4)上拉第一节点Q(n+1)的电位至第一电位。
第一下拉控制模块1513用于接收第n+7级级传信号C(n+7)，根据第n+7级级传信号C(n+7)下拉第一节点Q(n+1)的电位至第二电位。
输出模块1512用于在第一节点Q(n+1)的电位为第一电位的情况下，根据时钟信号CLK(n+1)输出第n+1级级传信号C(n+1)和第n+1级扫描信号G(n+1)；在第一节点Q(n+1)的电位为第二电位的情况下，停止输出第n+1级级传信号C(n+1)和第n+1级扫描信号G(n+1)。
具体地，第n个GDL电路的上拉控制模块1511可以包括：第一晶体管T1，第一晶体管T1的栅极和漏极均接入第n-5级级传信号C(n-5)，第一晶体管T1的源极与第一节点Q(n)电连接。
输出模块1512可以包括：第二晶体管T2和第三晶体管T3，第二晶体管T2和第三晶体管T3的栅极均与第一节点Q(n)电连接，第二晶体管T2和第三晶体管T3的漏极接入同一时钟信号CLK(N)，第二晶体管T2的源极输出第n级级传信号C(n)，第三晶体管T3的源极输出第n级扫描信号G(n)。
第一下拉控制模块1513可以包括第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7。其中，第四晶体管T4的栅极接入第n+6级级传信号C(n+6)，源极与第一节点Q(n)电连接，漏极与第一低压端电连接，以接收第一低电平信号VSSQ。第五晶体管T5的栅极接入第一复位信号Reset，源极与第一节点Q(n)电连接，漏极与第一低压端电连接，以接收第一低电平信号VSSQ。第六晶体管T6的栅极与第n+1个 GDL电路的第二节点Qb(n+1)电连接，源极与第一节点Q(n)电连接，漏极与第一低压端电连接，以接收第一低电平信号VSSQ。第七晶体管T7的栅极与第二节点Qb(n)电连接，源极与第一节点Q(n)电连接，漏极与第一低压端电连接，以接收第一低电平信号VSSQ。
由于各级级传信号的电位会先保持第一高电位一段时间，再上升至第二高电位，即第四晶体管T4接收的第n+6级级传信号C(n+6)，也会在保持第一高电位一段时间，这段时间内第四晶体管T4没有完全打开，第一低压端输出的第一低电平信号VSSQ可以将第一节点Q(n)的电位下拉到高于第二电位的第三电位，因此，第二晶体管T2和第三晶体管T3在这段时间内仍然导通，第三晶体管T3的源极仍然能够输出第n级扫描信号G(n)，并且在时钟信号转换为低电位时，能够迅速降低第n级扫描信号G(n)的电位，从而减小第n级扫描信号G(n)的下降时间。
第二下拉控制模块1514可以包括第八晶体管T8、第九晶体管T9和第十晶体管T10。第八晶体管T8的源极和栅极均与电源电压VDD_O电连接，漏极与第九晶体管T9的栅极、第十晶体管T10的源极电连接。第九晶体管T9的源极与电源电压VDD_O电连接，漏极与第二节点Qb(n)电连接。第十晶体管T10的栅极与第一节点Q(n)电连接，漏极与第一低压端电连接，以接收第一低电平信号VSSQ。
下拉模块1515可以包括第十一晶体管T11、第十二晶体管T12、第十三晶体管T13和第十四晶体管T14。其中，第十一晶体管T11的栅极与第二节点Qb(n)电连接，源极与第二晶体管T2的源极电连接，漏极与第一低压端电连接，以接收第一低电平信号VSSQ。第十二晶体管T12的栅极与第二节点Qb(n)电连接，源极与第三晶体管T3的源极电连接，漏极与第二低压端电连接，以接收第二低电平信号VSSG。第十三晶体管T13的栅极与第n+1个GDL电路的第二节点Qb(n+1)电连接，源极与第三晶体管T3的源极电连接，漏极与第二低压端电连接，以接收第二低电平信号VSSG。第十四晶体管T14的栅极与第n+1个GDL电路的第二节点Qb(n+1)电连接，源极与第二晶体管T2的源极电连接，漏极与第一低压端电连接，以接收第一低电平信号VSSQ。
下拉维持模块1516可以包括第十五晶体管T15、第十六晶体管T16和第十七晶体管T17。其中，第十五晶体管T15的栅极与第一节点Q(n)电连接，源极与第二节点Qb(n)电连接，漏极与第一低压端电连接，以接收第一低电平信号VSSQ。第十六晶体管T16的栅极接入第n-5级级传信号C(n-5)，漏极与第一低压端电连接，以接收第一低 电平信号VSSQ，源极与第二节点Qb(n)电连接。第十七晶体管T17的栅极与第n+1个GDL电路的第一节点Q(n+1)电连接，源极与第九晶体管T9的漏极电连接，漏极与第一低压端电连接，以接收第一低电平信号VSSQ。
第n+1个GDL电路中各模块具体包括的元件与第n个GDL电路类似，此处不再赘述。
第n+1个GDL电路中各元件的连接关系与第n个GDL电路也类似，不同之处主要在于如下几点，其中，如非特别说明，下面所述的元件均表示第n+1个GDL电路中的元件。
上拉控制模块1511的第一晶体管T1的栅极和漏极均接入第n-4级级传信号C(n-4)，源极与第一节点Q(n+1)电连接。
输出模块1512的第二晶体管T2和第三晶体管T3的栅极均与第一节点Q(n+1)电连接，漏极接入时钟信号CLK(n+1)，第二晶体管T2的源极输出第n+1级级传信号C(n+1)，第三晶体管T3的源极输出第n+1级扫描信号G(n+1)。
第一下拉控制模块1513的第四晶体管T4的栅极接入第n+7级级传信号C(n+7)，源极与第一节点Q(n+1)电连接，漏极与第一低压端电连接。第六晶体管T6的栅极与第n个GDL电路的第二节点Qb(n)电连接，源极与第一节点Q(n+1)电连接，漏极与第一低压端电连接。
下拉模块1515的第十三晶体管T13的栅极与第n个GDL电路的第二节点Qb(n)电连接，源极与第三晶体管T3的源极电连接，漏极与第二低压端电连接，第十四晶体管T14的栅极与第n个GDL电路的第二节点Qb(n)电连接，源极与第二晶体管T2的源极电连接，漏极与第一低压端电连接。
下拉维持模块1516的第十七晶体管T17的栅极与第n个GDL电路的第一节点Q(n)电连接，源极与第九晶体管T9的漏极电连接，漏极与第一低压端电连接。
上述的第n个GDL电路和第n+1个GDL电路中，各晶体管可以均为N型场效应管，以减小各晶体管在电路中的阻抗，图4中即是以此为例进行示例性说明。在一些实施例中，各晶体管也可以均为P型场效应管，以降低成本，本实施例对此不做特别限定。
本申请实施例提供的扫描驱动电路、阵列基板和显示面板，包括级联的N个GDL电路，第n个GDL电路包括：上拉控制模块、输出模块、第一下拉控制模块、第二 下拉控制模块、下拉模块、第一节点和第二节点，N为正整数，n∈[1，N]；上拉控制模块、第一下拉控制模块和输出模块均与第一节点电连接，上拉控制模块用于根据接收的第一目标级传信号，上拉第一节点的电位至第一电位；第一下拉控制模块用于根据接收的第二目标级传信号，下拉第一节点至第二电位；输出模块用于在第一节点的电位为第一电位的情况下，根据输入的时钟信号输出第n级级传信号和第n级扫描信号；在第一节点的电位为第二电位的情况下，停止输出第n级级传信号和第n级扫描信号；时钟信号的高电位持续时段包括第一时段和第二时段，时钟信号在第一时段保持第一高电位，在第二时段保持第二高电位，第二高电位高于第一高电位；第二下拉控制模块和下拉模块均与第二节点电连接，第二下拉控制模块用于上拉第二节点的电位至第一电位；下拉模块用于在第二节点的电位为第一电位的情况下，下拉输出模块输出端的电位。在上述方案中，时钟信号的高电位持续时段包括第一时段和第二时段，时钟信号在第一时段保持第一高电位，在第二时段保持第二高电位，第二高电位高于第一高电位，这样各级级传信号的电位也会先保持第一高电位一段时间，再上升至第二高电位，即各个GDL电路的第一下拉控制模块接收的第二目标级传信号，也会在一段时间内保持第一高电位，因此，各个GDL电路的第一节点的电位就可以在这段时间内不被直接下拉到第二电位，而是可以高于第二电位，这样各个GDL电路的输出模块在这段时间内仍然能够输出扫描信号，并且能够根据输入的时钟信号电位的降低，迅速降低扫描信号的电位，从而该方案可以减小GDL电路中各个扫描信号的下降时间，提升GDL电路的稳定性。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述或记载的部分，可以参见其它实施例的相关描述。
应当理解，当在本申请说明书和所附权利要求书中使用时，术语“包括”指示所描述特征、整体、步骤、操作、元素和/或组件的存在，但并不排除一个或多个其它特征、整体、步骤、操作、元素、组件和/或其集合的存在或添加。
在本申请中出现的对步骤进行的命名或者编号，并不意味着必须按照命名或者编号所指示的时间/逻辑先后顺序执行方法流程中的步骤，已经命名或者编号的流程步骤可以根据要实现的技术目的变更执行次序，只要能达到相同或者相类似的技术效果即可。
在本申请的描述中，除非另有说明，“/”表示前后关联的对象是一种“或” 的关系，例如，A/B可以表示A或B；本申请中的“和/或”仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况，其中A，B可以是单数或者复数。
并且，在本申请的描述中，除非另有说明，“多个”是指两个或多于两个。“以下至少一项”或其类似表达，是指的这些项中的任意组合，包括单项或复数项的任意组合。例如，a，b，或c中的至少一项，可以表示：a，b，c，a-b，a-c，b-c，或a-b-c，其中a，b，c可以是单个，也可以是多个。
如在本申请说明书和所附权利要求书中所使用的那样，术语“如果”可以依据上下文被解释为“当...时”或“一旦”或“响应于确定”或“响应于检测到”。类似地，短语“如果确定”或“如果检测到[所描述条件或事件]”可以依据上下文被解释为意指“一旦确定”或“响应于确定”或“一旦检测到[所描述条件或事件]”或“响应于检测到[所描述条件或事件]”。
另外，在本申请说明书和所附权利要求书的描述中，术语“第一”、“第二”、“第三”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。
在本申请说明书中描述的参在本申请说明书中描述的参考“一个实施例”或“一些实施例”等意味着在本申请的一个或多个实施例中包括结合该实施例描述的特定特征、结构或特点。由此，在本说明书中的不同之处出现的语句“在一个实施例中”、“在一些实施例中”、“在其他一些实施例中”、“在另外一些实施例中”等不是必然都参考相同的实施例，而是意味着“一个或多个但不是所有的实施例”，除非是以其他方式另外特别强调。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (15)

  1. 一种扫描驱动电路，其中，包括：级联的N个GDL电路，第n个GDL电路包括：上拉控制模块、输出模块、第一下拉控制模块、第二下拉控制模块、下拉模块、第一节点和第二节点，N为正整数，n∈[1，N]；
    所述上拉控制模块、所述第一下拉控制模块和所述输出模块均与所述第一节点电连接，所述上拉控制模块用于根据接收的第一目标级传信号，上拉所述第一节点的电位至第一电位；
    所述第一下拉控制模块用于根据接收的第二目标级传信号，下拉所述第一节点至第二电位；
    所述输出模块用于在所述第一节点的电位为第一电位的情况下，根据输入的时钟信号输出第n级级传信号和第n级扫描信号；在所述第一节点的电位为第二电位的情况下，停止输出所述第n级级传信号和所述第n级扫描信号；所述时钟信号的高电位持续时段包括第一时段和第二时段，所述时钟信号在所述第一时段保持第一高电位，在所述第二时段保持第二高电位，所述第二高电位高于所述第一高电位；
    所述第二下拉控制模块和所述下拉模块均与所述第二节点电连接，所述第二下拉控制模块用于上拉所述第二节点的电位至第一电位；
    所述下拉模块用于在所述第二节点的电位为第一电位的情况下，下拉所述输出模块输出端的电位。
  2. 根据权利要求1所述的电路，其中，所述时钟信号的第一时段相对于所述高电位持续时段的占比小于或等于1/4。
  3. 根据权利要求2所述的电路，其中，所述时钟信号的第一时段相对于所述高电位持续时段的占比等于1/8。
  4. 根据权利要求1所述的电路，其中，所述时钟信号的高电位持续时段的占空比小于1/2。
  5. 根据权利要求1所述的电路，其中，所述第一目标级传信号为第n-5级级传信号，所述第二目标级传信号为第n+6级级传信号，5＜n≤N-6。
  6. 根据权利要求1所述的电路，其中，所述上拉控制模块包括：第一晶体管，所述第一晶体管的控制极和第一极均接入所述第一目标级传信号，所述第一晶体管的第 二极与所述第一节点电连接。
  7. 根据权利要求1所述的电路，其中，所述输出模块包括：第二晶体管和第三晶体管，所述第二晶体管和所述第三晶体管的控制极均与所述第一节点电连接，所述第二晶体管和所述第三晶体管的第一极接入同一时钟信号，所述第二晶体管的第二极输出所述第n级级传信号，所述第三晶体管的第二极输出所述第n级扫描信号。
  8. 根据权利要求7所述的电路，其中，所述第一下拉控制模块包括第四晶体管、第五晶体管、第六晶体管和第七晶体管；
    所述第四晶体管的栅极接入所述第二目标级传信号，所述第四晶体管的源极与第n级的所述第一节点电连接，所述第四晶体管的漏极与第一低压端电连接；
    所述第五晶体管的栅极接入第一复位信号，所述第五晶体管的源极与第n级的所述第一节点电连接，所述第五晶体管的漏极与所述第一低压端电连接；
    所述第六晶体管的栅极与第n+1级的所述第二节点电连接，所述第六晶体管的源极与第n级的第一节点电连接，漏极与所述第一低压端电连接；
    所述第七晶体管的栅极与第n级的所述第二节点电连接，所述第七晶体管的源极与第n级的所述第一节点电连接，所述第七晶体管的漏极与所述第一低压端电连接。
  9. 根据权利要求8所述的电路，其中，所述第二下拉控制模块包括第八晶体管、第九晶体管和第十晶体管；
    所述第八晶体管的源极和栅极均与电源电压电连接，所述第八晶体管的漏极与所述第九晶体管的栅极、所述第十晶体管T10的源极电连接；
    所述第九晶体管的源极与电源电压电连接，所述第九晶体管的漏极与第n级的所述第二节电连接；
    所述第十晶体管的栅极与第n级的所述第一节点电连接，所述第十晶体管的漏极与第一低压端电连接。
  10. 根据权利要求9所述的电路，其中，所述下拉模块包括第十一晶体管、第十二晶体管、第十三晶体管和第十四晶体管；
    所述第十一晶体管的栅极与第n级的所述第二节点电连接，所述第十一晶体管的源极与所述第二晶体管的源极电连接，所述第十一晶体管的漏极与第一低压端电连接；
    所述第十二晶体管的栅极与第n级的所述第二节点电连接，所述第十二晶体管的 源极与所述第三晶体管的源极电连接，所述第十二晶体管的漏极与第二低压端电连接；
    所述第十三晶体管的栅极与第n+1级的所述第二节点电连接，所述第十三晶体管的源极与所述第三晶体管的源极电连接，所述第十三晶体管的漏极与所述第二低压端电连接；
    所述第十四晶体管的栅极与第n+1级的所述第二节点电连接，所述第十四晶体管的源极与所述第二晶体管的源极电连接，所述第十四晶体管的漏极与所述第一低压端电连接。
  11. 根据权利要求10所述的电路，其中，所述第n个GDL电路还包括：
    下拉维持模块，所述下拉维持模块与第二节点电连接，用于根据接收的第一目标级传信号，维持所述第二节点的电位。
  12. 根据权利要求11所述的电路，其中，所述下拉维持模块包括第十五晶体管、第十六晶体管和第十七晶体管；
    所述第十五晶体管的栅极与第n级的所述第一节点电连接，所述第十五晶体管的源极与第n级的所述第二节点电连接，所述第十五晶体管的漏极与所述第一低压端电连接；
    所述第十六晶体管的栅极接入所述第一目标级传信号，所述第十六晶体管的漏极与所述第一低压端电连接，所述第十六晶体管的源极与第n级的所述第二节点电连接；
    所述第十七晶体管的栅极与第n+1级的所述第一节点电连接，所述第十七晶体管的源极与所述第九晶体管的漏极电连接，所述第十七晶体管的漏极与所述第一低压端电连接。
  13. 一种阵列基板，其中，包括：如权利要求1所述的扫描驱动电路和N条扫描线，所述扫描驱动电路中的N个GDL电路与所述N条扫描线一一对应连接，每条扫描线连接多个像素单元。
  14. 根据权利要求13所述的阵列基板，其中，所述阵列基板还包括：数据驱动电路和时序控制电路；
    所述数据驱动电路与每条数据线电连接，所述数据驱动电路用于将待显示的图像数据通过所述数据线以数据电压的形式传输至对应的所述像素单元；
    所述时序控制电路分别与所述数据驱动电路和所述扫描驱动电路电连接，所述时序控制电路用于输出时钟信号控制所述数据驱动电路和所述扫描驱动电路的工作时序。
  15. 一种显示面板，其中，所述显示面板的非显示区域包括信号线和如权利要求1所述的扫描驱动电路。
PCT/CN2022/137322 2022-06-28 2022-12-07 扫描驱动电路、阵列基板和显示面板 Ceased WO2024001053A1 (zh)

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