WO2024000726A1 - 半导体结构的制备方法 - Google Patents

半导体结构的制备方法 Download PDF

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Publication number
WO2024000726A1
WO2024000726A1 PCT/CN2022/109571 CN2022109571W WO2024000726A1 WO 2024000726 A1 WO2024000726 A1 WO 2024000726A1 CN 2022109571 W CN2022109571 W CN 2022109571W WO 2024000726 A1 WO2024000726 A1 WO 2024000726A1
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conductive material
material layer
semiconductor structure
structure according
annealed
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PCT/CN2022/109571
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English (en)
French (fr)
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刘佑铭
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长鑫存储技术有限公司
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Priority to EP22790199.8A priority Critical patent/EP4322203A1/en
Priority to US18/154,756 priority patent/US20240008248A1/en
Publication of WO2024000726A1 publication Critical patent/WO2024000726A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to methods of manufacturing semiconductor structures.
  • a method of manufacturing a semiconductor structure is provided.
  • embodiments of the present disclosure provide a method for preparing a semiconductor structure, including:
  • an annealing treatment is performed on the deposited conductive material layer.
  • the portions of the conductive material layer located at the top corners of the side walls of the etching holes are all rounded.
  • the structure to be etched includes a substrate, the etching hole includes a bit line contact hole, and the conductive material layer fills the etching hole without holes to form a bit line contact structure.
  • the at least part of the conductive material layer deposition process further includes performing an annealing treatment on the deposited conductive material layer, including:
  • the deposited conductive material layer is annealed
  • the deposited conductive material layer is annealed.
  • the number of annealing processes performed on the deposited conductive material layer is greater than or equal to half of the number of times the conductive material layer is deposited.
  • the structure to be etched includes: a substrate and a dielectric layer located on the substrate; the etching hole penetrates the dielectric layer along the thickness direction; and the conductive material layer fills all the holes without holes. After etching the holes, a capacitor storage node contact structure is formed.
  • the layer of conductive material includes a layer of doped polysilicon.
  • the aspect ratio of the etched hole is greater than or equal to 4:1.
  • the conductive material layer is annealed in an atmosphere including hydrogen.
  • the conductive material layer is annealed in a pure hydrogen atmosphere.
  • the conductive material layer is annealed in a mixed atmosphere of hydrogen and nitrogen.
  • the temperature of the annealing treatment includes 700°C to 1200°C.
  • the time of the annealing treatment includes 30s to 2h.
  • the annealing pressure during the annealing process includes 10 Torr to 760 Torr.
  • the gas flow rate of hydrogen is 1 slm to 100 slm.
  • Embodiments of the present disclosure may/at least have the following advantages:
  • conductive material layer deposition processes are performed instead of filling the etching holes in one deposition process, and at least After the partial conductive material layer deposition process, the deposited conductive material layer is annealed, so that the conductive material layer can fill the etching holes without holes.
  • Figure 1 is a flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure
  • Figure 2 is a flow chart of a method for manufacturing a semiconductor structure provided in another embodiment of the present disclosure.
  • 3 to 9 are schematic cross-sectional structural diagrams of structures obtained by each step of a method for preparing a semiconductor structure provided in another embodiment of the present disclosure.
  • Figure 10 is a flow chart of a method for manufacturing a semiconductor structure provided in yet another embodiment of the present disclosure.
  • 11 to 17 are schematic cross-sectional structural diagrams of the structure obtained by each step of the method for preparing a semiconductor structure provided in yet another embodiment of the present disclosure.
  • Figure 18 is a flow chart of a method for manufacturing a memory device structure provided in yet another embodiment of the present disclosure.
  • 19 to 30 are schematic structural diagrams of the structure obtained by each step of the method for preparing a memory device structure provided in yet another embodiment of the present disclosure.
  • first, second, etc. used in the embodiments of the present disclosure may be used to describe various elements herein, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element.
  • the first power input terminal may be referred to as a second power input terminal, and similarly, the second power input terminal may be referred to as a first power input terminal.
  • the first power input terminal and the second power input terminal are both power input terminals, but they are not the same power input terminal.
  • connection in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have the transmission of electrical signals or data between each other.
  • DRAM Dynamic Random Access Memory
  • the depth of the contact holes of the BL (Bitline, bit line) in the ARRAY area and the capacitive storage node The aspect ratio is getting higher and higher, and when a conductive material layer is deposited in a contact hole using a single deposition process to form a bit line contact structure (BLC, Bit Line Coupling) or a capacitive storage node contact structure, it is inevitable that the bit line contact structure and Void is generated in the capacitive storage node contact structure, thereby affecting the contact resistance of the bit line contact structure and the capacitive storage node contact structure, and even affecting the yield of the semiconductor device structure.
  • BLC Bit Line Coupling
  • an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including:
  • S12 Perform multiple conductive material layer deposition processes until no holes in the conductive material layer fill the etching holes; wherein at least part of the conductive material layer deposition process further includes annealing the deposited conductive material layer.
  • the preparation method of the above-mentioned semiconductor structure when depositing a conductive material layer to fill the etching holes, performs multiple conductive material layer deposition processes instead of filling the etching holes in one deposition process, and depositing at least part of the conductive material layer After the process, the deposited conductive material layer is annealed so that the conductive material layer can fill the etching holes without holes.
  • the structure to be etched includes a substrate.
  • a method for preparing a semiconductor structure may include the following steps:
  • S20 Provide a structure to be etched, which includes a substrate;
  • S21 Form etching holes in the structure to be etched, and the etching holes include bit line contact holes;
  • S22 Perform multiple conductive material layer deposition processes until no holes in the conductive material layer fill the etching holes; wherein at least part of the conductive material layer deposition process further includes annealing the deposited conductive material layer.
  • step S20 please refer to step S20 in Figure 2 and Figure 3 to provide a structure to be etched, and the structure to be etched includes the substrate 101.
  • substrate 101 may include, but is not limited to, a silicon substrate.
  • step S21 please refer to step S21 in FIG. 2 and FIG. 3, an etching hole is formed in the structure to be etched, and the etching hole includes the bit line contact hole 103.
  • a photolithography process may be used to form the bit line contact hole 103 in the substrate 101 .
  • the longitudinal cross-sectional shape of the bit line contact hole 103 can be set according to actual needs.
  • the longitudinal cross-sectional shape of the bit line contact hole 103 can be an inverted trapezoid, a rectangle, a U-shape, etc.; in this embodiment, the longitudinal cross-section of the bit line contact hole 103 is The shape is an inverted trapezoid, as shown in Figure 3.
  • the depth of the bit line contact hole 103 is smaller than the depth of the substrate 101 .
  • the aspect ratio of the bit line contact hole 103 can be set according to actual needs. In this embodiment, the aspect ratio of the bit line contact hole 103 can be greater than or equal to 4:1. For example, the aspect ratio of the bit line contact hole 103 The aspect ratio can be 4:1, 5:1, 10:1, 15:1 or 20:1 etc.
  • step S22 please refer to step S22 in Figure 2 and Figures 4 to 8 to perform multiple deposition processes of the conductive material layer 11 until no holes are filled in the etching holes in the conductive material layer 11; wherein, at least part of the conductive material layer 11 After the deposition process, the deposited conductive material layer 11 is also subjected to an annealing process.
  • the deposited conductive material layer 11 may be annealed after a portion of the deposition process.
  • the deposited conductive material layer 11 may be annealed. In another optional example, after the deposition process of the even-numbered conductive layer 11 , the deposited conductive material layer 11 may be annealed. Of course, in other examples, after the deposition process of any part of the conductive material layer 11, the deposited conductive material layer 11 can also be annealed according to actual needs.
  • the number of times of annealing treatment on the deposited conductive material layer 11 is greater than or equal to half of the number of times of deposition of the conductive material layer 11 .
  • the number of annealing treatments on the deposited conductive material layer 11 should be greater than 5 times. That is, after more than 5 times of deposition of the conductive material layer 11, a corresponding annealing heat treatment needs to be performed.
  • step S22 may include the following steps:
  • S224 Perform annealing treatment on the second conductive material layer 113. After the annealing treatment, the second conductive layer 113 is obtained, as shown in Figure 7;
  • S225 Use a deposition process to fill the Nth conductive material layer 115 in the bit line contact hole 103, and the Nth conductive material layer 115 fills the bit line contact hole 103, as shown in FIG. 8; where N is an integer greater than or equal to 3. .
  • N is an integer greater than 3
  • steps of forming a conductive material layer corresponding to the substrate and annealing the deposited conductive material layer are also included between step 224 and step S225.
  • the first conductive material layer 111 may be formed using a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process.
  • the formed first conductive material layer 111 may include but is not limited to a doped polysilicon layer.
  • the first conductive material layer 111 may be annealed in an atmosphere including hydrogen.
  • the first conductive material layer 111 may be annealed in a pure hydrogen atmosphere.
  • hydrogen gas can be introduced into the environment where the first conductive material layer 111 is located to form a pure hydrogen atmosphere.
  • the gas flow rate of hydrogen can be 1slm (Standard Liter per Minute, standard liter per minute) to 100slm.
  • the gas flow rate of hydrogen can be 1slm, 10slm, 50slm or 100slm, etc.
  • the first conductive material layer 111 may be annealed in a mixed atmosphere of hydrogen and nitrogen.
  • a mixed gas of hydrogen and nitrogen can be introduced into the environment where the first conductive material layer 111 is located to form a mixed atmosphere of hydrogen and nitrogen.
  • the gas flow rate of hydrogen can be 1slm (Standard Liter per Minute, standard liter per minute) to 100slm.
  • the gas flow rate of hydrogen can be 1slm, 10slm, 50slm or 100slm, etc.
  • the temperature for annealing the first conductive material layer 111 may be 700°C (degrees Celsius) to 1200°C. Specifically, the temperature for annealing the first conductive material layer 111 may be 700°C, 800°C, 900°C, 1000°C, 1100°C or 1200°C, etc.
  • the time for annealing the first conductive material layer 111 may be 30s (seconds) to 2h (hours). Specifically, the time for annealing the first conductive material layer 111 may be 30s, 5min (minutes), 10min, 30min, 1h or 2h, etc.
  • the annealing pressure of the first conductive material layer 111 may be 10 Torr to 760 Torr. Specifically, the annealing pressure of the first conductive material layer 111 may be 10Torr, 50Torr, 100Torr, 200Torr, 300Torr, 400Torr, 500Torr, 600Torr, 700Torr or 760Torr, etc.
  • step S222 after the first conductive material layer 111 is annealed, the portions of the obtained first conductive layer 112 located at the top corners of the side walls of the bit line contact holes 103 are all rounded, as shown in FIG. 5 .
  • the specific selection of the above gas flow, pressure and annealing time can control the filleting rate at the corners. Under the same gas flow and annealing time, the greater the pressure, the higher the temperature, the greater the filleting rate. When the pressure and time are constant, the greater the flow rate, the higher the temperature, and the greater the filleting rate. Depending on the aspect ratio of the bit line contact hole 103 and the specific thickness of the deposited conductive material layer, the requirements for flow rate, pressure, processing time, and processing temperature are also different.
  • the second conductive material layer 113 may be formed using a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or the like.
  • the formed second conductive material layer 113 may include but is not limited to a doped polysilicon layer.
  • step S224 the second conductive material layer 113 may be annealed in an atmosphere including hydrogen.
  • the second conductive material layer 113 may be annealed in a pure hydrogen atmosphere.
  • hydrogen gas can be introduced into the environment where the second conductive material layer 113 is located to form a pure hydrogen atmosphere.
  • the gas flow rate of hydrogen can be 1slm (Standard Liter per Minute, standard liter per minute) to 100slm.
  • the gas flow rate of hydrogen can be 1slm, 10slm, 50slm or 100slm, etc.
  • the second conductive material layer 113 may be annealed in a mixed atmosphere of hydrogen and nitrogen.
  • a mixed gas of hydrogen and nitrogen can be introduced into the environment where the second conductive material layer 113 is located to form a mixed atmosphere of hydrogen and nitrogen.
  • the gas flow rate of hydrogen can be 1slm (Standard Liter per Minute, standard liter per minute) to 100slm.
  • the gas flow rate of hydrogen can be 1slm, 10slm, 50slm or 100slm, etc.
  • the temperature for annealing the second conductive material layer 113 may be 700°C (degrees Celsius) to 1200°C. Specifically, the temperature for annealing the second conductive material layer 113 may be 700°C, 800°C, 900°C, 1000°C, 1100°C or 1200°C, etc.
  • the time for annealing the second conductive material layer 113 may be 30s (seconds) to 2h (hours). Specifically, the time for annealing the second conductive material layer 113 may be 30s, 5min (minutes), 10min, 30min, 1h or 2h, etc.
  • the annealing pressure for the second conductive material layer 113 may be 10 Torr to 760 Torr. Specifically, the annealing pressure for the second conductive material layer 113 may be 10Torr, 50Torr, 100Torr, 200Torr, 300Torr, 400Torr, 500Torr, 600Torr, 700Torr or 760Torr, etc.
  • step S224 after the second conductive material layer 113 is annealed, the portions of the obtained second conductive layer 114 located at the top corners of the side walls of the bit line contact holes 103 are all rounded, as shown in FIG. 7 .
  • the Nth conductive material layer 115 may be formed using a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or the like.
  • the Nth conductive material layer 115 formed may include but is not limited to a doped polysilicon layer.
  • step S225 uses a deposition process to fill the Nth conductive material layer 115 in the bit line contact hole 103 , it also includes:
  • step S226 Planarize the structure obtained in step S225 to remove the first conductive layer 112, the second conductive layer 114 and the Nth conductive material layer 115 located on the upper surface of the substrate 101, leaving the Nth conductive material layer 115 in the bit line contact hole 103.
  • a conductive layer 112 , a second conductive layer 114 and an Nth conductive material layer 115 together form a bit line structure 116 .
  • step S226 a CMP (Chemical Mechanical Polishing) process can be used to planarize the structure obtained in step S225.
  • CMP Chemical Mechanical Polishing
  • the conductive material layer 11 when the conductive material layer 11 is deposited to fill the bit line contact hole 103, multiple deposition processes of the conductive material layer 11 are performed instead of filling the bit line contact hole 103 in one deposition process. After at least part of the conductive material layer 11 is deposited, the deposited conductive material layer 11 is annealed, so that the conductive material layer 11 can fill the bit line contact hole 103 without holes, that is, a hole-free bit line contact structure can be obtained. 116, thereby reducing the contact resistance of the bit line contact structure 116 and improving the yield of the semiconductor device structure.
  • a method for preparing a semiconductor structure may include the following steps:
  • S30 Provide a structure to be etched, which includes a substrate and a dielectric layer located on the substrate;
  • S31 Form an etching hole in the structure to be etched, the etching hole penetrates the dielectric layer along the thickness direction, and the etching hole includes the capacitor storage node contact hole;
  • S32 Perform multiple conductive material layer deposition processes until no holes in the conductive material layer fill the etching holes; wherein at least part of the conductive material layer deposition process further includes annealing the deposited conductive material layer.
  • step S30 please refer to step S30 in FIG. 10 and FIG. 11 to provide a structure 10 to be etched.
  • the structure 10 to be etched includes a substrate 101 and a dielectric layer 102 located on the substrate 101.
  • the substrate 101 may include, but is not limited to, a silicon substrate; the dielectric layer 102 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like.
  • step S31 please refer to step S31 in Figure 10 and Figure 11, an etching hole is formed in the structure 10 to be etched, the etching hole penetrates the dielectric layer 102 along the thickness direction, and the etching hole includes the capacitor storage node contact hole 104. .
  • a photolithography process may be used to form the capacitor storage node contact hole 104 in the dielectric layer 102 .
  • the longitudinal cross-sectional shape of the capacitor storage node contact hole 104 can be set according to actual needs.
  • the longitudinal cross-sectional shape of the capacitor storage node contact hole 104 can be an inverted trapezoid, a rectangle, a U-shape, etc.; in this embodiment, the capacitor storage node contact hole 104
  • the longitudinal cross-sectional shape is an inverted trapezoid, as shown in Figure 11.
  • the depth of the capacitive storage node contact hole 104 may be greater than the thickness of the dielectric layer 102 and less than the sum of the thicknesses of the dielectric layer 102 and the substrate 101 , that is, the capacitive storage node contact hole 104 penetrates deep into the interior of the substrate 101 .
  • the aspect ratio of the capacitor storage node contact hole 104 can be set according to actual needs. In this embodiment, the aspect ratio of the capacitor storage node contact hole 104 can be greater than or equal to 4:1. For example, the capacitor storage node contact hole 104 can have an aspect ratio greater than or equal to 4:1. The aspect ratio of the contact hole 104 may be 4:1, 5:1, 10:1, 15:1, or 20:1, etc.
  • step S32 please refer to step S32 in Figure 10 and Figures 12 to 17 to perform multiple deposition processes of the conductive material layer 11 until no holes in the conductive material layer 11 fill the etching holes; wherein, at least part of the conductive material layer 11 After the deposition process, the deposited conductive material layer 11 is also subjected to an annealing process.
  • the deposited conductive material layer 11 may be annealed after a portion of the deposition process.
  • the deposited conductive material layer 11 can be annealed. In another optional example, after the deposition process of the even-numbered conductive layer 11 , the deposited conductive material layer 11 may be annealed. Of course, in other examples, after the deposition process of any part of the conductive material layer 11, the deposited conductive material layer 11 can also be annealed according to actual needs.
  • the number of times of annealing treatment on the deposited conductive material layer 11 is greater than or equal to half of the number of times of deposition of the conductive material layer 11 .
  • the number of annealing treatments on the deposited conductive material layer 11 should be greater than 5 times. That is, after more than 5 times of deposition of the conductive material layer 11, a corresponding annealing heat treatment needs to be performed.
  • step S32 may include the following steps:
  • S322 Perform annealing treatment on the first conductive material layer 111, and obtain the first conductive layer 112 after the annealing treatment, as shown in Figure 13;
  • S324 Perform annealing treatment on the second conductive material layer 113. After the annealing treatment, the second conductive layer 113 is obtained, as shown in Figure 15;
  • S325 Use a deposition process to fill the Nth conductive material layer 115 in the capacitor storage node contact hole 104, and the Nth conductive material layer 115 fills the capacitor storage node contact hole 104, as shown in Figure 16; where N is greater than or equal to 3 integer.
  • N is an integer greater than 3
  • steps of forming a conductive material layer corresponding to the substrate and annealing the deposited conductive material layer are also included between step 324 and step S325.
  • the first conductive material layer 111 may be formed using a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or the like.
  • the formed first conductive material layer 111 may include but is not limited to a doped polysilicon layer.
  • the first conductive material layer 111 may be annealed in an atmosphere including hydrogen.
  • the first conductive material layer 111 may be annealed in a pure hydrogen atmosphere.
  • hydrogen gas can be introduced into the environment where the first conductive material layer 111 is located to form a pure hydrogen atmosphere.
  • the gas flow rate of hydrogen can be 1slm (Standard Liter per Minute, standard liter per minute) to 100slm.
  • the gas flow rate of hydrogen can be 1slm, 10slm, 50slm or 100slm, etc.
  • the first conductive material layer 111 may be annealed in a mixed atmosphere of hydrogen and nitrogen.
  • a mixed gas of hydrogen and nitrogen can be introduced into the environment where the first conductive material layer 111 is located to form a mixed atmosphere of hydrogen and nitrogen.
  • the gas flow rate of hydrogen can be 1slm (Standard Liter per Minute, standard liter per minute) to 100slm.
  • the gas flow rate of hydrogen can be 1slm, 10slm, 50slm or 100slm, etc.
  • the temperature for annealing the first conductive material layer 111 may be 700°C (degrees Celsius) to 1200°C. Specifically, the temperature for annealing the first conductive material layer 111 may be 700°C, 800°C, 900°C, 1000°C, 1100°C or 1200°C, etc.
  • the time for annealing the first conductive material layer 111 may be 30s (seconds) to 2h (hours). Specifically, the time for annealing the first conductive material layer 111 may be 30s, 5min (minutes), 10min, 30min, 1h or 2h, etc.
  • the annealing pressure of the first conductive material layer 111 may be 10 Torr to 760 Torr. Specifically, the annealing pressure of the first conductive material layer 111 may be 10Torr, 50Torr, 100Torr, 200Torr, 300Torr, 400Torr, 500Torr, 600Torr, 700Torr or 760Torr, etc.
  • step S322 after the first conductive material layer 111 is annealed, the portions of the obtained first conductive layer 112 located at the top corners of the side walls of the capacitor storage node contact holes 104 are all rounded, as shown in FIG. 13 .
  • the specific selection of the above gas flow, pressure and annealing time can control the filleting rate at the corners. Under the same gas flow and annealing time, the greater the pressure, the higher the temperature, the greater the filleting rate. When the pressure and time are constant, the greater the flow rate, the higher the temperature, and the greater the filleting rate. Depending on the aspect ratio of the bit line contact hole 103 and the specific thickness of the deposited conductive material layer, the requirements for flow rate, pressure, processing time, and processing temperature are also different.
  • the second conductive material layer 113 may be formed using a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or the like.
  • the formed second conductive material layer 113 may include but is not limited to a doped polysilicon layer.
  • step S324 the second conductive material layer 113 may be annealed in an atmosphere including hydrogen.
  • the second conductive material layer 113 may be annealed in a pure hydrogen atmosphere.
  • hydrogen gas can be introduced into the environment where the second conductive material layer 113 is located to form a pure hydrogen atmosphere.
  • the gas flow rate of hydrogen can be 1slm (Standard Liter per Minute, standard liter per minute) to 100slm.
  • the gas flow rate of hydrogen can be 1slm, 10slm, 50slm or 100slm, etc.
  • the second conductive material layer 113 may be annealed in a mixed atmosphere of hydrogen and nitrogen.
  • a mixed gas of hydrogen and nitrogen can be introduced into the environment where the second conductive material layer 113 is located to form a mixed atmosphere of hydrogen and nitrogen.
  • the gas flow rate of hydrogen can be 1slm (Standard Liter per Minute, standard liter per minute) to 100slm.
  • the gas flow rate of hydrogen can be 1slm, 10slm, 50slm or 100slm, etc.
  • the temperature for annealing the second conductive material layer 113 may be 700°C (degrees Celsius) to 1200°C. Specifically, the temperature for annealing the second conductive material layer 113 may be 700°C, 800°C, 900°C, 1000°C, 1100°C or 1200°C, etc.
  • the time for annealing the second conductive material layer 113 may be 30s (seconds) to 2h (hours). Specifically, the time for annealing the second conductive material layer 113 may be 30s, 5min (minutes), 10min, 30min, 1h or 2h, etc.
  • the annealing pressure of the second conductive material layer 113 may be 10 Torr to 760 Torr.
  • the annealing pressure for the second conductive material layer 113 may be 10Torr, 50Torr, 100Torr, 200Torr, 300Torr, 400Torr, 500Torr, 600Torr, 700Torr or 760Torr, etc.
  • step S324 after the second conductive material layer 113 is annealed, the portions of the obtained second conductive layer 114 located at the top corners of the side walls of the capacitor storage node contact holes 104 are all rounded, as shown in FIG. 7 .
  • the Nth conductive material layer 115 may be formed using a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or the like.
  • the Nth conductive material layer 115 formed may include but is not limited to a doped polysilicon layer.
  • step S325 uses a deposition process to fill the Nth conductive material layer 115 in the capacitor storage node contact hole 104 , it also includes:
  • step S326 Perform planarization processing on the structure obtained in step S325 to remove the first conductive layer 112, the second conductive layer 114 and the Nth conductive material layer 115 located on the upper surface of the dielectric layer 102, leaving those remaining in the capacitor storage node contact hole 104.
  • the first conductive layer 112 , the second conductive layer 114 and the Nth conductive material layer 115 together form a capacitive storage node contact structure 117 .
  • step S326 a CMP (Chemical Mechanical Polishing) process can be used to planarize the structure obtained in step S325.
  • CMP Chemical Mechanical Polishing
  • the capacitor storage node contact hole is filled by performing multiple deposition processes of the conductive material layer 11 instead of one deposition process.
  • 104 is filled, and the deposited conductive material layer 11 is annealed after at least part of the conductive material layer 11 deposition process, so that the conductive material layer 11 can fill the capacitor storage node contact hole 104 without holes, that is, a capacitor without holes can be obtained.
  • the storage node contact structure 117 thereby reduces the contact resistance of the capacitive storage node contact structure 117 and improves the yield of the semiconductor device structure.
  • the capacitance storage node contact hole 104 can also be replaced by an interconnection contact hole between the metal layer and the substrate, and the final capacitance storage node contact structure 117 can be replaced by the metal layer. interconnection contact structure with the substrate.
  • the substrate 101 can also be replaced with a dielectric layer formed with a metal layer.
  • the capacitor storage node contact hole 104 can also be replaced with an interconnection contact hole between the metal layers.
  • the resulting capacitive storage node contact structure 117 can be replaced by an interconnection contact structure between metal layers.
  • This embodiment of the present disclosure also provides a method for preparing a memory device structure, including the following steps:
  • FIG. 19 is a top structural schematic diagram of the structure obtained in step S40, and Figure 20 is a cross-sectional structural schematic diagram along the AA direction in Figure 19.
  • FIG. 21 is a schematic top view of the structure obtained in step S41
  • FIG. 22 is a schematic cross-sectional structural view along the AA direction in FIG. 21.
  • the buried gate word line 20 may include a gate oxide layer 201, a first gate conductive layer 202, a second gate conductive layer 203 and a filling dielectric layer 204; the gate oxide layer 201 is located on the sidewalls and bottom of the gate trench.
  • the first gate conductive layer 202 is located in the gate trench and is located on the surface of the gate oxide layer 201;
  • the second gate conductive layer 203 is located in the gate trench and is located on the surface of the first gate conductive layer 202 , the top of the first gate conductive layer 202 and the top of the second gate conductive layer 203 are lower than the top of the gate trench;
  • the filling dielectric layer 204 fills the gate trench.
  • S42 Form a bit line contact hole 103 in the substrate 101, and form a bit line contact structure 116 in the bit line contact hole 103 using the semiconductor structure preparation method corresponding to the embodiment shown in Figure 2 to Figure 9.
  • the bit line contact structure 116 In contact with the active area, as shown in Figure 23 and Figure 24.
  • bit line structure 30 Form a plurality of bit line structures 30 arranged in parallel and spaced apart on the substrate 101.
  • the bit line structures 30 extend along a third direction; the second direction intersects both the first direction and the third direction, as shown in Figure 25 and
  • Figure 25 is a top structural schematic diagram of the structure obtained in step S43
  • Figure 26 is a cross-sectional structural schematic diagram along the AA direction in Figure 25.
  • the bit line structure 30 may include a stacked structure composed of a first bit line conductive layer 301, a second bit line conductive layer 302 and a bit line dielectric layer 303 sequentially stacked from bottom to top, and bit lines located on the side walls of the stacked structure. Side wall 304, as shown in Figure 26.
  • the insulating isolation layer 40 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or the like.
  • S45 Form the capacitance storage node contact hole 104 in the insulating isolation layer 40, as shown in FIG. 28; use the preparation method of the semiconductor structure in the corresponding embodiment of FIG. 10 to FIG. 17 to form the capacitance storage node contact hole 104.
  • Node contact structure 117, the capacitive storage node contact structure 117 is in contact with the active area, as shown in Figure 29.
  • the capacitor 50 may include a lower electrode (not shown), a capacitive dielectric layer (not shown) located on the surface of the lower electrode, and an upper electrode (not shown).
  • the lower electrode and the capacitor The storage node contact structures 117 are in contact, as shown in FIG. 30 .
  • the execution of the steps is not strictly limited in order, and the steps may be executed in other orders. Moreover, at least part of the steps described may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but may be executed at different times. The execution sequence is not necessarily sequential, but may be performed in turn or alternately with other steps or sub-steps of other steps or at least part of the stages.

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Abstract

本公开实施例涉及一种半导体结构的制备方法，包括：提供待刻蚀结构；于待刻蚀结构内形成刻蚀孔；执行多次导电材料层沉积工艺，直至导电材料层无孔洞填满刻蚀孔；其中，至少部分导电材料层沉积工艺之后还包括对沉积的导电材料层进行退火处理。上述半导体结构的制备方法，在沉积导电材料层对刻蚀孔进行填充时，通过执行多次导电材料层沉积工艺，而并非一次沉积工艺将刻蚀孔填满，并在至少部分导电材料层沉积工艺之后对沉积的导电材料层进行退火处理，可以使得导电材料层无孔洞填满刻蚀孔。

Description

半导体结构的制备方法
相关申请的交叉引用
本公开实施例要求于2022年6月30日提交中国专利局、申请号为202210761057.8的中国专利的优先权，所述专利申请的全部内容通过引用结合在本公开实施例中。
技术领域
本公开实施例涉及半导体技术领域，特别是涉及半导体结构的制备方法。
背景技术
随着半导体技术的发展，半导体结构的尺寸越来越小，半导体结构中的刻蚀孔的深宽比会越来越高，当使用导电材料层于刻蚀孔内进行一次沉积填充形成导电接触结构时，很容易在导电接触结构内形成孔洞(Void)，从而影响导电接触结构的接触电阻，甚至影响半导体器件结构的良率。
发明内容
根据本公开实施例的各种实施例，提供一种半导体结构的制备方法。
根据一些实施例，本公开实施例一方面提供一种半导体结构的制备方法，包括：
提供待刻蚀结构；
于所述待刻蚀结构内形成刻蚀孔；
执行多次导电材料层沉积工艺，直至所述导电材料层无孔洞填满所述刻蚀孔；其中，至少部分所述导电材料层沉积工艺之后还包括对沉积的所述导电材料层进行退火处理。
根据一些实施例，各所述导电材料层沉积工艺之后，均还包括对沉积的所述导电材料层进行退火处理。
根据一些实施例，对所述导电材料层进行退火处理后，所述导电材料层位于所述刻蚀孔侧壁顶部拐角处的部分均呈圆角状。
根据一些实施例，所述待刻蚀结构包括衬底，所述刻蚀孔包括位线接触孔，所述导电材料层无孔洞填满所述刻蚀孔后形成位线接触结构。
根据一些实施例，所述至少部分所述导电材料层沉积工艺之后还包括对沉积的所述导电材料层进行退火处理，包括：
在第奇数次所述导电材料层沉积工艺之后，对沉积的所述导电材料层进行退火处理；或
在第偶数次所述导电材料层沉积工艺之后，对沉积的所述导电材料层进行退火处理。
根据一些实施例，所述执行多次导电材料层沉积工艺的过程中，对沉积的所述导电材料层进行退火处理的次数大于等于所述导电材料层沉积的次数的一半。
根据一些实施例，所述待刻蚀结构包括：衬底及位于所述衬底上的介质层；所述刻蚀孔沿厚度方向贯穿所述介质层；所述导电材料层无孔洞填满所述刻蚀孔后形成电容存储节点接触结构。
根据一些实施例，所述导电材料层包括掺杂多晶硅层。
根据一些实施例，所述刻蚀孔的深宽比大于或等于4:1。
根据一些实施例，于包括氢气的气氛下对所述导电材料层进行退火处理。
根据一些实施例，于纯氢气气氛下对所述导电材料层进行退火处理。
根据一些实施例，于氢气及氮气的混合气氛下对所述导电材料层进行退火处理。
根据一些实施例，所述退火处理的温度包括700℃～1200℃。
根据一些实施例，所述退火处理的时间包括30s～2h。
根据一些实施例，所述退火处理过程中的退火压力包括10Torr～760Torr。
根据一些实施例，于包括氢气的气氛下对所述导电材料层进行退火处理的过程中，氢气的气体流量为1slm～100slm。
本公开实施例可以/至少具有以下优点：
本公开实施例中的半导体结构的制备方法，在沉积导电材料层对刻蚀孔进行填充时，通过执行多次导电材料层沉积工艺，而并非一次沉积工艺将刻蚀孔填满，并在至少部分导电材料层沉积工艺之后对沉积的导电材料层进行退火处理，可以使得导电材料层无孔洞填满刻蚀孔。
本公开实施例的一个或多个实施例的细节在下面的附图和描述中提出。本公开实施例的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为本公开一实施例中提供的半导体结构的制备方法的流程图；
图2为本公开另一实施例中提供的半导体结构的制备方法的流程图；
图3至图9为本公开另一个实施例中提供的半导体结构的制备方法各步骤所得结构的截面结构示意图；
图10为本公开又一实施例中提供的半导体结构的制备方法的流程图；
图11至图17为本公开又一个实施例中提供的半导体结构的制备方法各步骤所得结构的截面结构示意图；
图18为本公开又一实施例中提供的存储器件结构的制备方法的流程图；
图19至图30为本公开又一个实施例中提供的存储器件结构的制备方法各步骤所得结构的结构示意图。
具体实施方式
为了便于理解本公开实施例，下面将参照相关附图对本公开实施例进行更全面的描述。附图中给出了本公开实施例的实施例。但是，本公开实施例可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本公开实施例的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开实施例的技术领域的技术人员通常理解的含义相同。本文中在本公开实施例的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本公开实施例。
可以理解，本公开实施例所使用的术语“第一”、“第二”等可在本文中用于描述各种元件，但这些元件不受这些术语限制。这些术语仅用于将第一个元件与另一个元件区分。举例来说，在不脱离本公开实施例的范围的情况下，可以将第一电源输入端称为第二电源输入端，且类似地，可将第二电源输入端称为第一电源输入端。第一电源输入端和第二电源输入端两者都是电源输入端，但其不是同一电源输入端。
可以理解，以下实施例中的“连接”，如果被连接的电路、模块、单元等相互之间具有电信号或数据的传递，则应理解为“电连接”、“通信连接”等。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应当理解的是，术语“包括/包含”或“具有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在，但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。
随着半导体技术的发展，半导体结构的尺寸越来越小，半导体结构中的刻蚀孔的深宽比会越来越高，当使用到的材料层于刻蚀孔内进行沉积填充形成导电接触结构时，很容易在导电接触结构内形成孔洞(Void)，从而影响导电接触结构与其他结构的接触电阻，甚至影响半导体结构的良率。
以DRAM(Dynamic Random Access Memory，动态随机存取存储器)为例，随着DRAM的尺寸缩小，ARRAY区(阵列区)的BL(Bitline，位线)的接触孔及电容存储节点的接触孔的深宽比越来越高，而在接触孔内采用一次沉积工艺沉积导电材料层形成位线接触结构(BLC，Bit Line Coupling)或电容存储节点接触结构时，不可避免地会在位线接触结构和电容存储节点接触结构内产生孔洞(Void)，从而影响位线接触结构和电容存储节点接触结构的接触电阻，甚至影响半导体器件结构部的良率。
请参阅图1，本公开实施例提供一种半导体结构的制备方法，包括：
S10：提供待刻蚀结构；
S11：于待刻蚀结构内形成刻蚀孔；
S12：执行多次导电材料层沉积工艺，直至导电材料层无孔洞填满刻蚀孔；其中，至少部分所述导电材料层沉积工艺之后还包括对沉积的导电材料层进行退火处理。
上述半导体结构的制备方法，在沉积导电材料层对刻蚀孔进行填充时，通过执行多次 导电材料层沉积工艺，而并非一次沉积工艺将刻蚀孔填满，并在至少部分导电材料层沉积工艺之后对沉积的导电材料层进行退火处理，可以使得导电材料层无孔洞填满刻蚀孔。
在一个实施例中，待刻蚀结构包括衬底。在该实施例中，如图2所示，半导体结构的制备方法可以包括如下步骤：
S20：提供待刻蚀结构，待刻蚀结构包括衬底；
S21：于待刻蚀结构内形成刻蚀孔，刻蚀孔包括位线接触孔；
S22：执行多次导电材料层沉积工艺，直至导电材料层无孔洞填满刻蚀孔；其中，至少部分所述导电材料层沉积工艺之后还包括对沉积的导电材料层进行退火处理。
在步骤S20中，请参阅图2中的S20步骤及图3，提供待刻蚀结构，待刻蚀结构包括衬底101。
在一个示例中，衬底101可以包括但不仅限于硅衬底。
在步骤S21中，请参阅图2中的S21步骤及图3，于待刻蚀结构内形成刻蚀孔，刻蚀孔包括位线接触孔103。
在一个示例中，可以采用光刻刻蚀工艺于衬底101内形成位线接触孔103。位线接触孔103的纵截面形状可以根据实际需要进行设置，位线接触孔103的纵截面形状可以为倒梯形、矩形或U形等等；本实施例中，位线接触孔103的纵截面形状为倒梯形，如图3所示。
需要说明的是，位线接触孔103的深度小于衬底101的深度。
在一个示例中，位线接触孔103的深宽比可以根据实际需要进行设置，本实施例中，位线接触孔103的深宽比可以大于或等于4:1，譬如，位线接触孔103的深宽比可以为4:1、5:1、10:1、15:1或20:1等等。
在步骤S22中，请参阅图2中的S22步骤及图4至图8，执行多次导电材料层11沉积工艺，直至导电材料层11无孔洞填满刻蚀孔；其中，至少部分导电材料层11沉积工艺之后还包括对沉积的导电材料层11进行退火处理。
在一个示例中，可以在其中一部分沉积工艺之后对沉积的导电材料层11进行退火处理。
在一个可选的示例中，可以在第奇数层导电材料层11沉积工艺之后，对沉积的导电材料层11进行退火处理。在另一个可选的示例中，可以在第偶数层导电层11沉积工艺之后，对沉积的导电材料层11进行退火处理。当然，在其他示例中，也可以根据实际需要对任意部分导电材料层11沉积工艺之后，对沉积的导电材料层11进行退火处理。
需要说明的是，在上述执行多次导电材料层沉积工艺的过程中，对沉积的导电材料层11进行退火处理的次数大于等于导电材料层11沉积的次数的一半。譬如，导电材料层11沉积的次数为10次，对沉积导电材料层11进行退火处理的次数应大于5次，即在大于5次的导电材料层11沉积后需要进行对应的退火热处理。
在另一个示例中，各导电材料层11沉积工艺之后，均还包括对沉积的导电材料层11进行退火处理。该示例中，步骤S22可以包括如下步骤：
S221：采用沉积工艺于位线接触孔103内沉积第一导电材料层111，如图4所示；
S222：对第一导电材料层111进行退火处理，退火处理后得到第一导电层112，如图5所示；
S223：采用沉积工艺于第一导电层112的上表面形成第二导电材料层113，如图6所示；
S224：对第二导电材料层113进行退火处理，退火处理后得到第二导电层113，如图7所示；
S225：采用沉积工艺于位线接触孔103内填充第N导电材料层115，第N导电材料层115填满位线接触孔103，如图8所示；其中，N为大于或等于3的整数。
需要说明的是，当N为大于3的整数时，步骤224与步骤S225之间还包括若干步衬底对应的导电材料层及对沉积的导电材料层进行退火处理的步骤。图8以N＝3作为示例，在其他示例中，N的取值并不以此为限。
在步骤S221中，可以采用物理气相沉积工艺、化学气相沉积工艺或原子层沉积工艺分别形成第一导电材料层111。
在步骤S221中，形成的第一导电材料层111可以包括但不仅限于掺杂多晶硅层。
在步骤S222中，可以于包括氢气的气氛下对第一导电材料层111进行退火处理。
在一个可选的示例中，可以于纯氢气气氛下对第一导电材料层111进行退火处理。具体的，可以向第一导电材料层111所处的环境通入氢气，以形成纯氢气气氛。更为具体的，本示例中，氢气的气体流量可以为1slm(Standard Liter per Minute，每分钟标准升)～100slm，譬如，氢气的气体流量可以为1slm、10slm、50slm或100slm等等。
在另一个可选的示例中，可以于氢气及氮气的混合气氛下对第一导电材料层111进行退火处理。具体的，可以向第一导电材料层111所处的环境通入氢气与氮气的混合气体，以形成氢气及氮气的混合气氛。更为具体的，本示例中，氢气的气体流量可以为1slm(Standard Liter per Minute，每分钟标准升)～100slm，譬如，氢气的气体流量可以为1slm、10slm、50slm或100slm等等。
在步骤S222中，对第一导电材料层111退火处理的温度可以为700℃(摄氏度)～1200℃。具体的，对第一导电材料层111退火处理的温度可以为700℃、800℃、900℃、1000℃、1100℃或1200℃等等。
在步骤S222中，对第一导电材料层111退火处理的时间可以为30s(秒)～2h(小时)。具体的，对第一导电材料层111退火处理的时间可以为30s、5min(分钟)、10min、30min、1h或2h等等。
在步骤S222中，对第一导电材料层111退火处理的退火压力可以为10Torr(托)～760Torr。具体的，对第一导电材料层111退火处理的退火压力可以为10Torr、50Torr、100Torr、200Torr、300Torr、400Torr、500Torr、600Torr、700Torr或760Torr等等。
在步骤S222中，对第一导电材料层111进行退火处理后，得到的第一导电层112位于位线接触孔103侧壁顶部拐角处的部分均呈圆角状，如图5所示。
上述气体流量，压力以及退火时间的具体选择，可以对拐角处的圆角化率进行控制，在同样的气体流量和退火时间下，压力越大，温度越高，圆角化率越大，在压力和时间恒定的情况下，流量越大，温度越高，圆角化率越大。依据位线接触孔103的深宽比的不同以及沉积的导电材料层的具体厚度不同，其对流量，压力以及处理时间，处理温度的需求也不同。
在步骤S223中，可以采用物理气相沉积工艺、化学气相沉积工艺或原子层沉积工艺等分别形成第二导电材料层113。
在步骤S223中，形成的第二导电材料层113可以包括但不仅限于掺杂多晶硅层。
在步骤S224中，可以于包括氢气的气氛下对第二导电材料层113进行退火处理。
在一个可选的示例中，可以于纯氢气气氛下对第二导电材料层113进行退火处理。具体的，可以向第二导电材料层113所处的环境通入氢气，以形成纯氢气气氛。更为具体的，本示例中，氢气的气体流量可以为1slm(Standard Liter per Minute，每分钟标准升)～100slm，譬如，氢气的气体流量可以为1slm、10slm、50slm或100slm等等。
在另一个可选的示例中，可以于氢气及氮气的混合气氛下对第二导电材料层113进行退火处理。具体的，可以向第二导电材料层113所处的环境通入氢气与氮气的混合气体，以形成氢气及氮气的混合气氛。更为具体的，本示例中，氢气的气体流量可以为1slm(Standard Liter per Minute，每分钟标准升)～100slm，譬如，氢气的气体流量可以为1slm、10slm、50slm或100slm等等。
在步骤S224中，对第二导电材料层113退火处理的温度可以为700℃(摄氏度)～1200℃。具体的，对第二导电材料层113退火处理的温度可以为700℃、800℃、900℃、1000℃、1100℃或1200℃等等。
在步骤S224中，对第二导电材料层113退火处理的时间可以为30s(秒)～2h(小时)。具体的，对第二导电材料层113退火处理的时间可以为30s、5min(分钟)、10min、30min、1h或2h等等。
在步骤S224中，对第二导电材料层113退火处理的退火压力可以为10Torr(托)～760Torr。具体的，对第二导电材料层113退火处理的退火压力可以为10Torr、50Torr、100Torr、200Torr、300Torr、400Torr、500Torr、600Torr、700Torr或760Torr等等。
在步骤S224中，对第二导电材料层113进行退火处理后，得到的第二导电层114位于位线接触孔103侧壁顶部拐角处的部分均呈圆角状，如图7所示。
在步骤S225中，可以采用物理气相沉积工艺、化学气相沉积工艺或原子层沉积工艺等分别形成第N导电材料层115。
在步骤S225中，形成的第N导电材料层115可以包括但不仅限于掺杂多晶硅层。
在一个示例中，请参阅图9，步骤S225采用沉积工艺于位线接触孔103内填充第N导电材料层115之后，还包括：
S226：将步骤S225所得结构进行平坦化处理，以去除位于衬底101上表面的第一导电层112、第二导电层114及第N导电材料层115，保留于位线接触孔103内的第一导电 层112、第二导电层114及第N导电材料层115共同构成位线结构116。
具体的，步骤S226中，可以采用CMP(Chemical Mechanical Polishing，化学机械抛光)工艺对步骤S225所得结构进行平坦化处理。
上述实施例中的半导体结构的制备方法，在沉积导电材料层11对位线接触孔103进行填充时，通过执行多次导电材料层11沉积工艺，而并非一次沉积工艺将位线接触孔103填满，并在至少部分导电材料层11沉积工艺之后对沉积的导电材料层11进行退火处理，可以使得导电材料层11无孔洞填满位线接触孔103，即可以得到无孔隙的位线接触结构116，从而降低位线接触结构116的接触电阻，提高半导体器件结构的良率。
在另一个实施例中，衬底及位于衬底上的介质层；刻蚀孔沿厚度方向贯穿介质层。在该实施例中，如图10所示，半导体结构的制备方法可以包括如下步骤：
S30：提供待刻蚀结构，待刻蚀结构包括衬底及位于衬底上的介质层；
S31：于待刻蚀结构内形成刻蚀孔，刻蚀孔沿厚度方向贯穿介质层，刻蚀孔包括电容存储节点接触孔；
S32：执行多次导电材料层沉积工艺，直至导电材料层无孔洞填满刻蚀孔；其中，至少部分所述导电材料层沉积工艺之后还包括对沉积的导电材料层进行退火处理。
在步骤S30中，请参阅图10中的S30步骤及图11，提供待刻蚀结构10，待刻蚀结构10包括衬底101及位于衬底101上的介质层102。
在一个示例中，衬底101可以包括但不仅限于硅衬底；介质层102可以包括但不仅限于氧化硅层、氮化硅层或氮氧化硅层等等。
在步骤S31中，请参阅图10中的S31步骤及图11，于待刻蚀结构10内形成刻蚀孔，刻蚀孔沿厚度方向贯穿介质层102，刻蚀孔包括电容存储节点接触孔104。
在一个示例中，可以采用光刻刻蚀工艺于介质层102内形成电容存储节点接触孔104。电容存储节点接触孔104的纵截面形状可以根据实际需要进行设置，电容存储节点接触孔104的纵截面形状可以为倒梯形、矩形或U形等等；本实施例中，电容存储节点接触孔104的纵截面形状为倒梯形，如图11所示。
需要说明的是，电容存储节点接触孔104的深度可以大于介质层102的厚度，小于介质层102与衬底101的厚度之和，即电容存储节点接触孔104深入到衬底101的内部。
在一个示例中，电容存储节点接触孔104的深宽比可以根据实际需要进行设置，本实施例中，电容存储节点接触孔104的深宽比可以大于或等于4:1，譬如，电容存储节点接触孔104的深宽比可以为4:1、5:1、10:1、15:1或20:1等等。
在步骤S32中，请参阅图10中的S32步骤及图12至图17，执行多次导电材料层11沉积工艺，直至导电材料层11无孔洞填满刻蚀孔；其中，至少部分导电材料层11沉积工艺之后还包括对沉积的导电材料层11进行退火处理。
在一个示例中，可以在其中一部分沉积工艺之后对沉积的导电材料层11进行退火处理。
在一个可选的示例中，可以在第奇数层导电材料层11沉积工艺之后，对沉积的导电 材料层11进行退火处理。在另一个可选的示例中，可以在第偶数层导电层11沉积工艺之后，对沉积的导电材料层11进行退火处理。当然，在其他示例中，也可以根据实际需要对任意部分导电材料层11沉积工艺之后，对沉积的导电材料层11进行退火处理。
需要说明的是，在上述执行多次导电材料层沉积工艺的过程中，对沉积的导电材料层11进行退火处理的次数大于等于导电材料层11沉积的次数的一半。譬如，导电材料层11沉积的次数为10次，对沉积导电材料层11进行退火处理的次数应大于5次，即在大于5次的导电材料层11沉积后需要进行对应的退火热处理。
在另一个示例中，各导电材料层11沉积工艺之后，均还包括对沉积的导电材料层11进行退火处理。该示例中，步骤S32可以包括如下步骤：
S321：采用沉积工艺于电容存储节点接触孔104内沉积第一导电材料层111，如图12所示；
S322：对第一导电材料层111进行退火处理，退火处理后得到第一导电层112，如图13所示；
S323：采用沉积工艺于第一导电层112的上表面形成第二导电材料层113，如图14所示；
S324：对第二导电材料层113进行退火处理，退火处理后得到第二导电层113，如图15所示；
S325：采用沉积工艺于电容存储节点接触孔104内填充第N导电材料层115，第N导电材料层115填满电容存储节点接触孔104，如图16所示；其中，N为大于或等于3的整数。
需要说明的是，当N为大于3的整数时，步骤324与步骤S325之间还包括若干步衬底对应的导电材料层及对沉积的导电材料层进行退火处理的步骤。图16以N＝3作为示例，在其他示例中，N的取值并不以此为限。
在步骤S321中，可以采用物理气相沉积工艺、化学气相沉积工艺或原子层沉积工艺等形成第一导电材料层111。
在步骤S321中，形成的第一导电材料层111可以包括但不仅限于掺杂多晶硅层。
在步骤S322中，可以于包括氢气的气氛下对第一导电材料层111进行退火处理。
在一个可选的示例中，可以于纯氢气气氛下对第一导电材料层111进行退火处理。具体的，可以向第一导电材料层111所处的环境通入氢气，以形成纯氢气气氛。更为具体的，本示例中，氢气的气体流量可以为1slm(Standard Liter per Minute，每分钟标准升)～100slm，譬如，氢气的气体流量可以为1slm、10slm、50slm或100slm等等。
在另一个可选的示例中，可以于氢气及氮气的混合气氛下对第一导电材料层111进行退火处理。具体的，可以向第一导电材料层111所处的环境通入氢气与氮气的混合气体，以形成氢气及氮气的混合气氛。更为具体的，本示例中，氢气的气体流量可以为1slm(Standard Liter per Minute，每分钟标准升)～100slm，譬如，氢气的气体流量可以为1slm、10slm、50slm或100slm等等。
在步骤S322中，对第一导电材料层111退火处理的温度可以为700℃(摄氏度)～1200℃。具体的，对第一导电材料层111退火处理的温度可以为700℃、800℃、900℃、1000℃、1100℃或1200℃等等。
在步骤S322中，对第一导电材料层111退火处理的时间可以为30s(秒)～2h(小时)。具体的，对第一导电材料层111退火处理的时间可以为30s、5min(分钟)、10min、30min、1h或2h等等。
在步骤S322中，对第一导电材料层111退火处理的退火压力可以为10Torr(托)～760Torr。具体的，对第一导电材料层111退火处理的退火压力可以为10Torr、50Torr、100Torr、200Torr、300Torr、400Torr、500Torr、600Torr、700Torr或760Torr等等。
在步骤S322中，对第一导电材料层111进行退火处理后，得到的第一导电层112位于电容存储节点接触孔104侧壁顶部拐角处的部分均呈圆角状，如图13所示。
上述气体流量，压力以及退火时间的具体选择，可以对拐角处的圆角化率进行控制，在同样的气体流量和退火时间下，压力越大，温度越高，圆角化率越大，在压力和时间恒定的情况下，流量越大，温度越高，圆角化率越大。依据位线接触孔103的深宽比的不同以及沉积的导电材料层的具体厚度不同，其对流量，压力以及处理时间，处理温度的需求也不同。
在步骤S323中，可以采用物理气相沉积工艺、化学气相沉积工艺或原子层沉积工艺等分别形成第二导电材料层113。
在步骤S323中，形成的第二导电材料层113可以包括但不仅限于掺杂多晶硅层。
在步骤S324中，可以于包括氢气的气氛下对第二导电材料层113进行退火处理。
在一个可选的示例中，可以于纯氢气气氛下对第二导电材料层113进行退火处理。具体的，可以向第二导电材料层113所处的环境通入氢气，以形成纯氢气气氛。更为具体的，本示例中，氢气的气体流量可以为1slm(Standard Liter per Minute，每分钟标准升)～100slm，譬如，氢气的气体流量可以为1slm、10slm、50slm或100slm等等。
在另一个可选的示例中，可以于氢气及氮气的混合气氛下对第二导电材料层113进行退火处理。具体的，可以向第二导电材料层113所处的环境通入氢气与氮气的混合气体，以形成氢气及氮气的混合气氛。更为具体的，本示例中，氢气的气体流量可以为1slm(Standard Liter per Minute，每分钟标准升)～100slm，譬如，氢气的气体流量可以为1slm、10slm、50slm或100slm等等。
在步骤S324中，对第二导电材料层113退火处理的温度可以为700℃(摄氏度)～1200℃。具体的，对第二导电材料层113退火处理的温度可以为700℃、800℃、900℃、1000℃、1100℃或1200℃等等。
在步骤S324中，对第二导电材料层113退火处理的时间可以为30s(秒)～2h(小时)。具体的，对第二导电材料层113退火处理的时间可以为30s、5min(分钟)、10min、30min、1h或2h等等。
在步骤S324中，对第二导电材料层113退火处理的退火压力可以为10Torr(托) ～760Torr。具体的，对第二导电材料层113退火处理的退火压力可以为10Torr、50Torr、100Torr、200Torr、300Torr、400Torr、500Torr、600Torr、700Torr或760Torr等等。
在步骤S324中，对第二导电材料层113进行退火处理后，得到的第二导电层114位于电容存储节点接触孔104侧壁顶部拐角处的部分均呈圆角状，如图7所示。
在步骤S325中，可以采用物理气相沉积工艺、化学气相沉积工艺或原子层沉积工艺等分别形成第N导电材料层115。
在步骤S325中，形成的第N导电材料层115可以包括但不仅限于掺杂多晶硅层。
在一个示例中，请参阅图17，步骤S325采用沉积工艺于电容存储节点接触孔104内填充第N导电材料层115之后，还包括：
S326：将步骤S325所得结构进行平坦化处理，以去除位于介质层102上表面的第一导电层112、第二导电层114及第N导电材料层115，保留于电容存储节点接触孔104内的第一导电层112、第二导电层114及第N导电材料层115共同构成电容存储节点接触结构117。
具体的，步骤S326中，可以采用CMP(Chemical Mechanical Polishing，化学机械抛光)工艺对步骤S325所得结构进行平坦化处理。
上述实施例中的半导体结构的制备方法，在沉积导电材料层11对电容存储节点接触孔104进行填充时，通过执行多次导电材料层11沉积工艺，而并非一次沉积工艺将电容存储节点接触孔104填满，并在至少部分导电材料层11沉积工艺之后对沉积的导电材料层11进行退火处理，可以使得导电材料层11无孔洞填满电容存储节点接触孔104，即可以得到无孔隙的电容存储节点接触结构117，从而降低电容存储节点接触结构117的接触电阻，提高半导体器件结构的良率。
需要说明的是，在其他一个实施例中，电容存储节点接触孔104还可以替换为金属层与衬底之间的互连接触孔，最终得到的电容存储节点接触结构117即可替换为金属层与衬底之间的互连接触结构。在其他另一个实施例中，衬底101也可以替换为形成有金属层的介质层，此时，电容存储节点接触孔104还可以替换为金属层与金属层之间的互连接触孔，最终得到的电容存储节点接触结构117即可替换为金属层与金属层之间的互连接触结构。
在又一个实施例中，请参阅图18，本公开实施例还提供一种存储器件结构的制备方法，包括如下步骤：
S40：提供衬底101，衬底101内形成有浅沟槽隔离结构106，浅沟槽隔离结构106于衬底内隔离出多个间隔排布的有源区105，有源区105沿第一方向延伸，如图19及图20所示，其中，图19为步骤S40所得结构的俯视结构示意图，图20为沿图19中AA方向的截面结构示意图。
S41：于衬底101内形成多条平行间隔排布的埋入式栅极字线20，埋入式栅极字线20沿第二方向延伸，如图21及图22所示，其中，图21为步骤S41所得结构的俯视结构示意图，图22为沿图21中AA方向的截面结构示意图。埋入式栅极字线20可以包括栅氧化层201、第一栅极导电层202、第二栅极导电层203及填充介质层204；栅氧化层201位 于栅极沟槽的侧壁及底壁；第一栅极导电层202位于栅极沟槽内，且位于栅氧化层201的表面；第二栅极导电层203位于栅极沟槽内，且位于第一栅极导电层202的表面，第一栅极导电层202的顶部及第二栅极导电层203的顶部低于栅极沟槽的顶部；填充介质层204填满栅极沟槽。
S42：于衬底内101形成位线接触孔103，采用如图2至图9对应实施例中的半导体结构的制备方法于位线接触孔103内形成位线接触结构116，位线接触结构116与有源区相接触，如图23及图24所示。
S43：于衬底101上形成多条平行间隔排布的位线结构30，位线结构30沿第三方向延伸；第二方向与所述第一方向及第三方向均相交，如图25及图26所示，其中，图25为步骤S43所得结构的俯视结构示意图，图26为沿图25中AA方向的截面结构示意图。位线结构30可以包括由下至上依次叠置的第一位线导电层301、第二位线导电层302及位线介质层303构成的叠层结构，以及位于叠层结构侧壁的位线侧墙304，如图26所示。
S44：于相邻位线结构30之间填充绝缘隔离层40，如图27所示。绝缘隔离层40可以包括但不仅限于氧化硅层、氮化硅层或氮氧化硅层等等。
S45：于绝缘隔离层40内形成电容存储节点接触孔104，如图28所示；采用如图10至图17对应实施例中的半导体结构的制备方法于电容存储节点接触孔104内形成电容存储节点接触结构117，电容存储节点接触结构117与有源区相接触，如图29所示。
S46：于绝缘隔离层40上形成电容器50，电容器50可以包括下电极(未示出)、位于下电极表面的电容介质层(未示出)及上电极(未示出)，下电极与电容存储节点接触结构117相接触，如图30所示。
上述实施例中的存储器件结构的制备方法，在沉积导电材料层对位线接触孔103进行填充时，通过执行多次导电材料层沉积工艺，而并非一次沉积工艺将位线接触孔103填满，并在至少部分导电材料层沉积工艺之后对沉积的导电材料层进行退火处理，可以使得导电材料层无孔洞填满位线接触孔103，即可以得到无孔隙的位线接触结构116，从而降低位线接触结构116的接触电阻，提高存储器件结构的良率。
上述实施例中的存储器件结构的制备方法，在沉积导电材料层对电容存储节点接触孔104进行填充时，通过执行多次导电材料层沉积工艺，而并非一次沉积工艺将电容存储节点接触孔104填满，并在至少部分导电材料层沉积工艺之后对沉积的导电材料层进行退火处理，可以使得导电材料层无孔洞填满电容存储节点接触孔104，即可以得到无孔隙的电容存储节点接触结构117，从而降低电容存储节点接触结构117的接触电阻，提高存储器件结构的良率。
应该理解的是，除非本文中有明确的说明，所述的步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，所述的步骤的至少一部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些子步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤的子步骤或者阶段的至少一部分轮流或者交替地执行。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本公开实施例的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本公开实施例构思的前提下，还可以做出若干变形和改进，这些都属于本公开实施例的保护范围。因此，本公开实施例专利的保护范围应以所附权利要求为准。

Claims (16)

  1. 一种半导体结构的制备方法，包括：
    提供待刻蚀结构；
    于所述待刻蚀结构内形成刻蚀孔；
    执行多次导电材料层沉积工艺，直至所述导电材料层无孔洞填满所述刻蚀孔；其中，至少部分所述导电材料层沉积工艺之后还包括对沉积的所述导电材料层进行退火处理。
  2. 根据权利要求1所述的半导体结构的制备方法，其中，各所述导电材料层沉积工艺之后，均还包括对沉积的所述导电材料层进行退火处理。
  3. 根据权利要求1所述的半导体结构的制备方法，其中，对所述导电材料层进行退火处理后，所述导电材料层位于所述刻蚀孔侧壁顶部拐角处的部分均呈圆角状。
  4. 根据权利要求1所述的半导体结构的制备方法，其中，所述待刻蚀结构包括衬底，所述刻蚀孔包括位线接触孔，所述导电材料层无孔洞填满所述刻蚀孔后形成位线接触结构。
  5. 根据权利要求1所述的半导体结构的制备方法，其中，所述至少部分所述导电材料层沉积工艺之后还包括对沉积的所述导电材料层进行退火处理，包括：
    在第奇数次所述导电材料层沉积工艺之后，对沉积的所述导电材料层进行退火处理；或
    在第偶数次所述导电材料层沉积工艺之后，对沉积的所述导电材料层进行退火处理。
  6. 根据权利要求5所述的半导体结构的制备方法，其中，所述执行多次导电材料层沉积工艺的过程中，对沉积的所述导电材料层进行退火处理的次数大于等于所述导电材料层沉积的次数的一半。
  7. 根据权利要求1所述的半导体结构的制备方法，其中，所述待刻蚀结构包括：衬底及位于所述衬底上的介质层；所述刻蚀孔沿厚度方向贯穿所述介质层；所述导电材料层无孔洞填满所述刻蚀孔后形成电容存储节点接触结构。
  8. 根据权利要求1所述的半导体结构的制备方法，其中，所述导电材料层包括掺杂多晶硅层。
  9. 根据权利要求1所述的半导体结构的制备方法，其中，所述刻蚀孔的深宽比大于或等于4:1。
  10. 根据权利要求1至10中任一项所述的半导体结构的制备方法，其中，于包括氢气的气氛下对所述导电材料层进行退火处理。
  11. 根据权利要求10所述的半导体结构的制备方法，其中，于纯氢气气氛下对所述导电材料层进行退火处理。
  12. 根据权利要求10所述的半导体结构的制备方法，其中，于氢气及氮气的混合气氛下对所述导电材料层进行退火处理。
  13. 根据权利要求10所述的半导体结构的制备方法，其中，所述退火处理的温度包括700℃～1200℃。
  14. 根据权利要求10所述的半导体结构的制备方法，其中，所述退火处理的时间包括 30s～2h。
  15. 根据权利要求10所述的半导体结构的制备方法，其中，所述退火处理过程中的退火压力包括10Torr～760Torr。
  16. 根据权利要求10所述的半导体结构的制备方法，其中，于包括氢气的气氛下对所述导电材料层进行退火处理的过程中，氢气的气体流量为1slm～100slm。
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