WO2024000701A1 - 像素电路及显示面板 - Google Patents

像素电路及显示面板 Download PDF

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Publication number
WO2024000701A1
WO2024000701A1 PCT/CN2022/106969 CN2022106969W WO2024000701A1 WO 2024000701 A1 WO2024000701 A1 WO 2024000701A1 CN 2022106969 W CN2022106969 W CN 2022106969W WO 2024000701 A1 WO2024000701 A1 WO 2024000701A1
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WIPO (PCT)
Prior art keywords
transistor
control signal
wiring
pixel circuit
source
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Application number
PCT/CN2022/106969
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English (en)
French (fr)
Inventor
张淑媛
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/798,997 priority Critical patent/US20240194135A1/en
Publication of WO2024000701A1 publication Critical patent/WO2024000701A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present application relates to the field of display technology, and specifically to a pixel circuit and a display panel.
  • the data signal can be written to the gate of the driving transistor in the first working cycle of the corresponding transistor, while in the subsequent working cycles of the same frame, the data signal can only be written to the gate of the driving transistor. Write to one or both poles of the drive transistor except the gate. If the data signal is written continuously in this way, the three-terminal voltage of the drive transistor will change. Affected by the hysteresis characteristics, the threshold voltage (Vth) of the drive transistor will change. Drift (Shift) occurs, and the final manifestation is that the luminous brightness in the first working cycle is inconsistent with the luminous brightness in other subsequent working cycles in the same frame. This brightness difference will cause regular changes in brightness, and then show severe flickering. (Flicker).
  • This application provides a pixel circuit and a display panel to alleviate the technical problem of threshold voltage drift of the driving transistor in low-frequency operating mode.
  • the present application provides a pixel circuit.
  • the pixel circuit includes a driving transistor, a writing transistor, a first transistor and a second transistor.
  • One of the source/drain of the writing transistor and the source/drain of the driving transistor are One of the drains is connected, the other of the source/drain of the write transistor is connected to the data line, the gate of the write transistor is connected to the first trace; one of the source/drain of the first transistor Connected to the second wiring, the other of the source/drain of the first transistor is connected to one of the source/drain of the driving transistor, and the gate of the first transistor is connected to the third wiring; the second transistor One of the source/drain electrodes is connected to the other of the source/drain electrodes of the driving transistor, the other of the source/drain electrodes of the second transistor is connected to the gate electrode of the driving transistor, and the gate electrode of the second transistor is connected to the gate electrode of the driving transistor.
  • the pole is connected to the fourth wiring; wherein, before and after each working
  • the second trace before and after each working cycle of the writing transistor, respectively resets the voltage of one of the source/drain of the driving transistor through the first transistor.
  • the voltage reset duration of one of the source/drain electrodes of the driving transistor is the first reset duration; after each working cycle of the writing transistor, The voltage reset duration of one of the source/drain electrodes of the driving transistor is the second reset duration; and the first reset duration is equal to the second reset duration.
  • the pixel circuit further includes a third transistor and a light-emitting device, one of the source/drain of the third transistor is connected to the other of the source/drain of the driving transistor, and the gate of the third transistor
  • the anode of the light-emitting device is connected to the other of the source/drain electrodes of the third transistor, and the cathode of the light-emitting device is connected to the sixth wiring; wherein, when the third transistor is in the off state, the A transistor switches the switching state at least once before and after each working cycle.
  • the first trace is used to transmit the first control signal
  • the third trace is used to transmit the third control signal
  • the fifth trace is used to transmit the fifth control signal
  • each working cycle includes a first At least one pulse of the control signal, before the working period, the duration between the rising edge of the pulse of the third control signal and the rising edge of the pulse of the fifth control signal is a first voltage reset of one of the source/drain electrodes of the driving transistor Duration; after the working period, the duration between the pulse falling edge of the third control signal and the pulse falling edge of the fifth control signal is the second voltage reset duration of one of the source/drain electrodes of the driving transistor.
  • the duration between the falling edges of the two pulses is the second voltage reset duration; the falling edge of the second pulse lags behind the falling edge of the first pulse in timing.
  • the first voltage reset duration is equal to the second voltage reset duration.
  • the channel type of the first transistor is different from the channel type of the second transistor, and the third wiring and the fourth wiring are the same wiring.
  • both the first transistor and the second transistor are N-channel thin film transistors, and the third wiring is different from the fourth wiring; the first wiring is used to transmit the first control signal, and the third wiring Used to transmit the seventh control signal; before and after each working cycle, the seventh control signal has at least one forward pulse.
  • the seventh control signal before each working cycle, has a first forward pulse; after each working cycle, the seventh control signal has a second forward pulse; the first forward pulse The duration is equal to the duration of the second forward pulse.
  • the first transistor is turned on at least once before and after a working cycle.
  • the pixel circuit further includes a first initialization transistor, one of the source/drain of the first initialization transistor is connected to the anode of the light-emitting device, and the other of the source/drain of the first initialization transistor It is electrically connected to the first initialization line, and the gate of the first initialization transistor is connected to the fifth wiring or the seventh wiring.
  • the gate of the first initialization transistor is connected to the fifth wiring; or, the third transistor
  • the gate of the first initialization transistor is connected to the seventh line, and the seventh line is used to transmit the eighth control signal; the first line is used to transmit the first The first control signal lags behind the eighth control signal in time sequence.
  • the first wiring is used to transmit the first control signal
  • the fourth wiring is used to transmit the fourth control signal; each duty cycle of the fourth control signal corresponds to at least one duty cycle of the first control signal.
  • a first duty cycle of the first control signal and a duty cycle of the fourth control signal at least partially overlap in timing; and the fourth control signal does not include other Working period.
  • the start time of one working cycle of the fourth control signal is earlier than the start time of the first working cycle of the first control signal, and the end time of one working cycle of the fourth control signal is later than that of the first control signal. The end time of the signal's first duty cycle.
  • the first transistor is a P-channel thin film transistor; the third trace is used to transmit the tenth control signal.
  • the potential of the tenth control signal is high in turn. potential, low potential and high potential; after each working cycle of the writing transistor, the potential of the tenth control signal is high potential, low potential and high potential in sequence; and during each working cycle of the writing transistor, the potential of the tenth control signal The potential of the control signal remains high.
  • the time the tenth control signal is at a low level before each working cycle of the writing transistor is equal to the time the tenth control signal is at a low level after each working cycle of the writing transistor.
  • the second transistor is a P-channel thin film transistor; the first wiring is connected to the fourth wiring.
  • the pixel circuit further includes a second initialization transistor, one of the source/drain of the second initialization transistor is connected to the gate of the driving transistor, and the other of the source/drain of the second initialization transistor is connected to the gate of the driving transistor.
  • One is connected to the second initialization line, and the gate of the second initialization transistor T4 is connected to the gate of the first initialization transistor; wherein the channel type of the second initialization transistor is the same as the channel type of the first initialization transistor.
  • both the first initialization transistor and the second initialization transistor are dual-gate thin film transistors.
  • the present application provides a display panel, which includes the pixel circuit in at least one of the above embodiments, wherein the first wiring is used to transmit a first control signal, and the fourth wiring is used to transmit a fourth control signal. signal; as the refresh frequency of the display panel decreases, the frequency of the first control signal remains unchanged, and the frequency of the fourth control signal decreases.
  • the first transistor switches the switching state at least once before and after each working cycle of the writing transistor, so that the potential of one pole of the driving transistor can be reset each time the switching state is switched.
  • the potential of one pole of the driving transistor is stabilized, and the potential of the other pole of the driving transistor is linked to the potential of one pole of the driving transistor.
  • the potential of one pole of the driving transistor is stable, the potential of the other pole of the driving transistor is also As a result, the driving transistor can maintain the stability of the three-terminal voltage in both high and low frequency operating modes, thereby alleviating the technical problem of threshold voltage drift of the driving transistor in low frequency operating modes, and also alleviating the problems caused by regular changes in brightness. causing flickering.
  • the first transistor can not only reset one pole of the driving transistor in the non-light-emitting phase, but also control the light-emitting current in the light-emitting phase, multiplexing is achieved, which reduces the number of thin film transistors used in the pixel circuit.
  • the structure of the pixel circuit is simplified, which is beneficial to increasing the pixel density.
  • Figure 1 is a schematic diagram of the brightness difference caused by switching from high-frequency display to low-frequency display in the related art.
  • FIG. 2 is a first structural schematic diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 3 is a timing diagram of the pixel circuit shown in FIG. 2 .
  • FIG. 4 is another timing diagram of the pixel circuit shown in FIG. 2 .
  • FIG. 5 is a second structural schematic diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 6 is a timing diagram of the pixel circuit shown in FIG. 5 .
  • FIG. 7 is a third structural schematic diagram of a pixel circuit provided by an embodiment of the present application.
  • Figure 8 is a schematic diagram of the simulation waveforms of corresponding signals and node potentials in the pixel circuit shown in Figure 2.
  • FIG. 9 is a fourth structural schematic diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 10 is a timing diagram of the pixel circuit shown in FIG. 9 .
  • FIG. 11 is a fifth structural schematic diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 12 is a timing diagram of the pixel circuit shown in FIG. 11 .
  • Figure 1 is a schematic diagram of the brightness difference caused by switching from high-frequency display to low-frequency display in related technologies.
  • the ordinate represents brightness, in unit nit; the abscissa represents time (Time), in seconds (s).
  • 1 frame time at a 10Hz refresh rate is equivalent to 12 frame times at a 120Hz refresh rate.
  • the data signal can be written to the gate of the driving transistor in each frame; at a refresh frequency of 10Hz, the data signal is only written to the gate of the driving transistor within the first 120Hz frame time. The data signal is not written to the gate of the driving transistor during the subsequent 11 120Hz frames, but is written to the source or drain of the driving transistor.
  • the pixel circuit includes a driver The transistor T1, the writing transistor T2, the first transistor T5 and the second transistor T3.
  • One of the source/drain electrodes of the writing transistor T2 is connected to one of the source/drain electrodes of the driving transistor T1.
  • the writing transistor T2 The other of the source/drain electrodes is connected to the data line, the gate electrode of the writing transistor T2 is connected to the first wiring line; one of the source electrode/drain electrodes of the first transistor T5 is connected to the second wiring line, and the gate electrode of the writing transistor T2 is connected to the first wiring line.
  • the other of the source/drain of a transistor T5 is connected to one of the source/drain of the driving transistor T1, the gate of the first transistor T5 is connected to the third wiring; the source/drain of the second transistor T3 One of the drains is connected to the other of the source/drain of the driving transistor T1, the other of the source/drain of the second transistor T3 is connected to the gate of the driving transistor T1, and the gate of the second transistor T3
  • the pole is connected to the fourth wiring; wherein, before and after each working cycle of the writing transistor T2, the first transistor T5 switches the switching state at least once respectively.
  • the pixel circuit provided in this embodiment switches the switching state at least once before and after each working cycle of the writing transistor T2 by the first transistor T5, and can change the driving transistor T1 every time the switching state is switched.
  • Resetting the potential of one pole of the driving transistor T1 can stabilize the potential of one pole of the driving transistor T1 in the low-frequency operating mode, and the potential of the other pole of the driving transistor T1 is linked to the potential of one pole of the driving transistor T1.
  • the potential of one pole of the driving transistor T1 is stable, down, the potential of the other pole of the driving transistor T1 is also stabilized.
  • the driving transistor T1 can maintain the stability of the three-terminal voltage in both high and low frequency operating modes, thereby alleviating the threshold voltage drift of the driving transistor T1 in the low frequency operating mode.
  • the technical problem also alleviates the flickering phenomenon caused by regularly changing brightness.
  • each time the first transistor T5 switches the switch state it means that the first transistor T5 switches from on/on to off/off, or it can also switch from off/off to on/on, whichever it is. It means that the first transistor T5 is turned on or turned on before and after each working cycle, and the source or drain potential of the driving transistor T1 can be reset.
  • the second wiring can provide the required constant voltage signal or alternating direct current voltage signal, and is not limited to providing the positive power signal shown in Figure 2, Figure 5 and Figure 7 VDD. It can be understood that when the second trace provides the positive power signal VDD, the first transistor T5 can not only reset one pole of the driving transistor T1 in the non-light-emitting phase, but also control the light-emitting current in the light-emitting phase, that is, to achieve This eliminates multiplexing, which reduces the number of thin film transistors used in the pixel circuit, simplifies the structure of the pixel circuit, and helps increase the pixel density.
  • One electrode of the driving transistor T1 may be one of the source electrode and the drain electrode of the driving transistor T1
  • the other electrode of the driving transistor T1 may be the other one of the source electrode and the drain electrode of the driving transistor T1 .
  • the pixel circuit further includes a third transistor T6 and a light-emitting device D1.
  • One of the source/drain electrodes of the third transistor T6 is connected to the other of the source/drain electrodes of the driving transistor T1.
  • the gate of the third transistor T6 is connected to the fifth wiring; the anode of the light-emitting device D1 is connected to the other source/drain of the third transistor T6; and the cathode of the light-emitting device D1 is connected to the sixth wiring.
  • the third transistor T6 is used to allow the light-emitting current to flow through the light-emitting device D1 during the light-emitting phase, and to prevent the light-emitting current from flowing through the light-emitting device D1 during the non-light emitting phase.
  • the sixth trace can be used to transmit the negative power signal VSS.
  • the negative power signal VSS and the above-mentioned positive power signal VDD form a DC power supply to provide corresponding driving voltage or light-emitting current for the light-emitting device D1.
  • the above-mentioned light-emitting device D1 may be one of a mini-light-emitting diode, a micro-light-emitting diode, a quantum dot light-emitting diode or an organic light-emitting diode.
  • the pixel circuit further includes a first initialization transistor T7.
  • One of the source/drain electrodes of the first initialization transistor T7 is connected to the anode of the light-emitting device D1.
  • the first initialization transistor T7 The other of the source/drain electrodes is electrically connected to the first initialization line, and the gate electrode of the first initialization transistor T7 is connected to the fifth wiring.
  • the third transistor T6 and the first initialization transistor T7 need to be configured as thin film transistors of different channel types.
  • the third transistor T6 is a P-channel thin film transistor and the first initialization transistor T7 is an N-type thin film transistor.
  • channel thin film transistor, or the third transistor T6 may be an N-channel thin film transistor, and the first initialization transistor T7 may be a P-channel thin film transistor.
  • the first initialization transistor T7 can be used to initialize the anode potential of the light-emitting device D1 to a certain potential.
  • the first initialization line can be used to transmit the first initialization signal Vi_Ano.
  • the potential of the first initialization signal Vi_Ano is the above-mentioned potential.
  • a certain potential for example, it can be -2.5V.
  • the fifth control signal transmitted by the fifth line can have a higher frequency and can also have more pulses, which can not only meet the various needs of customers, but also improve the anode potential of the light-emitting device D1. Initialize the frequency to reduce or avoid the risk of light-emitting device D1 stealing light.
  • the fifth control signal may be the control signal EM, or may be other applicable control signals.
  • the pixel circuit further includes a second initialization transistor T4.
  • One of the source/drain electrodes of the second initialization transistor T4 is connected to the gate electrode of the driving transistor T1.
  • the second initialization transistor T4 The other one of the source/drain of T4 is electrically connected to the second initialization line, and the gate of the second initialization transistor T4 is connected to the eighth wiring.
  • the second initialization transistor T4 can be used to initialize the gate potential of the driving transistor T1.
  • the second initialization line can be used to transmit the second initialization signal Vi_G.
  • the potential of the second initialization signal Vi_G can be based on The pixel circuit needs to be set, for example, it can be -3.5V.
  • the eighth trace can be used to transmit a ninth control signal, which is ahead of the fourth control signal in timing.
  • the ninth control signal can be the n-1th level scanning signal to the n-th level.
  • One of the 8-level scanning signals may specifically be one of the n-1th level scanning signal to the n-8th level scanning signal having a forward pulse.
  • it can be the n-7th level scan signal Nscan(n-7) with forward pulses as shown in Figures 2 and 5, or it can be the n-5th level scan signal with forward pulses as shown in Figure 7 Nscan(n-5).
  • the fourth control signal may specifically be, but is not limited to, the n-th level scan signal Nscan(n) with a forward pulse, or may be other applicable control signals.
  • the pixel circuit further includes a storage capacitor Cst, one end of the storage capacitor Cst is connected to the gate of the driving transistor T1 , and the other end of the storage capacitor Cst is connected to the second wiring.
  • the storage capacitor Cst can provide a corresponding potential to the gate of the driving transistor T1 during the light-emitting phase to control the conduction degree of the driving transistor T1.
  • the pixel circuit also includes a voltage stabilizing capacitor Cboost.
  • One end of the voltage stabilizing capacitor Cboost is connected to the gate of the driving transistor T1, and the other end of the voltage stabilizing capacitor Cboost is connected to the first wiring. .
  • the voltage stabilizing capacitor Cboost can be used to stabilize the gate potential of the driving transistor T1.
  • any one of the driving transistor T1, the writing transistor T2, the first transistor T5, the second transistor T3, the third transistor T6, the first initialization transistor T7 and the second initialization transistor T4 may be, but is not limited to,
  • the N-channel thin film transistor may also be an indium gallium zinc oxide thin film transistor; it may also be a P-channel thin film transistor, and specifically it may be a low-temperature polysilicon thin film transistor.
  • the second transistor T3, the first initialization transistor T7, and The second initialization transistors T4 all use N-channel metal oxide thin film transistors, which can not only improve the dynamic performance of the pixel circuit to a certain extent, but also reduce the gate leakage current of the driving transistor T1 to a certain extent, so that the driving transistor T1 can The degree of conduction in the luminescence phase is more permanently stable.
  • the first trace is used to transmit a first control signal.
  • the first control signal may be, but is not limited to, an n-th level scanning signal Pscan(n) with a negative pulse, or may be other applicable control signals.
  • the third wiring is used to transmit a third control signal.
  • the third control signal may be, but is not limited to, an n-th level scanning signal Nscan(n) with a forward pulse, or may be other applicable control signals.
  • the fourth trace is used to transmit the fourth control signal.
  • the fifth trace is used to transmit the fifth control signal.
  • the data line is used to transmit the data signal Data.
  • Figure 3 is a timing diagram of the pixel circuit shown in Figure 2.
  • Figure 3 shows the first three 120Hz frames in time at the 10Hz refresh frequency, namely the 120Hz first frame, the 120Hz second frame, the 120Hz third frame, and The subsequent 4th frame of 120Hz to the 12th frame of 120Hz are not shown.
  • the third transistor T6 is turned off when the fifth control signal is at a high potential
  • the second transistor T3 is turned on when the fourth control signal is at a high potential.
  • One or two negative pulses of the first control signal can be turned on.
  • the data signal Data can be written to the gate of the driving transistor T1 through the writing transistor T2, the drain and source of the driving transistor T1, and the second transistor T3; however, in the subsequent 120Hz second
  • the fifth control signal and the first control signal still maintain the same waveform as in the first frame of 120Hz, while the fourth control signal has no pulse, that is, a jump as shown in Figure 3.
  • Frame (Nscan(n) Skip) maintains a constant low potential.
  • the second transistor T3 is in a closed state, and the data signal Data can only be written to the source and/or drain of the driving transistor T1, which will affect the driving
  • the voltage at the source or drain of the transistor T1 causes the threshold voltage of the driving transistor T1 to shift.
  • the potential of the data signal Data can be set to the potential of the positive power supply signal VDD, so that the source or drain potential of the driving transistor T1 is reset when it is reset. It is closer to the potential of the positive power supply signal VDD, which is beneficial to improving the reset speed.
  • the second wiring respectively resets the voltage of one of the source/drain electrodes of the driving transistor T1 through the first transistor T5.
  • one working cycle of the write transistor T2 corresponds to one working cycle of the first control signal
  • one working cycle of the first control signal may include one or more negative pulses, for example, It can be two negative pulses, three negative pulses, four negative pulses or five negative pulses, etc.
  • Each negative pulse means a writing of the data signal Data. Therefore, the number of negative pulses should be based on the resolution. Reasonable setting, too much will take up too much writing time, thus reducing the lighting time.
  • the channel type of the first transistor T5 is different from the channel type of the second transistor T3, and the third wiring and the fourth wiring are the same wiring. That is to say, at this time, the third control signal Same as the fourth control signal.
  • the third control signal Same as the fourth control signal.
  • the third control signal/fourth control signal switches from a low potential to a high potential, then the first transistor T6 T5 switches from the open state to the closed state to realize a switching state, that is, the source or drain potential of the driving transistor T1 is reset by the positive power supply signal VDD, and the second transistor T3 switches from the closed state to the open state to obtain data.
  • the signal Data is transmitted to the gate of the driving transistor T1 to provide a corresponding path.
  • the third transistor T6 is in a closed state, and the third control signal/fourth control signal switches from a high potential to a low potential, then the first The switching of the transistor T5 from the off state to the on state realizes a switching state, that is, the potential of the source or drain of the driving transistor T1 is reset by the positive power supply signal VDD, and the second transistor T3 switches from the on state to the off state. Keep the gate of the driving transistor T1 from leaking current, and realize the preset brightness display of one frame.
  • the voltage reset duration of one of the source/drain electrodes of the driving transistor T1 is the first reset duration; before each working cycle of the writing transistor T2 After the period, the voltage reset duration of one of the source/drain electrodes of the driving transistor T1 is the second reset duration; and the first reset duration is equal to the second reset duration.
  • the first reset duration is equal to the second reset duration, which is beneficial to balancing the electrical stress on the driving transistor T1, thereby alleviating or improving the threshold voltage drift of the driving transistor T1.
  • each working cycle includes at least one pulse of the first control signal.
  • the pulse rising edge of the third control signal and the pulse rising edge of the fifth control signal are The duration between is the first voltage reset duration of one of the source/drain electrodes of the driving transistor T1; after the working period, the duration between the pulse falling edge of the third control signal and the pulse falling edge of the fifth control signal is A second voltage reset duration of one of the source/drain electrodes of the drive transistor T1.
  • the reset duration is jointly determined through the third control signal and the fifth control signal.
  • the duration between the first pulse falling edge of the third control signal and the first pulse falling edge of the fifth control signal, the second pulse falling edge of the third control signal and the third pulse falling edge of the fifth control signal are The duration between the falling edges of the two pulses is the second voltage reset duration; the falling edge of the second pulse lags behind the falling edge of the first pulse in timing.
  • step voltage that lasts for a certain period of time between the falling edge of the first pulse and the falling edge of the second pulse of the same control signal.
  • This step voltage can only turn on the corresponding transistor for an instant, and cannot turn on the corresponding transistor at this step voltage. The duration during which one turns on the corresponding transistor.
  • the first voltage reset duration is equal to the second voltage reset duration, which is beneficial to balancing the electrical stress on the driving transistor T1, thereby alleviating or improving the threshold voltage drift of the driving transistor T1.
  • Figure 5 is a second structural schematic diagram of a pixel circuit provided by an embodiment of the present application.
  • the channel type of the first transistor T5 is modified to an N-channel type.
  • the third transistor T5 The third control signal transmitted by the line is also constructed as a seventh control signal that is used alone. The construction of the seventh control signal not only needs to consider resetting the source or drain of the driving transistor T1, but also needs to consider providing a corresponding response to the light-emitting current. transmission path.
  • the seventh control signal may be, but is not limited to, the control signal EM2 shown in FIG. 5 and FIG. 6 , or may be other applicable control signals.
  • Figure 6 is a timing diagram of the pixel circuit shown in Figure 5.
  • the waveforms of the first control signal, the fourth control signal, and the fifth control signal have not changed, but the seventh control signal is at a low potential.
  • the seventh control signal is at a low potential.
  • two forward pulses are constructed, and each forward pulse can independently control the turn-on time of the first transistor T5, that is, the reset time of the source or drain of the driving transistor T1. This can make the reset time of the source or drain of the driving transistor T1 more flexible and accurate.
  • the fifth control signal may control the signal EM1.
  • the first transistor T5 and the second transistor T3 are both N-channel thin film transistors, and the third wiring is different from the fourth wiring, and are respectively used to transmit different Control signals, the first wiring is used to transmit the first control signal, and the third wiring is used to transmit the seventh control signal. Before and after each working cycle, the seventh control signal has at least one positive pulse respectively.
  • this embodiment can reset the source or drain of the driving transistor T1 before and after each working cycle, and the duration of each forward pulse can also be independently modulated, and can be the same or different.
  • the seventh control signal before each working cycle, has a first forward pulse; after each working cycle, the seventh control signal has a second forward pulse. ;
  • the duration of the first forward pulse is equal to the duration of the second forward pulse.
  • this implementation can be used as a preferred solution, which not only reduces the number of pulses of the seventh control signal, but also can flexibly and accurately control the reset time of the source or drain of the driving transistor T1.
  • the first transistor T5 is turned on at least once before and after a working cycle.
  • the third transistor T6 is in a continuous off state.
  • the pixel circuit is in the non-light-emitting stage and can be the source of the driving transistor T1.
  • a separate period is provided for the pole/drain reset time.
  • the first transistor T5 does not turn on once to reset the source/drain of the driving transistor T1, and each turn-on time of the first transistor T5 is the reset time of the source/drain of the driving transistor T1. reset time.
  • each duty cycle of the fourth control signal corresponds to at least one duty cycle of the first control signal.
  • the first control signal may have one or more working periods
  • the fourth control signal may only have one working period
  • one working period of the fourth control signal is only the same as that of the first control signal.
  • the on state of the second transistor T3 is synchronized with the on state of the writing transistor T2 to provide a writing path of the data signal Data to the gate of the driving transistor T1.
  • a first duty cycle of the first control signal and a duty cycle of the fourth control signal at least partially overlap in timing; and the fourth control signal does not include other duty cycles in a frame.
  • the start time of one working cycle of the fourth control signal is earlier than the start time of the first working cycle of the first control signal, and the end time of one working cycle of the fourth control signal is later than that of the first control signal.
  • the conduction time of the second transistor T3 can cover the conduction time of the writing transistor T2, which can further ensure that the data signal Data is written to the gate of the driving transistor T1 smoothly and without loss.
  • FIG. 7 is a third structural schematic diagram of a pixel circuit provided by an embodiment of the present application.
  • the first initialization transistor T7 is configured as a P-channel low-temperature polysilicon thin film transistor.
  • the dynamic performance of the pixel circuit is further improved, and the layout design of each thin film transistor in the pixel circuit is also more optimized and highly practical.
  • the gate of the first initialization transistor T7 is connected to the seventh wiring, and the seventh wiring is used to transmit the eighth control signal.
  • the first control signal and the eighth control signal can be scan signals with negative pulses output by the same gate drive circuit. It only needs to be ensured that the first control signal lags behind the eighth control signal in timing.
  • the control signal and the eighth control signal can also be selected as any scanning signal with negative pulses.
  • the eighth control signal may be the n-1th level scan signal Pscan(n-1) with negative pulses as shown in FIG. 7 .
  • Figure 8 is a schematic diagram of the simulation waveform of the corresponding signal and node potential in the pixel circuit shown in Figure 2, where VQ represents the waveform change of the potential at point Q, VA represents the waveform change of the potential at point A, VB represents the waveform change of the potential at point B, VC Represents the waveform change of potential at point C.
  • the first control signal in this simulation waveform diagram only shows one pulse. It can be understood that whether the first control signal has one or more pulses, when the first control signal Before and after a working cycle, the potential VA of point A remains stable. Since the potential of point B is linked to the potential of point A, the potential VB of point B also remains stable.
  • the source and drain potentials of the driving transistor T1 are in the data
  • the signal Data remains stable before and after it is written to the gate of the drive transistor T1. That is, the three-terminal voltage of the drive transistor T1 is stabilized before and after the data signal Data is written to the gate of the drive transistor T1, effectively easing the problem of driving in low-frequency operating mode.
  • the threshold voltage of transistor T1 drifts.
  • FIG. 9 is a fourth structural schematic diagram of a pixel circuit provided by an embodiment of the present application.
  • the first transistor T5 is configured as a P-channel thin film transistor, and may specifically be a low-temperature polysilicon thin film transistor.
  • the first transistor T5 is a P-channel thin film transistor; the third wiring is used to transmit the tenth control signal.
  • the potential of the tenth control signal is high potential, low potential and high potential in sequence; after each working cycle of writing transistor T2, the potential of the tenth control signal is high potential, low potential and high potential in sequence; and after In each working cycle of the writing transistor T2, the potential of the tenth control signal remains high.
  • the fifth control signal may be the control signal EM1.
  • the first transistor T5 when the tenth control signal is at a low level, the first transistor T5 is in an open state or a conductive state. At this time, the control can also be implemented before and after each working cycle of the writing transistor T2.
  • One of the source/drain electrodes of the driving transistor T1 is reset to maintain the potential stability of one of the source/drain electrodes of the driving transistor T1 before and after each working cycle of the writing transistor T2, thereby maintaining The potential stability of the other source/drain of the driving transistor T1 in the linkage relationship can maintain the stability of the three-terminal voltage of the driving transistor T1 before and after each working cycle of the writing transistor T2 to reduce its The degree of drift in the threshold voltage.
  • the time the tenth control signal is at a low level before each working cycle of the writing transistor T2 is equal to the tenth time after each working cycle of the writing transistor T2. The time the control signal is low.
  • this embodiment is beneficial to balancing the electrical stress experienced by the driving transistor T1, thereby further alleviating or improving the threshold voltage drift of the driving transistor T1.
  • the tenth control signal may be the signal EM2 shown in FIG. 10 and FIG. 12 .
  • the second transistor T3 is a P-channel thin film transistor; the first wiring is connected to the fourth wiring.
  • the first wiring and the fourth wiring can be configured as the same wiring, which can reduce the number of wirings required for the pixel circuit, thereby improving the aperture ratio of the pixel.
  • the pixel circuit further includes a second initialization transistor T4.
  • One of the source/drain electrodes of the second initialization transistor T4 is connected to the gate electrode of the driving transistor T1.
  • the source/drain electrode of the second initialization transistor T4 is connected to the gate electrode of the driving transistor T1.
  • the other one of the terminals is connected to the second initialization line, and the gate of the second initialization transistor T4 is connected to the gate of the first initialization transistor T7; wherein, the channel type of the second initialization transistor T4 is the same as the channel type of the first initialization transistor T7. Tao type is the same.
  • the gate electrode of the first initialization transistor T7 and the gate electrode of the second initialization transistor T4 can share the same wiring, which can reduce the number of wirings required for the pixel circuit, thereby improving the efficiency of the pixel. Opening rate.
  • both the first initialization transistor T7 and the second initialization transistor T4 are dual-gate thin film transistors, and specifically may also be low-temperature polysilicon thin film transistors.
  • first initialization transistor T7 and the second initialization transistor T4 are configured as double-gate low-temperature polysilicon thin film transistors, the process can be simplified and the cost can be reduced.
  • the signal Pscan(n) and the signal Pscan(n-1) may have but are not limited to only one negative pulse, or they may With multiple negative pulses.
  • this embodiment provides a display panel, which includes the pixel circuit in at least one of the above embodiments.
  • the first transistor T5 switches the switching state at least once before and after each working cycle of the writing transistor T2, so that a switch state of the driving transistor T1 can be changed each time the switching state is switched.
  • Resetting the potential of one pole of the driving transistor T1 can stabilize the potential of one pole of the driving transistor T1 in the low-frequency operating mode, and the potential of the other pole of the driving transistor T1 is linked to the potential of one pole of the driving transistor T1.
  • the potential of one pole of the driving transistor T1 is stable, down, the potential of the other pole of the driving transistor T1 is also stabilized.
  • the driving transistor T1 can maintain the stability of the three-terminal voltage in both high and low frequency operating modes, thereby alleviating the threshold voltage drift of the driving transistor T1 in the low frequency operating mode.
  • the technical problem also alleviates the flickering phenomenon caused by regularly changing brightness.
  • the first transistor T5 can not only reset one pole of the driving transistor T1 in the non-light-emitting phase, but also control the light-emitting current in the light-emitting phase, multiplexing is achieved, which reduces the use of thin film transistors in the pixel circuit. quantity, simplifying the structure of the pixel circuit and helping to increase the pixel density.
  • the frequency of the first control signal remains unchanged and the frequency of the fourth control signal decreases.
  • the low frequency in this application can be a refresh frequency below 30Hz, for example, 20Hz, 10Hz, 1Hz, 0.5Hz... and so on.
  • the high frequency in this application can be a refresh frequency above 30Hz, for example, 60Hz, 90Hz, 120Hz, 240Hz...and so on.

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Abstract

一种像素电路及显示面板，像素电路包括驱动晶体管(T1)、写入晶体管(T2)、第一晶体管(T5)以及第二晶体管(T3)，通过第一晶体管(T5)在写入晶体管(T2)的每个工作周期前后分别切换至少一次开关状态，能够稳定驱动晶体管(T1)的一极电位，而驱动晶体管(T1)的另一极电位与驱动晶体管(T1)的一极电位联动，驱动晶体管(T1)的另一极电位也随之稳定。

Description

像素电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种像素电路及显示面板。
 背景技术
像素电路处于低频工作模式下且在一帧时间中，数据信号在对应晶体管的第一个工作周期可以写入到驱动晶体管的栅极，而在同一帧中后续的其他工作周期内数据信号仅可以写入到驱动晶体管除栅极外的一个极或者两个极，数据信号如此持续地写入，驱动晶体管的三端电压会发生变化，受迟滞特性的影响，驱动晶体管的阈值电压（Vth）会发生漂移（Shift），最终表现为第一个工作周期内的发光亮度与同一帧中后续的其它工作周期内的发光亮度不一致，这种亮度差异会导致亮度出现规律变化，进而呈现出严重的闪烁（Flicker）。
 技术问题
本申请提供一种像素电路及显示面板，以缓解低频工作模式下驱动晶体管的阈值电压漂移的技术问题。
 技术解决方案
第一方面，本申请提供一种像素电路，该像素电路包括驱动晶体管、写入晶体管、第一晶体管以及第二晶体管，写入晶体管的源极/漏极中的一个与驱动晶体管的源极/漏极中的一个连接，写入晶体管的源极/漏极中的另一个与数据线连接，写入晶体管的栅极与第一走线连接；第一晶体管的源极/漏极中的一个与第二走线连接，第一晶体管的源极/漏极中的另一个与驱动晶体管的源极/漏极中的一个连接，第一晶体管的栅极与第三走线连接；第二晶体管的源极/漏极中的一个与驱动晶体管的源极/漏极中的另一个连接，第二晶体管的源极/漏极中的另一个与驱动晶体管的栅极连接，第二晶体管的栅极与第四走线连接；其中，在写入晶体管的每个工作周期前后，第一晶体管分别切换至少一次开关状态。
在其中一些实施方式中，在写入晶体管的每个工作周期前后，第二走线通过第一晶体管分别复位驱动晶体管的源极/漏极中的一个的电压。
在其中一些实施方式中，在写入晶体管的每个工作周期之前，驱动晶体管的源极/漏极中的一个的电压复位时长为第一复位时长；在写入晶体管的每个工作周期之后，驱动晶体管的源极/漏极中的一个的电压复位时长为第二复位时长；且第一复位时长等于第二复位时长。
在其中一些实施方式中，像素电路还包括第三晶体管和发光器件，第三晶体管的源极/漏极中的一个与驱动晶体管的源极/漏极中的另一个连接，第三晶体管的栅极与第五走线连接；发光器件的阳极与第三晶体管的源极/漏极中的另一个连接，发光器件的阴极与第六走线连接；其中，第三晶体管处于关闭状态时，第一晶体管在每个工作周期前后分别切换至少一次开关状态。
在其中一些实施方式中，第一走线用于传输第一控制信号，第三走线用于传输第三控制信号，第五走线用于传输第五控制信号；每个工作周期包括第一控制信号的至少一个脉冲，在工作周期之前，第三控制信号的脉冲上升沿与第五控制信号的脉冲上升沿之间的时长为驱动晶体管的源极/漏极中的一个的第一电压复位时长；在工作周期之后，第三控制信号的脉冲下降沿与第五控制信号的脉冲下降沿之间的时长为驱动晶体管的源极/漏极中的一个的第二电压复位时长。
在其中一些实施方式中，第三控制信号的第一脉冲下降沿与第五控制信号的第一脉冲下降沿之间的时长、第三控制信号的第二脉冲下降沿与第五控制信号的第二脉冲下降沿之间的时长均为第二电压复位时长；其中，第二脉冲下降沿在时序上滞后于第一脉冲下降沿。
在其中一些实施方式中，第一电压复位时长等于第二电压复位时长。
在其中一些实施方式中，第一晶体管的沟道类型与第二晶体管的沟道类型不同，第三走线、第四走线为同一走线。
在其中一些实施方式中，第一晶体管、第二晶体管均为N沟道型薄膜晶体管，第三走线异于第四走线；第一走线用于传输第一控制信号，第三走线用于传输第七控制信号；在每个工作周期前后，第七控制信号分别具有至少一个正向脉冲。
在其中一些实施方式中，在每个工作周期之前，第七控制信号具有一个第一正向脉冲；在每个工作周期之后，第七控制信号具有一个第二正向脉冲；第一正向脉冲的持续时间等于第二正向脉冲的持续时间。
在其中一些实施方式中，在第三晶体管处于一个持续的关闭状态期间，第一晶体管在一个工作周期前后各打开至少一次。
在其中一些实施方式中，像素电路还包括第一初始化晶体管，第一初始化晶体管的源极/漏极中的一个与发光器件的阳极连接，第一初始化晶体管的源极/漏极中的另一个与第一初始线电性连接，第一初始化晶体管的栅极与第五走线或者第七走线连接。
在其中一些实施方式中，第三晶体管为P沟道型薄膜晶体管且第一初始化晶体管为N沟道型薄膜晶体管时，第一初始化晶体管的栅极与第五走线连接；或者，第三晶体管、第一初始化晶体管均为P沟道型薄膜晶体管时，第一初始化晶体管的栅极与第七走线连接，第七走线用于传输第八控制信号；第一走线用于传输第一控制信号，第一控制信号在时序上滞后于第八控制信号。
在其中一些实施方式中，第一走线用于传输第一控制信号，第四走线用于传输第四控制信号；第四控制信号的每个工作周期对应第一控制信号的至少一个工作周期。
在其中一些实施方式中，在一帧中，第一控制信号的第一个工作周期与第四控制信号的一个工作周期在时序上至少部分重叠；且第四控制信号在一帧中不包括其他工作周期。
在其中一些实施方式中，第四控制信号的一个工作周期的开始时间早于第一控制信号的第一个工作周期的开始时间，第四控制信号的一个工作周期的结束时间晚于第一控制信号的第一个工作周期的结束时间。
在其中一些实施方式中，第一晶体管为P沟道型薄膜晶体管；第三走线用于传输第十控制信号，在写入晶体管的每个工作周期之前，第十控制信号的电位依次为高电位、低电位以及高电位；在写入晶体管的每个工作周期之后，第十控制信号的电位依次为高电位、低电位以及高电位；且在写入晶体管的每个工作周期中，第十控制信号的电位保持为高电位。
在其中一些实施方式中，在写入晶体管的每个工作周期之前第十控制信号处于低电位的时间等于在写入晶体管的每个工作周期之后第十控制信号处于低电位的时间。
在其中一些实施方式中，第二晶体管为P沟道型薄膜晶体管；第一走线与第四走线连接。
在其中一些实施方式中，像素电路还包括第二初始化晶体管，第二初始化晶体管的源极/漏极中的一个与驱动晶体管的栅极连接，第二初始化晶体管的源极/漏极中的另一个与第二初始线连接，第二初始化晶体管T4的栅极与第一初始化晶体管的栅极连接；其中，第二初始化晶体管的沟道类型与第一初始化晶体管的沟道类型相同。
在其中一些实施方式中，第一初始化晶体管、第二初始化晶体管均为双栅型薄膜晶体管。
第二方面，本申请提供一种显示面板，该显示面板包括上述至少一实施方式中的像素电路，其中，第一走线用于传输第一控制信号，第四走线用于传输第四控制信号；随着显示面板的刷新频率的降低，第一控制信号的频率保持不变，第四控制信号的频率减小。
 有益效果
本申请提供的像素电路及显示面板，通过第一晶体管在写入晶体管的每个工作周期前后分别切换至少一次开关状态，可以在每次切换开关状态时对驱动晶体管的一极电位进行复位，能够在低频工作模式下稳定驱动晶体管的一极电位，而驱动晶体管的另一极电位与驱动晶体管的一极电位联动，在驱动晶体管的一极电位稳定的情况下，驱动晶体管的另一极电位也随之稳定，如此，驱动晶体管在高低频工作模式下均可以保持三端电压的稳定性，进而缓解了低频工作模式下驱动晶体管的阈值电压漂移的技术问题，也缓解了规律性变化的亮度所导致的闪烁现象。
又，由于第一晶体管不仅可以在非发光阶段中对驱动晶体管的一极进行复位，还可以在发光阶段中控制发光电流，即实现了复用，这减少了像素电路中薄膜晶体管的使用数量，简化了像素电路的结构，有利于提高像素密度。
 附图说明
图1为相关技术中高频显示切换至低频显示导致的亮度差异示意图。
图2为本申请实施例提供的像素电路的第一种结构示意图。
图3为图2所示像素电路的一种时序示意图。
图4为图2所示像素电路的另一种时序示意图。
图5为本申请实施例提供的像素电路的第二种结构示意图。
图6为图5所示像素电路的时序示意图。
图7为本申请实施例提供的像素电路的第三种结构示意图。
图8为图2所示像素电路中对应信号、节点电位的仿真波形示意图。
图9为本申请实施例提供的像素电路的第四种结构示意图。
图10为图9所示像素电路的时序示意图。
图11为本申请实施例提供的像素电路的第五种结构示意图。
图12为图11所示像素电路的时序示意图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
图1为相关技术中高频显示切换至低频显示导致的亮度差异示意图，纵坐标表示亮度，单位为nit；横坐标表示时间（Time），单位秒（s）。在对应的分辨率下，10Hz刷新频率下的1帧时间与120Hz刷新频率下的12帧时间相当。然而，120Hz刷新频率下每帧数据信号均可以写入到驱动晶体管的栅极；10Hz刷新频率下仅在第一个120Hz帧时间内写入数据信号至驱动晶体管的栅极，在10Hz刷新频率下的后续11个120Hz帧时间内数据信号并未写入至驱动晶体管的栅极，而是写入到了驱动晶体管的源极或者漏极，如此导致了如图1中虚线框所示的10Hz刷新频率下第一个120Hz帧时间内的亮度与后续的其他11个120Hz帧时间内的亮度存在差异，这种亮度差异会导致亮度出现规律变化，进而呈现出严重的闪烁。
有鉴于上述提及的低频工作模式下驱动晶体管T1的阈值电压漂移的技术问题，本实施例提供了一种像素电路，请参阅图2至图8，如图2所示，该像素电路包括驱动晶体管T1、写入晶体管T2、第一晶体管T5以及第二晶体管T3，写入晶体管T2的源极/漏极中的一个与驱动晶体管T1的源极/漏极中的一个连接，写入晶体管T2的源极/漏极中的另一个与数据线连接，写入晶体管T2的栅极与第一走线连接；第一晶体管T5的源极/漏极中的一个与第二走线连接，第一晶体管T5的源极/漏极中的另一个与驱动晶体管T1的源极/漏极中的一个连接，第一晶体管T5的栅极与第三走线连接；第二晶体管T3的源极/漏极中的一个与驱动晶体管T1的源极/漏极中的另一个连接，第二晶体管T3的源极/漏极中的另一个与驱动晶体管T1的栅极连接，第二晶体管T3的栅极与第四走线连接；其中，在写入晶体管T2的每个工作周期前后，第一晶体管T5分别切换至少一次开关状态。
可以理解的是，本实施例提供的像素电路，通过第一晶体管T5在写入晶体管T2的每个工作周期前后分别切换至少一次开关状态，可以在每次切换开关状态时对驱动晶体管T1的一极电位进行复位，能够在低频工作模式下稳定驱动晶体管T1的一极电位，而驱动晶体管T1的另一极电位与驱动晶体管T1的一极电位联动，在驱动晶体管T1的一极电位稳定的情况下，驱动晶体管T1的另一极电位也随之稳定，如此，驱动晶体管T1在高低频工作模式下均可以保持三端电压的稳定性，进而缓解了低频工作模式下驱动晶体管T1的阈值电压漂移的技术问题，也缓解了规律性变化的亮度所导致的闪烁现象。
其中，第一晶体管T5每次切换开关状态意味着第一晶体管T5由导通/打开切换至截止/关闭，或者，也可以是由截止/关闭切换至导通/打开，无论是哪种均可以说明第一晶体管T5在每个工作周期前后均导通过或者打开过，能够实现驱动晶体管T1的源极或者漏极电位的复位。
需要进行说明的是，在本实施例中第二走线可以提供所需的恒压信号或者交变直流电压信号，并不局限于提供图2、图5以及图7中所示的电源正信号VDD。可以理解的是，当第二走线提供电源正信号VDD时，第一晶体管T5不仅可以在非发光阶段中对驱动晶体管T1的一极进行复位，还可以在发光阶段中控制发光电流，即实现了复用，这减少了像素电路中薄膜晶体管的使用数量，简化了像素电路的结构，有利于提高像素密度。其中，驱动晶体管T1的一极可以为驱动晶体管T1的源极/漏极中的一个，驱动晶体管T1的另一极可以为驱动晶体管T1的源极/漏极中的另一个。
在其中一个实施例中，像素电路还包括第三晶体管T6和发光器件D1，第三晶体管T6的源极/漏极中的一个与驱动晶体管T1的源极/漏极中的另一个连接，第三晶体管T6的栅极与第五走线连接；发光器件D1的阳极与第三晶体管T6的源极/漏极中的另一个连接，发光器件D1的阴极与第六走线连接。
需要进行说明的是，第三晶体管T6用于在发光阶段中允许发光电流流经发光器件D1，在非发光阶段中阻止发光电流流经发光器件D1。
其中，第六走线可以用于传输电源负信号VSS，该电源负信号VSS与上述的电源正信号VDD构成为一直流电源，为发光器件D1提供对应的驱动电压或者发光电流。
其中，上述的发光器件D1可以为迷你发光二极管、微发光二极管、量子点发光二极管或者有机发光二极管中的一种。
在其中一个实施例中，如图2所示，像素电路还包括第一初始化晶体管T7，第一初始化晶体管T7的源极/漏极中的一个与发光器件D1的阳极连接，第一初始化晶体管T7的源极/漏极中的另一个与第一初始线电性连接，第一初始化晶体管T7的栅极与第五走线连接。
可以理解的是，在本实施例中，由于第一初始化晶体管T7的栅极、第三晶体管T6的栅极共用了同一第五走线，可以减少像素电路所需的走线数量。在此情况下，第三晶体管T6、第一初始化晶体管T7需要设置为不同沟道类型的薄膜晶体管，例如本实施例中第三晶体管T6为P沟道型薄膜晶体管、第一初始化晶体管T7为N沟道型薄膜晶体管，或者，也可以设置第三晶体管T6为N沟道型薄膜晶体管、第一初始化晶体管T7为P沟道型薄膜晶体管。
其中，第一初始化晶体管T7可以用于初始化发光器件D1的阳极电位为一定电位，此时，第一初始线可以用于传输第一初始化信号Vi_Ano，该第一初始化信号Vi_Ano的电位即为上述的一定电位，例如可以为-2.5V。
需要进行说明的是，第五走线传输的第五控制信号可以具有更高的频率，也可以具有更多的脉冲，不仅可以满足客户的多方面需求，还可以提高发光器件D1的阳极电位的初始化频率，减少或者避免发光器件D1偷亮的风险。
其中，在图2、图7所示的像素电路中，第五控制信号可以为控制信号EM，也可以为适用的其他控制信号。
在其中一个实施例中，如图2所示，像素电路还包括第二初始化晶体管T4，第二初始化晶体管T4的源极/漏极中的一个与驱动晶体管T1的栅极连接，第二初始化晶体管T4的源极/漏极中的另一个与第二初始线电性连接，第二初始化晶体管T4的栅极与第八走线连接。
需要进行说明的是，第二初始化晶体管T4可以用于初始化驱动晶体管T1的栅极电位，此时，第二初始线可以用于传输第二初始化信号Vi_G，该第二初始化信号Vi_G的电位可以根据像素电路的需要进行设定，例如可以为-3.5V。
其中，第八走线可以用于传输第九控制信号，该第九控制信号在时序上超前于第四控制信号，例如，该第九控制信号可以为第n-1级扫描信号至第n-8级扫描信号中的一个，具体可以为具有正向脉冲的第n-1级扫描信号至第n-8级扫描信号中的一个。优选地，可以为图2、图5所示具有正向脉冲的第n-7级扫描信号Nscan（n-7），也可以为图7所示具有正向脉冲的第n-5级扫描信号Nscan（n-5）。
其中，第四控制信号具体可以但不限于为具有正向脉冲的第n级扫描信号Nscan（n），也可以是适用的其他控制信号。
在其中一个实施例中，如图2所示，像素电路还包括存储电容Cst，存储电容Cst的一端与驱动晶体管T1的栅极连接，存储电容Cst的另一端与第二走线连接。
需要进行说明的是，该存储电容Cst可以在发光阶段中为驱动晶体管T1的栅极提供对应的电位，以控制驱动晶体管T1的导通程度。
在其中一个实施例中，如图2所示，像素电路还包括稳压电容Cboost，稳压电容Cboost的一端与驱动晶体管T1的栅极连接，稳压电容Cboost的另一端与第一走线连接。
需要进行说明的是，该稳压电容Cboost可以用于稳定驱动晶体管T1的栅极电位。
需要进行说明的是，驱动晶体管T1、写入晶体管T2、第一晶体管T5、第二晶体管T3、第三晶体管T6、第一初始化晶体管T7以及第二初始化晶体管T4中的任一个可以但不限于为N沟道型薄膜晶体管，具体还可以为铟镓锌氧化物薄膜晶体管；还可以为P沟道型薄膜晶体管，具体还可以为低温多晶硅薄膜晶体管。优选地，图2所示像素电路中驱动晶体管T1、写入晶体管T2、第一晶体管T5、第三晶体管T6均采用P沟道型低温多晶硅薄膜晶体管，第二晶体管T3、第一初始化晶体管T7以及第二初始化晶体管T4均采用N沟道型金属氧化物薄膜晶体管，如此不仅可以一定程度上提高像素电路的动态性能，同时可以一定程度上降低驱动晶体管T1的栅极漏电流，使得驱动晶体管T1在发光阶段中的导通程度更为持久地稳定。
第一走线用于传输第一控制信号，第一控制信号可以但不限于为具有负脉冲的第n级扫描信号Pscan（n），也可以为适用的其他控制信号。第三走线用于传输第三控制信号，第三控制信号具体可以但不限于为具有正向脉冲的第n级扫描信号Nscan（n），也可以是适用的其他控制信号。第四走线用于传输第四控制信号。第五走线用于传输第五控制信号。数据线用于传输数据信号Data。
图3为图2所示像素电路的一种时序示意图，图3示出了10Hz刷新频率下在时间上的前三个120Hz帧即120Hz第1帧、120Hz第2帧、120Hz第3帧、以及后续未示出的120Hz第4帧至120Hz第12帧。其中，在120Hz第1帧中，第五控制信号处于高电位时第三晶体管T6关闭，第四控制信号处于高电位时第二晶体管T3打开，第一控制信号的一个或者两个负脉冲可以打开写入晶体管T2，此时，数据信号Data可以经写入晶体管T2、驱动晶体管T1的漏极、源极以及第二晶体管T3写入至驱动晶体管T1的栅极；然而，在后续的120Hz第2帧至120Hz第12帧的任一个中时，第五控制信号、第一控制信号仍然保持着与120Hz第1帧中的波形进行，而第四控制信号没有了脉冲即如图3所示的跳帧（Nscan（n） Skip），保持恒定的低电位，此时第二晶体管T3处于关闭状态，数据信号Data只可以写入到驱动晶体管T1的源极和/或漏极，这会影响到驱动晶体管T1的源极或者漏极的电压，进而致使驱动晶体管T1的阈值电压发生漂移。
需要进行说明的是，在后续的120Hz第2帧至120Hz第12帧中，数据信号Data的电位可以设置为电源正信号VDD的电位，这样驱动晶体管T1的源极或者漏极电位在被复位时更接近电源正信号VDD的电位，有利于提高复位速度。
在其中一个实施例中，在写入晶体管T2的每个工作周期前后，第二走线通过第一晶体管T5分别复位驱动晶体管T1的源极/漏极中的一个的电压。
需要进行说明的是，如图4所示，写入晶体管T2的一个工作周期对应着第一控制信号的一个工作周期，第一控制信号的一个工作周期可以包括一个或者多个负脉冲，例如，可以为两个负脉冲、三个负脉冲、四个负脉冲或者五个负脉冲等等，每个负脉冲即意味着一次数据信号Data的写入，因此，负脉冲的数量应该根据分辨率进行合理设定，过多的话会占用过多的写入时间，从而减少了发光时间。
在本实施例中，第一晶体管T5的沟道类型与第二晶体管T3的沟道类型不同，第三走线、第四走线为同一走线，也就是说，此时，第三控制信号与第四控制信号相同。第五控制信号处于高电位时第三晶体管T6处于关闭状态，第一控制信号的工作周期即负脉冲未到来之前，第三控制信号/第四控制信号由低电位切换至高电位，则第一晶体管T5由打开状态切换为关闭状态实现了一次开关状态的切换，即驱动晶体管T1的源极或者漏极的电位被电源正信号VDD进行了复位，第二晶体管T3由关闭状态切换为打开状态以为数据信号Data传输至驱动晶体管T1的栅极提供对应的路径。第一控制信号的工作周期即负脉冲到来之后，第五控制信号仍然处于高电位时第三晶体管T6处于关闭状态，第三控制信号/第四控制信号由高电位切换至低电位，则第一晶体管T5由关闭状态切换为打开状态实现了一次开关状态的切换，即驱动晶体管T1的源极或者漏极的电位被电源正信号VDD进行了复位，第二晶体管T3由打开状态切换为关闭状态以保持驱动晶体管T1的栅极不发生电流泄露，实现一帧的预设亮度显示。
在其中一个实施例中，在写入晶体管T2的每个工作周期之前，驱动晶体管T1的源极/漏极中的一个的电压复位时长为第一复位时长；在写入晶体管T2的每个工作周期之后，驱动晶体管T1的源极/漏极中的一个的电压复位时长为第二复位时长；且第一复位时长等于第二复位时长。
需要进行说明的是，第一复位时长等于第二复位时长，有利于平衡驱动晶体管T1所受到的电应力，进而可以缓解或者改善驱动晶体管T1的阈值电压漂移程度。
在其中一个实施例中，如图4所示，每个工作周期包括第一控制信号的至少一个脉冲，在工作周期之前，第三控制信号的脉冲上升沿与第五控制信号的脉冲上升沿之间的时长为驱动晶体管T1的源极/漏极中的一个的第一电压复位时长；在工作周期之后，第三控制信号的脉冲下降沿与第五控制信号的脉冲下降沿之间的时长为驱动晶体管T1的源极/漏极中的一个的第二电压复位时长。
需要进行说明的是，本实施例是通过第三控制信号、第五控制信号来共同确定复位时长的。
在其中一个实施例中，第三控制信号的第一脉冲下降沿与第五控制信号的第一脉冲下降沿之间的时长、第三控制信号的第二脉冲下降沿与第五控制信号的第二脉冲下降沿之间的时长均为第二电压复位时长；其中，第二脉冲下降沿在时序上滞后于第一脉冲下降沿。
需要进行说明的是，同一控制信号的第一脉冲下降沿、第二脉冲下降沿之间存在一个持续一定时间的台阶电压，该台阶电压仅可以打开对应晶体管一瞬间，并不能够在该台阶电压的持续时间中一个打开对应的晶体管。
其中，第一电压复位时长等于第二电压复位时长，有利于平衡驱动晶体管T1所受到的电应力，进而可以缓解或者改善驱动晶体管T1的阈值电压漂移程度。
图5为本申请实施例提供的像素电路的第二种结构示意图，与图2所示像素电路相比，第一晶体管T5的沟道类型被改造为N沟道型，对应地，第三走线传输的第三控制信号也被构造为单独使用的第七控制信号，该第七控制信号的构造即需要考虑对驱动晶体管T1的源极或者漏极进行复位，又需要考虑为发光电流提供对应的传输路径。
其中，第七控制信号可以但不限于为图5、图6中所示的控制信号EM2，也可以是适用的其他控制信号。
图6为图5所示像素电路的时序示意图，与图4相比的话，第一控制信号、第四控制信号、第五控制信号的波形均未发生改变，仅是第七控制信号处于低电位期间构造了两个正向脉冲，每个正向脉冲均可以单独控制第一晶体管T5的打开时间即驱动晶体管T1的源极或者漏极的复位时间。如此可以使得驱动晶体管T1的源极或者漏极的复位时间更加灵活、精准。其中，第五控制信号可以控制信号EM1。
在其中一个实施例中，图5所示像素电路中，第一晶体管T5、第二晶体管T3均为N沟道型薄膜晶体管，第三走线异于第四走线，分别用于传输不同的控制信号，第一走线用于传输第一控制信号，第三走线用于传输第七控制信号。在每个工作周期前后，第七控制信号分别具有至少一个正向脉冲。
需要进行说明的是，本实施例在每个工作周期前后均可以对驱动晶体管T1的源极或者漏极进行复位，而每个正向脉冲的持续时间也可以单独进行调制，可以相同或者不同。
在其中一个实施例中，如图6所示，在每个工作周期之前，第七控制信号具有一个第一正向脉冲；在每个工作周期之后，第七控制信号具有一个第二正向脉冲；第一正向脉冲的持续时间等于第二正向脉冲的持续时间。
可以理解的是，本实施可以作为优选方案，不仅减小了第七控制信号的脉冲数量，也可以灵活、精准地控制驱动晶体管T1的源极或者漏极的复位时间。
在其中一个实施例中，在第三晶体管T6处于一个持续的关闭状态期间，第一晶体管T5在一个工作周期前后各打开至少一次。
需要进行说明的是，第五控制信号处于一个高电位的持续期间，对应地，第三晶体管T6处于一个持续的关闭状态期间，此时，像素电路处于非发光阶段，可以为驱动晶体管T1的源极/漏极的复位时间提供一个单独的时间段。
在本实施例中，第一晶体管T5没打开一次可以为驱动晶体管T1的源极/漏极进行一次复位，而第一晶体管T5的每次打开时间即为驱动晶体管T1的源极/漏极的复位时间。
在其中一个实施例中，第四控制信号的每个工作周期对应第一控制信号的至少一个工作周期。
需要进行说明的是，在一帧中，第一控制信号可以具有一个或者多个工作周期，第四控制信号仅具有一个工作周期，而且第四控制信号的一个工作周期仅与第一控制信号的第一个工作周期对应，此时，第二晶体管T3的打开状态与写入晶体管T2的打开状态同步以提供数据信号Data至驱动晶体管T1的栅极的写入路径。
也就是说，在一帧中，第一控制信号的第一个工作周期与第四控制信号的一个工作周期在时序上至少部分重叠；且第四控制信号在一帧中不包括其他工作周期。
在其中一个实施例中，第四控制信号的一个工作周期的开始时间早于第一控制信号的第一个工作周期的开始时间，第四控制信号的一个工作周期的结束时间晚于第一控制信号的第一个工作周期的结束时间。
可以理解的是，本实施例中第二晶体管T3的导通时间可以覆盖到写入晶体管T2的导通时间，可以进一步确保数据信号Data畅通无损地写入至驱动晶体管T1的栅极。
图7为本申请实施例提供的像素电路的第三种结构示意图，与图2所示像素电路的不同之处在于，第一初始化晶体管T7被构造为P沟道型低温多晶硅薄膜晶体管，不仅可以进一步提高像素电路的动态性能，同时像素电路中各薄膜晶体管的布局（Layout）设计也更为优化，实用性高。对应地，第一初始化晶体管T7的栅极与第七走线连接，第七走线用于传输第八控制信号。其中，第一控制信号、第八控制信号可以为同一栅极驱动电路输出的具有负脉冲的扫描信号，仅需在保证第一控制信号在时序上滞后于第八控制信号的情况下，第一控制信号、第八控制信号还可以选用为任一具有负脉冲的扫描信号。例如，第八控制信号可以为如图7所示的具有负脉冲的第n-1级扫描信号Pscan（n-1）。
图8为图2所示像素电路中对应信号、节点电位的仿真波形示意图，其中，VQ表示Q点电位的波形变化，VA表示A点电位的波形变化，VB表示B点电位的波形变化，VC表示C点电位的波形变化。可以看到的是，与图4相比，本仿真波形图中第一控制信号仅示出了一个脉冲，可以理解的是，不论第一控制信号具有一个或者多个脉冲，在第一控制信号的一个工作周期前后，A点电位VA均保持稳定，由于B点电位与A点电位联动，则B点电位VB也保持了稳定，也就是说，驱动晶体管T1的源极、漏极电位在数据信号Data写入至驱动晶体管T1的栅极前后均保持了稳定，即数据信号Data写入至驱动晶体管T1的栅极前后驱动晶体管T1的三端电压得到了稳定，有效缓解了低频工作模式下驱动晶体管T1的阈值电压漂移。
图9为本申请实施例提供的像素电路的第四种结构示意图，与图7相比，第一晶体管T5被构造为P沟道型的薄膜晶体管，具体还可以为低温多晶硅薄膜晶体管。
在其中一个实施例中，如图9、图10所示，第一晶体管T5为P沟道型薄膜晶体管；第三走线用于传输第十控制信号，在写入晶体管T2的每个工作周期之前，第十控制信号的电位依次为高电位、低电位以及高电位；在写入晶体管T2的每个工作周期之后，第十控制信号的电位依次为高电位、低电位以及高电位；且在写入晶体管T2的每个工作周期中，第十控制信号的电位保持为高电位。其中，第五控制信号可以为控制信号EM1。
可以理解的是，在本实施例中，当第十控制信号处于低电位时，第一晶体管T5处于打开状态或者导通状态，此时同样可以在写入晶体管T2的每个工作周期前后实现对驱动晶体管T1的源极/漏极中的一个进行复位，以保持在写入晶体管T2的每个工作周期前后实现对驱动晶体管T1的源极/漏极中的一个的电位稳定性，进而可以保持处于联动关系中的驱动晶体管T1的源极/漏极中的另一个的电位稳定性，如此可以在写入晶体管T2的每个工作周期前后保持驱动晶体管T1的三端电压的稳定性以降低其阈值电压的漂移程度。
在其中一个实施例中，如图9、图10所示，在写入晶体管T2的每个工作周期之前第十控制信号处于低电位的时间等于在写入晶体管T2的每个工作周期之后第十控制信号处于低电位的时间。
需要进行说明的是，本实施例有利于平衡驱动晶体管T1所受到的电应力，进而可以进一步缓解或者改善驱动晶体管T1的阈值电压漂移程度。
其中，第十控制信号可以图10、图12中所示的信号EM2。
在其中一个实施例中，如图11所示，第二晶体管T3为P沟道型薄膜晶体管；第一走线与第四走线连接。
需要进行说明的是，本实施例中第一走线、第四走线可以构造为同一走线，如此可以减少像素电路所需的走线数量，进而可以提高像素的开口率。
在其中一个实施例中，像素电路还包括第二初始化晶体管T4，第二初始化晶体管T4的源极/漏极中的一个与驱动晶体管T1的栅极连接，第二初始化晶体管T4的源极/漏极中的另一个与第二初始线连接，第二初始化晶体管T4的栅极与第一初始化晶体管T7的栅极连接；其中，第二初始化晶体管T4的沟道类型与第一初始化晶体管T7的沟道类型相同。
需要进行说明的是，本实施例中第一初始化晶体管T7的栅极、第二初始化晶体管T4的栅极可以共用同一走线，如此可以减少像素电路所需的走线数量，进而可以提高像素的开口率。
在其中一个实施例中，第一初始化晶体管T7、第二初始化晶体管T4均为双栅型薄膜晶体管，具体还可以为低温多晶硅薄膜晶体管。
需要进行说明的是，当第一初始化晶体管T7、第二初始化晶体管T4被构造为双栅型低温多晶硅薄膜晶体管时，可以在工艺上得到简化，在成本上得到降低。
在其中一个实施例中，如图12所示，在写入晶体管T2的每个工作周期中，信号Pscan（n）、信号Pscan（n-1）可以但不限于仅具有一个负脉冲，也可以具有多个负脉冲。
在其中一个实施例中，本实施例提供一种显示面板，该显示面板包括上述至少一实施例中的像素电路。
可以理解的是，本实施例提供的显示面板，通过第一晶体管T5在写入晶体管T2的每个工作周期前后分别切换至少一次开关状态，可以在每次切换开关状态时对驱动晶体管T1的一极电位进行复位，能够在低频工作模式下稳定驱动晶体管T1的一极电位，而驱动晶体管T1的另一极电位与驱动晶体管T1的一极电位联动，在驱动晶体管T1的一极电位稳定的情况下，驱动晶体管T1的另一极电位也随之稳定，如此，驱动晶体管T1在高低频工作模式下均可以保持三端电压的稳定性，进而缓解了低频工作模式下驱动晶体管T1的阈值电压漂移的技术问题，也缓解了规律性变化的亮度所导致的闪烁现象。
又，由于第一晶体管T5不仅可以在非发光阶段中对驱动晶体管T1的一极进行复位，还可以在发光阶段中控制发光电流，即实现了复用，这减少了像素电路中薄膜晶体管的使用数量，简化了像素电路的结构，有利于提高像素密度。
在其中一个实施例中，随着显示面板的刷新频率的降低，第一控制信号的频率保持不变，第四控制信号的频率减小。
需要进行说明的是，本申请中的低频可以为30Hz以下的刷新频率，例如，20Hz、10Hz、1Hz、0.5Hz...等等。本申请中的高频可以为30Hz以上的刷新频率，例如，60Hz、90Hz、120Hz、240Hz...等等。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (22)

  1. 一种像素电路，包括：
    驱动晶体管；
    写入晶体管，所述写入晶体管的源极/漏极中的一个与所述驱动晶体管的源极/漏极中的一个连接，所述写入晶体管的源极/漏极中的另一个与数据线连接，所述写入晶体管的栅极与第一走线连接；
    第一晶体管，所述第一晶体管的源极/漏极中的一个与第二走线连接，所述第一晶体管的源极/漏极中的另一个与所述驱动晶体管的源极/漏极中的一个连接，所述第一晶体管的栅极与第三走线连接；以及
    第二晶体管，所述第二晶体管的源极/漏极中的一个与所述驱动晶体管的源极/漏极中的另一个连接，所述第二晶体管的源极/漏极中的另一个与所述驱动晶体管的栅极连接，所述第二晶体管的栅极与第四走线连接；
    其中，在所述写入晶体管的每个工作周期前后，所述第一晶体管分别切换至少一次开关状态。
  2. 根据权利要求1所述的像素电路，其中，在所述写入晶体管的每个工作周期前后，所述第二走线通过所述第一晶体管分别复位所述驱动晶体管的源极/漏极中的一个的电压。
  3. 根据权利要求2所述的像素电路，其中，在所述写入晶体管的每个工作周期之前，所述驱动晶体管的源极/漏极中的一个的电压复位时长为第一复位时长；在所述写入晶体管的每个工作周期之后，所述驱动晶体管的源极/漏极中的一个的电压复位时长为第二复位时长；且所述第一复位时长等于所述第二复位时长。
  4. 根据权利要求1所述的像素电路，其中，所述像素电路还包括：
    第三晶体管，所述第三晶体管的源极/漏极中的一个与所述驱动晶体管的源极/漏极中的另一个连接，所述第三晶体管的栅极与第五走线连接；和
    发光器件，所述发光器件的阳极与所述第三晶体管的源极/漏极中的另一个连接，所述发光器件的阴极与第六走线连接；
    其中，所述第三晶体管处于关闭状态时，所述第一晶体管在每个所述工作周期前后分别切换至少一次开关状态。
  5. 根据权利要求4所述的像素电路，其中，所述第一走线用于传输第一控制信号，所述第三走线用于传输第三控制信号，所述第五走线用于传输第五控制信号；
    每个所述工作周期包括所述第一控制信号的至少一个脉冲，在所述工作周期之前，所述第三控制信号的脉冲上升沿与所述第五控制信号的脉冲上升沿之间的时长为所述驱动晶体管的源极/漏极中的一个的第一电压复位时长；在所述工作周期之后，所述第三控制信号的脉冲下降沿与所述第五控制信号的脉冲下降沿之间的时长为所述驱动晶体管的源极/漏极中的一个的第二电压复位时长。
  6. 根据权利要求5所述的像素电路，其中，所述第三控制信号的第一脉冲下降沿与所述第五控制信号的第一脉冲下降沿之间的时长、所述第三控制信号的第二脉冲下降沿与所述第五控制信号的第二脉冲下降沿之间的时长均为所述第二电压复位时长；其中，所述第二脉冲下降沿在时序上滞后于所述第一脉冲下降沿。
  7. 根据权利要求6所述的像素电路，其中，所述第一电压复位时长等于所述第二电压复位时长。
  8. 根据权利要求1所述的像素电路，其中，所述第一晶体管的沟道类型与所述第二晶体管的沟道类型不同，所述第三走线、所述第四走线为同一走线。
  9. 根据权利要求4所述的像素电路，其中，所述第一晶体管、所述第二晶体管均为N沟道型薄膜晶体管，所述第三走线异于所述第四走线；所述第一走线用于传输第一控制信号，所述第三走线用于传输第七控制信号；在每个所述工作周期前后，所述第七控制信号分别具有至少一个正向脉冲。
  10. 根据权利要求9所述的像素电路，其中，在每个所述工作周期之前，所述第七控制信号具有一个第一正向脉冲；在每个所述工作周期之后，所述第七控制信号具有一个第二正向脉冲；所述第一正向脉冲的持续时间等于所述第二正向脉冲的持续时间。
  11. 根据权利要求9所述的像素电路，其中，在所述第三晶体管处于一个持续的关闭状态期间，所述第一晶体管在一个所述工作周期前后各打开至少一次。
  12. 根据权利要求4所述的像素电路，其中，所述像素电路还包括第一初始化晶体管，所述第一初始化晶体管的源极/漏极中的一个与所述发光器件的阳极连接，所述第一初始化晶体管的源极/漏极中的另一个与所述第一初始线电性连接，所述第一初始化晶体管的栅极与所述第五走线或者第七走线连接。
  13. 根据权利要求12所述的像素电路，其中，所述第三晶体管为P沟道型薄膜晶体管且所述第一初始化晶体管为N沟道型薄膜晶体管时，所述第一初始化晶体管的栅极与所述第五走线连接；或者，
    所述第三晶体管、所述第一初始化晶体管均为P沟道型薄膜晶体管时，所述第一初始化晶体管的栅极与所述第七走线连接，所述第七走线用于传输第八控制信号；所述第一走线用于传输第一控制信号，所述第一控制信号在时序上滞后于所述第八控制信号。
  14. 根据权利要求1所述的像素电路，其中，所述第一走线用于传输第一控制信号，所述第四走线用于传输第四控制信号；所述第四控制信号的每个工作周期对应所述第一控制信号的至少一个工作周期。
  15. 根据权利要求14所述的像素电路，其中，在一帧中，所述第一控制信号的第一个工作周期与所述第四控制信号的一个工作周期在时序上至少部分重叠；且所述第四控制信号在所述一帧中不包括其他工作周期。
  16. 根据权利要求14所述的像素电路，其中，所述第四控制信号的一个工作周期的开始时间早于所述第一控制信号的第一个工作周期的开始时间，所述第四控制信号的一个工作周期的结束时间晚于所述第一控制信号的第一个工作周期的结束时间。
  17. 根据权利要求1所述的像素电路，其中，所述第一晶体管为P沟道型薄膜晶体管；
    所述第三走线用于传输第十控制信号，在所述写入晶体管的每个工作周期之前，所述第十控制信号的电位依次为高电位、低电位以及高电位；在所述写入晶体管的每个工作周期之后，所述第十控制信号的电位依次为高电位、低电位以及高电位；且在所述写入晶体管的每个工作周期中，所述第十控制信号的电位保持为高电位。
  18. 根据权利要求17所述的像素电路，其中，在所述写入晶体管的每个工作周期之前所述第十控制信号处于所述低电位的时间等于在所述写入晶体管的每个工作周期之后所述第十控制信号处于所述低电位的时间。
  19. 根据权利要求1所述的像素电路，其中，所述第二晶体管为P沟道型薄膜晶体管；所述第一走线与所述第四走线连接。
  20. 根据权利要求13所述的像素电路，其中，像素电路还包括第二初始化晶体管，所述第二初始化晶体管的源极/漏极中的一个与所述驱动晶体管的栅极连接，所述第二初始化晶体管的源极/漏极中的另一个与第二初始线连接，所述第二初始化晶体管T4的栅极与所述第一初始化晶体管的栅极连接；
    其中，所述第二初始化晶体管的沟道类型与所述第一初始化晶体管的沟道类型相同。
  21. 根据权利要求20所述的像素电路，其中，所述第一初始化晶体管、所述第二初始化晶体管均为双栅型薄膜晶体管。
  22. 一种显示面板，包括如权利要求1所述的像素电路，其中，所述第一走线用于传输第一控制信号，所述第四走线用于传输第四控制信号；随着所述显示面板的刷新频率的降低，所述第一控制信号的频率保持不变，所述第四控制信号的频率减小。
PCT/CN2022/106969 2022-06-29 2022-07-21 像素电路及显示面板 WO2024000701A1 (zh)

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