WO2024000459A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

Info

Publication number
WO2024000459A1
WO2024000459A1 PCT/CN2022/102958 CN2022102958W WO2024000459A1 WO 2024000459 A1 WO2024000459 A1 WO 2024000459A1 CN 2022102958 W CN2022102958 W CN 2022102958W WO 2024000459 A1 WO2024000459 A1 WO 2024000459A1
Authority
WO
WIPO (PCT)
Prior art keywords
cathode voltage
cathode
display
voltage line
area
Prior art date
Application number
PCT/CN2022/102958
Other languages
English (en)
French (fr)
Inventor
李云龙
卢鹏程
陈小川
卜维亮
Original Assignee
京东方科技集团股份有限公司
云南创视界光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 云南创视界光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/102958 priority Critical patent/WO2024000459A1/zh
Priority to CN202280002045.5A priority patent/CN117652226A/zh
Publication of WO2024000459A1 publication Critical patent/WO2024000459A1/zh

Links

Images

Definitions

  • Embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular, to a display substrate, a preparation method thereof, and a display device.
  • Micro Organic Light-Emitting Diode is a micro-display developed in recent years, and silicon-based OLED is one of them. Silicon-based OLED can not only realize active addressing of pixels, but also can prepare structures such as pixel drive circuits on silicon-based substrates, which is beneficial to reducing system volume and achieving lightweight. Silicon-based OLED is prepared using the mature Complementary Metal Oxide Semiconductor (CMOS) integrated circuit process. It has the advantages of small size, high resolution (Pixels Per Inch, referred to as PPI), and high refresh rate. It is widely used in In the field of near-eye display of Virtual Reality (VR for short) or Augmented Reality (AR for short).
  • CMOS Complementary Metal Oxide Semiconductor
  • Embodiments of the present disclosure provide a display substrate, including a substrate, a display area and a cathode ring area provided on the substrate, the cathode ring area is located outside the display area; perpendicular to the display substrate On a plane, the display substrate includes an insulating layer provided on the substrate and a light-emitting structure layer provided on the insulating layer.
  • the light-emitting structure layer includes an anode layer, a pixel definition layer, a light-emitting layer and a cathode
  • the anode layer includes a plurality of display anodes located in the display area and a cathode voltage line located in the cathode ring area, the cathode is connected to the cathode voltage line
  • the substrate includes a power supply electrode and a pixel driving circuit
  • the insulating layer includes a first conductive pillar and a second conductive pillar, and the display anode is connected to the pixel driving circuit through the first conductive pillar;
  • the cathode voltage line includes a plurality of first cathode voltage lines and a plurality of a second cathode voltage line, the first cathode voltage line extends along a first direction, the second cathode voltage line extends along a second direction, the first direction is a direction parallel to the edge of the display substrate, so The second direction intersects the first direction; at
  • An embodiment of the present disclosure also provides a display device, including: a display substrate as described in any embodiment of the present disclosure.
  • Embodiments of the present disclosure also provide a method for preparing a display substrate, which includes a display area and a cathode ring area located outside the display area.
  • the preparation method includes:
  • the insulating layer includes a first conductive pillar and a second conductive pillar.
  • the light-emitting structure layer includes an anode layer, a pixel definition layer, an organic light-emitting layer and a cathode.
  • the anode layer includes a display anode located in the display area and a cathode voltage line located in the cathode ring area, the cathode is connected to the cathode voltage line, and the display anode is connected to the pixel through the first conductive pillar.
  • the cathode voltage lines include a plurality of first cathode voltage lines and a plurality of second cathode voltage lines, the first cathode voltage lines extend along a first direction, and the second cathode voltage lines extend along a second direction Extending, the first direction is a direction parallel to the edge of the display substrate, and the second direction intersects the first direction; at least one second cathode voltage line is disposed between two adjacent second cathode voltage lines.
  • the cathode voltage line is connected to the power supply electrode through the second conductive pillar, and the cathode voltage line is connected to the
  • the orthographic projection on the substrate covers the orthographic projection of the second conductive pillar on the substrate.
  • Figure 1 is a schematic structural diagram of a silicon-based OLED display device
  • Figure 2 is a schematic plan view of a silicon-based OLED display device
  • Figure 3 is a schematic plan view of the display area in a silicon-based OLED display device
  • Figure 4A is an equivalent circuit diagram of a pixel driving circuit
  • Figure 4B is a working timing diagram of a pixel driving circuit
  • Figure 5 is a schematic structural diagram of a silicon-based OLED display substrate according to an exemplary embodiment of the present disclosure
  • Figure 6A is a schematic cross-sectional structural diagram along the direction AA' in Figure 5;
  • Figure 6B, Figure 6C, Figure 6D and Figure 6E are four enlarged structural schematic diagrams of area B in Figure 5;
  • Figure 6F is a schematic plan view of a display substrate after preparing the anode layer
  • Figure 6G is a schematic plan view of a display substrate after preparing the pixel definition layer
  • Figure 7 is a schematic diagram after forming a silicon-based substrate according to an embodiment of the present disclosure.
  • Figure 8 is a schematic diagram after the first insulating layer is formed according to an embodiment of the present disclosure.
  • Figure 9 is a schematic diagram after forming a reflective layer according to an embodiment of the present disclosure.
  • Figure 10 is a schematic diagram after forming a second insulating layer pattern according to an embodiment of the present disclosure.
  • Figure 11 is a schematic diagram after forming an anode layer pattern according to an embodiment of the present disclosure.
  • Figure 12 is a schematic diagram after the first pixel definition layer pattern is formed according to an embodiment of the present disclosure.
  • Figure 13 is a schematic diagram after forming a cathode pattern according to an embodiment of the present disclosure.
  • Figure 14 is a schematic diagram after the encapsulation layer pattern is formed according to an embodiment of the present disclosure.
  • FIG. 15 is another enlarged structural schematic diagram of area B in FIG. 5 .
  • the scale of the drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels and the number of sub-pixels in each pixel in the display device are not limited to the numbers shown in the figures.
  • the figures described in the present disclosure are only structural schematic diagrams, and one mode of the present disclosure is not limited to the figures. The shape or numerical value shown in the figure.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • connection should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, an indirect connection through an intermediate piece, or an internal connection between two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, channel region, and source electrode .
  • the channel region refers to the region through which current mainly flows.
  • first pole in order to distinguish the two poles of the transistor except the control electrode, one pole is directly described as the first pole and the other pole is the second pole.
  • the first pole can be the drain electrode and the second pole can be the source electrode.
  • the first electrode can be the source electrode and the second electrode can be the drain electrode.
  • electrical connection includes a case where constituent elements are connected together through an element having some electrical effect.
  • component having some electrical function There is no particular limitation on the “component having some electrical function” as long as it can transmit and receive electrical signals between the connected components.
  • elements having some electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.
  • parallel refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less.
  • vertical refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes an angle of 85° or more and 95° or less.
  • film and “layer” may be interchanged.
  • conductive layer may sometimes be replaced by “conductive film.”
  • insulating film may sometimes be replaced by “insulating layer”.
  • the "same layer arrangement" used refers to structures formed by patterning two (or more than two) structures through the same patterning process, and their materials may be the same or different.
  • the precursor materials used to form multiple structures arranged in the same layer are the same, and the final materials formed may be the same or different.
  • triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not strictly speaking. They can be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances. There can be leading angles, arc edges, deformations, etc.
  • FIG. 1 is a schematic structural diagram of a silicon-based OLED display device.
  • the silicon-based OLED display device may include a timing controller, a data signal driver, a scanning signal driver, and a pixel array.
  • the pixel array may include a plurality of scanning signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn) and multiple sub-pixels Pxij.
  • the timing controller may provide a gray value and a control signal suitable for the specifications of the data signal driver to the data signal driver, and may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan signal driver. Provided to scan signal driver.
  • the data signal driver may generate data voltages to be provided to the data signal lines D1, D2, D3, . . . and Dn using the grayscale values and control signals received from the timing controller. For example, the data signal driver may sample the grayscale value using a clock signal, and apply a data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in sub-pixel row units, where n may be a natural number.
  • the scan signal driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, . . . and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan signal driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm.
  • the scan signal driver may be configured in the form of a shift register, and may generate the scan in a manner that sequentially transmits a scan start signal provided in the form of an on-level pulse to a next-stage circuit under the control of a clock signal.
  • Signal, m can be a natural number.
  • the sub-pixel array may include a plurality of pixel sub-Pxij. Each pixel sub-Pxij can be connected to the corresponding data signal line and the corresponding scanning signal line, and i and j can be natural numbers.
  • the sub-pixel Pxij may refer to a sub-pixel in which the transistor is connected to the i-th scanning signal line and connected to the j-th data signal line.
  • Figure 2 is a schematic plan view of a silicon-based OLED display device.
  • the silicon-based OLED display device may include a display area 100 and a dummy pixel area 200 located outside the display area 100 .
  • the display area 100 is an active area (AA) for image display, and may include a plurality of sub-pixels constituting a pixel array.
  • the sub-pixels may include a pixel driving circuit and a display light-emitting device, and the plurality of sub-pixels may be configured to display Moving pictures or still images.
  • the dummy pixel area 200 is located at the periphery of the display area 100 and may include a plurality of dummy light-emitting devices configured to present the appearance of the display light-emitting device but not perform image display.
  • the silicon-based OLED display device may further include a cathode ring region 300 , and the cathode ring region 300 may be located at the periphery of the dummy pixel region 200 , that is, the dummy pixel region 200 is located between the display region 100 and the cathode ring region 300 .
  • cathode ring region 300 may include a cathode voltage line configured to provide a common voltage (VCOM).
  • VCOM common voltage
  • the cathode voltage line may form a ring-shaped structure surrounding the dummy pixel area 200, and the cathode voltage line of the ring-shaped structure may be called a cathode ring.
  • Figure 3 is a schematic plan view of a display area in a silicon-based OLED display device.
  • the display area may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first sub-pixel P1 that emits light of a first color, a third sub-pixel that emits light of a second color.
  • the second sub-pixel P2 and the third sub-pixel P3 that emit light of the third color, the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 all include a pixel driving circuit and a light-emitting device.
  • the pixel driving circuit in the sub-pixel is connected to the scanning signal line and the data signal line respectively.
  • the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and output a corresponding current to the display light-emitting device.
  • the display light-emitting device in the sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the display light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.
  • the first sub-pixel P1 may be a red sub-pixel emitting red (R) light
  • the second sub-pixel P2 may be a blue sub-pixel emitting blue (B) light
  • the third sub-pixel P3 It can be a green sub-pixel that emits green (G) light.
  • the shape of the sub-pixels may be any one or more of triangles, squares, rectangles, rhombuses, trapezoids, parallelograms, pentagons, hexagons and other polygons, and may be horizontally juxtaposed, Vertically juxtaposed, X-shaped, cross-shaped, Z-shaped, square, diamond-shaped or delta-shaped, etc., the disclosure is not limited here.
  • the pixel unit may include four sub-pixels, which is not limited by the present disclosure.
  • FIG. 4A is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure.
  • the pixel driving circuit may include 3 transistors (first transistor T1 to third transistor T3) and 1 storage capacitor C.
  • the pixel driving circuit is connected with 5 signal lines (scanning signal line S, data signal line D , the reference signal line REF, the first power supply line VDD and the cathode voltage line VSS) are connected, and the first node N1 and the second node N2 are meeting points representing relevant electrical connections in the circuit diagram.
  • a first terminal of the storage capacitor C is connected to the first node N1, and a second terminal of the storage capacitor C is connected to the cathode voltage line VSS.
  • control electrode of the first transistor T1 is connected to the scanning signal line S, the first electrode of the first transistor T1 is connected to the data signal line D, and the second electrode of the first transistor T1 is connected to the first node N1 .
  • control electrode of the second transistor T2 is connected to the reference signal line REF
  • first electrode of the second transistor T2 is connected to the second node N2
  • second electrode of the second transistor T2 is connected to the display light-emitting device XL.
  • the first electrode is connected
  • the second electrode of the display light-emitting device XL is connected to the cathode voltage line VSS.
  • control electrode of the third transistor T3 is connected to the first node N1
  • first electrode of the third transistor T3 is connected to the first power line VDD
  • second electrode of the third transistor T3 is connected to the second node N2. connect.
  • the signal of the first power line VDD may be a continuously provided high-level signal
  • the signal of the cathode voltage line VSS may be a continuously provided low-level signal
  • the reference signal line REF may be a continuously provided low-level signal. flat signal, or can be a variable voltage signal.
  • the first transistor T1 is configured to receive the data voltage transmitted by the data signal line D under the control of the signal of the scanning signal line S, store the data voltage into the storage capacitor C, and transmit the data voltage to the third transistor T3
  • the first control electrode provides the data voltage
  • the second transistor T2 is configured to provide the voltage signal of the second node N2 to the first electrode of the display light-emitting device XL under the control of the signal of the reference signal line REF
  • the third transistor T3 It is configured to provide the signal of the first power line VDD to the second node N2 under the control of the signal of the first node N1 to drive the display light-emitting device XL to emit light.
  • the first, second, and third transistors T1, T2, and T3 may be P-type transistors. In another exemplary embodiment, the first, second, and third transistors T1, T2, and T3 may be N-type transistors. In yet another exemplary embodiment, the first, second, and third transistors T1, T2, and T3 may include P-type transistors and N-type transistors.
  • the first transistor T1 and the second transistor T2 may be P-type metal oxide semiconductor transistors (PMOS), and the third transistor T3 may be an N-type metal oxide semiconductor transistor (NMOS).
  • the display light-emitting device XL may be an OLED, or may be a QLED, etc., which is not limited by the present disclosure.
  • a plurality of pixel driving circuits may be provided in the display area, and auxiliary circuits may be provided at the periphery of the display area (eg, a dummy pixel area or other areas).
  • the auxiliary circuit may include a reset subcircuit, the reset subcircuit is connected to the second node N2, the discharge signal line and the initial signal line, and the reset subcircuit is configured to under the control of the signal of the discharge signal line, to the second node N2 provides the initial voltage provided by the initial signal line.
  • Figure 4B is a working timing diagram of a pixel driving circuit. The following describes exemplary embodiments of the present disclosure through the working process of the pixel driving circuit illustrated in FIG. 4A.
  • the first transistor T1 and the second transistor T2 are P-type transistors
  • the third transistor T3 is an N-type transistor.
  • the working process of the pixel driving circuit may include:
  • the first phase S1 is called the reset phase or initialization phase.
  • the signal of the scanning signal line S is a high-level signal
  • the signal of the data signal line D is a low-level signal
  • the signal of the reference signal line REF is a low-level signal
  • the signal of the first power line VDD is a low-level signal. flat signal.
  • the reset subcircuit provides an initial voltage to the second node N2.
  • the low-level signal of the reference signal line REF turns on the P-type second transistor T2, so that the initial voltage is provided to the display light-emitting device XL through the turned-on second transistor T2.
  • the first pole initializes the display light-emitting device XL, which can quickly discharge (clear) the charge stored in the first pole of the display light-emitting device XL, ensuring that the display light-emitting device XL does not emit light, and achieving better dynamic contrast.
  • the high-level signal of the scanning signal line S causes the P-type first transistor T1 to turn off.
  • the second phase S2 is called the data writing phase.
  • the signal of the scanning signal line S is a low-level signal
  • the signal of the data signal line D is a high-level signal
  • the signal of the reference signal line REF is a low-level signal
  • the signal of the first power line VDD is a low-level signal. flat signal.
  • the low-level signal of the scanning signal line S turns on the P-type first transistor T1
  • the data voltage of the data signal line D is provided to the first node N1 through the turned-on first transistor T1, charging the storage capacitor C, so that The data voltage output from the data signal line D is stored in the storage capacitor C.
  • the third stage S3 is called the luminous stage.
  • the signal of the scanning signal line S is a high-level signal
  • the signal of the data signal line D is a low-level signal
  • the signal of the reference signal line REF is a low-level signal
  • the signal of the first power line VDD is a high-level signal. flat signal.
  • the high-level signal of the scanning signal line S turns off the P-type first transistor T1, and the data voltage stored in the storage capacitor C is provided to the first node N1.
  • the potential of the first node N1 is the data voltage of the data signal line D, so that The N-type third transistor T3 is turned on.
  • the low-level signal of the reference signal line REF turns on the P-type second transistor T2, so that the high-level signal output by the first power supply line VDD is provided to the display light-emitting device through the turned-on third transistor T3 and the second transistor T2.
  • the first pole of XL causes the display light-emitting device XL to emit light.
  • the driving current flowing through the third transistor T3 (referred to as the driving transistor) is determined by the connection between the control electrode of the third transistor T3 and the first electrode of the third transistor T3. Determined by the voltage difference, the driving current of the third transistor T3 is:
  • I represents the driving current flowing through the third transistor T3
  • K represents a constant
  • Vgs represents the voltage difference between the gate electrode of the third transistor T3 and the first electrode
  • Vth represents the threshold voltage of the third transistor T3
  • Vdate represents data.
  • the data voltage provided by the signal line D, Vdd represents the power supply voltage output by the first power supply line VDD.
  • FIG. 5 is a schematic structural diagram of a silicon-based OLED display substrate according to an exemplary embodiment of the present disclosure.
  • the silicon-based OLED display substrate may include a display area 100 , a cathode ring area 300 located at the periphery of the display area 100 and a cathode ring area 300 located at the periphery of the display area 100 .
  • the display area 100 may include a plurality of pixel driving circuits and a plurality of display light-emitting devices Pa
  • the display light-emitting device Pa may include a display anode, a cathode, and a display light-emitting layer disposed between the display anode and the cathode.
  • the display anodes of the plurality of display light-emitting devices Pa are correspondingly connected to the plurality of pixel driving circuits.
  • the dummy pixel area 200 may include a plurality of dummy light-emitting devices P b , and the dummy light-emitting devices P b may include a dummy anode, a cathode, and a dummy light-emitting layer disposed between the dummy anode and the cathode.
  • the plurality of dummy light-emitting devices P b The dummy anode of the device P b can be in a floating state without electrical connection, or the dummy anodes and cathodes of multiple dummy light-emitting devices P b can both be connected to the cathode voltage line, and both have the same potential, so , it can be guaranteed that the dummy light-emitting device P b will not emit light.
  • the cathode ring region 300 may include a cathode voltage line connected to the cathode through the pixel definition layer opening and a cathode configured to provide a common voltage (VCOM).
  • the cathode voltage line may be located on a side of the dummy light-emitting device P b away from the display area 100 and may form a ring-shaped structure surrounding the dummy light-emitting device P b .
  • the cathode voltage line of the ring-shaped structure may be called a cathode ring.
  • connection structure can be understood as a resistor series structure along the direction away from the display area, which further increases the cathode overlap resistance, affects the voltage drop (IR DROP) in the display area, and in severe cases, causes a black screen of the display device.
  • Figure 6A is a schematic cross-sectional structural diagram along the AA' direction in Figure 5.
  • the display light-emitting device Pa in Figure 6A illustrates a structure that uses white light + color film to achieve full color.
  • the silicon-based OLED display device may include: a silicon-based substrate 10, the silicon-based substrate 10 of the display area 100 is integrated with a pixel driving circuit, and the silicon-based substrate 10 of the cathode ring area 300 is integrated with a power supply electrode,
  • the light-emitting structure layer 20 is provided on the silicon-based substrate 10
  • the first encapsulation layer 40 is provided on the side of the light-emitting structure layer 20 away from the silicon-based substrate 10
  • the first encapsulation layer 40 is provided on the side away from the silicon-based substrate 10
  • the color filter structural layer 50 is provided with a second encapsulation layer (not shown in the figure) on the side of the color filter structural layer 50 away from the silicon-based substrate 10
  • the second encapsulation layer is provided on the
  • the silicon-based substrate 10 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate.
  • the pixel driving circuit and the power supply circuit can be prepared on the silicon-based substrate 10 through a silicon semiconductor process (such as a CMOS process).
  • the pixel driving circuit is connected to the scanning signal line and the data signal line respectively.
  • the pixel driving circuit can include a plurality of transistors and storage capacitors. , only one transistor is used as an example in Figure 6A.
  • the transistor may include a control electrode G, a first electrode S, and a second electrode D.
  • the control electrode G, the first electrode S, and the second electrode D may be connected to the control electrode G, the first electrode S, and the second electrode D through a tungsten metal-filled via hole (ie, a tungsten via hole, W-via), respectively.
  • a tungsten metal-filled via hole ie, a tungsten via hole, W-via
  • connection electrodes are connected, and can be connected to other electrical structures (such as wiring, etc.) through the connection electrodes.
  • the light-emitting structure layer 20 of the display area 100 may include a display anode 31A, a pixel definition layer, a display light-emitting layer 34A, and a cathode 35.
  • the display anode 31A may be connected to the transistor through a connecting electrode (the first reflective electrode 141).
  • the second electrode D is connected.
  • the pixel definition layer is provided with a first pixel opening.
  • the first pixel opening exposes at least part of the display anode 31A.
  • the display luminescent layer 34A is connected to the display anode 31A through the first pixel opening.
  • the cathode 35 is connected to the display luminescent layer 34A.
  • the display luminescent layer 34A emits light driven by the display anode 31A and the cathode 35 .
  • the display luminescent layer 34A may include an luminescent layer (EML for short), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), and an electron blocking layer (EBL). , hole blocking layer (HBL), electron transport layer (ETL) and electron injection layer (EIL).
  • EML luminescent layer
  • HIL hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • EIL electron injection layer
  • the display light-emitting layers 34A of all sub-pixels may be a common layer connected together.
  • the light-emitting structure layer 20 of the dummy pixel region 200 may include a dummy anode 31B, a pixel definition layer, a dummy light-emitting layer 34B and a cathode 35.
  • the dummy anode 31B may be in a floating state and has no electrical connection.
  • the pixel definition layer is provided with a second pixel opening, the second pixel opening exposes at least part of the dummy anode 31B, the dummy light-emitting layer 34B is connected to the dummy anode 31B through the second pixel opening, and the cathode 35 is connected to the dummy light-emitting layer 34B.
  • the light emitting structure layer 20 of the cathode ring region 300 may include a cathode voltage line 32, a pixel definition layer and a cathode 35, the pixel definition layer is provided with a third opening, the third opening exposes at least part of the cathode voltage line 32 , the cathode voltage line 32 is connected to the cathode 35 through the third opening, the cathode voltage line 32 is connected to the power supply electrode 301 through the connection electrode (third reflective electrode 143), and is configured to provide a common voltage (VCOM).
  • VCOM common voltage
  • the first encapsulation layer 40 and the second encapsulation layer can adopt a thin film encapsulation (TFE) method, which can ensure that external water vapor cannot enter the light-emitting structure layer and the cover plate.
  • TFE thin film encapsulation
  • the layer (not shown in the figure) can be made of glass or plastic colorless polyimide with flexible properties.
  • the color filter structure layer 50 may include a black matrix (BM) and a color filter (CF).
  • the position of the color filter may correspond to the position of the light-emitting device, and the black matrix may be located adjacent to Between the color filters, the color filters are configured to filter the white light emitted from the light-emitting device into red (R) light, green (G) light and blue (B) light to form red sub-pixels, green sub-pixels and Blue subpixel.
  • FIGS 6B, 6C, 6D and 6E are four enlarged structural schematic diagrams of area B in Figure 5.
  • the display substrate includes: a silicon-based substrate 10, an anode layer, a pixel definition layer, an organic light-emitting layer and a cathode arranged on the silicon-based substrate 10 in sequence.
  • the anode layer includes a display anode 31A provided in the display area 100 and a cathode voltage line 32 provided in the cathode ring area 300.
  • the cathode voltage line 32 includes a plurality of first cathode voltage lines 320 and a plurality of second cathode voltage lines 321.
  • each second cathode voltage line 321 is disposed between two adjacent first cathode voltage lines 320 and connected to the two adjacent first cathode voltage lines 320 .
  • the display substrate in the embodiment of the disclosure may also be made of other materials, and the embodiment of the disclosure does not limit this.
  • a plurality of first cathode voltage lines 320 extend along a first direction X
  • a plurality of second cathode voltage lines 321 extend along a second direction Y.
  • the first direction X intersects with the second direction Y.
  • the first direction X is the row direction
  • the second direction Y is the column direction
  • the first direction X is the column direction
  • the second direction Y is the row direction. That is, the first direction X is a direction parallel to the edge of the display substrate.
  • first direction X and the second direction Y are perpendicular to each other.
  • the silicon-based substrate 10 includes a power supply electrode 301, and a cathode voltage line 32 passes through a metal via hole (ie, the second conductive pillar 13B and the fifth conductive pillar 16C described later,
  • a metal via hole ie, the second conductive pillar 13B and the fifth conductive pillar 16C described later
  • the metal via hole when the reflective layer is not provided, the metal via hole (the second conductive pillar 13B described below) is connected to the power supply electrode 301 .
  • the metal via hole may be a tungsten hole.
  • the cathode voltage line 32 is connected to the power supply electrode 301 through a metal via hole.
  • the first cathode voltage line 320 may be connected to the power supply electrode 301 through a metal via hole, or the third cathode voltage line 320 may be connected to the power supply electrode 301 through a metal via hole.
  • the two cathode voltage lines 321 are connected to the power supply electrode 301 through metal via holes.
  • the specific location of the metal via holes can be adjusted according to actual electrical connection needs, for example, it is located in the area covered by the first cathode voltage line 320 or is located adjacent to the first cathode voltage line. Within the area covered by the second cathode voltage line 321 between the lines 320, the embodiment of the present disclosure does not limit this.
  • the length of the metal via hole may be between 0.3um and 0.5um, and the width of the metal via hole may be between 0.3um and 0.5um.
  • the length of the metal via hole may be 0.4um, and the width of the metal via hole may be 0.4um.
  • the orthographic projection of the cathode voltage line 32 on the silicon-based substrate 10 covers the orthographic projection of the metal via on the silicon-based substrate 10 .
  • the width b1 of the first cathode voltage line 320 in the direction perpendicular to the first direction X is greater than the width b1 of the second cathode voltage line 321 in the direction perpendicular to the second direction Y. Width b2.
  • the cathode voltage line 32 forms a first zigzag structure edge 320_1
  • the pixel definition layer is on the substrate 10
  • the orthographic projection of covers the orthographic projection of the first zigzag structure edge 320_1 on the substrate 10 .
  • the anode layer also includes a dummy anode 31B located in the dummy pixel area 200 , and a side of the dummy anode 31B close to the cathode ring area 300 forms a second zigzag shape.
  • the structural edge, the edge of the first zigzag structure and the edge of the second zigzag structure are complementary structures.
  • the pixel definition layer of the cathode ring region 300 includes a third opening that exposes at least a portion of the first cathode voltage line 320 and at least a portion of the second cathode voltage line 321 (
  • the position of the third opening in the figure is the position of the exposed first cathode voltage line 320 and the second cathode voltage line 321), and the second cathode voltage line 321 exposed by the third opening is close to the edge of the dummy pixel area 200. It is a smooth curved surface convex toward the dummy pixel area 200 (ie, the area C identified by the dotted box in FIG. 6E).
  • Figure 6F is a schematic plan view of a display substrate after the anode layer is prepared according to an embodiment of the present disclosure.
  • Figure 6G is a schematic plan view of a display substrate after the pixel definition layer is prepared according to an embodiment of the present disclosure, where 17 represents the first pixel definition layer.
  • 33 represents the second pixel definition layer.
  • the pixel definition layer may also be a single layer, and the embodiment of the present disclosure does not limit this. As shown in FIGS.
  • the anode layer in the cathode ring area 300 , includes a first etching area, and the first etching area is located in the area surrounded by the adjacent first cathode voltage line 320 and the adjacent second cathode voltage line 321 Inside, the pixel definition layer of the cathode ring region 300 covers the first etching area and the cathode voltage line located around the first etching area.
  • the cathode voltage line 32 at the position of the first zigzag structure edge 320_1 is covered by the pixel definition layer, and therefore does not have conductive properties. Only the first cathode voltage line 320 and the second cathode voltage line 321 exposed by the third opening have electrical conductivity and can transmit low voltage to the cathode 35 .
  • the pixel definition layer of the dummy pixel area 200 includes a second pixel opening, and the second pixel opening exposes the dummy anode 31B (the position of the second pixel opening in the figure is the same as that of the dummy anode 31B). The position of the dummy anode 31B is the same);
  • the distance b3 between the edge of the cathode voltage line close to the dummy pixel area 200 and the edge of the second pixel opening close to the cathode ring area 300 is smaller than the first cathode voltage line 320 along the direction perpendicular to the first direction X.
  • the distance b4 between adjacent first cathode voltage lines 320 is greater than the width b1 of the first cathode voltage lines 320 in the direction perpendicular to the first direction X.
  • the pixel definition layer of the display area 100 includes a first pixel opening, and the first pixel opening exposes the display anode 31A (the position of the first pixel opening in the figure is consistent with the display The position of anode 31A is the same);
  • the pixel defining layer of the cathode ring region 300 includes a third opening having a different shape than the first pixel opening.
  • the width b1 of the first cathode voltage line 320 in the direction perpendicular to the first direction X is smaller than the width b1 of the first pixel opening in the direction perpendicular to the first direction X.
  • the first cathode voltage lines 320 include N, and the first to Nth first cathode voltage lines 320 to 320 are along a line close to the display area 100
  • the second cathode voltage lines 321 are arranged sequentially in the direction of It is provided between the i-th first cathode voltage line 320 and the (i+1)-th first cathode voltage line 320, where i is a natural number between 1 and N-1.
  • any i-th sub-second cathode voltage line 321_i there is an (i+1)-th sub-second cathode voltage line 321_i+1 and the i-th sub-second cathode voltage line 321_i
  • the cathode voltage line 321_i is located on a straight line.
  • the number of second cathode voltage lines 321 between two adjacent first cathode voltage lines 320 is different from the number of second conductive lines covered by each first cathode voltage line 320 .
  • the number of columns 13B is the same.
  • any i-th sub-second cathode voltage line 321_i and any (i+1)-th sub-second cathode voltage line 321_i+1 are not located on a straight line.
  • the ratio of the area of the orthographic projection of the cathode voltage line 32 on the silicon-based substrate 10 to the area of the orthographic projection of the cathode ring region 300 on the silicon-based substrate 10 is equal to the area of the orthographic projection of the display anode 31A on the silicon-based substrate 10 .
  • the ratio of the area of the orthographic projection on the substrate 10 and the area of the orthographic projection of the display area 100 on the silicon-based substrate 10 is close to or the same, that is, the distribution density of the cathode voltage line 32 in the cathode ring area 300 and the distribution density of the display anode 31A in The distribution density of the display area 100 is close to the same or the same.
  • “nearly the same” means that the difference between the distribution density of the cathode voltage line 32 in the cathode ring area 300 and the distribution density of the display anode 31A in the display area 100 is less than a preset difference threshold, which is It can be set according to actual needs, and the embodiment of the present disclosure does not limit this.
  • the anode layer includes a composite metal layer and a transparent oxide layer sequentially disposed on the silicon-based substrate 10 .
  • the composite metal layer includes titanium/aluminum/titanium (Ti/Al/Ti); the transparent oxide layer is indium tin oxide (ITO).
  • the anode layer includes a composite metal layer or a transparent oxide layer disposed on the silicon-based substrate 10 .
  • the pixel definition layer includes a first pixel definition layer 17 and a second pixel definition layer 33 , and the surface of the first pixel definition layer 17 and the surface of the anode layer are Flush, the anode layer includes a plurality of anode blocks, the anode blocks may be the display anode 31A, the dummy anode 31B and the cathode voltage line 32, the first pixel definition layer 17 is disposed in the interval between adjacent anode blocks, the second pixel
  • the definition layer 33 is disposed on a side of the first pixel definition layer 17 away from the silicon-based substrate 10 and covers the first pixel definition layer 17 . As shown in FIG.
  • the space between adjacent anode blocks is the area between adjacent display anodes 31A and the area between adjacent dummy anodes 31B; in the cathode ring area 300, the space between adjacent anode blocks is the area surrounded by adjacent first cathode voltage lines 320 and adjacent second cathode voltage lines 321, which is the aforementioned first etching area.
  • the pixel definition layer in the cathode ring region 300 , includes a plurality of pixel definition islands, and the pixel definition islands are disposed on two adjacent first cathode voltage lines 320 and within the area surrounded by two adjacent second cathode voltage lines 321.
  • the shape of the pixel definition island in Figure 6B and Figure 6C is a rounded rectangle, and the shape of the pixel definition island in Figure 6D is an ellipse.
  • the embodiment of the present disclosure does not limit this, and the shape of the pixel definition island can also be any other shape. shape.
  • the distance b6 between the pixel definition island and the first cathode voltage line 320 along the second direction Y is greater than the distance b6 between the pixel definition island and the second cathode voltage line 321 .
  • the distance b7 in the first direction X is greater than the distance b6 between the pixel definition island and the second cathode voltage line 321 .
  • the shortest distance b8 between any vertex corner of the pixel definition island and the cathode voltage line in the third opening is greater than any side of the pixel definition island and the third opening.
  • the length of the pixel definition island may be between 3um and 5um
  • the width of the pixel definition island may be between 3um and 5um
  • the distance between adjacent pixel definition islands may be between 3um and 5um.
  • the spacing can be between 1um and 3um.
  • the spacing between adjacent pixel definition islands can be 2um.
  • the orthographic projection of the second pixel definition layer 33 on the silicon-based substrate 10 overlaps with the orthographic projection of the display anode 31A on the silicon-based substrate 10 .
  • the display anode 31A of the display light-emitting device P a , the dummy anode 31B of the dummy light-emitting device P b and the cathode voltage line 32 of the cathode ring region 300 may be disposed in the same layer and pass through the same layer. Sub-patterning processes are formed simultaneously.
  • the display light-emitting layer 34A of the display light-emitting device P a and the dummy light-emitting layer 34B of the dummy light-emitting device P b may be provided in the same layer and formed simultaneously through the same evaporation process.
  • the cathode of the display light-emitting device P a , the cathode of the dummy light-emitting device P b and the cathode of the cathode ring region 300 may be arranged on the same layer and be an integral structure connected to each other.
  • the following is an exemplary description through the preparation process of the display device.
  • the "patterning process" mentioned in this disclosure includes processes such as coating of photoresist, mask exposure, development, etching, and stripping of photoresist for metal materials, inorganic materials, or transparent conductive materials.
  • organic materials it includes Processes such as coating of organic materials, mask exposure and development.
  • Deposition can use any one or more of sputtering, evaporation, and chemical vapor deposition.
  • Coating can use any one or more of spraying, spin coating, and inkjet printing.
  • Etching can use dry etching and wet etching. Any one or more of them are not limited by this disclosure.
  • Thin film refers to a thin film produced by depositing, coating or other processes of a certain material on a substrate. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer.” If the "thin film” requires a patterning process during the entire production process, it will be called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”. “A and B are arranged on the same layer” mentioned in this disclosure means that A and B are formed simultaneously through the same patterning process, and the “thickness” of the film layer is the size of the film layer in the direction perpendicular to the display device.
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the orthographic projection of A includes the orthographic projection of B means that the boundary of the orthographic projection of B falls within the orthographic projection of A. within the bounds of A, or the bounds of the orthographic projection of A overlap with the bounds of the orthographic projection of B.
  • a silicon-based OLED display device may include a display area 100, a dummy pixel area 200 located on the periphery of the display area 100, and a cathode ring area 300 located on a side of the dummy area area 200 away from the display area 100.
  • the preparation process of the display device may include the following steps.
  • the display area 100 includes multiple display units.
  • the silicon-based substrate 10 of each display unit is integrated with a pixel driving circuit.
  • the silicon-based substrate 10 of the cathode ring area 300 is integrated with a power supply circuit.
  • FIG. 7 illustrates three display units of the display area 100: the first display unit, the second display unit and the third display unit, illustrating the driving transistor 11 included in the pixel driving circuit, illustrating Power supply electrode 301 of cathode ring region 300.
  • the driving transistor 11 of the display area 100 includes an active layer, a gate electrode, a source electrode, a drain electrode and a gate connection electrode.
  • the source electrode and the drain electrode are respectively connected to the active layer through conductive pillars, and the gate connection is The electrode is connected to the gate electrode through a conductive pillar.
  • the silicon-based substrate 10 can be prepared using a mature CMOS integrated circuit process, which is not limited by this disclosure. After the preparation is completed, the surface of the silicon-based substrate 10 exposes the source electrode, drain electrode and gate connection electrode of the display area 100 and the power supply electrode 301 of the cathode ring area 300 .
  • the first via holes The first conductive pillar 13A in the second via hole is connected to the drain electrode of the display unit, and the second conductive pillar 13B in the second via hole is connected to the power supply electrode 301 of the cathode ring area 300, as shown in FIG. 8 .
  • the first conductive pillar 13A and the second conductive pillar 13B may be made of metal material. After the first conductive pillar 13A and the second conductive pillar 13B are formed through a filling process, a polishing process may also be performed.
  • the first conductive pillar 13A and the second conductive pillar 13B can be made of metal tungsten (W), and a via hole filled with tungsten metal is called a tungsten via (W-via).
  • W metal tungsten
  • W-via tungsten via
  • Tungsten vias are not only suitable for the connection between the silicon-based substrate 10 and the reflective layer, but also for the connection between the reflective layer and the anode layer, as well as the connection between other wiring layers.
  • the reflective layer includes a reflective layer disposed in the display area.
  • the first reflective electrodes 141 pass through the first The conductive pillar 13A is connected to the drain electrode, the second reflective electrode 142 is not connected to other signal lines, and the third reflective electrode 143 is connected to the power supply electrode 301 through the second conductive pillar 13B, as shown in FIG. 9 .
  • the first reflective electrode 141 of each display unit is used to form a microcavity structure with the subsequently formed cathode, and the strong reflection effect of the reflective electrode is utilized, so that the light emitted directly from the organic light-emitting layer interacts with the light reflected by the reflective electrode. The light interferes with each other, increasing the color gamut of the emitted light and enhancing the brightness of the emitted light.
  • the display area 100 The second insulating layer 15 forms a plurality of third via holes, the second insulating layer 15 of the dummy pixel area 200 forms a plurality of fourth via holes, the second insulating layer 15 of the cathode ring area 300 forms at least one fifth via hole, and more A plurality of third via holes respectively expose the first reflective electrode 141 of the display area 100 , a plurality of fourth via holes respectively expose the second reflective electrode 142 of the dummy pixel area 200 , and a fifth via hole exposes the first reflective electrode 141 of the cathode ring area 300 .
  • Three reflective electrodes 143 Subsequently, a plurality of third conductive pillars 16A are formed in the third via holes on the second insulating layer 15, and a plurality of fourth conductive pillars 16B are formed in the fourth via holes on the second insulating layer 15. A plurality of fifth conductive pillars 16C are formed in the fifth via hole on layer 15. The third conductive pillar 16A in the third via hole is connected to the first reflective electrode 141 of the display unit.
  • the fourth conductive pillar 16C in the fourth via hole is The pillar 16B is connected to the second reflective electrode 142 of the dummy pixel area 200, and the fifth conductive pillar 16C in the fifth via hole is connected to the third reflective electrode 143 of the cathode ring area 300, as shown in FIG. 10 .
  • the third conductive pillar 16A, the fourth conductive pillar 16B and the fifth conductive pillar 16C may be made of a metal material and formed through a filling process. After the pillars 16C are removed, a polishing process can also be performed.
  • the surfaces of the second insulating layer 15, the third conductive pillar 16A, the fourth conductive pillar 16B and the fifth conductive pillar 16C are corroded and rubbed through the polishing process to remove the second insulating layer 15. , the partial thickness of the third conductive pillar 16A, the fourth conductive pillar 16B and the fifth conductive pillar 16C, so that the second insulating layer 15, the third conductive pillar 16A, the fourth conductive pillar 16B and the fifth conductive pillar 16C form a flush surface.
  • the third conductive pillar 16A, the fourth conductive pillar 16B and the fifth conductive pillar 16C may be made of metal tungsten (W).
  • a composite metal film and a transparent conductive film are sequentially deposited on the silicon-based substrate 10 forming the aforementioned structure, and the composite metal film and transparent conductive film are patterned through a patterning process.
  • An anode layer pattern is formed on the second insulating layer 15 of the area 300.
  • the anode layer includes a display anode 31A provided in the display area 100, a dummy anode 31B provided in the dummy pixel area 200, and a cathode voltage line 32 provided in the cathode ring area 300.
  • the display anode 31A is connected to the first reflective electrode 141 through the third conductive pillar 16A
  • the dummy anode 31B is connected to the second reflective electrode 142 through the fourth conductive pillar 16B
  • the cathode voltage line 32 is connected to the third reflective electrode through the fifth conductive pillar 16C. 143 connection, as shown in Figure 11.
  • the display anode 31A is connected to the first reflective electrode 141 through the third conductive pillar 16A
  • the first reflective electrode 141 is connected to the drain electrode of the driving thin film transistor 11 through the first conductive pillar 13A. In this way, the voltage provided by the pixel driving circuit The signal is transmitted to the display anode 31A through the first reflective electrode 141.
  • the first reflective electrode 141 forms a conductive channel between the pixel driving circuit and the anode, and on the other hand, forms a microcavity structure, which not only facilitates the control of the light-emitting device by the pixel driving circuit, but also makes the structure of the display substrate more compact, which is beneficial to Miniaturization of silicon-based OLED display devices.
  • the cathode voltage line 32 is connected to the third reflective electrode 143 through the fifth conductive pillar 16C, and the third reflective electrode 143 is connected to the power supply electrode 301 through the second conductive pillar 13B, so that the low voltage signal provided by the power supply electrode 301 It is transmitted to the cathode voltage line 32 through the third reflective electrode 143 .
  • the material of the anode layer may include a composite metal layer and a transparent oxide layer sequentially provided on the silicon-based substrate 10 , or may only include a single layer of composite metal layer or a single layer of transparent oxide layer.
  • the composite metal layer may include titanium/aluminum/titanium (Ti/Al/Ti); the transparent oxide layer may be indium tin oxide (ITO).
  • the composite metal layer and the transparent oxide layer can be formed by being deposited separately in two chambers and then etched in one step.
  • the cathode voltage line 32 includes a plurality of first cathode voltage lines 320 and a plurality of second cathode voltage lines 321, and each second cathode voltage line 321 is disposed between two adjacent first cathode voltage lines 320. Connected to two adjacent first cathode voltage lines 320 .
  • the second pixel definition layer 33 is provided with a first pixel opening, and the first pixel opening exposes the surface of the display anode 31A.
  • the second pixel definition layer 33 is provided with a first pixel opening. There are two pixel openings, and the second pixel opening exposes the surface of the dummy anode 31B.
  • the second pixel definition layer 33 has a third opening, and the third opening exposes part of the surface of the cathode voltage line 32.
  • the first pixel opening is used to limit the anode opening ratio.
  • the second pixel opening is mainly used to increase the etching uniformity of the display area 100 and the dummy pixel area 200.
  • the third opening can prevent the metal in the cathode voltage line 32 from being corroded.
  • the first pixel definition layer 17 is disposed in the space between adjacent anode blocks, and the second pixel definition layer 33 is disposed on a side of the first pixel definition layer 17 away from the silicon-based substrate 10 and covers the first pixel definition layer 17 .
  • Pixel definition layer 17. In this way, the first pixel definition layer 17 can be prevented from being etched again.
  • Steps (6) and (7) in the embodiment of the present disclosure can also be combined into one step, that is, only a single layer of pixel definition layer is formed, and the embodiment of the present disclosure does not limit this.
  • the pixel definition layer includes a plurality of pixel definition islands (distributed in an island shape). Each pixel definition island is disposed between two adjacent first cathode voltage lines 320 and two adjacent second cathode voltage lines 320. within the area enclosed by the cathode voltage line 321.
  • the pixel definition island is not only beneficial to cathode bonding (reducing cathode bonding resistance), but also has an uneven structure (in the embodiment of the present disclosure, part of the pixel definition island covers part of the cathode voltage line, and the other part of the pixel definition island covers the first etching area , the height of the pixel definition island covering part of the cathode voltage line from the substrate is larger than the height of the pixel definition island covering the first etching area from the substrate), which is also beneficial to the subsequent thin film packaging structure.
  • the display light-emitting layer 34A and the dummy light-emitting layer 34B are formed in the display area 100 and the dummy pixel area 200 respectively, and then the cathode 35 is formed in the display area 100, the dummy pixel area 200 and the cathode ring area 300.
  • the cathode 35 can be Overall shape.
  • the display luminescent layer 34A is connected to the display anode 31A through the first pixel opening, and the cathode 35 is connected to the display luminescent layer 34A; in the dummy pixel area 200, the dummy luminescent layer 34B is connected to the dummy anode 31B through the second pixel opening, The cathode 35 is connected to the dummy light-emitting layer 34B; in the cathode ring area 300, the cathode 35 is connected to the cathode voltage line 32 through the third opening, as shown in FIG. 13 .
  • the cathode 35 is a semi-transparent and semi-counter electrode, and forms a microcavity structure with the first reflective electrode 141 formed above.
  • the first insulating film, the second insulating film and the third insulating film can be made of silicon oxide (SiOx), silicon nitride (SiNx) or silicon oxynitride (SiON), and can be a single-layer structure, or can be It is a multi-layer composite structure.
  • the first metal film can be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al) or molybdenum (Mo), or can be made of alloy materials composed of metals, such as aluminum-neodymium alloy (AlNd) or molybdenum.
  • Niobium alloy MoNb
  • the alloy material can be a single-layer structure, or it can be a multi-layer composite structure, such as a Mo/Cu/Mo composite structure.
  • the transparent conductive film can use indium tin oxide (ITO) or indium zinc oxide (IZO), or a composite structure of ITO/Ag/ITO.
  • the pixel definition layer can use polyimide, acrylic or polyethylene terephthalate. wait.
  • a first encapsulation layer 40 pattern is formed in the display area 100, the dummy pixel area 200 and the cathode ring area 300.
  • the first encapsulation layer 40 is a thin film encapsulation structure, as shown in Figure 14 shown.
  • a color filter layer 50 pattern is formed in the display area 100, the dummy pixel area 200, the cathode ring area 300 and part of the metal wiring area 400.
  • the color filter layer of the display area 100 50 includes a first color unit 53, a second color unit 54 and a third color unit 55 arranged at intervals or overlapping each other.
  • the color units of the display area 100 may overlap each other as black. matrix, or set a black matrix between color cells.
  • the color filter layer 50 of the dummy pixel area 200 and the cathode ring area 300 may include a first color unit 53 and a second color unit 54 arranged in a stack, as shown in FIG. 6A .
  • the first color unit may be a green unit G
  • the second color unit may be a red unit R
  • the third color unit may be a blue unit B.
  • the preparation process of the color filter layer 50 includes: first forming the blue unit B, then forming the red unit R, and then forming the green unit G.
  • the blue color film has greater adhesion. Forming the blue unit B first can reduce the possibility of the color film layer 50 being peeled off from the cathode.
  • the red unit R has less adhesion but good fluidity, in the process of forming the red unit R, the number of bubbles on the surface of the blue unit B and the red unit R away from the cathode can be reduced, thereby improving the blue color Uniformity of film thickness where unit B and red unit R overlap. Since the base material of the green unit G and the red unit R are approximately the same, the adhesion force between the green unit G and the red unit R is relatively large, which can reduce the possibility of the color filter layer 50 being peeled off from the cathode. In some possible implementations, the color filter layer 50 may include other color units, such as white or yellow.
  • a second encapsulation layer pattern is formed in the display area 100, the dummy pixel area 200 and the cathode ring area 300.
  • a sealing process is used to form a cover plate, and the cover plate and the silicon-based substrate 10 are fixed by sealant. Since the silicon-based substrate 10, the cover plate and the sealant together form a closed space, they provide a guarantee of blocking water and oxygen, greatly extending the life of the silicon-based OLED display substrate.
  • the formed display motherboard is cut to form individual display substrates.
  • the present disclosure can ensure both the etching load (Loading) of the cathode voltage line in the cathode ring region 300 and the The display anode etching load in the display area is close to that of the display area, which can also improve the problem of overlap between the cathode voltage line and the cathode metal, reduce the cathode overlap resistance, reduce the IR Drop in the display area, and improve the display effect.
  • the preparation process of the present disclosure can be realized using mature preparation equipment.
  • the preparation process is simple and does not increase the mask process. It can be realized only by revising the metal arrangement of the cathode ring. It has high compatibility, simple process flow, and is easy to perform periodic equipment maintenance and production. It has high efficiency, low production cost, high yield, and is convenient for large-scale mass production.
  • the prepared display substrate can be used in virtual reality equipment or enhanced display equipment, or in other types of display devices, and has good application prospects.
  • the structure and its preparation process shown in the present disclosure are only illustrative. In the exemplary embodiment, the corresponding structure can be changed and the patterning process can be added or reduced according to actual needs, and the present disclosure is not limited here.
  • FIG. 15 is another enlarged structural schematic diagram of area B in FIG. 5 .
  • at least one first cathode voltage line 320 includes first sub-sections 320_1 and second sub-sections 320_2 that are alternately arranged along the first direction X and connected to each other.
  • the shape of the portion 320_1 is the same as the shape of the display anode 31A.
  • the orthographic projection of the first sub-portion 320_1 on the silicon-based substrate 10 covers the orthographic projection of the second conductive pillar 13B on the silicon-based substrate 10 .
  • the shape of the first sub-section 320_1 and the shape of the display anode 31A are both regular hexagonal shapes, however, the embodiments of the present disclosure are not limited to this.
  • the second sub-part 320_2 is a connection structure provided between two first sub-parts 320_1 adjacent along the first direction X.
  • the second cathode voltage line 321 is a connection structure provided between two adjacent first sub-portions 320_1 along the second direction Y.
  • the present disclosure also provides a method for preparing a display substrate.
  • the display device includes a display area and a cathode ring area located outside the display area.
  • the preparation method includes the following steps:
  • a silicon-based substrate which contains a pixel driving circuit and a power supply electrode;
  • the insulating layer includes a first conductive pillar and a second conductive pillar.
  • the light-emitting structure layer includes an anode layer, a pixel definition layer, an organic light-emitting layer and a cathode.
  • the anode layer includes a display anode located in the display area and a cathode voltage line located in the cathode ring area, the cathode is connected to the cathode voltage line, and the display anode is connected to the pixel through the first conductive pillar.
  • the cathode voltage lines include a plurality of first cathode voltage lines and a plurality of second cathode voltage lines, the first cathode voltage lines extend along a first direction, and the second cathode voltage lines extend along a second direction Extending, the first direction is a direction parallel to the edge of the display substrate, and the second direction intersects the first direction; at least one second cathode voltage line is disposed between two adjacent second cathode voltage lines.
  • the cathode voltage line is connected to the power supply electrode through the second conductive pillar, and the cathode voltage line is connected to the
  • the orthographic projection on the substrate covers the orthographic projection of the second conductive pillar on the substrate.
  • the present disclosure also provides a display device, including the display substrate described in any of the preceding embodiments.
  • the display device may be a virtual reality device, an augmented reality device or a near-eye display device, or it may be a mobile phone, a tablet computer, a television, a monitor, a laptop, a digital photo frame or a navigator, or any other product or component with a display function.

Landscapes

  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示基板，包括显示区域(100)和阴极环区域(300)；还包括依次设置在衬底(10)上的绝缘层(15)和发光结构层(20)，发光结构层(20)包括阳极层、像素定义层、发光层和阴极(35)，阳极层包括位于显示区域(100)的显示阳极(31A)和位于阴极环区域(300)的阴极电压线(32)，阴极(35)与阴极电压线(32)连接；阴极电压线(32)包括第一阴极电压线(320)和第二阴极电压线(321)，第一阴极电压线(320)沿第一方向(X)延伸，第二阴极电压线(321)沿第二方向(Y)延伸，第一方向(X)为平行于显示基板的边沿的方向，至少一条第二阴极电压线(321)设置在相邻两条第一阴极电压线(320)之间，且与相邻的两条第一阴极电压线(320)连接。

Description

显示基板及其制备方法、显示装置 技术领域
本公开实施例涉及但不限于显示技术领域，尤其涉及一种显示基板及其制备方法、显示装置。
背景技术
微型有机发光二极管(Micro Organic Light-Emitting Diode，简称Micro-OLED)是近年来发展起来的微型显示器，硅基OLED是其中的一种。硅基OLED不仅可以实现像素的有源寻址，并且可以实现在硅基衬底上制备像素驱动电路等结构，有利于减小系统体积，实现轻量化。硅基OLED采用成熟的互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，简称CMOS)集成电路工艺制备，具有体积小、高分辨率(Pixels Per Inch，简称PPI)、高刷新率等优点，广泛应用在虚拟现实(Virtual Reality，简称VR)或增强现实(Augmented Reality，简称AR)近眼显示领域中。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种显示基板，包括衬底以及设置在所述衬底上的显示区域和阴极环区域，所述阴极环区域位于所述显示区域的外侧；在垂直于所述显示基板的平面上，所述显示基板包括设置在所述衬底上的绝缘层和设置在所述绝缘层上的发光结构层，所述发光结构层包括阳极层、像素定义层、发光层和阴极，所述阳极层包括位于所述显示区域的多个显示阳极和位于所述阴极环区域的阴极电压线，所述阴极与所述阴极电压线连接，所述衬底包括供电电极和像素驱动电路，所述绝缘层包括第一导电柱和第二导电柱，所述显示阳极通过所述第一导电柱与所述像素驱动电路连接；所述阴极电压线包括多条第一阴极电压线和多条第二阴极电压线，所述第一阴极电压线沿 第一方向延伸，所述第二阴极电压线沿第二方向延伸，所述第一方向为平行于所述显示基板的边沿的方向，所述第二方向与所述第一方向相交；至少一条所述第二阴极电压线设置在相邻两条所述第一阴极电压线之间，且与相邻的两条所述第一阴极电压线连接；所述阴极电压线通过所述第二导电柱与所述供电电极连接，所述阴极电压线在所述衬底上的正投影覆盖所述第二导电柱在所述衬底上的正投影。
本公开实施例还提供了一种显示装置，包括：如本公开任一实施例所述的显示基板。
本公开实施例还提供了一种显示基板的制备方法，所述显示基板包括显示区域以及位于显示区域外侧的阴极环区域，所述制备方法包括：
提供衬底，所述衬底内包含像素驱动电路和供电电极；
在所述衬底上依次形成绝缘层和发光结构层，所述绝缘层包括第一导电柱和第二导电柱，所述发光结构层包括阳极层、像素定义层、有机发光层和阴极，所述阳极层包括位于所述显示区域的显示阳极和位于所述阴极环区域的阴极电压线，所述阴极与所述阴极电压线连接，所述显示阳极通过所述第一导电柱与所述像素驱动电路连接；所述阴极电压线包括多条第一阴极电压线和多条第二阴极电压线，所述第一阴极电压线沿第一方向延伸，所述第二阴极电压线沿第二方向延伸，所述第一方向为平行于所述显示基板的边沿的方向，所述第二方向与所述第一方向相交；至少一条所述第二阴极电压线设置在相邻两条所述第一阴极电压线之间，且与相邻的两条所述第一阴极电压线连接；所述阴极电压线通过所述第二导电柱与所述供电电极连接，所述阴极电压线在所述衬底上的正投影覆盖所述第二导电柱在所述衬底上的正投影。
在阅读并理解了附图和详细描述后，可以明白其它方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中每个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种硅基OLED显示装置的结构示意图；
图2为一种硅基OLED显示装置的平面结构示意图；
图3为一种硅基OLED显示装置中显示区域的平面结构示意图；
图4A为一种像素驱动电路的等效电路图；
图4B为一种像素驱动电路的工作时序图；
图5为本公开示例性实施例一种硅基OLED显示基板的结构示意图；
图6A为图5中AA’方向的剖面结构示意图；
图6B、图6C、图6D和图6E为图5中B区域的四种放大结构示意图；
图6F为制备完阳极层后的一种显示基板平面示意图；
图6G为制备完像素定义层后的一种显示基板平面示意图；
图7为本公开实施例形成硅基衬底后的示意图；
图8为本公开实施例形成第一绝缘层后的示意图；
图9为本公开实施例形成反射层后的示意图；
图10为本公开实施例形成第二绝缘层图案后的示意图；
图11为本公开实施例形成阳极层图案后的示意图；
图12为本公开实施例形成第一像素定义层图案后的示意图；
图13为本公开实施例形成阴极图案后的示意图；
图14为本公开实施例形成封装层图案后的示意图；
图15为图5中B区域的另一种放大结构示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在 不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示装置中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，为了区分晶体管除控制极之外的两极，直接描述了其中一极为第一极，另一极为第二极，其中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
在本说明书中，所采用的“同层设置”是指两种(或两种以上)结构通过同一次图案化工艺得以图案化而形成的结构，它们的材料可以相同或不同。例如，形成同层设置的多种结构的前驱体的材料是相同的，最终形成的材料可以相同或不同。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种硅基OLED显示装置的结构示意图。如图1所示，硅基OLED显示装置可以包括时序控制器、数据信号驱动器、扫描信号驱动器和像素阵 列，像素阵列可以包括多个扫描信号线(S1到Sm)、多个数据信号线(D1到Dn)和多个子像素Pxij。在示例性实施方式中，时序控制器可以将适合于数据信号驱动器的规格的灰度值和控制信号提供到数据信号驱动器，可以将适合于扫描信号驱动器的规格的时钟信号、扫描起始信号等提供到扫描信号驱动器。数据信号驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据信号驱动器可以利用时钟信号对灰度值进行采样，并且以子像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描信号驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描信号驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描信号驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。子像素阵列可以包括多个像素子Pxij。每个像素子Pxij可以连接到对应的数据信号线和对应的扫描信号线，i和j可以是自然数。子像素Pxij可以指其中晶体管连接到第i扫描信号线且连接到第j数据信号线的子像素。
图2为一种硅基OLED显示装置的平面结构示意图。如图2所示，在平行于硅基OLED显示装置的平面上，硅基OLED显示装置可以包括显示区域100和位于显示区域100外侧的虚设像素区域200。在示例性实施方式中，显示区域100是进行图像显示的有效区域(AA)，可以包括组成像素阵列的多个子像素，子像素可以包括像素驱动电路和显示发光器件，多个子像素被配置为显示动态图片或静止图像。在示例性实施方式中，虚设像素区域200位于显示区域100的外围，可以包括多个虚设发光器件，多个虚设发光器件被配置为呈现显示发光器件的形貌，但不进行图像显示。
在示例性实施方式中，硅基OLED显示装置还可以包括阴极环区域300，阴极环区域300可以位于虚设像素区域200的外围，即，虚设像素区域200位于显示区域100与阴极环区域300之间。在示例性实施方式中，阴极环区域300可以包括阴极电压线，阴极电压线被配置为提供公共电压(VCOM)。 阴极电压线可以形成围绕虚设像素区域200的环形结构，环形结构的阴极电压线可以称为阴极环。
图3为一种硅基OLED显示装置中显示区域的平面结构示意图。如图3所示，显示区域可以包括以矩阵方式排布的多个像素单元P，多个像素单元P的至少一个包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3，第一子像素P1、第二子像素P2和第三子像素P3均包括像素驱动电路和发光器件。子像素中的像素驱动电路分别与扫描信号线和数据信号线连接，像素驱动电路被配置为在扫描信号线的控制下，接收数据信号线传输的数据电压，向显示发光器件输出相应的电流。子像素中的显示发光器件分别与所在子像素的像素驱动电路连接，显示发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色(R)光线的红色子像素、第二子像素P2可以是出射蓝色(B)光线的蓝色子像素，第三子像素P3可以是出射绿色(G)光线的绿色子像素。在示例性实施方式中，子像素的形状可以是三角形、正方形、矩形、菱形、梯形、平行四边形、五边形、六边形和其它多边形中的任意一种或多种，可以采用水平并列、竖直并列、X形、十字形、品字形、正方形、钻石形或者delta等方式排列，本公开在此不做限定。
在示例性实施方式中，像素单元可以包括四个子像素，本公开在此不做限定。
图4A为本公开示例性实施例一种像素驱动电路的等效电路图。在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C或7T1C等结构。如图4A所示，像素驱动电路可以包括3个晶体管(第一晶体管T1到第三晶体管T3)和1个存储电容C，像素驱动电路与5个信号线(扫描信号线S、数据信号线D、参考信号线REF、第一电源线VDD和阴极电压线VSS)连接，第一节点N1和第二节点N2是表示电路图中相关电连接的汇合点。
在示例性实施方式中，存储电容C的第一端与第一节点N1连接，存储 电容C的第二端与阴极电压线VSS连接。
在示例性实施方式中，第一晶体管T1的控制极与扫描信号线S连接，第一晶体管T1的第一极与数据信号线D连接，第一晶体管T1的第二极与第一节点N1连接。
在示例性实施方式中，第二晶体管T2的控制极与参考信号线REF连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与显示发光器件XL的第一极连接，显示发光器件XL的第二极与阴极电压线VSS连接。
在示例性实施方式中，第三晶体管T3的控制极与第一节点N1连接，第三晶体管T3的第一极与第一电源线VDD连接，第三晶体管T3的第二极与第二节点N2连接。
在示例性实施方式中，第一电源线VDD的信号可以为持续提供的高电平信号，阴极电压线VSS的信号可以为持续提供的低电平信号，参考信号线REF可以为持续提供低电平信号，或者可以为可变的电压信号。
在示例性实施方式中，第一晶体管T1被配置为在扫描信号线S的信号的控制下，接收数据信号线D传输的数据电压，将数据电压存储至存储电容C，并向第三晶体管T3的第一控制极提供数据电压，第二晶体管T2被配置为在参考信号线REF的信号的控制下，将第二节点N2的电压信号提供给显示发光器件XL的第一极，第三晶体管T3被配置为在第一节点N1的信号的控制下，向第二节点N2提供第一电源线VDD的信号，以驱动显示发光器件XL发光。
在一种示例性实施方式中，第一晶体管T1、第二晶体管T2和第三晶体管T3可以是P型晶体管。在另一种示例性实施方式中，第一晶体管T1、第二晶体管T2和第三晶体管T3可以是N型晶体管。在又一种示例性实施方式中，第一晶体管T1、第二晶体管T2和第三晶体管T3可以包括P型晶体管和N型晶体管。例如，第一晶体管T1和第二晶体管T2可以为P型金属氧化物半导体晶体管(PMOS)，第三晶体管T3可以为N型金属氧化物半导体晶体管(NMOS)。在示例性实施方式中，显示发光器件XL可以是OLED，或者可以是QLED等，本公开在此不做限定。
在示例性实施方式中，多个像素驱动电路可以设置在显示区域，显示区域的外围(例如，虚设像素区域或其他区域)可以设置辅助电路。示例性的，辅助电路可以包括复位子电路，复位子电路与第二节点N2、放电信号线和初始信号线连接，复位子电路被配置为在放电信号线的信号的控制下，向第二节点N2提供初始信号线提供的初始电压。
图4B为一种像素驱动电路的工作时序图。下面通过图4A示例的像素驱动电路的工作过程说明本公开示例性实施例。图4A示例的像素驱动电路中,第一晶体管T1和第二晶体管T2为P型晶体管，第三晶体管T3为N型晶体管。
在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段S1，称为复位阶段或初始化阶段。此阶段中，扫描信号线S的信号为高电平信号，数据信号线D的信号为低电平信号，参考信号线REF的信号为低电平信号，第一电源线VDD的信号为低电平信号。复位子电路向第二节点N2提供初始电压，参考信号线REF的低电平信号使得P型的第二晶体管T2导通，使得初始电压经过导通的第二晶体管T2提供至显示发光器件XL的第一极，对显示发光器件XL进行初始化，可以快速泄放(清空)显示发光器件XL第一极存储的电荷，确保显示发光器件XL不发光，并可以实现较好的动态对比度。此阶段中，扫描信号线S的高电平信号使得P型的第一晶体管T1断开。
第二阶段S2，称为数据写入阶段。此阶段中，扫描信号线S的信号为低电平信号，数据信号线D的信号为高电平信号，参考信号线REF的信号为低电平信号，第一电源线VDD的信号为低电平信号。扫描信号线S的低电平信号使得P型的第一晶体管T1导通，数据信号线D的数据电压经过导通的第一晶体管T1提供至第一节点N1，对存储电容C进行充电，使得数据信号线D输出的数据电压被存储在存储电容C中。
第三阶段S3，称为发光阶段。此阶段中，扫描信号线S的信号为高电平信号，数据信号线D的信号为低电平信号，参考信号线REF的信号为低电平信号，第一电源线VDD的信号为高电平信号。扫描信号线S的高电平信号使得P型的第一晶体管T1断开，存储电容C存储的数据电压提供至第一 节点N1，第一节点N1的电位为数据信号线D的数据电压，使得N型的第三晶体管T3导通。参考信号线REF的低电平信号使得P型的第二晶体管T2导通，使得第一电源线VDD输出的高电平信号经过导通的第三晶体管T3和第二晶体管T2提供至显示发光器件XL的第一极，使得显示发光器件XL发光。
在示例性实施方式中，在像素驱动电路驱动过程中，流过第三晶体管T3(称为驱动晶体管)的驱动电流由第三晶体管T3的控制极和第三晶体管T3的第一极之间的电压差决定，第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vdate)-Vth] 2
其中，I表示流过第三晶体管T3的驱动电流，K表示常数，Vgs表示第三晶体管T3的栅电极和第一极之间的电压差，Vth表示第三晶体管T3的阈值电压，Vdate表示数据信号线D提供的数据电压，Vdd表示第一电源线VDD输出的电源电压。
图5为本公开示例性实施例一种硅基OLED显示基板的结构示意图。如图5所示，在示例性实施方式中，在平行于硅基OLED显示基板的平面上，硅基OLED显示基板可以包括显示区域100、位于显示区域100外围的阴极环区域300以及位于显示区域100和阴极环区域300之间的虚设像素区域200。
在示例性实施方式中，显示区域100可以包括多个像素驱动电路和多个显示发光器件P a，显示发光器件P a可以包括显示阳极、阴极以及设置在显示阳极和阴极之间的显示发光层，多个显示发光器件P a的显示阳极与多个像素驱动电路对应连接。
在示例性实施方式中，虚设像素区域200可以包括多个虚设发光器件P b，虚设发光器件P b可以包括虚设阳极、阴极以及设置在虚设阳极和阴极之间的虚设发光层，多个虚设发光器件P b的虚设阳极可以为浮置(Floating)状态，无电性连接，或者，多个虚设发光器件P b的虚设阳极和阴极可以均与阴极电压线连接，两者具有相同的电位，因而，可以保证虚设发光器件P b不会发光。
在示例性实施方式中，阴极环区域300可以包括阴极电压线和阴极，阴极电压线通过像素定义层开口与阴极连接，阴极电压线被配置为提供公共电压(VCOM)。阴极电压线可以位于虚设发光器件P b远离显示区域100的一 侧，并可以形成围绕虚设发光器件P b的环形结构，环形结构的阴极电压线可以称为阴极环。
在一些显示面板中，当阴极电压线通过像素定义层开口与阴极连接时，阴极在像素定义层开口的侧壁斜面处变薄，电阻增大，整面的阴极与多条阴极电压线的搭接结构可以理解为沿着远离显示区域方向的电阻串联结构，从而进一步增大了阴极搭接电阻，影响了显示区域的电压降(IR DROP)，严重时还会造成显示器件黑屏。
图6A为图5中AA’方向的剖面结构示意图，图6A中的显示发光器件P a示意了一种采用白光+彩膜方式实现全彩的结构。如图6A所示，硅基OLED显示装置可以包括：硅基衬底10，显示区域100的硅基衬底10集成有像素驱动电路，阴极环区域300的硅基衬底10集成有供电电极，设置在硅基衬底10上的发光结构层20，设置在发光结构层20远离硅基衬底10一侧的第一封装层40，设置在第一封装层40远离硅基衬底10一侧的彩膜结构层50，设置在彩膜结构层50远离硅基衬底10一侧的第二封装层(图中未示出)，以及设置在第二封装层远离硅基衬底10一侧的盖板层(图中未示出)。在一些可能的实现方式中，硅基OLED显示装置可以包括其它膜层，本公开在此不做限定。
在示例性实施方式中，硅基衬底10可以为体硅基底或者绝缘层上硅(SOI，Silicon-On-Insulator)基底。像素驱动电路和供电电路可以通过硅半导体工艺(例如CMOS工艺)制备在硅基衬底10上，像素驱动电路分别与扫描信号线和数据信号线连接，像素驱动电路可以包括多个晶体管和存储电容，图6A中仅以一个晶体管作为示例。晶体管可以包括控制极G、第一极S和第二极D，控制极G、第一极S和第二极D可以通过钨金属填充的过孔(即钨过孔，W-via)分别与相应的连接电极连接，并可以通过连接电极与其它电学结构(如走线等)进行连接。
在示例性实施方式中，显示区域100的发光结构层20可以包括显示阳极31A、像素定义层、显示发光层34A和阴极35，显示阳极31A可以通过连接电极(第一反射电极141)与晶体管的第二极D连接，像素定义层设置有第一像素开口，第一像素开口暴露出至少部分显示阳极31A，显示发光层34A 通过第一像素开口与显示阳极31A连接，阴极35与显示发光层34A连接，显示发光层34A在显示阳极31A和阴极35驱动下出射光线。在示例性实施方式中，显示发光层34A可以包括发光层(简称EML)，以及如下任意一种多种：空穴注入层(HIL)、空穴传输层(HTL)、电子阻挡层(EBL)、空穴阻挡层(HBL)、电子传输层(ETL)和电子注入层(EIL)。在示例性实施方式中，对于出射白光的发光器件，所有子像素的显示发光层34A可以是连接在一起的共通层。
在示例性实施方式中，虚设像素区域200的发光结构层20可以包括虚设阳极31B、像素定义层、虚设发光层34B和阴极35，虚设阳极31B可以为浮置(Floating)状态，无电性连接，像素定义层设置有第二像素开口，第二像素开口暴露出至少部分虚设阳极31B，虚设发光层34B通过第二像素开口与虚设阳极31B连接，阴极35与虚设发光层34B连接。
在示例性实施方式中，阴极环区域300的发光结构层20可以包括阴极电压线32、像素定义层和阴极35，像素定义层设置有第三开口，第三开口暴露出至少部分阴极电压线32，阴极电压线32通过第三开口与阴极35连接，阴极电压线32通过连接电极(第三反射电极143)与供电电极301连接，被配置为提供公共电压(VCOM)。
在示例性实施方式中，第一封装层40和第二封装层(图中未示出)可以采用薄膜封装(Thin Film Encapsulation，简称TFE)方式，可以保证外界水汽无法进入发光结构层，盖板层(图中未示出)可以采用玻璃，或者采用具可挠特性的塑胶类无色聚酰亚胺等。
在示例性实施方式中，彩膜结构层50可以包括黑矩阵(BM)和彩色滤光片(CF)，彩色滤光片的位置可以与发光器件的位置相对应，黑矩阵可以位于相邻的彩色滤光片之间，彩色滤光片被配置为将发光器件出射的白光过滤成红色(R)光、绿色(G)光和蓝色(B)光，形成红色子像素、绿色子像素和蓝色子像素。
图6B、图6C、图6D和图6E为图5中B区域的四种放大结构示意图。如图6A、图6B、图6C、图6D和图6E所示，显示基板包括：硅基衬底10、依次设置在硅基衬底10上的阳极层、像素定义层、有机发光层和阴极，其中： 阳极层包括设置在显示区域100的显示阳极31A和设置在阴极环区域300的阴极电压线32，阴极电压线32包括多条第一阴极电压线320和多条第二阴极电压线321，每条第二阴极电压线321设置在相邻两条第一阴极电压线320之间且与相邻的两条第一阴极电压线320连接。
本公开实施例中的显示基板的衬底除硅基衬底10外，也可以使用其他材质的衬底，本公开实施例对此不作限制。
在示例性实施方式中，如图6B和图6C所示，多条第一阴极电压线320沿第一方向X延伸，多条第二阴极电压线321沿第二方向Y延伸，第一方向X和第二方向Y相交。
在示例性实施方式中，对于显示装置左右方向的两侧，第一方向X为行方向，第二方向Y为列方向。对于显示装置上下方向的两侧，第一方向X为列方向，第二方向Y为行方向。即第一方向X为平行于显示基板的边沿的方向。
在示例性实施方式中，第一方向X和第二方向Y相互垂直。
在示例性实施方式中，如图6A所示，硅基衬底10包括供电电极301，阴极电压线32通过金属过孔(即后文所述的第二导电柱13B和第五导电柱16C，在另一些示例性实施方式中，当没有设置反射层时，金属过孔即后文所述的第二导电柱13B)与供电电极301连接。示例性的，金属过孔可以为钨孔。
如图6B至6E所示，本公开实施例中，阴极电压线32通过金属过孔与供电电极301连接，可以是第一阴极电压线320通过金属过孔与供电电极301连接，也可以是第二阴极电压线321通过金属过孔与供电电极301连接，金属过孔的具体位置可以根据实际电连接需要进行调整，例如位于第一阴极电压线320覆盖的区域内或者位于相邻第一阴极电压线320之间的第二阴极电压线321覆盖的区域内，本公开实施例对此不作限制。
在示例性实施方式中，在平行于显示基板的平面上，金属过孔的长度可以在0.3um至0.5um之间，金属过孔的宽度可以在0.3um至0.5um之间。示例性的，金属过孔的长度可以为0.4um，金属过孔的宽度可以为0.4um。
在示例性实施方式中，如图6B和图6C所示，阴极电压线32在硅基衬底10上的正投影覆盖金属过孔在硅基衬底10上的正投影。
在示例性实施方式中，如图6E所示，第一阴极电压线320沿垂直于第一方向X的方向上的宽度b1大于第二阴极电压线321沿垂直于第二方向Y的方向上的宽度b2。
在示例性实施方式中，如图6B至6E所示，在阴极环区域300靠近显示区域100的一侧，阴极电压线32形成第一锯齿形结构边沿320_1，且像素定义层在衬底10上的正投影覆盖第一锯齿形结构边沿320_1在衬底10上的正投影。
在一些示例性实施方式中，如图5、图6A至图6D所示，阳极层还包括位于虚设像素区域200的虚设阳极31B，虚设阳极31B靠近阴极环区域300的一侧形成第二锯齿形结构边沿，第一锯齿形结构的边沿与第二锯齿形结构的边沿为互补结构。
在一些示例性实施方式中，如图6E所示，阴极环区域300的像素定义层包括第三开口，第三开口暴露出至少部分第一阴极电压线320和至少部分第二阴极电压线321(图中第三开口的位置即为暴露出的第一阴极电压线320和第二阴极电压线321的位置)，第三开口暴露出的第二阴极电压线321靠近虚设像素区域200一侧的边缘为朝向虚设像素区域200凸起的平滑曲面(即图6E中的虚线框标识的C区域)。
图6F为本公开实施例制备完阳极层后的一种显示基板平面示意图，图6G为本公开实施例制备完像素定义层后的一种显示基板平面示意图，其中，17表示第一像素定义层，33表示第二像素定义层，在一些示例性实施方式中，像素定义层也可以为单层，本公开实施例对此不作限制。如图6F和6G所示，在阴极环区域300，阳极层包括第一刻蚀区，第一刻蚀区位于相邻第一阴极电压线320以及相邻第二阴极电压线321围成的区域内，阴极环区域300的像素定义层覆盖第一刻蚀区以及位于第一刻蚀区周边的阴极电压线。
本实施例中，第一锯齿形结构边沿320_1所在位置的阴极电压线32由于被像素定义层覆盖，因此，不具有导电性能。只有第三开口暴露出的第一阴极电压线320和第二阴极电压线321具有导电性能，能够起到向阴极35传递 低电压的作用。
在一些示例性实施方式中，如图6A至图6E所示，虚设像素区域200的像素定义层包括第二像素开口，第二像素开口暴露出虚设阳极31B(图中第二像素开口的位置与虚设阳极31B的位置相同)；
阴极电压线靠近虚设像素区域200的一侧的边缘与第二像素开口靠近阴极环区域300的一侧的边缘之间的距离b3，小于第一阴极电压线320沿垂直于第一方向X的方向上的宽度b1。
在一些示例性实施方式中，如图6A至图6D所示，相邻第一阴极电压线320间的距离b4大于第一阴极电压线320沿垂直于第一方向X的方向上的宽度b1。
在一些示例性实施方式中，如图6A至图6D所示，显示区域100的像素定义层包括第一像素开口，第一像素开口暴露出显示阳极31A(图中第一像素开口的位置与显示阳极31A的位置相同)；
阴极环区域300的像素定义层包括第三开口，第三开口的形状与第一像素开口的形状不同。
在一些示例性实施方式中，如图6A至图6D所示，第一阴极电压线320沿垂直于第一方向X的方向上的宽度b1小于第一像素开口沿垂直于第一方向X的方向上的宽度b5。
在示例性实施方式中，如图6B和图6C所示，第一阴极电压线320包括N条，第一条第一阴极电压线320至第N条第一阴极电压线320沿靠近显示区域100的方向依次排布，第二阴极电压线321包括第一子第二阴极电压线321_1至第(N-1)子第二阴极电压线321_N-1，其中，第i子第二阴极电压线321_i设置在第i条第一阴极电压线320与第(i+1)条第一阴极电压线320之间，i为1至N-1之间的自然数。
在示例性实施方式中，如图6B所示，至少存在一条第i子第二阴极电压线321_i和一条第(i+1)子第二阴极电压线321_i+1位于一条直线上。
在示例性实施方式中，如图6B所示，对于任意一条第i子第二阴极电压线321_i，存在一条第(i+1)子第二阴极电压线321_i+1与该第i子第二阴极 电压线321_i位于一条直线上。
在示例性实施方式中，如图6B所示，相邻两条第一阴极电压线320之间的第二阴极电压线321的条数，与每条第一阴极电压线320覆盖的第二导电柱13B的个数相同。
在示例性实施方式中，如图6C所示，任意一条第i子第二阴极电压线321_i和任意一条第(i+1)子第二阴极电压线321_i+1均不位于一条直线上。
在示例性实施方式中，阴极电压线32在硅基衬底10上的正投影的面积与阴极环区域300在硅基衬底10上的正投影的面积的比值，与显示阳极31A在硅基衬底10上的正投影的面积与显示区域100在硅基衬底10上的正投影的面积的比值接近或相同，即，阴极电压线32在阴极环区域300的分布密度和显示阳极31A在显示区域100的分布密度接近相同或相同。本公开实施例中的接近相同，指的是阴极电压线32在阴极环区域300的分布密度和显示阳极31A在显示区域100的分布密度的差值小于预设的差值阈值，该差值阈值可以根据实际需要进行设置，本公开实施例对此不作限制。
在示例性实施方式中，阳极层包括依次设置在硅基衬底10上的复合金属层和透明氧化物层。示例性的，复合金属层包括钛/铝/钛(Ti/Al/Ti)；透明氧化物层为氧化铟锡(ITO)。
在示例性实施方式中，阳极层包括设置在硅基衬底10上的复合金属层或透明氧化物层。
在示例性实施方式中，如图6A、图6B和图6C所示，像素定义层包括第一像素定义层17和第二像素定义层33，第一像素定义层17的表面与阳极层的表面齐平，阳极层包括多个阳极块，阳极块可以为显示阳极31A、虚设阳极31B和阴极电压线32，第一像素定义层17设置在相邻阳极块之间的间隔部中，第二像素定义层33设置在第一像素定义层17远离硅基衬底10的一侧且覆盖第一像素定义层17。如图6F所示，在显示区域100和虚设像素区域200，相邻阳极块之间的间隔部为相邻显示阳极31A之间的区域以及相邻虚设阳极31B之间的区域；在阴极环区域300，相邻阳极块之间的间隔部为相邻第一阴极电压线320以及相邻第二阴极电压线321围成的区域，也即前述的第一刻蚀区。
在示例性实施方式中，如图6B、图6C和图6D所示，在阴极环区域300，像素定义层包括多个像素定义岛，像素定义岛设置在相邻两条第一阴极电压线320和相邻两条第二阴极电压线321围成的区域内。
图6B和图6C中的像素定义岛的形状为圆角矩形，图6D中的像素定义岛的形状为椭圆，然而，本公开实施例对此不作限制，像素定义岛的形状也可以为其他任意的形状。
在另一些示例性实施方式中，在阴极环区域300，也可以存在至少一个像素定义岛，该至少一个像素定义岛没有设置在相邻两条第一阴极电压线320和相邻两条第二阴极电压线321围成的区域内。
在一些示例性实施方式中，如图6B、图6C和图6D所示，像素定义岛与第一阴极电压线320沿第二方向Y的距离b6大于像素定义岛与第二阴极电压线321沿第一方向X的距离b7。
在一些示例性实施方式中，如图6B和图6C所示，像素定义岛的任一顶角与第三开口内的阴极电压线之间的最短距离b8，大于像素定义岛的任一边与第三开口内的阴极电压线之间的最短距离b9。
在示例性实施方式中，在平行于显示基板的平面上，像素定义岛的长度可以在3um至5um之间，像素定义岛的宽度可以在3um至5um之间，相邻像素定义岛之间的间距可以在1um至3um之间，示例性的，相邻像素定义岛之间的间距可以为2um。
在示例性实施方式中，如图6A所示，第二像素定义层33在硅基衬底10上的正投影与显示阳极31A在硅基衬底10上的正投影交叠。
在示例性实施方式中，如图6A所示，显示发光器件P a的显示阳极31A、虚设发光器件P b的虚设阳极31B和阴极环区域300的阴极电压线32可以同层设置，且通过同一次图案化工艺同时形成。
在示例性实施方式中，如图6A所示，显示发光器件P a的显示发光层34A和虚设发光器件P b的虚设发光层34B可以同层设置，且通过同一次蒸镀工艺同时形成。
在示例性实施方式中，如图6A所示，显示发光器件P a的阴极、虚设发 光器件P b的阴极和阴极环区域300的阴极可以同层设置，且为相互连接的一体结构。
下面通过显示装置的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示装置方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，硅基OLED显示装置可以包括显示区域100、位于显示区域100外围的虚设像素区域200以及位于虚设区域区域200远离显示区域100一侧的阴极环区域300。以显示区域包括三个显示单元为例，显示装置的制备过程可以包括以下步骤。
(1)制备硅基衬底10，显示区域100包括多个显示单元，每个显示单元的硅基衬底10集成有像素驱动电路，阴极环区域300的硅基衬底10集成有供电电路，如图7所示。作为一种示例性说明，图7中示意了显示区域100的三个显示单元：第一显示单元、第二显示单元和第三显示单元，示意了像素驱动电路所包括的驱动晶体管11，示意了阴极环区域300的供电电极301。在一示例性实施方式中，显示区域100的驱动晶体管11包括有源层、栅电极、源电极、漏电极和栅连接电极，源电极和漏电极分别通过导电柱与有源层连接，栅连接电极通过导电柱与栅电极连接。制备硅基衬底10可以采用成熟的 CMOS集成电路工艺，本公开对此不作限制。制备完成后，硅基衬底10的表面暴露出显示区域100的源电极、漏电极和栅连接电极以及阴极环区域300的供电电极301。
(2)在硅基衬底10上沉积第一绝缘薄膜，通过构图工艺对第一绝缘薄膜进行构图，形成覆盖硅基衬底10的第一绝缘层12图案，显示区域100的第一绝缘层12形成多个第一过孔，阴极环区域300的第一绝缘层12形成至少一个第二过孔，多个第一过孔分别暴露出每个显示单元的漏电极，第二过孔暴露出供电电极301。随后，在第一绝缘层12上的第一过孔内形成多个第一导电柱13A，在第一绝缘层12上的第二过孔内形成多个第二导电柱13B，第一过孔内的第一导电柱13A与所在显示单元的漏电极连接，第二过孔内的第二导电柱13B与阴极环区域300的供电电极301连接，如图8所示。在示例性实施方式中，第一导电柱13A和第二导电柱13B可以由金属材料制成，通过填充处理形成第一导电柱13A和第二导电柱13B后，还可以进行抛光处理，通过抛光工艺对第一绝缘层12、第一导电柱13A和第二导电柱13B的表面进行腐蚀和摩擦，去除第一绝缘层12、第一导电柱13A和第二导电柱13B的部分厚度，使第一绝缘层12、第一导电柱13A和第二导电柱13B形成平齐的表面。在一些可能的实现方式中，第一导电柱13A和第二导电柱13B可以采用金属钨(W)，由钨金属填充的过孔称为钨过孔(W-via)。在第一绝缘层12厚度较大的情况下，采用钨过孔可以保证导电通路的稳定性，由于制作钨过孔的工艺成熟，所得到的第一绝缘层12的表面平坦度好，有利于降低接触电阻。钨过孔不仅适用于硅基衬底10与反射层之间的连接，还适用于反射层与阳极层之间的连接，以及其它布线层之间的连接。
(3)在形成前述结构的硅基衬底10上沉积第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，在第一绝缘层12上形成反射层图案，反射层包括设置在显示区域100的多个第一反射电极141，设置在虚设像素区域200的多个第二反射电极142，以及设置在阴极环区域300内的多个第三反射电极143，第一反射电极141通过第一导电柱13A与漏电极连接，第二反射电极142不与其他信号线连接，第三反射电极143通过第二导电柱13B与供电电极301连接，如图9所示。在示例性实施方式中，每个显示单元的第一反 射电极141用于与后续形成的阴极构成微腔结构，利用反射电极的强反射效应，使得有机发光层直接出射的光线与反射电极反射的光线相互干涉，提高了出射光的色域，强化了出射光的的亮度。
(4)在形成前述结构的硅基衬底10上沉积第二绝缘薄膜，通过构图工艺对第二绝缘薄膜进行构图，形成覆盖硅基衬底10的第二绝缘层15图案，显示区域100的第二绝缘层15形成多个第三过孔，虚设像素区域200的第二绝缘层15形成多个第四过孔，阴极环区域300的第二绝缘层15形成至少一个第五过孔，多个第三过孔分别暴露出显示区域100的第一反射电极141，多个第四过孔分别暴露出虚设像素区域200的第二反射电极142，第五过孔暴露出阴极环区域300的第三反射电极143。随后，在第二绝缘层15上的第三过孔内形成多个第三导电柱16A，在第二绝缘层15上的第四过孔内形成多个第四导电柱16B，在第二绝缘层15上的第五过孔内形成多个第五导电柱16C，第三过孔内的第三导电柱16A与所在显示单元的第一反射电极141连接，第四过孔内的第四导电柱16B与虚设像素区域200的第二反射电极142连接，第五过孔内的第五导电柱16C与阴极环区域300的第三反射电极143连接，如图10所示。在示例性实施方式中，第三导电柱16A、第四导电柱16B和第五导电柱16C可以由金属材料制成，通过填充处理形成第三导电柱16A、第四导电柱16B和第五导电柱16C后，还可以进行抛光处理，通过抛光工艺对第二绝缘层15、第三导电柱16A、第四导电柱16B和第五导电柱16C的表面进行腐蚀和摩擦，去除第二绝缘层15、第三导电柱16A、第四导电柱16B和第五导电柱16C的部分厚度，使第二绝缘层15、第三导电柱16A、第四导电柱16B和第五导电柱16C形成平齐的表面。在一些可能的实现方式中，第三导电柱16A、第四导电柱16B和第五导电柱16C可以采用金属钨(W)。
(5)在形成前述结构的硅基衬底10上依次沉积复合金属薄膜和透明导电薄膜，通过构图工艺对复合金属薄膜和透明导电薄膜进行构图，在显示区域100、虚设像素区域200和阴极环区域300的第二绝缘层15上形成阳极层图案，阳极层包括设置在显示区域100的显示阳极31A，设置在虚设像素区域200的虚设阳极31B，以及设置在阴极环区域300的阴极电压线32，显示阳极31A通过第三导电柱16A与第一反射电极141连接，虚设阳极31B通 过第四导电柱16B与第二反射电极142连接，阴极电压线32通过第五导电柱16C与第三反射电极143连接，如图11所示。在显示区域100，显示阳极31A通过第三导电柱16A与第一反射电极141连接，第一反射电极141通过第一导电柱13A与驱动薄膜晶体管11的漏电极连接，这样像素驱动电路提供的电信号通过第一反射电极141传输到显示阳极31A。第一反射电极141一方面形成像素驱动电路与阳极之间的导电通道，另一方面形成微腔结构，不仅有利于像素驱动电路对发光器件的控制，而且使显示基板的结构更紧凑，有利于硅基OLED显示装置的微型化。在阴极环区域300，阴极电压线32通过第五导电柱16C与第三反射电极143连接，第三反射电极143通过第二导电柱13B与供电电极301连接，这样供电电极301提供的低电压信号通过第三反射电极143传输到阴极电压线32。
示例性的，阳极层的材料可以包括依次设置在硅基衬底10上的复合金属层和透明氧化物层，也可以只包括单层的复合金属层或单层的透明氧化物层。示例性的，复合金属层可以包括钛/铝/钛(Ti/Al/Ti)；透明氧化物层可以为氧化铟锡(ITO)。复合金属层和透明氧化物层可以通过在两个腔室内分别沉积后一次刻蚀成形。
示例性的，阴极电压线32包括多条第一阴极电压线320和多条第二阴极电压线321，每条第二阴极电压线321设置在相邻两条第一阴极电压线320之间且与相邻的两条第一阴极电压线320连接。
(6)在形成前述结构的硅基衬底10上沉积第三绝缘薄膜，利用刻蚀气体对第三绝缘薄膜进行无差别刻蚀，形成填充在阳极层的间隔中的第一像素定义层17图案，如图12所示。
(7)在形成前述结构的硅基衬底10上涂覆像素定义薄膜，通过掩膜、曝光、显影工艺，在显示区域100、虚设像素区域200和阴极环区域300形成第二像素定义层(PDL)33图案，在显示区域100，第二像素定义层33开设有第一像素开口，第一像素开口暴露出显示阳极31A的表面，在虚设像素区域200，第二像素定义层33开设有第二像素开口，第二像素开口暴露出虚设阳极31B的表面，在阴极环区域300，第二像素定义层33开设有第三开口，第三开口暴露出部分阴极电压线32的表面。通过第一像素开口实现对阳 极开口率的限制，第二像素开口主要用于增加显示区域100与虚设像素区域200的刻蚀均一性，第三开口可以防止阴极电压线32中的金属被腐蚀。
示例性的，第一像素定义层17设置在相邻阳极块之间的间隔部中，第二像素定义层33设置在第一像素定义层17远离硅基衬底10的一侧且覆盖第一像素定义层17。这样，可以防止第一像素定义层17被再次刻蚀。
本公开实施例步骤(6)和步骤(7)也可以合并为一个步骤，即只形成单层的像素定义层，本公开实施例对此不作限制。
示例性的，在阴极环区域300，像素定义层包括多个像素定义岛(呈岛状分布)，每个像素定义岛设置在相邻两条第一阴极电压线320和相邻两条第二阴极电压线321围成的区域内。像素定义岛不仅有利于阴极搭接(降低阴极搭接电阻)，其高低不平结构(本公开实施例中，一部分像素定义岛覆盖部分的阴极电压线，另一部分像素定义岛覆盖第一刻蚀区，覆盖部分的阴极电压线的像素定义岛距离衬底的高度比覆盖第一刻蚀区的像素定义岛距离衬底的高度大一些)也有利于后续的薄膜封装结构。
随后，在显示区域100和虚设像素区域200分别形成显示发光层34A和虚设发光层34B，然后在显示区域100、虚设像素区域200和阴极环区域300形成阴极35，示例性的，阴极35可以为整面形状。在显示区域100，显示发光层34A通过第一像素开口与显示阳极31A连接，阴极35与显示发光层34A连接；在虚设像素区域200，虚设发光层34B通过第二像素开口与虚设阳极31B连接，阴极35与虚设发光层34B连接；在阴极环区域300，阴极35通过第三开口与阴极电压线32连接，如图13所示。在示例性实施方式中，阴极35为半透半反电极，与前述形成的第一反射电极141构成微腔结构。
前述制备过程中，第一绝缘薄膜、第二绝缘薄膜和第三绝缘薄膜可以采用硅氧化物(SiOx)、硅氮化物(SiNx)或氮氧化硅(SiON)，可以是单层结构，或者可以是多层复合结构。第一金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)或钼(Mo)等，或者可以采用由金属组成的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)等，合金材料可以是单层结构，或者可以是多层复合结构，如Mo/Cu/Mo的复合结构。透明导电薄膜可以采用氧化铟锡(ITO)或氧化铟锌(IZO)，或ITO/Ag/ITO的复合结构，像素 定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等。
(8)在形成前述结构的硅基衬底10上，在显示区域100、虚设像素区域200和阴极环区域300形成第一封装层40图案，第一封装层40为薄膜封装结构，如图14所示。
(9)在形成前述结构的硅基衬底10上，在显示区域100、虚设像素区域200、阴极环区域300和部分金属走线区400形成彩膜层50图案，显示区域100的彩膜层50包括相互间隔设置或相互交叠设置的第一颜色单元53、第二颜色单元54和第三颜色单元55，在一种示例性实施例中，显示区域100的颜色单元可以相互交叠作为黑矩阵，或者在颜色单元之间设置黑矩阵。虚设像素区域200和阴极环区域300的彩膜层50可以包括叠层设置的第一颜色单元53和第二颜色单元54，如图6A所示。在示例性实施方式中，第一颜色单元可以为绿色单元G，第二颜色单元可以为红色单元R，第三颜色单元可以为蓝色单元B。在一些可能的实现方式中，彩膜层50的制备过程包括：先形成蓝色单元B，然后形成红色单元R，然后形成绿色单元G。蓝色彩膜的粘附性较大，先形成蓝色单元B可以减小彩膜层50从阴极上剥离的可能性。由于红色单元R的粘附性较小，但流动性好，因而在形成红色单元R的过程中，可以减少蓝色单元B和红色单元R远离阴极一侧表面的气泡数量，从而可以提高蓝色单元B和红色单元R二者交叠位置处膜厚的均一性。由于绿色单元G的基体材料和红色单元R的基体材料大致相同，因而绿色单元G和红色单元R之间的粘附力较大，可以减小彩膜层50从阴极上剥离的可能性。在一些可能的实现方式中，彩膜层50可以包括其它颜色单元，例如白色或黄色等。
后续工艺中，在显示区域100、虚设像素区域200和阴极环区域300形成第二封装层图案，然后，采用密封工艺形成盖板，盖板与硅基衬底10之间通过密封胶固定。由于硅基衬底10、盖板和密封胶一起形成封闭的空间，因而提供了阻隔水氧的保障，使硅基OLED显示基板的寿命大幅提升。随后，对形成的显示母板进行切割，形成单独的显示基板。
通过本公开显示基板的结构及其制备过程可以看出，本公开通过将阴极电压线的形状设计成网状(Mesh)，既能保证阴极环区域300的阴极电压线 刻蚀负载(Loading)与显示区域的显示阳极刻蚀负载接近，又能改善阴极电压线与阴极金属搭接的问题，减小了阴极搭接电阻，减小了显示区域的IR Drop，提高了显示效果。
本公开的制备工艺可以利用成熟的制备设备实现，制备流程简单，不会增加Mask制程，仅通过改版阴极环金属排布即可实现，兼容性高，工艺流程简便，易于设备周期性维护，生产效率高，生产成本低，良品率高，便于大规模量产，所制备的显示基板可以应用在虚拟现实设备或增强显示设备中，或应用在其它类型的显示装置中，具有良好的应用前景。
本公开所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺，本公开在此不做限定。
图15为图5中B区域的另一种放大结构示意图。在另一些示例性实施方式中，如图15所示，至少一条第一阴极电压线320包括沿第一方向X交替设置且相互连接的第一子部320_1和第二子部320_2，第一子部320_1的形状与显示阳极31A的形状相同。
在一些示例性实施方式中，如图15所示，第一子部320_1在硅基衬底10上的正投影覆盖第二导电柱13B在硅基衬底10上的正投影。
在一些示例性实施方式中，如图15所示，第一子部320_1的形状与显示阳极31A的形状均为正六边形形状，然而，本公开实施例对此不作限制。
在一些示例性实施方式中，如图15所示，第二子部320_2为设置在沿第一方向X相邻的两个第一子部320_1之间的连接结构。
在一些示例性实施方式中，如图15所示，第二阴极电压线321为设置在沿第二方向Y相邻的两个第一子部320_1之间的连接结构。
本公开还提供了一种显示基板的制备方法，在示例性实施方式中，所述显示装置包括显示区域以及位于显示区域外侧的阴极环区域，该制备方法包括如下步骤：
提供硅基衬底，所述硅基衬底内包含像素驱动电路和供电电极；
在所述衬底上依次形成绝缘层和发光结构层，所述绝缘层包括第一导电柱和第二导电柱，所述发光结构层包括阳极层、像素定义层、有机发光层和阴极，所述阳极层包括位于所述显示区域的显示阳极和位于所述阴极环区域的阴极电压线，所述阴极与所述阴极电压线连接，所述显示阳极通过所述第一导电柱与所述像素驱动电路连接；所述阴极电压线包括多条第一阴极电压线和多条第二阴极电压线，所述第一阴极电压线沿第一方向延伸，所述第二阴极电压线沿第二方向延伸，所述第一方向为平行于所述显示基板的边沿的方向，所述第二方向与所述第一方向相交；至少一条所述第二阴极电压线设置在相邻两条所述第一阴极电压线之间，且与相邻的两条所述第一阴极电压线连接；所述阴极电压线通过所述第二导电柱与所述供电电极连接，所述阴极电压线在所述衬底上的正投影覆盖所述第二导电柱在所述衬底上的正投影。
本公开还提供了一种显示装置，包括前述任一实施例所述的显示基板。显示装置可以为虚拟现实装置、增强现实装置或近眼显示装置，或者可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪，或任何其它具有显示功能的产品或部件。
虽然本公开所揭露的实施方式如上，但上述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (24)

  1. 一种显示基板，包括衬底以及设置在所述衬底上的显示区域和阴极环区域，所述阴极环区域位于所述显示区域的外侧；
    在垂直于所述显示基板的平面上，所述显示基板包括设置在所述衬底上的绝缘层和设置在所述绝缘层上的发光结构层，所述发光结构层包括阳极层、像素定义层、发光层和阴极，所述阳极层包括位于所述显示区域的多个显示阳极和位于所述阴极环区域的阴极电压线，所述阴极与所述阴极电压线连接，所述衬底包括供电电极和像素驱动电路，所述绝缘层包括第一导电柱和第二导电柱，所述显示阳极通过所述第一导电柱与所述像素驱动电路连接；
    所述阴极电压线包括多条第一阴极电压线和多条第二阴极电压线，所述第一阴极电压线沿第一方向延伸，所述第二阴极电压线沿第二方向延伸，所述第一方向为平行于所述显示基板的边沿的方向，所述第二方向与所述第一方向相交；至少一条所述第二阴极电压线设置在相邻两条所述第一阴极电压线之间，且与相邻的两条所述第一阴极电压线连接；
    所述阴极电压线通过所述第二导电柱与所述供电电极连接，所述阴极电压线在所述衬底上的正投影覆盖所述第二导电柱在所述衬底上的正投影。
  2. 根据权利要求1所述的显示基板，其中，所述第一阴极电压线沿垂直于所述第一方向的方向上的宽度大于所述第二阴极电压线沿垂直于所述第二方向的方向上的宽度。
  3. 根据权利要求1所述的显示基板，其中，在所述阴极环区域，所述阳极层包括第一刻蚀区，所述第一刻蚀区位于相邻所述第一阴极电压线以及相邻所述第二阴极电压线围成的区域内，所述阴极环区域的像素定义层覆盖所述第一刻蚀区以及位于所述第一刻蚀区周边的阴极电压线。
  4. 根据权利要求1所述的显示基板，其中，在所述阴极环区域靠近所述显示区域的一侧，所述阴极电压线形成第一锯齿形结构边沿，且所述像素定义层在所述衬底上的正投影覆盖所述第一锯齿形结构边沿在所述衬底上的正投影。
  5. 根据权利要求4所述的显示基板，还包括虚设像素区域，所述虚设像素区域设置在所述显示区域和所述阴极环区域之间，所述阳极层还包括位于所述虚设像素区域的虚设阳极，所述虚设阳极浮置。
  6. 根据权利要求5所述的显示基板，其中，所述虚设阳极靠近所述阴极环区域的一侧形成第二锯齿形结构边沿，所述第一锯齿形结构边沿与所述第二锯齿形结构边沿为互补结构。
  7. 根据权利要求5所述的显示基板，其中，所述阴极环区域的像素定义层包括第三开口，所述第三开口暴露出至少部分第一阴极电压线和至少部分第二阴极电压线，所述第三开口暴露出的第二阴极电压线靠近所述虚设像素区域一侧的边缘为朝向所述虚设像素区域凸起的平滑曲面。
  8. 根据权利要求5所述的显示基板，其中，所述虚设像素区域的像素定义层包括第二像素开口；
    所述阴极电压线靠近所述虚设像素区域的一侧的边缘与所述第二像素开口靠近所述阴极环区域的一侧的边缘之间的距离，小于所述第一阴极电压线沿垂直于所述第一方向的方向上的宽度。
  9. 根据权利要求1所述的显示基板，其中，相邻所述第一阴极电压线间的距离大于所述第一阴极电压线沿垂直于所述第一方向的方向上的宽度。
  10. 根据权利要求1所述的显示基板，其中，所述显示区域的像素定义层包括第一像素开口；
    所述第一阴极电压线沿垂直于所述第一方向的方向上的宽度小于所述第一像素开口沿垂直于所述第一方向的方向上的宽度。
  11. 根据权利要求1所述的显示基板，其中，相邻两条所述第一阴极电压线之间的第二阴极电压线的条数，与每条所述第一阴极电压线覆盖的第二导电柱的个数相同。
  12. 根据权利要求1所述的显示基板，其中，所述第二阴极电压线与所述第二导电柱的排布位于一条直线上。
  13. 根据权利要求1所述的显示基板，其中，所述像素定义层包括第一像素定义层和第二像素定义层，所述第一像素定义层远离衬底一侧的表面与所述阳极层远离衬底一侧的表面齐平，所述第一像素定义层设置在所述阳极层的间隔部中，所述第二像素定义层设置在所述第一像素定义层远离所述衬底的一侧且覆盖所述第一像素定义层。
  14. 根据权利要求13所述的显示基板，其中，在所述显示区域，所述第二像素定义层在所述衬底上的正投影与所述显示阳极在所述衬底上的正投影交叠。
  15. 根据权利要求1所述的显示基板，其中，所述阴极环区域的像素定义层包括多个像素定义岛，所述像素定义岛与第一阴极电压线沿所述第二方向的距离大于所述像素定义岛与所述第二阴极电压线沿所述第一方向的距离。
  16. 根据权利要求15所述的显示基板，其中，所述阴极环区域的像素定义层包括第三开口，所述第三开口暴露出至少部分第一阴极电压线和至少部分第二阴极电压线，所述像素定义岛的形状为圆角矩形，所述像素定义岛的任一顶角与所述第三开口内所述阴极电压线之间的最短距离，大于所述像素定义岛的任一边与所述第三开口内所述阴极电压线之间的最短距离。
  17. 根据权利要求1所述的显示基板，其中，所述第一阴极电压线包括N条，第一条所述第一阴极电压线至第N条所述第一阴极电压线沿靠近所述显示区域的方向依次排布；
    所述第二阴极电压线包括第一子第二阴极电压线至第(N-1)子第二阴极电压线，第i子第二阴极电压线设置在第i条第一阴极电压线与第(i+1)条第一阴极电压线之间，i为1至(N-1)之间的自然数。
  18. 根据权利要求17所述的显示基板，其中，至少存在一条第i子第二阴极电压线和一条第(i+1)子第二阴极电压线位于一条直线上。
  19. 根据权利要求17所述的显示基板，其中，任意一条第i子第二阴极电压线和任意一条第(i+1)子第二阴极电压线均不位于一条直线上。
  20. 根据权利要求1所述的显示基板，其中，所述阴极电压线在所述衬底上的正投影的面积与所述阴极环区域在所述衬底上的正投影的面积的比值为第一比值，所述显示阳极在所述衬底上的正投影的面积与所述显示区域在衬底上的正投影的面积的比值为第二比值，所述第一比值与所述第二比值相同，或者，所述第一比值与所述第二比值的差值小于预设的差值阈值。
  21. 根据权利要求1所述的显示基板，其中，至少一条所述第一阴极电压线包括沿所述第一方向交替设置且相互连接的第一子部和第二子部，所述第一子部的形状与所述显示阳极的形状相同，所述第二子部为设置在沿所述第一方向相邻的两个所述第一子部之间的连接结构。
  22. 根据权利要求21所述的显示基板，其中，所述第一子部在所述衬底上的正投影覆盖所述第二导电柱在所述衬底上的正投影。
  23. 一种显示装置，包括：如权利要求1至22任一所述的显示基板。
  24. 一种显示基板的制备方法，所述显示基板包括显示区域和阴极环区域，所述阴极环区域位于所述显示区域的外侧，所述制备方法包括：
    提供衬底，所述衬底内包含像素驱动电路和供电电极；
    在所述衬底上依次形成绝缘层和发光结构层，所述绝缘层包括第一导电柱和第二导电柱，所述发光结构层包括阳极层、像素定义层、有机发光层和阴极，所述阳极层包括位于所述显示区域的显示阳极和位于所述阴极环区域的阴极电压线，所述阴极与所述阴极电压线连接，所述显示阳极通过所述第一导电柱与所述像素驱动电路连接；所述阴极电压线包括多条第一阴极电压线和多条第二阴极电压线，所述第一阴极电压线沿第一方向延伸，所述第二阴极电压线沿第二方向延伸，所述第一方向为平行于所述显示基板的边沿的方向，所述第二方向与所述第一方向相交；至少一条所述第二阴极电压线设置在相邻两条所述第一阴极电压线之间，且与相邻的两条所述第一阴极电压线连接；所述阴极电压线通过所述第二导电柱与所述供电电极连接，所述阴极电压线在所述衬底上的正投影覆盖所述第二导电柱在所述衬底上的正投影。
PCT/CN2022/102958 2022-06-30 2022-06-30 显示基板及其制备方法、显示装置 WO2024000459A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2022/102958 WO2024000459A1 (zh) 2022-06-30 2022-06-30 显示基板及其制备方法、显示装置
CN202280002045.5A CN117652226A (zh) 2022-06-30 2022-06-30 显示基板及其制备方法、显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/102958 WO2024000459A1 (zh) 2022-06-30 2022-06-30 显示基板及其制备方法、显示装置

Publications (1)

Publication Number Publication Date
WO2024000459A1 true WO2024000459A1 (zh) 2024-01-04

Family

ID=89383829

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/102958 WO2024000459A1 (zh) 2022-06-30 2022-06-30 显示基板及其制备方法、显示装置

Country Status (2)

Country Link
CN (1) CN117652226A (zh)
WO (1) WO2024000459A1 (zh)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009010258A (ja) * 2007-06-29 2009-01-15 Kyocera Corp 画像表示装置
CN102222683A (zh) * 2003-10-09 2011-10-19 三星移动显示器株式会社 平板显示器设备及其制造方法
CN111834410A (zh) * 2019-04-15 2020-10-27 三星显示有限公司 显示设备
US20200365681A1 (en) * 2018-02-06 2020-11-19 Japan Display Inc Display device
CN113284921A (zh) * 2020-02-19 2021-08-20 合肥鑫晟光电科技有限公司 阵列基板及显示装置
WO2021189485A1 (zh) * 2020-03-27 2021-09-30 京东方科技集团股份有限公司 显示基板及显示方法、显示装置
WO2021189482A1 (zh) * 2020-03-27 2021-09-30 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
US20220140021A1 (en) * 2020-03-27 2022-05-05 Boe Technology Group Co., Ltd. Display Substrate, Manufacturing Method Thereof, and Display Apparatus

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102222683A (zh) * 2003-10-09 2011-10-19 三星移动显示器株式会社 平板显示器设备及其制造方法
JP2009010258A (ja) * 2007-06-29 2009-01-15 Kyocera Corp 画像表示装置
US20200365681A1 (en) * 2018-02-06 2020-11-19 Japan Display Inc Display device
CN111834410A (zh) * 2019-04-15 2020-10-27 三星显示有限公司 显示设备
CN113284921A (zh) * 2020-02-19 2021-08-20 合肥鑫晟光电科技有限公司 阵列基板及显示装置
WO2021189485A1 (zh) * 2020-03-27 2021-09-30 京东方科技集团股份有限公司 显示基板及显示方法、显示装置
WO2021189482A1 (zh) * 2020-03-27 2021-09-30 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
US20220140021A1 (en) * 2020-03-27 2022-05-05 Boe Technology Group Co., Ltd. Display Substrate, Manufacturing Method Thereof, and Display Apparatus

Also Published As

Publication number Publication date
CN117652226A (zh) 2024-03-05

Similar Documents

Publication Publication Date Title
WO2022042046A1 (zh) 显示基板及其制备方法、显示装置
EP4131398A1 (en) Display substrate and preparation method therefor, and display apparatus
WO2023241344A1 (zh) 显示基板及其制备方法、显示装置
EP4131396A1 (en) Display panel, method for manufacturing same and electronic device
WO2021189484A9 (zh) 显示基板及其制作方法、显示装置
US11475837B2 (en) Silicon-based organic light-emitting diode display device and silicon-based organic light-emitting diode display method
WO2021189480A1 (zh) 显示基板及其制备方法、显示装置
WO2024000459A1 (zh) 显示基板及其制备方法、显示装置
WO2024040389A1 (zh) 显示面板和显示装置
WO2022170547A1 (zh) 显示基板及其制备方法、显示装置
WO2024021001A1 (zh) 显示基板及其制备方法、显示装置
WO2024092391A1 (zh) 显示基板及其制备方法、显示装置
WO2023000215A1 (zh) 显示基板及显示装置
WO2023178591A1 (zh) 显示基板及其制备方法、显示装置
WO2022226737A1 (zh) 显示基板及其制备方法、显示装置
WO2023201591A1 (zh) 显示基板及其制备方法、显示装置
WO2023178612A1 (zh) 显示基板及其制备方法、显示装置
EP4333022A1 (en) Display panel and display apparatus
WO2023184163A1 (zh) 显示基板及显示装置
WO2024050839A1 (zh) 显示基板、显示装置
WO2023283768A1 (zh) 显示基板及其制备方法、显示装置
WO2023039886A1 (zh) 显示基板及其制备方法、显示装置
US20240135869A1 (en) Display panel
WO2023115463A1 (zh) 显示装置
WO2023206462A1 (zh) 显示基板及其制备方法、显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 18023379

Country of ref document: US