WO2021189485A1 - 显示基板及显示方法、显示装置 - Google Patents

显示基板及显示方法、显示装置 Download PDF

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Publication number
WO2021189485A1
WO2021189485A1 PCT/CN2020/081857 CN2020081857W WO2021189485A1 WO 2021189485 A1 WO2021189485 A1 WO 2021189485A1 CN 2020081857 W CN2020081857 W CN 2020081857W WO 2021189485 A1 WO2021189485 A1 WO 2021189485A1
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WIPO (PCT)
Prior art keywords
pixel
display
column
area
display area
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PCT/CN2020/081857
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English (en)
French (fr)
Inventor
朱志坚
敖雨
卢鹏程
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/081857 priority Critical patent/WO2021189485A1/zh
Priority to JP2021570495A priority patent/JP2023528699A/ja
Priority to EP20897647.2A priority patent/EP4131224A4/en
Priority to US17/257,843 priority patent/US11475837B2/en
Priority to CN202080000420.3A priority patent/CN113748452B/zh
Publication of WO2021189485A1 publication Critical patent/WO2021189485A1/zh

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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate, a display method, and a display device.
  • the embodiment of the present disclosure provides a display substrate including a display area and an offset area surrounding the display area.
  • the display substrate In a direction perpendicular to the plane where the display substrate is located, the display substrate includes a silicon-based substrate and is arranged on the silicon-based substrate.
  • the light emitting structure layer on the substrate, the packaging layer disposed on the side of the light emitting structure layer away from the silicon base substrate, the silicon base substrate of the display area is integrated with the first pixel driving circuit, and the offset area
  • the silicon-based substrate is integrated with a second pixel drive circuit; the first pixel drive circuit is connected to the light emitting structure layer of the display area, and at least part of the first pixel drive circuit is configured to:
  • the light emitting structure layer electrically connected to the first pixel driving circuit provides a driving signal;
  • the second pixel driving circuit is connected to the light emitting structure layer of the offset area, and at least part of the second pixel driving circuit is configured as:
  • no driving signal is provided for the light-emitting structure layer electrically connected to the second pixel driving circuit.
  • all the first pixel driving circuits are configured to provide driving signals for the light-emitting structure layer electrically connected to the first pixel driving circuit.
  • the offset area includes a left offset area, a right offset area, and/or an upper offset area and a lower offset area, and the left offset area and the right offset area
  • the difference in the number of pixel columns included in the offset area does not exceed 10 rows, and the difference in the number of pixel rows included in the upper offset area and the lower offset area does not exceed 10 rows.
  • the number of pixel columns contained in the left offset area and the right offset area are equal, and the number of pixel rows contained in the upper offset area and the lower offset area are equal.
  • the ratio of the number of columns of pixel units in the left offset area or the right offset area to the number of columns of pixel units in the display area is greater than or equal to 1%; the upper side The ratio of the number of rows of pixel units in the offset area or the lower offset area to the number of rows of pixel units in the display area is greater than or equal to 1%.
  • the display substrate further includes a color filter layer disposed on a side of the encapsulation layer away from the light-emitting structure layer, and the color filter layers in the display area and the offset area respectively include arrays.
  • the display substrate further includes a dummy pixel area at least partially surrounding the offset area.
  • the dummy pixel area includes a silicon-based substrate, A light-emitting structure layer arranged on a silicon-based substrate, and an encapsulation layer arranged on a side of the light-emitting structure layer away from the silicon-based substrate.
  • An embodiment of the present disclosure also provides a display device, including: the display substrate as described in any one of the preceding items, and further including: a gate driver, a source driver, and a timing controller, wherein: the gate driver is configured to The gate control signal output by the timing controller is received, and the scan signal is generated and transmitted to the actual display area on the display substrate through the scan line.
  • the actual display area is performed according to the position and number of the dead pixels of the pixel unit on the display substrate Adjustment;
  • the source driver is configured to receive the data voltage and source control signal output by the timing controller, generate a corresponding data voltage signal and output to the actual display area on the display substrate through the data line;
  • the timing controller Is configured to receive externally input red, green and blue data and timing control signals; according to the red, green and blue data and timing control signals, generate data voltages and source control signals and output them to the source driver, generate gate drive signals and output them to Gate driver.
  • the actual display area is adjusted according to the position and number of the dead pixels of the pixel unit on the display substrate, including: during initial display, the gate driver and the source driver drive the Ath
  • the pixel units from row to row B and from column C to column D are displayed; when the display area near the left edge of the pixel unit from column C to column (C+N) includes more than the second preset ratio
  • the gate driver and the source driver drive the pixel units from row A to row B, and from column (C+N+1) to column (D+N+1) for display;
  • the gate driver and the source driver drive rows A to B,
  • the pixel units in the (CN-1) column to the (DN-1) column are displayed; when the display area is close to the upper edge of the pixel unit in the A-th row to the (A+M)-th row, the pixel units in the row (
  • the embodiment of the present disclosure also provides a display method, which includes: performing dead pixel detection on a plurality of pixel units in the display area; When setting the proportion of dead pixels, adjust the pixel row output by the gate driver or the pixel column output by the source driver to move to the side opposite to the side where the dead pixels are located.
  • the pixel row or source output by the gate driver is adjusted.
  • the pixel column output by the pole driver moves to the side opposite to the side where the dead pixel is located, including: during initial display, the gate driver and the source driver drive the pixel units from the Ath row to the Bth row, and the Cth column to the Dth column.
  • the performing dead pixel detection on multiple pixel units in the display area includes: grouping the multiple pixel units in the display area; driving the multiple groups to emit light in sequence; and to emit light in each group.
  • the pixel unit in the group emits light, it is determined whether the group includes dead pixels and the number of dead pixels included.
  • FIG. 1 is a schematic diagram of a structure of a display substrate of the present disclosure
  • FIG. 2 is a schematic diagram of the actual display area shifted to the right when the pixels on the left edge of the display substrate in FIG. 1 are damaged;
  • FIG. 3 is a schematic diagram of the actual display area moving up when the pixels on the lower edge of the display substrate in FIG. 1 are damaged;
  • FIG. 4 is a schematic cross-sectional view of the display substrate of the present disclosure.
  • Fig. 5 is a schematic diagram of a circuit principle of a silicon-based substrate of the present disclosure
  • FIG. 6 is a schematic diagram of a circuit implementation of the voltage control circuit and the pixel driving circuit of the disclosure
  • FIG. 7 is a schematic diagram of a display substrate after preparing a silicon-based substrate according to the present disclosure.
  • FIG. 8 is a schematic diagram of a display substrate after forming a first insulating layer and a first conductive pillar;
  • FIG. 9 is a schematic diagram of a display substrate after forming a reflective electrode in the present disclosure.
  • FIG. 10 is a schematic diagram of a display substrate after forming a second insulating layer and a second conductive pillar in the present disclosure
  • FIG. 11 is a schematic diagram of a display substrate after forming an anode layer in the present disclosure.
  • FIG. 12 is a schematic diagram of a display substrate after forming an organic light-emitting layer and a cathode in the present disclosure
  • FIG. 13 is a schematic diagram of a display substrate after forming an encapsulation layer in the present disclosure
  • FIG. 14 is a schematic diagram of a display substrate after forming a color filter layer in the present disclosure.
  • 15 is a schematic diagram of the structure of an organic light-emitting layer of the present disclosure.
  • FIG. 16 is a schematic flowchart of a display method of the present disclosure.
  • connection should be interpreted broadly. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection or a connection; it can be a direct connection, or an indirect connection through an intermediate piece, or a connection between two components.
  • connection should be interpreted broadly. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection or a connection; it can be a direct connection, or an indirect connection through an intermediate piece, or a connection between two components.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • it may be the drain electrode of the first electrode and the source electrode of the second electrode, or it may be the source electrode of the first electrode and the drain electrode of the second electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged.
  • connection includes the case where constituent elements are connected together by elements having a certain electrical function.
  • An element having a certain electrical function is not particularly limited as long as it can transmit and receive electrical signals between connected constituent elements.
  • elements having a certain electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore, it also includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore, also includes a state where an angle of 85° or more and 95° or less is included.
  • film and “layer” can be interchanged.
  • the “conductive layer” can be replaced by the “conductive film.”
  • the “insulating film” can sometimes be replaced with an “insulating layer.”
  • At least one embodiment of the present disclosure provides a display substrate.
  • the display substrate includes a display area and an offset area surrounding the display area.
  • the light-emitting structure layer on the substrate, the packaging layer arranged on the side of the light-emitting structure layer away from the silicon-based substrate, the silicon-based substrate in the display area is integrated with the first pixel drive circuit, and the silicon-based substrate in the offset area is integrated with the first pixel drive circuit.
  • the first pixel driving circuit is connected to the light-emitting structure layer of the display area, and at least part of the first pixel driving circuit is configured to provide driving for the light-emitting structure layer electrically connected to the first pixel driving circuit during normal display Signal;
  • the second pixel drive circuit is connected to the light-emitting structure layer in the offset area, and at least part of the second pixel drive circuit is configured to not provide drive signals for the light-emitting structure layer electrically connected to the second pixel drive circuit during normal display .
  • Some embodiments of the present disclosure also provide a display device and a display method corresponding to the above-mentioned display substrate.
  • the display substrate provided by the above-mentioned embodiments of the present disclosure is provided with an offset area, so that when a part of the pixel unit of the display area at a certain edge of the display module is damaged by processes such as packaging and patching, the position of the actual display area can be adjusted toward the offset
  • the area is moved to avoid the pixel unit damaged by the packaging patch to ensure that the actual number of pixels displayed is consistent with the pre-designed number of pixels.
  • FIG. 1 is a schematic diagram of the structure of a display substrate of the present disclosure.
  • the display substrate includes a display area 100 and an offset area 200 surrounding the display area 100.
  • the display substrate includes a silicon-based substrate,
  • the light-emitting structure layer on the silicon-based substrate, the packaging layer arranged on the side of the light-emitting structure layer away from the silicon-based substrate, the silicon-based substrate in the display area integrates the first pixel drive circuit, and the silicon-based substrate in the offset area
  • the second pixel driving circuit is integrated; the first pixel driving circuit is connected to the light emitting structure layer of the display area, and at least part of the first pixel driving circuit is configured to be a light emitting structure electrically connected to the first pixel driving circuit during normal display
  • the second pixel drive circuit is connected to the light-emitting structure layer in the offset area, and at least part of the second pixel drive circuit is configured to: during normal display, it is not a
  • all the first pixel driving circuits are configured to provide driving signals for the light emitting structure layer electrically connected to the first pixel driving circuit.
  • the display substrate may further include a dummy pixel area 300 at least partially surrounding the offset area 200.
  • the dummy pixel area 300 may include A silicon-based substrate, a light-emitting structure layer provided on the silicon-based substrate, and an encapsulation layer provided on the side of the light-emitting structure layer away from the silicon-based substrate.
  • the display substrate may further include a cathode ring 400 surrounding the dummy pixel region 300.
  • the cathode ring 400 may include The power supply electrode layer on the substrate, the reflective layer provided on the side of the power supply electrode layer away from the silicon-based substrate, the anode layer provided on the side of the reflective layer away from the power supply electrode layer, and the cathode layer provided on the side of the anode layer away from the reflective layer .
  • the display area 100 includes a plurality of first pixel units 101
  • the offset area 200 includes a plurality of second pixel units 201
  • the second pixel units 201 are configured as first pixel units.
  • the display substrate may be a silicon-based OLED micro display substrate or any other type of display substrate.
  • Silicon-based OLED micro-display substrates use monocrystalline silicon wafers as active drive backplanes, which have excellent characteristics such as high PPI, high integration, small size, easy portability, good shock resistance, and ultra-low power consumption.
  • the offset area 200 may include any one or more of the following: left offset area, right offset area, upper offset area, and lower offset area, left offset area
  • left offset area The difference between the number of pixel columns contained in the area and the right offset area does not exceed 10 rows, and the difference between the number of pixel rows contained in the upper offset area and the lower offset area does not exceed 10 rows.
  • the number of pixel columns contained in the left offset area and the right offset area may be equal.
  • the pixel column output by the adjusted source driver moves to the right, that is, the actual display is The area moves to the right.
  • the pixel column output by the adjusted source driver moves to the left, that is, the actual display area moves to the left .
  • the ratio of the number of columns of the second pixel unit in the left offset area to the number of columns of the first pixel unit in the display area is greater than or equal to 1%
  • the second pixel in the right offset area The ratio of the number of columns of cells to the number of columns of the first pixel unit in the display area is greater than or equal to 1%.
  • the display area includes 1920 rows*1080 columns of first pixel units
  • the number of second pixel units included in the left offset area is between 0 and 16 columns
  • the right offset area includes the first pixel unit.
  • the number of columns of the two-pixel unit is between 0 and 16 columns.
  • the number of pixel rows contained in the upper offset area and the lower offset area may be equal.
  • the pixel row output by the adjustment gate driver moves upward, that is, the actual display is The area moves up.
  • the pixel row output by the adjustment gate driver moves downward, that is, the actual display area moves downward.
  • the ratio of the number of rows of the second pixel unit in the upper offset area to the number of rows of the first pixel unit in the display area is greater than or equal to 1%
  • the second pixel in the lower offset area The ratio of the number of rows of cells to the number of rows of the first pixel unit in the display area is greater than or equal to 1%.
  • the display area includes 1920 rows*1080 columns of first pixel units
  • the number of rows of second pixel units included in the upper offset area is between 0 and 16 rows
  • the lower offset area includes the first pixel unit.
  • the number of rows of the two-pixel unit is between 0 and 16 rows.
  • the display area 100 and the offset area 200 of the display substrate respectively include a silicon-based substrate 10 and a light-emitting structure disposed on the silicon-based substrate 10.
  • the silicon-based substrate 10 of the display area 100 and the offset area 200 of the display substrate integrates a pixel drive circuit for generating drive signals, a gate drive circuit for generating gate drive signals, and a data drive for generating data signals. Circuit.
  • the light-emitting structure layer 20 includes a reflective layer, an anode layer, an organic light-emitting layer, and a cathode layer stacked on a silicon-based substrate 10.
  • the reflective layer is used to form a microcavity structure with the cathode layer, so that the light directly emitted by the organic light-emitting layer is reflected The light reflected by the layer interferes with each other to increase the color gamut of the emitted light and enhance the brightness of the emitted light.
  • the light emitting structure layer 20 may further include a structure film layer such as a pixel definition layer or a flat layer.
  • the encapsulation layer 40 wrapping the light-emitting structure layer 20 means that the encapsulation layer 40 is disposed on the upper surface of the light-emitting structure layer 20 away from the silicon base substrate 10, and is disposed on all side surfaces of the light-emitting structure layer 20, so that the encapsulation layer 40
  • the silicon-based substrate 10 forms a sealed cavity, and the light-emitting structure layer 20 is disposed in the sealed cavity.
  • the orthographic projection of the encapsulation layer 40 on the silicon-based substrate 10 includes the orthographic projection of the light-emitting structure layer 20 on the silicon-based substrate 10.
  • the color filter layer 50 of the display area 100 and the offset area 200 respectively includes a first color unit 53, a second color unit 54 and a third color unit 55 arranged in an array, wherein the first The color unit 53, the second color unit 54 and the third color unit 55 may be respectively a red (R) color filter unit (Color Filter, CF), a green (G) color filter unit, and a blue (B) color filter unit One of them.
  • the color units in the color filter layer 50 can overlap each other as a black matrix, or a black matrix can be arranged between the color units.
  • the present disclosure adopts the white light + color film method to achieve a high resolution greater than 2000, and can meet the requirements of VR/AR.
  • At least one layer of the organic light-emitting layer 33 may be arranged on the entire surface, or may be arranged separately for each pixel area, which can satisfy that the light-emitting layer of each color in each pixel area emits white light. Can.
  • the organic light-emitting layer 33 may also be arranged in arrays of light-emitting layers of three colors, such as red, green, and blue, respectively, and each pixel area emits red, blue, and green light separately.
  • the dummy pixel area 300 does not include a color filter structure; for example, when the display unit in the offset area 200 on a certain side of the substrate is not used, the area above the display unit in the offset area 200
  • the color film layer can be used as a dummy color film to balance the uneven problem caused by uneven exposure and development during the production of the color film layer.
  • the dummy pixel area 300 may include a color filter structure; it may be configured in the same manner as the color filter layer in the display area, which will not be repeated in this embodiment.
  • a color filter layer may be disposed above the cathode ring 400, and the color filter layer in this area may extend to the peripheral area.
  • the display substrate may further include a cover plate 70 which is disposed above the color film layer 50 to realize the function of protecting the color film 50.
  • the cover plate 70 is connected to the silicon-based substrate 10 through a sealant, and the sealant is disposed between the silicon-based substrate 10 and the cover plate 70, which can provide further protection against the intrusion of water and oxygen, so that The life span of silicon-based OLED display substrates has been greatly improved.
  • the sealant may be provided on the side surface of the cover plate 70, and the surrounding sides of the cover plate 70 and the silicon-based substrate 10 are sealed by the sealant, and the sealant is away from the side of the silicon-based substrate 10.
  • the end surface is located between the surface of the cover plate 70 on the side adjacent to the silicon-based substrate 10 and the surface of the cover plate 70 on the side away from the silicon-based substrate 10, thereby not only ensuring the sealing effect, but also preventing the sealant from rising above the cover plate 70 This leads to an increase in the thickness of the display substrate.
  • the cover plate 70 is disposed in the display area 100, which can better realize the alignment and sealing, and avoid the cover plate 70 from being broken during the cutting process.
  • the display substrate may further include a protective layer 60 disposed between the color filter layer 50 and the cover plate 70, and the protective layer 60 covers the color filter layer 50.
  • the protective layer 60 may be SiC or SiCNx. Since SiC or SiCNx tends to have inorganic characteristics, it can protect the color film layer 50 on the one hand, reduce the aging damage of the color film layer 50, and increase the service life. On the one hand, a flat surface can be formed, which facilitates the leveling of the glue material in the subsequent process of attaching the cover plate, and improves the quality of the cover plate bonding.
  • FIG. 5 is a schematic diagram of a circuit principle of a silicon-based substrate of the present disclosure.
  • the silicon-based substrate 10 includes a plurality of display units located in the display area 100 (AA area) and the offset area 200, and a control circuit located in the peripheral area.
  • the multiple display units in the display area 100 are arranged regularly to form a plurality of Display rows and multiple display columns, each display unit includes a pixel drive circuit 103 and a light emitting device 104 connected to the pixel drive circuit 103, and the pixel drive circuit 103 includes at least a drive transistor.
  • the control circuit includes at least a plurality of voltage control circuits 110, and each voltage control circuit 110 is connected to a plurality of pixel driving circuits 103.
  • a voltage control circuit 110 is connected to the pixel drive circuit 103 in a display row, the first pole of the drive transistor in the display row pixel drive circuit 103 is commonly connected to the voltage control circuit 110, and the second pole of each drive transistor is connected to the The anode of the light emitting device 104 of the present display unit is connected, and the cathode of the light emitting device 104 is connected to the input terminal of the second power signal VSS.
  • the voltage control circuit 110 is respectively connected to the input terminal of the first power signal VDD, the input terminal of the initialization signal Vinit, the input terminal of the reset control signal RE, and the input terminal of the light emission control signal EM, and the voltage control circuit 110 is configured to respond to the reset control
  • the signal RE outputs the initialization signal Vinit to the first pole of the driving transistor, and controls the corresponding light-emitting device 104 to reset.
  • the voltage control circuit 110 is also configured to output the first power signal VDD to the first pole of the driving transistor in response to the light emission control signal EM to drive the light emitting device 104 to emit light.
  • each pixel drive circuit 103 in a display row By connecting the pixel drive circuits 103 in a display row to the voltage control circuit 110 in common, the structure of each pixel drive circuit 103 in the display area 100 can be simplified, and the occupied area of the pixel drive circuit 103 in the display area 100 can be reduced, thereby making the display area 100 More pixel driving circuits 103 and light emitting devices 104 are provided to realize high PPI display.
  • the voltage control circuit 110 outputs the initialization signal Vinit to the first pole of the driving transistor under the control of the reset control signal RE, and controls the corresponding light-emitting device 104 to reset, which can prevent the voltage applied to the light-emitting device 104 from being lowered when the previous frame emits light. The effect of one frame of light can improve the afterimage phenomenon.
  • 3 display units of different colors form 1 pixel unit (the pixel unit may be a first pixel unit or a second pixel unit), and the 3 display units may be red display units, Green display unit and blue display unit.
  • one pixel unit may include 4, 5 or more display units, which can be designed and determined according to the actual application environment, which is not limited here.
  • one voltage control circuit 110 can be connected to the pixel drive circuits 103 in two adjacent display units in the same display row, or can be connected to the pixel drive circuits 103 in three or more display units in the same display row.
  • the pixel driving circuit 103 is not limited here.
  • FIG. 6 is a schematic diagram of a circuit implementation of the voltage control circuit and the pixel driving circuit of the present disclosure.
  • the light-emitting device may include an OLED.
  • the anode of the OLED is connected to the second electrode D of the driving transistor M0, and the cathode of the OLED is connected to the input terminal of the second power signal VSS.
  • the voltage of the second power signal VSS is generally negative.
  • the voltage or ground voltage V GND generally 0V
  • the voltage of the initialization signal Vinit can also be set to the ground voltage V GND .
  • the OLED may be Micro-OLED or Mini-OLED, which is beneficial for realizing high PPI display.
  • the voltage control circuit 110 is connected to two pixel driving circuits 103 in a display row.
  • the pixel driving circuit 103 includes a driving transistor M0, a third transistor M3, a fourth transistor M4, and a storage capacitor Cst.
  • the circuit 110 includes a first transistor M1 and a second transistor M2.
  • the driving transistor M0, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all metal oxide semiconductor field effect transistors (MOS) fabricated in a silicon-based substrate.
  • the control electrode of the first transistor M1 is connected to the input end of the reset control signal RE for receiving the reset control signal RE, and the first electrode of the first transistor M1 is connected to the input end of the initialization signal Vinit for receiving the initialization signal Vinit.
  • the second pole of a transistor M1 is respectively connected to the first pole S of the corresponding driving transistor M0 and the second pole of the second transistor M2.
  • the control electrode of the second transistor M2 is connected to the input end of the light emission control signal EM for receiving the light emission control signal EM, and the first electrode of the second transistor M2 is connected to the input end of the first power signal VDD for receiving the light emission control signal EM.
  • a power signal VDD, the second pole of the second transistor M2 is respectively connected to the first pole S of the corresponding driving transistor M0 and the second pole of the first transistor M1.
  • the types of the first transistor M1 and the second transistor M2 may be different, for example, the first transistor M1 is an N-type transistor, the second transistor M2 is a P-type transistor, or the first transistor M1 is a P-type transistor.
  • the second transistor M2 is an N-type transistor.
  • the types of the first transistor M1 and the second transistor M2 can be the same, which can be designed and determined according to the actual application environment, which is not limited herein.
  • the pixel driving circuit 103 includes a driving transistor M0, a third transistor M3, a fourth transistor M4, and a storage capacitor Cst.
  • the control electrode G of the driving transistor M0, the first electrode S of the driving transistor M0 are connected to the second electrode of the first transistor M1 and the second electrode of the second transistor M2, and the second electrode D of the driving transistor M0 is connected to the anode of the OLED.
  • the control electrode of the third transistor M3 is connected to the input end of the first control electrode scanning signal S1 for receiving the first control electrode scanning signal S1, and the first electrode of the third transistor M3 is connected to the input end of the data signal DA for receiving the first control electrode scanning signal S1.
  • the second electrode of the third transistor M3 is connected to the control electrode G of the driving transistor M0.
  • the control electrode of the fourth transistor M4 is connected to the input end of the second control electrode scanning signal S2 for receiving the second control electrode scanning signal S2, and the first electrode of the fourth transistor M4 is connected to the input end of the data signal DA for receiving the second control electrode scanning signal S2.
  • the second electrode of the fourth transistor M4 is connected to the control electrode G of the driving transistor M0.
  • the first end of the storage capacitor Cst is connected to the control electrode G of the driving transistor M0, and the second end of the storage capacitor Cst is connected to the ground terminal GND.
  • the driving transistor M0 may be an N-type transistor, and the types of the third transistor M3 and the fourth transistor M4 may be different, for example, the third transistor M3 is an N-type transistor, and the fourth transistor M4 is a P-type transistor.
  • the P-type fourth transistor M4 is turned on to transmit the data signal DA to the control electrode G of the driving transistor M0, which can prevent the voltage of the data signal DA from being affected by, for example, N The influence of the threshold voltage of the third transistor M3.
  • the third transistor M3 of the N type is turned on to transmit the data signal DA to the control electrode G of the driving transistor M0, which can prevent the voltage of the data signal DA from being affected by the P type.
  • the influence of the threshold voltage of the fourth transistor M4. In this way, the voltage range input to the control electrode G of the driving transistor M0 can be increased.
  • the type of the third transistor M3 and the fourth transistor M4 may be that the third transistor M3 is a P-type transistor, and the fourth transistor M4 is an N-type transistor.
  • the pixel driving circuit may be a 3T1C, 5T1C, or 7T1C circuit structure, or may be a circuit structure with internal compensation or external compensation, which is not limited in the present disclosure.
  • the "patterning process” referred to in the present disclosure includes film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping treatments.
  • the deposition can be any one or more of sputtering, evaporation and chemical vapor deposition
  • the coating can be any one or more of spraying and spin coating
  • the etching can be any of dry etching and wet etching.
  • “Thin film” refers to a layer of film made by depositing or coating a certain material on a substrate.
  • the "film” can also be referred to as a "layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • “A and B are arranged in the same layer” means that A and B are formed at the same time through the same patterning process.
  • the orthographic projection of A includes the orthographic projection of B” means that the orthographic projection of B falls within the orthographic projection range of A, or that the orthographic projection of A covers the orthographic projection of B.
  • the silicon-based substrate 10 is prepared.
  • the silicon-based substrate 10 includes a display area 100 and a peripheral area surrounding the display area 100.
  • the peripheral area includes an offset area 200, a dummy pixel area 300, and a cathode ring 400.
  • the silicon-based substrate 10 of the shift area 200 is integrated with a pixel driving circuit
  • the silicon-based substrate 10 of the cathode ring 400 is integrated with a power supply circuit, as shown in FIG. 7.
  • FIG. 7 illustrates three display units of the display area 100: a first preferred display unit, a second preferred display unit, and a third preferred display unit, and three display units of the offset area 200 are illustrated.
  • the first candidate display unit, the second candidate display unit, and the third candidate display unit indicate the driving transistor 11 included in the pixel driving circuit, and indicate the power supply electrode 401 of the cathode ring 400.
  • the driving thin film transistors of the display area 100 and the offset area 200 respectively include an active layer, a gate electrode, a source electrode, a drain electrode, and a gate connection electrode.
  • the source electrode and the drain electrode are connected to each other through a conductive pillar.
  • the source layer is connected, and the gate connection electrode is connected to the gate electrode through the conductive pillar.
  • a mature CMOS integrated circuit process can be used to prepare the silicon-based substrate 10, which is not limited in the present disclosure.
  • the surface of the silicon-based substrate 10 exposes the source electrode, the drain electrode and the gate connection electrode of the display area 100, the source electrode, the drain electrode and the gate connection electrode of the offset area 200, and the power supply electrode 401 of the cathode ring 400.
  • a first insulating film is deposited on the silicon-based substrate 10, and the first insulating film is patterned through a patterning process to form a pattern of the first insulating layer 12 covering the silicon-based substrate 10, the display area 100 and the offset area 200
  • a plurality of first via holes are formed in the first insulating layer 12 of the cathode ring 400, at least one second via hole is formed in the first insulating layer 12 of the cathode ring 400, and the plurality of first via holes respectively expose the drain electrode of each display unit.
  • the two via holes expose the power supply electrode 301.
  • first conductive pillars 13 are formed in the first via hole and the second via hole on the first insulating layer 12, and the first conductive pillar 13 in the first via hole is connected to the drain electrode of the display unit where it is located.
  • the first conductive pillar 13 in the two via holes is connected to the power supply electrode 401 of the cathode ring 400, as shown in FIG. 8.
  • the first conductive pillar 13 may be made of a metal material.
  • a polishing process may also be performed.
  • the first insulating layer 12 and the first conductive pillar may be polished through a polishing process.
  • the surface of 13 is corroded and rubbed to remove part of the thickness of the first insulating layer 12 and the first conductive pillar 13 so that the first insulating layer 12 and the first conductive pillar 13 form a flat surface.
  • the first conductive pillar 13 may be metal tungsten (W), and the via filled with tungsten metal is called a tungsten via (W-via).
  • W-via metal tungsten via
  • the tungsten vias can ensure the stability of the conductive path.
  • the resulting first insulating layer 12 has a good surface flatness, which is beneficial to Reduce contact resistance.
  • the tungsten via is not only suitable for the connection between the silicon-based substrate 10 and the reflective layer, but also for the connection between the reflective layer and the anode layer, and the connection between other wiring layers.
  • the reflective electrode 14 is connected to the drain electrode through the first conductive pillar 13 and the cathode ring 400 reflects The electrode 14 is connected to the power supply electrode 401 through the first conductive pillar 13 as shown in FIG. 9.
  • the reflective electrode 14 of each display unit is used to form a microcavity structure with the cathode formed subsequently, and the strong reflection effect of the reflective electrode is used to make the light directly emitted by the organic light-emitting layer and the light reflected by the reflective electrode interact with each other. Interference improves the color gamut of the emitted light and strengthens the brightness of the emitted light.
  • a second insulating film is deposited on the silicon-based substrate 10 forming the foregoing structure, and the second insulating film is patterned through a patterning process to form a pattern of the second insulating layer 15 covering the silicon-based substrate 10, and the display area 100 and
  • the second insulating layer 15 of the offset region 200 respectively forms a plurality of third via holes
  • the second insulating layer 15 of the dummy pixel region 300 forms a plurality of fourth via holes
  • the second insulating layer 15 of the cathode ring 400 forms at least one first via.
  • a plurality of third vias respectively expose the reflective electrode 14 of each display unit
  • a plurality of fourth vias respectively expose the reflective electrode 14 of each dummy pixel area 300
  • a fifth via exposes the cathode ring 400 ⁇ Reflective electrode 14.
  • a plurality of second conductive pillars 16 are formed in the third via hole, the fourth via hole, and the fifth via hole on the second insulating layer 15. The second conductive pillar 16 in the third via hole is connected to the display unit.
  • the reflective electrode 14 is connected, the second conductive pillar 16 in the fourth via hole is connected to the reflective electrode 14 of the dummy pixel region 300, and the second conductive pillar 16 in the fifth via hole is connected to the reflective electrode 14 of the cathode ring 400, as shown in FIG. 10 shown.
  • the second conductive pillar 16 may be made of a metal material. After the second conductive pillar 16 is formed by a filling process, a polishing process may also be performed. The second insulating layer 15 and the second conductive pillar may be polished by a polishing process.
  • the surface of 16 is corroded and rubbed to remove part of the thickness of the second insulating layer 15 and the second conductive pillar 16 so that the second insulating layer 15 and the second conductive pillar 16 form a flat surface.
  • the second conductive pillar 16 may be metal tungsten (W).
  • a transparent conductive film is deposited on the silicon base substrate 10 forming the aforementioned structure, and the transparent conductive film is patterned through a patterning process.
  • An anode layer pattern is respectively formed on the insulating layer 15.
  • the anode layer includes a plurality of anodes 31 arranged in the display area 100, the offset area 200, the dummy pixel area 300 and the cathode ring 400.
  • the anodes 31 pass through the second conductive pillar 16 and the reflective electrode 14 Connect, as shown in Figure 11.
  • the anode 31 is connected to the reflective electrode 14 through the second conductive pillar 16, and the reflective electrode 14 is connected to the drain electrode of the driving thin film transistor 11 through the first conductive pillar 13, so that the electrical signal provided by the pixel driving circuit is transmitted through the reflective electrode 14.
  • the reflective electrode 14 forms a conductive channel between the pixel drive circuit and the anode on the one hand, and forms a microcavity structure on the other hand, which not only facilitates the control of the light emitting device by the pixel drive circuit, but also makes the structure of the display substrate more compact. It is beneficial to the miniaturization of silicon-based OLED display devices.
  • the organic light-emitting layer 33 is connected to the anode 31 of the display unit where it is located, and the planar cathode 34 It is connected to the organic light emitting layer 33 of each display unit; a cathode 34 is formed in the cathode ring 400, and the cathode 34 of the cathode ring 400 is connected to the anode 31 through the pixel opening, as shown in FIG. 12.
  • the cathode 34 is a semi-transmissive and semi-reverse electrode, and forms a microcavity structure with the reflective electrode 14 formed above.
  • the first insulating film and the second insulating film may be silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), and may be a single-layer structure or a multilayer composite structure.
  • the first metal film can be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al), or molybdenum (Mo), or can be made of metal alloy materials, such as aluminum neodymium (AlNd) or molybdenum Niobium alloy (MoNb), etc., the alloy material can be a single-layer structure or a multilayer composite structure, such as a Mo/Cu/Mo composite structure.
  • the transparent conductive film can be made of indium tin oxide (ITO) or indium zinc oxide (IZO), or a composite structure of ITO/Ag/ITO, and the pixel definition layer can be made of polyimide, acrylic or polyethylene terephthalate Wait.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • a composite structure of ITO/Ag/ITO and the pixel definition layer can be made of polyimide, acrylic or polyethylene terephthalate Wait.
  • an encapsulation layer pattern is formed in the display area 100, the offset area 200, the dummy pixel area 300, and the cathode ring 400.
  • the encapsulation layer 40 is a thin-film encapsulation structure, as shown in FIG. Show.
  • a pattern of the color filter layer 50 is formed on the display area 100, the offset area 200, the dummy pixel area 300 and the cathode ring 400, and the color of the display area 100 and the offset area 200
  • the film layer 50 includes a first color unit 53, a second color unit 54 and a third color unit 55 arranged at intervals or overlapping each other.
  • the color film layer 50 of the dummy pixel area 300 and the cathode ring 400 includes The first color unit 53 and the second color unit 54 are sequentially stacked from bottom to top, as shown in FIG. 14.
  • the first color cell may be a green cell G
  • the second color cell may be a red cell R
  • the third color cell may be a blue cell B.
  • the preparation process of the color filter layer 50 includes: first forming the blue unit B, then forming the red unit R, and then forming the green unit G.
  • the adhesion of the blue color film is relatively high. Forming the blue unit B first can reduce the possibility of the color film layer 50 peeling off from the cathode. Since the red cell R has low adhesion but good fluidity, in the process of forming the red cell R, the number of bubbles on the surface of the blue cell B and the red cell R away from the cathode can be reduced, thereby increasing the blue color.
  • the color film layer 50 may include other color units, such as white or yellow.
  • a sealing process is used to form the cover plate 60, and the cover plate 60 and the silicon-based substrate 10 are fixed by a sealant. Since the silicon-based substrate 10, the cover plate 60, and the sealant together form a closed space, it provides a guarantee for blocking water and oxygen, and greatly improves the life of the silicon-based OLED display substrate. Subsequently, the formed display mother board is cut to form a separate display substrate.
  • FIG. 15 is a schematic diagram of a structure of the organic light-emitting layer of the present disclosure.
  • the structure of the organic light-emitting layer of the present disclosure includes a first light-emitting sublayer 331, a first charge generation layer 332, a second light-emitting sublayer 333, and a second charge generation layer sequentially stacked between the anode and the cathode. 334 and the third light-emitting sublayer 335.
  • the first light emitting sublayer 331 is configured to emit light of the first color, and includes a first hole transport layer (HTL) 3311, a first light emitting material layer (EML) 3312, and a first electron transport layer (ETL) 3313 that are sequentially stacked.
  • HTL hole transport layer
  • EML light emitting material layer
  • ETL electron transport layer
  • the second light emitting sub-layer 333 is configured to emit light of the second color, and includes a second hole transport layer 3331, a second light emitting material layer 3332, and a second electron transport layer 3333 that are sequentially stacked.
  • the third light-emitting sublayer 335 is configured to emit light of the third color, and includes a third hole transport layer 3351, a third light-emitting material layer 3352, and a third electron transport layer 3353 that are sequentially stacked.
  • the first charge generation layer 332 is disposed between the first light-emitting sub-layer 331 and the second light-emitting sub-layer 333, and is used to connect the two light-emitting sub-layers in series to realize the transfer of carriers.
  • the second charge generation layer 334 is disposed between the second light-emitting sub-layer 333 and the third light-emitting sub-layer 335, and is used to connect the two light-emitting sub-layers in series to realize the transfer of carriers. Since the organic light-emitting layer of the present disclosure includes a first light-emitting material layer that emits light of a first color, a second light-emitting material layer that emits light of a second color, and a third light-emitting material layer that emits light of a third color, the organic light-emitting layer finally emits light The light is mixed light.
  • the first light-emitting material layer is a red light material layer that emits red light
  • the second light-emitting material layer is a green light material layer that emits green light
  • the third light-emitting material layer is a blue material layer that emits blue light. The layer finally emits white light.
  • the organic light-emitting layer shown in FIG. 15 is only an example structure, and the present disclosure does not limit this.
  • the structure of the organic light-emitting layer can be designed according to actual needs.
  • a hole injection layer (HIL) and an electron injection layer (EIL) may also be provided.
  • the first electron transport layer 3313, the first charge generation layer 332, and the second hole transport layer 3331 can be eliminated, that is, the second light-emitting material layer 3332 can be directly disposed on the first light-emitting material.
  • the organic light-emitting layer may be an organic light-emitting layer that emits light of the first color and an organic light-emitting layer that emits complementary light of the first color light, and the two organic light-emitting layers are sequentially stacked relative to the silicon-based substrate. Therefore, the white light is emitted as a whole, and the present disclosure does not limit this, as long as the white light can be realized.
  • the actual display can be adjusted.
  • the position of the display area moves toward the offset area to avoid the pixel units damaged by the packaging patch, so as to ensure that the actual number of pixels displayed is consistent with the pre-designed number of pixels.
  • the preparation process of the present disclosure can be realized by using mature preparation equipment, with little process improvement, high compatibility, simple process flow, easy periodic maintenance of equipment, high production efficiency, low production cost, high yield rate, and convenient mass production
  • the prepared display substrate can be used in virtual reality equipment or enhanced display equipment, or in other types of display devices, and has a good application prospect.
  • the structure shown in the present disclosure and the preparation process thereof are only an exemplary description.
  • the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs.
  • the length of the microcavity structure of each display unit may be the same or may be different.
  • the bonding area may form a corresponding pad, which is not specifically limited in the present disclosure.
  • the present disclosure also provides a display method. As shown in FIG. 16, the display method includes steps S1 to S2.
  • step S1 includes: performing dead pixel detection on a plurality of pixel units in the display area.
  • the performing dead pixel detection on a plurality of pixel units in the display area includes:
  • each group When each group emits light, it is determined whether the group includes dead pixels and the number of dead pixels included according to whether the pixel units in the group emit light.
  • Step S2 includes: adjusting the pixel row output by the gate driver or the pixel column output by the source driver when the first predetermined number of pixel units close to the side edge of the display area include dead pixels exceeding a second predetermined ratio Move to the side opposite to the side where the dead pixel is located.
  • adjusting the pixel row output by the gate driver or the pixel column output by the source driver to move to the side opposite to the side where the dead pixel is located includes:
  • the gate driver and the source driver drive the pixel units from row A to row B, and column C to column D for display;
  • the pixel columns output by the source driver are adjusted to be the (CN-1)th column to the (CN-1)th column (DN-1) column;
  • the source The pixel column output by the source driver is from the 21st to the 1101th column; when the display area near the right edge of the pixel unit from the 1094th column to the 1097th column contains more than 50% of the dead pixels, adjust the pixel column output by the source driver From the 13th column to the 1093th column; when the display area near the upper edge of the pixel unit from the 17th to the 20th row contains more than 50% of the dead pixels, adjust the pixel behavior of the gate driver output from the 21st to the 1941th Line; when the pixel unit from line 1934 to line 1937 near the lower edge of the display area includes more than 50% of dead pixels, adjust the pixel line output by the gate driver from line 13 to line 1933.
  • the display method of this embodiment adjusts the pixel row or source output by the gate driver when the first preset number of first pixel units close to the side edge of the display area include dead pixels exceeding the second preset ratio.
  • the pixel column output by the pole driver moves to the opposite side of the side where the dead pixel is located, so that when some of the pixel units in the display area on one side of the display module are damaged due to packaging, patching and other processes, the position of the actual display area can be adjusted to avoid the cause. Pack the damaged pixels of the patch to ensure that the actual number of pixels displayed is consistent with the pre-designed number of pixels.
  • the present disclosure also provides a display device including the aforementioned display substrate.
  • the display device may be a virtual reality device, an augmented reality device, or a near-eye display device, or may be a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator, or any other product or component with a display function.
  • the display device also includes: a gate driver, a source driver, and a timing controller, wherein:
  • the gate driver is connected to the display substrate through the row scan line GL, and is configured to receive the gate control signal GCS output by the timing controller, generate a scan signal, and transmit the scan signal to the actual display on the display substrate through the scan line GL Area, the actual display area is adjusted according to the position and number of the dead pixels of the first pixel unit on the display substrate;
  • the source driver is configured to receive the data voltage Vdata and the source control signal SCS output by the timing controller, generate a corresponding data voltage signal and output it to the actual display area on the display substrate through the data line DL.
  • the actual display area Adjust according to the position and number of dead pixels of the pixel unit on the display substrate;
  • the timing controller is configured to receive externally input RGB (red, green, and blue) data and timing control (Timing Control) signals; generate data voltage Vdata and source control signals according to RGB data, timing control signals and pixel columns to be output
  • RGB red, green, and blue
  • Timing Control timing control
  • the SCS is output to the source driver, a gate driving signal GCS is generated according to the pixel row to be output, and the gate driving signal GCS is output to the gate driver.
  • the actual display area is adjusted according to the position and number of the dead pixels of the first pixel unit on the display substrate, including:
  • the gate driver and the source driver drive the pixel units from row A to row B, and column C to column D for display;
  • the gate driver and the source driver drive the rows A to B,
  • the pixel units in the (C+N+1)th column to the (D+N+1)th column perform display;
  • the gate driver and the source driver drive the Ath to Bth rows and the ( The pixel units from column CN-1) to column (DN-1) are displayed;
  • the gate driver and the source driver drive (A+M+1)
  • the pixel units from row to row (B+M+1) and from column C to column D perform display;
  • the gate driver and the source driver drive the (AM-1)th to the (AM-1)th row to the (AM-1)th row to the (AM-1)th row to (BM-1)
  • the pixel units in row, column C to column D are displayed, where A, B, C, D, N, and M are all natural numbers greater than or equal to 1, and A ⁇ B, C ⁇ D, N ⁇ C, M ⁇ A.
  • the number of pixel columns contained in the left offset area and the right offset area are both 16 columns
  • the upper offset area and the lower offset area The number of pixel rows included in the shift area is 16 rows
  • the second preset ratio is 50%.
  • the source The pixel column output by the driver is column 21 to column 1101; when the display area near the right edge of the pixel unit from column 1094 to column 1097 contains more than 50% of the dead pixels, the pixel column output by the source driver is column No.
  • the gate driver output pixel line 21st to 1941th; when the pixel units from rows 1934 to 1937 near the lower edge of the display area include more than 50% of the dead pixels, the pixel rows output by the gate driver are rows 13 to 1933.

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Abstract

一种显示基板及显示方法、显示装置，其中，显示基板包括显示区域(100)以及围绕显示区域(100)的偏移区域(200)，显示基板包括硅基衬底(10)、设置在硅基衬底(10)上的发光结构层(20)，显示区域(100)的硅基衬底(10)集成有第一像素驱动电路，偏移区域(200)的硅基衬底(10)集成有第二像素驱动电路；第一像素驱动电路与显示区域(100)的发光结构层(20)连接，至少部分第一像素驱动电路被配置为：在正常显示时，为与第一像素驱动电路电连接的发光结构层(20)提供驱动信号；第二像素驱动电路与偏移区域(200)的发光结构层(20)连接，至少部分第二像素驱动电路被配置为：在正常显示时，不为与第二像素驱动电路电连接的发光结构层(20)提供驱动信号。

Description

显示基板及显示方法、显示装置 技术领域
本公开涉及但不限于显示技术领域，尤其涉及一种显示基板及显示方法、显示装置。
背景技术
随着增强现实/虚拟现实(Virtual Reality/Augmented Reality，VR/AR)技术的日益进步和市场的快速增长，适用于VR/AR领域的显示面板也正在加急步伐向微型化、高像素密度(Pixels Per Inch，PPI)、快速响应和高色域的方向发展，而硅基有机发光二极管(Organic Light-Emitting Diode，OLED)微显示面板正是其中突出的一个方向。虽然硅基OLED微显示技术起步较晚，但凭借着其微型化和高PPI的优势，也正在成为显示领域的新的关注焦点。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种显示基板，包括显示区域以及围绕显示区域的偏移区域，在垂直于所述显示基板所在平面的方向上，所述显示基板包括硅基衬底、设置在硅基衬底上的发光结构层、设置在所述发光结构层远离所述硅基衬底一侧的封装层，所述显示区域的硅基衬底集成有第一像素驱动电路，所述偏移区域的硅基衬底集成有第二像素驱动电路；所述第一像素驱动电路与所述显示区域的发光结构层连接，至少部分所述第一像素驱动电路被配置为：在正常显示时，为与所述第一像素驱动电路电连接的发光结构层提供驱动信号；所述第二像素驱动电路与所述偏移区域的发光结构层连接，至少部分所述第二像素驱动电路被配置为：在正常显示时，不为与所述第二像素驱动电路电连接的发光结构层提供驱动信号。
在一些可能的实现方式中，全部所述第一像素驱动电路均配置为：为与 所述第一像素驱动电路电连接的发光结构层提供驱动信号。
在一些可能的实现方式中，所述偏移区域包括左侧偏移区域、右侧偏移区域和/或上侧偏移区域和下侧偏移区域，所述左侧偏移区域和右侧偏移区域包含的像素列数的差值不超过10行，所述上侧偏移区域和下侧偏移区域包含的像素行数的差值不超过10行。
在一些可能的实现方式中，所述左侧偏移区域和右侧偏移区域包含的像素列数相等，所述上侧偏移区域和下侧偏移区域包含的像素行数相等。
在一些可能的实现方式中，所述左侧偏移区域或右侧偏移区域的像素单元的列数与所述显示区域的像素单元的列数的比值大于或等于1％；所述上侧偏移区域或下侧偏移区域的像素单元的行数与显示区域的像素单元的行数的比值大于或等于1％。
在一些可能的实现方式中，所述显示基板还包括设置在所述封装层远离所述发光结构层一侧的彩膜层，所述显示区域和偏移区域的彩膜层分别包括呈阵列设置的第一颜色单元、第二颜色单元和第三颜色单元。
在一些可能的实现方式中，所述的显示基板还包括至少部分围绕偏移区域的虚设像素区，在垂直于所述显示基板所在平面的方向上，所述虚设像素区包括硅基衬底、设置在硅基衬底上的发光结构层、设置在所述发光结构层远离所述硅基衬底一侧的封装层。
本公开实施例还提供了一种显示装置，包括：如前任一项所述的显示基板，还包括：栅极驱动器、源极驱动器和时序控制器，其中：所述栅极驱动器，被配置为接收时序控制器输出的栅极控制信号，产生扫描信号并通过扫描线传送给显示基板上的实际显示区域，所述实际显示区域根据所述显示基板上的像素单元的坏点的位置和数目进行调整；所述源极驱动器，被配置为接收时序控制器输出的数据电压和源极控制信号，产生相应的数据电压信号并通过数据线输出给显示基板上的实际显示区域；所述时序控制器，被配置为接收外部输入的红绿蓝数据和时序控制信号；根据红绿蓝数据和时序控制信号，生成数据电压和源极控制信号并输出给源极驱动器，生成栅极驱动信号并输出给栅极驱动器。
在一些可能的实现方式中，所述实际显示区域根据所述显示基板上的像素单元的坏点的位置和数目进行调整，包括：初始显示时，所述栅极驱动器和源极驱动器驱动第A行至第B行、第C列至第D列的像素单元进行显示；当所述显示区域靠近左侧边缘的第C列至第(C+N)列像素单元中包括超过第二预设比例的坏点时，所述栅极驱动器和源极驱动器驱动第A行至第B行、第(C+N+1)列至第(D+N+1)列的像素单元进行显示；当所述显示区域靠近右侧边缘的第(D-N)列至第D列像素单元中包括超过第二预设比例的坏点时，所述栅极驱动器和源极驱动器驱动第A行至第B行、第(C-N-1)列至第(D-N-1)列的像素单元进行显示；当所述显示区域靠近上侧边缘的第A行至第(A+M)行像素单元中包括超过第二预设比例的坏点时，所述栅极驱动器和源极驱动器驱动第(A+M+1)行至第(B+M+1)行、第C列至第D列的像素单元进行显示；当所述显示区域靠近下侧边缘的第(B-M)行至第B行像素单元中包括超过第二预设比例的坏点时，所述栅极驱动器和源极驱动器驱动第(A-M-1)行至第(B-M-1)行、第C列至第D列的像素单元进行显示，其中，A、B、C、D、N和M均为大于或等于1的自然数，且A<B，C<D，N<C，M<A。
本公开实施例还提供了一种显示方法，包括：对显示区域的多个像素单元进行坏点检测；当显示区域靠近一侧边缘的第一预设个数的像素单元中包括超过第二预设比例的坏点时，调整栅极驱动器输出的像素行或源极驱动器输出的像素列朝坏点所在侧的对侧移动。
在一些可能的实现方式中，所述当显示区域靠近一侧边缘的第一预设个数的像素单元中包括超过第二预设比例的坏点时，调整栅极驱动器输出的像素行或源极驱动器输出的像素列朝坏点所在侧的对侧移动，包括：初始显示时，所述栅极驱动器和源极驱动器驱动第A行至第B行、第C列至第D列的像素单元进行显示；当所述显示区域靠近左侧边缘的第C列至第(C+N)列像素单元中包括超过第二预设比例的坏点时，调整源极驱动器输出的像素列为第(C+N+1)列至第(D+N+1)列；当所述显示区域靠近右侧边缘的第(D-N)列至第D列像素单元中包括超过第二预设比例的坏点时，调整源极驱动器输出的像素列为第(C-N-1)列至第(D-N-1)列；当所述显示区域靠 近上侧边缘的第A行至第(A+M)行像素单元中包括超过第二预设比例的坏点时，调整栅极驱动器输出的像素行为第(A+M+1)行至第(B+M+1)行；当所述显示区域靠近下侧边缘的第(B-M)行至第B行像素单元中包括超过第二预设比例的坏点时，调整栅极驱动器输出的像素行为第(A-M-1)行至第(B-M-1)行，其中，A、B、C、D、N和M均为大于或等于1的自然数，且A<B，C<D，N<C，M<A。
在一些可能的实现方式中，所述对显示区域的多个像素单元进行坏点检测，包括：将所述显示区域的多个像素单元进行分组；驱动多个分组依次发光；在每个分组发光时，根据该分组中的像素单元是否发光确定该分组中是否包括坏点以及包括的坏点的数目。
在阅读并理解了附图概述和本公开的实施方式后，可以明白其他方面。
附图说明
图1为本公开显示基板的一种结构示意图；
图2为图1中显示基板左侧边缘像素损坏时，实际显示区域右移示意图；
图3为图1中显示基板下侧边缘像素损坏时，实际显示区域上移示意图；
图4为本公开显示基板的剖面示意图；
图5为本公开硅基衬底一种电路原理的示意图；
图6为本公开电压控制电路和像素驱动电路一种电路实现的示意图；
图7为本公开一种显示基板制备硅基衬底后的示意图；
图8为本公开一种显示基板形成第一绝缘层和第一导电柱后的示意图；
图9为本公开一种显示基板形成反射电极后的示意图；
图10为本公开一种显示基板形成第二绝缘层和第二导电柱后的示意图；
图11为本公开一种显示基板形成阳极层后的示意图；
图12为本公开一种显示基板形成有机发光层和阴极后的示意图；
图13为本公开一种显示基板形成封装层后的示意图；
图14为本公开一种显示基板形成彩膜层后的示意图；
图15为本公开一种有机发光层结构示意图；
图16为本公开一种显示方法的流程示意图。
附图标记说明：
Figure PCTCN2020081857-appb-000001
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此， 本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的实施方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的实施方式不局限于附图所示的形状或数值。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，可以是第一极为漏电极、第二极为源电极，或者可以是第一极为源电极、第二极为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
在硅基OLED微显示器制作过程中，封装、贴片等工艺有时会导致显示模组某一边的显示区部分像素损坏，进而导致显示时，实际显示的像素点数低于预先设计的像素点数。
本公开至少一实施例提供一种显示基板，该显示基板包括显示区域以及围绕显示区域的偏移区域，在垂直于显示基板所在平面的方向上，显示基板包括硅基衬底、设置在硅基衬底上的发光结构层、设置在发光结构层远离硅基衬底一侧的封装层，显示区域的硅基衬底集成有第一像素驱动电路，偏移区域的硅基衬底集成有第二像素驱动电路；第一像素驱动电路与显示区域的发光结构层连接，至少部分第一像素驱动电路被配置为：在正常显示时，为与第一像素驱动电路电连接的发光结构层提供驱动信号；第二像素驱动电路与偏移区域的发光结构层连接，至少部分第二像素驱动电路被配置为：在正常显示时，不为与第二像素驱动电路电连接的发光结构层提供驱动信号。
本公开一些实施例还提供对应于上述显示基板的显示装置及显示方法。
本公开上述实施例提供的显示基板，通过设置偏移区域，使得当封装、贴片等工艺导致显示模组某一边缘的显示区域部分像素单元损坏时，可以调整实际显示区域的位置朝偏移区域移动，避开因封装贴片损坏的像素单元，以保证实际显示的像素点数与预先设计的像素点数一致。
图1是本公开的一种显示基板的结构示意图。如图1所示，在本实施例中，该显示基板包括显示区域100以及围绕显示区域100的偏移区域200，在垂直于显示基板所在平面的方向上，显示基板包括硅基衬底、设置在硅基衬底上的发光结构层、设置在发光结构层远离硅基衬底一侧的封装层，显示区域的硅基衬底集成有第一像素驱动电路，偏移区域的硅基衬底集成有第二像素驱动电路；第一像素驱动电路与显示区域的发光结构层连接，至少部分第一像素驱动电路被配置为：在正常显示时，为与第一像素驱动电路电连接的发光结构层提供驱动信号；第二像素驱动电路与偏移区域的发光结构层连接，至少部分第二像素驱动电路被配置为：在正常显示时，不为与第二像素驱动电路电连接的发光结构层提供驱动信号。
在一种示例性实施例中，全部第一像素驱动电路均配置为：为与第一像素驱动电路电连接的发光结构层提供驱动信号。
在一种示例性实施例中，如图1所示，显示基板还可以包括至少部分围绕偏移区域200的虚设像素区域300，在垂直于显示基板所在平面的方向上，虚设像素区域300可以包括硅基衬底、设置在硅基衬底上的发光结构层、设置在所述发光结构层远离硅基衬底一侧的封装层。
在一种示例性实施例中，如图1所示，显示基板还可以包括围绕虚设像素区域300的阴极环400，在垂直于显示基板所在平面的方向上，阴极环400可以包括设置在硅基衬底上的供电电极层、设置在供电电极层远离硅基衬底一侧的反射层、设置在反射层远离供电电极层一侧的阳极层以及设置在阳极层远离反射层一侧的阴极层。
在一种示例性实施例中，如图1所示，显示区域100包括多个第一像素单元101，偏移区域200包括多个第二像素单元201，第二像素单元201被配置为第一像素单元101的备用像素单元。
在一种示例性实施例中，该显示基板可以为硅基OLED微显示基板或其他任意类型的显示基板。硅基OLED微显示基板采用单晶硅晶圆作为有源驱动背板，具有高PPI、高度集成、体积小、易于携带、抗震性能好、超低功耗等优异特性。
在一种示例性实施例中，偏移区域200可以包括以下任意一个或多个： 左侧偏移区域、右侧偏移区域、上侧偏移区域和下侧偏移区域，左侧偏移区域和右侧偏移区域包含的像素列数的差值不超过10行，上侧偏移区域和下侧偏移区域包含的像素行数的差值不超过10行。
在一种示例性实施例中，左侧偏移区域和右侧偏移区域包含的像素列数可以相等。
如图2所示，当显示区域100靠近左侧边缘的第一像素单元101中包括超过第二预设比例的坏点102时，调整源极驱动器输出的像素列朝右侧移动，即实际显示区域右移。同理，当显示区域100靠近右侧边缘的第一像素单元101中包括超过第二预设比例的坏点102时，调整源极驱动器输出的像素列朝左侧移动，即实际显示区域左移。
在一种示例性实施例中，左侧偏移区域的第二像素单元的列数与显示区域的第一像素单元的列数的比值大于或等于1％，右侧偏移区域的第二像素单元的列数与显示区域的第一像素单元的列数的比值大于或等于1％。示例性的，当显示区域包括1920行*1080列第一像素单元时，左侧偏移区域包括的第二像素单元的列数为0列至16列之间，右侧偏移区域包括的第二像素单元的列数为0列至16列之间。通过设置合理数量的第二像素单元，使得在显示基板的实际显示空间不被浪费的同时，留有一定的备选显示空间，以备预设显示区域的第一像素单元有边缘被损坏时使用。
在一种示例性实施例中，上侧偏移区域和下侧偏移区域包含的像素行数可以相等。
如图3所示，当显示区域100靠近下侧边缘的第一像素单元101中包括超过第二预设比例的坏点102时，调整栅极驱动器输出的像素行朝上侧移动，即实际显示区域上移。同理，当显示区域100靠近上侧边缘的第一像素单元101中包括超过第二预设比例的坏点102时，调整栅极驱动器输出的像素行朝下侧移动，即实际显示区域下移。
在一种示例性实施例中，上侧偏移区域的第二像素单元的行数与显示区域的第一像素单元的行数的比值大于或等于1％，下侧偏移区域的第二像素单元的行数与显示区域的第一像素单元的行数的比值大于或等于1％。示例性的，当显示区域包括1920行*1080列第一像素单元时，上侧偏移区域包括 的第二像素单元的行数为0行至16行之间，下侧偏移区域包括的第二像素单元的行数为0行至16行之间。通过设置合理数量的第二像素单元，使得在显示基板的实际显示空间不被浪费的同时，留有一定的备选显示空间，以备预设显示区域的第一像素单元有边缘被损坏时使用。
本实施例中，如图4所示，在垂直于显示基板的平面内，显示基板的显示区域100和偏移区域200分别包括硅基衬底10、设置在硅基衬底10上的发光结构层20、设置在发光结构层20上的封装层40以及设置在封装层40上的彩膜层50。显示基板的显示区域100和偏移区域200的硅基衬底10，集成有用于产生驱动信号的像素驱动电路、用于产生栅极驱动信号的栅极驱动电路和用于产生数据信号的数据驱动电路。发光结构层20包括在硅基衬底10上叠设的反射层、阳极层、有机发光层和阴极层，反射层用于与阴极层构成微腔结构，使得有机发光层直接出射的光线与反射层反射的光线相互干涉，提高出射光的色域，强化出射光的亮度。在一示例性实施方式中，发光结构层20还可以包括像素定义层或平坦层等结构膜层。封装层40包裹发光结构层20是指，封装层40设置在发光结构层20远离硅基衬底10一侧的上表面上，以及设置在发光结构层20的所有侧表面上，使封装层40与硅基衬底10构成密封腔体，发光结构层20设置在该密封腔体内。在平行于硅基衬底10和垂直于硅基衬底10的平面内，封装层40在硅基衬底10上的正投影包含发光结构层20在硅基衬底10上的正投影。
在一种示例性实施例中，显示区域100和偏移区域200的彩膜层50分别包括成阵列设置的第一颜色单元53、第二颜色单元54和第三颜色单元55，其中，第一颜色单元53、第二颜色单元54和第三颜色单元55可以分别为红(R)色滤光单元(Color Filter，CF)、绿(G)色滤光单元和蓝(B)色滤光单元中的其中一种。在一些可能的实现方式中，彩膜层50中颜色单元可以相互交叠作为黑矩阵，或者在颜色单元之间设置黑矩阵。本公开采用白光+彩膜方式可以实现大于2000的高分辨率，能够适应VR/AR需求。
在一种示例性实施例中，有机发光层33中的至少一层可以整面设置，也可以单独按照每个像素区域设置，可以满足每个像素区域中的各颜色的发光层叠置发出白光即可。
在一种示例性实施例中，有机发光层33也可以是如红、绿、蓝三种颜色的发光层分别阵列排布，每个像素区域中单独发出红光、蓝光、绿光。
在一种示例性实施例中，虚设像素区域300不包括彩膜结构；当例如基板上某一侧的偏移区域200中的显示单元未被使用时，偏移区域200中的显示单元上方的彩膜层可以作为虚设彩膜平衡彩膜层在制作时，由于曝光显影不均匀而带来的不均匀问题。
在一种示例性实施例中，虚设像素区域300可以包括彩膜结构；其可以与显示区域中的彩膜层设置方式相同，本实施例不再赘述。
在一种示例性实施例中，阴极环400上方上可以设置彩膜层，该区域彩膜层可以延伸至外围区域。
在一种示例性实施例中，显示基板还可以包括盖板70，盖板70设置在彩膜层50的上方，可以实现保护彩膜50的功能。在一示例性实施方式中，盖板70通过密封胶与硅基衬底10连接，密封胶设置于硅基衬底10与盖板70之间，可以为阻隔水氧入侵提供进一步的保障，使硅基OLED显示基板寿命大幅提升。在另一示例性实施方式中，密封胶可以设置于盖板70的侧面，盖板70的四周侧面与硅基衬底10之间通过密封胶密封，密封胶远离硅基衬底10一侧的端面位于盖板70邻近硅基衬底10一侧的表面与盖板70远离硅基衬底10一侧的表面之间，由此既能够确保密封效果，又可以防止密封胶高出盖板70导致显示基板的厚度增加。在示例性实施方式中，盖板70设置在显示区域100，可以较好地实现对位和密封，避免在切割过程中导致盖板70破裂。
在一种示例性实施例中，显示基板还可以包括保护层60，保护层60设置在彩膜层50和盖板70之间，保护层60覆盖彩膜层50。在一示例性实施方式中，保护层60可以采用SiC或SiCNx，由于SiC或SiCNx倾向于具有无机特性，一方面可以保护彩膜层50，减少彩膜层50的老化损伤，增加使用寿命，另一方面可以形成平坦表面，便于后续贴合盖板工艺中胶材的流平，提高盖板贴合质量。
图5为本公开硅基衬底一种电路原理的示意图。硅基衬底10包括位于显 示区域100(AA区)和偏移区域200中的多个显示单元和位于外围区域中的控制电路，显示区域100中的多个显示单元规则排布，形成多个显示行和多个显示列，每个显示单元包括像素驱动电路103以及与像素驱动电路103连接的发光器件104，像素驱动电路103至少包括驱动晶体管。控制电路至少包括多个电压控制电路110，每个电压控制电路110与多个像素驱动电路103连接。例如，一个电压控制电路110与一个显示行中的像素驱动电路103连接，该显示行像素驱动电路103中驱动晶体管的第一极共同连接该电压控制电路110，每个驱动晶体管的第二极与本显示单元的发光器件104的阳极连接，发光器件104的阴极连接第二电源信号VSS的输入端。电压控制电路110分别与第一电源信号VDD的输入端、初始化信号Vinit的输入端、复位控制信号RE的输入端和发光控制信号EM的输入端连接，电压控制电路110被配置为响应于复位控制信号RE，将初始化信号Vinit输出至驱动晶体管的第一极，控制对应的发光器件104复位。电压控制电路110还被配置为响应于发光控制信号EM，将第一电源信号VDD输出至驱动晶体管的第一极，以驱动发光器件104发光。通过一个显示行中的像素驱动电路103共同连接电压控制电路110，可以简化显示区域100中每个像素驱动电路103的结构，降低显示区域100中像素驱动电路103的占用面积，从而使显示区域100设置更多的像素驱动电路103和发光器件104，实现高PPI显示。电压控制电路110在复位控制信号RE的控制下将初始化信号Vinit输出至驱动晶体管的第一极，控制对应的发光器件104复位，可以避免上一帧发光时加载于发光器件104上的电压对下一帧发光的影响，可以改善残影现象。
在示例性实施方式中，3个不同颜色的显示单元组成1个像素单元(该像素单元可以是第一像素单元，或可以是第二像素单元)，3个显示单元可以分别为红色显示单元、绿色显示单元以及蓝色显示单元。在一些可能的实现方式中，1个像素单元可以包括4个、5个或更多的显示单元，可以根据实际应用环境来设计确定，在此不作限定。在一些可能的实现方式中，一个电压控制电路110可以连接同一显示行中两个相邻的显示单元中的像素驱动电路103，或可以连接同一显示行中三个或更多的显示单元中的像素驱动电路103，在此不作限定。
图6为本公开电压控制电路和像素驱动电路一种电路实现的示意图。如图6所示，发光器件可以包括OLED，OLED的阳极与驱动晶体管M0的第二极D连接，OLED的阴极与第二电源信号VSS的输入端连接，第二电源信号VSS的电压一般为负电压或接地电压V GND(一般为0V)，初始化信号Vinit的电压也可以设置为接地电压V GND。在示例性实施方式中，OLED可以是Micro-OLED或Mini-OLED，有利于实现高PPI显示。
在示例性实施方式中，电压控制电路110与一显示行中的两个像素驱动电路103连接，像素驱动电路103包括驱动晶体管M0、第三晶体管M3、第四晶体管M4和存储电容Cst，电压控制电路110包括第一晶体管M1和第二晶体管M2。驱动晶体管M0、第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4均是制备在硅基衬底中的金属氧化物半导体场效应管(Metal Oxide Semiconductor，MOS)。
第一晶体管M1的控制极与复位控制信号RE的输入端连接，用于接收复位控制信号RE，第一晶体管M1的第一极与初始化信号Vinit的输入端连接，用于接收初始化信号Vinit，第一晶体管M1的第二极分别与对应的驱动晶体管M0的第一极S和第二晶体管M2的第二极连接。第二晶体管M2的控制极与发光控制信号EM的输入端连接，用于用于接收发光控制信号EM，第二晶体管M2的第一极与第一电源信号VDD的输入端连接，用于接收第一电源信号VDD，第二晶体管M2的第二极分别与对应的驱动晶体管M0的第一极S和第一晶体管M1的第二极连接。在示例性实施方式中，第一晶体管M1与第二晶体管M2的类型可以不同，例如，第一晶体管M1为N型晶体管，第二晶体管M2为P型晶体管，或者，第一晶体管M1为P型晶体管，第二晶体管M2为N型晶体管。在一些可能的实现方式中，第一晶体管M1与第二晶体管M2的类型可以相同，可以根据实际应用环境来设计确定，在此不作限定。
像素驱动电路103包括驱动晶体管M0、第三晶体管M3、第四晶体管M4和存储电容Cst。驱动晶体管M0的控制极G，驱动晶体管M0的第一极S与第一晶体管M1的第二极和第二晶体管M2的第二极连接，驱动晶体管M0的第二极D与OLED的阳极连接。第三晶体管M3的控制极与第一控制 极扫描信号S1的输入端连接，用于接收第一控制极扫描信号S1，第三晶体管M3的第一极与数据信号DA的输入端连接，用于接收数据信号DA，第三晶体管M3的第二极与驱动晶体管M0的控制极G连接。第四晶体管M4的控制极与第二控制极扫描信号S2的输入端连接，用于接收第二控制极扫描信号S2，第四晶体管M4的第一极与数据信号DA的输入端连接，用于接收数据信号DA，第四晶体管M4的第二极与驱动晶体管M0的控制极G连接。存储电容Cst的第一端与驱动晶体管M0的控制极G连接，存储电容Cst的第二端与接地端GND连接。在示例性实施方式中，驱动晶体管M0可以为N型晶体管，第三晶体管M3与第四晶体管M4的类型可以不同，例如，第三晶体管M3为N型晶体管，第四晶体管M4为P型晶体管。当数据信号DA的电压为高灰阶对应的电压时，通过P型的第四晶体管M4导通以将数据信号DA传输给驱动晶体管M0的控制极G，可以避免数据信号DA的电压受例如N型的第三晶体管M3的阈值电压的影响。当数据信号DA的电压为低灰阶对应的电压时，通过N型的第三晶体管M3导通以将数据信号DA传输给驱动晶体管M0的控制极G，可以避免数据信号DA的电压受P型的第四晶体管M4的阈值电压的影响。这样，可以提高输入到驱动晶体管M0的控制极G上的电压范围。在一些可能的实现方式中，第三晶体管M3与第四晶体管M4的类型可以是，第三晶体管M3为P型晶体管，第四晶体管M4为N型晶体管。在一些可能的实现方式中，像素驱动电路可以是3T1C、5T1C或7T1C电路结构，或可以是具有内部补偿或外部补偿功能的电路结构，本公开对此不作限制。
下面通过显示基板的制备过程的示例说明显示基板的结构。本公开所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶处理。沉积可以采用溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用喷涂和旋涂中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。若在整个制作过程中该“薄膜”需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一 个“图案”。本公开中所说的“A和B同层设置”是指，A和B通过同一次构图工艺同时形成。本公开中所说的“A的正投影包含B的正投影”是指，B的正投影落入A的正投影范围内，或者A的正投影覆盖B的正投影。
(1)制备硅基衬底10，硅基衬底10包括显示区域100和包围显示区域100的外围区域，外围区域包括偏移区域200、虚设像素区域300和阴极环400，显示区域100和偏移区域200的硅基衬底10均集成有像素驱动电路，阴极环400的硅基衬底10集成有供电电路，如图7所示。作为一种示例性说明，图7中示意了显示区域100的三个显示单元：第一首选显示单元、第二首选显示单元和第三首选显示单元，示意了偏移区域200的三个显示单元：第一备选显示单元、第二备选显示单元和第三备选显示单元，示意了像素驱动电路所包括的驱动晶体管11，示意了阴极环400的供电电极401。在一示例性实施方式中，显示区域100和偏移区域200的驱动薄膜晶体管分别包括有源层、栅电极、源电极、漏电极和栅连接电极，源电极和漏电极分别通过导电柱与有源层连接，栅连接电极通过导电柱与栅电极连接。制备硅基衬底10可以采用成熟的CMOS集成电路工艺，本公开对此不作限制。制备完成后，硅基衬底10的表面暴露出显示区域100的源电极、漏电极和栅连接电极，偏移区域200的源电极、漏电极和栅连接电极，阴极环400的供电电极401。
(2)在硅基衬底10上沉积第一绝缘薄膜，通过构图工艺对第一绝缘薄膜进行构图，形成覆盖硅基衬底10的第一绝缘层12图案，显示区域100和偏移区域200的第一绝缘层12分别形成多个第一过孔，阴极环400的第一绝缘层12形成至少一个第二过孔，多个第一过孔分别暴露出每个显示单元的漏电极，第二过孔暴露出供电电极301。随后，在第一绝缘层12上的第一过孔和第二过孔内形成多个第一导电柱13，第一过孔内的第一导电柱13与所在显示单元的漏电极连接，第二过孔内的第一导电柱13与阴极环400的供电电极401连接，如图8所示。在示例性实施方式中，第一导电柱13可以由金属材料制成，通过填充处理形成第一导电柱13后，还可以进行抛光处理，通过抛光工艺对第一绝缘层12和第一导电柱13的表面进行腐蚀和摩擦，去除第一绝缘层12和第一导电柱13的部分厚度，使第一绝缘层12和第一导电柱13形成平齐的表面。在一些可能的实现方式中，第一导电柱13可以采用金 属钨(W)，由钨金属填充的过孔称为钨过孔(W-via)。在第一绝缘层12厚度较大的情况下，采用钨过孔可以保证导电通路的稳定性，由于制作钨过孔的工艺成熟，所得到的第一绝缘层12的表面平坦度好，有利于降低接触电阻。钨过孔不仅适用于硅基衬底10与反射层之间的连接，还适用于反射层与阳极层之间的连接，以及其它布线层之间的连接。
(3)在形成前述结构的硅基衬底10上沉积第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，在第一绝缘层12上形成反射层图案，反射层包括设置在显示区域100、偏移区域200、虚设像素区域300和阴极环400内的多个反射电极14，在每个显示单元内，反射电极14通过第一导电柱13与漏电极连接，在阴极环400，反射电极14通过第一导电柱13与供电电极401连接，如图9所示。在示例性实施方式中，每个显示单元的反射电极14用于与后续形成的阴极构成微腔结构，利用反射电极的强反射效应，使得有机发光层直接出射的光线与反射电极反射的光线相互干涉，提高了出射光的色域，强化了出射光的亮度。
(4)在形成前述结构的硅基衬底10上沉积第二绝缘薄膜，通过构图工艺对第二绝缘薄膜进行构图，形成覆盖硅基衬底10的第二绝缘层15图案，显示区域100和偏移区域200的第二绝缘层15分别形成多个第三过孔，虚设像素区域300的第二绝缘层15形成多个第四过孔，阴极环400的第二绝缘层15形成至少一个第五过孔，多个第三过孔分别暴露出每个显示单元的反射电极14，多个第四过孔分别暴露出每个虚设像素区域300的反射电极14，第五过孔暴露出阴极环400的反射电极14。随后，在第二绝缘层15上的第三过孔、第四过孔和第五过孔内形成多个第二导电柱16，第三过孔内的第二导电柱16与所在显示单元的反射电极14连接，第四过孔内的第二导电柱16与虚设像素区域300的反射电极14连接，第五过孔内的第二导电柱16与阴极环400的反射电极14连接，如图10所示。在示例性实施方式中，第二导电柱16可以由金属材料制成，通过填充处理形成第二导电柱16后，还可以进行抛光处理，通过抛光工艺对第二绝缘层15和第二导电柱16的表面进行腐蚀和摩擦，去除第二绝缘层15和第二导电柱16的部分厚度，使第二绝缘层15和第二导电柱16形成平齐的表面。在一些可能的实现方式中，第二导电柱 16可以采用金属钨(W)。
(5)在形成前述结构的硅基衬底10上沉积透明导电薄膜，通过构图工艺对透明导电薄膜进行构图，在显示区域100、偏移区域200、虚设像素区域300和阴极环400的第二绝缘层15上分别形成阳极层图案，阳极层包括设置在显示区域100、偏移区域200、虚设像素区域300和阴极环400的多个阳极31，阳极31通过第二导电柱16与反射电极14连接，如图11所示。本公开中，阳极31通过第二导电柱16与反射电极14连接，反射电极14通过第一导电柱13与驱动薄膜晶体管11的漏电极连接，这样像素驱动电路提供的电信号通过反射电极14传输到阳极31，反射电极14一方面形成像素驱动电路与阳极之间的导电通道，另一方面形成微腔结构，不仅有利于像素驱动电路对发光器件的控制，而且使显示基板的结构更紧凑，有利于硅基OLED显示装置的微型化。
(6)在形成前述结构的硅基衬底10上涂覆像素定义薄膜，通过掩膜、曝光、显影工艺，在显示区域100、偏移区域200、虚设像素区域300和阴极环400形成像素定义层(PDL)32图案，在每个显示单元，像素定义层32开设有像素开口，像素开口暴露出阳极31的表面。随后，在显示区域100、偏移区域200和虚设像素区域300依次形成有机发光层33和阴极34，在每个显示单元，有机发光层33与所在显示单元的阳极31连接，面状的阴极34与每个显示单元的有机发光层33连接；在阴极环400形成阴极34，阴极环400的阴极34通过像素开口与阳极31连接，如图12所示。在示例性实施方式中，阴极34为半透半反电极，与前述形成的反射电极14构成微腔结构。
前述制备过程中，第一绝缘薄膜和第二绝缘薄膜可以采用硅氧化物(SiOx)、硅氮化物(SiNx)或氮氧化硅(SiON)，可以是单层结构，或者可以是多层复合结构。第一金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)或钼(Mo)等，或者可以采用由金属组成的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)等，合金材料可以是单层结构，或者可以是多层复合结构，如Mo/Cu/Mo的复合结构。透明导电薄膜可以采用氧化铟锡(ITO)或氧化铟锌(IZO)，或ITO/Ag/ITO的复合结构，像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等。
(7)在形成前述结构的硅基衬底10上，在显示区域100、偏移区域200、虚设像素区域300和阴极环400形成封装层图案，封装层40为薄膜封装结构，如图13所示。
(8)在形成前述结构的硅基衬底10上，在显示区域100、偏移区域200、虚设像素区域300和阴极环400形成彩膜层50图案，显示区域100和偏移区域200的彩膜层50包括相互间隔设置或相互交叠设置的第一颜色单元53、第二颜色单元54和第三颜色单元55，虚设像素区域300和阴极环400的彩膜层50包括在封装层上从下至上依次叠层设置的第一颜色单元53和第二颜色单元54，如图14所示。在示例性实施方式中，第一颜色单元可以为绿色单元G，第二颜色单元可以为红色单元R，第三颜色单元可以为蓝色单元B。在一些可能的实现方式中，彩膜层50的制备过程包括：先形成蓝色单元B，然后形成红色单元R，然后形成绿色单元G。蓝色彩膜的粘附性较大，先形成蓝色单元B可以减小彩膜层50从阴极上剥离的可能性。由于红色单元R的粘附性较小，但流动性好，因而在形成红色单元R的过程中，可以减少蓝色单元B和红色单元R远离阴极一侧表面的气泡数量，从而可以提高蓝色单元B和红色单元R二者交叠位置处膜厚的均一性。由于绿色单元G的基体材料和红色单元R的基体材料大致相同，因而绿色单元G和红色单元R之间的粘附力较大，可以减小彩膜层50从阴极上剥离的可能性。在一些可能的实现方式中，彩膜层50可以包括其它颜色单元，例如白色或黄色等。
后续工艺中，采用密封工艺形成盖板60，盖板60与硅基衬底10之间通过密封胶固定。由于硅基衬底10、盖板60和密封胶一起形成封闭的空间，因而提供了阻隔水氧的保障，使硅基OLED显示基板的寿命大幅提升。随后，对形成的显示母板进行切割，形成单独的显示基板。
图15为本公开有机发光层一种结构的示意图。如图15所示，本公开有机发光层的结构包括在阳极与阴极之间依次叠设的第一发光子层331、第一电荷产生层332、第二发光子层333、第二电荷产生层334和第三发光子层335。第一发光子层331设置为出射第一颜色光，包括依次叠设的第一空穴传输层(HTL)3311、第一发光材料层(EML)3312和第一电子传输层(ETL)3313。第二发光子层333设置为出射第二颜色光，包括依次叠设的第二空穴 传输层3331、第二发光材料层3332和第二电子传输层3333。第三发光子层335设置为出射第三颜色光，包括依次叠设的第三空穴传输层3351、第三发光材料层3352和第三电子传输层3353。第一电荷产生层332设置在第一发光子层331与第二发光子层333之间，用于将两个发光子层串联起来，实现载流子的传递。第二电荷产生层334设置在第二发光子层333与第三发光子层335之间，用于将两个发光子层串联起来，实现载流子的传递。由于本公开有机发光层包括出射第一颜色光的第一发光材料层、出射第二颜色光的第二发光材料层和出射第三颜色光的第三发光材料层，因而有机发光层最终出射的光为混合光。例如，可以设置第一发光材料层是出射红光的红光材料层，第二发光材料层是出射绿光的绿光材料层，第三发光材料层是出射蓝光的蓝光材料层，因而有机发光层最终出射白光。
在示例性实施方式中，图15所示的有机发光层仅仅是一种示例结构，本公开对此不作限制。实际实施时，可以根据实际需要设计有机发光层的结构。例如，每个发光子层中，为了能够提高电子和空穴注入发光材料层的效率，还可以设置空穴注入层(HIL)和电子注入层(EIL)。又如，为了简化有机发光层的结构，可以取消第一电子传输层3313、第一电荷产生层332和第二空穴传输层3331，即第二发光材料层3332可以直接设置在第一发光材料层3312上。
在一些可能的实现方式中，有机发光层可以采用出射第一颜色光的有机发光层和出射第一颜色光的互补光的有机发光层，该两个有机发光层相对于硅基衬底依次堆叠，从而整体上发白光，本公开对此不作限制，只要可以实现发白光即可。
通过本公开显示基板的结构及其制备过程可以看出，通过设置偏移区域，使得当封装、贴片等工艺导致显示模组某一边缘的显示区域部分第一像素单元损坏时，可以调整实际显示区域的位置朝偏移区域移动，避开因封装贴片损坏的像素单元，以保证实际显示的像素点数与预先设计的像素点数一致。
本公开的制备工艺可以利用成熟的制备设备实现，对工艺改进较小，兼容性高，工艺流程简便，易于设备周期性维护，生产效率高，生产成本低， 良品率高，便于大规模量产，所制备的显示基板可以应用在虚拟现实设备或增强显示设备中，或应用在其它类型的显示装置中，具有良好的应用前景。
本公开所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，每个显示单元微腔结构的长度可以相同，或者可以不同。又如，在显示区域形成反射电极的工艺中，绑定区可以形成相应焊盘，本公开在此不做具体的限定。
本公开还提供了一种显示方法，如图16所示，该显示方法包括步骤S1至步骤S2。
其中，步骤S1包括：对显示区域的多个像素单元进行坏点检测。
在一种示例性实施例中，所述对显示区域的多个像素单元进行坏点检测，包括：
将显示区域的多个像素单元进行分组；
驱动多个分组依次发光；
在每个分组发光时，根据该分组中的像素单元是否发光确定该分组中是否包括坏点以及包括的坏点的数目。
步骤S2包括：当显示区域靠近一侧边缘的第一预设个数的像素单元中包括超过第二预设比例的坏点时，调整栅极驱动器输出的像素行或源极驱动器输出的像素列朝坏点所在侧的对侧移动。
在一种示例性实施例中，调整栅极驱动器输出的像素行或源极驱动器输出的像素列朝坏点所在侧的对侧移动，包括：
初始显示时，栅极驱动器和源极驱动器驱动第A行至第B行、第C列至第D列的像素单元进行显示；
当显示区域靠近左侧边缘的第C列至第(C+N)列像素单元中包括超过第二预设比例的坏点时，调整源极驱动器输出的像素列为第(C+N+1)列至第(D+N+1)列；
当显示区域靠近右侧边缘的第(D-N)列至第D列像素单元中包括超过 第二预设比例的坏点时，调整源极驱动器输出的像素列为第(C-N-1)列至第(D-N-1)列；
当显示区域靠近上侧边缘的第A行至第(A+M)行像素单元中包括超过第二预设比例的坏点时，调整栅极驱动器输出的像素行为第(A+M+1)行至第(B+M+1)行；
当显示区域靠近下侧边缘的第(B-M)行至第B行像素单元中包括超过第二预设比例的坏点时，调整栅极驱动器输出的像素行为第(A-M-1)行至第(B-M-1)行，其中，A、B、C、D、N和M均为大于或等于1的自然数，且A<B，C<D，N<C，M<A。
示例性的，A＝17，B＝1937，C＝17，D＝1097，左侧偏移区域和右侧偏移区域包含的像素列数均为16列，上侧偏移区域和下侧偏移区域包含的像素行数均为16行，第二预设比例为50％，当显示区域靠近左侧边缘的第17列至第20列像素单元中包括超过50％的坏点时，调整源极驱动器输出的像素列为第21列至第1101列；当显示区域靠近右侧边缘的第1094列至第1097列像素单元中包括超过50％的坏点时，调整源极驱动器输出的像素列为第13列至第1093列；当显示区域靠近上侧边缘的第17行至第20行像素单元中包括超过50％的坏点时，调整栅极驱动器输出的像素行为第21行至第1941行；当显示区域靠近下侧边缘的第1934行至第1937行像素单元中包括超过50％的坏点时，调整栅极驱动器输出的像素行为第13行至第1933行。
本实施例的显示方法，通过当显示区域靠近一侧边缘的第一预设个数的第一像素单元中包括超过第二预设比例的坏点时，调整栅极驱动器输出的像素行或源极驱动器输出的像素列朝坏点所在侧的对侧移动，使得当封装、贴片等工艺导致显示模组某一边的显示区部分像素单元损坏时，可以调整实际显示区域的位置，避开因封装贴片损坏的像素，以保证实际显示的像素点数与预先设计的像素点数一致。
本公开还提供了一种显示装置，包括前述的显示基板。显示装置可以为虚拟现实装置、增强现实装置或近眼显示装置，或者可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪，或任何其它具有显示功能的产品或部件。该显示装置还包括：栅极驱动器、源极驱动器和时序控制 器，其中：
栅极驱动器，通过行扫描线GL与显示基板连接，被配置为接收时序控制器输出的栅极控制信号GCS，产生扫描信号，并将该扫描信号通过扫描线GL传送给显示基板上的实际显示区域，实际显示区域根据显示基板上的第一像素单元的坏点的位置和数目进行调整；
源极驱动器，被配置为接收时序控制器输出的数据电压Vdata和源极控制信号SCS，产生相应的数据(data)电压信号并通过数据线DL输出给显示基板上的实际显示区域，实际显示区域根据显示基板上的像素单元的坏点的位置和数目进行调整；
时序控制器，被配置为接收外部输入的RGB(红绿蓝)数据和时序控制(Timing Control)信号；根据RGB数据、时序控制信号和要输出的像素列，生成数据电压Vdata和源极控制信号SCS并输出给源极驱动器，根据要输出的像素行产生栅极驱动信号GCS，并将该栅极驱动信号GCS输出给栅极驱动器。
在一种示例性实施例中，实际显示区域根据显示基板上的第一像素单元的坏点的位置和数目进行调整，包括：
初始显示时，栅极驱动器和源极驱动器驱动第A行至第B行、第C列至第D列的像素单元进行显示；
当显示区域靠近左侧边缘的第C列至第(C+N)列像素单元中包括超过第二预设比例的坏点时，栅极驱动器和源极驱动器驱动第A行至第B行、第(C+N+1)列至第(D+N+1)列的像素单元进行显示；
当显示区域靠近右侧边缘的第(D-N)列至第D列像素单元中包括超过第二预设比例的坏点时，栅极驱动器和源极驱动器驱动第A行至第B行、第(C-N-1)列至第(D-N-1)列的像素单元进行显示；
当显示区域靠近上侧边缘的第A行至第(A+M)行像素单元中包括超过第二预设比例的坏点时，栅极驱动器和源极驱动器驱动第(A+M+1)行至第(B+M+1)行、第C列至第D列的像素单元进行显示；
当显示区域靠近下侧边缘的第(B-M)行至第B行像素单元中包括超过 第二预设比例的坏点时，栅极驱动器和源极驱动器驱动第(A-M-1)行至第(B-M-1)行、第C列至第D列的像素单元进行显示，其中，A、B、C、D、N和M均为大于或等于1的自然数，且A<B，C<D，N<C，M<A。
示例性的，A＝17，B＝1937，C＝17，D＝1097，左侧偏移区域和右侧偏移区域包含的像素列数均为16列，上侧偏移区域和下侧偏移区域包含的像素行数均为16行，第二预设比例为50％，当显示区域靠近左侧边缘的第17列至第20列像素单元中包括超过50％的坏点时，源极驱动器输出的像素列为第21列至第1101列；当显示区域靠近右侧边缘的第1094列至第1097列像素单元中包括超过50％的坏点时，源极驱动器输出的像素列为第13列至第1093列；当显示区域靠近上侧边缘的第17行至第20行像素单元中包括超过50％的坏点时，栅极驱动器输出的像素行为第21行至第1941行；当显示区域靠近下侧边缘的第1934行至第1937行像素单元中包括超过50％的坏点时，栅极驱动器输出的像素行为第13行至第1933行。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (12)

  1. 一种显示基板，包括显示区域以及围绕显示区域的偏移区域，在垂直于所述显示基板所在平面的方向上，所述显示基板包括硅基衬底、设置在硅基衬底上的发光结构层、设置在所述发光结构层远离所述硅基衬底一侧的封装层，所述显示区域的硅基衬底集成有第一像素驱动电路，所述偏移区域的硅基衬底集成有第二像素驱动电路；
    所述第一像素驱动电路与所述显示区域的发光结构层连接，至少部分所述第一像素驱动电路被配置为：在正常显示时，为与所述第一像素驱动电路电连接的发光结构层提供驱动信号；
    所述第二像素驱动电路与所述偏移区域的发光结构层连接，至少部分所述第二像素驱动电路被配置为：在正常显示时，不为与所述第二像素驱动电路电连接的发光结构层提供驱动信号。
  2. 根据权利要求1所述的显示基板，其中，全部所述第一像素驱动电路均配置为：为与所述第一像素驱动电路电连接的发光结构层提供驱动信号。
  3. 根据权利要求1所述的显示基板，其中，所述偏移区域包括左侧偏移区域、右侧偏移区域和/或上侧偏移区域和下侧偏移区域，所述左侧偏移区域和右侧偏移区域包含的像素列数的差值不超过10行，所述上侧偏移区域和下侧偏移区域包含的像素行数的差值不超过10行。
  4. 根据权利要求3所述的显示基板，其中，所述左侧偏移区域和右侧偏移区域包含的像素列数相等，所述上侧偏移区域和下侧偏移区域包含的像素行数相等。
  5. 根据权利要求3所述的显示基板，其中，所述左侧偏移区域或右侧偏移区域的像素单元的列数与所述显示区域的像素单元的列数的比值大于或等于1％；所述上侧偏移区域或下侧偏移区域的像素单元的行数与显示区域的像素单元的行数的比值大于或等于1％。
  6. 根据权利要求1所述的显示基板，所述显示基板还包括设置在所述封 装层远离所述发光结构层一侧的彩膜层，所述显示区域和偏移区域的彩膜层分别包括呈阵列设置的第一颜色单元、第二颜色单元和第三颜色单元。
  7. 根据权利要求1所述的显示基板，还包括至少部分围绕偏移区域的虚设像素区域，在垂直于所述显示基板所在平面的方向上，所述虚设像素区域包括硅基衬底、设置在硅基衬底上的发光结构层、设置在所述发光结构层远离所述硅基衬底一侧的封装层。
  8. 一种显示装置，包括：如权利要求1至7任一项所述的显示基板，还包括：栅极驱动器、源极驱动器和时序控制器，其中：
    所述栅极驱动器，被配置为接收时序控制器输出的栅极控制信号，产生扫描信号并通过扫描线传送给显示基板上的实际显示区域，所述实际显示区域根据所述显示基板上的像素单元的坏点的位置和数目进行调整；
    所述源极驱动器，被配置为接收时序控制器输出的数据电压和源极控制信号，产生相应的数据电压信号并通过数据线输出给显示基板上的实际显示区域；
    所述时序控制器，被配置为接收外部输入的红绿蓝数据和时序控制信号；根据红绿蓝数据和时序控制信号，生成数据电压和源极控制信号并输出给源极驱动器，生成栅极驱动信号并输出给栅极驱动器。
  9. 根据权利要求8所述的显示装置，其中，所述实际显示区域根据所述显示基板上的像素单元的坏点的位置和数目进行调整，包括：
    初始显示时，所述栅极驱动器和源极驱动器驱动第A行至第B行、第C列至第D列的像素单元进行显示；
    当所述显示区域靠近左侧边缘的第C列至第(C+N)列像素单元中包括超过第二预设比例的坏点时，所述栅极驱动器和源极驱动器驱动第A行至第B行、第(C+N+1)列至第(D+N+1)列的像素单元进行显示；
    当所述显示区域靠近右侧边缘的第(D-N)列至第D列像素单元中包括超过第二预设比例的坏点时，所述栅极驱动器和源极驱动器驱动第A行至第B行、第(C-N-1)列至第(D-N-1)列的像素单元进行显示；
    当所述显示区域靠近上侧边缘的第A行至第(A+M)行像素单元中包括超过第二预设比例的坏点时，所述栅极驱动器和源极驱动器驱动第(A+M+1)行至第(B+M+1)行、第C列至第D列的像素单元进行显示；
    当所述显示区域靠近下侧边缘的第(B-M)行至第B行像素单元中包括超过第二预设比例的坏点时，所述栅极驱动器和源极驱动器驱动第(A-M-1)行至第(B-M-1)行、第C列至第D列的像素单元进行显示，其中，A、B、C、D、N和M均为大于或等于1的自然数，且A<B，C<D，N<C，M<A。
  10. 一种显示方法，包括：
    对显示区域的多个像素单元进行坏点检测；
    当显示区域靠近一侧边缘的第一预设个数的像素单元中包括超过第二预设比例的坏点时，调整栅极驱动器输出的像素行或源极驱动器输出的像素列朝坏点所在侧的对侧移动。
  11. 根据权利要求10所述的显示方法，其中，所述当显示区域靠近一侧边缘的第一预设个数的像素单元中包括超过第二预设比例的坏点时，调整栅极驱动器输出的像素行或源极驱动器输出的像素列朝坏点所在侧的对侧移动，包括：
    初始显示时，所述栅极驱动器和源极驱动器驱动第A行至第B行、第C列至第D列的像素单元进行显示；
    当所述显示区域靠近左侧边缘的第C列至第(C+N)列像素单元中包括超过第二预设比例的坏点时，调整所述源极驱动器输出的像素列为第(C+N+1)列至第(D+N+1)列；
    当所述显示区域靠近右侧边缘的第(D-N)列至第D列像素单元中包括超过第二预设比例的坏点时，调整所述源极驱动器输出的像素列为第(C-N-1)列至第(D-N-1)列；
    当所述显示区域靠近上侧边缘的第A行至第(A+M)行像素单元中包括超过第二预设比例的坏点时，调整所述栅极驱动器输出的像素行为第(A+M+1)行至第(B+M+1)行；
    当所述显示区域靠近下侧边缘的第(B-M)行至第B行像素单元中包括超过第二预设比例的坏点时，调整所述栅极驱动器输出的像素行为第(A-M-1)行至第(B-M-1)行，其中，A、B、C、D、N和M均为大于或等于1的自然数，且A<B，C<D，N<C，M<A。
  12. 根据权利要求10所述的显示方法，其中，所述对显示区域的多个像素单元进行坏点检测，包括：
    将所述显示区域的多个像素单元进行分组；
    驱动多个分组依次发光；
    在每个分组发光时，根据该分组中的像素单元是否发光确定该分组中是否包括坏点以及包括的坏点的数目。
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