WO2024000361A1 - 显示基板、显示面板及电子设备 - Google Patents

显示基板、显示面板及电子设备 Download PDF

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Publication number
WO2024000361A1
WO2024000361A1 PCT/CN2022/102693 CN2022102693W WO2024000361A1 WO 2024000361 A1 WO2024000361 A1 WO 2024000361A1 CN 2022102693 W CN2022102693 W CN 2022102693W WO 2024000361 A1 WO2024000361 A1 WO 2024000361A1
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WIPO (PCT)
Prior art keywords
area
display
peripheral
spacers
display area
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PCT/CN2022/102693
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English (en)
French (fr)
Inventor
程羽雕
嵇凤丽
卢彦伟
闫卓然
周宏军
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280001983.3A priority Critical patent/CN117643200A/zh
Priority to PCT/CN2022/102693 priority patent/WO2024000361A1/zh
Publication of WO2024000361A1 publication Critical patent/WO2024000361A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a display panel and an electronic device.
  • OLED Organic Light Emitting Diode
  • OLED Organic Light Emitting Diode
  • a display panel is provided.
  • the display panel includes a display area, a packaging area and a peripheral area.
  • the packaging area is located outside the display area, and the peripheral area is located between the display area and the packaging area.
  • the display substrate includes a base substrate, a pixel definition layer and a spacer layer.
  • the pixel defining layer is disposed on a side of the base substrate, and the spacer layer is disposed on a side of the pixel defining layer away from the base substrate.
  • the spacer layer includes a plurality of peripheral spacers arranged in the peripheral area; the vertical direction of the boundary of the display area adjacent to the plurality of peripheral spacers is the first direction, along which In the first direction, the distance from the peripheral spacer closest to the packaging area among the plurality of peripheral spacers to the packaging area is the first distance; among the plurality of peripheral spacers, the distance closest to the packaging area is the first distance; The distance from the outer peripheral spacer of the packaging area to the display area is the second distance.
  • the first distance is less than or equal to the second distance.
  • the size of the peripheral area in a direction perpendicular to the boundary of the display area adjacent to the peripheral area is the width of the peripheral area, and the ratio of the first distance to the width of the peripheral area is less than or equal to 0.2.
  • the peripheral spacer closest to the packaging area is the first peripheral spacer, and the peripheral spacer closest to the outer periphery of the display area The spacer is a second peripheral spacer.
  • the distance between the first peripheral spacer and the second peripheral spacer is greater than or equal to 80% of the width of the peripheral area.
  • the plurality of peripheral spacers are arranged in multiple rows along the first direction and arranged in multiple columns along the second direction; the second direction is perpendicular to the first direction.
  • the maximum distance between two adjacent peripheral spacers is L MAX
  • the minimum distance between two adjacent peripheral spacers is L MIN .
  • the first distance is less than or equal to L MAX ; the first distance is less than or equal to 260 ⁇ m.
  • the display substrate further includes a plurality of display spacers disposed in the display area.
  • the area ratio of the plurality of peripheral spacers in the peripheral area is a first ratio, and the area ratio of the multiple display spacers in the display area is a second ratio; the first The proportion is smaller than the second proportion.
  • the ratio of the first proportion to the second proportion is less than or equal to 65%.
  • the at least one peripheral spacer is the same shape and size as the at least one display spacer.
  • the plurality of display spacers and the plurality of peripheral spacers are arranged in multiple rows and columns, and at least one row of peripheral spacers and one row of display spacers are located on the same straight line, and the display The number of rows of spacers is greater than the number of rows of peripheral spacers.
  • the plurality of display spacers and the plurality of peripheral spacers are arranged in multiple rows and columns, and one row of peripheral spacers and one row of display spacers constitute a row of spacers, In the row of spacers, the distance between at least some adjacent peripheral spacers is equal to the distance between adjacent display spacers.
  • the display substrate further includes a first voltage signal line and an adapter part.
  • the first voltage signal line is provided on the base substrate and is configured to transmit a cathode signal to the display area.
  • the transfer part is disposed in the peripheral area, the transfer part is electrically connected to the first voltage signal line, and there is a first boundary between the transfer part close to the display area and the display area. interval.
  • the distance of the first interval is greater than the first distance
  • the distance of the first spacing is greater than or equal to 300 ⁇ m in a direction perpendicular to the boundary of the display area.
  • the orthographic projection of some of the plurality of peripheral spacers on the base substrate overlaps with the orthographic projection of the adapter portion on the base substrate;
  • peripheral spacers among the plurality of peripheral spacers are disposed within the first interval; and/or, there is a second boundary between the transition portion and the packaging area close to the packaging area. intervals, and some of the peripheral spacers among the plurality of peripheral spacers are disposed within the second interval.
  • the display substrate further includes a spacer block disposed on a side of the peripheral spacer close to the substrate substrate; the pixel definition layer is in the same layer as the spacer block. set up.
  • the transfer part includes a through hole
  • the display substrate further includes a filling part that fills the through hole, and the filling part is disposed in the same layer as the pixel defining layer.
  • the display substrate further includes a first electrode layer, and the first electrode layer includes the transfer portion and a plurality of anodes located in the display area.
  • the adapter part is a closed structure that is sleeved outside the display area.
  • the display substrate further includes a plurality of scanning signal lines.
  • the peripheral area includes a first area and a second area distributed on both sides of the display area along the extending direction of the plurality of scanning signal lines.
  • the display substrate further includes a scan drive circuit disposed in the first area and/or the second area, and the scan drive circuit is electrically connected to the plurality of scan signal lines.
  • the scan driving circuit is close to the boundary of the display area, closer to the display area than the transition portion is close to the boundary of the display area, and the The orthographic projection of the adapter portion on the base substrate does not overlap or partially overlaps the orthographic projection of the scan driving circuit on the base substrate.
  • the scan driving circuit includes a first driving circuit and a second driving circuit, one of the first driving circuit and the second driving circuit is configured to output a row scan signal, and the other is configured to output a row scan signal. Configured to output lighting control signals.
  • the first driving circuit is closer to the display area than the second driving circuit.
  • the adapter portion at least partially overlaps the second drive circuit and does not overlap the first drive circuit; or, the adapter portion overlaps the second driver circuit. Neither the first drive circuit nor the second drive circuit overlap.
  • the scan driving circuit further includes a third driving circuit configured to output a reset signal.
  • the first driving circuit, the third driving circuit and the second driving circuit are arranged in sequence.
  • the adapter portion at least partially overlaps the second drive circuit and the third drive circuit, but does not overlap the first drive circuit; or, the adapter portion at least partially overlaps the first drive circuit;
  • the adapter portion at least partially overlaps the second drive circuit and does not overlap the first drive circuit and the third drive circuit; or the adapter portion overlaps the first drive circuit and the third drive circuit. Neither the third driving circuit nor the second driving circuit overlap.
  • some of the plurality of peripheral spacers overlap the third driving circuit and the second driving circuit.
  • the display substrate further includes a plurality of data signal lines.
  • the peripheral area includes a third area and a fourth area distributed on both sides of the display area along the extension direction of the plurality of data signal lines; the display substrate also includes a third area located in the fourth area away from the display area. fan-out area on one side.
  • the display substrate further includes a time-division multiplexing circuit disposed in the fourth region, and the time-division multiplexing circuit is electrically connected to the plurality of data signal lines.
  • the time-division multiplexing circuit is close to the boundary of the display area and is closer to the display area than the transfer part is close to the boundary of the display area, and
  • the switching part and the time division multiplexing circuit do not overlap or partially overlap.
  • some of the peripheral spacers overlap the time division multiplexing circuit.
  • the display substrate further includes a gate metal layer and a source and drain electrode layer disposed on the base substrate.
  • the first voltage signal line includes a first wiring portion located on the gate metal layer, and a second wiring portion located on the source and drain electrode layer.
  • the first wiring portion is at least partially located in the packaging area, and the second wiring portion is located between the packaging area and the display area.
  • the display substrate further includes a first electrode layer, a luminescent layer and a second electrode layer.
  • the luminescent layer is disposed on one side of the first electrode layer, and the second electrode layer is disposed on the side of the first electrode layer.
  • the light-emitting layer is on a side away from the first electrode layer.
  • the first electrode layer includes a plurality of anodes disposed in the display area, and a transfer portion disposed in the peripheral area, the plurality of anodes and the transfer portion are insulated from each other; the second The electrode layer is electrically connected to the transfer part.
  • a display panel which includes a display substrate, an encapsulant, and a protective cover.
  • the display substrate is the display substrate described in the above embodiment
  • the encapsulating glue is disposed in the encapsulating area of the display substrate
  • the protective cover is disposed on the side of the encapsulating glue away from the base substrate.
  • the protective cover and the display substrate are encapsulated by the encapsulant, and the plurality of peripheral spacers of the display substrate are in the orthographic projection of the base substrate, and the protective cover is on the lining.
  • the orthographic projection of the base substrate overlaps.
  • the peripheral spacer and the encapsulant are flush or nearly flush at ends away from the base substrate.
  • an electronic device including the display panel according to any one of the above embodiments.
  • Figure 1 is a structural diagram of a display substrate according to some embodiments.
  • Figure 2 is a structural diagram of a display substrate in a display area according to some embodiments.
  • Figure 3 is a structural diagram of an OLED light-emitting device according to some embodiments.
  • Figure 4 is a circuit diagram of a 4T2C pixel driving circuit according to some embodiments.
  • Figure 5 is a circuit diagram of a display driving circuit provided according to some embodiments.
  • FIG. 6 is a circuit diagram of a GOA circuit provided in accordance with some embodiments.
  • Figure 7 is a stacked view of a display substrate according to some embodiments.
  • Figure 8 is a structural diagram of a first electrode layer according to some embodiments.
  • Figure 9 is a cross-sectional view of the adapter part at the position of the through hole according to some embodiments.
  • Figure 10 is an overlapping diagram of the second electrode layer and the first electrode layer according to some embodiments.
  • Figure 11 is a structural diagram of an adapter part and a first voltage signal line according to some embodiments.
  • Figure 12 is a structural diagram of a first voltage signal line according to some embodiments.
  • Figure 13 is a structural diagram showing spacers in a display area according to some embodiments.
  • Figure 14 is a front view of a display substrate according to some embodiments.
  • Figure 15 is a stacked view of a display panel according to some embodiments.
  • Figure 16 is a structural diagram of a display substrate in a fourth region according to some embodiments.
  • Figure 17 is a diagram showing the relationship between the first voltage signal line and the packaging area according to some embodiments.
  • Figure 18 is a distribution diagram of peripheral spacers according to some embodiments.
  • Figure 19 is a distribution diagram of peripheral spacers in the first direction according to some embodiments.
  • Figure 20 is a structural diagram of an adapter part according to some embodiments.
  • Figure 21 is a structural diagram of the adapter part in the first area in Figure 20;
  • Figure 22 is a structural diagram of the adapter part and the peripheral spacer according to some embodiments.
  • Figure 23 is the AA' view in Figure 22;
  • Figure 24 is a structural diagram of the first space in the first region of the display panel according to some embodiments.
  • Figure 25 is the BB' view in Figure 22;
  • Figure 26 is the CC' view in Figure 22;
  • Figure 27 is a structural diagram of the second interval in the first area of the display panel according to other embodiments.
  • Figure 28 is a structural diagram of the second interval in the fourth area of the display panel according to other embodiments.
  • Figure 29 is a structural diagram of a display panel in the display area and part of the first area according to some embodiments.
  • Figure 30 is a partial structural diagram of a display panel in a display area according to some embodiments.
  • Figure 31 is a structural diagram of a display panel in the display area and part of the first area according to some embodiments.
  • Figure 32 is a structural diagram of a display panel in the display area and part of the fourth area according to some embodiments.
  • Figure 33 is a schematic diagram of an electronic device according to some embodiments.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and includes the following combinations of A, B and C: A only, B only, C only, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally interpreted to mean “when” or “in response to” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrase “if it is determined" or “if [stated condition or event] is detected” is optionally interpreted to mean “when it is determined" or “in response to the determination" or “on detection of [stated condition or event]” or “in response to detection of [stated condition or event]”.
  • parallel includes absolutely parallel and approximately parallel, and the acceptable deviation range of approximately parallel may be, for example, a deviation within 5°;
  • perpendicular includes absolutely vertical and approximately vertical, and the acceptable deviation range of approximately vertical may also be, for example, Deviation within 5°.
  • equal includes absolute equality and approximate equality, wherein the difference between the two that may be equal within the acceptable deviation range of approximately equal is less than or equal to 5% of either one, for example.
  • Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • some embodiments of the present disclosure provide a display substrate 1, which includes a display area (Active Area, AA area for short) 2 and a non-display area 3 located on the periphery of the display area 2, wherein the display
  • the area 2 is an area of the display substrate 1 used to implement the display function.
  • the non-display area 3 is an area of the display substrate 1 where display cannot be performed, and is usually located on the outer periphery of the display area 2 .
  • the display substrate 1 includes a plurality of pixel units arranged in a display area 2, and the plurality of pixel units are arranged in an array to form a pixel array.
  • the pixel unit in the display substrate 1 may include OLED (Organic Light-Emitting Diode, organic light-emitting diode), QLED (Quantum Dot Light Emitting Diode, quantum dot light-emitting diode), Mini LED (sub-millimeter light-emitting diode) or Micro-LED ( Micro light-emitting diodes), etc.
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • QLED Quantum Dot Light Emitting Diode, quantum dot light-emitting diode
  • Mini LED sub-millimeter light-emitting diode
  • Micro-LED Micro light-emitting diodes
  • each OLED pixel unit 5 includes a plurality of OLED sub-pixels 4.
  • each OLED pixel unit 5 may include a plurality of OLED sub-pixels 4 capable of emitting different colors. ;
  • color display is achieved by controlling the light emission and color mixing of the OLED sub-pixels 4 of different colors in each OLED pixel unit 5.
  • the OLED pixel unit 5 includes an R sub-pixel capable of emitting red (Red) light, a G sub-pixel capable of emitting green (Green) light, and a B sub-pixel capable of emitting blue (Blue) light.
  • Red, green and blue are the three primary colors.
  • the display substrate 1 displays, by controlling the R sub-pixel, G sub-pixel and B sub-pixel to emit light in different degrees, the three colors can be mixed according to different proportions, thus achieving The display substrate 1 provides color display.
  • the OLED pixel unit 5 can also achieve full-color display through colorization technologies such as color transfer or color filters.
  • OLED sub-pixels 4 in the OLED pixel unit 5 There are also various pixel arrangements for the OLED sub-pixels 4 in the OLED pixel unit 5. For example, they can be RGB arrangement, GGRB arrangement, PenTile arrangement (referred to as P row), Delta arrangement (referred to as D row), diamond arrangement, etc.
  • P row PenTile arrangement
  • D row Delta arrangement
  • D row diamond arrangement
  • the type, number and size of OLED sub-pixels 4 in the OLED pixel unit 5 may also be different.
  • the embodiment of the present disclosure does not limit the pixel arrangement of the OLED sub-pixels 4 in the OLED pixel unit 5.
  • FIG. 2 is a structural diagram of a display substrate in a display area according to some embodiments.
  • multiple OLED sub-pixels 4 of the display substrate 1 in the display area 2 are arranged in multiple rows.
  • the multi-column arrangement includes a plurality of pixel rows 8 extending in the pixel row direction, and a plurality of pixel columns 11 extending in the pixel column direction.
  • the pixel row direction and the pixel column direction are perpendicular to each other.
  • Each pixel row 8 includes a plurality of OLED sub-pixels 4 arranged along the pixel row direction.
  • Each pixel column 11 includes a plurality of OLED sub-pixels arranged along the pixel column direction. 4.
  • a plurality of pixel rows 8 in the display area 2 are arranged side by side along the pixel column direction, and a plurality of pixel columns 11 in the display area 2 are arranged side by side along the pixel row direction, thereby forming a cross-arranged pixel array.
  • the pixel row direction is the horizontal direction, parallel to the direction of the X coordinate axis in Figure 2
  • the pixel column direction is the longitudinal direction, parallel to the direction of the Y coordinate axis in Figure 2.
  • each OLED sub-pixel 4 includes an OLED light-emitting device 10 and a pixel driving circuit 9 for driving the OLED light-emitting device 10 to emit light.
  • FIG 3 is a structural diagram of an OLED light-emitting device according to some embodiments.
  • the OLED light-emitting device 10 includes an anode (Anode) 14, an organic functional layer 13 and a cathode (Cathode) 12.
  • the anode 14 is opposite to the cathode 12.
  • the organic functional layer 13 is located between the anode 14 and the cathode 12 and includes an organic light-emitting layer (Emitting Material Layer, abbreviation EML); the organic light-emitting layers corresponding to the OLED light-emitting devices 10 of different colors are usually different.
  • EML Organic Light-emitting Layer
  • an electric field is generated by controlling the anode 14 and the cathode 12. Under the action of the electric field, the holes generated by the anode 14 and the electrons generated by the cathode 12 will move. When the two meet, energy excitation will be generated. ions, and then radiate and recombine to produce visible light to achieve self-luminous display.
  • the anode 14 can be made of a material with a high work function, and the cathode 12 can be made of a material with a low work function.
  • the organic functional layer 13 may also include a hole transport layer (Hole Transport Layer, abbreviation HTL), a hole injection layer (Hole Inject Layer, abbreviation HIL), an electron transport layer (Electron Transport Layer, abbreviation ETL) and an electron injection layer (Electron Inject Layer (abbreviation EIL) at least one in order to improve the luminous efficiency of the organic light-emitting layer (EML).
  • HTL hole transport layer
  • HIL Hole Inject Layer
  • ETL electron transport layer
  • EIL Electrode Inject Layer
  • Each OLED sub-pixel 4 also includes a pixel driving circuit 9 for driving the OLED light-emitting device 10 to emit light; the pixel driving circuit 9 is divided into passive driving (Passive-Matrix, abbreviated as PM) and active driving (PM) according to different driving methods. Active-Matrix, abbreviated AM).
  • PM passive driving
  • PM active driving
  • AM Active-Matrix
  • the display substrate 1 adopts active driving. Please continue to refer to Figure 2.
  • the display substrate 1 includes a plurality of scan signal lines (Scan Line) 6 and a plurality of data signals provided in the display area 2.
  • the pixel drive circuit 9 includes a thin film transistor (Thin Film Transistor, TFT for short).
  • the thin film transistor used in the embodiments of the present disclosure includes a source electrode, a gate electrode, and a drain electrode. Since the source electrode and the drain electrode are symmetrical in some cases, the source electrode and the drain electrode are interchangeable. of. For the convenience of description, this article will call one of the source electrode and the drain electrode the first electrode, the other of the source electrode and the drain electrode the second electrode, and the gate electrode the control electrode; that is, when the third electrode When one pole is the source, the second pole is the drain; when the first pole is the drain, the second pole is the source.
  • the display substrate 1 also includes a first voltage signal line, a second voltage signal line and an initialization voltage signal line, wherein the first voltage signal line is configured to output a VSS voltage signal, that is, a cathode signal, to the display area 2; the second voltage signal line It is configured to output the VDD voltage signal to the display area 2; the initialization voltage signal line is configured to output the initialization voltage signal to the display area 2.
  • the first voltage signal line is configured to output a VSS voltage signal, that is, a cathode signal, to the display area 2
  • the second voltage signal line It is configured to output the VDD voltage signal to the display area 2
  • the initialization voltage signal line is configured to output the initialization voltage signal to the display area 2.
  • multiple scanning signal lines 6 all extend along the pixel row direction, and multiple scanning signal lines 6 are arranged side by side in the pixel column direction; multiple data signal lines 7 all extend along the pixel column direction, and multiple The data signal lines 7 are arranged in parallel in the pixel row direction.
  • the plurality of scanning signal lines 6 and the plurality of data signal lines 7 are arranged crosswise.
  • the OLED sub-pixel 4 is located at the intersection of the scanning signal line 6 and the data signal line 7 .
  • the scanning signal lines 6 extend in the transverse direction and are arranged side by side in the longitudinal direction.
  • the extending direction of the data signal lines 7 is in the longitudinal direction, and multiple data signal lines 7 are arranged in the transverse direction. .
  • the pixel driving circuit 9 includes at least two thin film transistors, a switching transistor (Switching TFT) and a driving transistor (Driving TFT), and at least one storage capacitor.
  • the pixel driving circuit 9 can be represented by the number of thin film transistors and storage capacitors in the pixel driving circuit 9.
  • 2T1C includes 2 thin film transistors and 1 storage capacitor
  • 7T1C includes 7 thin film transistors and 1 storage capacitor.
  • Figure 4 is a circuit diagram of a 4T2C pixel driving circuit according to some embodiments.
  • the pixel driving circuit 9 includes a first thin film transistor T1, a second thin film transistor T2, a second thin film transistor T3, and a fourth thin film transistor T4.
  • the first capacitor C 1 and the second capacitor C 2 include a line scanning signal input terminal, a data signal input terminal, a lighting signal input terminal, a reset signal input terminal, a first voltage input terminal, a second voltage input terminal and an initialization voltage. input terminal.
  • the row scanning signal input terminal is connected to the scanning signal line 6 and is configured to input the row scanning signal SCAN;
  • the data signal input terminal is connected to the data signal line 7 and is configured to input the data voltage signal V Data ;
  • the luminescence signal input terminal is connected to the luminescence signal
  • the signal control circuit is connected and is configured to input the luminescence signal EM;
  • the reset signal input terminal is connected to the reset signal control circuit and is configured to input the reset signal RESET of the reset pixel driving circuit 9;
  • the first voltage input terminal is connected to the first voltage signal line , is configured to input the VSS voltage signal;
  • the second voltage input terminal is connected to the second voltage signal line, and is configured to input the VDD voltage signal;
  • the initialization voltage input terminal is connected to the initialization voltage signal line, and is configured to input the reset voltage signal V init .
  • the first thin film transistor T1 is a switching transistor, and its control electrode is connected to the row scanning signal input terminal.
  • the first electrode is connected to the data signal input terminal, and the second electrode is connected to the control electrode of the second thin film transistor T2.
  • the fourth thin film transistor T4 is a driving transistor, its control electrode is connected to the second electrode of the first thin film transistor T1, the first electrode is connected to the second thin film transistor T2, and the second electrode is connected to the anode 14 of the OLED light-emitting device 10; the OLED emits light.
  • Cathode 12 in device 10 is connected to a first voltage input.
  • One end of the first capacitor C 1 is connected to the control electrode of the second thin film transistor T2, and the other end is connected to the second electrode.
  • the control electrode of the second thin film transistor T2 is connected to the light-emitting signal input terminal, the first electrode is connected to the second voltage input terminal, and the second electrode is connected to the first electrode of the fourth thin film transistor T4.
  • One end of the second capacitor C2 is connected to the second voltage input terminal, and the other end is connected to the second pole of the fourth thin film transistor T4.
  • the control electrode of the third thin film transistor T3 is connected to the reset signal input terminal, the first electrode is connected to the initialization voltage input terminal, and the second electrode is connected to the second electrode of the fourth thin film transistor T4.
  • FIG. 5 is a circuit diagram of a display driving circuit provided according to some embodiments.
  • the display substrate 1 includes a display driving circuit that controls display.
  • the display driving circuit includes a scan driver circuit (Scan Driver IC) 15, a data driver Circuit (Data Driver IC) 17 and power circuit (Power IC) 16.
  • Scan Driver IC scan driver circuit
  • Data Driver IC data driver Circuit
  • Power IC power circuit
  • the scan driving circuit 15 is connected to the scanning signal line 6 in the display area 2 and is used to output the row scanning signal SCAN for controlling the switching transistor during the display driving stage.
  • the scan driving circuit 15 may be different for different pixel driving circuits 9 .
  • the scan driving circuit 15 is further configured to output the lighting control signal EM to the lighting signal input terminal in the pixel driving circuit 9 , and is configured to output a reset signal to the reset signal input terminal in the pixel driving circuit 9 RESET.
  • the data driving circuit 17 is connected to the data signal line 7 in the display area 2 and is used to provide the data voltage signal V data to the data signal input terminal of the pixel driving circuit 9 during the display driving stage.
  • the data driving circuit 17 usually adopts an integrated circuit chip bound to the display substrate 1 .
  • the power circuit 16 is used to convert the input voltage into working voltages of different sizes and output them.
  • the power circuit 16 is connected to the first voltage signal line 36 , the second voltage signal line and the initialization voltage signal line respectively, and is configured to supply the display area 2 Output VSS voltage signal, VDD voltage signal and initialization voltage signal V init .
  • the scan drive circuit 15 adopts GOA (Gate Driver on Array) design, that is, the scan drive circuit 15 is integrated on the display substrate; the scan drive circuit 15 integrated on the display substrate using GOA technology is also It is called GOA circuit.
  • GOA Gate Driver on Array
  • the GOA circuit is usually arranged outside the end of the scanning signal line 6 (pixel row 8), and is a multi-stage shift register unit (GOA unit) cascaded along the extension direction of the data signal line 7 (the arrangement direction of the pixel row 8).
  • GOA unit multi-stage shift register unit
  • the output signal of the first-level shift register unit is also output to the upper-level shift register unit (if any) as the reset signal of the upper-level shift register unit; it is also output to The next-level shift register unit (if any) serves as the input signal of the next-level shift register unit.
  • the input signal of the first-stage shift register unit is the frame start signal STV, and no reset signal is output.
  • the last level shift register unit is connected to the first level redundant shift register unit (Dummy GOA) to realize the reset of the last level shift register unit. It can be seen from this that the cascaded multi-stage shift register units interact with each other to generate shift pulse signals to realize progressive scanning of the pixel array.
  • FIG. 6 is a circuit diagram of a GOA circuit provided according to some embodiments.
  • the GOA circuit 18 generally includes a scanning signal control circuit (Gate GOA, abbreviated G-GOA) 183, an luminescence signal control circuit (EM GOA, abbreviated E -GOA) 181 and a reset signal control circuit (Reset GOA, abbreviated R-GOA) 182; among them, the scan signal control circuit 183 is configured to output the row scan signal SCAN during the display driving stage, and the pixel drive circuit 9 receives the row scan signal The control switching transistor is turned on during SCAN.
  • G-GOA scanning signal control circuit
  • E -GOA luminescence signal control circuit
  • Reset GOA reset signal control circuit
  • the light-emitting signal control circuit 181 is configured to output the light-emitting signal EM in the display driving stage, and the pixel driving circuit 9 controls light emission when receiving the light-emitting signal EM.
  • the reset signal control circuit 182 is configured to output the reset signal RESET during the display driving stage. When the pixel driving circuit 9 receives the reset signal RESET, it can implement an initialization reset to clear possible signal residues and ensure the display effect of the display substrate 1 .
  • the scanning signal control circuit 183 and the reset signal control circuit 182 in the GOA circuit 18 usually adopt an integrated design. That is to say, the GOA circuit 18 only includes the scanning signal control circuit 183 and the light-emitting signal control circuit 181.
  • the scanning signal control circuit 183 is used. It not only outputs the row scanning signal SCAN that controls the switching transistor, but also outputs the reset signal RESET to the pixel driving circuit 9 .
  • the reset signal control circuit 182 in the GOA circuit 18 can be set separately.
  • Figure 7 is a stacked view of a display substrate according to some embodiments.
  • the display substrate 1 includes a base substrate 19 and a barrier layer (Buffer) stacked on one side of the base substrate 19. 32.
  • Active layer 34 Active layer 34, first gate insulating layer (GI1) 20, gate metal layer (Gate) 33, second gate insulating layer (GI2) 21, interlayer insulating layer (Inter Layer Dielectric, abbreviation ILD) 22,
  • PDL Pixel Definition Layer
  • PS Photo Spacer
  • the base substrate 19 may be a rigid plate-shaped structure, such as a glass plate, quartz plate or acrylic plate.
  • the base substrate 19 includes a first surface and a second surface arranged oppositely. Taking the orientation shown in FIG. 7 as an example, the first surface and the second surface are opposite planes placed laterally, and in the longitudinal direction, the first surface is located at Above the second surface, that is to say, the first surface is the upper surface and the second surface is the lower surface.
  • the direction perpendicular to the first surface of the base substrate 19 is defined herein as the stacking direction, and the stacking direction is parallel to the direction of the Z coordinate axis in FIG. 7 .
  • this article will refer to the X coordinate axis, Y coordinate axis and Z coordinate axis marked in the accompanying drawings for structural description, but the X coordinate axis, Y coordinate axis and Z coordinate axis are not limited to The three axes of a Cartesian coordinate system, but can be interpreted in a broader sense.
  • the X coordinate axis, the Y coordinate axis, and the Z coordinate axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.
  • the barrier layer 32 is disposed on the first surface of the base substrate 19 and is an inorganic insulating film layer. It can be made of silicon-containing inorganic materials and can have a multi-layer or single-layer structure.
  • the silicon-containing inorganic materials can be silicon oxide SiO 2 or nitrogen. At least one of silicon nitride SiN X and silicon oxynitride SiON. Designed in this way, the material properties of the inorganic material are used to isolate the substrate substrate 19 and the structure on the substrate substrate 19, reduce or block the penetration of foreign substances, moisture, or outside air from the bottom of the substrate substrate 19, and can provide Flat surface.
  • the active layer 34 is disposed on the side of the barrier layer 32 away from the base substrate 19, and can be made of amorphous silicon (Amorphous Silicon, abbreviated ⁇ -Si, also known as amorphous silicon), polycrystalline silicon (Polycrystalline Silicon, abbreviated Poly-Si), It is made of materials such as low-temperature polycrystalline silicon (LTPS) or metal oxide (such as indium gallium zinc oxide, abbreviated IGZO).
  • LTPS low-temperature polycrystalline silicon
  • IGZO indium gallium zinc oxide
  • the first gate insulating layer 20 is disposed on a side of the active layer 34 away from the base substrate 19 .
  • a gate metal layer 33 is disposed on the side of the first gate insulating layer 20 away from the base substrate 19 .
  • the gate metal layer 33 includes a The gate electrode of the thin film transistor in the display area 2 and the scanning signal line 6 .
  • Active layer 34 includes a channel region corresponding to the gate electrode.
  • the second gate insulating layer 21 is disposed on the side of the gate metal layer 33 away from the base substrate 19
  • the interlayer insulating layer 22 is disposed on the side of the second gate insulating layer away from the base substrate 19 ;
  • the first source-drain metal layer 31 is provided on the side of the interlayer insulating layer 22 away from the base substrate 19;
  • the first source-drain metal layer 31 is provided on the side away from the base substrate 19 with a first flat layer 23 and a passivation layer 24, and the passivation layer 24 is far away from the base substrate 19.
  • a second source and drain metal layer 30 is provided on one side of the base substrate 19 .
  • the first source-drain metal layer 31 and the second source-drain metal layer 30 are metal layers at different heights, the source electrode and the drain electrode in the thin film transistor, the data signal line 7 in the display substrate, the first voltage signal line, the second voltage Signal lines such as signal lines and initialization voltage signal lines, and plates of storage capacitors can be selectively disposed on the first source-drain metal layer 31 or the second source-drain metal layer 30 .
  • the signal lines they can also be provided in both the first source-drain metal layer 31 and the second source-drain metal layer 30 .
  • signal lines such as data signal lines, first voltage signal lines, second voltage signal lines, and initializing voltage signal lines in the display substrate, as well as the plates of the storage capacitors, may be partially or entirely provided on the gate metal layer 33 .
  • the second source-drain metal layer 30 is provided with a second flat layer 25 on the side away from the base substrate 19.
  • the second flat layer 25 has a flat surface on the side away from the base substrate 19. This flat surface facilitates the structure above it. of production and shaping.
  • the pixel driving circuit 9 for driving the OLED light-emitting device 10 can be formed in the passivation layer 24, the second source-drain metal layer 30 and the second planar layer 25, so they are usually combined together and called a driving circuit layer.
  • the driving circuit layer is the collective name for the pixel driving circuits 9 of all OLED sub-pixels 4 in the display substrate 1.
  • the base substrate 19 and the driving circuit layer are usually combined together and are called a backplane (BP).
  • the first electrode layer 26 is disposed on a side of the second flat layer 25 away from the base substrate 19 .
  • the first electrode layer 26 includes a plurality of anodes 14 located in the display area 2 .
  • the anode 14 is connected to the driver circuit layer.
  • the pixel defining layer 27 is disposed on the side of the first electrode layer 26 away from the base substrate 19 and has a pixel opening.
  • the anode 14 in the first electrode layer 26 is exposed through the pixel opening.
  • the organic functional layer 13 is disposed in the pixel opening, and the second electrode layer 29 is located on the side of the organic light-emitting layer away from the first electrode layer 26 .
  • the organic functional layer 13 located in the pixel opening and the first electrode layer 26 and the second electrode layer 29 located on both sides of the organic functional layer 13 form an OLED light-emitting device 10 .
  • the spacer layer 28 is disposed on the side of the pixel definition layer 27 away from the base substrate 19 and includes a plurality of display spacers 281 located in the display area 2.
  • the display spacers 281 are columnar structures erected on the pixel definition layer 27. , this columnar structure is used to support the mask plate (MASK) used for evaporation.
  • MASK mask plate
  • the first gate insulating layer 20, the second gate insulating layer 21, the interlayer insulating layer 22 and the passivation layer 24 are all inorganic insulating film layers, which can be made of silicon-containing inorganic materials, and can be multi-layered. Or a single-layer structure, the silicon-containing inorganic material can be at least one of silicon oxide SiO 2 , silicon nitride SiN X , and silicon oxynitride SiON.
  • Figure 8 is a structural diagram of the first electrode layer according to some embodiments.
  • the first electrode layer 26 includes a plurality of anodes 14 located in the display area 2.
  • the plurality of anodes 14 are connected to the OLEDs in the display area 2.
  • Sub-pixel 4 has a one-to-one correspondence.
  • the first electrode layer 26 also includes a transfer portion 35 located in the non-display area 3 , and the transfer portion 35 is insulated from the plurality of anodes 14 in the display area 2 .
  • the adapter part 35 is provided with a plurality of through holes 351, and the through holes 351 are used for exhaust during the process stage.
  • the display substrate 1 further includes a filling portion 271 that fills the through hole 351 .
  • the filling portion 271 covers the edge of the through hole 351 to prevent the through hole 351 from being side-eroded by the chemical solution during the manufacturing process.
  • the filling portion 271 is designed in the same layer as the pixel defining layer 27 , that is, a part of the pixel defining layer 27 is used as the filling portion 271 to fill the through hole 351 .
  • Figure 10 is an overlapping diagram of the second electrode layer and the first electrode layer according to some embodiments.
  • the second electrode layer 29 covers the display area 2 and serves as the common electrode of the OLED sub-pixel 4 in the display area 2.
  • the portion of the second electrode layer 29 corresponding to the OLED sub-pixel 4 is the cathode 12 of the OLED light-emitting device 10 .
  • the second electrode layer 29 also extends outward from the display area 2, extends to the position of the adapter portion 35, and contacts the adapter portion 35 to achieve overlapping.
  • Figure 11 is a structural diagram of the adapter part and the first voltage signal line according to some embodiments.
  • the display substrate 1 includes the first voltage signal line 36, and the adapter part 35 is connected to the first voltage signal line 36.
  • the first voltage signal line 36 is configured to output a VSS voltage signal to the display area 2 .
  • the display substrate 1 can output the VSS voltage signal to the display area 2 through the first voltage signal line 36 , the adapter portion 35 and the second electrode layer 29 , that is, output the cathode signal to the cathode 12 of the OLED light-emitting device 10 .
  • the transfer part 35 used to transfer the VSS voltage signal to the second electrode layer 29 may be provided on the same layer as the first electrode layer 26 or on the same layer as other metal layers; for example, the transfer part 35 It can be set on the same layer as the source and drain metal layers.
  • Figure 12 is a structural diagram of a first voltage signal line according to some embodiments.
  • the first voltage signal line 36 includes a first wiring portion 361 and a second wiring portion 362.
  • the first wiring part 361 and the second wiring part 362 are respectively located on different layers. With this design, the wiring resistance is reduced through double-layer wiring, thereby achieving the technical effect of reducing the voltage drop of the first voltage signal line 36 .
  • the first voltage signal line 36 includes a first wiring portion 361 located on the first source-drain metal layer 31 and a second wiring portion 362 located on the gate metal layer 33 .
  • the resistance of the first source-drain metal layer 31 is generally 1/10 of the resistance of the gate metal layer 33. Therefore, when the first wiring portion 361 and the second wiring portion 362 are routed in parallel, the wiring resistance can be reduced, thereby reducing the voltage. technical effects of reduction.
  • Figure 13 is a structural diagram of a display spacer 281 in the display area according to some embodiments. As shown in Figure 13, the display spacer 281 in the display area 3 is located on one side of the pixel opening, that is, on the side of the OLED light-emitting device 10 A plurality of display spacers 281 are arranged aside and arranged in rows and columns along the pixel row direction and the pixel column direction.
  • the display panel 41 includes a display substrate 1 , an encapsulant 40 and a protective cover 39 , wherein the encapsulant 40 and the protective cover 39 Disposed on the display side of the display substrate 1, the display side is the side to which the display direction of the display substrate points.
  • the encapsulant 40 and the protective cover 39 are disposed on the second electrode layer 29 away from the substrate. one side of the base substrate 19 .
  • the protective cover 39 is a transparent rigid plate, such as a glass plate, a quartz plate or a plastic plate, and is used to encapsulate and protect the display substrate 1 .
  • the sealant 40 is disposed between the protective cover 39 and the display substrate 1 for connecting the protective cover 39 and the display substrate 1 .
  • the protective cover 39 is sealed with the display substrate 1 through the packaging glue 40 .
  • the non-display area 3 of the display substrate 1 includes a packaging area 37 and a peripheral area 38.
  • the packaging area 37 is an area for disposing the packaging glue 40.
  • the display substrate 1 and the protective cover are connected through the packaging glue 40 in the packaging area 37. 39, thereby realizing packaging with the protective cover 39.
  • the encapsulation area 37 is designed as a closed annular area nested around the periphery of the display area 2, and the encapsulation adhesive 40 provided in the encapsulation area 37 is also closed. Cyclic colloid.
  • the area between the display area 2 and the packaging area 37 is the peripheral area 38
  • the peripheral area 38 is also a closed annular area nested around the periphery of the display area 2 .
  • the peripheral area 38 can be divided into different areas according to different relative positions to the display area 2 .
  • the boundary line outline of the display substrate 1 and the display area 2 can be square, circular, elliptical or other regular or irregular shapes.
  • the packaging area 37 and the peripheral area 38 are in the same shape as the display substrate 1 and the display area. 2 border lines to match the shape.
  • the boundary outline of the display substrate 1 is a first rectangle
  • the boundary outline of the display area 2 is a second rectangle
  • the first rectangle is nested outside the second rectangle
  • the first rectangle is in the The long sides of the rectangle and the long sides of the rectangle in the second rectangle are parallel to each other.
  • Both the peripheral area 38 and the packaging area 37 are rectangular frames with a certain width.
  • the long sides of the rectangle in the first rectangle and the long side of the rectangle in the second rectangle are parallel to the pixel row direction, that is, parallel to the extension direction of the scanning signal line 6 .
  • the short sides of the rectangle in the first rectangle and the short sides of the rectangle in the second rectangle are both parallel to the pixel column direction, that is, parallel to the extension direction of the data signal line 7 .
  • the peripheral area 38 of the display substrate 1 includes a first area 381 and a second area 382 located on both sides of the display area 2.
  • the peripheral area 38 of the backplane includes a first area 381 and a second area 382 located on both sides of the display area 2.
  • the extending direction of the scanning signal line 6 is parallel to the pixel row direction
  • the extending direction of the data signal line 7 is parallel to the pixel column direction. That is to say, the first area 381 and the second area 382 are parts of the peripheral area 38 that are located on both sides of the display area 2 along the extension direction of the scanning signal line 6
  • the third area 383 and the fourth area 384 are the peripheral area 38 Parts located on both sides of the display area 2 along the extension direction of the data signal line 7 .
  • the first area 381 and the second area 382 are the parts of the peripheral area 38 located on the left and right sides of the display area 2.
  • the first area 381 is located on the left side of the display area 2, and the second area 382 is located on the left side of the display area 2.
  • the right side of area 2, that is, the first area 381 is the left frame area, and the second area 382 is the right frame area.
  • the pixel column direction, the extension direction of the data signal line 7, the direction of the short side of the rectangle in the first rectangle and the direction of the short side of the rectangle in the second rectangle are all longitudinal directions, parallel to the Y coordinate axis in Figure 14, and the third area 383 and the fourth area 384 are the parts of the peripheral area 38 located on the upper and lower sides of the display area 2, the third area 383 is located above the display area 2, and the fourth area 384 is located below the display area 2, that is, the third area 383 is The upper frame area, and the fourth area 384 is the lower frame area.
  • the display substrate 1 is usually provided with a scan drive circuit 15 in the first area 381 and/or the second area 382.
  • the scan drive circuit 15 is a GOA circuit 18
  • the GOA circuit 18 can be provided on one side of the display area 2, That is, it is provided only in the first area 381 or the second area 382.
  • the GOA circuit 18 has a scanning signal control circuit 183, a light-emitting signal control circuit 181, and a reset signal control circuit 182, the scanning signal control circuit 183, the reset signal control circuit 182, and the light-emitting signal control circuit 181 in the GOA circuit 18 are connected to
  • the direction in which the scanning signal lines 6 are located is arranged in the first area 381 or the second area 382, and the arrangement order can be in any order.
  • the scanning signal control circuit 183 , the reset signal control circuit 182 and the light emitting signal control circuit 181 are arranged in sequence in a direction away from the display area 2 , where the scanning signal control circuit 183 is located close to the boundary of the display area 2 .
  • the scanning signal control circuit 183 and the light-emitting signal control circuit 181 are arranged in the first area 381 or the second area 382, and the arrangement order may be: Any order.
  • the scanning signal control circuit 183 and the light emitting signal control circuit 181 are arranged in sequence in a direction away from the display area 2 , where the scanning signal control circuit 183 is disposed close to the boundary of the display area 2 .
  • the GOA circuit 18 may be provided on both sides of the display area 2 , that is, in both the first area 381 and the second area 382 .
  • the first GOA circuit 18 that drives part of the pixel rows 8 is provided in the first region 381
  • the second GOA circuit 18 that drives the remaining part of the pixel rows 8 is provided in the second region 382 .
  • the first GOA circuit 18 is used to drive even pixel rows 8
  • the second GOA circuit 18 is used to drive odd pixel rows 8 .
  • the arrangement of the first GOA circuit 18 and the second GOA circuit 18 may refer to the above arrangement of the single-side arrangement, and will not be described again here.
  • different functional parts of the GOA circuit 184 are respectively provided in the first area 381 and the second area 382.
  • the GOA circuit 18 includes a scanning signal control circuit 183 and a lighting signal control circuit 181
  • the scanning signal One of the control circuit 183 and the light-emitting signal control circuit 181 may be provided in the first area 381, and the other may be provided in the second area 382.
  • the display substrate 1 is provided with a fan-out area 43 in the fourth area 384, and the data signal line 7 in the display area 2 extends to the fourth area 384, that is, in the lower frame area, and after passing through the fan-out area 43, the extended trace is connected to the data driving circuit 17 at a position outside the packaging area 37.
  • the data driving circuit 17 usually uses an integrated circuit chip bound to the display substrate 1. However, the number of pins that the data driving circuit 17 can connect to the data signal line 7 is limited. Therefore, in some embodiments, the display substrate 1 is included in the fourth region. 384 is provided with a time-division multiplexing circuit 42, and the display substrate 1 has a fan-out area 43 on a side of the time-division multiplexing circuit 42 away from the display panel 41.
  • the time-division multiplexing circuit 42 includes multiple multiplexers (Multiplexers, MUX for short).
  • the multiplexers usually have one input terminal and at least two output terminals.
  • the input terminals of the multiplexer and the intermediate wiring 431 The intermediate wiring 431 extends after passing through the fan-out area 43 and is connected to the data driving circuit 17 at a position outside the packaging area 37 .
  • At least two output terminals of the multiplexer are respectively connected to the data signal lines 7; the multiplexer implements time-sharing transmission of the data power signal output by one output terminal in the data drive circuit 17 to the plurality of data signal lines 7.
  • the data signal line 7 can also be led out at the top of the display area 2, and the fan-out area 43 and the time-division multiplexing circuit 42 are correspondingly provided in the third area 383, that is, in the upper frame area.
  • Figure 17 is a diagram showing the relationship between the first voltage signal line and the packaging area according to some embodiments.
  • the display substrate 1 includes a first voltage signal line configured to provide a VSS signal to the display area 2 in the peripheral area 38. 36.
  • the first voltage signal line 36 is extended and arranged around the peripheral edge of the display area 2 in the first area 381, the third area 383 and the second area 382, and both ends of the first voltage signal line 36 extend to the fourth area 384,
  • the power supply circuit 16 is connected to both ends of the first voltage signal line 36 .
  • the first voltage signal line 36 is arranged away from the display area 2 relative to the GOA circuit 18 , and is located relative to the display area 2 from the GOA circuit 18 . outside.
  • the first voltage signal line 36 includes a first wiring part 361 and a second wiring part 362.
  • the first wiring part 361 and the second wiring part 362 are respectively located on different layers and are directed to the substrate. 19, the first wiring part 361 is located between the packaging area 37 and the display area 2, and the second wiring part 142 is at least partially located in the packaging area 37.
  • the protective cover 39 is sealed and encapsulated with the display substrate 1 through the encapsulating glue 40 provided in the encapsulation area 37 .
  • the packaging method of the display panel 41 is Frit (glass glue) packaging, that is, through the glass glue (Frit Seal) provided in the packaging area 37, the protection cover 39 and the display substrate 1 are realized after the glass glue is melted and solidified. Sealed packaging, Frit packaging method has the advantages of no need for grooves, good water and oxygen barrier ability, and relatively simple process.
  • the encapsulant 40 is usually a colloid structure extending along a closed contour.
  • the encapsulant 40 may be a square frame colloid.
  • a certain gap is maintained between the display substrate 1 and the protective cover 39 in the display direction of the display panel 41.
  • the gap supported by the encapsulant 40 is located between the display substrate 1 and the protective cover 39. The gap between them is the packaging gap.
  • the size of the packaging gap is related to the thickness of the packaging glue 40 .
  • a thicker packaging glue 40 can support a larger packaging gap, while a thinner packaging glue 40 can support a smaller packaging gap.
  • This article defines the space surrounded by the sealant 40 between the display substrate 1 and the protective cover 39 as the sealant space.
  • the sealant space is filled with air, such as nitrogen N 2 , to form an air film with a thickness.
  • the thickness of the air film is equal to The package gaps at the locations are equal.
  • the protective cover 39 generally has certain rigidity requirements, due to the influence of its own material and structure and other factors, in the natural state or under the action of external forces, for example, the protective cover 39 will also be affected by external forces, such as touch.
  • the protective cover 39 is easily deformed toward the display substrate 1 due to pressing, accidental extrusion, etc. under the action of external force, and the thickness of the air film between the deformed protective cover 39 and the display substrate 1 becomes smaller or even zero.
  • Newton's ring is a thin film interference phenomenon.
  • Thin film interference refers to the phenomenon in which a beam of light wave is irradiated on a thin film. Due to the different refractive index, the light wave will be reflected by the upper and lower interfaces of the thin film respectively, and new light waves will be formed due to mutual interference.
  • Newton's rings belong to the equal-thickness interference phenomenon in thin film interference.
  • the interference pattern is a number of concentric rings with alternating light and dark circles. For example, if the convex surface of a convex lens with a large radius of curvature is in contact with a flat glass, under sunlight or when illuminated with white light, you can see that the contact point in the interference pattern is a dark spot, surrounded by some alternating light and dark colored rings; When illuminated with monochromatic light, the interference pattern appears as some monochromatic rings of alternating light and dark.
  • the rings (colored rings or monochromatic rings) in Newton's rings are interference rings formed by the interference of light rays. The order of the interference rings relative to the center of the circle is the pole order of the interference ring. For colored rings, The colored rings of different polarities in the interference pattern have different colors.
  • the display panel 41 in the related art it is usually used under daylight and white light, so the Newton rings are colorful Newton rings with colors.
  • an embodiment of the present disclosure provides a display substrate. Please refer to FIG. 18 .
  • the display substrate 1 includes a plurality of peripheral spacers 44 provided in the peripheral area 38 .
  • the peripheral spacers in the plurality of peripheral spacers 44 The object 44 is used to support the protective cover 39 when the display substrate 1 and the protective cover 39 are packaged. That is to say, the orthographic projection of the plurality of peripheral spacers 44 on the base substrate overlaps with the orthographic projection of the protective cover 39 on the base substrate.
  • the direction perpendicular to the boundary of the display area 2 adjacent to the plurality of peripheral spacers 44 is defined as the first direction.
  • the distance from the peripheral spacer closest to the packaging area 37 among the plurality of peripheral spacers 44 to the packaging area 37 is the first distance.
  • the distance from the peripheral spacer closest to the packaging area 37 among the plurality of peripheral spacers 44 to the display area 2 is the second distance.
  • the first distance is less than or equal to the second distance.
  • the ratio of the first distance to the width of the peripheral area 38 is 0 to 0.5, for example, 0 to 0.2, 0.2 to 0.4, 0.4 to 0.5, for example, 0, 0.05, 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45 and 0.5.
  • the peripheral spacer 44 closest to the packaging area 37 is arranged closer to the boundary of the packaging area 37 . It should be noted that when the ratio of the first distance to the width of the peripheral area 38 is 0, that is, when the first distance is 0, the outer peripheral spacer 44 closest to the packaging area 37 is in contact with and adjacent to the peripheral area 38 s position.
  • the display substrate 1 provided by the embodiment of the present disclosure adopts the above design.
  • the display substrate 1 can improve the supporting effect of the protective cover 39 when it is packaged with the protective cover 39, and avoid the protective cover 39
  • the deformation occurs at the arrangement position of the outer peripheral spacer 44 , thereby improving or even eliminating the effect of Newton rings (rainbow pattern defects), thereby improving the display quality of the display panel 41 having the display substrate 1 .
  • the outer peripheral spacer 44 closest to the packaging area 37 is arranged closer to the boundary of the packaging area 37 . Designed in this way, even when a Newton ring occurs, the position where the Newton ring occurs will be close to the packaging area 37 and away from the display area 2, thereby reducing or even eliminating the impact of the Newton ring on the display effect in the display area 2, and improving the efficiency of the display area.
  • the display quality of the display panel 41 of the display substrate 1 is arranged closer to the boundary of the packaging area 37 .
  • the peripheral spacer 44 is a columnar structure erected on the display substrate 1 .
  • the columnar structure may be a regular or irregular three-dimensional shape such as a cylinder, a tapered column, or a square column.
  • the peripheral spacers 44 can be arranged in the same layer as the display spacers 281, or can be formed by patterning a separate organic layer.
  • “standing on the display substrate 1 ” here means that the extension direction of the peripheral spacers 44 is perpendicular or substantially perpendicular to the base substrate 19 in the display substrate 1 , that is, the direction of lamination defined above is (the direction of the Z coordinate axis in Figure 7) is parallel or basically parallel.
  • the end of the peripheral spacers 44 away from the display substrate 1 and the end of the sealant 40 away from the display substrate 1 should be flush or nearly flush.
  • the distance between the end of the peripheral spacer 44 away from the display substrate 1 and the base substrate 19 is the first height, and the encapsulation glue 40 is far away from the end of the display substrate 1
  • the distance between the end and the base substrate 19 is the second height; the end of the peripheral spacer 44 away from the display substrate 1 is flush with the end of the encapsulant 40 away from the display substrate 1 , which means that the first height and the second height are equal and nearly flush. This means that although the first height and the second height are not equal, the difference between them is small. This small difference prevents the protective cover 39 from generating colored Newton rings even when the protective cover 39 is deformed.
  • the second electrode layer 29 is disposed at the end of the peripheral spacer 44 away from the display substrate 1 .
  • the outer peripheral spacer 44 supports the second electrode layer 29 in contact with the protective cover 39 .
  • the second electrode layer 29 is disposed at the end of the peripheral spacer 44 away from the display substrate 1 . Since the thickness of the electrode layer 29 is small, it can be ignored when compared with the height of the peripheral spacer 44 . However, in a scenario where the thickness of the second electrode layer 29 needs to be considered, the above limitation on the height of the peripheral spacers 44 should be understood as the limitation on the sum of the thickness of the peripheral spacers 44 and the second electrode layer 29 .
  • the direction perpendicular to the boundary of the display area 2 adjacent to the plurality of peripheral spacers 44 is defined in this article as the first direction.
  • the direction in which the boundaries of adjacent display areas 2 of the cushion 44 are parallel is the second direction.
  • the first direction and the second direction at the same position in the peripheral area 38 are perpendicular to each other. At different positions in the peripheral area 38, the first direction may be different; when the first direction is different, the second direction is also different.
  • the first direction is a direction that extends laterally and is parallel to the direction of the X coordinate axis in FIG. 14 ;
  • the second direction is the direction of longitudinal extension, parallel to the direction of the X coordinate axis in Figure 14.
  • the first direction is the direction of longitudinal extension, parallel to the direction of the Y coordinate axis in Figure 14; the second direction is the direction of transverse extension, parallel to the direction of the Y coordinate axis in Figure 14 The direction of the X coordinate axis.
  • the boundary shape of the display area 2 is a circle
  • the boundary shape of the peripheral area 38 is a circular ring shape concentric with the display area 2
  • the first direction at different positions of the peripheral area 38 is the radial direction of the circular display area 2.
  • direction, the second direction at different positions in the peripheral area 38 is a direction perpendicular to the first direction, that is, the direction of the tangent of the circular display area 2 at the corresponding position.
  • a plurality of peripheral spacers 44 in the peripheral region 38 are disposed at a plurality of different positions along a first direction, and at a plurality of different positions along a second direction;
  • peripheral spacers 44 are arranged in the peripheral area 38, the larger the arranged area is, the larger the support area for the protective cover 39 is, and the better the support effect is, and the better the support effect for the Newton ring.
  • the improvement effect will be greater.
  • the plurality of peripheral spacers 44 are arranged in multiple rows and columns along the third direction and the fourth direction, and the third direction is perpendicular to the fourth direction; wherein, the third direction may be parallel to the first direction, and in the first direction When the direction is parallel to the third direction, the fourth direction is also parallel to the second direction; according to the above description, it can be seen that the first direction may be different at different positions of the peripheral area 38; therefore, multiple peripheral spacers 44 are arranged in rows The row direction and column direction of the arrangement may also be different at different locations in the peripheral area 38 .
  • the third direction and the fourth direction may be parallel to the first direction and the second direction at a certain location, that is, in the peripheral area 38, a plurality of peripheral spacers
  • the row direction of the mats 44 arranged in rows and columns is consistent with the column direction.
  • the row and column directions of the rows and columns of the plurality of peripheral spacers 44 in the peripheral area 38 are the same as the row and column directions of the plurality of display spacers 281 in the display area 2 .
  • the pixel row direction and the pixel column direction are parallel.
  • multiple peripheral spacers 44 arranged in multiple rows and multiple columns can be staggered between adjacent rows and/or adjacent columns. By staggering the outer spacers 44 , the outer circumference can be effectively improved.
  • the spacer 44 supports the protective cover 39 .
  • a plurality of display spacers 281 and a plurality of peripheral spacers 44 are arranged in multiple rows and columns along the same row direction and column direction, and at least one row of peripheral spacers 44 and one row of display spacers are arranged in multiple rows and columns.
  • the spacers 281 are located on the same straight line, and the number of rows of the spacers 281 is greater than the number of rows of the peripheral spacers 44 .
  • At least one row of peripheral spacers 44 and one row of display spacers 281 are located on the same straight line, and the number of columns of display spacers 281 is greater than the number of columns of peripheral spacers 44 .
  • multiple display spacers 281 and multiple peripheral spacers 44 are arranged in multiple rows and multiple columns, and one row of peripheral spacers 44 and one row of display spacers 281 constitute a spacer. Things go well. In the row of spacers, the distance between at least some adjacent peripheral spacers 44 is equal to the distance between adjacent display spacers 281 .
  • a row of peripheral spacers 44 and a row of display spacers 281 form a spacer row.
  • the spacer row at least part of the distance between adjacent peripheral spacers 44 is equal to the distance between adjacent display spacers 281 .
  • this article defines that along the first direction, among the plurality of peripheral spacers 44, the peripheral spacer 44 closest to the packaging area 37 is the first peripheral spacer 441, which is closest to the display area.
  • the peripheral spacer 44 of 2 is the second peripheral spacer 442 .
  • the distance between the first peripheral spacer 441 and the boundary of the packaging area 37 along the first direction is the first distance, and the first distance is represented by L 1 .
  • the distance between the first peripheral spacer 441 and the boundary of the display area 2 along the first direction is the second distance, and the second distance is represented by L 2 .
  • the distance between the second peripheral spacer 442 and the first peripheral spacer 441 along the first direction is the third distance, and the third distance is represented by L 3 ; it is defined that the second peripheral spacer 442 is in the first direction.
  • the distance upward to the boundary of the display area 2 is the fourth distance, and the fourth distance is represented by L 4 .
  • the largest spacing between two adjacent peripheral spacers 44 is the maximum spacing, and the maximum spacing is represented by L MAX ; the smallest spacing is the minimum spacing, and the minimum spacing is represented by L MIN .
  • the distance between the two outer boundaries of the peripheral area 38 is the width of the peripheral area 38 , and L is used to represent the width of the peripheral area 38 .
  • the distribution of the plurality of peripheral spacers 44 in the peripheral area 38 can be expressed. area, the position relative to the boundary of the display area 2 and the position relative to the boundary of the packaging area 37 .
  • the ratio of the first distance L 1 to the width L of the peripheral region 38 is 0 to 0.2. That is, among the plurality of peripheral spacers 44 , the one closest to the packaging region 37 along the first direction
  • the distance from the first peripheral spacer 441 of the boundary to the boundary of the packaging area 37 is 0% to 20% of the width of the peripheral area 38; for example, 0 ⁇ 0.08, 0.08 ⁇ 0.16, 0.16 ⁇ 0.2, for example, 0, 0.02 , 0.04, 0.06, 0.08, 0.1, 0.12, 0.14, 0.16, 0.18, 0.2.
  • the first peripheral spacer 441 closest to the boundary of the packaging area 37 is located closer to the packaging area 37 ; such a design can be closer to the packaging area 37
  • the position of the packaging area 37 effectively supports the protective cover 39 , thereby improving or even eliminating the Newton ring effect on the one hand, thereby improving the display quality of the display panel 41 having the display substrate 1 .
  • the first peripheral spacer 441 is located at the boundary of the packaging area 37 close to the peripheral area 38 , or at a position close to the packaging area 37 .
  • Such a design can effectively support the protective cover 39 at the boundary of the packaging area 37 close to the peripheral area 38 or close to the packaging area 37 , thereby avoiding the need for space between multiple peripheral spacers 44 and the packaging area 37 Newton's rings occur to improve the display quality of the display panel 41 having the display substrate 1 .
  • the first distance L 1 is approximately equal to the fourth distance L 4 . It should be noted that here it is approximately equal. It should be understood that the ratio of the first distance L 1 to the fourth distance L 4 is around 1, For example, the ratio of the first distance L 1 to the fourth distance L 4 is between 0.9 and 1.1.
  • the first distance L 1 is approximately equal to the fourth distance L 4 , and refers to the boundary between the second peripheral spacer 442 and the display area 2 that is closest to the boundary of the display area 2 along the first direction among the plurality of peripheral spacers 44 .
  • the distance is equivalent to the distance between the first peripheral spacer 441 closest to the boundary of the packaging area 37 and the boundary of the packaging area 37 .
  • the plurality of peripheral spacers 44 of the peripheral area 38 are also arranged closer to the boundary of the display area 2 on the side closer to the display area 2 .
  • Such a design can effectively support the protective cover 39 in the area close to the boundary of the display area 2, thereby improving or even eliminating the effect of Newton's rings, thereby improving the display quality of the display panel 41 with the display substrate 1 .
  • the second peripheral spacer 442 may be located at the boundary of the display area 2 , or at a position close to the boundary of the display area 2 .
  • the peripheral spacers 44 are extended and arranged through the display spacers 281 in the display area 2, and the distribution area of the peripheral spacers 44 extends from the boundary position of the display area 2 along the first direction toward the packaging area 37, and extends to the vicinity of the boundary line of the packaging area 37 . Therefore, the fourth distance L 4 may be smaller than the first distance L 1 .
  • the plurality of peripheral spacers 44 of the peripheral area 38 are designed to be close to the boundary of the display area 2 on the side close to the display area 2 , and are designed to be close to the boundary of the packaging area 37 on the side close to the packaging area 37 .
  • both ends of the distribution area of the plurality of peripheral spacers 44 in the peripheral area 38 are respectively at or close to the boundaries.
  • the distance between the first peripheral spacer 441 and the second peripheral spacer 442 is a third distance L 3
  • the third distance L 3 is greater than or equal to the width L of the peripheral area 38 80%.
  • the maximum distance between two adjacent peripheral spacers 44 should not exceed 20 times the minimum distance, that is, the distance between the peripheral spacers 44
  • the arrangement should not be too sparse.
  • the first distance L 1 is less than or equal to L MAX ; that is, along the first direction, the distance from the first peripheral spacer 441 to the boundary of the packaging area 37 is smaller than that of two adjacent peripheral spacers.
  • the maximum spacing L MAX in 44 such a design can, on the one hand, limit the distance between the first peripheral spacer 441 and the boundary of the packaging area 37 to be small, and on the other hand, it can limit the arrangement of the peripheral spacers 44 in the first direction. Yu sparse.
  • the first distance L 1 is less than or equal to 260 ⁇ m.
  • the first distance L 1 in the first area 381 is 188 ⁇ m
  • the first distance L 1 in the second area 382 is 153 ⁇ m
  • the first distance L 1 in the third area 383 is 164 ⁇ m.
  • the first distance L 1 is 248 ⁇ m in the fourth area 384 . It can be seen that in some products, the first distance L 1 is 150 ⁇ m ⁇ 260 ⁇ m.
  • peripheral spacers 44 arranged in the peripheral area 38, the larger the supporting area for the protective cover 39, the better the supporting effect for the protective cover 39, and the better the Newton's performance.
  • the improvement effect of the ring will be greater.
  • too many peripheral spacers 44 will increase the contact area with the mask plate (MASK) during evaporation, thereby exacerbating the problem of sheet sticking.
  • the contact area between the outer peripheral spacers 44 and the protective cover 39 should also be limited.
  • the area ratio may be used to represent the distribution of the peripheral spacers 44 and the display spacers 281 .
  • the area proportion of the plurality of peripheral spacers 44 in the peripheral area 38 is defined as the first proportion
  • the area proportion of the plurality of display spacers 281 in the display area 2 is defined as the second proportion; wherein, the first proportion Less than the second proportion.
  • the area ratio of the peripheral spacers 44 is reduced, that is, the contact area between the peripheral spacers 44 and the protective cover 39 in the peripheral area 38 is reduced, thereby The problem of adhesion between the peripheral spacer 44 and the mask plate during evaporation is reduced.
  • the ratio of the first proportion to the second proportion is less than or equal to 65%, for example, it may be 60%.
  • the second proportion that is, the area proportion of the plurality of display spacers 281 in the display area 2, is generally less than 10%.
  • the second proportion is usually related to the pixel arrangement. For example, for products with GGRB arrangement, the second proportion is about 7.6%.
  • the peripheral spacer 44 and the display spacer 281 have the same shape and size, and the single area of the peripheral spacer 44 is the same as the single area of the display spacer 281; in this case , the relationship between the first proportion and the second proportion is the relationship between the number of peripheral spacers 44 and the number of display spacers 281 in the unit area.
  • the ratio of the first proportion to the second proportion is less than or equal to 65%
  • the number of peripheral spacers 44 per unit area is less than or equal to 65% of the number of display spacers 281 .
  • the border of the adapter portion 35 close to the display area is relatively close to the border of the display area, because the adapter portion 35 is a part of the first electrode layer 26 and is a large piece of metal or a reflective film layer; Therefore, when the display area emits light for display, the adapter portion 35 will reflect the light emitted from the display area, thus affecting the display quality.
  • the distance between the inner boundary of the adapter portion 35 and the display area 2 is controlled so as to improve the problem of the adapter portion 35 reflecting the light emitted from the display area 2, thereby avoiding the problem. Since the adapter portion 35 reflects light, the display quality is affected.
  • first interval 352 between the border of the adapter 35 and the border of the display area 2. Based on the first direction defined above, the first interval is defined along the first direction.
  • the width of 352 is the first spacing, and the first spacing is represented by S 1 .
  • the first interval S 1 is greater than the first distance L 1 .
  • the first spacing S 1 should be above 300 ⁇ m.
  • the ability of the adapter 35 to reflect the light emitted from the display area 2 can be significantly improved. Therefore, it is possible to avoid affecting the display quality due to reflection of light from the adapter portion 35 .
  • the first spacing S 1 should satisfy the above-mentioned spacing conditions at different positions around the display area 2 .
  • the adapter portion 35 is a closed structure that is sleeved on the outside of the display area 2 , and the first spacing S 1 is in the first area 381 , the second area 382 , the third area 383 and the fourth area 384 of the peripheral area 38 Both are 345 ⁇ m.
  • the arrangement of the first spacer 352 can expose the structure at the corresponding position of the display substrate 1.
  • This article defines the structure exposed through the first spacer as the first exposed structure.
  • Some of the peripheral spacers 44 among the plurality of peripheral spacers 44 are disposed above the adapter portion 35; and some of the plurality of peripheral spacers 44 are disposed on the first exposed structure at first intervals. above.
  • the orthographic projection of some of the peripheral spacers 44 on the base substrate 19 overlaps with the orthographic projection of the adapter portion 35 on the base substrate 19; and, the plurality of outer peripheral spacers
  • the orthographic projection of part of the peripheral spacers 44 on the base substrate 19 overlaps with the orthographic projection of the first exposed structure on the base substrate 19 .
  • Figure 22 is a structural diagram of the adapter part and the peripheral spacers according to some embodiments
  • Figure 23 is the AA' view in Figure 22; as shown in Figures 22 and 23, part of the periphery of the multiple peripheral spacers 44
  • the spacer 44 is disposed above the first exposed structure 46 at the first interval 352 .
  • the spacer pad 45 may be disposed on the same layer as the pixel definition layer 27 .
  • the GOA circuit 18 is provided in the first area 381 and/or the second area 382 of the peripheral area 38 .
  • the GOA circuit 18 in the orthographic projection to the base substrate 19 , the GOA circuit 18 is closer to the boundary of the display area 2 and closer to the display area 2 than the adapter 35 The boundary is closer to the display area 2, and the transition portion 35 and the GOA circuit 18 do not overlap or partially overlap.
  • the first space exposes part or all of the GOA circuit 18 , and some of the plurality of peripheral spacers 44 are disposed above the exposed GOA circuit 18 .
  • the GOA circuit exposed through the first gap is the first exposed structure 46 .
  • the scan driving circuit 15 includes a first driving circuit and a second driving circuit, one of the first driving circuit and the second driving circuit is configured to output a row scan signal, and the other is configured to output a light emitting signal. Control signal; the first driving circuit is closer to the display area 2 than the second driving circuit.
  • the adapter portion 35 at least partially overlaps with the second drive circuit and does not overlap with the first drive circuit; or, the adapter portion 35 overlaps with the first drive circuit and the second drive circuit. None overlap.
  • the adapter portion 35 completely overlaps with the second driving circuit and does not overlap with the first driving circuit.
  • the scan driving circuit 15 further includes a third driving circuit configured to output a reset signal.
  • the first driving circuit, the third driving circuit and the second driving circuit are arranged in sequence.
  • the adapter portion 35 at least partially overlaps with the second drive circuit and the third drive circuit, but does not overlap with the first drive circuit; or, the adapter portion 35 overlaps with the second drive circuit It at least partially overlaps and does not overlap with the first driving circuit and the third driving circuit; or, the adapter portion 35 does not overlap with the first driving circuit, the third driving circuit and the second driving circuit.
  • the adapter portion 35 completely overlaps with the second driving circuit and the third driving circuit, but does not overlap with the first driving circuit.
  • the display panel includes a first sub-initialization signal line 47 located in the first area 381.
  • the first sub-initialization signal line 47 is part of the initialization voltage signal line and is close to the display in the first area 381.
  • the position of the boundary line of area 2 extends along the boundary of adjacent display area 2; that is, it extends along the second direction.
  • the first driving circuit 48 includes a plurality of control signal lines 481 and a plurality of GOA units 482.
  • the plurality of control signal lines 481 are far away from the display area 2 relative to the plurality of GOA units 482.
  • the plurality of control signal lines 481 all extend along the second direction. lines, and are arranged side by side along the second direction.
  • Multiple GOA units 482 are arranged along the second direction and connected to the control signal line 481 .
  • the adapter portion 35 does not overlap with the first driving circuit 48 , which means that it does not overlap with the plurality of control signal lines 481 and the plurality of GOA units 482 , so that the plurality of control signal lines 481 and the plurality of GOA units 482 are exposed through the first intervals 352 .
  • the display substrate 1 includes the time-division multiplexing circuit 42 .
  • the time-division multiplexing circuit 42 is close to the boundary of the display area 2 , compared to the transition portion 35 The boundary close to the display area 2 is closer to the display area 2 , and the switching part 35 and the time division multiplexing circuit 42 do not overlap or partially overlap.
  • Part or all of the time division multiplexing circuit 42 is exposed through the first interval 352, and the exposed part here is the first exposed structure 46.
  • Some of the plurality of peripheral spacers 44 are disposed above the first exposed structure 46 . That is, in the orthographic projection onto the base substrate 19 , some of the peripheral spacers 44 among the plurality of peripheral spacers 44 overlap the time-division multiplexing circuit 42 .
  • the display substrate 1 includes the first voltage signal line 36 ; in the orthographic projection to the base substrate 19 , the first voltage signal line 36 is close to the boundary of the display area 2 , compared to the transition portion 35 The boundary close to the display area 2 is closer to the display area 2 , and the adapter portion 35 and the first voltage signal line 36 do not overlap or partially overlap. Part or all of the first voltage signal line 36 is exposed through the first gap 352 , and the exposed part here is the first exposed structure 46 . Some of the plurality of peripheral spacers 44 are disposed above the first exposed structure 46 .
  • peripheral spacers 44 among the plurality of peripheral spacers 44 are disposed above the adapter portion 35 .
  • the outer peripheral spacer 44 is also provided in the adapter part 35 at a position with the through hole 351 and at a position without the through hole 35,
  • the peripheral spacer 44 is provided at the position where the adapter part 35 has the through hole 351 , wherein the display substrate 1 is provided with the adapter part 35 on the second flat layer 25 side, and the adapter part 35 It has a through hole 351, and the through hole 351 is filled by the filling part 271; the filling part 271 is provided with an outer peripheral spacer 44 on the side away from the adapter part 35, and the outer peripheral spacer 44 supports the second electrode layer 29, and the second electrode layer 29 overlaps the adapter portion 35 at the position on the outer peripheral spacer 44 side.
  • the peripheral spacer 44 is provided at a position where the adapter portion 35 is not provided with a through hole.
  • the display substrate 1 is provided with an adapter portion 35 on the side of the second flat layer 25 .
  • the adapter portion 35 A spacer block 45 is provided on one side, and a peripheral spacer 44 is provided on the side of the spacer block 45 away from the adapter portion 35.
  • the outer peripheral spacer 44 supports the second electrode layer 29, and the second electrode layer 29 overlaps the adapter portion 35 at the position on the outer peripheral spacer 44 side.
  • the end of the adapter portion 35 away from the display area 2 can be extended to the location of the packaging area 37, or to a location close to the packaging area 37.
  • the adapter portion 35 is close to the boundary of the packaging area 37 and the package.
  • the second spacing S 2 is generally smaller than the first spacing S 1 .
  • the arrangement of the second spacer 353 can expose the structure at the corresponding position of the display substrate 1 , and the structure exposed through the second spacer 353 is defined as the second exposed structure.
  • Some of the plurality of peripheral spacers 44 may be disposed above the second exposed structure at the second interval 353 .
  • the solution of the outer peripheral spacer 44 being disposed above the second exposed structure at the second interval please refer to the above solution of the outer peripheral spacer 44 being disposed above the first exposed structure, which will not be described again here.
  • the outer peripheral spacer 44 does not need to be provided above the second exposed structure.
  • FIG. 27 is a structural diagram of the second interval in the first area of the display panel according to other embodiments.
  • the second gap 353 In the first area 381, the second exposed structure exposed through the second gap 353 is the first voltage signal line 36.
  • the first voltage signal line 36 is connected to the adjacent display area 2 in the first area 381.
  • the boundary extends in a parallel direction, that is, along the second direction.
  • Some of the peripheral spacers 44 among the plurality of peripheral spacers 44 are disposed above the first voltage signal lines 36 at the second intervals 353 and extend along the extension direction of the second voltage signal lines 36 .
  • FIG. 28 is a structural diagram of the second gap in the fourth region of the display panel according to other embodiments. As shown in FIG. 28 , there is a second gap 353 between the border of the adapter portion 35 and the packaging region 37 . , in the fourth area 384, the second exposed structure exposed through the second spacer 353 may be an intermediate trace in the fan-out area, and no peripheral spacer is provided on the second exposed structure.
  • Figure 29 is a structural diagram of a display panel in the display area and part of the first area according to some embodiments.
  • the display panel adopts a GGRB arrangement in the display area 2, and in each OLED pixel unit , both include one R sub-pixel, one B sub-pixel and two G sub-pixels, and the two G sub-pixels are arranged along the extension direction of the scanning signal line, one R sub-pixel, one B sub-pixel and two G sub-pixels Arrange along the extension direction of the data signal lines.
  • the extension direction of the scanning signal line is the horizontal direction, parallel to the direction of the X coordinate axis in Figure 29, and the extension direction of the data signal line is the longitudinal direction, parallel to the direction of the Y coordinate axis in Figure 28 parallel. That is, in an OLED pixel unit shown in FIG. 28 , two G sub-pixels are arranged in the horizontal direction, and one R sub-pixel, one B sub-pixel and two G sub-pixels are arranged in the longitudinal direction.
  • the first electrode layer 26 includes a plurality of anodes 14 located in the display area 2 and a transition portion 35 located in the first area 381 .
  • the first electrode layer 26 includes one R anode 141, one B anode 142 and two G anodes 143 in each OLED pixel unit.
  • two G anodes 143 are arranged in the transverse direction
  • one B anode 142, one R anode 141 and two G anodes 143 are arranged in the longitudinal direction.
  • the first electrode layer 26 also includes a first sub-initialization signal line 47 located in the first area.
  • the first sub-initialization signal line 47 is part of the initialization voltage signal line. It is located near the boundary line of the display area 2 in the first area 381, along The boundaries of adjacent display areas 2 extend, that is, in the longitudinal direction.
  • the display area 2 includes multiple pairs of display spacers 281 , two of the pair of display spacers 281 are arranged laterally, and each display spacer 281 is a rectangular structure extending in the transverse direction. That is to say, the extending direction of the spacer 281 is perpendicular to the extending direction of the first sub-initialization signal line.
  • the area between an adjacent R sub-pixel and a B sub-pixel, between an adjacent B sub-pixel and two G sub-pixels, and between adjacent A pair of display spacers 281 is provided between two adjacent G sub-pixels and R sub-pixels.
  • the two display spacers 281 correspond to the two G sub-pixels respectively.
  • the display spacers 281 in the display area 2 may be placed at an angle relative to the scanning signal lines and the data signal lines. For example, as shown in FIG. 30 , the display spacers 281 in the display area 2 are placed at an angle relative to the sub-pixels The sides are parallel.
  • the peripheral spacers 44 in the first area 381 adopt the same shape and size as the display spacers 281 , and the plurality of display spacers 281 and the plurality of peripheral spacers 44 are arranged in the same row direction and reverse column direction. There are multiple rows and multiple columns, and at least one row of peripheral spacers 44 and one row of display spacers 281 are located on the same straight line. In addition, the number of rows of display spacers is greater than the number of rows of peripheral spacers, so that the first proportion is smaller than the second proportion, wherein the area proportion of the plurality of peripheral spacers 44 in the peripheral area 38 It is the first ratio, and the area ratio of the plurality of display spacers 281 in the display area 2 is the second ratio.
  • the single area of the outer peripheral spacer 44 is the same as the single area of the display spacer 281; in this case, the first proportion is the same as the second proportion.
  • the relationship between the proportions is the relationship between the number of peripheral spacers 44 and the number of display spacers 281 per unit area.
  • FIG. 29 there are two dotted square borders with equal areas, one located in the display area 2 and one located in the first area 381 .
  • the dotted square frame located in the display area 2 is surrounded by 6 pairs of display spacers 281
  • the dotted square frame located in the first area 381 is surrounded by 4 pairs of peripheral spacers 44 .
  • the relationship between the first proportion and the second proportion is not limited to this, as long as the plurality of peripheral spacers and the plurality of display spacers can be relatively uniform.
  • FIG. 31 there are three dotted square borders with equal areas, one is located in the display area 2 and two are located in the first area 381 .
  • the dotted square frame located in the display area 2 is surrounded by 6 pairs of display spacers 281, and the two dotted square frames located in the first area 381 are surrounded by 5 pairs of peripheral spacers 44 and 3 pairs of peripheral spacers 44 respectively, and
  • the dotted square frame surrounded by three pairs of peripheral spacers 44 is farther away from the display area 2 than the dotted square frame surrounded by five pairs of peripheral spacers 44 . That is to say, in some embodiments, the farther away from the display area 2 , the smaller the area ratio of the peripheral spacers 44 is.
  • Figure 32 is a structural diagram of a display panel in the display area and the fourth area according to some embodiments.
  • the first electrode layer 26 includes a plurality of anodes located in the display area 2, and anodes located in the fourth area 384. Transition part 35.
  • the display panel includes a plurality of display spacers 281 located in the display area 2 and a plurality of peripheral spacers 44 located in the fourth area 384 .
  • the arrangement of the plurality of peripheral spacers 44 in the fourth area 384 may refer to the first area 381 and will not be described again here. It can also be seen from FIG. 28 and FIG. 29 that the number of columns between the plurality of peripheral spacers 44 and the plurality of display spacers 281 is the same and aligned.
  • the number of rows of the plurality of peripheral spacers 44 is smaller than the number of rows of the plurality of display spacers 281 .
  • the present disclosure also provides an electronic device 100 having the display panel in the above embodiment.
  • the electronic device 100 is capable of displaying images (including static images or dynamic images, where the dynamic images may be videos).
  • Functional products for example, the electronic device 100 may be any of: a monitor, a mobile phone, a notebook computer, a tablet computer, a personal wearable device, a billboard, a digital photo frame, an e-reader, and the like.
  • the above-mentioned electronic device 100 has the same structure and beneficial technical effects as the display panel 41 provided in some of the above embodiments, and will not be described again here.

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Abstract

一种显示基板、显示面板及电子设备，显示基板包括显示区、封装区与周边区，封装区位于显示区的外侧，周边区位于显示区与封装区之间。显示基板包括衬底基板、像素界定层与隔垫物层。像素界定层设置在衬底基板一侧，隔垫物层设置在像素界定层远离衬底基板一侧。其中，隔垫物层包括设置在周边区的多个外周隔垫物；与多个外周隔垫物相邻的显示区的边界垂直的方向为第一方向，沿第一方向，多个外周隔垫物中最靠近封装区的外周隔垫物，到封装区的距离为第一距离；多个外周隔垫物中最靠近封装区的外周隔垫物，到显示区的距离为第二距离；其中，第一距离小于或等于第二距离。

Description

显示基板、显示面板及电子设备 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板、显示面板及电子设备。
背景技术
OLED(Organic Light Emitting Diode，有机发光二极管)因具有高亮度、全视角、响应速度快以及可柔性显示等优点，已在显示领域得到广泛应用。
发明内容
一方面，提供一种显示面板。所述显示面板包括显示区、封装区与周边区，所述封装区位于所述显示区的外侧，所述周边区位于所述显示区与所述封装区之间。
所述显示基板包括衬底基板、像素界定层与隔垫物层。
所述像素界定层设置在所述衬底基板一侧，所述隔垫物层设置在所述像素界定层远离所述衬底基板一侧。
其中，所述隔垫物层包括设置在所述周边区的多个外周隔垫物；与所述多个外周隔垫物相邻的所述显示区的边界垂直的方向为第一方向，沿所述第一方向，所述多个外周隔垫物中最靠近所述封装区的外周隔垫物，到所述封装区的距离为第一距离；所述多个外周隔垫物中最靠近所述封装区的外周隔垫物，到所述显示区的距离为第二距离。
所述第一距离小于或等于所述第二距离。
在一些实施例中，所述周边区在垂直于和周边区相邻的显示区的边界的方向的尺寸为所述周边区的宽度，所述第一距离与所述周边区的宽度比值小于或等于0.2。
在一些实施例中，沿所述第一方向，所述多个外周隔垫物中，最靠近所述封装区的外周隔垫物为第一外周隔垫物，最靠近所述显示区的外周隔垫物为第二外周隔垫物。
所述第一外周隔垫物与所述第二外周隔垫物之间的距离，大于或等于所述周边区的宽度的80％。
在一些实施例中，所述多个外周隔垫物沿第一方向的排列成多行，且沿第二方向的排列成多列；所述第二方向和所述第一方向相垂直。
在一些实施例中，沿所述第一方向，相邻两个外周隔垫物之间的最大间距为L MAX，相邻两个外周隔垫物之间的最小间距为L MIN。
其中，L MAX≤20×L MIN。
在一些实施例中，所述第一距离小于或等于L MAX；所述第一距离小于或等于260μm。
在一些实施例中，所述显示基板还包括设置在所述显示区的多个显示隔垫物。
所述多个外周隔垫物在所述周边区的面积占比为第一占比，所述多个显示隔垫物在所述显示区的面积占比为第二占比；所述第一占比小于所述第二占比。
在一些实施例中，所述第一占比与所述第二占比的比值小于或等于65％。
在一些实施例中，至少一个外周隔垫物与至少一个显示隔垫物形状与尺寸相同。
在一些实施例中，所述多个显示隔垫物与所述多个外周隔垫物均排列成多行多列，至少一行外周隔垫物与一行显示隔垫物位于同一条直线上，显示隔垫物的行的数目多于外周隔垫物的行的数目。
在一些实施例中，所述多个显示隔垫物与所述多个外周隔垫物均排列成多行多列，一行外周隔垫物与一行显示隔垫物构成了一个隔垫物行，在所述隔垫物行中，至少部分相邻的外周隔垫物之间的距离与相邻的显示隔垫物之间的距离相等。
在一些实施例中，所述显示基板还包括第一电压信号线与转接部。
所述第一电压信号线设置于所述衬底基板，被配置为向所述显示区传输阴极信号。
所述转接部设置于所述周边区，所述转接部与所述第一电压信号线电连接，所述转接部靠近所述显示区的边界与所述显示区之间具有第一间隔。
其中，沿垂直于所述显示区的边界的方向，所述第一间隔的距离大于所述第一距离。
在一些实施例中，沿垂直于所述显示区的边界的方向，所述第一间隔的距离大于或等于300μm。
在一些实施例中，所述多个外周隔垫物中的部分外周隔垫物在所述衬底基板的正投影，与所述转接部在所述衬底基板的正投影交叠；以及
所述多个外周隔垫物中的部分外周隔垫物设置于所述第一间隔内；和/或，所述转接部靠近所述封装区的边界与所述封装区之间具有第二间隔，所述多个外周隔垫物中的部分外周隔垫物设置于所述第二间隔内。
在一些实施例中，所述显示基板还包括设置于所述外周隔垫物靠近所述 衬底基板一侧的隔垫物垫块；所述像素界定层与所述隔垫物垫块同层设置。
在一些实施例中，所述转接部包括贯通孔，所述显示基板还包括填充所述贯通孔的填充部，所述填充部与所述像素界定层同层设置。
在一些实施例中，所述显示基板还包括第一电极层，所述第一电极层包括所述转接部以及位于所述显示区的多个阳极。
在一些实施例中，所述转接部为套设于所述显示区外侧的闭合结构。
在一些实施例中，所述显示基板还包括多根扫描信号线。
所述周边区包括沿所述多根扫描信号线的延伸方向分布于所述显示区两侧的第一区域和第二区域。
所述显示基板还包括设置于所述第一区域和/或所述第二区域的扫描驱动电路，所述扫描驱动电路与所述多根扫描信号线电连接。
在向所述衬底基板的正投影中，所述扫描驱动电路靠近所述显示区的边界，相较于所述转接部靠近所述显示区的边界更靠近所述显示区，且所述转接部在所述衬底基板的正投影与所述扫描驱动电路在所述衬底基板的正投影不交叠或部分交叠。
在一些实施例中，所述扫描驱动电路包括第一驱动电路和第二驱动电路，所述第一驱动电路和所述第二驱动电路中的一方被配置为输出行扫描信号，另一方为被配置为输出发光控制信号。
所述第一驱动电路相对于所述第二驱动电路靠近所述显示区。
在向所述衬底基板的正投影中，所述转接部与所述第二驱动电路至少部分交叠，与所述第一驱动电路不交叠；或，所述转接部与所述第一驱动电路和所述第二驱动电路均不交叠。
在一些实施例中，所述扫描驱动电路还包括第三驱动电路，所述第三驱动电路被配置为输出复位信号。
沿远离所述显示区的方向，所述第一驱动电路、所述第三驱动电路和所述第二驱动电路依次布置。
在向所述衬底基板的正投影中，所述转接部与所述第二驱动电路和所述第三驱动电路至少部分交叠，与所述第一驱动电路不交叠；或，所述转接部与所述第二驱动电路至少部分交叠，与所述第一驱动电路和所述第三驱动电路不交叠；或，所述转接部与所述第一驱动电路、所述第三驱动电路和所述第二驱动电路均不交叠。
在一些实施例中，在所述衬底基板的正投影中，所述多个外周隔垫物中的部分外周隔垫物与所述第三驱动电路和所述第二驱动电路交叠。
在一些实施例中，所述显示基板还包括多根数据信号线。
所述周边区包括沿所述多条数据信号线的延伸方向分布于所述显示区两侧的第三区域和第四区域；所述显示基板还包括位于所述第四区域远离所述显示区的一侧的扇出区。
所述显示基板还包括设置于所述第四区域的分时复用电路，所述分时复用电路与所述多根数据信号线电连接。
在向所述衬底基板的正投影中，所述分时复用电路靠近所述显示区的边界，相较于所述转接部靠近所述显示区的边界更靠近所述显示区，且所述转接部与所述分时复用电路不交叠或部分交叠。
在向所述衬底基板的正投影中，所述多个外周隔垫物中的部分外周隔垫物与所述分时复用电路交叠。
在一些实施例中，所述显示基板还包括设置于所述衬底基板上的栅极金属层和源漏电极层。
所述第一电压信号线包括位于所述栅极金属层的第一走线部，以及位于所述源漏电极层的第二走线部。
在向所述衬底基板的正投影中，所述第一走线部至少部分位于所述封装区，所述第二走线部位于所述封装区和所述显示区之间。
在一些实施例中，所述显示基板还包括第一电极层、发光层和第二电极层，所述发光层设置于所述第一电极层一侧，所述第二电极层设置于所述发光层远离所述第一电极层一侧。
其中，所述第一电极层包括设置于所述显示区的多个阳极，以及设置于所述周边区的转接部，所述多个阳极与所述转接部相互绝缘；所述第二电极层与所述转接部电连接。
又一方面，提供一种显示面板，所述显示面板包括显示基板、封装胶以及保护盖板。所述显示基板为上述实施例中所述的显示基板，所述封装胶设置于所述显示基板中封装区，所述保护盖板设置于所述封装胶远离衬底基板一侧。
其中，所述保护盖板与所述显示基板通过所述封装胶封装，所述显示基板的多个外周隔垫物在所述衬底基板的正投影，与所述保护盖板在所述衬底基板的正投影交叠。
在一些实施例中，所述外周隔垫物和所述封装胶在远离所述衬底基板的末端平齐或接近平齐。
再一方面，提供一种电子设备，包括上述实施例中任一项所述的显示面 板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的显示基板的结构图；
图2为根据一些实施例的显示基板在显示区的结构图；
图3为根据一些实施例的OLED发光器件的结构图；
图4为根据一些实施例的4T2C像素驱动电路的电路图；
图5为根据一些实施例提供的显示驱动电路的电路图；
图6为根据一些实施例提供的GOA电路的电路图；
图7为根据一些实施例的显示基板的层叠图；
图8为根据一些实施例的第一电极层的结构图；
图9为根据一些实施例的转接部在贯通孔位置的截面图；
图10为根据一些实施例的第二电极层与第一电极层的搭接图；
图11为根据一些实施例的转接部与第一电压信号线的结构图；
图12为根据一些实施例的第一电压信号线的结构图；
图13为根据一些实施例的显示区中显示隔垫物的结构图；
图14为根据一些实施例的显示基板的正面图；
图15为根据一些实施例的显示面板的层叠图；
图16为根据一些实施例的显示基板在第四区域的结构图；
图17为根据一些实施例的第一电压信号线与封装区的关系图；
图18为根据一些实施例的外周隔垫物的分布图；
图19为根据一些实施例的外周隔垫物在第一方向的分布图；
图20为根据一些实施例的转接部的结构图；
图21为图20中转接部在第一区域的结构图；
图22为根据一些实施例的转接部与外周隔垫物的结构图；
图23为图22中AA＇视图；
图24为根据一些实施例的显示面板中第一间隔在第一区域的结构图；
图25为图22中BB＇视图；
图26为图22中CC＇视图；
图27为根据另一些实施例的显示面板中第二间隔在第一区域的结构图；
图28为根据另一些实施例的显示面板中第二间隔在第四区域的结构图；
图29为根据又一些实施例的显示面板在显示区和第一区域中部分区域的结构图；
图30为根据一些实施例的显示面板在显示区的局部结构图；
图31为根据又一些实施例的显示面板在显示区和第一区域中部分区域的结构图；
图32为根据又一些实施例的显示面板在显示区和第四区域中部分区域的结构图；
图33为根据一些实施例的电子设备的示意图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术 语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间 存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
如图1所示，本公开的一些实施例提供一种显示基板1，该显示基板1包括显示区(Active Area，简称AA区)2和位于显示区2外周的非显示区3，其中，显示区2为该显示基板1中用于实现显示功能的区域，非显示区3为该显示基板1中无法进行显示的区域，通常位于显示区2的外周。
该显示基板1包括在显示区2中设置的多个像素单元，多个像素单元阵列排布形成像素阵列。
该显示基板1中的像素单元可以包括OLED(Organic Light-Emitting Diode，有机发光二极管)、QLED(Quantum Dot Light Emitting Diodes，量子点发光二极管)、Mini LED(次毫米发光二极管)或者Micro-LED(微型发光二极管)等。本公开实施例以像素单元为OLED像素单元5为例进行描述，其他类型的像素单元可以参考OLED像素单元5的有关内容。
在一些实施例中，每个OLED像素单元5包括多个OLED子像素4，对于能够实现彩色显示的显示基板1，每个OLED像素单元5可以均包括能够发出不同色彩的多种OLED子像素4；在该显示基板1进行显示时，通过控制每个OLED像素单元5中不同色彩的OLED子像素4的发光、混色实现彩色显示。
示例性地，OLED像素单元5包括能够发出红(Red)光的R子像素、能够发出绿(Green)光的G子像素以及能够发出蓝(Blue)光的B子像素。红色、绿色和蓝色为三基色，在该显示基板1进行显示时，通过控制R子像素、G子像素和B子像素不同程度的发光，实现三种颜色按照不同比例进行混色，从而可以实现该显示基板1的彩色显示。
在一些实施例中，OLED像素单元5还可以通过色彩转移或彩色滤光片等彩色化技术实现全彩显示。
OLED像素单元5中OLED子像素4的像素排列方式也有多种，例如，可以为RGB排列、GGRB排列、PenTile排列(简称P排)、Delta排列(简 称D排)和钻石排列等，对于不同像素排列，OLED像素单元5中OLED子像素4的种类、数目和大小也可能不同。本公开实施例不限定OLED像素单元5中OLED子像素4的像素排列方式。
图2为根据一些实施例的显示基板在显示区的结构图，如图2所示，在本公开的一些实施例中，显示基板1在显示区2中的多个OLED子像素4呈多行多列排布，包括多个沿像素行方向延伸的像素行8，以及，多个沿像素列方向延伸的像素列11。其中，像素行方向与像素列方向相互垂直，每个像素行8均包括沿像素行方向排列的多个OLED子像素4，每个像素列11中均包括沿像素列方向排列多个OLED子像素4。显示区2中的多个像素行8沿像素列方向并列排布，显示区2中的多个像素列11沿像素行方向并列排布，从而形成交叉布置的像素阵列。
以图2中所示的方位为例，像素行方向为横向方向，与图2中X坐标轴所在方向平行，像素列方向为纵向方向，与图2中Y坐标轴所在方向平行。
需要说明的是，为了描述方便，本文会以附图中标注的X坐标轴所在方向为横向方向，Y坐标轴所在方向为纵向方向进行结构描述，显然该横向和纵向为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
在显示区中，每个OLED子像素4均包括一个OLED发光器件10，以及一个用于驱动该OLED发光器件10发光的像素驱动电路9。
图3为根据一些实施例的OLED发光器件的结构图，请参考图3，OLED发光器件10包括阳极(Anode)14、有机功能层13和阴极(Cathode)12，阳极14与阴极12相对设置，有机功能层13位于阳极14与阴极12之间，包括有机发光层(Emitting Material Layer，缩写EML)；与不同颜色OLED发光器件10对应的有机发光层通常不同。
在该显示基板1进行显示时，通过控制阳极14和阴极12产生电场，在电场的作用下，阳极14产生的空穴和阴极12产生的电子就会发生移动，当二者相遇时产生能量激子，进而辐射复合产生可见光，以实现自发光显示。
阳极14可选用高功函数的材料制作，阴极12可选用低功函数的材料制作。有机功能层13还可以包括空穴传输层(Hole Transport Layer，缩写HTL)、空穴注入层(Hole Inject Layer，缩写HIL)、电子传输层(Electron Transport Layer，缩写ETL)和电子注入层(Electron Inject Layer，缩写EIL)中的至少一个，以提高有机发光层(EML)的发光效率。
每个OLED子像素4还包括用于驱动该OLED发光器件10发光的像素驱动电路9；像素驱动电路9根据驱动方式的不同分为无源驱动(Passive-Matrix，缩写PM)和有源驱动(Active-Matrix，缩写AM)。
在本公开的一些实施例中，显示基板1采用有源驱动，请继续参考图2，该显示基板1包括在显示区2中设置的多根扫描信号线(Scan Line)6、多根数据信号线(Data Line)7，以及，对应OLED子像素4设置的像素驱动电路9；像素驱动电路9中包括薄膜晶体管(Thin Film Transistor，缩写TFT)。
需要说明的是，本公开实施例中采用的薄膜晶体管包括源极、栅极和漏极，由于在一些情况下，源极、漏极是对称的，所以其源极、漏极是可以互换的。为了便于描述，本文将源极和漏极中的一个称为第一极，将源极和漏极中的另一个称为第二极，将栅极称为控制极；也就是说，当第一极为源极时，第二极为漏极；当第一极为漏极时，第二极为源极。
显示基板1还包括第一电压信号线、第二电压信号线与初始化电压信号线，其中，第一电压信号线被配置为向显示区2输出VSS电压信号，即阴极信号；第二电压信号线被配置为向显示区2输出VDD电压信号；初始化电压信号线被配置为向显示区2输出初始化电压信号。
如图2所示，多根扫描信号线6均沿像素行方向延伸，并且多根扫描信号线6在像素列方向上并列排布；多根数据信号线7均沿像素列方向延伸，并且多根数据信号线7在像素行方向上并列排布。多根扫描信号线6与多根数据信号线7交叉布置。OLED子像素4位于扫描信号线6和数据信号线7的交叉位置。
以图2中所示的方位为例，扫描信号线6的延伸方向为横向方向，且在纵向方向上并排设置，数据信号线7的延伸方向为纵向方向，且在横向方向上排列有多根。
在像素驱动电路9中，至少包括开关晶体管(Switching TFT)和驱动晶体管(Driving TFT)两个薄膜晶体管以及至少包括一个存储电容。通常可以采用像素驱动电路9中薄膜晶体管和存储电容的数目对像素驱动电路9进行简称表示，例如2T1C即包括2个薄膜晶体管和1个存储电容，7T1C即包括7个薄膜晶体管和1个存储电容；又例如还有5T1C、4T2C等。
图4为根据一些实施例的4T2C像素驱动电路的电路图，如图4所示，该像素驱动电路9包括第一薄膜晶体管T1、第二薄膜晶体管T2、第二薄膜晶体管T3、第四薄膜晶体管T4、第一电容C 1和第二电容C 2；并包括行扫描信号输入端、数据信号输入端、发光信号输入端、复位信号输入端、第一电压输 入端、第二电压输入端与初始化电压输入端。
其中，行扫描信号输入端与扫描信号线6连接，被配置为输入行扫描信号SCAN；数据信号输入端与数据信号线7连接，被配置为输入数据电压信号V Data；发光信号输入端与发光信号控制电路相连，被配置为输入发光信号EM；复位信号输入端与复位信号控制电路相连，被配置为输入复位像素驱动电路9的复位信号RESET；第一电压输入端与第一电压信号线相连，被配置为输入VSS电压信号；第二电压输入端与第二电压信号线相连，被配置为输入VDD电压信号；初始化电压输入端与初始化电压信号线相连，被配置为输入复位电压信号V init。
请继续参考图4，第一薄膜晶体管T1为开关晶体管，其控制极与行扫描信号输入端相连，第一极与数据信号输入端相连，第二极与第二薄膜晶体管T2的控制极相连。
第四薄膜晶体管T4为驱动晶体管，其控制极与第一薄膜晶体管T1的第二极相连，第一极与第二薄膜晶体管T2相连，第二极与OLED发光器件10的阳极14相连；OLED发光器件10中的阴极12与第一电压输入端相连。
第一电容C 1的一端与第二薄膜晶体管T2的控制极相连，另一端与第二极相连。
第二薄膜晶体管T2的控制极与发光信号输入端相连，第一极与第二电压输入端相连，第二极与第四薄膜晶体管T4的第一极相连。第二电容C 2的一端与第二电压输入端相连，另一端与第四薄膜晶体管T4的第二极相连。第三薄膜晶体管T3的控制极与复位信号输入端相连，第一极与初始化电压输入端相连，第二极与第四薄膜晶体管T4的第二极相连。
图5为根据一些实施例提供的显示驱动电路的电路图，如图5所示，该显示基板1包括控制显示的显示驱动电路，该显示驱动电路包括扫描驱动电路(Scan Driver IC)15、数据驱动电路(Data Driver IC)17与电源电路(Power IC)16。
其中，扫描驱动电路15与显示区2中的扫描信号线6相连，用于在显示驱动阶段输出控制开关晶体管的行扫描信号SCAN。对于不同的像素驱动电路9，扫描驱动电路15可能不同。
例如，在一些实施例中，扫描驱动电路15还被配置为向像素驱动电路9中的发光信号输入端输出发光控制信号EM，以及被配置为向像素驱动电路9中复位信号输入端输出复位信号RESET。
数据驱动电路17与显示区2中的数据信号线7相连，用于在显示驱动阶 段向像素驱动电路9中数据信号输入端提供数据电压信号V data。数据驱动电路17通常采用绑定于显示基板1的集成电路芯片。
电源电路16用于将输入电压转换为不同大小的工作电压并输出，例如电源电路16分别与第一电压信号线36、第二电压信号线和初始化电压信号线相连，被配置为向显示区2输出VSS电压信号、VDD电压信号和初始化电压信号V init。
在本公开一些实施例的显示基板中，扫描驱动电路15采用GOA(Gate Driver on Array)设计，即将扫描驱动电路15集成在显示基板上；利用GOA技术集成在显示基板的扫描驱动电路15也被称为GOA电路。
GOA电路通常设置于扫描信号线6(像素行8)的端部外侧，沿数据信号线7延伸方向(像素行8的排布方向)级联的多级移位寄存器单元(GOA单元)，当前级移位寄存器单元输出信号除了输出驱动本行像素单元的像素晶体管外，还输出至上一级移位寄存器单元(如果有的话)，作为上一级移位寄存器单元的复位信号；还输出至下一级移位寄存器单元(如果有的话)，作为下一级移位寄存器单元的输入信号。
在整个GOA电路中，第一级移位寄存器单元的输入信号是帧起始信号STV，而且不输出复位信号。最后一级移位寄存器单元连接一级冗余移位寄存器单元(Dummy GOA)，实现最后一级移位寄存器单元的复位。由此可以看出，级联的多级移位寄存器单元互相影响，产生移位脉冲信号，实现对像素阵列进行逐行扫描。
图6为根据一些实施例提供的GOA电路的电路图，如图6所示，GOA电路18通常包括扫描信号控制电路(Gate GOA，缩写G-GOA)183、发光信号控制电路(EM GOA，缩写E-GOA)181与复位信号控制电路(Reset GOA，缩写R-GOA)182；其中，扫描信号控制电路183被配置为在显示驱动阶段输出行扫描信号SCAN，像素驱动电路9在接收到行扫描信号SCAN时控制开关晶体管导通。发光信号控制电路181被配置为在显示驱动阶段输出发光信号EM，像素驱动电路9在接收到发光信号EM时控制发光。复位信号控制电路182被配置为在显示驱动阶段输出复位信号RESET，像素驱动电路9在接收到复位信号RESET时能够实现初始化复位，以清除可能存在的信号残留，保证显示基板1的显示效果。
GOA电路18中扫描信号控制电路183与复位信号控制电路182通常采用一体化设计，也就是说，在GOA电路18中仅包括扫描信号控制电路183与发光信号控制电路181，采用扫描信号控制电路183既输出控制开关晶体管 的行扫描信号SCAN，又输出复位信号RESET至像素驱动电路9。
然而在一些应用场景中，例如大尺寸、高刷新率的产品中，为了保证扫描信号控制电路183与复位信号控制电路182的驱动能力，GOA电路18中的复位信号控制电路182可以单独设置。
图7为根据一些实施例的提供的一种显示基板的层叠图，如图7所示，该显示基板1包括衬底基板19，以及在衬底基板19一侧层叠设置的阻挡层(Buffer)32、有源层34、第一栅绝缘层(GI1)20、栅极金属层(Gate)33、第二栅绝缘层(GI2)21、层间绝缘层(Inter Layer Dielectric，缩写ILD)22、第一源漏金属层(SD1)31、第一平坦层(Planarization，缩写PLN)23、钝化层(Passivation，缩写PVX)24、第二源漏金属层(SD2)30、第二平坦层25、像素界定层(Pixel Definition Layer，缩写PDL)27、隔垫物(Photo Spacer，缩写PS)层28、第一电极层26、有机功能层13和第二电极层29。
其中，衬底基板19可以为刚性的板状结构，例如可以为玻璃板、石英板或亚克力板等。衬底基板19包括相对设置的第一表面与第二表面，以图7中所示方位为例，第一表面和第二表面为横向放置的相对平面，且在纵向方向上，第一表面位于第二表面的上方，也就是说，第一表面为上表面，第二表面为下表面。
本文中定义与衬底基板19中第一表面垂直的方向为层叠方向，层叠方向与图7中Z坐标轴所在方向平行。
需要说明的是，为了描述方便，本文会以附图中标注的X坐标轴、Y坐标轴与Z坐标轴为参考进行结构描述，但是X坐标轴、Y坐标轴与Z坐标轴并不局限于直角坐标系的三条轴线，而是可以以更广泛的意义解释。例如，X坐标轴、Y坐标轴与Z坐标轴可以相互垂直，或者可以表示相互不垂直的不同的方向。
阻挡层32设置于衬底基板19的第一表面，为无机绝缘膜层，可以采用含硅无机材料制作，并且可以为多层或者单层结构，含硅无机材料可以为氧化硅SiO 2、氮化硅SiN X和氮氧化硅SiON中的至少一种。如此设计，利用无机材料的材料特性，隔离衬底基板19和衬底基板19上的结构，减小或者阻断外来物质、湿气、或者外界空气从衬底基板19的下方渗透，并且可以提供平坦表面。
有源层34设置于阻挡层32远离衬底基板19的一侧，可以采用非晶硅(Amorphous Silicon，缩写α-Si，又名无定形硅)、多晶硅(Polycrystalline Silicon，缩写Poly-Si)、低温多晶硅(Low-temperature Polycrystalline Silicon， LTPS)，或者，金属氧化物(例如氧化铟镓锌Indium Gallium Zinc Oxide，缩写IGZO)等材料制作。
第一栅绝缘层20设置于有源层34远离衬底基板19的一侧，第一栅绝缘层20远离衬底基板19的一侧设置有栅极金属层33，栅极金属层33包括位于显示区2的薄膜晶体管的栅极和扫描信号线6。有源层34包括与栅极对应的沟道区。
第二栅绝缘层21设置于栅极金属层33远离衬底基板19的一侧，层间绝缘层22设置于第二栅极绝缘层远离衬底基板19的一侧；第一源漏金属层31设置于层间绝缘层22远离衬底基板19的一侧；第一源漏金属层31远离衬底基板19的一侧设置有第一平坦层23和钝化层24，钝化层24远离衬底基板19的一侧设置有第二源漏金属层30。
第一源漏金属层31和第二源漏金属层30为处于不同高度的金属层，薄膜晶体管中的源极、漏极，显示基板中的数据信号线7第一电压信号线、第二电压信号线和初始化电压信号线等信号线，以及，存储电容的极板可以选择性地设置在第一源漏金属层31或第二源漏金属层30。对某些信号线，还可以在第一源漏金属层31和第二源漏金属层30中均设置。通过在不同金属层中走线的方式，可以降低信号线电阻以及耦合电容，有利于适应大尺寸、高分辨率及高刷新率的应用场景。
另外，显示基板中的数据信号线、第一电压信号线、第二电压信号线和初始化电压信号线等信号线以及存储电容的极板可以部分或全部设置在栅极金属层33。
第二源漏金属层30在远离衬底基板19的一侧设置有第二平坦层25，第二平坦层25远离衬底基板19的一侧具有平坦的表面，该平坦的表面方便其上方结构的制作成型。
根据以上描述可知，在有源层34、第一栅绝缘层20、栅极金属层33、第二栅绝缘层21、层间绝缘层22、第一源漏金属层31、第一平坦层23、钝化层24、第二源漏金属层30与第二平坦层25中能够形成驱动OLED发光器件10的像素驱动电路9，因此也通常合并在一起称作驱动电路层。驱动电路层为显示基板1中全部OLED子像素4的像素驱动电路9的统称，衬底基板19与驱动电路层通常合并在一起称作背板(Backplane，简称BP)。
第一电极层26设置于第二平坦层25远离衬底基板19的一侧，第一电极层26包括位于显示区2的多个阳极14。阳极14与驱动电路层相连。
像素界定层27设置于第一电极层26远离衬底基板19的一侧，具有像素 开口。第一电极层26中的阳极14通过像素开口露出。有机功能层13设置于像素开口中，第二电极层29位于有机发光层远离第一电极层26的一侧。位于像素开口中的有机功能层13以及位于有机功能层13两侧的第一电极层26和第二电极层29形成一个OLED发光器件10。
隔垫物层28设置于像素界定层27远离衬底基板19的一侧，包括位于显示区2的多个显示隔垫物281，显示隔垫物281为立设于像素界定层27的柱状结构，该柱状结构用于支撑蒸镀所用的掩膜板(MASK)。
在上述实施方式中，第一栅绝缘层20、第二栅绝缘层21、层间绝缘层22和钝化层24均为无机绝缘膜层，可以采用含硅无机材料制作，并且可以为多层或者单层结构，含硅无机材料可以为氧化硅SiO 2、氮化硅SiN X和氮氧化硅SiON中的至少一种。
图8为根据一些实施例的第一电极层的结构图，如图8所示，第一电极层26包括位于显示区2中的多个阳极14，多个阳极14与显示区2中的OLED子像素4一一对应。第一电极层26还包括位于非显示区3的转接部35，转接部35与显示区2中的多个阳极14相互绝缘。转接部35设置有多个贯通孔351，贯通孔351用于在工艺阶段的排气。
如图9所示，显示基板1还包括填充贯通孔351的填充部271，填充部271包覆贯通孔351的边缘，从而避免贯通孔351被在制作过程中被药液侧蚀。在一些实施例中，填充部271与像素界定层27同层设计，即像素界定层27的一部分用作填充贯通孔351的填充部271。
图10为根据一些实施例的第二电极层与第一电极层的搭接图，请参考图10，第二电极层29覆盖显示区2，作为显示区2中OLED子像素4的公共电极，第二电极层29中与OLED子像素4对应的部分为OLED发光器件10的阴极12。第二电极层29还自显示区2向外侧延伸，延伸至转接部35所在位置并与转接部35接触实现搭接。
图11为根据一些实施例的转接部与第一电压信号线的结构图，如图11所示，显示基板1包括第一电压信号线36，转接部35与第一电压信号线36相连，第一电压信号线36被配置为向显示区2输出VSS电压信号。
通过采用上述设计，显示基板1可以通过第一电压信号线36、转接部35和第二电极层29向显示区2输出VSS电压信号，即向OLED发光器件10的阴极12输出阴极信号。
需要说明的是，用于对第二电极层29转接VSS电压信号的转接部35可以与第一电极层26同层设置，也可以与其他金属层同层设置；例如，转接部 35可以与源漏金属层同层设置。
图12为根据一些实施例的第一电压信号线的结构图，如图12所示，在一些实施例中，第一电压信号线36包括第一走线部361和第二走线部362，第一走线部361和第二走线部362分别位于不同层，如此设计，通过双层走线的方式，降低走线电阻，从而实现降低第一电压信号线36压降的技术效果。
示例性地，第一电压信号线36包括位于第一源漏金属层31的第一走线部361，以及位于栅极金属层33的第二走线部362。第一源漏金属层31的电阻一般为栅极金属层33电阻的1/10，因此在第一走线部361和第二走线部362并列走线时可以降低走线电阻，从而缩小压降的技术效果。
图13为根据一些实施例的显示区中显示隔垫物281的结构图，如图13所示，显示区3中的显示隔垫物281位于像素开口的一侧，即在OLED发光器件10的一旁设置，并且多个显示隔垫物281沿像素行方向和像素列方向呈行列排布。
本公开的一些实施例提供了一种显示面板，如图14和图15所示，该显示面板41包括显示基板1、封装胶40和保护盖板39，其中，封装胶40和保护盖板39设置于显示基板1的显示侧，显示侧为显示基板的显示方向指向的一侧，以图7所示的实施方式为例，封装胶40和保护盖板39设置于第二电极层29远离衬底基板19的一侧。
保护盖板39为透明的刚性板，例如为玻璃板、石英板或塑料板等，用于对显示基板1进行封装保护。封装胶40设置有保护盖板39与显示基板1之间，用于连接保护盖板39与显示基板1。保护盖板39通过封装胶40与显示基板1封装。
该显示基板1的非显示区3包括封装区37与周边区38，其中，封装区37为用于设置封装胶40的区域，通过封装区37中的封装胶40连接显示基板1与保护盖板39，从而实现与保护盖板39封装的封装。
为了保证封装胶40对整个显示区2中OLED发光器件10的密封效果，封装区37设计为套设于显示区2外周的闭合环状区域，设置在封装区37的封装胶40同样为闭合的环状胶体。
在显示基板1中，显示区2与封装区37之间的区域为周边区38，周边区38也为套设于显示区2外周的闭合环状区域。周边区38可以根据与显示区2不同的相对位置，划分为不同的区域。
该显示基板1及显示区2的边界线轮廓可以为方形、圆形、椭圆形或者其他规则或不规则的形状，与之对应地，封装区37和周边区38为与显示基 板1及显示区2的边界线轮廓相匹配的形状。
在图14所示的实施方式中，显示基板1的边界线轮廓为第一矩形，显示区2的边界线轮廓为第二矩形，第一矩形套设于第二矩形外侧，且第一矩形中的矩形长边和第二矩形中的矩形长边相互平行。周边区38和封装区37均为具有一定宽度的矩形边框。
在本实施例中，第一矩形中的矩形长边和第二矩形中的矩形长边均与像素行方向平行，也即与扫描信号线6的延伸方向平行。第一矩形中的矩形短边和第二矩形中的矩形短边均与像素列方向平行，也即与数据信号线7的延伸方向平行。
沿像素行方向，该显示基板1的周边区38包括分置于显示区2两侧的第一区域381和第二区域382，沿像素列方向，该背板的周边区38包括分置于显示区2两侧的第三区域383和第四区域384。
通过上述描述可知，扫描信号线6的延伸方向与像素行方向平行，数据信号线7的延伸方向与像素列方向平行。也就是说，第一区域381和第二区域382为周边区38中沿扫描信号线6的延伸方向分置于显示区2两侧的部分，第三区域383和第四区域384为周边区38中沿数据信号线7的延伸方向分置于显示区2两侧的部分。
以图14中所示方位为例，像素行方向、扫描信号线6的延伸方向、第一矩形中矩形长边的所在方向和第二矩形中矩形长边的所在方向均为横向方向，与图14中X坐标轴平行，第一区域381和第二区域382为周边区38位于显示区2左、右两侧的部分，第一区域381位于显示区2的左侧，第二区域382位于显示区2的右侧，即第一区域381为左边框区域，第二区域382为右边框区域。
像素列方向、数据信号线7的延伸方向、第一矩形中矩形短边的所在方向和第二矩形中矩形短边的所在方向均为纵向方向，与图14中Y坐标轴平行，第三区域383和第四区域384为周边区38位于显示区2上、下两侧的部分，第三区域383位于显示区2的上方，第四区域384位于显示区2的下方，即第三区域383为上边框区域，第四区域384为下边框区域。
显示基板1在第一区域381和/或第二区域382通常设置有扫描驱动电路15，在扫描驱动电路15为GOA电路18的实施方式中，GOA电路18可以在显示区2的单侧设置，即仅在第一区域381或第二区域382中设置。
在GOA电路18具有扫描信号控制电路183、发光信号控制电路181与复位信号控制电路182的实施方式中，GOA电路18中扫描信号控制电路183、 复位信号控制电路182与发光信号控制电路181沿与扫描信号线6所在方向排布在第一区域381或第二区域382，排布顺序可以为任意顺序。示例性地，扫描信号控制电路183、复位信号控制电路182与发光信号控制电路181沿远离显示区2的方向依次排布，其中，扫描信号控制电路183靠近显示区2的边界设置。
在GOA电路18具有扫描信号控制电路183与发光信号控制电路181的实施方式中，扫描信号控制电路183与发光信号控制电路181排布在第一区域381或第二区域382，排布顺序可以为任意顺序。示例性地，扫描信号控制电路183与发光信号控制电路181沿远离显示区2的方向依次排布，其中，扫描信号控制电路183靠近显示区2的边界设置。
在一些可能的实施例中，GOA电路18可以在显示区2的双侧设置，即在第一区域381和第二区域382中均设置。例如，在第一区域381设置有驱动部分像素行8的第一GOA电路18，在第二区域382设置有驱动剩余部分像素行8的第二GOA电路18。示例性地，第一GOA电路18用于驱动偶数像素行8，第二GOA电路18用于驱动奇数像素行8。第一GOA电路18和第二GOA电路18的排布可参考上文关于单侧设置的排布方式，此处不再赘述。
又例如，在第一区域381和第二区域382分别设置GOA电路184的不同功能部分，示例性地，在GOA电路18包括扫描信号控制电路183与发光信号控制电路181的实施方式中，扫描信号控制电路183与发光信号控制电路181中的一方可以设置于第一区域381，另一方可以设置有第二区域382。
请参考图16，在本公开的一些实施例中，该显示基板1在第四区域384中设置有扇出区43，显示区2中的数据信号线7延伸至第四区域384，即在下边框区域，并经过扇出区43后延伸走线在封装区37外部的位置与数据驱动电路17相连。
数据驱动电路17通常采用绑定于显示基板1的集成电路芯片，然而数据驱动电路17能够与数据信号线7连接的引脚数量有限，因此在一些实施例中，显示基板1包括在第四区域384设置的分时复用电路42，显示基板1在分时复用电路42远离显示面板41的一侧具有扇出区43。
其中，分时复用电路42包括多个多路选择器(Multiplexer，简称MUX)，多路选择器通常具有一个输入端和至少两个输出端，多路选择器的输入端与中间走线431相连，中间走线431经过扇出区43后延伸走线，并在封装区37外部的位置与数据驱动电路17相连。多路选择器的至少两个输出端分别与数据信号线7相连；多路选择器实现将由数据驱动电路17中一个输出端输出的 数据电源信号分时传输至该多根数据信号线7中。
在可能的实施方式中，数据信号线7也可以在显示区2的顶部引出，扇出区43和分时复用电路42相应地设置在第三区域383，即设置在上边框区域。
图17为根据一些实施例的第一电压信号线与封装区的关系图，如图17所示，该显示基板1在周边区38包括被配置向显示区2提供VSS信号的第一电压信号线36，第一电压信号线36在第一区域381、第三区域383和第二区域382中围绕显示区2的外周边缘延伸布置，第一电压信号线36的两端延伸至第四区域384，电源电路16与第一电压信号线36的两端端部连接。
在具有GOA电路18的周边区38，也就是第一区域381和/或第二区域382，第一电压信号线36相对于GOA电路18远离显示区2设置，位于GOA电路18相对于显示区2的外侧。
在一些实施例中，第一电压信号线36包括第一走线部361和第二走线部362，第一走线部361和第二走线部362分别位于不同层，在向衬底基板19的正投影中，第一走线部361位于封装区37和显示区2之间，第二走线部142至少部分位于封装区37。
根据上述描述可知，保护盖板39通过设置于封装区37的封装胶40与显示基板1密封封装。在本实施例中，显示面板41的封装方式为Frit(玻璃胶)封装，即通过设置于封装区37的玻璃胶(Frit Seal)，保护盖板39与显示基板1在玻璃胶熔融固化后实现密封封装，Frit封装方式具有无需开槽，阻隔水氧能力好，工艺较简单等优势。
封装胶40通常为沿闭合轮廓延伸的胶体结构，例如封装胶40可以为方框胶体。在封装胶40的支撑下，显示基板1和保护盖板39之间在显示面板41的显示方向上保持有一定的间隙，该被封装胶40支撑出的、位于显示基板1和保护盖板39之间的间隙为封装间隙。
可以理解的，封装间隙的大小与封装胶40的厚度相关，较厚的封装胶40可以支撑起的封装间隙较大，而较薄的封装胶40可以支撑起的封装间隙较小。
本文将显示基板1和保护盖板39之间被封装胶40包围的空间定义为框胶空间，框胶空间中被空气填充，例如氮气N 2，形成具有厚度的空气薄膜，空气薄膜的厚度与所在位置的封装间隙相等。
在相关技术中，保护盖板39虽然一般具有一定的刚性要求，但是由于自身材料和结构等因素的影响，在自然状态或者外力作用下，例如：保护盖板39还会受到外力作用，例如触摸按压、意外挤压等，保护盖板39在受外力作用下容易发生朝向显示基板1的形变，形变后的保护盖板39与显示基板1之 间的空气薄膜厚度变小甚至为零。
在保护盖板39会朝向显示基板1一侧形变，且形变幅度达到一定程度时，例如与显示基板1接触时，在接触位置会产生彩色牛顿环，即彩虹纹不良，彩色牛顿环的圆心即该接触位置。
牛顿环是一种薄膜干涉现象，薄膜干涉是指假设照射一束光波于薄膜，由于折射率不同，光波会被薄膜的上界面与下界面分别反射，因相互干涉而形成新的光波的现象。
牛顿环属于薄膜干涉中的等厚干涉现象，干涉图样是一些明暗相间的同心圆环。例如用一个曲率半径很大的凸透镜的凸面和一平面玻璃接触，在日光下或用白光照射时，可以看到干涉图样中接触点为一暗点，其周围为一些明暗相间的彩色圆环；而用单色光照射时，干涉图样则表现为一些明暗相间的单色圆环。牛顿环中的圆环(彩色圆环或单色圆环)为光线相互干涉而形成的干涉圆环，干涉圆环相对于圆心的次序为干涉圆环的极次，对于彩色圆环而言，干涉图样中不同极次的彩色圆环具有不同的颜色。
在相关技术中显示面板41的常见应用场景中，通常在日光和白色灯光下使用，因此牛顿环为具有颜色的彩色牛顿环。
鉴于此，本公开实施例提供一种显示基板，请参考图18，该显示基板1包括在周边区38中设置的多个外周隔垫物44，多个外周隔垫物44中的外周隔垫物44在该显示基板1与保护盖板39封装时，用于支撑保护盖板39。也就是说，多个外周隔垫物44在衬底基板的正投影，与保护盖板39在衬底基板的正投影交叠。
其中，定义与多个外周隔垫物44相邻的显示区2的边界垂直的方向为第一方向。沿第一方向，多个外周隔垫物44中最靠近封装区37的外周隔垫物，到封装区37的距离为第一距离。多个外周隔垫物44中最靠近封装区37的外周隔垫物，到显示区2的距离为第二距离。其中，第一距离小于或等于第二距离。
也就是说，第一距离与周边区38的宽度的比值为0～0.5，示例性的，0～0.2、0.2～0.4、0.4～0.5，例如，0、0.05、0.1、0.15、0.2、0.25、0.3、0.35、0.4、0.45与0.5。
如此设计，在周边区38的多个外周隔垫物44中，最靠近封装区37的外周隔垫物44布置在距离封装区37边界较近的位置。需要说明的是，当第一距离与周边区38的宽度的比值为0时，也即当第一距离为0时，最靠近封装区37的外周隔垫物44处于与周边区38接触相邻的位置。
本公开实施例提供的显示基板1采用上述设计，一方面通过增设外周隔垫物44能够提高显示基板1在与保护盖板39封装时，对保护盖板39的支撑效果，避免保护盖板39在外周隔垫物44的布置位置发生形变，从而能够起到改善、甚至消除牛顿环(彩虹纹不良)的效果，以提高具有该显示基板1的显示面板41的显示质量。
另一方面，在周边区38的多个外周隔垫物44中，最靠近封装区37的外周隔垫物44布置距离封装区37边界较近的位置。如此设计，使得在即使发生牛顿环时，牛顿环的发生位置也会处于靠近封装区37而远离显示区2的位置，从而降低、甚至消除牛顿环对显示区2中显示效果的影响，提高具有该显示基板1的显示面板41的显示质量。
在本公开的一些实施例中，外周隔垫物44为立设于显示基板1的柱状结构，该柱状结构可以为圆柱、锥形柱或方形柱等规则或不规则的立体形状。外周隔垫物44可以与显示隔垫物281同层设置，也可以采用单独的有机层图案化形成。
需要说明的是，此处“立设于显示基板1”是指外周隔垫物44的延伸方向与显示基板1中衬底基板19垂直或基本垂直，也就是说，与上文定义的层叠方向(图7中Z坐标轴所在方向)平行或基本平行。
为了在显示基板1与保护盖板39封装时，使得外周隔垫物44能够实现对保护盖板39的支撑作用，外周隔垫物44远离显示基板1的末端与封装胶40远离显示基板1的末端应当平齐或接近平齐。本文中定义：沿与显示基板1中衬底基板19垂直的层叠方向，外周隔垫物44远离显示基板1的末端与衬底基板19的距离为第一高度，封装胶40远离显示基板1的末端与衬底基板19的距离为第二高度；外周隔垫物44远离显示基板1的末端与封装胶40远离显示基板1的末端平齐是指第一高度与第二高度相等，接近平齐是指第一高度与第二高度虽然不相等，但是两者的差距较小，该较小的差距使得保护盖板39即使发生形变时，形变幅度也不会产生彩色牛顿环。
另外还需要说明的是，第二电极层29设置于外周隔垫物44远离显示基板1的末端，外周隔垫物44支撑着第二电极层29与保护盖板39接触，通常情况下第二电极层29由于厚度较小，在与外周隔垫物44的高度进行比较时可以忽略。但是在需要考虑第二电极层29厚度的场景下，以上关于外周隔垫物44高度的限制应当理解对外周隔垫物44加第二电极层29厚度之和的限定。
为了便于描述周边区38中多个外周隔垫物44的分布情况，本文中定义与多个外周隔垫物44相邻的显示区2的边界垂直的方向为第一方向，与多个 外周隔垫物44相邻的显示区2的边界平行的方向为第二方向。处于周边区38同一位置的第一方向和第二方向相互垂直，在周边区38的不同位置，第一方向可能是不同的；当第一方向不同时，第二方向也是不同的。
例如，在图14所示的实施方式中，在周边区38中的第一区域381和第二区域382中，第一方向为横向延伸的方向，平行于图14中X坐标轴所在方向；第二方向为纵向延伸的方向，平行于图14中X坐标轴所在方向。
在周边区38中的第三区域383和第四区域384，第一方向为纵向延伸的方向，平行于图14中Y坐标轴所在方向；第二方向为横向延伸的方向，平行于图14中X坐标轴所在方向。
又例如，显示区2的边界形状为圆形，周边区38的边界形状为与显示区2同心的圆环形状；第一方向在周边区38的不同位置均为圆形显示区2的径向方向，第二方向在周边区38的不同位置均为与第一方向垂直的方向，也即圆形显示区2在对应位置的切线所在方向。
在本公开的一些实施例中，周边区38中的多个外周隔垫物44在沿第一方向的多个不同位置，以及沿第二方向的多个不同位置均有布置；通过在第一方向和第二方向的多个不同位置设置外周隔垫物44，能在周边区38的不同位置实现对保护盖板39的支撑目的，从而能够保证在周边区38中的多个位置均可以起到改善、甚至消除牛顿环的效果。
可以理解的，多个外周隔垫物44在周边区38中布置的越多，布置的区域范围越大，对保护盖板39的支撑区域也越大，支撑效果也越好，对牛顿环的改善效果程度也就越大。
示例性地，多个外周隔垫物44沿第三方向和第四方向呈多行多列排布，第三方与第四方向垂直；其中，第三方向可以与第一方向平行，在第一方向与第三方向平行时，第四方向也与第二方向平行；根据上文描述可知，在周边区38的不同位置，第一方向可能是不同的；因此，多个外周隔垫物44行列排布的行方向与列方向，在周边区38的不同位置也可能是不同的。
在第一方向随所在位置的不同而发生变化的实施方式中，第三方向和第四方向可以与某一位置的第一方向和第二方向平行，即在周边区38中，多个外周隔垫物44行列排列的行方向与列方向保持一致。
例如，请参考图18，周边区38中多个外周隔垫物44的行列排列的行方向与列方向，和显示区2中多个显示隔垫物281的行方向和列方向相同，均与显示区2中像素行方向和像素列方向平行。
在本公开的一些实施例中，呈多行多列排布的多个外周隔垫物44在相邻 行和/或相邻列之间可以错开设置，通过错开设置的形式，可以有效提升外周隔垫物44对保护盖板39的支撑效果。
在本公开的一些实施例中，多个显示隔垫物281与多个外周隔垫物44均沿相同的行方向与列方向排列成多行多列，至少一行外周隔垫物44与一行显示隔垫物281位于同一条直线上，且显示隔垫物281的行的数目多于外周隔垫物44的行的数目。
和/或，至少一列外周隔垫物44与一列显示隔垫物281位于同一条直线上，且显示隔垫物281的列的数目多于外周隔垫物44的列的数目。
在本公开的一些实施例中，多个显示隔垫物281与多个外周隔垫物44均排列成多行多列，一行外周隔垫物44与一行显示隔垫物281构成了一个隔垫物行。在隔垫物行中，至少部分相邻的外周隔垫物44之间的距离与相邻的显示隔垫物281之间的距离相等。
和/或，一列外周隔垫物44与一列显示隔垫物281构成了一个隔垫物列。在隔垫物列中，至少部分相邻的外周隔垫物44之间的距离与相邻的显示隔垫物281之间的距离相等。
请参考图19，为了方便描述，本文中定义沿第一方向，多个外周隔垫物44中，最靠近封装区37的外周隔垫物44为第一外周隔垫物441，最靠近显示区2的外周隔垫物44为第二外周隔垫物442。第一外周隔垫物441沿第一方向与封装区37的边界之间的距离即第一距离，第一距离采用L 1表示。第一外周隔垫物441沿第一方向与显示区2的边界之间的距离即第二距离，第二距离采用L 2表示。
定义沿第一方向，第二外周隔垫物442和第一外周隔垫物441之间的间距为第三距离，第三距离采用L 3表示；定义第二外周隔垫物442在第一方向上与显示区2的边界之间的距离为第四距离，第四距离采用L 4表示。
定义沿第一方向，相邻两个外周隔垫物44之间间距最大的为最大间距，最大间距采用L MAX表示；间距最小的为最小间距，最小间距采用L MIN表示。另外，沿第一方向，周边区38中两外侧边界之间的距离为周边区38的宽度，采用L表示周边区38的宽度。
通过限制第一距离L 1、第二距离L 2、第三距离L 3、第四距离L 4与周边区38的宽度L的关系，可以表示周边区38中多个外周隔垫物44的分布区域，相对于显示区2边界的位置以及相对于封装区37边界的位置。
在本公开的一些实施例中，第一距离L 1与周边区38宽度L的比值为0至0.2，也就是说，在多个外周隔垫物44中，沿第一方向最接近封装区37边 界的第一外周隔垫物441到封装区37边界的距离，为周边区38宽度的0％到20％；示例性的，0～0.08、0.08～0.16、0.16～0.2，例如，0、0.02、0.04、0.06、0.08、0.1、0.12、0.14、0.16、0.18、0.2。
因此可以看出，沿第一方向，多个外周隔垫物44中，最接近封装区37边界的第一外周隔垫物441处于距离封装区37较近的位置；如此设计，能够在更靠近封装区37的位置，对保护盖板39实现有效的支撑，从而一方面能够起到改善、甚至消除牛顿环的效果，以提高具有该显示基板1的显示面板41的显示质量。
另一方面，在即使发生牛顿环时，将牛顿环的发生位置移动到靠近封装区37的位置，即远离显示区2的位置，从而降低、甚至消除牛顿环对显示区2中显示效果的影响，提高具有该显示基板1的显示面板41的显示质量。
在第一距离L 1与周边区38宽度L的比值为0或接近0的情况下，第一外周隔垫物441处于封装区37靠近周边区38的边界，或接近封装区37的位置。如此设计，能够在封装区37靠近周边区38的边界，或接近封装区37的位置，对保护盖板39实现有效的支撑，从而可以避免在多个外周隔垫物44与封装区37之间发生牛顿环的情况，以提高具有该显示基板1的显示面板41的显示质量。
在本公开的一些实施例中，第一距离L 1大致等于第四距离L 4，需要说明的是，此处大致等于应该理解第一距离L 1与第四距离L 4的比值在1左右，例如第一距离L 1与第四距离L 4的比值为0.9-1.1之间。
第一距离L 1大致等于第四距离L 4，是指，在多个外周隔垫物44中，沿第一方向最接近显示区2边界的第二外周隔垫物442与显示区2的边界的距离，和最接近封装区37边界的第一外周隔垫物441与封装区37边界的距离相当。
也就是说，在本公开的一些实施例中，周边区38的多个外周隔垫物44在靠近显示区2的一侧也采用布置到距离显示区2边界较近位置的设置。如此设计，能够在靠近显示区2边界的区域，对保护盖板39实现有效的支撑，从而能够起到改善、甚至消除牛顿环的效果，以提高具有该显示基板1的显示面板41的显示质量。
在第二外周隔垫物442距离显示区2较近的情景中，第二外周隔垫物442可以处于显示区2的边界，或接近显示区2边界的位置。
在一些应用场景中，外周隔垫物44通过显示区2中的显示隔垫物281延伸布置，外周隔垫物44的分布区域自显示区2边界位置，沿第一方向朝向封 装区37延伸，并延伸至封装区37边界线的附近。因此，第四距离L 4可以小于第一距离L 1。
通过上文描述可知，周边区38的多个外周隔垫物44在靠近显示区2一侧采用靠近显示区2边界的设计，在靠近封装区37的一侧采用靠近封装区37边界的设计。在一些实施例中，沿第一方向，多个外周隔垫物44在周边区38中分布区域的两端分别为或接近边界。示例性地，沿第一方向，第一外周隔垫物441与第二外周隔垫物442之间的距离为第三距离L 3，第三距离L 3大于或等于周边区38的宽度L的80％。
为了保证第一外周隔垫物441与第二外周隔垫物442之间外周隔垫物44对保护盖板39的支撑效果，还应限制在沿第一方向的外周隔垫物44不应过于稀疏。
在本公开的一些实施例中，L MAX≤20×L MIN。
也就是说，在沿第一方向，多个外周隔垫物44中，相邻两个外周隔垫物44之间最大间距不应超过最小间距的20倍，也即，外周隔垫物44的排布不应过于稀疏。
在一些实施例中，第一距离L 1小于或等于L MAX；也就是说，沿第一方向，第一外周隔垫物441到封装区37边界的距离，小于相邻两个外周隔垫物44中最大间距L MAX，如此设计一方面能够限制第一外周隔垫物441到封装区37边界的距离较小，另一方面能够限制在第一方向上，外周隔垫物44的排布不过于稀疏。
在一些实施例中，第一距离L 1小于或者等于260μm。
虽然限定了第一距离L 1与周边区38宽度L的比例关系，但是由于在显示面板41中，第一区域381、第二区域382、第三区域383和第四区域384的宽度通常不同，因此第一距离在不同区域中可能不同。例如，在一具体产品中，位于第一区域381中第一距离L 1为188μm，在第二区域382中第一距离L 1为153μm，在第三区域383中第一距离L 1为164μm，在第四区域384中第一距离L 1为248μm。由此可以看出，在一些产品中，第一距离L 1为150μm～260μm。
通过上述描述可知，周边区38中的多个外周隔垫物44的布置数目越多，对保护盖板39的支撑面积也越大，对保护盖板39的支撑效果也就越好，对牛顿环的改善效果程度也就越大。然而，过多的外周隔垫物44会增大在蒸镀时与掩膜板(MASK)的接触面积，从而会加剧粘片的问题。
鉴于此，应当在保证外周隔垫物44对保护盖板39支撑效果的同时，还 应限制外周隔垫物44与保护盖板39的接触面积。在一些实施例中，可以采用面积占比来表示外周隔垫物44和显示隔垫物281的分布情况。定义多个外周隔垫物44在周边区38的面积占比为第一占比，多个显示隔垫物281在显示区2中的面积占比为第二占比；其中，第一占比小于第二占比。
如此设计，在顾及外周隔垫物44支持效果的同时，减小了外周隔垫物44的面积占比，即减少了周边区38中外周隔垫物44与保护盖板39的接触面积，从而减弱了蒸镀时外周隔垫物44与掩膜板粘片问题，
在一些实施例中，第一占比与第二占比的比值小于或等于65％，例如可以为60％。
第二占比，即多个显示隔垫物281在显示区2中的面积占比，一般低于10％。第二占比通常有像素排列方式有关，例如对于GGRB排列的产品，第二占比约为7.6％。
在本公开的一些实施例中，外周隔垫物44和显示隔垫物281的形状、大小相同，外周隔垫物44的单个面积与显示隔垫物281的单个面积相同；在此种情况下，第一占比与第二占比之间的关系，即为在单位面积中外周隔垫物44的数目与显示隔垫物281的数目之间的关系。例如，在第一占比与第二占比的比值小于或等于65％的实施方式中，在单位面积中，外周隔垫物44的数目小于或等于显示隔垫物281的数目的65％。
另外，在相关技术的显示面板41中，转接部35靠近显示区的边界距离显示区的边界较近，由于转接部35为第一电极层26的一部分，为大片金属或反射膜层；因此在显示区发光显示时，转接部35会对显示区的发光进行反射，从而影响显示质量。
鉴于此，在本公开实施例提供的显示基板中，控制转接部35内侧边界距离显示区2的间距，使其能够改善转接部35对显示区2的发光进行反射的问题，从而可以避免由于转接部35反光而影响显示质量。
请结合图20和图21，转接部35靠近显示区2的边界与显示区2的边界之间具有第一间隔352，基于上文定义的第一方向，定义沿第一方向，第一间隔352的宽度为第一间距，第一间距采用S 1表示。第一间隔S 1大于第一距离L 1。
在本公开的一些实施例中，第一间距S 1应当在300μm以上。
如此设计，在沿第一方向，转接部35靠近显示区2的边界与显示区2的边界之间具有300μm以上的间隔时，能够显著改善转接部35对显示区2的发光进行反射的问题，从而可以避免由于转接部35反光而影响显示质量。
在转接部35为环绕延伸的闭合结构的实施方式中，在围绕显示区2的不同位置，第一间距S 1均应满足上述的间隔条件。
示例性地，转接部35为套设于显示区2外侧的闭合结构，第一间距S 1在周边区38的第一区域381、第二区域382、第三区域383和第四区域384中均为345μm。
第一间隔352的设置可以露出显示基板1对应位置的结构，本文定义经第一间隔露出的结构为第一露出结构。多个外周隔垫物44中的部分外周隔垫物44设置于转接部35的上方；以及多个外周隔垫物44中的部分外周隔垫物44在第一间隔设置于第一露出结构的上方。
也就是说，多个外周隔垫物44中的部分外周隔垫物44在衬底基板19的正投影，与转接部35在衬底基板19的正投影交叠；以及，多个外周隔垫物44中的部分外周隔垫物44在衬底基板19的正投影，与第一露出结构在衬底基板19的正投影交叠。
图22为根据一些实施例的转接部与外周隔垫物的结构图，图23为图22中AA＇视图；如图22和图23所示，多个外周隔垫物44中的部分外周隔垫物44在第一间隔352设置于第一露出结构46的上方。
其中，在第一露出结构46上方为第二平坦层25，第二平坦层25远离第一露出结构46的一侧为隔垫物垫块45，隔垫物垫块45远离第二平坦层25的一侧设置有外周隔垫物44，外周隔垫物44支撑第二电极层29。隔垫物垫块45可以与像素界定层27同层设置。
通过上文描述可知，GOA电路18设置于周边区38的第一区域381和/或第二区域382。针对具有GOA电路18的第一区域381和/或第二区域382，在向衬底基板19的正投影中，GOA电路18靠近显示区2的边界，相较于转接部35靠近显示区2的边界更靠近显示区2，且转接部35与GOA电路18不交叠或部分交叠。第一间隔露出部分或全部GOA电路18，多个外周隔垫物44中的部分外周隔垫物44设置于露出的GOA电路18的上方。此处通过第一间隔露出的GOA电路即第一露出结构46。
在一些实施例中，扫描驱动电路15包括位于第一驱动电路和第二驱动电路，第一驱动电路和第二驱动电路中的一方被配置为输出行扫描信号，另一方为被配置为输出发光控制信号；第一驱动电路相对于第二驱动电路靠近显示区2。
在向衬底基板19的正投影中，转接部35与第二驱动电路至少部分交叠，与第一驱动电路不交叠；或，转接部35与第一驱动电路和第二驱动电路均不 交叠。
示例性地，在向衬底基板19的正投影中，转接部35与第二驱动电路全部交叠，与第一驱动电路不交叠。
在一些其他实施例中，扫描驱动电路15还包括第三驱动电路，第三驱动电路被配置为输出复位信号。
沿远离显示区2的方向，第一驱动电路、第三驱动电路和第二驱动电路依次布置。
在向衬底基板19的正投影中，转接部35与第二驱动电路和第三驱动电路至少部分交叠，与第一驱动电路不交叠；或，转接部35与第二驱动电路至少部分交叠，与第一驱动电路和第三驱动电路不交叠；或，转接部35与第一驱动电路、第三驱动电路和第二驱动电路均不交叠。
示例性地，转接部35与第二驱动电路和第三驱动电路全部交叠，与第一驱动电路不交叠。请参考图24，在一些实施例中，显示面板包括位于第一区域381的第一子初始化信号线47，第一子初始化信号线47为初始化电压信号线的部分，在第一区域381靠近显示区2边界线的位置，沿相邻显示区2的边界延伸；即沿第二方向延伸。
第一驱动电路48包括多根控制信号线481以及多个GOA单元482，多根控制信号线481相对于多个GOA单元482远离显示区2，多根控制信号线481均沿第二方向延伸走线，且沿第二方向并列排布。多个GOA单元482沿第二方向排布，并与控制信号线481相连。
转接部35与第一驱动电路48不交叠，是指与多根控制信号线481以及多个GOA单元482均不交叠，以通过第一间隔352露出多根控制信号线481以及多个GOA单元482。
对于第四区域384而言，显示基板1包括分时复用电路42，在向衬底基板19的正投影中，分时复用电路42靠近显示区2的边界，相较于转接部35靠近显示区2的边界更靠近显示区2，且转接部35与分时复用电路42不交叠或部分交叠。分时复用电路42部分或全部通过第一间隔352露出，此处露出的部分即第一露出结构46。多个外周隔垫物44中的部分外周隔垫物44设置于第一露出结构46的上方。即，在向衬底基板19的正投影中，多个外周隔垫物44中的部分外周隔垫物44与分时复用电路42交叠。
对于第三区域383而言，显示基板1包括第一电压信号线36；在向衬底基板19的正投影中，第一电压信号线36靠近显示区2的边界，相较于转接部35靠近显示区2的边界更靠近显示区2，且转接部35与第一电压信号线 36不交叠或部分交叠。第一电压信号线36部分或全部通过第一间隔352露出，此处露出的部分即第一露出结构46。多个外周隔垫物44中的部分外周隔垫物44设置于第一露出结构46的上方。
通过上文描述，多个外周隔垫物44中的部分外周隔垫物44设置于转接部35的上方。在设置于转接部35的实施方式中，还包括外周隔垫物44设置在转接部35中具有贯通孔351的位置，以及不具有贯通孔35的位置，
请参考图22和图25，外周隔垫物44设置在转接部35具有贯通孔351的位置，其中，显示基板1在第二平坦层25一侧设置有转接部35，转接部35具有贯通孔351，贯通孔351被填充部271填充；填充部271远离转接部35的一侧设置有外周隔垫物44，外周隔垫物44撑起第二电极层29，第二电极层29在外周隔垫物44一侧的位置与转接部35搭接。
请参考图22和图26，外周隔垫物44设置在转接部35未设置贯通孔的位置，其中，显示基板1在第二平坦层25一侧设置有转接部35，转接部35一侧设置有隔垫物垫块45，隔垫物垫块45远离转接部35的一侧设置有外周隔垫物44，外周隔垫物44撑起第二电极层29，第二电极层29在外周隔垫物44一侧的位置与转接部35搭接。
请继续参考图20和图21，转接部35远离显示区2的一端可以延伸至封装区37所在位置，或延伸至靠近封装区37的位置，转接部35靠近封装区37的边界与封装区37之间具有第二间隔353；本文中定义沿第一方向，第二间隔353的宽度为第二间距，第二间距采用S 2表示。第二间距S 2通常小于第一间距S 1。
第二间隔353的设置可以露出显示基板1对应位置的结构，定义经第二间隔353露出的结构为第二露出结构。多个外周隔垫物44中的部分外周隔垫物44可以在第二间隔353设置于第二露出结构的上方。外周隔垫物44在第二间隔设置于第二露出结构的上方的方案，可参考上文关于外周隔垫物44设置于第一露出结构的上方的方案，此处不再赘述。在第二露出结构的上方也可以不设置外周隔垫物44。
示例性地，图27为根据另一些实施例的显示面板中第二间隔在第一区域的结构图，如图27所示，转接部35靠近封装区37的边界与封装区37之间具有第二间隔353，在第一区域381中，经第二间隔353露出的第二露出结构为第一电压信号线36，第一电压信号线36在第一区域381中沿与相邻显示区2边界平行的方向延伸，即沿第二方向延伸。多个外周隔垫物44中的部分外周隔垫物44在第二间隔353设置于第一电压信号线36的上方，且沿第二电压信号线36的延伸方向延伸排布。
图28为根据另一些实施例的显示面板中第二间隔在第四区域的结构图，如图28所示，转接部35靠近封装区37的边界与封装区37之间具有第二间 隔353，在第四区域384中，经第二间隔353露出的第二露出结构可以为扇出区中的中间走线，第二露出结构上并未设置外周隔垫物。
图29为根据又一些实施例的显示面板在显示区和第一区域中部分区域的结构图，如图29所示，该显示面板在显示区2中采用GGRB排列，在每个OLED像素单元中，均包括一个R子像素，一个B子像素以及两个G子像素，且两个G子像素沿扫描信号线的延伸方向排布，一个R子像素、一个B子像素与两个G子像素沿数据信号线的延伸方向排布。
以图29中所示方位为例，扫描信号线的延伸方向为横向方向，与图29中X坐标轴所在方向平行，数据信号线的延伸方向为纵向方向，与图28中Y坐标轴所在方向平行。即在图28中所示的一个OLED像素单元中，两个G子像素沿横向方向排布，一个R子像素、一个B子像素与两个G子像素沿纵向方向排布。
根据上述描述可知，第一电极层26包括位于显示区2的多个阳极14，位于第一区域381的转接部35。在GGRB排列的实施方式中，第一电极层26在每个OLED像素单元均中包括一个R阳极141，一个B阳极142以及两个G阳极143。在一个OLED像素单元中，两个G阳极143沿横向方向排布，一个B阳极142、一个R阳极141与两个G阳极143沿纵向方向排布。
第一电极层26还包括位于第一区域的第一子初始化信号线47，第一子初始化信号线47为初始化电压信号线的部分，在第一区域381靠近显示区2边界线的位置，沿相邻显示区2的边界延伸，也即沿纵向方向延伸。
显示区2中的包括多对显示隔垫物281，一对显示隔垫物281中的2个显示隔垫物281横向排列，每个显示隔垫物281均为沿横向方向延伸的矩形结构。也即显示隔垫物281的延伸方向垂直于第一子初始化信号线的延伸方向。
如图29所示，在显示区2中沿纵向方向，相邻的一个R子像素与一个B子像素之间的区域，相邻的一个B子像素与两个G子像素之间，以及相邻的两个G子像素与R子像素之间的位置设置有一对显示隔垫物281。
在两个G子像素上下两侧的一对显示隔垫物281中，两个显示隔垫物281分别与两个G子像素一一对应。
在一些实施方式中，显示区2中显示隔垫物281可以相对于扫描信号线和数据信号线倾斜放置，例如，如图30所示，显示区2中显示隔垫物281与子像素的斜边平行。
第一区域381中的外周隔垫物44采用与显示隔垫物281相同的形状与大小，多个显示隔垫物281与多个外周隔垫物44均沿相同的行方向与列反向排列成多行多列，且至少一行外周隔垫物44与一行显示隔垫物281位于同一条直线上。另外，显示隔垫物的行的数目多于外周隔垫物的行的数目，从而使得第一占比小于第二占比，其中，多个外周隔垫物44在周边区38的面积占 比为第一占比，多个显示隔垫物281在显示区2中的面积占比为第二占比。
由于外周隔垫物44和显示隔垫物281的形状、大小相同，外周隔垫物44的单个面积与显示隔垫物281的单个面积相同；在此种情况下，第一占比与第二占比之间的关系，即为在单位面积中外周隔垫物44的数目与显示隔垫物281的数目之间的关系。
例如，在图29中具有面积相等的两个虚线正方形边框，一个位于显示区2中，一个位于第一区域381。位于显示区2中的虚线正方形边框包围有6对显示隔垫物281，位于第一区域381的虚线正方形边框包围有4对外周隔垫物44。
第一占比与第二占比之间的关系并不局限于此，能够使多个外周隔垫物与多个显示隔垫物相对均匀即可。
例如，如图31所示，图31中具有面积相等的三个虚线正方形边框，一个位于显示区2中，两个位于第一区域381。位于显示区2中的虚线正方形边框包围有6对显示隔垫物281，位于第一区域381的两个虚线正方形边框分别包围有5对外周隔垫物44和3对周隔垫物44，并且包围有3对周隔垫物44的虚线正方形边框相对于包围有5对周隔垫物44的虚线正方形边框远离显示区2。也就是说，在一些实施例中，越远离显示区2，外周隔垫物44的面积占比越小。
图32为根据又一些实施例的显示面板在显示区与第四区域的结构图，如图32所示，第一电极层26包括位于显示区2的多个阳极，以及位于第四区域384的转接部35。该显示面板包括位于显示区2中的多个显示隔垫物281，以及位于第四区域384中的多个外周隔垫物44。多个外周隔垫物44在第四区域384中的设置可以参考第一区域381，此处不再赘述。通过图28和图29也可以看出，在多个外周隔垫物44与多个显示隔垫物281之间，其列数目相同，且对齐。多个外周隔垫物44的行数目小于多个显示隔垫物281的行数目。
如图33所示，本公开同时提供了一种具有上述实施例中显示面板的电子设备100，该电子设备100为具有图像(包括：静态图像或动态图像，其中，动态图像可以是视频)显示功能的产品，例如，电子设备100可以是：显示器、手机、笔记本电脑、平板电脑、个人穿戴设备、广告牌、数码相框和电子阅读器等中的任一种。
上述电子设备100具有与上述一些实施例中提供的显示面板41相同的结构和有益技术效果，在此不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (28)

  1. 一种显示基板，包括显示区，位于所述显示区外侧的封装区，以及位于所述显示区与所述封装区之间的周边区；
    所述显示基板包括：
    衬底基板；
    设置在所述衬底基板一侧的像素界定层；以及
    设置在所述像素界定层远离所述衬底基板一侧的隔垫物层；
    其中，所述隔垫物层包括设置在所述周边区的多个外周隔垫物；
    与所述多个外周隔垫物相邻的所述显示区的边界垂直的方向为第一方向，沿所述第一方向，所述多个外周隔垫物中最靠近所述封装区的外周隔垫物，到所述封装区的距离为第一距离；所述多个外周隔垫物中最靠近所述封装区的外周隔垫物，到所述显示区的距离为第二距离；
    所述第一距离小于或等于所述第二距离。
  2. 根据权利要求1所述的显示基板，其中，所述周边区在垂直于和周边区相邻的显示区的边界的方向的尺寸为所述周边区的宽度，所述第一距离与所述周边区的宽度比值小于或等于0.2。
  3. 根据权利要求1或2所述的显示基板，其中，沿所述第一方向，所述多个外周隔垫物中，最靠近所述封装区的外周隔垫物为第一外周隔垫物，最靠近所述显示区的外周隔垫物为第二外周隔垫物；
    所述第一外周隔垫物与所述第二外周隔垫物之间的距离，大于或等于所述周边区的宽度的80％。
  4. 根据权利要求1～3中任一项所述的显示基板，其中，所述多个外周隔垫物沿第一方向的排列成多行，且沿第二方向的排列成多列；所述第二方向和所述第一方向相垂直。
  5. 根据权利要求1～4中任一项所述的显示基板，其中，沿所述第一方向，相邻两个外周隔垫物之间的最大间距为L MAX，相邻两个外周隔垫物之间的最小间距为L MIN；
    其中，L MAX≤20×L MIN。
  6. 根据权利要求5所述的显示基板，其中，所述第一距离小于或等于L MAX；
    所述第一距离小于或等于260μm。
  7. 根据权利要求1～6中任一项所述的显示基板，所述显示基板还包括设置在所述显示区的多个显示隔垫物；
    所述多个外周隔垫物在所述周边区的面积占比为第一占比，所述多个显示隔垫物在所述显示区的面积占比为第二占比；所述第一占比小于所述第二占比。
  8. 根据权利要求7所述的显示基板，其中，所述第一占比与所述第二占比的比值小于或等于65％。
  9. 根据权利要求7或8所述的显示基板，其中，至少一个外周隔垫物与至少一个显示隔垫物形状与尺寸相同。
  10. 根据权利要求7～9中任一项所述的显示基板，其中，所述多个显示隔垫物与所述多个外周隔垫物均排列成多行多列，至少一行外周隔垫物与一行显示隔垫物位于同一条直线上，显示隔垫物的行的数目多于外周隔垫物的行的数目。
  11. 根据权利要求7～9中任一项所述的显示基板，其中，所述多个显示隔垫物与所述多个外周隔垫物均排列成多行多列，一行外周隔垫物与一行显示隔垫物构成了一个隔垫物行，在所述隔垫物行中，至少部分相邻的外周隔垫物之间的距离与相邻的显示隔垫物之间的距离相等。
  12. 根据权利要求1～11中任一项所述的显示基板，所述显示基板还包括：
    设置于所述衬底基板上的第一电压信号线，所述第一电压信号线被配置为向所述显示区传输阴极信号；以及
    设置于所述周边区的转接部，所述转接部与所述第一电压信号线电连接，所述转接部靠近所述显示区的边界与所述显示区之间具有第一间隔；
    其中，沿垂直于所述显示区的边界的方向，所述第一间隔的距离大于所述第一距离。
  13. 根据权利要求12所述的显示基板，其中，沿垂直于所述显示区的边界的方向，所述第一间隔的距离大于或等于300μm。
  14. 根据权利要求12或13所述的显示基板，其中，所述多个外周隔垫物中的部分外周隔垫物在所述衬底基板的正投影，与所述转接部在所述衬底基板的正投影交叠；以及
    所述多个外周隔垫物中的部分外周隔垫物设置于所述第一间隔内；和/或，所述转接部靠近所述封装区的边界与所述封装区之间具有第二间隔，所述多个外周隔垫物中的部分外周隔垫物设置于所述第二间隔内。
  15. 根据权利要求12～14中任一项所述的显示基板，所述显示基板还包括设置于所述外周隔垫物靠近所述衬底基板一侧的隔垫物垫块；所述像素界定层与所述隔垫物垫块同层设置。
  16. 根据权利要求15所述的显示基板，其中，所述转接部包括贯通孔，所述显示基板还包括填充所述贯通孔的填充部，所述填充部与所述像素界定层同层设置。
  17. 根据权利要求12～16中任一项所述的显示基板，所述显示基板还包括第一电极层，所述第一电极层包括所述转接部以及位于所述显示区的多个阳极。
  18. 根据权利要求12～16中任一项所述的显示基板，其中，所述转接部为套设于所述显示区外侧的闭合结构。
  19. 根据权利要求12～18中任一项所述的显示基板，所述显示基板还包括多根扫描信号线；
    所述周边区包括沿所述多根扫描信号线的延伸方向分布于所述显示区两侧的第一区域和第二区域；
    所述显示基板还包括设置于所述第一区域和/或所述第二区域的扫描驱动电路，所述扫描驱动电路与所述多根扫描信号线电连接；
    在向所述衬底基板的正投影中，所述扫描驱动电路靠近所述显示区的边界，相较于所述转接部靠近所述显示区的边界更靠近所述显示区，且所述转接部在所述衬底基板的正投影与所述扫描驱动电路在所述衬底基板的正投影不交叠或部分交叠。
  20. 根据权利要求19所述的显示基板，其中，所述扫描驱动电路包括第一驱动电路和第二驱动电路，所述第一驱动电路和所述第二驱动电路中的一方被配置为输出行扫描信号，另一方为被配置为输出发光控制信号；
    所述第一驱动电路相对于所述第二驱动电路靠近所述显示区；
    在向所述衬底基板的正投影中，所述转接部与所述第二驱动电路至少部分交叠，与所述第一驱动电路不交叠；或，所述转接部与所述第一驱动电路和所述第二驱动电路均不交叠。
  21. 根据权利要求19或20所述的显示基板，其中，所述扫描驱动电路还包括第三驱动电路，所述第三驱动电路被配置为输出复位信号；
    沿远离所述显示区的方向，所述第一驱动电路、所述第三驱动电路和所述第二驱动电路依次布置；
    在向所述衬底基板的正投影中，所述转接部与所述第二驱动电路和所述第三驱动电路至少部分交叠，与所述第一驱动电路不交叠；或，所述转接部与所述第二驱动电路至少部分交叠，与所述第一驱动电路和所述第三驱动电路不交叠；或，所述转接部与所述第一驱动电路、所述第三驱动电路和所述 第二驱动电路均不交叠。
  22. 根据权利要求21所述的显示基板，其中，在所述衬底基板的正投影中，所述多个外周隔垫物中的部分外周隔垫物与所述第三驱动电路和所述第二驱动电路交叠。
  23. 根据权利要求12～22中任一项所述的显示基板，所述显示基板还包括多根数据信号线；
    所述周边区包括沿所述多条数据信号线的延伸方向分布于所述显示区两侧的第三区域和第四区域；所述显示基板还包括位于所述第四区域远离所述显示区的一侧的扇出区；
    所述显示基板还包括设置于所述第四区域的分时复用电路，所述分时复用电路与所述多根数据信号线电连接；
    在向所述衬底基板的正投影中，所述分时复用电路靠近所述显示区的边界，相较于所述转接部靠近所述显示区的边界更靠近所述显示区，且所述转接部与所述分时复用电路不交叠或部分交叠；
    在向所述衬底基板的正投影中，所述多个外周隔垫物中的部分外周隔垫物与所述分时复用电路交叠。
  24. 根据权利要求12～23中任一项所述的显示基板，所述显示基板还包括设置于所述衬底基板上的栅极金属层和源漏电极层；
    所述第一电压信号线包括位于所述栅极金属层的第一走线部，以及位于所述源漏电极层的第二走线部；
    在向所述衬底基板的正投影中，所述第一走线部至少部分位于所述封装区，所述第二走线部位于所述封装区和所述显示区之间。
  25. 根据权利要求1～24中任一项所述的显示基板，所述显示基板还包括：
    第一电极层；
    设置于所述第一电极层一侧的发光层；以及
    设置于所述发光层远离所述第一电极层一侧的第二电极层；
    其中，所述第一电极层包括设置于所述显示区的多个阳极，以及设置于所述周边区的转接部，所述多个阳极与所述转接部相互绝缘；所述第二电极层与所述转接部电连接。
  26. 一种显示面板，包括：
    如权利要求1～25中任一项所述的显示基板；
    设置于所述显示基板中封装区的封装胶；以及
    设置于所述封装胶远离衬底基板一侧的保护盖板；
    其中，所述保护盖板与所述显示基板通过所述封装胶封装，所述显示基板的多个外周隔垫物在所述衬底基板的正投影，与所述保护盖板在所述衬底基板的正投影交叠。
  27. 根据权利要求26所述的显示面板，其中，所述外周隔垫物和所述封装胶在远离所述衬底基板的末端平齐或接近平齐。
  28. 一种电子设备，包括如权利要求26或27所述的显示面板。
PCT/CN2022/102693 2022-06-30 2022-06-30 显示基板、显示面板及电子设备 WO2024000361A1 (zh)

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CN104517990A (zh) * 2013-09-27 2015-04-15 群创光电股份有限公司 有机发光二极管显示面板、有机发光二极管显示设备
CN107275517A (zh) * 2017-06-30 2017-10-20 京东方科技集团股份有限公司 一种显示基板及其制备方法和显示装置
CN107302016A (zh) * 2017-08-08 2017-10-27 京东方科技集团股份有限公司 一种有机发光二极管显示面板及其制作方法
CN111384110A (zh) * 2018-12-31 2020-07-07 乐金显示有限公司 电致发光显示装置
CN212062439U (zh) * 2019-12-30 2020-12-01 华为技术有限公司 一种显示装置和终端设备
CN113539177A (zh) * 2021-07-30 2021-10-22 京东方科技集团股份有限公司 扫描控制电路及其驱动方法、栅极驱动电路、显示装置

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CN1750720A (zh) * 2004-09-16 2006-03-22 Lg.菲利浦Lcd株式会社 有机电致发光器件及其制造方法
CN104517990A (zh) * 2013-09-27 2015-04-15 群创光电股份有限公司 有机发光二极管显示面板、有机发光二极管显示设备
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