WO2024114368A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2024114368A1
WO2024114368A1 PCT/CN2023/131546 CN2023131546W WO2024114368A1 WO 2024114368 A1 WO2024114368 A1 WO 2024114368A1 CN 2023131546 W CN2023131546 W CN 2023131546W WO 2024114368 A1 WO2024114368 A1 WO 2024114368A1
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WO
WIPO (PCT)
Prior art keywords
area
bus
substrate
packaging
layer
Prior art date
Application number
PCT/CN2023/131546
Other languages
English (en)
French (fr)
Inventor
卢彦伟
周桢力
闫卓然
程羽雕
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2024114368A1 publication Critical patent/WO2024114368A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G09F9/335—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes being organic light emitting diodes [OLED]

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel and a display device.
  • Display panels are an indispensable part of electronic devices such as mobile phones. Among them, organic electroluminescent display panels (OLEDs) that use organic light-emitting diodes as light-emitting devices are widely used.
  • OLEDs organic electroluminescent display panels
  • the light-emitting devices need to be packaged, but the packaging effect of the existing packaging method needs to be improved.
  • the present disclosure provides a display panel and a display device.
  • a display panel comprising a display area and a peripheral area outside the display area, wherein the peripheral area comprises a lead-out area, and the lead-out area comprises a binding portion; the display panel comprises:
  • a driving backplane comprising a substrate and a circuit layer arranged on one side of the substrate, wherein the circuit layer comprises a packaging substrate and a power bus distributed in a direction away from the substrate, wherein the packaging substrate is arranged in the peripheral area and around the display area; the power bus is at least partially located in the lead-out area, and the part of the power bus located in the lead-out area is located between the display area and the binding part and is connected to the binding part; the packaging substrate is at most The package substrate is partially overlapped with the lead-out area; the package substrate is a reflective structure;
  • a light emitting device is provided on a side of the circuit layer away from the substrate and located in the display area;
  • the packaging glue is at least partially disposed on a surface of the packaging base away from the substrate and surrounds the display area along an extension track of the packaging base;
  • the packaging cover is arranged on the surface of the packaging glue away from the substrate.
  • the package substrate includes a transfer portion at a portion of the lead-out region
  • the power bus includes a first bus portion and a second bus portion, wherein the first bus portion is at least partially located on a side of the adapter portion close to the display area; the second bus portion is at least partially located on a side of the adapter portion away from the display area and is connected to the binding portion; the first bus portion and the second bus portion are both connected to the adapter portion.
  • the transition portion includes a first transition portion and a second transition portion spaced apart along a first direction;
  • the power bus includes a first power bus and a second power bus, wherein the first bus portion and the second bus portion of the first power bus are connected via the first adapter portion; and the first bus portion and the second bus portion of the second power bus are connected via the second adapter portion.
  • the circuit layer also includes a plurality of first signal lines, wherein the first signal lines are at least partially located in the lead-out area and between the display area and the binding portion; the portion of the first signal lines located in the lead-out area includes a first segment extending along the first direction and a second segment extending along the second direction, and the second segment connects the first segment and the binding portion.
  • the peripheral area further includes side areas distributed along the first direction on both sides of the display area and a top area distributed on a side of the display area away from the lead-out area;
  • the packaging substrate comprises a substrate body located in the side area and the top area, at least a portion of the first section, and at least a portion of the second section;
  • Each of the first signal lines includes two signal line groups that are symmetrically distributed about the central axis of the binding portion along the second direction; and the first adapter portion is located between the two signal line groups.
  • the peripheral area further includes side regions distributed along the second direction on both sides of the display region and a top region distributed along the second direction on a side of the display region away from the lead-out region;
  • the first section is located between the transition portion and the display area, and the second section and the transition portion are distributed along the first direction;
  • the packaging substrate comprises a substrate body located in the side area and the top area and at least a portion of each of the second segments;
  • Each of the first signal lines is divided into two signal line groups that are symmetrically distributed about the central axis of the binding portion along the second direction; and the adapter portion is located outside the two signal line groups.
  • the packaging substrate further includes a first dummy portion, which is spaced apart between the first transition portion and the second transition portion along the first direction; and the packaging glue covers the first dummy portion.
  • a second dummy portion is provided between the second sections belonging to the packaging substrate, and the packaging glue covers the second dummy portion.
  • both the first dummy portion and the second dummy portion extend along the second direction.
  • At least a portion of the second section belonging to the packaging substrate extends along a bending track.
  • At least a portion of the second section belonging to the packaging substrate includes a first bending portion and a second bending portion bent in opposite directions in the first direction, and the first bending portion and the second bending portion are alternately distributed along the second direction.
  • the circuit layer further includes a plurality of first signal lines, wherein at least a portion of the first signal lines is located in the lead-out area and between the display area and the binding portion; a portion of the first signal lines located in the lead-out area includes a first segment extending along a first direction and a second segment extending along a second direction, wherein the second segment connects the first segment and the binding portion;
  • the portion of the power bus located in the lead-out area includes a first bus portion extending along the first direction and a second bus portion extending along the second direction, the second bus portion connecting the first bus portion and the binding portion; the first bus portion is located between the first signal line and the display area; the second bus portion overlaps with the first section, and the packaging glue covers the second bus portion.
  • the second bus portion is provided with a plurality of first through holes, and the packaging glue fills the first through holes.
  • a width of the second bus portion in the first direction is not greater than 300 ⁇ m.
  • a partial area of the package substrate is provided with a second through hole.
  • the second through hole is filled with a filling layer, and the filling layer is provided with a plurality of third through holes; and the packaging glue fills each of the third through holes.
  • the circuit layer includes a first gate layer, a first gate insulating layer, a second gate layer, an interlayer dielectric layer, a first source-drain layer, a first flat layer, a second source-drain layer, and a second flat layer, which are sequentially distributed in a direction away from the substrate; the light-emitting device is provided on a surface of the second flat layer away from the substrate;
  • the packaging substrate is located at the first gate layer or the second gate layer, and the power bus is located at the first source-drain layer or the second source-drain layer.
  • a display device comprising any one of the display panels described above.
  • FIG. 1 is a top view of an embodiment of a display panel of the present disclosure.
  • FIG. 2 is a schematic diagram of wiring of an embodiment of a display panel disclosed herein.
  • FIG. 4 is a partial cross-sectional schematic diagram of a display area in an embodiment of a display panel disclosed herein.
  • FIG. 5 is a schematic cross-sectional view of a first embodiment of a display panel according to the present disclosure.
  • FIG. 6 is a partial schematic diagram of FIG. 5 .
  • FIG. 7 is a schematic cross-sectional view of a second embodiment of the display panel of the present disclosure.
  • FIG. 8 is a schematic cross-sectional view of a third embodiment of the display panel of the present disclosure.
  • FIG. 9 is a partial top view of a packaging substrate in an embodiment of a display panel disclosed herein.
  • FIG. 10 is a partial top view of a base body in an embodiment of a display panel disclosed herein.
  • FIG. 11 is a partial top view of a packaging substrate in another embodiment of a display panel disclosed herein.
  • FIG. 12 is a partial top view of a lead-out area in an embodiment of a display panel disclosed herein.
  • FIG. 13 is a partial top view of a packaging substrate in yet another embodiment of a display panel disclosed herein.
  • the first direction X and the second direction Y herein are merely two directions perpendicular to each other or intersecting at other angles.
  • the first direction X may be horizontal and the second direction Y may be vertical, but the present invention is not limited thereto. If the display panel is rotated, the actual directions of the first direction X and the second direction Y may change.
  • overlapping of feature A and feature B means that the orthographic projection of feature A on the substrate and the orthographic projection of feature B on the substrate at least partially overlap.
  • the embodiment of the present disclosure provides a display panel, as shown in FIG. 1 to FIG. 3 , the display panel includes a display area AA and a peripheral area WA outside the display area AA, the peripheral area WA includes a lead-out area FA, the lead-out area FA includes a binding portion BA; the display panel includes:
  • the driving backplane BP includes a substrate SU and a circuit layer TL arranged on one side of the substrate SU, the circuit layer TL includes a packaging substrate TB and a power bus distributed in a direction away from the substrate SU, the packaging substrate TB is arranged in the peripheral area WA and at least partially surrounds the display area AA; the power bus is at least partially located in the lead-out area FA, and the part of the power bus located in the lead-out area FA is located between the display area AA and the binding part BA, and is connected to the binding part BA; the packaging substrate TB at most overlaps with the part of the power bus located in the lead-out area FA; the packaging substrate TB is a reflective structure;
  • the light emitting device LD is arranged on a side of the circuit layer TL away from the substrate SU and is located in the display area AA;
  • the packaging glue FR is at least partially disposed on the surface of the packaging base TB away from the substrate SU, and at least partially surrounds the display area AA along the extension track of the packaging base TB;
  • the packaging cover plate CG is disposed on the surface of the packaging glue FR away from the substrate SU.
  • the display panel of the embodiment of the present disclosure can cover the light-emitting device LD with the encapsulation cover plate CG, and seal it with the encapsulation glue FR to protect the light-emitting device LD.
  • a light-emitting encapsulation base TB is provided in the peripheral area WA, and the encapsulation glue FR is provided on the encapsulation base TB, the light intensity on the encapsulation glue FR can be enhanced, the curing degree of the encapsulation glue FR can be improved, and the connection between the encapsulation cover plate TB and the driving back plate BP can be made tighter and firmer, thereby improving the encapsulation effect.
  • the encapsulation glue FR is supported by the encapsulation base TB, which is conducive to improving the flatness of the surface where the encapsulation glue FR is located, and reducing the risk of cracks in the drop ball test when there are steps with large step differences in the area covered by the encapsulation glue FR, thereby improving the product yield.
  • the display area AA of the display panel is a light-emitting area for displaying images.
  • the peripheral area WA is located outside the display area AA.
  • the peripheral area WA may be a continuous or discontinuous annular area surrounding the display area AA, or may be a semi-enclosed area such as a "U" shape.
  • the shape of the peripheral area WA is not specifically limited here.
  • the peripheral area WA may include a lead-out area FA, and the lead-out area FA has a binding portion BA.
  • the binding portion BA may be connected to a flexible circuit board, which may be connected to a control circuit board, and the control circuit board may transmit a signal to the binding portion BA through the flexible circuit board.
  • the peripheral area WA can be divided into a plurality of areas, including a lead-out area FA surrounding the display area AA, two side areas
  • the two side areas SA and the top area TA, the two side areas SA may be distributed on both sides of the display area AA along the first direction X, and may be symmetrically arranged about the central axis of the display area AA along the second direction Y.
  • the top area TA and the lead-out area FA may be distributed on both sides of the display area AA along the second direction Y, that is, the top area TA is located on the side of the display area AA away from the lead-out area.
  • the lead-out area FA, the two side areas SA and the top area TA may be connected to form a ring-shaped peripheral area WA surrounding the display area AA.
  • the display area AA and the peripheral area WA are divided according to their functions, but are not limited to physical boundaries in the display panel for realizing the partitions.
  • the driving backplane BP has a driving circuit for driving the light emitting device LD to emit light.
  • the driving circuit may include a pixel circuit located in the display area AA and a peripheral circuit located in the peripheral area WA, wherein:
  • One pixel circuit can be connected to one light-emitting device LD.
  • one pixel circuit is connected to multiple light-emitting devices LD. This article only takes the one-to-one connection between the pixel circuit and the light-emitting device LD as an example for explanation.
  • the pixel circuit may include multiple transistors and capacitors, which may be 3T1C, 7T1C, 8T1C and other pixel circuits.
  • nTmC means that a pixel circuit includes n transistors (indicated by the letter “T") and m capacitors (indicated by the letter “C").
  • the peripheral circuit may be connected to the pixel circuit and the light emitting device LD, and may control the current passing through the light emitting device LD through the pixel circuit, thereby controlling the brightness of the light emitting device LD.
  • the peripheral circuit may include a plurality of transistors and capacitors, and may include a gate drive circuit and a light emitting control circuit, etc. Of course, it may also include other circuits, and the specific structure of the peripheral circuit is not particularly limited here.
  • the above pixel circuit may adopt LTPS (low temperature polysilicon) technology, that is, each transistor of the pixel circuit is a low temperature polysilicon transistor.
  • LTPS low temperature polysilicon
  • LTPO LTPS+Oxide
  • each film layer of the driving backplane BP is a description of each film layer of the driving backplane BP:
  • the driving backplane BP may include a substrate SU and a circuit layer TL, wherein:
  • the substrate SU may be the base of the driving backplane BP, which may carry pixel circuits and peripheral circuits.
  • the substrate SU may be a hard or flexible structure, and may be a single-layer or multi-layer structure, which is not particularly limited here.
  • the circuit layer TL is disposed on one side of the substrate SU, and may include transistors and capacitors of the driving circuit.
  • the circuit layer TL may include a semiconductor layer POL, a first gate insulating layer GI1, a first gate layer GA1, a second gate insulating layer GI2, a second gate layer GA2, an interlayer dielectric layer ILD, a first source and drain layer SD1, a first planar layer PLN1, a second source and drain layer SD2, and a second planar layer PLN2, which are sequentially stacked in a direction away from the substrate SU, wherein:
  • the semiconductor layer POL may be disposed on one side of the substrate SU and include channels of each transistor, and the material thereof may be polysilicon.
  • the first gate insulating layer GI1 may cover the semiconductor layer POL, and the material of the first gate insulating layer GI1 may be an insulating material such as silicon nitride and silicon oxide.
  • the first gate layer GA1 may be disposed on a surface of the first gate insulating layer GI1 away from the substrate SU, and includes gates of each transistor and a first plate of a capacitor.
  • the second gate insulating layer GI2 may cover the first gate layer GA1 , and the material of the second gate insulating layer GI2 may be insulating materials such as silicon nitride and silicon oxide.
  • the second gate layer GA2 may be disposed on a surface of the second gate insulating layer GI2 away from the substrate SU, and include a second electrode plate of the capacitor, and the second electrode plate overlaps with the first electrode plate to form a capacitor.
  • the interlayer dielectric layer ILD may cover the second gate layer GA2 , and the material of the interlayer dielectric layer ILD may include inorganic insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, etc., which are not particularly limited herein.
  • the first source-drain layer SD1 may be disposed on the surface of the interlayer dielectric layer ILD away from the substrate SU, and may be a single-layer or multi-layer structure, and its material may include one or more metals such as Ti, Al, Mg, Ag, etc.
  • the first source-drain layer SD1 may include a first sublayer, a second sublayer, and a third sublayer stacked in sequence in a direction away from the substrate SU, wherein the first sublayer and the third sublayer may be made of the same metal material, such as Ti, and the second sublayer may be made of a metal material different from that of the first sublayer and the third sublayer, such as Al.
  • the first planar layer PLN1 may be arranged on the side of the first source-drain layer SD1 away from the substrate SU, and its material may be an insulating material such as resin.
  • the circuit layer TL may also include a passivation layer, which may cover the first source-drain layer SD1, and the first planar layer PLN1 may cover the passivation layer.
  • the first planar layer PLN1 may also directly cover the first source-drain layer SD1.
  • the second source-drain layer SD2 may be disposed on a surface of the first planar layer PLN1 away from the substrate SU. It may be a single-layer or multi-layer structure, and its material may include one or more metals such as Ti, Al, Mg, Ag, etc. For example, the second source-drain layer SD2 may be a three-layer structure like the first source-drain layer SD1.
  • the second planar layer PLN2 may cover the second source/drain layer SD2 , and the material of the second planar layer PLN2 may be an insulating material such as resin.
  • the circuit layer TL may include a plurality of routing lines for transmitting signals, including a plurality of power lines VDL and data lines DAL, the power lines VDL may extend along the second direction Y, and at least a portion of any power line VDL may be located within the display area AA.
  • Each power line VDL may be spaced apart along the first direction X, and a column of pixel circuits may be connected to a power line VDL, and a first power signal may be transmitted to the pixel circuit via the power line VDL.
  • At least a portion of any data line DAL may be located within the display area AA.
  • a column of pixel circuits may be connected to a data line DAL, and a data signal may be transmitted to the pixel circuit via the data line DAL, so as to control the brightness of the light emitting device LD.
  • the power line VDL and the data line DAL may be located in the second source and drain layer SD2.
  • the circuit layer TL may further include a power bus located in the peripheral area WA, the power bus is at least partially located in the lead-out area FA, and the portion of the power bus located in the lead-out area FA is located between the display area AA and the binding portion BA, and is connected to the binding portion BA.
  • the power bus may include a first power bus VDM and a second power bus VSM, wherein:
  • the first power bus VDM is at least partially located in the lead-out area FA and between the display area AA and the binding part BA.
  • Each power line VDL is connected to the first power bus VDM, so that a first power signal can be transmitted to each power line VDL through the first power bus VDM.
  • the first power bus VDM can be connected to the binding part BA, and the first power signal is transmitted to the first power bus VDM through the binding part BA.
  • the second power bus VSM is at least partially located in the lead-out area FA, and is located between the display area AA and the binding portion BA, and is connected to the binding portion BA.
  • the second power signal can be transmitted to the second power bus VSM through the binding portion BA.
  • the first power bus VDM and the second power bus VSM may be disposed in the same layer, and both may be located in the first source-drain layer SD1 or the second source-drain layer SD2 .
  • the binding part BA may include a plurality of pads spaced apart along the first direction X, and a pad may be connected to a trace, which may be a first power bus VDM, a second power bus VSM, The first signal line DL, the second signal line GL, etc.
  • the pad can be used to bind with the flexible circuit board, or the pad can also be a pin of a driving chip arranged on the driving backplane BP, and the structure of the binding part BA is not specifically limited here.
  • the first power bus VDM may be completely located in the lead-out area FA, or may extend from the lead-out area FA to the side area SA.
  • the second power bus VSM may extend from at least the side area SA to the lead-out area FA.
  • the second power bus VSM may extend from the top area TA to the lead-out area FA via the side area SA, and be connected to the binding portion BA.
  • the second power bus VSM may be symmetrical about the central axis of the display area AA along the second direction Y.
  • the second power bus VSM is located outside the first power bus VDM, that is, the first power bus VDM is located within the range surrounded by the second power bus VSM.
  • the second power bus VSM may extend from two side areas SA to the lead-out area FA, and be connected to the binding portion BA.
  • the position where the first power bus VDS is connected to the binding portion BA is located between the two positions where the second power bus VSM is connected to the binding portion BA.
  • the circuit layer TL may further include a plurality of first signal lines DL and second signal lines GL, wherein:
  • the first signal line DL is at least partially located in the lead-out area FA, and a first signal line DL can be connected to a data line DAL, and the first signal line DL can be connected to the binding part BA, so as to transmit the data signal to the data line DAL through the binding part BA.
  • the first signal line DL is located between the display area AA and the binding part BA, and the part of any first signal line DL located in the lead-out area FA may include a first segment DL1 extending along the first direction X and a second segment DL2 extending along the second direction Y, one end of the first segment DL1 can be connected to the data line DAL, and the other end can be connected to the second segment DL2, and the second segment DL2 can be connected to the binding part BA.
  • the first signal line DL can be located in the first gate layer GA1 or the second gate layer GA2, so the first power bus VDM and the second power bus VSM can be located on the side of the first signal line DL away from the substrate SU, and can overlap with the first signal line DL.
  • the extension direction of the first segment DL1 and the second segment DL2 of the first signal line DL refers to the direction of the extension trend of the two, and is not limited to being strictly parallel to the straight line and the arrow direction shown in the first direction X and the second direction Y in the figure.
  • the first segment DL1 has a certain angle with the straight line showing the first direction X, but the first segment DL1 still extends from one side of the display panel to the other side along the first direction X.
  • the extension direction of the first segment DL1 in Figures 5 to 8 can still be defined as the first direction X, and the end of the first segment DL1 connected to the second segment LD2 can be inclined toward the binding portion BA.
  • the first segment DL1 can also extend parallel to the straight line shown in the first direction X in the figure.
  • the second signal line GL can be connected to a peripheral circuit.
  • the second signal line GL can be connected to a gate drive circuit and a light-emitting control circuit, and a gate drive circuit and a light-emitting control circuit can be connected to multiple second signal lines GL at the same time, and different second signal lines GL can transmit different signals.
  • Each second signal line GL can at least extend from the side area SA to the lead-out area FA and be connected to the binding part BA.
  • the second signal line GL can be located in the first source-drain layer SD1 or the second source-drain layer SD2, so that each second signal line GL is located on the side of each first signal line DL close to the display area AA.
  • the second signal line GL and the power line can be located in the first source-drain layer SD1.
  • each light emitting device LD may be disposed on one side of the driving backplane BP, for example, the light emitting device LD may be disposed on the surface of the second flat layer PLN2 away from the substrate SU.
  • Each light emitting device LD is located in the display area AA, and the light emitting device LD may be an OLED (organic light emitting diode), or of course, a Micro LED (micrometer light emitting diode) and a Mini LED (sub-millimeter light emitting diode), or a light emitting device such as a QLED (quantum dot diode).
  • the light emitting device LD may include a first electrode ANO, a light emitting layer EL, and a second electrode CAT stacked in a direction away from the driving backplane BP, wherein: the first electrode ANO may be arranged on one side of the driving backplane BP and distributed in an array, for example, the first electrode ANO may be arranged on the surface of the second flat layer PLN2 away from the substrate SU.
  • the first electrode ANO is connected to the pixel circuit.
  • the light emitting layer EL may include a hole injection layer, a hole transport layer, a light emitting material layer, an electron transport layer, and an electron injection layer stacked in a direction away from the driving backplane BP.
  • Each light emitting device LD may share the second electrode CAT, that is, the second electrode CAT may be a continuous whole layer structure.
  • the second electrode CAT may be connected to a second power bus VSD in the peripheral area WA, so that a second power signal may be applied to the second electrode CAT through the second power bus VSD.
  • a pixel definition layer PDL may be provided on the surface where the first electrode ANO is provided, and the pixel definition layer PDL is located in the display area AA, and may be provided with an opening for exposing each first electrode ANO, and the light emitting layer EL is stacked with the first electrode ANO in the opening.
  • the first electrodes ANO are all arranged on the surface of the second planar layer PLN2 away from the substrate SU.
  • the opening of the pixel definition layer PDL may be smaller than the exposed first electrode ANO. Since the light emitting layer EL is a whole layer structure, the light emitting layer EL not only overlaps with the first electrode ANO in the opening, but also covers the pixel definition layer PDL.
  • the light-emitting material layers of different light-emitting devices LD are spaced apart from each other, so that the light-emitting device LD can directly emit monochromatic light, and the light-emitting colors of different light-emitting devices LD can be different, thereby realizing color display.
  • the light-emitting material layers of each light-emitting device LD can also be a continuous whole layer structure, so that the light-emitting colors of each light-emitting device LD are the same, and color display can be realized by cooperating with the filter layer CFL located on the side of the light-emitting device LD away from the driving backplane BP.
  • the display panel may further include a packaging glue FR and a packaging cover plate CG, wherein:
  • the light emitting device LD in the display area AA can be packaged by bonding the packaging cover plate CG and the driving back plate with the packaging glue FR, thereby preventing the light emitting device LD from being corroded by external water and oxygen.
  • the packaging glue FR may be an annular structure, which may surround the display area AA, that is, the packaging glue FR may extend to the top area TA, the side area SA and the lead-out area FA at the same time. At the same time, the packaging glue FR is located on the side of the binding part BA close to the display area AA in the lead-out area FA.
  • the packaging cover plate CG can be a transparent hard material such as glass or acrylic, which can be bonded to the surface of the packaging glue FR away from the substrate SU.
  • the material of the packaging glue FR can be frit glue, which can be mixed with glass powder and solvent, etc., and melted after laser sintering to achieve sealing and bonding.
  • an inert gas can be filled into the space surrounded by the packaging cover plate CG, the driving backplane BP and the packaging glue FR.
  • the number of support pillars PS can be multiple, and the array is distributed on the side of the light-emitting device LD away from the driving backplane BP, and at least part of the support pillars PS is located in the display area AA.
  • the support pillars PS can be directly arranged on the surface of the pixel definition layer PDL away from the substrate SU, and the second electrode CAT covers the support pillars PS and protrudes at the position corresponding to the support pillars PS.
  • the support pillars PS can also be arranged on the surface of the second electrode CAT away from the substrate SU.
  • the packaging cover plate CG can be arranged on the side of the support column PS away from the driving back plate BP.
  • the packaging cover plate CG can be on the second electrode CAT lifted by the support column PS, and can directly contact the support column PS arranged on the surface of the second electrode CAT away from the substrate SU.
  • the circuit layer TL may include a packaging substrate TB, which is disposed in the peripheral area WA and around the display area AA.
  • the packaging substrate TB overlaps with the portion of the power bus located in the lead-out area at most.
  • the packaging glue FR may be disposed on the surface of the packaging substrate TB away from the substrate SU, and may extend along the extension track of the packaging substrate TB, so that the packaging glue FR may be supported by the packaging substrate TB.
  • the packaging substrate TB is a reflective structure, so that the curing degree of the packaging glue FR can be improved by the reflection of the packaging substrate TB, making the packaging glue FR more firm, thereby improving the sealing effect.
  • the package substrate TB is located in the top area TA, the side area SA and the lead-out area FA, and the package substrate TB is located outside the second signal line GL.
  • the package substrate TB may be located in the first gate layer GA1 or the second gate layer GA2.
  • the package substrate TB and the first signal line DL are located in the first gate layer GA1
  • the power line is located in the first source and drain layer SD1, so the power line is located on the side of the package substrate TB away from the substrate SU.
  • the package substrate TB may include a plurality of spaced portions distributed around the display area AA, and is not necessarily a continuous annular structure.
  • at least a portion of the package substrate TB may utilize a local area of the first signal line DL and other routing lines.
  • the package substrate TB may include a substrate body TB1, which is located in the side area SA and the top area TA, and is located on the side of the second signal line GL away from the display area AA, that is, located outside the second signal line GL.
  • a portion of the first signal line DL in the lead-out area FA may serve as a portion of the package substrate TB, that is, the package substrate TB may include the substrate body TB1 and a portion of the first signal line DL.
  • the inventors propose to reduce or eliminate the area where the power line overlaps with the package substrate TB, so that the packaging glue FR is located as much as possible on the surface of the package substrate TB away from the substrate SU.
  • the portion of the power bus located in the lead-out area FA may include a first bus portion and a second bus portion, the first bus portion extending along a first direction X and located between the first signal line DL and the second signal line GL.
  • the second bus portion may extend along a second direction Y, and the second bus portion may connect the first bus portion and the binding portion BA.
  • the second bus overlaps the first segment DL1 of the first signal line DL, and the packaging glue FR may cover the second bus portion.
  • the first bus portion VDM1 of the first power bus VDM and the first bus portion VSM1 of the second bus portion VDM2 may be distributed along the first direction X and located between the display area AA and the first segment DL1 of each first signal line DL.
  • the second bus portion VDM2 of the first power bus VDM and the second bus portion VSM2 of the second power bus VSM may extend along the second direction Y and be connected to the binding portion BA.
  • the second bus section VDM2 and the second bus section VSM2 overlap with the first section DL1, and these first sections DL1 are part of the package substrate TB, that is, the first power bus VDM and the second power bus VSM overlap with the package substrate TB only in the second bus section VSM2 and the second bus section VSM2, while the first bus section VDM1 and the first bus section VSM1 do not overlap with the package substrate TB.
  • the packaging glue FR covers the package substrate TB and the second bus section VSM2 and the second bus section VSM2.
  • both the first power bus VDM and the second power bus VSM overlap with the package substrate TB, so that the overlapping area is reduced, the first power bus VDM and the second power bus VSM directly covered by the packaging glue FR are reduced, and the range of the step difference is reduced, which is conducive to reducing the range of crack generation and improving product yield.
  • the widths of the second bus portion VSM2 and the second bus portion VSM2 in the first direction X can be made no greater than 300 ⁇ m to avoid excessive overlap.
  • the second bus portion VSM2 and the second bus portion VSM2 may be provided with a plurality of first through holes Ho1, and the packaging glue FR may fill the first through holes Ho1, thereby increasing the contact surface between the packaging glue FR and the second bus portion VSM2 and the second bus portion VSM2, and increasing the complexity of the cross-section, which is beneficial to blocking water and oxygen, thereby improving the sealing effect.
  • the power bus and the packaging base TB may not overlap, so that the packaging glue FR is within the packaging base TB away from the surface of the substrate SU, and the power bus is located outside the range covered by the packaging glue FR.
  • the step difference caused by the overlap of the power bus and the packaging glue FR is eliminated, and the risk of cracks is reduced.
  • the packaging substrate TB can include a transfer portion CP in the lead-out area FA, and the power bus is divided into a first bus portion and a second bus portion located on both sides of the transfer portion CP. The first bus portion and the second bus portion can be connected through the transfer portion CP, so that the packaging substrate TB does not overlap with the power bus, thereby eliminating the step difference in the packaging glue FR.
  • the first segment DL1 of each first signal line DL is located between the power bus and the binding portion BA, the first bus portion is at least partially located on the side of the adapter CP close to the display area AA; the second bus portion is at least partially located on the side of the adapter CP away from the display area AA, and is connected to the binding portion BA.
  • the first bus portion and the second bus portion are located on the surface of the adapter CP away from the substrate SU, and the first bus portion and the second bus portion are both connected to the adapter.
  • the packaging glue FR covers the adapter CP, and the adapter CP is part of the packaging base TB, so that the packaging glue FR does not need to cover the power line.
  • the transfer portion CP is located on a side of the first signal line DL away from the display area AA.
  • the transfer portion CP and at least a portion of the first signal line DL are distributed along the first direction X, and the portion of the first signal line DL serves as a part of the package substrate TB.
  • the first bus portion of the power bus includes a side of the transfer portion CP close to the display area AA, the second bus portion is located between the transfer portion CP and the binding portion BA, and is connected to the binding portion BA, and the first bus portion and the second bus portion are connected through the transfer portion CP.
  • the transfer portion CP may include a first transfer portion CP1 and a second transfer portion CP2 spaced apart along the first direction X.
  • the power bus may include a first power bus VDM and a second power bus VSM.
  • the first bus portion VDM1 and the second bus portion VDM2 of the first power bus VDM are connected through the first transfer portion CP1.
  • the first signal line DL in the lead-out area FA includes two signal line groups DLC symmetrically distributed about the central axis of the binding portion BA along the second direction Y, the first transfer portion CP1 is located between the two signal line groups DLC, and the first bus portion VDM1 and the second bus portion VDM2 of the first power bus VDM are connected through the first transfer portion CP1.
  • the second transfer portion CP2 and the base body TB1 located in the side area SA can be an integrated structure, that is, the second transfer portion CP2 can be the portion of the base body TB1 in the side area SA extending to the lead-out area FA, and the first bus portion VSM1 and the second bus portion VSM2 of the second power bus VSM are connected through the second transfer portion CP2.
  • the package substrate TB may include a substrate body TB1 located in the side area SA and the top area TA, at least a portion of the first segment DL1 of at least part of the first signal line DL, and at least a portion of the second segment DL2.
  • the first segment DL1 of each first signal line DL is located between the transfer portion CP and the display area AA, the transfer portion CP is located between the first segment DL1 and the binding portion BA, and the second segment DL2 of the first signal line DL and the transfer portion CP are distributed along the first direction X.
  • Each first signal line DL is divided into two signal line groups DLC that are symmetrically distributed about the central axis of the binding portion BA along the second direction Y; the transfer portion CP is located outside the two signal line groups DLC.
  • the package substrate TB may include a substrate body TB1 located in the side area SA and the top area TA and at least a partial region of each second segment DL2 .
  • the transfer portion CP may include a first transfer portion CP1 and a second transfer portion CP2 spaced apart along the first direction X, the second transfer portion CP2 is located between the side area SA and the first transfer portion CP1, and the first transfer portion CP1, the second transfer portion CP2 and the second segment DL2 of the first signal line DL are distributed along the first direction X.
  • the first segment DL1 of the first signal line DL is located between the transfer portion CP and the display area AA.
  • the power bus may include a first power bus VDM and a second power bus VSM, wherein a first bus portion VDM1 of the first power bus VDM is connected to a second bus portion VDM2 via a first adapter portion CP1; a first bus portion VSM1 of the second power bus VSM is connected to a second bus portion VSM2 via a second adapter portion CP2. Both the second bus portion VDM2 and the second bus portion VSM2 are connected to a binding portion BA.
  • the packaging substrate TB may further include a first dummy portion DU1, which may be arranged between the first adapter portion CP1 and the second adapter portion CP2 at intervals along the first direction X, and the packaging glue FR may cover the first dummy portion DU1.
  • the first dummy portion DU1 is floating, that is, it is not connected to any electrical signal.
  • the first dummy portion DU1 may fill the space between the first adapter portion CP1 and the second adapter portion CP2, so that the packaging glue FR is smoother, further improving the uniformity of the packaging glue FR, and increasing the area of the bonding surface between the packaging glue FR and the packaging substrate TB, thereby improving the barrier effect against water and oxygen.
  • the number of the first dummy portion DU1 may be multiple, and may be spaced along the first direction X, and the first dummy portion DU1 may extend along the second direction Y.
  • the circuit layer TL may further include a test line CT, which is at least partially disposed in the lead-out area FA and connected to the binding portion BA.
  • the test line CT may overlap with the second bus portion VDM2 and the second bus portion VSM2, and the test line CT may be located in the first gate layer GA1 or the second gate layer GA2.
  • At least a part of the second segment DL2 of at least a part of the first signal line DL belongs to the packaging substrate TB, and a second dummy portion DU2 may be provided between two adjacent second segments DL2, and the packaging glue FR may cover each second dummy portion DU2.
  • the second dummy portion DU2 may fill the space between two adjacent second segments DL2, making the packaging glue FR smoother, further improving the uniformity of the packaging glue FR, and increasing the area of the bonding surface between the packaging glue FR and the packaging substrate TB, thereby improving the barrier effect against water and oxygen.
  • the number of the second dummy parts DU2 may be plural, and a second dummy part DU2 is disposed between two adjacent second segments DL2 .
  • the second dummy parts DU2 may be distributed along the first direction X at intervals and extend along the second direction Y.
  • the first dummy portion DU1 is a linear structure with the same width as the second segment DL2 of the first signal line DL, one or more second dummy portions DU2 are arranged between two adjacent second segments DL2, and the spacing between two adjacent second dummy portions DU2 and one adjacent second dummy DU2 and the second segment DL1 is the same.
  • first dummy portions DU1 can be arranged between the first transfer portion CP1 and the second transfer portion CP2, and the spacing between the first dummy portions DU1 here is equal to the spacing between the second dummy portions DU2 between the second segments DL2, so that the overall density of the first dummy portion DU1, the second dummy portion DU2 and the second segment DL2 in the packaging substrate TB is consistent, which is conducive to improving the uniformity within the coverage range of the packaging glue FR.
  • At least a portion of the second segment DL2 belonging to the packaging substrate TB may extend along a bending track, thereby increasing the bonding surface area between the packaging glue FR and the packaging substrate TB and improving the barrier effect against water and oxygen.
  • At least part of the second segment DL2 belonging to the package substrate TB may include a first bending portion WP1 and a second bending portion WP2 that are bent in opposite directions in the first direction X, and the first bending portion WP1 and the second bending portion WP2 may be alternately distributed along the second direction Y.
  • the shapes of the first bending portion WP1 and the second bending portion WP2 may be an open polygon, such as a rectangle, or, of course, may be a curved shape such as an arc.
  • the package substrate TB A second through hole Ho2 is provided in a partial area of the package.
  • the second through hole Ho2 can be filled with a filling layer FL.
  • the filling layer FL is provided with a plurality of third through holes Ho3.
  • the packaging glue FR fills each third through hole Ho3 to increase the bonding surface area of the packaging glue FR and the packaging substrate TB, thereby improving the barrier effect against water and oxygen.
  • the package substrate TB is located in the first gate layer GA1 or the second gate layer GA2, that is, it is disposed in the same layer as the first gate layer GA1 or the second gate layer GA2.
  • the filling layer FL can be formed simultaneously with the interlayer dielectric layer ILD, that is, they are disposed in the same layer.
  • the distance may be greater than 30 ⁇ m.
  • a second through hole Ho2 is provided in a partial area of the packaging substrate TB, and a plurality of filling portions FL1 may be filled in the second through hole Ho2.
  • the filling portions FL1 are distributed in an array in the second through hole Ho2.
  • the packaging glue FR is filled in the second through hole Ho2 and covers each filling portion FL1, so that the contact surface with the packaging glue FR can be increased through the second through hole Ho2 and the filling portion FL1, thereby improving the barrier effect against water and oxygen.
  • the present disclosure also provides a display device, which may include a display panel of any of the above embodiments.
  • the display panel is a display panel of any of the above embodiments, and its specific structure and beneficial effects can be referred to the embodiments of the display panel above, which will not be repeated here.
  • the display device disclosed in the present invention can be a mobile phone, a smart watch, a smart bracelet, a tablet computer, a television, or other electronic device with a display function, which will not be listed one by one here.

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  • Microelectronics & Electronic Packaging (AREA)
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Abstract

一种显示面板及显示装置，涉及显示技术领域。显示面板包括显示区（AA）和包括引出区（FA）的外围区（WA），引出区（FA）包括绑定部（BA）；显示面板包括驱动背板（BP）、发光器件（LD）、封装胶（FR）和封装盖板（CG），驱动背板（BP）包括衬底（SU）和电路层（TL），电路层（TL）包括沿远离衬底（SU）的方向分布的封装基底（TB）和电源总线，封装基底（TB）设于外围区（WA）且围绕显示区（AA）设置；电源总线至少部分位于引出区（FA），电源总线位于引出区（FA）的部分位于显示区（AA）和绑定部（BA）之间，且与绑定部（BA）连接；封装基底（TB）至多与电源总线位于引出区（FA）的部分交叠；封装基底（TB）为反光结构。发光器件（LD）设于电路层（TL）远离衬底（SU）的一侧，且位于显示区（AA）。封装胶（FR）至少部分设于封装基底（TB）远离衬底（SU）的表面，且沿封装基底（TB）的延伸轨迹围绕于显示区（AA）外。封装盖板（CG）设于封装胶（FR）远离衬底（SU）的表面。

Description

显示面板及显示装置
交叉引用
本公开要求于2022年12月01日提交的申请号为202211539087.0名称为“显示面板及显示装置”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示面板及显示装置。
背景技术
显示面板是手机等电子设备不可或缺的部分，其中，采用有机发光二极管作为发光器件的有机电致发光显示面板(OLED)的应用较为广泛，现有技术中，为了防止外界水氧对发光器件造成侵蚀，需要对发光器件进行封装，但是现有封装方式的封装效果有待提高。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开提供一种显示面板及显示装置。
根据本公开的一个方面，提供一种显示面板，包括显示区和所述显示区外的外围区，所述外围区包括引出区，所述引出区包括绑定部；所述显示面板包括：
驱动背板，包括衬底和设于所述衬底一侧的电路层，所述电路层包括沿远离所述衬底的方向分布的封装基底和电源总线，所述封装基底设于所述外围区且围绕所述显示区设置；所述电源总线至少部分位于所述引出区，所述电源总线位于所述引出区的部分位于所述显示区和所述绑定部之间，且与所述绑定部连接；所述封装基底至多与所述电源总线位 于所述引出区的部分交叠；所述封装基底为反光结构；
发光器件，设于所述电路层远离所述衬底的一侧，且位于所述显示区；
封装胶，至少部分设于所述封装基底远离所述衬底的表面，且沿所述封装基底的延伸轨迹围绕于所述显示区外；
封装盖板，设于所述封装胶远离所述衬底的表面。
在本公开的一种示例性实施方式中，所述封装基底在所述引出区的部分包括转接部；
所述电源总线包括第一总线部和第二总线部，所述第一总线部至少部分位于所述转接部靠近所述显示区的一侧；所述第二总线至少部分部位于所述转接部远离所述显示区的一侧，且与所述绑定部连接；所述第一总线部和所述第二总线部均与所述转接部连接。
在本公开的一种示例性实施方式中，所述转接部包括沿第一方向间隔分布的第一转接部和第二转接部；
所述电源总线包括第一电源总线和第二电源总线，所述第一电源总线的第一总线部和第二总线部通过所述第一转接部连接；所述第二电源总线的第一总线部和第二总线部通过第二转接部连接。
在本公开的一种示例性实施方式中，所述电路层还包括多个第一信号线，所述第一信号线至少部分位于所述引出区，且位于所述显示区和所述绑定部之间；所述第一信号线位于所述引出区的部分包括沿所述第一方向延伸的第一段和沿第二方向延伸的第二段，所述第二段连接所述第一段和所述绑定部。
在本公开的一种示例性实施方式中，所述外围区还包括沿所述第一方向分布于所述显示区两侧的侧边区和分布于所述显示区远离所述引出区的一侧的顶部区；
所述封装基底包括位于所述侧边区和所述顶部区的基底主体、所述第一段的至少部分区域以及所述第二段的至少部分区域；
各所述第一信号线包括关于所述绑定部沿所述第二方向的中轴线对称分布的两个信号线组；所述第一转接部位于两个所述信号线组之间。
在本公开的一种示例性实施方式中，所述外围区还包括沿所述第一 方向分布于所述显示区两侧的侧边区和沿所述第二方向分布于所述显示区远离所述引出区的一侧的顶部区；
所述第一段位于所述转接部和所述显示区之间，所述第二段与所述转接部沿所述第一方向分布；
所述封装基底包括位于所述侧边区和所述顶部区的基底主体和各所述第二段的至少部分区域；
各所述第一信号线分为关于所述绑定部沿第二方向的中轴线对称分布的两个信号线组；所述转接部位于两个所述信号线组外侧。
在本公开的一种示例性实施方式中，所述封装基底还包括第一虚设部，所述第一虚设部沿所述第一方向间隔设于所述第一转接部和所述第二转接部之间；所述封装胶覆盖所述第一虚设部。
在本公开的一种示例性实施方式中，属于所述封装基底的所述第二段之间设有第二虚设部，所述封装胶覆盖所述第二虚设部。
在本公开的一种示例性实施方式中，所述第一虚设部和所述第二虚设部均沿所述第二方向延伸。
在本公开的一种示例性实施方式中，属于所述封装基底的至少部分所述第二段沿弯折轨迹延伸。
在本公开的一种示例性实施方式中，属于所述封装基底的至少部分所述第二段包括在第一方向上反向弯折的第一弯折部和第二弯折部，所述第一弯折部和所述第二弯折部沿第二方向交替分布。
在本公开的一种示例性实施方式中，所述电路层还包括多个第一信号线，所述第一信号线至少部分位于所述引出区，且位于所述显示区和所述绑定部之间；所述第一信号线位于所述引出区的部分包括沿第一方向延伸的第一段和沿第二方向延伸的第二段，所述第二段连接所述第一段和所述绑定部；
所述电源总线位于所述引出区的部分包括沿所述第一方向延伸的第一总线部和沿所述第二方向延伸的第二总线部，所述第二总线部连接所述第一总线部和所述绑定部；所述第一总线部位于所述第一信号线和所述显示区之间；所述第二总线部与所述第一段交叠，所述封装胶覆盖所述第二总线部。
在本公开的一种示例性实施方式中，所述第二总线部设有多个第一通孔，所述封装胶填充所述第一通孔。
在本公开的一种示例性实施方式中，所述第二总线部在所述第一方向上的宽度不大于300μm。
在本公开的一种示例性实施方式中，所述封装基底的部分区域设有第二通孔。
在本公开的一种示例性实施方式中，所述第二通孔内填充有填充层，且所述填充层设有多个第三通孔；所述封装胶填充各所述第三通孔。
在本公开的一种示例性实施方式中，所述电路层包括沿远离所述衬底的方向依次分布的第一栅极层、第一栅绝缘层、第二栅极层、层间介质层、第一源漏层、第一平坦层、第二源漏层和第二平坦层；所述发光器件设于所述第二平坦层远离所述衬底的表面；
所述封装基底位于所述第一栅极层或所述第二栅极层，所述电源总线位于所述第一源漏层或所述第二源漏层。
根据本公开的一个方面，提供一种显示装置，包括上述任意一项所述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开显示面板一实施方式的俯视图。
图2为本公开显示面板一实施方式的走线的示意图。
图3为本公开显示面板一实施方式的截面示意图。
图4为本公开显示面板一实施方式中显示区的局部截面示意图。
图5为本公开显示面板的第一种实施方式的截面示意图。
图6为图5的局部示意图。
图7为本公开显示面板的第二种实施方式的截面示意图。
图8为本公开显示面板的第三种实施方式的截面示意图。
图9为本公开显示面板一实施方式中封装基底的局部俯视图。
图10为本公开显示面板一实施方式中基底主体的局部俯视图。
图11为本公开显示面板另一实施方式中封装基底的局部俯视图。
图12为本公开显示面板一实施方式中引出区的局部俯视图。
图13为本公开显示面板再一实施方式中封装基底的局部俯视图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
本文中的第一方向X和第二方向Y仅为两个相互垂直或以其它角度交叉的方向，在本公开的附图中，第一方向X可以是横向，第二方向Y可以是纵向，但并不限于此，若显示面板发生旋转，则第一方向X和第二方向Y的实际朝向可能发生变化。
本文中的A特征和B特征“交叠”是指A特征在衬底上的正投影和B特征在衬底上的正投影至少部分重合。
本公开实施方式提供了一种显示面板，如图1-图3所示，该显示面板包括显示区AA和显示区AA外的外围区WA，外围区WA包括引出区FA，引出区FA包括绑定部BA；显示面板包括：
驱动背板BP包括衬底SU和设于衬底SU一侧的电路层TL，电路层TL包括沿远离衬底SU的方向分布的封装基底TB和电源总线，封装基底TB设于外围区WA且至少部分围绕显示区AA设置；电源总线至少部分位于引出区FA，且电源总线位于引出区FA的部分位于显示区AA和绑定部BA之间，且与绑定部BA连接；封装基底TB至多与电源总线位于引出区FA的部分交叠；封装基底TB为反光结构；
发光器件LD设于电路层TL远离衬底SU的一侧，且位于显示区AA；
封装胶FR至少部分设于封装基底TB远离衬底SU的表面，且至少部分沿封装基底TB的延伸轨迹围绕于显示区AA外；
封装盖板CG设于封装胶FR远离衬底SU的表面。
本公开实施方式的显示面板，可通过封装盖板CG对发光器件LD进行覆盖，且通过封装胶FR进行密封，对发光器件LD进行保护。同时，由于在外围区WA设置了发光的封装基底TB，而封装胶FR设置在封装基底TB上，可增强对封装胶FR的光照强度，提高封装胶FR的固化程度，使封装盖板TB和驱动背板BP的连接更加紧密、牢固，从而提高封装效果。此外，通过封装基底TB对封装胶FR进行承载，有利于提升使封装胶FR所处的表面的平坦化程度，降低因封装胶FR覆盖的区域存在段差较大的台阶时，在落球试验中发生出现裂纹的风险，从而提高产品良率。
下面对本公开显示面板进行详细说明：
如图1所示，显示面板的显示区AA为可发光的区域，用于显示图像。外围区WA位于显示区AA外，外围区WA可以是围绕显示区AA的连续或间断的环形区域，或者，也可以是“U”形等半封闭的区域，在此不对外围区WA的形状做特殊限定。外围区WA可包括引出区FA，引出区FA具有绑定部BA。绑定部BA可与一柔性电路板连接，该柔性电路板可与控制电路板连接，控制电路板可通过柔性电路板向绑定部BA传输信号。
如图1和图2所示，在本公开的一些实施方式中，外围区WA可划分为多个区域，其中包括围绕于显示区AA外的引出区FA，两个侧边区 SA和顶部区TA，两个侧边区SA可沿第一方向X分布于显示区AA两侧，且可以关于显示区AA沿第二方向Y的中轴线对称设置。顶部区TA和引出区FA可沿第二方向Y分布于显示区AA的两侧，即顶部区TA位于显示区AA远离引出区的一侧。引出区FA，两个侧边区SA和顶部区TA可连接成一围绕显示区AA的环形的外围区WA。
上述的显示区AA和外围区WA是根据其功能进行的划分，而并非限定显示面板中存在用于实现分区的实体的边界。
如图2-图4所示，驱动背板BP具有用于驱动发光器件LD发光的驱动电路。驱动电路可包括位于显示区AA的像素电路和位于外围区WA的外围电路，其中：
像素电路的数量为多个，且沿第一方向X和第二方向Y阵列分布成多行和多列，一像素电路可连接一个发光器件LD，当然，也可以存在一个像素电路连接多个发光器件LD的情况，本文仅以像素电路和发光器件LD一一对应地连接为例进行说明。
像素电路可包括多个晶体管和电容，其可以是3T1C、7T1C、8T1C等像素电路，nTmC表示一个像素电路包括n个晶体管(用字母“T”表示)和m个电容(用字母“C”表示)。
外围电路可与像素电路和发光器件LD连接，并可通过像素电路控制通过发光器件LD的电流，从而控制发光器件LD的亮度。外围电路可包括多个晶体管和电容，且其可包括栅极驱动电路和发光控制电路等，当然，还可包括其它电路，在此不对外围电路的具体结构做特殊限定。
上述的像素电路可采用LTPS(低温多晶硅)技术，即像素电路的各晶体管均为低温多晶硅晶体管。当然，也可以采用LTPO(LTPS+Oxide)在此不做特殊限定。
下面对驱动背板BP的各膜层进行示例性说明：
如图3和图4所示，驱动背板BP可包括衬底SU和电路层TL，其中：
衬底SU可为驱动背板BP的基底，其可承载像素电路和外围电路，衬底SU可为硬质或柔性结构，其可以是单层或多层结构，在此不做特殊限定。
电路层TL设于衬底SU一侧，其可包括驱动电路的各晶体管和电容。
如图4所示，在本公开的一些实施方式中，电路层TL可包括沿远离衬底SU的方向依次堆叠的半导体层POL、第一栅绝缘层GI1、第一栅极层GA1、第二栅绝缘层GI2、第二栅极层GA2和层间介质层ILD、第一源漏层SD1、第一平坦层PLN1、第二源漏层SD2和第二平坦层PLN2，其中：
半导体层POL可设于衬底SU一侧，且包括各晶体管的沟道，其材料可以是多晶硅。
第一栅绝缘层GI1可覆盖半导体层POL，第一栅绝缘层GI1的材料可以是氮化硅、氧化硅等绝缘材料。
第一栅极层GA1可设于第一栅绝缘层GI1远离衬底SU的表面，且包括各晶体管的栅极和电容的第一极板。
第二栅绝缘层GI2可覆盖第一栅极层GA1，其材料可以是氮化硅、氧化硅等绝缘材料。
第二栅极层GA2可设于第二栅绝缘层GI2远离衬底SU的表面，且包括电容的第二极板，第二极板与第一极板交叠，形成电容。
层间介质层ILD可覆盖第二栅极层GA2，层间介质层ILD的材料可以包括氮化硅、氧化硅、氮氧化硅等无机绝缘材料等，在此不做特殊限定。
第一源漏层SD1可设于层间介质层ILD远离衬底SU的表面，其可以是单层或多层结构，且其材料可包括Ti、Al、Mg、Ag等金属中的一种或多种。举例而言，第一源漏层SD1可包括沿远离衬底SU的方向依次堆叠的第一子层、第二子层和第三子层，其中，第一子层和第三子层可采用相同的金属材料，例如，Ti，第二子层可采用与第一子层和第三子层的材料不同的金属材料，例如Al。
第一平坦层PLN1可设于第一源漏层SD1远离衬底SU的一侧，其材料可以是树脂等绝缘材料。此外，电路层TL还可包括钝化层，其可覆盖第一源漏层SD1，第一平坦层PLN1可覆盖钝化层，当然，第一平坦层PLN1也可以直接覆盖第一源漏层SD1。
第二源漏层SD2可设于第一平坦层PLN1远离衬底SU的表面，其 可以是单层或多层结构，且其材料可包括Ti、Al、Mg、Ag等金属中的一种或多种。例如，第二源漏层SD2可以是与第一源漏层SD1相同的三层结构。
第二平坦层PLN2可覆盖第二源漏层SD2，其材料可以是树脂等绝缘材料。
如图2所示，电路层TL可包括多个走线，以便传输信号，包括多个电源线VDL和数据线DAL，电源线VDL可沿第二方向Y延伸，任一电源线VDL的至少部分位于显示区AA内。各电源线VDL可沿第一方向X间隔分布，且一列像素电路可与一电源线VDL连接，可通过电源线VDL向像素电路传输第一电源信号。任一数据线DAL至少部分位于显示区AA内。一列像素电路可与一数据线DAL连接，可通过数据线DAL向像素电路传输数据信号，以便控制发光器件LD的亮度。举例而言，电源线VDL和数据线DAL可位于第二源漏层SD2。
如图2所示，电路层TL还可包括位于外围区WA的电源总线，电源总线至少部分位于引出区FA，且电源总线位于引出区FA的部分位于显示区AA和绑定部BA之间，且与绑定部BA连接。电源总线可包括第一电源总线VDM和第二电源总线VSM，其中：
第一电源总线VDM至少部分位于引出区FA，且位于显示区AA和绑定部BA之间，各电源线VDL均与第一电源总线VDM连接，从而可通过第一电源总线VDM向各电源线VDL传输第一电源信号。同时，为了便于向第一电源总线VDM输入第一电源信号，可将第一电源总线VDM与绑定部BA连接，通过绑定部BA向第一电源总线VDM传输第一电源信号。
第二电源总线VSM至少部分位于引出区FA，且位于显示区AA和绑定部BA之间，并与绑定部BA连接，通过绑定部BA可向第二电源总线VSM传输第二电源信号。
第一电源总线VDM和第二电源总线VSM可同层设置，二者可位于第一源漏层SD1或第二源漏层SD2。
绑定部BA可包括多个沿第一方向X间隔分布的焊盘，一焊盘可与一走线连接，该走线可以是第一电源总线VDM、第二电源总线VSM、 第一信号线DL、第二信号线GL等。该焊盘可用于与柔性电路板绑定，1，或者，该焊盘也可以是一设于驱动背板BP上的驱动芯片的引脚，在此不对绑定部BA的结构做特殊限定。
如图2所示，在本公开的一些实施方式中，第一电源总线VDM可完全位于引出区FA，也可以从引出区FA延伸至侧边区SA。第二电源总线VSM可至少由侧边区SA延伸至引出区FA，例如，第二电源总线VSM可从顶部区TA经侧边区SA延伸至引出区FA，且与绑定部BA连接。第二电源总线VSM可以关于显示区AA沿第二方向Y的中轴线对称。第二电源总线VSM位于第一电源总线VDM的外侧，即第一电源总线VDM位于第二电源总线VSM围绕的范围内。第二电源总线VSM可从两个侧边区SA延伸至引出区FA，并与绑定部BA连接，第一电源总线VDS与绑定部BA连接的位置位于第二电源总线VSM与绑定部BA连接的两个位置之间。
此外，如图2所示，电路层TL还可包括多个第一信号线DL和第二信号线GL，其中：
第一信号线DL至少部分位于引出区FA内，且一第一信号线DL可与一数据线DAL连接，且第一信号线DL可与绑定部BA连接，以便通过绑定部BA向数据线DAL传输数据信号。第一信号线DL位于显示区AA和绑定部BA之间，且任一第一信号线DL位于引出区FA的部分可包括沿第一方向X延伸的第一段DL1和沿第二方向Y延伸的第二段DL2，第一段DL1的一端可与数据线DAL连接，另一端可与第二段DL2连接，第二段DL2可与绑定部BA连接。第一信号线DL可为位于第一栅极层GA1或第二栅极层GA2，因此，第一电源总线VDM和第二电源总线VSM可位于第一信号线DL远离衬底SU的一侧，且可以与第一信号线DL交叠。
需要说明的是，第一信号线DL的第一段DL1和第二段DL2的延伸方向指的是二者延伸的趋势的朝向，而不限定为严格的平行与图中的第一方向X和第二方向Y示出的直线及箭头的方向，例如，在图8中，第一段DL1与示出第一方向X的直线存在一定的夹角，但第一段DL1仍然是沿第一方向X从显示面板的一侧向另一侧延伸，因此，在本公开的 实施方式中，图5-图8中的第一段DL1延伸方向仍然可以定义为第一方向X，第一段DL1与第二段LD2连接的一端可朝绑定部BA偏斜。当然，第一段DL1也可以平行于图中示出第一方向X的直线延伸。
如图2所示，第二信号线GL可与外围电路连接，例如，第二信号线GL可与栅极驱动电路和发光控制电路连接，且一栅极驱动电路和发光控制电路可同时与多个第二信号线GL连接，不同的第二信号线GL可传输不同的信号。各个第二信号线GL其至少可从侧边区SA延伸至引出区FA，并与绑定部BA连接。第二信号线GL可位于第一源漏层SD1或第二源漏层SD2，使得各第二信号线GL位于各第一信号线DL靠近显示区AA的一侧。例如，第二信号线GL可与电源线都位于第一源漏层SD1。
如图4所示，各发光器件LD可设于驱动背板BP一侧，例如，发光器件LD可设于的第二平坦层PLN2远离衬底SU的表面。各发光器件LD位于显示区AA内，同时，发光器件LD可以是OLED(有机发光二极管)，当然，也可以是Micro LED(微米发光二极管)和Mini LED(次毫米发光二极管)，还可以是QLED(量子点二极管)等发光器件。
举例而言，发光器件LD可包括沿远离驱动背板BP的方向堆叠的第一电极ANO、发光层EL和第二电极CAT，其中：第一电极ANO可设于驱动背板BP一侧，且阵列分布，例如，第一电极ANO可设于第二平坦层PLN2远离衬底SU的表面。第一电极ANO与像素电路连接。发光层EL可包括沿远离驱动背板BP的方向层叠的空穴注入层、空穴传输层、发光材料层、电子传输层和电子注入层。各个发光器件LD可共用第二电极CAT，也就是说，第二电极CAT可以是连续的整层结构。
第二电极CAT可与外围区WA内的第二电源总线VSD连接，从而可通过第二电源总线VSD向第二电极CAT施加第二电源信号。
此外，如图3和图4所示，为了限定发光器件LD的发光范围，防止串扰，可在设置第一电极ANO的表面设置像素定义层PDL，且像素定义层PDL位于显示区AA内，其可设有露出各第一电极ANO的开口，发光层EL在开口内与第一电极ANO层叠。例如，像素定义层PDL和 第一电极ANO均设于第二平坦层PLN2远离衬底SU的表面。像素定义层PDL的开口可小于其露出的第一电极ANO。由于发光层EL为整层结构，因而，发光层EL除了在开口内与第一电极ANO堆叠，还覆盖像素定义层PDL。
不同发光器件LD的发光材料层是相互间隔的，使得发光器件LD可以直接发出单色光，且不同发光器件LD的发光颜色可以不同，从而实现彩色显示。当然，各发光器件LD的发光材料层也可以是连续的整层结构，使得各发光器件LD的发光颜色相同，配合位于发光器件LD远离驱动背板BP的一侧的滤光层CFL可实现彩色显示。
如图3和图4所示，显示面板还可以包括封装胶FR和封装盖板CG，其中：
可通过封装胶FR对封装盖板CG和驱动背板的粘接实现对显示区AA内的发光器件LD的封装，阻挡外界的水、氧对发光器件LD的侵蚀。
封装胶FR可为环形结构，其可围绕于显示区AA外，也就是说，封装胶FR可同时延伸至顶部区TA、侧边区SA和引出区FA。同时，封装胶FR在引出区FA内位于绑定部BA靠近显示区AA的一侧。
封装盖板CG可为玻璃或亚克力等透明的硬质材料，其可粘接于封装胶FR远离衬底SU的表面。封装胶FR的材料可采用frit胶，其可由玻璃粉和溶剂等混合而成，并经过激光烧结后熔融，实现密封粘接。此外，还可向封装盖板CG、驱动背板BP和封装胶FR围成的空间内充入惰性气体。
此外，为了支撑封装盖板CG，支撑柱PS的数量可为多个，且阵列分布于发光器件LD远离驱动背板BP的一侧，且至少部分支撑柱PS位于显示区AA。支撑柱PS可直接设置在像素定义层PDL远离衬底SU的表面，第二电极CAT覆盖支撑柱PS，且在对应于支撑柱PS的位置凸起。当然，支撑柱PS也可以设置在第二电极CAT远离衬底SU的表面。
封装盖板CG可设于支撑柱PS远离驱动背板BP的一侧，例如，封装盖板CG可与被支撑柱PS顶起的第二电极CAT上，且可以直接与设置在第二电极CAT远离衬底SU的表面的支撑柱PS直接接触。
如图2所示，为了提高封装效果，电路层TL可包括封装基底TB，封装基底TB设于外围区WA且围绕显示区AA设置。封装基底TB至多与电源总线位于引出区的部分交叠。封装胶FR可设于封装基底TB远离衬底SU的表面，且可沿封装基底TB的延伸轨迹延伸，从而可利用封装基底TB支撑封装胶FR。同时，封装基底TB为反光结构，从而可通过封装基底TB的反光提高封装胶FR的固化程度，使封装胶FR更加牢固，从而提高密封效果。
如图2所示，封装基底TB位于顶部区TA、侧边区SA和引出区FA，且封装基底TB位于第二信号线GL外。封装基底TB可位于第一栅极层GA1或第二栅极层GA2，例如，封装基底TB和第一信号线DL位于第一栅极层GA1，电源线位于第一源漏层SD1，因而电源线位于封装基底TB远离衬底SU的一侧。同时，封装基底TB可以包括围绕显示区AA分布的多个间隔的部分，而不一定是连续的环形结构。同时，封装基底TB中至少一部分可利用第一信号线DL等走线的局部区域。
封装基底TB可包括基底主体TB1，基底主体TB1位于侧边区SA和顶部区TA内，且位于第二信号线GL远离显示区AA的一侧，即位于第二信号线GL外侧。第一信号线DL在引出区FA内的部分区域可作为封装基底TB的一部分，也就是说，封装基底TB可包括基底主体TB1和第一信号线DL的一部分。
发明人发现，若电源线与封装基底TB在引出区FA内交叠，且封装胶FR除了覆盖封装基底TB未与电源线交叠的部分，还覆盖电源线与封装基底TB交叠的部分，相较于未与电源线交叠的封装基底TB，与封装基底TB交叠的电源总线与未与电源总线交叠的封装基底TB存在高度差，即存在段差，使得封装胶FR存在爬坡和落差，在进行落球试验时，容易因前述落差的存在而受力不均，从而发生裂纹，导致试验失败，良品率有待提高。为此，发明人提出，减小或消除电源线与封装基底TB交叠的区域，使得封装胶FR尽可能多的位于封装基底TB远离衬底SU的表面。
下面结合封装基底TB的结构和分布方式进行示例性说明：
如图5和图6所示，在本公开的第一种实施方式中，电源总线位于引出区FA的部分可包括第一总线部和第二总线部，第一总线部沿第一方向X延伸，且位于第一信号线DL和第二信号线GL之间。第二总线部可沿第二方向Y延伸，且第二总线部可连接第一总线部和绑定部BA。第二总线与第一信号线DL的第一段DL1交叠，封装胶FR可覆盖第二总线部。
如图5和图6所示，在一实施方式中，第一电源总线VDM的第一总线部VDM1和第二总线部VDM2的第一总线部VSM1可沿第一方向X分布，且位于显示区AA和各第一信号线DL的第一段DL1之间。第一电源总线VDM的第二总线部VDM2和第二电源总线VSM的第二总线部VSM2可沿第二方向Y延伸，并与绑定部BA连接。
第二总线部VDM2和第二总线部VSM2与第一段DL1交叠，这些第一段DL1为封装基底TB的一部分，也就是说，第一电源总线VDM和第二电源总线VSM的仅在第二总线部VSM2和第二总线部VSM2与封装基底TB交叠，而第一总线部VDM1和第一总线部VSM1则不与封装基底TB交叠。封装胶FR覆盖封装基底TB以及第二总线部VSM2和第二总线部VSM2。通过对电源线的结构的设计，避免第一电源总线VDM和第二电源总线VSM都与封装基底TB交叠，使交叠的区域减小，减少封装胶FR直接覆盖的第一电源总线VDM和第二电源总线VSM，减少存在段差的范围，有利于缩小裂纹产生的范围，提高产品良率。
进一步的，可使第二总线部VSM2和第二总线部VSM2在第一方向X上的宽度不大于300μm，避免交叠范围过大。
进一步的，如图5和图6所示，第二总线部VSM2和第二总线部VSM2可设有多个第一通孔Ho1，封装胶FR可填充第一通孔Ho1，从而提高封装胶FR与第二总线部VSM2和第二总线部VSM2的接触面，且增大截面的复杂程度，有利于阻隔水、氧，从而提高密封效果。
如图7和图8所示，在本公开的其它实施方式中，在引出区FA内，还可以使电源总线与封装基底TB不交叠，使得封装胶FR范围于封装基底TB远离衬底SU的表面，电源总线位于封装胶FR覆盖的范围外，从 而消除因为电源总线和封装胶FR交叠而存在的段差，降低出现裂纹的风险。其中，可使封装基底TB在引出区FA的部分包括转接部CP，将电源总线分为位于转接部CP两侧的第一总线部和第二总线部，第一总线部和第二总线部可通过转接部CP连接，使得封装基底TB不与电源总线交叠，从而消除封装胶FR内的段差。
下面进行示例性说明：
如图7所示，在本公开的第二种实施方式中，各第一信号线DL的第一段DL1位于电源总线和绑定部BA之间，第一总线部至少部分位于转接部CP靠近显示区AA的一侧；第二总线部至少部分部位于转接部CP远离显示区AA的一侧，且与绑定部BA连接。第一总线部和第二总线部位于转接部CP远离衬底SU的表面，第一总线部和第二总线部均与转接部连接。封装胶FR覆盖转接部CP，转接部CP作为封装基底TB的一部分，使得封装胶FR不用覆盖电源线。
如图7所示，在一实施方式中，转接部CP位于第一信号线DL远离显示区AA的一侧。转接部CP与至少部分第一信号线DL沿第一方向X分布，该部分第一信号线DL作为封装基底TB的一部分。同时，电源总线的第一总线部包括位于转接部CP靠近显示区AA的一侧，第二总线部位于转接部CP和绑定部BA之间，并与绑定部BA连接，第一总线部和第二总线部通过转接部CP连接。
进一步的，转接部CP可包括沿第一方向X间隔分布的第一转接部CP1和第二转接部CP2。电源总线可包括第一电源总线VDM和第二电源总线VSM。第一电源总线VDM的第一总线部VDM1和第二总线部VDM2通过第一转接部CP1连接。引出区FA内的第一信号线DL包括关于绑定部BA沿第二方向Y的中轴线对称分布的两个信号线组DLC，第一转接部CP1位于两个信号线组DLC之间，第一电源总线VDM的第一总线部VDM1和第二总线部VDM2通过第一转接部CP1连接。
如图7所示，第二转接部CP2与位于侧边区SA的基底主体TB1可为一体结构，即第二转接部CP2可为侧边区SA的基底主体TB1延伸至引出区FA的部分，第二电源总线VSM的第一总线部VSM1和第二总线部VSM2通过第二转接部CP2连接。
如图2和图7所示，在本实施方式中，封装基底TB可包括位于侧边区SA和顶部区TA的基底主体TB1、至少部分第一信号线DL的第一段DL1的至少部分区域以及第二段DL2的至少部分区域。
如图8和图9所示，在本公开的第三种实施方式中，各第一信号线DL的第一段DL1位于转接部CP和显示区AA之间，转接部CP位于第一段DL1和绑定部BA之间，第一信号线DL的第二段DL2与转接部CP沿第一方向X分布。各第一信号线DL分为关于绑定部BA沿第二方向Y的中轴线对称分布的两个信号线组DLC；转接部CP位于两个信号线组DLC外侧。
封装基底TB可包括位于侧边区SA和顶部区TA的基底主体TB1和各第二段DL2的至少部分区域。
如图8和图9所示，在一实施方式中，转接部CP可包括沿第一方向X间隔分布的第一转接部CP1和第二转接部CP2，第二转接部CP2位于侧边区SA和第一转接部CP1之间，且第一转接部CP1、第二转接部CP2和第一信号线DL的第二段DL2沿第一方向X分布。第一信号线DL的第一段的DL1位于转接部CP和显示区AA之间。
电源总线可包括第一电源总线VDM和第二电源总线VSM，第一电源总线VDM的第一总线部VDM1通过第一转接部CP1与第二总线部VDM2连接；第二电源总线VSM的第一总线部VSM1通过第二转接部CP2与第二总线部VSM2连接。第二总线部VDM2和第二总线部VSM2均与绑定部BA连接。
如图8和图9所示，为了提高封装基底TB的均一性，封装基底TB还可包括第一虚设部DU1，第一虚设部DU1可沿第一方向X间隔设于第一转接部CP1和第二转接部CP2之间，封装胶FR可覆盖第一虚设部DU1。第一虚设部DU1浮接，即不接入任何电信号。通过第一虚设部DU1可填充第一转接部CP1和第二转接部CP2之间的空间，使封装胶FR更加平整，进一步提高封装胶FR的均匀性，且提高封装胶FR与封装基底TB的结合面的面积，提高对水、氧的阻隔效果。第一虚设部DU1的数量可为多个，且可沿第一方向X间隔分布，第一虚设部DU1可沿第二方向Y延伸。
如图8和图9所示，电路层TL还可包括测试线CT，测试线CT至少部分设于引出区FA，且与绑定部BA连接，测试线CT可与第二总线部VDM2和第二总线部VSM2交叠，且测试线CT可位于第一栅极层GA1或第二栅极层GA2。
进一步的，如图7和图8所示，至少一部分第一信号线DL的第二段DL2的至少部分区域属于封装基底TB，且这些第二段DL2中相邻两个之间可设有第二虚设部DU2，封装胶FR可覆盖各第二虚设部DU2。通过第二虚设部DU2可填充相邻两第二段DL2之间的空间，使封装胶FR更加平整，进一步提高封装胶FR的均匀性，且提高封装胶FR与封装基底TB的结合面的面积，提高对水、氧的阻隔效果。
第二虚设部DU2的数量可为多个，且相邻两第二段DL2之间设有第二虚设部DU2，第二虚设部DU2可沿第一方向X间隔分布，沿第二方向Y延伸。
进一步的，在本公开的一些实施方式中，第一虚设部DU1为与第一信号线DL的第二段DL2的宽度相同的线形结构，相邻两第二段DL2之间设置一个或多个多个第二虚设部DU2，且相邻的两第二虚设部DU2以及相邻的一第二虚设DU2和第二段DL1的间距相同。同时，第一转接部CP1和第二转接部CP2之间可设置多个第一虚设部DU1，且此处的第一虚设部DU1的间距与第二段DL2之间的第二虚设部DU2的间距相等，使得封装基底TB中的第一虚设部DU1、第二虚设部DU2和第二段DL2整体的密度一致，有利于提高封装胶FR覆盖范围内的均匀性。
如图13所示，在本公开的一些实施方式中，属于封装基底TB的至少部分第二段DL2可沿弯折轨迹延伸，从而增加封装胶FR与封装基底TB的结合面的面积，提高对水、氧的阻隔效果。
进一步的，如图13所示，属于封装基底TB的至少部分第二段DL2可包括在第一方向X上反向弯折的第一弯折部WP1和第二弯折部WP2，第一弯折部WP1和第二弯折部WP2可沿第二方向Y交替分布。第一弯折部WP1和第二弯折部WP2的形状可以是不封闭的多边形，例如矩形，当然，也可以是弧形等曲线形状。
在本公开的一些实施方式中，如图10和图11所示，封装基底TB 的部分区域设有第二通孔Ho2，同时，第二通孔Ho2内可填充有填充层FL，该填充层FL设有多个第三通孔Ho3，封装胶FR填充各第三通孔Ho3，增加封装胶FR与封装基底TB的结合面的面积，提高对水、氧的阻隔效果。
举例而言，封装基底TB位于第一栅极层GA1或第二栅极层GA2，即与第一栅极层GA1或第二栅极层GA2同层设置。填充层FL可与层间介质层ILD同时形成，即同层设置。
进一步的，第二通孔Ho2与封装基底TB的边界之间具有一定的距离，该距离可以大于30μm。
如图12所示，在本公开的一些实施方式中，封装基底TB的部分区域设有第二通孔Ho2，第二通孔Ho2内可填充有多个填充部FL1，填充部FL1阵列分布于第二通孔Ho2内，封装胶FR填充于第二通孔Ho2内，且覆盖各填充部FL1，从而可通过第二通孔Ho2和填充部FL1增大与封装胶FR的接触面，提高对水、氧的阻隔效果。
本公开实施方式还提供一种显示装置，该显示装置可包括上述任意实施方式的显示面板。该显示面板为上述任意实施方式的显示面板，其具体结构和有益效果可参考上文中显示面板的实施方式，在此不再赘述。
本公开的显示装置可以是手机、智能手表、智能手环、平板电脑、电视等具有显示功能的电子设备，在此不再一一列举。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (18)

  1. 一种显示面板，包括显示区和所述显示区外的外围区，所述外围区包括引出区，所述引出区包括绑定部；所述显示面板包括：
    驱动背板，包括衬底和设于所述衬底一侧的电路层，所述电路层包括沿远离所述衬底的方向分布的封装基底和电源总线，所述封装基底设于所述外围区且至少部分围绕所述显示区设置；所述电源总线至少部分位于所述引出区，所述电源总线位于所述引出区的部分位于所述显示区和所述绑定部之间，且与所述绑定部连接；所述封装基底至多与所述电源总线位于所述引出区的部分交叠；所述封装基底为反光结构；
    发光器件，设于所述电路层远离所述衬底的一侧，且位于所述显示区；
    封装胶，至少部分设于所述封装基底远离所述衬底的表面，且至少部分沿所述封装基底的延伸轨迹围绕于所述显示区外；
    封装盖板，设于所述封装胶远离所述衬底的表面。
  2. 根据权利要求1所述的显示面板，其中，所述封装基底在所述引出区的部分包括转接部；
    所述电源总线包括第一总线部和第二总线部，所述第一总线部至少部分位于所述转接部靠近所述显示区的一侧；所述第二总线至少部分部位于所述转接部远离所述显示区的一侧，且与所述绑定部连接；所述第一总线部和所述第二总线部均与所述转接部连接。
  3. 根据权利要求2所述的显示面板，其中，所述转接部包括沿第一方向间隔分布的第一转接部和第二转接部；
    所述电源总线包括第一电源总线和第二电源总线，所述第一电源总线的第一总线部和第二总线部通过所述第一转接部连接；所述第二电源总线的第一总线部和第二总线部通过第二转接部连接。
  4. 根据权利要求3所述的显示面板，其中，所述电路层还包括多个第一信号线，所述第一信号线至少部分位于所述引出区，且位于所述显示区和所述绑定部之间；所述第一信号线位于所述引出区的部分包括沿所述第一方向延伸的第一段和沿与所述第一方向相交的第二方向延伸的第二段，所述第二段连接所述第一段和所述绑定部。
  5. 根据权利要求4所述的显示面板，其中，所述外围区还包括沿所述第一方向分布于所述显示区两侧的侧边区和分布于所述显示区远离所述引出区的一侧的顶部区；
    所述封装基底包括位于所述侧边区和所述顶部区的基底主体、所述第一段的至少部分区域以及所述第二段的至少部分区域；
    各所述第一信号线的第二段包括关于所述绑定部沿所述第二方向方向的中轴线对称分布的两个信号线组；所述第一转接部位于两个所述信号线组之间。
  6. 根据权利要求4所述的显示面板，其中，所述外围区还包括沿所述第一方向分布于所述显示区两侧的侧边区和沿所述第二方向分布于所述显示区远离所述引出区的一侧的顶部区；
    所述第一段位于所述转接部和所述显示区之间，所述第二段与所述转接部沿所述第一方向分布；
    所述封装基底包括位于所述侧边区和所述顶部区的基底主体和各所述第二段的至少部分区域；
    各所述第一信号线的第二段分为关于所述绑定部沿第二方向的中轴线对称分布的两个信号线组；所述转接部位于两个所述信号线组外侧。
  7. 根据权利要求6所述的显示面板，其中，所述封装基底还包括第一虚设部，所述第一虚设部沿所述第一方向间隔设于所述第一转接部和所述第二转接部之间；所述封装胶覆盖所述第一虚设部。
  8. 根据权利要求7所述的显示面板，其中，属于所述封装基底的所述第二段之间设有第二虚设部，所述封装胶覆盖所述第二虚设部。
  9. 根据权利要求8所述的显示面板，其中，所述第一虚设部和所述第二虚设部均沿所述第二方向延伸。
  10. 根据权利要求1所述的显示面板，其中，属于所述封装基底的至少部分所述第二段沿弯折轨迹延伸。
  11. 根据权利要求1所述的显示面板，其中，属于所述封装基底的至少部分所述第二段包括在第一方向上反向弯折的第一弯折部和第二弯折部，所述第一弯折部和所述第二弯折部沿第二方向交替分布。
  12. 根据权利要求1所述的显示面板，其中，所述电路层还包括多 个第一信号线，所述第一信号线至少部分位于所述引出区，且位于所述显示区和所述绑定部之间；所述第一信号线位于所述引出区的部分包括沿第一方向延伸的第一段和沿第二方向延伸的第二段，所述第二段连接所述第一段和所述绑定部；
    所述电源总线位于所述引出区的部分包括沿所述第一方向延伸的第一总线部和沿所述第二方向延伸的第二总线部，所述第二总线部连接所述第一总线部和所述绑定部；所述第一总线部位于所述第一信号线和所述显示区之间；所述第二总线部与所述第一段交叠，所述封装胶覆盖所述第二总线部。
  13. 根据权利要求12所述的显示面板，其中，所述第二总线部设有多个第一通孔，所述封装胶填充所述第一通孔。
  14. 根据权利要求12所述的显示面板，其中，所述第二总线部在所述第一方向上的宽度不大于300μm。
  15. 根据权利要求1-14任一项所述的显示面板，其中，所述封装基底的部分区域设有第二通孔。
  16. 根据权利要求15所述的显示面板，其中，所述第二通孔内填充有填充层，且所述填充层设有多个第三通孔；所述封装胶填充各所述第三通孔。
  17. 根据权利要求1-14任一项所述的显示面板，其中，所述电路层包括沿远离所述衬底的方向依次分布的第一栅极层、第一栅绝缘层、第二栅极层、层间介质层、第一源漏层、第一平坦层、第二源漏层和第二平坦层；所述发光器件设于所述第二平坦层远离所述衬底的表面；
    所述封装基底位于所述第一栅极层或所述第二栅极层，所述电源总线位于所述第一源漏层或所述第二源漏层。
  18. 一种显示装置，包括权利要求1-17任一项所述的显示面板。
PCT/CN2023/131546 2022-12-01 2023-11-14 显示面板及显示装置 WO2024114368A1 (zh)

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