WO2022199062A1 - 显示装置、显示面板及其制造方法 - Google Patents

显示装置、显示面板及其制造方法 Download PDF

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Publication number
WO2022199062A1
WO2022199062A1 PCT/CN2021/131322 CN2021131322W WO2022199062A1 WO 2022199062 A1 WO2022199062 A1 WO 2022199062A1 CN 2021131322 W CN2021131322 W CN 2021131322W WO 2022199062 A1 WO2022199062 A1 WO 2022199062A1
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WIPO (PCT)
Prior art keywords
layer
substrate
orthographic projection
flat
area
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PCT/CN2021/131322
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English (en)
French (fr)
Inventor
刘江
王大伟
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication of WO2022199062A1 publication Critical patent/WO2022199062A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display device, a display panel, and a manufacturing method of the display panel.
  • display panels have been widely used in various electronic devices.
  • the packaging process is an important process to improve reliability.
  • organic electroluminescent display panels it is usually necessary to block the external water and oxygen through the packaging layer. Erosion of light emitting devices and circuits.
  • the film formation quality is prone to problems, and it is difficult to form a predetermined pattern.
  • the present disclosure provides a display device, a display panel and a manufacturing method thereof.
  • a display panel comprising:
  • a substrate including a display area and a peripheral area outside the display area, the peripheral area including a circuit area and a blocking area sequentially distributed along a direction away from the display area;
  • a driving device layer arranged on one side of the substrate and covering the display area and the peripheral area;
  • a flat layer disposed on the side of the driving device layer away from the substrate, and the boundary of the orthographic projection of the flat layer on the substrate is located in the circuit area;
  • a light-emitting layer disposed on the surface of the flat layer away from the substrate, and the orthographic projection of the light-emitting layer on the substrate at least covers the display area;
  • a blocking dam disposed on the side of the driving device layer away from the substrate, and disposed around the display area, and the orthographic projection of the blocking dam on the substrate is located in the blocking area;
  • a first inorganic encapsulation layer covering the light-emitting layer and the barrier dam, and the orthographic projection of the first inorganic encapsulation layer on the substrate covers the display area and the peripheral area;
  • an organic encapsulation layer disposed on the surface of the first inorganic encapsulation layer away from the substrate, the orthographic projection of the flat layer on the substrate is located within the orthographic projection of the organic encapsulation layer on the substrate ;
  • the second inorganic encapsulation layer covers the organic encapsulation layer, and the orthographic projection on the substrate covers the display area and the peripheral area.
  • the planarization layer includes:
  • the second flat layer is provided on the side of the first flat layer away from the substrate, and the boundary of the orthographic projection of the second flat layer on the substrate is located in the circuit area; the light-emitting layer is provided with on the surface of the second flat layer facing away from the substrate.
  • the light-emitting layer includes:
  • a first electrode layer is provided on the side of the second flat layer away from the substrate, the first electrode layer includes a first electrode and a transition part, and the first electrode is on the positive side of the substrate.
  • the projection is located in the display area, and the orthographic projection of the adapter on the substrate is located in the circuit area;
  • a pixel definition layer disposed on the surface of the second flat layer away from the substrate, the orthographic projection of the pixel definition layer on the substrate covers the display area and the circuit area; the pixel definition layer a pixel opening exposing the first electrode and a transfer opening exposing the transfer part are provided;
  • a light-emitting functional layer covering the pixel definition layer and the first electrode, and the orthographic projection of the light-emitting functional layer on the substrate is located in the display area;
  • the second electrode layer covers the light-emitting functional layer, the boundary of the orthographic projection of the second electrode layer on the substrate is located in the circuit region, and the second electrode layer communicates with the transfer part connection;
  • the first inorganic encapsulation layer covers the second electrode layer.
  • the blocking dam includes a first dam body and a second dam body, and the second dam body surrounds the outside of the first dam body.
  • the first dam is disposed in the same layer as the pixel definition layer;
  • the second dam includes a first barrier layer stacked in a direction away from the substrate;
  • the second barrier layer, the first barrier layer and the second flat layer are arranged in the same layer, and the second barrier layer and the pixel definition layer are arranged in the same layer.
  • the first electrode layer further includes:
  • an extension part connected with the adapter part, and the orthographic projection of the extension part on the substrate is located in the blocking area;
  • the first dam is provided on a surface of the extension portion facing away from the substrate.
  • the driving device layer includes:
  • an active layer disposed on one side of the substrate, and the orthographic projection of the active layer on the substrate is located in the display area and the circuit area;
  • a first gate insulating layer covering the active layer and the substrate
  • a gate which is arranged on the surface of the first gate insulating layer away from the substrate, and the orthographic projection of the gate on the substrate is located in the display area and the circuit area;
  • a source-drain layer disposed on the surface of the interlayer dielectric layer away from the substrate, and the orthographic projection of the source-drain layer on the substrate is located in the display area and the circuit area;
  • the first flat layer is disposed on the side of the source and drain layers away from the substrate;
  • the display panel also includes:
  • connection layer disposed on the surface of the first flat layer away from the substrate, and connected to the source and drain layers, the orthographic projection of the connection layer on the substrate is located in the display area;
  • a signal line is arranged on the side of the barrier dam close to the substrate, the signal line includes a first line layer and a second line layer stacked in sequence in a direction away from the substrate, the first line layer and the The source and drain layers are arranged in the same layer, and the second wire layer and the connection layer are arranged in the same layer; at least part of the second dam body is arranged on the surface of the second wire layer away from the substrate;
  • the extension portion is provided on a surface of the signal line facing away from the substrate.
  • the second flat layer is provided with a first barrier groove penetrating the second flat layer and the first flat layer, and the first barrier groove is in the liner
  • the orthographic projection on the bottom is located in the circuit area and surrounds the display area.
  • the interlayer dielectric layer is provided with a second blocking groove, and the orthographic projection of the second blocking groove on the substrate surrounds the outside of the second dam.
  • the distance between the boundary of the second planarizing layer and the first dam is a first distance, and the distance between the boundary of the second planarizing layer and the second dam is a second distance;
  • the ratio of the second distance to the first distance is 7/5.
  • a method for manufacturing a display panel including:
  • the substrate includes a display area and a peripheral area outside the display area, the peripheral area includes a circuit area and a blocking area sequentially distributed along a direction away from the display area;
  • a flat layer is formed on the side of the driving device layer away from the substrate, and the boundary of the orthographic projection of the flat layer on the substrate is located in the circuit region;
  • a blocking dam is formed on a side of the driving device layer away from the substrate, and the blocking dam is arranged around the display area, and an orthographic projection of the blocking dam on the substrate is located in the blocking area;
  • a light-emitting layer is formed on the surface of the flat layer away from the substrate, and the orthographic projection of the light-emitting layer on the substrate at least covers the display area;
  • first inorganic encapsulation layer covering the light-emitting layer and the barrier dam, the orthographic projection of the first inorganic encapsulation layer on the substrate covering the display area and the peripheral area;
  • a liquid organic material layer is formed on the surface of the first inorganic encapsulation layer facing away from the substrate, and the orthographic projection of the organic material layer on the substrate is located within the range surrounded by the barrier dam, and is connected to the There is a gap between the barrier dams; the boundary of the orthographic projection of the flat layer on the substrate is located within the orthographic projection of the organic material layer on the substrate, and is in the same direction with the organic material layer on the substrate the boundaries of the orthographic projections on the base at least partially coincide;
  • a second inorganic encapsulation layer covering the organic material layer is formed, and the orthographic projection of the second inorganic encapsulation layer on the substrate covers the display area and the peripheral region.
  • a flat layer is formed on a side of the driving device layer away from the substrate; including:
  • a second flat layer is formed on the side of the first flat layer away from the substrate, and the boundary of the orthographic projection of the second flat layer on the substrate is located in the circuit region;
  • the light-emitting layer is disposed on the surface of the second flat layer facing away from the substrate.
  • the orthographic projections of the second flat layer and the organic material layer on the substrate are both rectangles, and adjacent two sides of the rectangle are connected by rounded transitions ;
  • the rounded corners of the orthographic projection of the second flat layer on the substrate are inscribed to the rounded corners of the orthographic projection of the organic material layer on the substrate.
  • forming a light-emitting layer on a surface of the second flat layer away from the substrate including:
  • a first electrode layer is formed on the side of the second flat layer facing away from the substrate, the first electrode layer includes a first electrode and a transition part, and an orthographic projection of the first electrode on the substrate is located in the display area, and the orthographic projection of the switching portion on the substrate is located in the circuit area;
  • a pixel definition layer is formed on the surface of the second flat layer away from the substrate, and the orthographic projection of the pixel definition layer on the substrate covers the display area and the circuit area; the pixel definition layer is provided with There are pixel openings exposing the first electrodes and transfer openings exposing the transfer parts;
  • a second electrode layer covering the light-emitting functional layer is formed, the boundary of the orthographic projection of the second electrode layer on the substrate is located in the circuit region, and the second electrode layer is connected to the circuit region through the transfer opening. the transfer part is connected;
  • the blocking dam includes a first dam body and a second dam body, the second dam body surrounds the first dam body; the second dam body includes a first dam body stacked in a direction away from the substrate A barrier layer and a second barrier layer, the first barrier layer and the second flat layer are simultaneously provided by one patterning process, and the second barrier layer, the first dam and the pixel definition layer are patterned by one time The processes are formed simultaneously.
  • the thickness of the first dam is not greater than 2 ⁇ m, and the thickness of the organic material layer is not less than 8 ⁇ m.
  • a display device including the display panel described in any one of the above.
  • FIG. 1 is a top view of an embodiment of a display panel of the present disclosure.
  • FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1 .
  • FIG. 3 is a B-B sectional view of FIG. 1 .
  • FIG. 4 is a flow chart of an embodiment of the disclosed manufacturing method.
  • FIG. 5 is a schematic diagram of the boundaries in the display panel of the present disclosure.
  • Substrate 101, Display area; 102, Peripheral area; 1021, Circuit area; 1022, Blocking area;
  • Driving device layer 21, Active layer; 22, First gate insulating layer; 23, Gate electrode; 24, Second gate insulating layer; 25, Interlayer dielectric layer; 251, Second barrier groove; 26, Source Drain layer; 261, source electrode; 262, drain electrode;
  • Barrier dam 61, First dam body; 62, Second dam body; 621, First barrier layer; 622, Second barrier layer;
  • signal line 111, first line layer; 112, second line layer;
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • Embodiments of the present disclosure provide a display panel, which may be an organic electro-optical (OLED) display panel.
  • the display panel of the present disclosure may include a substrate 1 , a driving device layer 2 , The flat layer 100, the light emitting layer 5, the barrier dam 6, the first inorganic encapsulation layer 7, the organic encapsulation layer 8 and the second inorganic encapsulation layer 9, wherein:
  • the substrate 1 includes a display area 101 and a peripheral area 102 located outside the display area 101, and the peripheral area 102 includes a circuit area 1021 and a blocking area 1022 that are sequentially distributed along the direction away from the display area 101;
  • the driving device layer 2 is disposed on one side of the substrate 1 and covers the display area 101 and the peripheral area 102;
  • the flat layer 100 is disposed on the side of the driving device layer 2 away from the substrate 1, and the boundary of the orthographic projection of the flat layer 100 on the substrate 1 is located in the circuit region 1021;
  • the light-emitting layer 5 is disposed on the surface of the second flat layer 4 away from the substrate 1, and the orthographic projection of the light-emitting layer 5 on the substrate 1 at least covers the display area 101;
  • the blocking dam 6 is disposed on the side of the driving device layer 2 away from the substrate 1, and is disposed around the display area 101, and the orthographic projection of the blocking dam 6 on the substrate 1 is located in the blocking area 1022;
  • the first inorganic encapsulation layer 7 covers the light-emitting layer 5 and the blocking dam 6, and the orthographic projection of the first inorganic encapsulation layer 7 on the substrate 1 covers the display area 101 and the peripheral area 102;
  • the organic encapsulation layer 8 is provided on the surface of the first inorganic encapsulation layer 7 away from the substrate 1 , the orthographic projection of the organic encapsulation layer 8 on the substrate 1 is located within the range surrounded by the barrier dam 6 , and the second flat layer 4 is on the substrate 1 The orthographic projection of is located within the orthographic projection of the organic encapsulation layer 8 on the substrate 1;
  • the second inorganic encapsulation layer 9 covers the organic encapsulation layer 8 , and the orthographic projection on the substrate 1 covers the display area 101 and the peripheral area 102 .
  • the light-emitting layer 5 can be protected by the first inorganic encapsulation layer 7 , the organic encapsulation layer 8 and the second inorganic encapsulation layer 9 .
  • the first inorganic encapsulation layer 7 and the second inorganic encapsulation layer Layer 9 can block water, oxygen, and prevent corrosion.
  • the organic encapsulation layer 8 can be planarized and buffered. Wherein, when the organic encapsulation layer 8 is formed, a liquid organic material layer can be formed, and the boundary of the flat layer 100, that is, the first boundary 001, can be located within the boundary of the organic material layer, that is, within the second boundary 002.
  • the boundary of the flat layer 100 that is, the third boundary 003 is located within the boundary of the organic encapsulation layer 8 . Since the first boundary 001 is located in the circuit region 1021 and does not extend to the boundary of the substrate 1, a step is formed, and the organic encapsulation layer 8 can flatten the position of the step to avoid photolithography on the outside of the step in the subsequent process Glue buildup is difficult to expose in the exposure process, which affects the formation of subsequent film layers such as the touch layer, thereby affecting product quality.
  • a plurality of traces are arranged on the edge of the touch layer.
  • at least a part of the traces at least part of each trace is located outside the boundary of the flat layer.
  • There is a height difference at the boundary so that the photoresist is easy to accumulate, so that it is difficult to completely separate the regions of two adjacent traces outside the boundary, and a short circuit occurs.
  • the substrate 1 may include a display area 101 and a peripheral area 102 .
  • the peripheral area 102 is located outside the display area 101 , for example, the peripheral area 102 is an annular area surrounding the outside of the display area 101 .
  • the peripheral area 102 may include a circuit area 1021 and a blocking area 1022 sequentially distributed in a direction away from the display area 101 .
  • the substrate 1 can be a single-layer or multi-layer structure, and its material can include hard materials such as glass, and can also include flexible materials such as polyimide.
  • the driving device layer 2 is disposed on one side of the substrate 1 and covers the display area 101 and the peripheral area 102 , that is, the driving device layer 2 covers the display area 101 , the circuit area 1021 and the blocking area 1022 .
  • the driving device layer 2 is used to set the driving device required by the driving circuit, and the driving device may include thin film transistors, capacitors, etc., wherein, the area of the driving device layer 2 corresponding to the display area 101 may be provided with the thin film transistors and thin film transistors required by the pixel circuit.
  • the area of the driving device layer 2 corresponding to the circuit area 1021 may be provided with thin film transistors and capacitors required by the peripheral circuit, and the peripheral circuit may include a gate driving circuit and a light-emitting control circuit.
  • a top-gate thin film transistor may include an active layer 21 , a first gate insulating layer 22 , a gate electrode stacked in a direction away from the substrate 1 . 23.
  • the second gate insulating layer 24, the interlayer dielectric layer 25 and the source-drain layer 26, the driving device layer 2 has a plurality of thin film transistors, and the same film layer of any two thin film transistors in at least a part of the thin film transistors can be arranged in the same layer, so
  • the film layer structure of the driving device layer 2 can be described by describing the structure of a thin film transistor, that is, the driving device layer 2 may include an active layer 21, a first gate insulating layer 22, a gate electrode 23, a second gate insulating layer 24, The interlayer dielectric layer 25 and the source and drain layers 26, wherein:
  • the active layer 21 is arranged on one side of the substrate 1. Since each thin film transistor has an active layer 21, the number of the active layers 21 is multiple, and the orthographic projection of the active layer 21 on the substrate 1 is located at The display area 101 and the circuit area 1021 , that is, the display area 101 and the circuit area 1021 are both provided with the active layer 21 .
  • the first gate insulating layer 22 covers the active layer 21 and the substrate 1 , and the first gate insulating layer 22 may cover the display region 101 , the circuit region 1021 and the blocking region 1022 .
  • the gate electrode 23 is disposed on the surface of the first gate insulating layer 22 away from the substrate 1. Since each thin film transistor has a gate electrode 23, the number of the gate electrode 23 is multiple, and each gate electrode 23 is distributed in the display area 101 and the display area 101.
  • the circuit area 1021 that is, the orthographic projection of the gate electrode 23 on the substrate 1 is located in the display area 101 and the circuit area 1021 . Meanwhile, each gate 23 and each active layer 21 are arranged in a one-to-one correspondence in a direction perpendicular to the substrate 1, that is, the orthographic projection of the gate 23 on the substrate 1 at least partially overlaps with its corresponding active layer 21.
  • the second gate insulating layer 24 covers the gate electrode 23 and the first gate insulating layer 22 , and the boundary of the second gate insulating layer 24 may be flush with the boundary of the first gate insulating layer 22 .
  • the interlayer dielectric layer 25 can cover the second gate insulating layer 24 and is flush with the boundary of the second gate insulating layer 24 , that is, the orthographic projection of the interlayer dielectric layer 25 on the substrate 1 covers the display area 101 and the peripheral area 102 .
  • the material of the interlayer dielectric layer 25 can be an organic material.
  • the interlayer dielectric layer 25 can be arranged to penetrate the interlayer dielectric in a direction perpendicular to the substrate 1 .
  • the second blocking groove 251 of the layer 25 is an annular groove surrounding the circuit area 1021 , thereby cutting off the path of water and oxygen intruding into the display area 101 along the interlayer dielectric layer 25 .
  • the source and drain layers 26 are disposed on the surface of the interlayer dielectric layer 25 away from the substrate 1. Since each thin film transistor has a source and drain layer 26, the number of the source and drain layers 26 is multiple, and each source and drain layer 26 is distributed on the display.
  • the region 101 and the circuit region 1021 that is, the orthographic projection of the source and drain layers 26 on the substrate 1 are located in the display region 101 and the circuit region 1021 .
  • Each source and drain layer 26 is disposed corresponding to an active layer 21 and may include a source electrode 261 and a drain electrode 262 connected to both ends of the active layer 21 .
  • the driving device layer 2 may further include a passivation layer, the passivation layer may cover the source/drain layer 26 and the interlayer dielectric layer 25 , and the orthographic projection of the passivation layer on the substrate 1 may cover at least the display area 101 .
  • the planarization layer 100 is disposed on the side of the driving device layer 2 away from the substrate 1 , and the boundary of the orthographic projection of the planarization layer 100 on the substrate 1 is located in the circuit region 1021 .
  • the flat layer 100 on the substrate 1 may be a single-layer structure or a multi-layer structure.
  • the flat layer 100 may include a first flat layer 3 and a second flat layer 4, wherein:
  • the first flat layer 3 covers the driving device layer 2, for example, covers the source-drain layer 26 and the interlayer dielectric layer 25, and the boundary of the orthographic projection of the first flat layer 3 on the substrate 1 is located in the circuit region 1021, that is, the first The flat layer 3 only covers the entire display area 101 and at least part of the circuit area 1021 .
  • connection layer 10 and a signal line 11 can be provided, wherein:
  • connection layer 10 is disposed on the surface of the first flat layer 3 away from the substrate 1 , and the orthographic projection of the connection layer 10 on the substrate 1 is located in the display area 101 . Meanwhile, the connection layer 10 is connected to the source-drain layer 26 through via holes penetrating the first planar layer 3 .
  • the driving device layer 2 and the connection layer 10 may form a plurality of pixel circuits, and each pixel circuit may include a plurality of thin film transistors, capacitors and part of the connection layer 10.
  • the pixel circuit may be a pixel circuit such as 7T1C, 7T2C, 6T1C, or 6T2C, and its structure is not particularly limited here. Among them, nTmC indicates that a pixel circuit includes n transistors (represented by the letter "T”) and m capacitors (represented by the letter "C").
  • the signal line 11 is arranged on the side of the barrier dam 6 close to the substrate 1 .
  • the signal line 11 includes a first line layer 111 and a second line layer 112 which are sequentially stacked in the direction away from the substrate 1 .
  • the flat layer 3 faces away from the surface of the substrate 1 and is at least partially located in the blocking region 1022. Of course, it can also extend into the circuit region 1021.
  • the first line layer 111 and the source-drain layer 26 are arranged in the same layer, so that the same patterning process can be performed. form.
  • the second wire layer 112 is disposed on the surface of the first wire layer 111 away from the substrate 1 , and the second wire layer 112 and the connection layer 10 are disposed on the same layer, so that they can be formed by the same patterning process.
  • the second flat layer 4 is disposed on the surface of the first flat layer 3 away from the substrate 1 and covers the connection layer 10 .
  • the boundary of the orthographic projection of the second flat layer 4 on the substrate 1 is located in the circuit region 1021 , and the boundary is the boundary of the flat layer 100 , that is, the first boundary 001 , and the boundary of the first flat layer 3 is located within the first boundary 001 .
  • the light emitting layer 5 may be disposed on the surface of the second flat layer 4 away from the substrate 1 , and the orthographic projection of the light emitting layer 5 on the substrate 1 at least covers the display area 101 .
  • the light-emitting layer 5 may include a plurality of light-emitting devices, which may be organic electroluminescence (OLED) elements, and each light-emitting device may be connected to a pixel circuit.
  • Each light emitting device may include a first electrode 511 , a light emitting functional layer 53 and a second electrode stacked in a direction away from the substrate 1 .
  • the light-emitting layer 5 includes a first electrode layer 51 , a pixel definition layer 52 , a light-emitting functional layer 53 and a second electrode layer 54 , wherein:
  • the first electrode layer 51 is disposed on the side of the second flat layer 4 facing away from the substrate 1 , for example, the first electrode layer 51 is directly disposed on the surface of the second flat layer 4 facing away from the substrate 1 .
  • the first electrode layer 51 may include a first electrode 511 and a transition portion 512, and the first electrode 511 and the transition portion 512 may be formed simultaneously through the same patterning process, wherein: the orthographic projection of the first electrode 511 on the substrate 1 is located at The display area 101 is used to form the anode of the light-emitting device.
  • the number of the first electrodes 511 is multiple and distributed in an array.
  • the orthographic projection of the transfer portion 512 on the substrate 1 is located in the circuit area 1021, and is not connected to the first electrode 511, that is, the first electrode 511 is disconnected from the transfer portion 512, and the pattern of the transfer portion 512 is here Without special limitation, it can be used to connect the second electrode with the signal line 11 . Further, the adapter portion 512 may be provided with a plurality of through holes for exhaust.
  • the first electrode layer 51 may further include an extension portion 513 , which is connected to the transfer portion 512 , and whose orthographic projection on the substrate 1 is located in the blocking region 1022 , and the extension portion 513 may be a transfer portion
  • the portion 512 is a film layer extending continuously in the direction away from the first electrode 511 , and is an integral structure with the transition portion 512 , and can be formed simultaneously through a single patterning process.
  • the extension portion 513 covers the signal line 11 and is electrically connected to the signal line 11 .
  • the pixel definition layer 52 is disposed on the surface of the second flat layer 4 away from the substrate 1 , and the orthographic projection of the pixel definition layer 52 on the substrate 1 covers the display area 101 and the circuit area 1021 .
  • the pixel definition layer 52 is provided with pixel openings 521 and transfer openings 522 .
  • the number of the pixel openings 521 is the same as that of the first electrodes 511 , and the first electrodes 511 are exposed in a one-to-one correspondence.
  • the adapter opening 522 exposes the adapter portion 512 , but the number thereof is not particularly limited.
  • the light-emitting functional layer 53 covers the pixel definition layer 52 and the first electrode 511 , and the orthographic projection of the light-emitting functional layer 53 on the substrate 1 is located in the display area 101 .
  • the light-emitting functional layer 53 may include a hole injection layer, a hole transport layer, a light-emitting material layer, an electron transport layer, and an electron injection layer sequentially stacked in a direction away from the substrate 1 .
  • the second electrode layer 54 covers the light-emitting functional layer 53 , the boundary of the orthographic projection of the second electrode layer 54 on the substrate 1 is located in the circuit region 1021 , and the second electrode layer 54 is connected to the transfer portion 512 through the transfer opening 522 , thereby
  • the transition part 512 is connected to the signal line 11, and at the same time, the first electrode 511 can be connected to the connection layer 10 of the pixel circuit, so that a power supply signal can be input to the light-emitting device through the signal line 11, and the first electrode can be supplied to the first electrode through the peripheral circuit and the pixel circuit.
  • 511 inputs a driving signal, thereby driving the light-emitting functional layer 53 to emit light.
  • the blocking dam 6 may be disposed on the side of the driving device layer 2 away from the substrate 1 and surrounding the display area 101 , and the orthographic projection of the blocking dam 6 on the substrate 1 is located in the blocking area 1022 .
  • the barrier dam 6 may include multiple layers of concentrically spaced dam bodies, for example, it may include a first dam body 61 and a second dam body 62 , wherein :
  • the first dam 61 is disposed in the same layer as the pixel definition layer 52 , and is disposed on the surface of the extension portion 513 away from the substrate 1 .
  • At least a partial area of the second dam 62 is provided on the surface of the signal line 11 facing away from the substrate 1 , for example, a partial area of the second dam 62 is provided on the surface of the second line layer 112 facing away from the substrate; and the second dam 62 surrounds Outside the first dam body 61 , the thickness of the second dam body 62 may be greater than the thickness of the first dam body 61 .
  • the second dam body 62 may include a first barrier layer 621 and a second barrier layer 622 that are stacked in a direction away from the substrate 1 .
  • the first barrier layer 621 and the second flat layer 4 are arranged in the same layer, so that the same layer can pass through the same layer.
  • the second barrier layer 622 and the pixel definition layer 52 are disposed in the same layer, so that they can be formed by the same patterning process.
  • the distance between the boundary of the second planarization layer 4 and the first dam body 61 is the first distance L1.
  • the distance between the boundary of the second planarization layer 4 and the second dam 62 , and the minimum distance between the boundary of the second planarization layer 4 and the second dam 63 close to the sidewall of the second planarization layer 4 is the second distance L2 .
  • the first distance may be 200 ⁇ m
  • the second distance may be 280 ⁇ m.
  • the first inorganic encapsulation layer 7 covers the light emitting layer 5 and the barrier dam 6 , for example, the second electrode layer 54 and the barrier dam 6 .
  • the orthographic projection of the first inorganic encapsulation layer 7 on the substrate 1 covers the display area 101 and the peripheral area 102 , and the boundary of the first inorganic encapsulation layer 7 can be connected with the first gate insulating layer 22 , the second gate insulating layer 24 and the interlayer dielectric. The boundaries of layer 25 are flush.
  • the first inorganic packaging layer 7 faces the lining at the sidewall of the second flat layer 4 .
  • Bottom 1 is recessed to reach the surface of extension 513 facing away from substrate 1 .
  • the organic encapsulation layer 8 is provided on the surface of the first inorganic encapsulation layer 7 away from the substrate 1 , and the orthographic projection of the organic encapsulation layer 8 on the substrate 1 is located within the range surrounded by the barrier dam 6 , for example , the organic encapsulation layer 8 is located in the range surrounded by the first dam body 61 .
  • the orthographic projection of the second flat layer 4 on the substrate 1 is located within the orthographic projection of the organic encapsulation layer 8 on the substrate 1 , so that the boundary of the second flat layer 4 can be covered by the organic encapsulation layer 8 to achieve planarization .
  • the second inorganic encapsulation layer 9 covers the organic encapsulation layer 8 , and the orthographic projection on the substrate 1 covers the display area 101 and the peripheral area 102 , thereby covering the organic encapsulation layer 8 on the first Between the inorganic encapsulation layer 7 and the second inorganic encapsulation layer 9, external erosion is blocked.
  • a first blocking groove 31 can be opened in the second flat layer 4 penetrating the second flat layer 4 and the first flat layer 3 , and the orthographic projection of the first blocking groove 31 on the substrate 1 is located in the circuit area 1021 , and the first blocking groove 31 is an annular groove surrounding the display area 101 .
  • the number of the first blocking grooves 31 can be multiple, and they are arranged concentrically around the display area 101 .
  • the interlayer dielectric layer 25 is provided with a second blocking groove 251 penetrating the interlayer dielectric layer 25 .
  • the orthographic projection of the second blocking groove 251 on the substrate 1 surrounds the outside of the barrier dam 6 , for example, surrounds the outside of the second dam body 62 .
  • the number of the second blocking grooves 251 may be multiple, and they are arranged concentrically and spaced around the blocking dam 6 .
  • the display panel of the present disclosure may further include a touch layer disposed on the side of the second inorganic encapsulation layer 9 away from the substrate 1 , the touch layer includes an electrode area and a wiring area located in the electrode area, and the electrode area is provided with a touch
  • the trace area is provided with traces connected to the touch electrodes, each trace can be distributed in a direction away from the electrode area, and two adjacent traces are arranged at intervals to avoid short circuits.
  • the traces at least a partial area of a part of the traces is located outside the boundary of the second flat layer 4 , that is, the side away from the electrode area, and at least a part of the area of another part of the traces is located inside the boundary.
  • the planarization is achieved by the organic encapsulation layer 8, when the touch layer is formed by the photolithography process, there is a photoresist accumulation in the area outside the boundary corresponding to the second planarization layer 4, which makes it difficult to fully expose.
  • the insufficiently exposed area of the glue cannot be removed after development, so that the material in this area cannot be etched, so that the two adjacent traces inside and outside the boundary cannot be disconnected in this area, resulting in a short circuit and affecting the touch function. .
  • Embodiments of the present disclosure provide a method for manufacturing a display panel, where the display panel is the display panel of any of the above-mentioned embodiments. As shown in FIG. 4 , the manufacturing method may include steps S110 to S190, wherein:
  • Step S110 providing a substrate, the substrate includes a display area and a peripheral area located outside the display area, the peripheral area includes a circuit area and a blocking area sequentially distributed along a direction away from the display area;
  • Step S120 forming a driving device layer covering the display area and the peripheral area on one side of the substrate;
  • Step S130 forming a flat layer on the side of the driving device layer away from the substrate, and the boundary of the orthographic projection of the flat layer on the substrate is located in the circuit area;
  • Step S140 forming a barrier dam on the side of the driving device layer away from the substrate, and the barrier dam is arranged around the display area, and the orthographic projection of the barrier dam on the substrate is located at the barrier Area;
  • Step S150 forming a light-emitting layer on the surface of the flat layer away from the substrate, and the orthographic projection of the light-emitting layer on the substrate at least covers the display area;
  • Step S160 forming a first inorganic encapsulation layer covering the light-emitting layer and the barrier dam, and the orthographic projection of the first inorganic encapsulation layer on the substrate covers the display area and the peripheral area;
  • Step S170 forming a liquid organic material layer on the surface of the first inorganic encapsulation layer away from the substrate, the orthographic projection of the organic material layer on the substrate is located within the range surrounded by the barrier dam, and There is a gap between it and the blocking dam; the boundary of the orthographic projection of the flat layer on the substrate is located within the orthographic projection of the organic material layer on the substrate, and is within the orthographic projection of the organic material layer. The boundaries of the orthographic projections on the substrate at least partially coincide;
  • Step S180 after the organic material layer is leveled to form an organic encapsulation layer, a second inorganic encapsulation layer covering the organic material layer is formed, and the orthographic projection of the second inorganic encapsulation layer on the substrate covers all parts. the display area and the peripheral area.
  • a flat layer is formed on the side of the driving device layer away from the substrate, and the boundary of the orthographic projection of the flat layer on the substrate is located in the circuit that is, step S130 may include the following steps 1 and 2:
  • Step 1 forming a first flat layer covering the driving device layer, and the boundary of the orthographic projection of the first flat layer on the substrate is located in the circuit area;
  • Step 2 A second planarization layer is formed on the side of the first planarization layer away from the substrate, and the boundary of the orthographic projection of the second planarization layer on the substrate is located in the circuit region.
  • the light-emitting layer is disposed on the surface of the second flat layer facing away from the substrate.
  • the organic encapsulation layer 8 can be formed by an inkjet printing process.
  • an inkjet printing device can be used to print a liquid organic material layer on the first inorganic encapsulation layer 7, and the boundary of the organic material layer is inkjet printing.
  • the printing boundary set by the device forms the organic encapsulation layer 8 after the organic material diffuses outward and the boundary gradually expands to level.
  • the boundary of the second flat layer 4 is located within the boundary of the printed organic material layer, and in the direction perpendicular to the substrate 1, the boundary of the second flat layer 4 and the boundary of the organic material layer at least partially overlap, which ensures that the The boundary of the two flat layers 4 can also avoid printing too much organic material, which is too close to the barrier dam 6, and crosses the barrier dam 6 after leveling, resulting in package failure.
  • the thickness of the first dam 61 is not more than 2 ⁇ m, and the thickness of the organic material layer is not less than 8 ⁇ m.
  • the orthographic projections of the second flat layer and the organic material layer on the substrate are both rectangles, and adjacent two sides of the rectangles are connected by rounded transitions.
  • the four sides of the orthographic projection of the second flat layer on the substrate are located outside the orthographic projection of the organic material layer on the substrate, and the rounded corners of the orthographic projection of the second flat layer on the substrate are inscribed in the organic material layer Rounded corners in an orthographic projection on the substrate.
  • the first boundary 001 is the boundary of the second flat layer 4
  • the second boundary 002 is the boundary of the organic material layer.
  • a light-emitting layer is formed on the surface of the second flat layer away from the substrate; that is, step S160 includes the following steps 1-4, wherein:
  • Step 1 A first electrode layer is formed on the side of the second flat layer away from the substrate, the first electrode layer includes a first electrode and an adapter, and the first electrode is on the substrate
  • the orthographic projection of the adapter is located in the display area, and the orthographic projection of the adapter on the substrate is located in the circuit area;
  • Step 2 forming a pixel definition layer on the surface of the second flat layer away from the substrate, and the orthographic projection of the pixel definition layer on the substrate covers the display area and the circuit area; the pixels
  • the definition layer is provided with a pixel opening exposing the first electrode and a transfer opening exposing the transfer part;
  • Step 3 forming a light-emitting functional layer covering the pixel definition layer and the first electrode, and the orthographic projection of the light-emitting functional layer on the substrate is located in the display area;
  • Step 4 Form a second electrode layer covering the light-emitting functional layer, the boundary of the orthographic projection of the second electrode layer on the substrate is located in the circuit area, and the second electrode layer passes through the transfer the opening is connected with the adapter;
  • the barrier dam includes a first dam body and a second dam body.
  • first dam body and a second dam body are simultaneously provided through a patterning process, so The second barrier layer, the first dam and the pixel definition layer are formed simultaneously by one patterning process.
  • Embodiments of the present disclosure also provide a display device, which may include the display panel of any of the above-mentioned embodiments.
  • the structure and beneficial effects of the display panel may refer to the above-mentioned embodiments of the display panel, which will not be repeated here.
  • the display device of the present disclosure may be an electronic device such as a mobile phone, a tablet computer, a notebook computer, etc., which will not be listed one by one here.

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Abstract

一种显示装置、显示面板及其制造方法，涉及显示技术领域。显示面板包括衬底(1)、驱动器件层(2)、平坦层(100)、发光层(5)、阻挡坝(6)、第一无机封装层(7)、有机封装层(8)和第二无机封装层(9)，衬底(1)包括显示区(101)和位于显示区(101)外的外围区(102)，外围区(102)包括沿背离显示区(101)的方向依次分布的电路区(1021)和阻挡区(1022)；驱动器件层(2)设于衬底(1)一侧；平坦层(100)设于驱动器件层(2)背离衬底(1)的一侧，且平坦层(100)在衬底(1)上的正投影的边界位于电路区(1021)内；发光层(5)设于平坦层(100)背离衬底(1)的表面；阻挡坝(6)位于阻挡区(1022)；第一无机封装层(7)覆盖发光层(5)和阻挡坝(6)；有机封装层(8)设于第一无机封装层(7)上，平坦层(100)在衬底(1)上的正投影位于有机封装层(8)在衬底(1)上的正投影以内；第二无机封装层(9)覆盖有机封装层(8)。

Description

显示装置、显示面板及其制造方法
交叉引用
本公开要求于2021年3月25日提交的申请号为202110321693.4名称为“显示装置、显示面板及其制造方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示装置、显示面板及显示面板的制造方法。
背景技术
目前，显示面板已经广泛的应用于各种电子设备，其中，封装工艺是提高可靠性的重要工艺，特别是对于有机电致发光显示面板而言，通常需要通过封装层阻隔外界的水、氧对发光器件和电路的侵蚀。但是，现有显示面板中，在形成封装层后的其它膜层时，成膜质量容易出现问题，难以形成预定的图案。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开提供一种显示装置、显示面板及其制造方法。
根据本公开的一个方面，提供一种显示面板，包括：
衬底，包括显示区和位于所述显示区外的外围区，所述外围区包括沿背离所述显示区的方向依次分布的电路区和阻挡区；
驱动器件层，设于所述衬底一侧，且覆盖所述显示区和所述外围区；
平坦层，设于所述驱动器件层背离所述衬底的一侧，且所述平坦层在所述衬底上的正投影的边界位于所述电路区内；
发光层，设于所述平坦层背离所述衬底的表面，所述发光层在所述 衬底上的正投影至少覆盖所述显示区；
阻挡坝，设于所述驱动器件层背离所述衬底的一侧，且围绕所述显示区设置，所述阻挡坝在所述衬底上的正投影位于所述阻挡区；
第一无机封装层，覆盖所述发光层和所述阻挡坝，所述第一无机封装层在所述衬底上的正投影覆盖所述显示区和所述外围区；
有机封装层，设于所述第一无机封装层背离所述衬底的表面，所述平坦层在所述衬底上的正投影位于所述有机封装层在所述衬底上的正投影以内；
第二无机封装层，覆盖所述有机封装层，且在所述衬底上的正投影覆盖所述显示区和所述外围区。
在本公开的一种示例性实施例中，所述平坦层包括：
第一平坦层，覆盖所述驱动器件层，所述第一平坦层在所述衬底上的正投影的边界位于所述电路区内；
第二平坦层，设于所述第一平坦层背离所述衬底的一侧，所述第二平坦层在所述衬底上的正投影的边界位于所述电路区；所述发光层设于所述第二平坦层背离所述衬底的表面。
在本公开的一种示例性实施例中，所述发光层包括：
第一电极层，设于所述第二平坦层背离所述衬底的一侧，所述第一电极层包括第一电极和转接部，所述第一电极在所述衬底上的正投影位于所述显示区，所述转接部在所述衬底上的正投影位于所述电路区；
像素定义层，设于所述第二平坦层背离所述衬底的表面，所述像素定义层在所述衬底上的正投影覆盖所述显示区和所述电路区；所述像素定义层设有露出所述第一电极的像素开口和露出所述转接部的转接开口；
发光功能层，覆盖所述像素定义层和所述第一电极，所述发光功能层在所述衬底上的正投影位于所述显示区内；
第二电极层，覆盖所述发光功能层，所述第二电极层在所述衬底上的正投影的边界位于所述电路区，所述第二电极层通过所述转接开口与所述转接部连接；
所述第一无机封装层覆盖所述第二电极层。
在本公开的一种示例性实施例中，所述阻挡坝包括第一坝体和第二 坝体，所述第二坝体围绕于所述第一坝体以外。
在本公开的一种示例性实施例中，所述第一坝体与所述像素定义层同层设置；所述第二坝体包括向背离所述衬底的方向层叠的第一阻挡层和第二阻挡层，所述第一阻挡层与所述第二平坦层同层设置，所述第二阻挡层与所述像素定义层同层设置。
在本公开的一种示例性实施例中，所述第一电极层还包括：
延伸部，与所述转接部连接，所述延伸部在所述衬底上的正投影位于所述阻挡区；
所述第一坝体设于所述延伸部背离所述衬底的表面。
在本公开的一种示例性实施例中，所述驱动器件层包括：
有源层，设于所述衬底一侧面，所述有源层在所述衬底上的正投影位于所述显示区和所述电路区；
第一栅绝缘层，覆盖所述有源层和所述衬底；
栅极，设于所述第一栅绝缘层背离所述衬底的表面，所述栅极在所述衬底上的正投影位于所述显示区和所述电路区；
第二栅绝缘层，覆盖所述栅极和所述第一栅绝缘层；
层间介质层，覆盖所述第二栅绝缘层；
源漏层，设于所述层间介质层背离所述衬底的表面，所述源漏层在所述衬底上的正投影位于所述显示区和所述电路区；
所述第一平坦层设于所述源漏层背离所述衬底的一侧；
所述显示面板还包括：
连接层，设于所述第一平坦层背离所述衬底的表面，且与所述源漏层连接，所述连接层在所述衬底上的正投影位于所述显示区；
信号线，设于所述阻挡坝靠近所述衬底的一侧，所述信号线包括向背离所述衬底的方向依次层叠的第一线层和第二线层，所述第一线层与所述源漏层同层设置，所述第二线层与所述连接层同层设置；所述第二坝体的至少部分区域设于所述第二线层背离所述衬底的表面；
所述延伸部设于所述信号线背离所述衬底的表面。
在本公开的一种示例性实施例中，所述第二平坦层设有贯穿所述第二平坦层和所述第一平坦层的第一阻隔槽，所述第一阻隔槽在所述衬底 上的正投影位于所述电路区，且围绕所述显示区。
在本公开的一种示例性实施例中，
所述层间介质层设有第二阻隔槽，所述第二阻隔槽在所述衬底上的正投影围绕于所述第二坝体以外。
在本公开的一种示例性实施例中，
所述第二平坦化层的边界与所述第一坝体的距离为第一距离，所述第二平坦化层的边界与所述第二坝体的距离为第二距离；
所述第二距离与所述第一距离之比为7/5。
根据本公开的一个方面，提供一种显示面板的制造方法，包括：
提供一衬底，所述衬底包括显示区和位于所述显示区外的外围区，所述外围区包括沿背离所述显示区的方向依次分布的电路区和阻挡区；
在所述衬底一侧形成覆盖所述显示区和所述外围区驱动器件层；
在所述驱动器件层背离所述衬底的一侧形成平坦层，且所述平坦层在所述衬底上的正投影的边界位于所述电路区内；
在所述驱动器件层背离所述衬底的一侧形成阻挡坝，且所述阻挡坝围绕所述显示区设置，所述阻挡坝在所述衬底上的正投影位于所述阻挡区；
在所述平坦层背离所述衬底的表面形成发光层，所述发光层在所述衬底上的正投影至少覆盖所述显示区；
形成覆盖所述发光层和所述阻挡坝的第一无机封装层，所述第一无机封装层在所述衬底上的正投影覆盖所述显示区和所述外围区；
在所述第一无机封装层背离所述衬底的表面形成液态的有机材料层，所述有机材料层在所述衬底上的正投影位于所述阻挡坝围绕的范围内，且与所述阻挡坝之间具有间隙；所述平坦层在所述衬底上的正投影的边界位于所述有机材料层在所述衬底上的正投影以内，且与所述有机材料层在所述衬底上的正投影的边界至少部分重合；
在所述有机材料层流平形成有机封装层后，形成覆盖所述有机材料层的第二无机封装层，在所述第二无机封装层在所述衬底上的正投影覆盖所述显示区和所述外围区。
在本公开的一种示例性实施例中，在所述驱动器件层背离所述衬底 的一侧形成平坦层；包括：
形成覆盖所述驱动器件层的第一平坦层，所述第一平坦层在所述衬底上的正投影的边界位于所述电路区内；
在所述第一平坦层背离所述衬底的一侧形成第二平坦层，所述第二平坦层在所述衬底上的正投影的边界位于所述电路区；
所述发光层设于所述第二平坦层背离所述衬底的表面。
在本公开的一种示例性实施例中，所述第二平坦层和所述有机材料层在所述衬底上的正投影均为矩形，且所述矩形的相邻两边通过圆角过渡连接；
所述第二平坦层在所述衬底上的正投影的圆角内切于所述有机材料层在所述衬底上的正投影的圆角。
在本公开的一种示例性实施例中，在所述第二平坦层背离所述衬底的表面形成发光层；包括：
在所述第二平坦层背离所述衬底的一侧形成第一电极层，所述第一电极层包括第一电极和转接部，所述第一电极在所述衬底上的正投影位于所述显示区，所述转接部在所述衬底上的正投影位于所述电路区；
在所述第二平坦层背离所述衬底的表面形成像素定义层，所述像素定义层在所述衬底上的正投影覆盖所述显示区和所述电路区；所述像素定义层设有露出所述第一电极的像素开口和露出所述转接部的转接开口；
形成覆盖所述像素定义层和所述第一电极发光功能层，所述发光功能层在所述衬底上的正投影位于所述显示区内；
形成覆盖所述发光功能层的第二电极层，所述第二电极层在所述衬底上的正投影的边界位于所述电路区，所述第二电极层通过所述转接开口与所述转接部连接；
所述阻挡坝包括第一坝体和第二坝体，所述第二坝体围绕于所述第一坝体以外；所述第二坝体包括向背离所述衬底的方向层叠的第一阻挡层和第二阻挡层，所述第一阻挡层与所述第二平坦层通过一次构图工艺同时设置，所述第二阻挡层和所述第一坝体与所述像素定义层通过一次构图工艺同时形成。
在本公开的一种示例性实施例中，所述第一坝体的厚度不大于2μm， 所述有机材料层的厚度不小于8μm。
根据本公开的一个方面，提供一种显示装置，包括上述任意一项所述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开显示面板一实施方式的俯视图。
图2为图1的A-A截面图。
图3为图1的B-B截面图。
图4为本公开制造方法一实施方式的流程图。
图5为本公开显示面板中的边界示意图。
附图标记说明：
1、衬底；101、显示区；102、外围区；1021、电路区；1022、阻挡区；
2、驱动器件层；21、有源层；22、第一栅绝缘层；23、栅极；24、第二栅绝缘层；25、层间介质层；251、第二阻隔槽；26、源漏层；261、源极；262、漏极；
100、平坦层；3、第一平坦层；31、第一阻隔槽；4、第二平坦层；
5、发光层；51、第一电极层；511、第一电极；512、转接部；513、延伸部；52、像素定义层；521、像素开口；522、转接开口；53、发光功能层；54、第二电极层；
6、阻挡坝；61、第一坝体；62、第二坝体；621、第一阻挡层；622、第二阻挡层；
7、第一无机封装层；
8、有机封装层；
9、第二无机封装层；
10、连接层；
11、信号线；111、第一线层；112、第二线层；
001、第一边界；002、第二边界；003、第三边界；。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”等仅作为标记使用，不是对其对象的数量限制。
本公开实施方式提供了一种显示面板，该显示面板可为有机电致(OLED)显示面板，如图1-图3所示，本公开的显示面板可包括衬底1、驱动器件层2、平坦层100、发光层5、阻挡坝6、第一无机封装层7、有机封装层8和第二无机封装层9，其中：
衬底1包括显示区101和位于显示区101外的外围区102，外围区 102包括沿背离显示区101的方向依次分布的电路区1021和阻挡区1022；
驱动器件层2设于衬底1一侧，且覆盖显示区101和外围区102；
平坦层100设于驱动器件层2背离衬底1的一侧，平坦层100在衬底1上的正投影的边界位于电路区1021；
发光层5设于第二平坦层4背离衬底1的表面，发光层5在衬底1上的正投影至少覆盖显示区101；
阻挡坝6设于驱动器件层2背离衬底1的一侧，且围绕显示区101设置，阻挡坝6在衬底1上的正投影位于阻挡区1022；
第一无机封装层7覆盖发光层5和阻挡坝6，第一无机封装层7在衬底1上的正投影覆盖显示区101和外围区102；
有机封装层8设于第一无机封装层7背离衬底1的表面，有机封装层8在衬底1上的正投影位于阻挡坝6围绕的范围内，第二平坦层4在衬底1上的正投影位于有机封装层8在衬底1上的正投影以内；
第二无机封装层9覆盖有机封装层8，且在衬底1上的正投影覆盖显示区101和外围区102。
本公开实施方式的显示面板，可通过第一无机封装层7、有机封装层8和第二无机封装层9对发光层5进行保护，具体而言，第一无机封装层7和第二无机封装层9可阻隔水、氧，防止侵蚀。有机封装层8可实现平坦化，并进行缓冲。其中，在形成有机封装层8时，可形成液态的有机材料层，而平坦层100的边界，即第一边界001，可位于有机材料层的边界以内，即位于第二边界002以内，在有机材料层流平形成有机封装层8后，可确保平坦层100的边界，即第三边界003，位于有机封装层8的边界以内。由于第一边界001位于电路区1021，而未延伸至衬底1的边界，从而形成台阶，有机封装层8可对该台阶的位置实现平坦化，避免在后续工艺中，在台阶外侧出现光刻胶堆积，难以在曝光工艺中曝透，影响触控层等后续膜层的形成，从而影响产品质量。例如，在第二无机封装层上形成触控层时，触控层边缘设有多个走线，在至少一部分走线中，每个走线的至少部分区域位于平坦层的边界以外，由于在该边界处存在高度差，使得光刻胶容易出现堆积，从而使相邻两走线位于边界外的区域难以完全间隔开，而出现短路。
下面对本公开的显示面板进行详细说明：
如图1-图3所示，衬底1可包括显示区101和外围区102，外围区102位于显示区101外，例如，外围区102为围绕于显示区101外的环形区域。同时，外围区102可包括沿背离显示区101的方向依次分布的电路区1021和阻挡区1022。衬底1可为单层或多层结构，其材料可包括玻璃等硬质材料，也可包括聚酰亚胺等柔性材料。
如图1-图3所示，驱动器件层2设于衬底1一侧，且覆盖显示区101和外围区102，即驱动器件层2覆盖显示区101、电路区1021和阻挡区1022。驱动器件层2用于设置驱动电路所需的驱动器件，该驱动器件可包括薄膜晶体管和电容等，其中，驱动器件层2对应于显示区101的区域可设有像素电路所需的薄膜晶体管和电容等，驱动器件层2对应于电路区1021的区域可设有外围电路所需的薄膜晶体管和电容等，外围电路可包括栅极驱动电路，还可包括发光控制电路等。
在本公开的一些实施方式中，如图2所示，以顶栅型薄膜晶体管为例，其可包括向背离衬底1的方向层叠的有源层21、第一栅绝缘层22、栅极23、第二栅绝缘层24、层间介质层25和源漏层26，驱动器件层2有多个薄膜晶体管，至少一部分薄膜晶体管中的任意两薄膜晶体管的相同膜层可同层设置，因而可通过描述一个薄膜晶体管的结构对驱动器件层2的膜层结构进行说明，即驱动器件层2可包括有源层21、第一栅绝缘层22、栅极23、第二栅绝缘层24、层间介质层25和源漏层26，其中：
有源层21设于衬底1一侧面，由于各薄膜晶体管均具有一有源层21，因而，有源层21的数量为多个，且有源层21在衬底1上的正投影位于显示区101和电路区1021，即显示区101和电路区1021均设有有源层21。
第一栅绝缘层22覆盖有源层21和衬底1，且第一栅绝缘层22可覆盖显示区101、电路区1021和阻挡区1022。
栅极23设于第一栅绝缘层22背离衬底1的表面，由于各薄膜晶体管均具有一栅极23，因而，栅极23的数量为多个，各栅极23分布于显示区101和电路区1021，即栅极23在衬底1上的正投影位于显示区101和电路区1021。同时，各栅极23与各有源层21在垂直于衬底1的方向 上一一对应设置，即栅极23在衬底1上的正投影与其对应的有源层21至少部分重合。
第二栅绝缘层24覆盖栅极23和第一栅绝缘层22，第二栅绝缘层24的边界可与第一栅绝缘层22的边界平齐。
层间介质层25可覆盖第二栅绝缘层24，且与第二栅绝缘层24的边界平齐，即层间介质层25在衬底1上的正投影覆盖显示区101和外围区102。层间介质层25的材料可为有机材料，为了防止外界的水、氧沿层间介质层25侵入显示区101，可在层间介质层25设置沿垂直于衬底1的方向贯穿层间介质层25的第二阻隔槽251，第二阻隔槽251为围绕于电路区1021外的环形槽，从而切断水、氧沿层间介质层25侵入显示区101的路径。
源漏层26设于层间介质层25背离衬底1的表面，由于各薄膜晶体管均具有一源漏层26，因而，源漏层26的数量为多个，各源漏层26分布于显示区101和电路区1021，即源漏层26在衬底1上的正投影位于显示区101和电路区1021。每个源漏层26与一有源层21对应设置，并可包括连接至有源层21两端的源极261和漏极262。
此外，驱动器件层2还可包括钝化层，钝化层可覆盖源漏层26和层间介质层25，且钝化层在衬底1上的正投影至少覆盖显示区101。
如图2和图3所示，平坦层100设于驱动器件层2背离衬底1的一侧，平坦层100在衬底1上的正投影的边界位于电路区1021。同时，平坦层100在衬底1上的可为单层结构，也可为多层结构，举例而言，平坦层100可包括第一平坦层3和第二平坦层4，其中：
第一平坦层3覆盖驱动器件层2，例如，覆盖源漏层26和层间介质层25，且第一平坦层3在衬底1上的正投影的边界位于电路区1021内，即第一平坦层3仅覆盖全部的显示区101和电路区1021的至少部分区域。
在第一平坦层3背离衬底1的表面上，可设置连接层10和信号线11，其中：
连接层10设于第一平坦层3背离衬底1的表面，且连接层10在衬底1上的正投影位于显示区101。同时，连接层10通过贯穿第一平坦层3的过孔与源漏层26连接。驱动器件层2和连接层10可形成多个像素 电路，每个像素电路可包括多个薄膜晶体管、电容和部分连接层10。该像素电路可以是7T1C、7T2C、6T1C或6T2C等像素电路，在此不对其结构做特殊限定。其中，nTmC表示一个像素电路包括n个晶体管(用字母“T”表示)和m个电容(用字母“C”表示)。
信号线11设于阻挡坝6靠近衬底1的一侧，信号线11包括向背离衬底1的方向依次层叠的第一线层111和第二线层112，第一线层111设于第一平坦层3背离衬底1的表面，且至少部分位于阻挡区1022，当然，也可延伸至电路区1021内，第一线层111与源漏层26同层设置，从而可通过同一次构图工艺形成。第二线层112设于第一线层111背离衬底1的表面，第二线层112与连接层10同层设置，从而可通过同一次构图工艺形成。
如图2和图3所示，第二平坦层4设于第一平坦层3背离衬底1的表面，且覆盖连接层10。第二平坦层4在衬底1上的正投影的边界位于电路区1021，且该边界即为平坦层100的边界，即第一边界001，第一平坦层3的边界位于第一边界001以内。
如图2和图3所示，发光层5可设于第二平坦层4背离衬底1的表面，且发光层5在衬底1上的正投影至少覆盖显示区101。发光层5可包括多个发光器件，该发光器件可为有机电致发光(OLED)元件，每个发光器件可与一像素电路连接。每个发光器件可包括向背离衬底1的方向层叠的第一电极511、发光功能层53和第二电极。
在本公开的一些实施方式中，如图2和图3所示，发光层5包括第一电极层51、像素定义层52、发光功能层53和第二电极层54，其中：
第一电极层51设于第二平坦层4背离衬底1的一侧，例如，第一电极层51直接设于第二平坦层4背离衬底1的表面。第一电极层51可包括第一电极511和转接部512，第一电极511和转接部512可通过同一次构图工艺同时形成，其中：第一电极511在衬底1上的正投影位于显示区101，用于构成发光器件的阳极。第一电极511的数量为多个，且阵列分布。转接部512在衬底1上的正投影位于电路区1021，且与第一电极511之间不连接，即第一电极511与转接部512之间断开，转接部512的图案在此不做特殊限定，其可用于将第二电极与信号线11连接。 进一步的，转接部512上可设有多个用于排气的通孔。
进一步的，如图3所示，第一电极层51还可包括延伸部513，其与转接部512连接，且在衬底1上的正投影位于阻挡区1022，延伸部513可为转接部512向背离第一电极511的方向连续延伸的膜层，其与转接部512为一体结构，可通过一次构图工艺同时形成。同时，延伸部513覆盖信号线11，与信号线11电连接。
像素定义层52设于第二平坦层4背离衬底1的表面，像素定义层52在衬底1上的正投影覆盖显示区101和电路区1021。像素定义层52设有像素开口521和转接开口522，像素开口521的数量与第一电极511的数量相同，并一一对应地露出各第一电极511。转接开口522露出转接部512，但其数量不做特殊限定。
发光功能层53覆盖像素定义层52和第一电极511，发光功能层53在衬底1上的正投影位于显示区101内。举例而言，发光功能层53可包括向背离衬底1的方向依次层叠的空穴注入层、空穴传输层、发光材料层、电子传输层和电子注入层。
第二电极层54覆盖发光功能层53，第二电极层54在衬底1上的正投影的边界位于电路区1021，且第二电极层54通过转接开口522与转接部512连接，从而通过转接部512与信号线11连接，同时，第一电极511可与像素电路的连接层10连接，从而可通过信号线11向发光器件输入电源信号，通过外围电路和像素电路向第一电极511输入驱动信号，从而驱动发光功能层53发光。
如图2和图3所示，阻挡坝6可设于驱动器件层2背离衬底1的一侧，且围绕显示区101设置，阻挡坝6在衬底1上的正投影位于阻挡区1022。
在本公开的一些实施方式中，如图2和图3所示，阻挡坝6可包括多层同心间隔分布的坝体，例如，其可包括第一坝体61和第二坝体62，其中：
第一坝体61与像素定义层52同层设置，且设于延伸部513背离衬底1的表面。
第二坝体62的至少部分区域设于信号线11背离衬底1的表面，例 如，第二坝体62的部分区域设于第二线层112背离衬底的表面；且第二坝体62围绕于第一坝体61外，第二坝体62的厚度可大于第一坝体61的厚度。进一步的，第二坝体62可包括向背离衬底1的方向层叠的第一阻挡层621和第二阻挡层622，第一阻挡层621与第二平坦层4同层设置，从而可通过同一次构图工艺形成；第二阻挡层622与像素定义层52同层设置，从而可通过同一次构图工艺形成。
第二平坦化层4的边界与第一坝体61的距离，即第二平坦化层4的边界与第一坝体61靠近第二平坦化层4的侧壁的最小距离，为第一距离L1。
第二平坦化层4的边界与第二坝体62的距离，第二平坦化层4的边界与第二坝体63靠近第二平坦化层4的侧壁的最小距离，为第二距离L2。
第二距离L2与第一距离L1之比可为7/5，L2/L1＝7/5。举例而言，第一距离为200μm，第二距离可为280μm。
如图2和图3所示，第一无机封装层7覆盖发光层5和阻挡坝6，例如，覆盖第二电极层54和阻挡坝6。第一无机封装层7在衬底1上的正投影覆盖显示区101和外围区102，第一无机封装层7的边界可与第一栅绝缘层22、第二栅绝缘层24和层间介质层25的边界平齐。由于第二平坦层4的边界位于电路区1021内，而第一无机封装层7的边界在第二平坦层4外，故第一无机封装层7在第二平坦层4的侧壁处向衬底1凹陷，到达延伸部513背离衬底1的表面。
如图2和图3所示，有机封装层8设于第一无机封装层7背离衬底1的表面，有机封装层8在衬底1上的正投影位于阻挡坝6围绕的范围内，例如，有机封装层8位于第一坝体61围绕的范围内。同时，第二平坦层4在衬底1上的正投影位于有机封装层8在衬底1上的正投影以内，从而可通过有机封装层8包覆第二平坦层4的边界，实现平坦化。
如图2和图3所示，第二无机封装层9覆盖有机封装层8，且在衬底1上的正投影覆盖显示区101和外围区102，从而将有机封装层8包覆于第一无机封装层7和第二无机封装层9之间，阻挡外界侵蚀。
此外，为了进一步防止外界侵蚀，可在第二平坦层4开设贯穿第二 平坦层4和第一平坦层3的第一阻隔槽31，第一阻隔槽31在衬底1上的正投影位于电路区1021，且第一阻隔槽31为围绕显示区101的环形槽。第一阻隔槽31的数量可为多个，且围绕显示区101同心间隔设置。
层间介质层25设有贯穿层间介质层25的第二阻隔槽251，第二阻隔槽251在衬底1上的正投影围绕于阻挡坝6以外，例如，围绕于第二坝体62外。第二阻隔槽251的数量可为多个，且围绕阻挡坝6同心间隔设置。
此外，本公开的显示面板还可包括触控层，设于第二无机封装层9背离衬底1的一侧，触控层包括电极区和位于电极区的走线区，电极区设有触控电极，走线区设有与触控电极连接的走线，各走线可沿背离电极区的方向分布，且相邻两走线间隔设置，避免短路。在各走线中，一部分走线的至少部分区域位于第二平坦层4的边界的外侧，即背离电极区的一侧，另一部分走线的至少部分区域位于该边界的内侧。由于通过有机封装层8实现了平坦化，避免在通过光刻工艺形成触控层时，在对应于第二平坦层4的边界外的区域存在光刻胶堆积而难以充分曝光的情况，光刻胶的曝光不充分的区域在显影后无法被去除，导致该区域的材料无法被刻蚀，使得在该边界内外相邻的两走线在该区域无法断开，从而导致短路，影响触控功能。
本公开实施方式提供一种显示面板的制造方法，该显示面板为上述任意实施方式的显示面板，如图4所示，该制造方法可包括步骤S110-步骤S190，其中：
步骤S110、提供一衬底，所述衬底包括显示区和位于所述显示区外的外围区，所述外围区包括沿背离所述显示区的方向依次分布的电路区和阻挡区；
步骤S120、在所述衬底一侧形成覆盖所述显示区和所述外围区驱动器件层；
步骤S130、在所述驱动器件层背离所述衬底的一侧形成平坦层，且所述平坦层在所述衬底上的正投影的边界位于所述电路区内；
步骤S140、在所述驱动器件层背离所述衬底的一侧形成阻挡坝，且所述阻挡坝围绕所述显示区设置，所述阻挡坝在所述衬底上的正投影位 于所述阻挡区；
步骤S150、在所述平坦层背离所述衬底的表面形成发光层，所述发光层在所述衬底上的正投影至少覆盖所述显示区；
步骤S160、形成覆盖所述发光层和所述阻挡坝的第一无机封装层，所述第一无机封装层在所述衬底上的正投影覆盖所述显示区和所述外围区；
步骤S170、在所述第一无机封装层背离所述衬底的表面形成液态的有机材料层，所述有机材料层在所述衬底上的正投影位于所述阻挡坝围绕的范围内，且与所述阻挡坝之间具有间隙；所述平坦层在所述衬底上的正投影的边界位于所述有机材料层在所述衬底上的正投影以内，且与所述有机材料层在所述衬底上的正投影的边界至少部分重合；
步骤S180、在所述有机材料层流平形成有机封装层后，形成覆盖所述有机材料层的第二无机封装层，在所述第二无机封装层在所述衬底上的正投影覆盖所述显示区和所述外围区。
进一步的，在本公开的一些实施方式中，在所述驱动器件层背离所述衬底的一侧形成平坦层，且所述平坦层在所述衬底上的正投影的边界位于所述电路区内；即步骤S130可包括如下步骤一和步骤二：
步骤一、形成覆盖所述驱动器件层的第一平坦层，所述第一平坦层在所述衬底上的正投影的边界位于所述电路区内；
步骤二、在所述第一平坦层背离所述衬底的一侧形成第二平坦层，所述第二平坦层在所述衬底上的正投影的边界位于所述电路区。
所述发光层设于所述第二平坦层背离所述衬底的表面。
进一步的，有机封装层8可通过喷墨打印工艺形成，具体而言，可采用喷墨打印设备在第一无机封装层7上打印液态的有机材料层，有机材料层的边界即为喷墨打印设备设定的打印边界，在有机材料向外扩散，边界逐渐扩大至流平后，形成有机封装层8。第二平坦层4的边界位于打印有机材料层的边界以内，且在垂直于衬底1的方向上，第二平坦层4的边界与有机材料层的边界至少部分区域重合，既确保能够覆盖第二平坦层4的边界，又能避免打印的有机材料过多，距离阻挡坝6过近，而在流平后越过阻挡坝6，造成封装失效。举例而言，第一坝体61的厚 度不大于2μm，有机材料层的厚度不小于8μm。
在本公开的一些实施方式中，第二平坦层和有机材料层在衬底上的正投影均为矩形，且矩形的相邻两边通过圆角过渡连接。第二平坦层在衬底上的正投影的四个侧边位于有机材料层在衬底上的正投影以外，且第二平坦层在衬底上的正投影的圆角内切于有机材料层在衬底上的正投影的圆角。如图5所示，第一边界001为第二平坦层4的边界，第二边界002为有机材料层的边界。
在本公开的一些实施方式中，在所述第二平坦层背离所述衬底的表面形成发光层；即步骤S160，包括如下步骤一-步骤四，其中：
步骤一、在所述第二平坦层背离所述衬底的一侧形成第一电极层，所述第一电极层包括第一电极和转接部，所述第一电极在所述衬底上的正投影位于所述显示区，所述转接部在所述衬底上的正投影位于所述电路区；
步骤二、在所述第二平坦层背离所述衬底的表面形成像素定义层，所述像素定义层在所述衬底上的正投影覆盖所述显示区和所述电路区；所述像素定义层设有露出所述第一电极的像素开口和露出所述转接部的转接开口；
步骤三、形成覆盖所述像素定义层和所述第一电极发光功能层，所述发光功能层在所述衬底上的正投影位于所述显示区内；
步骤四、形成覆盖所述发光功能层的第二电极层，所述第二电极层在所述衬底上的正投影的边界位于所述电路区，所述第二电极层通过所述转接开口与所述转接部连接；
所述阻挡坝包括第一坝体和第二坝体，具体结构可参考上文显示面板的实施方式，其中，所述第一阻挡层与所述第二平坦层通过一次构图工艺同时设置，所述第二阻挡层和所述第一坝体与所述像素定义层通过一次构图工艺同时形成。
需要说明的是，尽管在附图中以特定顺序描述了本公开中制造方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/ 或者将一个步骤分解为多个步骤执行等。
本公开实施方式还提供一种显示装置，该显示装置可包括上述任意实施方式的显示面板，该显示面板的结构和有益效果可参考上文中显示面板的实施方式，在此不再赘述。本公开的显示装置可以是手机、平板电脑、笔记本电脑等电子设备，在此不再一一列举。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (16)

  1. 一种显示面板，其中，包括：
    衬底，包括显示区和位于所述显示区外的外围区，所述外围区包括沿背离所述显示区的方向依次分布的电路区和阻挡区；
    驱动器件层，设于所述衬底一侧，且覆盖所述显示区和所述外围区；
    平坦层，设于所述驱动器件层背离所述衬底的一侧，且所述平坦层在所述衬底上的正投影的边界位于所述电路区内；
    发光层，设于所述平坦层背离所述衬底的表面，所述发光层在所述衬底上的正投影至少覆盖所述显示区；
    阻挡坝，设于所述驱动器件层背离所述衬底的一侧，且围绕所述显示区设置，所述阻挡坝在所述衬底上的正投影位于所述阻挡区；
    第一无机封装层，覆盖所述发光层和所述阻挡坝，所述第一无机封装层在所述衬底上的正投影覆盖所述显示区和所述外围区；
    有机封装层，设于所述第一无机封装层背离所述衬底的表面，所述平坦层在所述衬底上的正投影位于所述有机封装层在所述衬底上的正投影以内；
    第二无机封装层，覆盖所述有机封装层，且在所述衬底上的正投影覆盖所述显示区和所述外围区。
  2. 根据权利要求1所述的显示面板，其中，所述平坦层包括：
    第一平坦层，覆盖所述驱动器件层，所述第一平坦层在所述衬底上的正投影的边界位于所述电路区内；
    第二平坦层，设于所述第一平坦层背离所述衬底的一侧，所述第二平坦层在所述衬底上的正投影的边界位于所述电路区；所述发光层设于所述第二平坦层背离所述衬底的表面。
  3. 根据权利要求2所述的显示面板，其中，所述发光层包括：
    第一电极层，设于所述第二平坦层背离所述衬底的一侧，所述第一电极层包括第一电极和转接部，所述第一电极在所述衬底上的正投影位于所述显示区，所述转接部在所述衬底上的正投影位于所述电路区；
    像素定义层，设于所述第二平坦层背离所述衬底的表面，所述像素定义层在所述衬底上的正投影覆盖所述显示区和所述电路区；所述像素 定义层设有露出所述第一电极的像素开口和露出所述转接部的转接开口；
    发光功能层，覆盖所述像素定义层和所述第一电极，所述发光功能层在所述衬底上的正投影位于所述显示区内；
    第二电极层，覆盖所述发光功能层，所述第二电极层在所述衬底上的正投影的边界位于所述电路区，所述第二电极层通过所述转接开口与所述转接部连接；
    所述第一无机封装层覆盖所述第二电极层。
  4. 根据权利要求3所述的显示面板，其中，所述阻挡坝包括第一坝体和第二坝体，所述第二坝体围绕于所述第一坝体以外。
  5. 根据权利要求4所述的显示面板，其中，所述第一坝体与所述像素定义层同层设置；所述第二坝体包括向背离所述衬底的方向层叠的第一阻挡层和第二阻挡层，所述第一阻挡层与所述第二平坦层同层设置，所述第二阻挡层与所述像素定义层同层设置。
  6. 根据权利要求5所述的显示面板，其中，所述第一电极层还包括：
    延伸部，与所述转接部连接，所述延伸部在所述衬底上的正投影位于所述阻挡区；
    所述第一坝体设于所述延伸部背离所述衬底的表面。
  7. 根据权利要求6所述的显示面板，其中，所述驱动器件层包括：
    有源层，设于所述衬底一侧面，所述有源层在所述衬底上的正投影位于所述显示区和所述电路区；
    第一栅绝缘层，覆盖所述有源层和所述衬底；
    栅极，设于所述第一栅绝缘层背离所述衬底的表面，所述栅极在所述衬底上的正投影位于所述显示区和所述电路区；
    第二栅绝缘层，覆盖所述栅极和所述第一栅绝缘层；
    层间介质层，覆盖所述第二栅绝缘层；
    源漏层，设于所述层间介质层背离所述衬底的表面，所述源漏层在所述衬底上的正投影位于所述显示区和所述电路区；
    所述第一平坦层设于所述源漏层背离所述衬底的一侧；
    所述显示面板还包括：
    连接层，设于所述第一平坦层背离所述衬底的表面，且与所述源漏 层连接，所述连接层在所述衬底上的正投影位于所述显示区；
    信号线，设于所述阻挡坝靠近所述衬底的一侧，所述信号线包括向背离所述衬底的方向依次层叠的第一线层和第二线层，所述第一线层与所述源漏层同层设置，所述第二线层与所述连接层同层设置；所述第二坝体的至少部分区域设于所述第二线层背离所述衬底的表面；
    所述延伸部设于所述信号线背离所述衬底的表面。
  8. 根据权利要求3所述的显示面板，其中，所述第二平坦层设有贯穿所述第二平坦层和所述第一平坦层的第一阻隔槽，所述第一阻隔槽在所述衬底上的正投影位于所述电路区，且围绕所述显示区。
  9. 根据权利要求7所述的显示面板，其中，
    所述层间介质层设有第二阻隔槽，所述第二阻隔槽在所述衬底上的正投影围绕于所述第二坝体以外。
  10. 根据权利要求4所述的显示面板，其中，
    所述第二平坦化层的边界与所述第一坝体的距离为第一距离，所述第二平坦化层的边界与所述第二坝体的距离为第二距离；
    所述第二距离与所述第一距离之比为7/5。
  11. 一种显示面板的制造方法，其中，包括：
    提供一衬底，所述衬底包括显示区和位于所述显示区外的外围区，所述外围区包括沿背离所述显示区的方向依次分布的电路区和阻挡区；
    在所述衬底一侧形成覆盖所述显示区和所述外围区驱动器件层；
    在所述驱动器件层背离所述衬底的一侧形成平坦层，且所述平坦层在所述衬底上的正投影的边界位于所述电路区内；
    在所述驱动器件层背离所述衬底的一侧形成阻挡坝，且所述阻挡坝围绕所述显示区设置，所述阻挡坝在所述衬底上的正投影位于所述阻挡区；
    在所述平坦层背离所述衬底的表面形成发光层，所述发光层在所述衬底上的正投影至少覆盖所述显示区；
    形成覆盖所述发光层和所述阻挡坝的第一无机封装层，所述第一无机封装层在所述衬底上的正投影覆盖所述显示区和所述外围区；
    在所述第一无机封装层背离所述衬底的表面形成液态的有机材料层， 所述有机材料层在所述衬底上的正投影位于所述阻挡坝围绕的范围内，且与所述阻挡坝之间具有间隙；所述平坦层在所述衬底上的正投影的边界位于所述有机材料层在所述衬底上的正投影以内，且与所述有机材料层在所述衬底上的正投影的边界至少部分重合；
    在所述有机材料层流平形成有机封装层后，形成覆盖所述有机材料层的第二无机封装层，在所述第二无机封装层在所述衬底上的正投影覆盖所述显示区和所述外围区。
  12. 根据权利要求11所述的制造方法，其中，在所述驱动器件层背离所述衬底的一侧形成平坦层；包括：
    形成覆盖所述驱动器件层的第一平坦层，所述第一平坦层在所述衬底上的正投影的边界位于所述电路区内；
    在所述第一平坦层背离所述衬底的一侧形成第二平坦层，所述第二平坦层在所述衬底上的正投影的边界位于所述电路区；
    所述发光层设于所述第二平坦层背离所述衬底的表面。
  13. 根据权利要求12所述的制造方法，其中，所述第二平坦层和所述有机材料层在所述衬底上的正投影均为矩形，且所述矩形的相邻两边通过圆角过渡连接；
    所述第二平坦层在所述衬底上的正投影的圆角内切于所述有机材料层在所述衬底上的正投影的圆角。
  14. 根据权利要求12所述的制造方法，其中，在所述第二平坦层背离所述衬底的表面形成发光层；包括：
    在所述第二平坦层背离所述衬底的一侧形成第一电极层，所述第一电极层包括第一电极和转接部，所述第一电极在所述衬底上的正投影位于所述显示区，所述转接部在所述衬底上的正投影位于所述电路区；
    在所述第二平坦层背离所述衬底的表面形成像素定义层，所述像素定义层在所述衬底上的正投影覆盖所述显示区和所述电路区；所述像素定义层设有露出所述第一电极的像素开口和露出所述转接部的转接开口；
    形成覆盖所述像素定义层和所述第一电极发光功能层，所述发光功能层在所述衬底上的正投影位于所述显示区内；
    形成覆盖所述发光功能层的第二电极层，所述第二电极层在所述衬 底上的正投影的边界位于所述电路区，所述第二电极层通过所述转接开口与所述转接部连接；
    所述阻挡坝包括第一坝体和第二坝体，所述第二坝体围绕于所述第一坝体以外；所述第二坝体包括向背离所述衬底的方向层叠的第一阻挡层和第二阻挡层，所述第一阻挡层与所述第二平坦层通过一次构图工艺同时设置，所述第二阻挡层和所述第一坝体与所述像素定义层通过一次构图工艺同时形成。
  15. 根据权利要求14所述的制造方法，其中，所述第一坝体的厚度不大于2μm，所述有机材料层的厚度不小于8μm。
  16. 一种显示装置，其中，包括权利要求1-10任一项所述的显示面板。
PCT/CN2021/131322 2021-03-25 2021-11-17 显示装置、显示面板及其制造方法 WO2022199062A1 (zh)

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CN113571561B (zh) * 2021-07-19 2023-12-01 云谷（固安）科技有限公司 显示面板及显示装置
CN113809112A (zh) * 2021-08-06 2021-12-17 武汉天马微电子有限公司 一种显示面板及显示装置
CN113838996B (zh) * 2021-09-23 2024-03-19 京东方科技集团股份有限公司 显示面板及其制备方法
CN114220821B (zh) * 2021-12-13 2023-07-25 武汉华星光电半导体显示技术有限公司 显示面板
CN115064568A (zh) * 2022-06-14 2022-09-16 京东方科技集团股份有限公司 显示面板及其制造方法、显示装置
CN115275045B (zh) * 2022-07-19 2023-07-04 武汉华星光电半导体显示技术有限公司 显示面板及显示终端
CN115167709A (zh) * 2022-07-26 2022-10-11 京东方科技集团股份有限公司 触控面板及显示装置
CN115581098A (zh) * 2022-11-10 2023-01-06 合肥京东方卓印科技有限公司 显示面板及显示装置
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