WO2023281556A1 - 表示装置およびその駆動方法 - Google Patents

表示装置およびその駆動方法 Download PDF

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Publication number
WO2023281556A1
WO2023281556A1 PCT/JP2021/025247 JP2021025247W WO2023281556A1 WO 2023281556 A1 WO2023281556 A1 WO 2023281556A1 JP 2021025247 W JP2021025247 W JP 2021025247W WO 2023281556 A1 WO2023281556 A1 WO 2023281556A1
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Prior art keywords
scanning signal
transistor
emission control
signal lines
lines
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PCT/JP2021/025247
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English (en)
French (fr)
Japanese (ja)
Inventor
薫 山本
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Sharp Display Technology Corp
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Sharp Display Technology Corp
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Priority to JP2023532859A priority Critical patent/JP7513847B2/ja
Priority to US18/566,949 priority patent/US12190828B2/en
Priority to PCT/JP2021/025247 priority patent/WO2023281556A1/ja
Publication of WO2023281556A1 publication Critical patent/WO2023281556A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0278—Details of driving circuits arranged to drive both scan and data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the following disclosure relates to a display device using display elements driven by current and a driving method thereof.
  • organic EL display devices equipped with pixel circuits including organic EL elements have been put to practical use.
  • An organic EL element also called an OLED (Organic Light-Emitting Diode)
  • OLED Organic Light-Emitting Diode
  • the organic EL display device can be easily made thinner, consumes less power, and has higher brightness than the liquid crystal display device which requires a backlight and a color filter. It is possible to plan for
  • a thin film transistor is typically employed as a drive transistor for controlling current supply to the organic EL element.
  • TFT thin film transistor
  • thin film transistors tend to vary in their characteristics. Specifically, the threshold voltage tends to vary. Variation in the threshold voltage of the drive transistors provided in the display unit causes variation in brightness, thereby deteriorating the display quality. Therefore, various processes (compensation processes) have been proposed to compensate for variations in threshold voltage.
  • compensation processing there is an internal compensation method in which compensation processing is performed by providing a capacitor in the pixel circuit for holding information on the threshold voltage of the drive transistor, and an internal compensation method, for example, by adjusting the magnitude of the current flowing through the drive transistor under predetermined conditions. is measured by a circuit provided outside the pixel circuit, and compensation processing is performed by correcting the video signal based on the measurement result.
  • FIG. 4 of US Pat. No. 1,030,4378 discloses a pixel circuit composed of one organic EL element, six N-channel thin film transistors, and one holding capacitor. Power consumption is reduced by adopting an oxide TFT (a thin film transistor having a channel region formed of an oxide semiconductor) as an N-channel thin film transistor.
  • oxide TFT a thin film transistor having a channel region formed of an oxide semiconductor
  • An organic EL display device having a pixel circuit (the pixel circuit disclosed in FIG. 4 of US Pat. No. 10304378) composed of one organic EL element, six N-channel thin film transistors and one holding capacitor. 35, a first scanning signal line driving circuit 91 for driving the first scanning signal line, a second scanning signal line driving circuit 92 for driving the second scanning signal line, and the first emission control line are connected.
  • a scanning-side drive circuit is provided which includes a first emission control line drive circuit 93 for driving and a second emission control line drive circuit 94 for driving the second emission control line.
  • FIG. 35 shows only the configuration of a portion corresponding to four lines (the same applies to FIGS. 1, 18, 21, 24, 30, and 34).
  • one pixel circuit included in each of the four rows is represented by a rectangle with reference numeral 90. As shown in FIG.
  • the first scanning signal line driving circuit 91, the second scanning signal line driving circuit 92, the first emission control line driving circuit 93, and the second emission control line driving circuit 94 are each configured by a shift register.
  • the first scanning signal line driving circuit 91 is configured by a shift register including unit circuits 910 in a number equal to the number of the first scanning signal lines
  • the second scanning signal line driving circuit 92 is configured by the second scanning signal line.
  • the first emission control line driving circuit 93 is constituted by a shift register including unit circuits 920 in a number equal to the number of the first emission control lines.
  • the two-emission control line drive circuit 94 is composed of a shift register including unit circuits 940 whose number is equal to the number of the second emission control lines.
  • the following disclosure aims to realize a narrow frame of a display device using a display element driven by current.
  • a display device is a display device using a display element driven by current, a plurality of data signal lines, a plurality of first scanning signal lines, a plurality of second scanning signal lines, a plurality of first emission control lines, a plurality of second emission control lines, a first power supply line, a a display unit including two power supply lines, an initialization power supply line, and a plurality of pixel circuits; a data side driving circuit that applies data signals to the plurality of data signal lines; a first scanning signal line driving circuit that selectively drives the plurality of first scanning signal lines; a second scanning signal line driving circuit that selectively drives the plurality of second scanning signal lines; a scanning side drive circuit including a light emission control line drive circuit that selectively drives one light emission control line and the plurality of second light emission control lines;
  • Each of the plurality of pixel circuits includes one of the plurality of data signal lines, one of the plurality of first scanning signal lines, one of the plurality of second scanning signal lines, and the plurality
  • each of the plurality of pixel circuits, the display element having a first terminal and a second terminal connected to the second power supply line; a drive transistor having a control terminal, a first conduction terminal, and a second conduction terminal and provided in series with the display element; a holding capacitor having one end connected to the control terminal of the drive transistor; A write having a control terminal connected to a corresponding second scanning signal line, a first conduction terminal connected to a corresponding data signal line, and a second conduction terminal connected to the second conduction terminal of the drive transistor.
  • control transistor It has a control terminal connected to a corresponding first scanning signal line, a first conduction terminal connected to the first conduction terminal of the drive transistor, and a second conduction terminal connected to the control terminal of the drive transistor.
  • a threshold voltage compensation transistor A power supply having a control terminal connected to a corresponding second emission control line, a first conduction terminal connected to the first power supply line, and a second conduction terminal connected to the first conduction terminal of the drive transistor.
  • a supply control transistor a control terminal connected to the corresponding first emission control line, a first conduction terminal connected to the second conduction terminal of the drive transistor, and a second conduction terminal connected to the first terminal of the display element; a light emission control transistor having An initialization having a control terminal connected to the corresponding first scanning signal line, a first conduction terminal connected to the first terminal of the display element, and a second conduction terminal connected to the initialization power supply line.
  • the first scanning signal line driving circuit is configured by a shift register including a number of unit circuits equal to the number of the plurality of first scanning signal lines, where Q is an integer equal to or greater than 2, the second scanning signal line driving circuit is composed of a shift register including a number of unit circuits equal to 1/Q of the number of the plurality of second scanning signal lines, a unit circuit included in a shift register constituting the first scanning signal line driving circuit drives a corresponding first scanning signal line; a unit circuit included in a shift register constituting the second scanning signal line driving circuit collectively drives the corresponding Q second scanning signal lines and the Q second scanning signal lines adjacent to each other; During the period in which the power supply control transistor and the light emission control transistor are maintained in the off state in all of the pixel circuits connected to each of the Q second scanning signal lines driven collectively, the collectively Q second scanning lines driven collectively during a period in which the write control transistors are maintained in an ON state in all pixel circuits connected to each of the Q second scanning signal lines to be driven;
  • a display device is a display device using a display element driven by current, a plurality of data signal lines, a plurality of first scanning signal lines, a plurality of second scanning signal lines, a plurality of third scanning signal lines, a plurality of first emission control lines, and a plurality of second emission control lines a display unit including a first power supply line, a second power supply line, an initialization power supply line, and a plurality of pixel circuits; a data side driving circuit that applies data signals to the plurality of data signal lines; a first scanning signal line driving circuit that selectively drives the plurality of first scanning signal lines; a second scanning signal line driving circuit that selectively drives the plurality of second scanning signal lines; a third scanning signal line driving circuit that selectively drives three scanning signal lines; and an emission control line driving circuit that selectively drives the plurality of first emission control lines and the plurality of second emission control lines.
  • Each of the plurality of pixel circuits includes one of the plurality of data signal lines, one of the plurality of first scanning signal lines, one of the plurality of second scanning signal lines, and the plurality of third scanning signals. corresponding to one of the lines, one of the plurality of first emission control lines, and one of the plurality of second emission control lines; each of the plurality of pixel circuits, the display element having a first terminal and a second terminal connected to the second power supply line; a drive transistor having a control terminal, a first conduction terminal, and a second conduction terminal and provided in series with the display element; a holding capacitor having one end connected to the control terminal of the drive transistor; A write having a control terminal connected to a corresponding second scanning signal line, a first conduction terminal connected to a corresponding data signal line, and a second conduction terminal connected to the second conduction terminal of the drive transistor.
  • control transistor It has a control terminal connected to a corresponding first scanning signal line, a first conduction terminal connected to the first conduction terminal of the drive transistor, and a second conduction terminal connected to the control terminal of the drive transistor.
  • a threshold voltage compensation transistor A power supply having a control terminal connected to a corresponding second emission control line, a first conduction terminal connected to the first power supply line, and a second conduction terminal connected to the first conduction terminal of the drive transistor.
  • a supply control transistor a control terminal connected to the corresponding first emission control line, a first conduction terminal connected to the second conduction terminal of the drive transistor, and a second conduction terminal connected to the first terminal of the display element; a light emission control transistor having An initialization having a control terminal connected to a corresponding third scanning signal line, a first conduction terminal connected to the first terminal of the display element, and a second conduction terminal connected to the initialization power supply line.
  • the first scanning signal line driving circuit is configured by a shift register including a number of unit circuits equal to the number of the plurality of first scanning signal lines, where Q is an integer equal to or greater than 2, the second scanning signal line driving circuit is composed of a shift register including a number of unit circuits equal to 1/Q of the number of the plurality of second scanning signal lines,
  • the third scanning signal line driving circuit is configured by a shift register including a number of unit circuits equal to 1/Q of the number of the plurality of third scanning signal lines, a unit circuit included in a shift register constituting the first scanning signal line driving circuit drives a corresponding first scanning signal line; a unit circuit included in a shift register constituting the second scanning signal line driving circuit collectively drives the corresponding Q second scanning signal lines and the Q second scanning signal lines adjacent to each other; a unit circuit included in a shift register constituting the third scanning signal line driving circuit collectively drives Q third scanning signal lines corresponding to each other and adjacent to each other; In all of the pixel circuits connected to the Q second scanning signal
  • a driving method (of a display device) is a driving method of a display device using a display element driven by current, comprising: The display device a plurality of data signal lines, a plurality of first scanning signal lines, a plurality of second scanning signal lines, a plurality of first emission control lines, a plurality of second emission control lines, a first power supply line, a a display unit including two power supply lines, an initialization power supply line, and a plurality of pixel circuits; a data side driving circuit that applies data signals to the plurality of data signal lines; a first scanning signal line driving circuit that selectively drives the plurality of first scanning signal lines; a second scanning signal line driving circuit that selectively drives the plurality of second scanning signal lines; a scanning side drive circuit including a light emission control line drive circuit that selectively drives one light emission control line and the plurality of second light emission control lines; Each of the plurality of pixel circuits includes one of the plurality of data signal lines, one of the plurality of first scanning
  • each of the plurality of pixel circuits, the display element having a first terminal and a second terminal connected to the second power supply line; a drive transistor having a control terminal, a first conduction terminal, and a second conduction terminal and provided in series with the display element; a holding capacitor having one end connected to the control terminal of the drive transistor; A write having a control terminal connected to a corresponding second scanning signal line, a first conduction terminal connected to a corresponding data signal line, and a second conduction terminal connected to the second conduction terminal of the drive transistor.
  • control transistor It has a control terminal connected to a corresponding first scanning signal line, a first conduction terminal connected to the first conduction terminal of the drive transistor, and a second conduction terminal connected to the control terminal of the drive transistor.
  • a threshold voltage compensation transistor A power supply having a control terminal connected to a corresponding second emission control line, a first conduction terminal connected to the first power supply line, and a second conduction terminal connected to the first conduction terminal of the drive transistor.
  • a supply control transistor a control terminal connected to the corresponding first emission control line, a first conduction terminal connected to the second conduction terminal of the drive transistor, and a second conduction terminal connected to the first terminal of the display element; a light emission control transistor having An initialization having a control terminal connected to the corresponding first scanning signal line, a first conduction terminal connected to the first terminal of the display element, and a second conduction terminal connected to the initialization power supply line.
  • the first scanning signal line driving circuit is configured by a shift register including a number of unit circuits equal to the number of the plurality of first scanning signal lines, where Q is an integer equal to or greater than 2, the second scanning signal line driving circuit is composed of a shift register including a number of unit circuits equal to 1/Q of the number of the plurality of second scanning signal lines, a unit circuit included in a shift register constituting the first scanning signal line driving circuit drives a corresponding first scanning signal line; a unit circuit included in a shift register constituting the second scanning signal line driving circuit collectively drives the corresponding Q second scanning signal lines and the Q second scanning signal lines adjacent to each other;
  • the driving method is a data writing step of writing the data signal to the plurality of pixel circuits; a pause step of stopping the writing of the data signal to the plurality of pixel circuits for a period of one frame period or longer; In the data writing step, in all pixel circuits connected to Q second scanning signal lines driven collectively, the write control transistor and the light emission control transistor are in an
  • the Q second scanning signal lines are driven together.
  • the Q second scanning signal lines are driven together.
  • the threshold voltage compensating transistor, the initialization transistor, and the power supply control transistor are turned off in all of the pixel circuits connected to the Q second scanning signal lines that are driven together. Further, the Q second scanning signal lines driven together are kept in a selected state for a predetermined period during the period in which the light emission control transistors are maintained in the ON state, thereby the Q number of second scanning signal lines driven together are selected.
  • a voltage of the first terminal of the display element is initialized in the pixel circuit connected to each of the second scanning signal lines.
  • a driving method (of a display device) is a driving method of a display device using a display element driven by current, comprising: The display device a plurality of data signal lines, a plurality of first scanning signal lines, a plurality of second scanning signal lines, a plurality of third scanning signal lines, a plurality of first emission control lines, and a plurality of second emission control lines a display unit including a first power supply line, a second power supply line, an initialization power supply line, and a plurality of pixel circuits; a data side driving circuit that applies data signals to the plurality of data signal lines; a first scanning signal line driving circuit that selectively drives the plurality of first scanning signal lines; a second scanning signal line driving circuit that selectively drives the plurality of second scanning signal lines; a third scanning signal line driving circuit that selectively drives three scanning signal lines; and an emission control line driving circuit that selectively drives the plurality of first emission control lines and the plurality of second emission control lines.
  • Each of the plurality of pixel circuits includes one of the plurality of data signal lines, one of the plurality of first scanning signal lines, one of the plurality of second scanning signal lines, and the plurality of third scanning signals. corresponding to one of the lines, one of the plurality of first emission control lines, and one of the plurality of second emission control lines; each of the plurality of pixel circuits, the display element having a first terminal and a second terminal connected to the second power supply line; a drive transistor having a control terminal, a first conduction terminal, and a second conduction terminal and provided in series with the display element; a holding capacitor having one end connected to the control terminal of the drive transistor; A write having a control terminal connected to a corresponding second scanning signal line, a first conduction terminal connected to a corresponding data signal line, and a second conduction terminal connected to the second conduction terminal of the drive transistor.
  • control transistor It has a control terminal connected to a corresponding first scanning signal line, a first conduction terminal connected to the first conduction terminal of the drive transistor, and a second conduction terminal connected to the control terminal of the drive transistor.
  • a threshold voltage compensation transistor A power supply having a control terminal connected to a corresponding second emission control line, a first conduction terminal connected to the first power supply line, and a second conduction terminal connected to the first conduction terminal of the drive transistor.
  • a supply control transistor a control terminal connected to the corresponding first emission control line, a first conduction terminal connected to the second conduction terminal of the drive transistor, and a second conduction terminal connected to the first terminal of the display element; a light emission control transistor having An initialization having a control terminal connected to a corresponding third scanning signal line, a first conduction terminal connected to the first terminal of the display element, and a second conduction terminal connected to the initialization power supply line.
  • the first scanning signal line driving circuit is configured by a shift register including a number of unit circuits equal to the number of the plurality of first scanning signal lines, where Q is an integer equal to or greater than 2, the second scanning signal line driving circuit is composed of a shift register including a number of unit circuits equal to 1/Q of the number of the plurality of second scanning signal lines,
  • the third scanning signal line driving circuit is configured by a shift register including a number of unit circuits equal to 1/Q of the number of the plurality of third scanning signal lines, a unit circuit included in a shift register constituting the first scanning signal line driving circuit drives a corresponding first scanning signal line; a unit circuit included in a shift register constituting the second scanning signal line driving circuit collectively drives the corresponding Q second scanning signal lines and the Q second scanning signal lines adjacent to each other; a unit circuit included in a shift register constituting the third scanning signal line driving circuit collectively drives Q third scanning signal lines corresponding to each other and adjacent to each other;
  • the driving method is a data writing step of writing the data signal
  • the Q second scans driven together By sequentially setting the Q first scanning signal lines corresponding to the signal lines to the selected state for each predetermined period, they are connected to the Q second scanning signal lines driven collectively, and After initializing the holding voltage of the holding capacitor and the voltage of the first terminal of the display element in the pixel circuits connected to each of the Q third scanning signal lines driven by the The light emission control transistor and the power supply control in all of the pixel circuits connected to each of the Q second scanning signal lines and connected to each of the Q third scanning signal lines driven together.
  • the Q third scanning lines are connected to the Q second scanning signal lines that are driven together and that are driven together. writing the data signal to the pixel circuit connected to each of the signal lines; In the resting step, the pixel circuits connected to each of the Q second scanning signal lines driven together and connected to each of the Q third scanning signal lines driven together are activated.
  • the threshold voltage compensating transistor and the write control transistor are kept in an OFF state and the power supply control transistor is kept in an ON state, and Q number of second scanning signal lines corresponding to the Q number of second scanning signal lines driven collectively are maintained.
  • the grouping is performed.
  • the first terminal of the display element in the pixel circuit connected to each of Q second scanning signal lines driven together and connected to each of Q third scanning signal lines driven collectively voltage is initialized.
  • the second scanning signal line driving circuit drives the number of second scanning signal lines so that Q is an integer equal to or greater than 2, and Q second scanning signal lines are driven at a time. It is composed of a shift register that includes a number of unit circuits equal to 1/Q. This reduces the area of the circuit region required around the display section to drive the second scanning signal lines. That is, it is possible to reduce the area of the frame region. As described above, it is possible to narrow the frame of a display device having a pixel circuit composed of one display element (display element driven by current), six transistors, and one holding capacitor.
  • the second scanning signal line driving circuit drives the second scanning signal lines such that Q is an integer equal to or greater than 2, and Q second scanning signal lines are driven.
  • the third scanning signal line driving circuit is composed of a shift register including a number of unit circuits equal to 1/Q of the number, and the number of the third scanning signal line driving circuits is equal to the number of the third scanning signal lines so that the Q third scanning signal lines are driven at a time. It is composed of a shift register that includes a number of unit circuits equal to 1/Q. This reduces the area of the circuit region required around the display section to drive the second scanning signal lines and the third scanning signal lines. That is, it is possible to reduce the area of the frame region. As described above, it is possible to narrow the frame of a display device having a pixel circuit composed of one display element (display element driven by current), six transistors, and one holding capacitor.
  • FIG. 3 is a block diagram showing a schematic configuration of a scanning-side drive circuit according to the first embodiment
  • FIG. 1 is a block diagram showing the overall configuration of an organic EL display device according to the first embodiment
  • FIG. 2 is a circuit diagram showing the configuration of a pixel circuit in the first embodiment
  • FIG. 4 is a timing chart for explaining the operation of the pixel circuit during the drive period in the first embodiment
  • 4 is a timing chart for explaining the operation of the pixel circuit during the pause period in the first embodiment
  • 3 is a block diagram showing the configuration of a first scanning signal line driving circuit in the first embodiment
  • FIG. 3 is a circuit diagram showing a configuration of a unit circuit included in a shift register that constitutes a first scanning signal line driving circuit in the first embodiment
  • FIG. 4 is a timing chart for explaining the operation of a unit circuit included in a shift register that configures the first scanning signal line drive circuit in the first embodiment
  • 3 is a block diagram showing the configuration of a second scanning signal line driving circuit in the first embodiment
  • FIG. 3 is a circuit diagram showing a configuration of a unit circuit included in a shift register that constitutes a second scanning signal line driving circuit in the first embodiment
  • FIG. 4 is a timing chart for explaining the operation of a unit circuit included in a shift register that constitutes the second scanning signal line driving circuit in the first embodiment
  • 4 is a block diagram showing the configuration of a first emission control line drive circuit in the first embodiment
  • FIG. It is a block diagram which shows the structure of the 2nd emission control line drive circuit in the said 1st Embodiment.
  • FIG. 4 is a circuit diagram showing the configuration of a unit circuit included in a shift register that constitutes the first emission control line drive circuit in the first embodiment;
  • FIG. 4 is a timing chart for explaining the operation of a unit circuit included in a shift register that constitutes the first emission control line drive circuit in the first embodiment;
  • FIG. 4 is a timing chart for explaining the overall operation during the drive period in the first embodiment;
  • FIG. 4 is a timing chart for explaining the overall operation during a rest period in the first embodiment;
  • FIG. FIG. 11 is a block diagram showing a schematic configuration of a scanning-side drive circuit in a first modification of the first embodiment;
  • FIG. 10 is a timing chart for explaining the operation of the pixel circuit during the driving period in the first modification of the first embodiment;
  • FIG. 9 is a timing chart for explaining the operation of the pixel circuit during the pause period in the first modification of the first embodiment;
  • FIG. 9 is a block diagram showing a schematic configuration of a scanning-side drive circuit in a second modification of the first embodiment;
  • FIG. 9 is a timing chart for explaining the operation of the pixel circuit during the drive period in the second modification of the first embodiment;
  • FIG. 10 is a timing chart for explaining the operation of the pixel circuit during the idle period in the second modification of the first embodiment;
  • FIG. FIG. 11 is a block diagram showing a schematic configuration of a scanning-side drive circuit according to a second embodiment;
  • FIG. It is a block diagram which shows the structure of the light emission control line drive circuit in the said 2nd Embodiment.
  • FIG. 9 is a block diagram showing a schematic configuration of a scanning-side drive circuit in a second modification of the first embodiment.
  • FIG. 9 is a timing chart for explaining the operation of the pixel circuit during the drive period in the second modification of the
  • FIG. 11 is a timing chart for explaining the operation of the pixel circuit during the pause period in the second embodiment;
  • FIG. FIG. 11 is a circuit diagram showing the configuration of a pixel circuit in a third embodiment;
  • FIG. FIG. 13 is a timing chart for explaining the operation of the pixel circuit during the drive period in the third embodiment;
  • FIG. FIG. 12 is a timing chart for explaining the operation of the pixel circuit during the idle period in the third embodiment;
  • FIG. FIG. 11 is a block diagram showing a schematic configuration of a scanning-side drive circuit in the third embodiment;
  • FIG. 11 is a block diagram showing the configuration of a third scanning signal line driving circuit in the third embodiment;
  • FIG. 11 is a timing chart for explaining the overall operation during the driving period in the third embodiment;
  • FIG. 11 is a timing chart for explaining the overall operation during a rest period in the third embodiment;
  • FIG. 11 is a block diagram showing a schematic configuration of a scanning-side drive circuit in a modified example of the third embodiment;
  • FIG. 11 is a block diagram showing a schematic configuration of a scanning-side drive circuit in a conventional example;
  • FIG. 2 is a block diagram showing the overall configuration of the organic EL display device according to the first embodiment.
  • this organic EL display device includes a display control circuit 100, a display section 200, a scanning side driving circuit 300, and a data side driving circuit 400.
  • FIG. A scanning side driving circuit 300 and a data side driving circuit 400 are included in the organic EL display panel 5 having the display portion 200 .
  • the scanning side driver circuit 300 is monolithic.
  • the data side driver circuit 400 may or may not be monolithic.
  • the display unit 200 includes i first scanning signal lines SCAN1(1) to SCAN1(i), i second scanning signal lines SCAN2(1) to SCAN2(i), and i first emission control lines. EM1(1) to EM1(i), i second emission control lines EM2(1) to EM2(i), and j data signal lines D(1) to D(j) are arranged. . Each first scanning signal line SCAN1 transmits a first scanning signal, each second scanning signal line SCAN2 transmits a second scanning signal, each first emission control line EM1 transmits a first emission control signal, and each A second emission control line EM2 transmits a second emission control signal.
  • the display unit 200 is also provided with i ⁇ j pixel circuits 20 .
  • Each of the i ⁇ j pixel circuits 20 includes one of the i first scanning signal lines SCAN1(1) to SCAN1(i) and the i second scanning signal lines SCAN2(1) to SCAN2(i). ), one of i first emission control lines EM1(1) to EM1(i), one of i second emission control lines EM2(1) to EM2(i), and j corresponds to one of the data signal lines D(1) to D(j).
  • First scanning signal lines SCAN1(1) to SCAN1(i), second scanning signal lines SCAN2(1) to SCAN2(i), first emission control lines EM1(1) to EM1(i), and second emission control lines EM2(1) to EM2(i) are typically parallel to each other.
  • the first scanning signal lines SCAN1(1) to SCAN1(i) are orthogonal to the data signal lines D(1) to D(j).
  • the first scanning signals respectively applied to the first scanning signal lines SCAN1(1) to SCAN1(i) are denoted by SCAN1(1) to SCAN1(i) as required, and the second scanning signal lines
  • the second scanning signals supplied to SCAN2(1) to SCAN2(i) are also labeled SCAN2(1) to SCAN2(i) and supplied to the first emission control lines EM1(1) to EM1(i), respectively.
  • Codes EM1(1) to EM1(i) are also given to the first emission control signals supplied to the second emission control lines EM2(1) to EM2(i), and codes EM2 ( 1) to EM2(i), and data signals applied to data signal lines D(1) to D(j), respectively, are also denoted by D(1) to D(j).
  • a power supply line (not shown) common to each pixel circuit 20 is arranged. More specifically, a power supply line for supplying a high level power supply voltage ELVDD for driving the organic EL elements (hereinafter referred to as a "high level power supply line”) and a low level power supply voltage ELVSS for driving the organic EL elements.
  • a power supply line (hereinafter referred to as “low-level power supply line”) and a power supply line (hereinafter referred to as "initialization power supply line”) for supplying initialization voltage Vini are provided.
  • a high-level power supply voltage ELVDD, a low-level power supply voltage ELVSS, and an initialization voltage Vini are supplied from a power supply circuit (not shown).
  • the high-level power line corresponds to the first power line
  • the low-level power line corresponds to the second power line.
  • the display control circuit 100 receives an input image signal DIN and a timing signal group (horizontal synchronizing signal, vertical synchronizing signal, etc.) TG sent from the outside, and controls the digital video signal DV and the operation of the scanning side driving circuit 300. It outputs a signal SCTL and a control signal DCTL for controlling the operation of the data side driving circuit 400 .
  • a timing signal group horizontal synchronizing signal, vertical synchronizing signal, etc.
  • the scanning side drive circuit 300 includes first scanning signal lines SCAN1(1) to SCAN1(i), second scanning signal lines SCAN2(1) to SCAN2(i), first emission control lines EM1(1) to EM1(i), and first scanning signal lines SCAN2(1) to SCAN2(i). ), and the second emission control lines EM2(1) to EM2(i).
  • the scanning-side driving circuit 300 applies the first scanning signal to the first scanning signal lines SCAN1(1) to SCAN1(i) based on the control signal SCTL output from the display control circuit 100, and applies the first scanning signal to the second scanning signal lines.
  • a second scanning signal is applied to SCAN2(1) to SCAN2(i), a first emission control signal is applied to first emission control lines EM1(1) to EM1(i), and a second emission control line EM2(1 ) to EM2(i).
  • the scan-side drive circuit 300 is also supplied with a high-level power supply voltage GVDD and a low-level power supply voltage GVSS for controlling the operation of each unit circuit, which will be described later. The detailed configuration and operation of the scanning side drive circuit 300 will be described later.
  • the data side drive circuit 400 is connected to the data signal lines D(1) to D(j).
  • the data side drive circuit 400 includes a j-bit shift register, a sampling circuit, a latch circuit, and j D/A converters (not shown).
  • the shift register has j registers connected in cascade.
  • the shift register sequentially transfers the start pulse included in the control signal DCTL from the input end (first stage register) to the output end (final stage register) based on the clock signal included in the control signal DCTL.
  • a sampling pulse is output from each stage of the shift register.
  • the sampling circuit stores the digital video signal DV.
  • the latch circuit takes in and holds the digital video signal DV for one row stored in the sampling circuit according to the latch strobe signal included in the control signal DCTL.
  • a D/A converter is provided to correspond to each data signal line D(1) to D(j).
  • the D/A converter converts the digital video signal DV held in the latch circuit into an analog voltage.
  • the converted analog voltage is applied as a data signal to all data signal lines D(1) to D(j) all at once.
  • data signals are applied to the data signal lines D(1) to D(j), first scanning signals are applied to the first scanning signal lines SCAN1(1) to SCAN1(i), and second scanning signal lines SCAN1(1) to SCAN1(i) are applied.
  • a second scanning signal is applied to the scanning signal lines SCAN2(1) to SCAN2(i)
  • a first emission control signal is applied to the first emission control lines EM1(1) to EM1(i)
  • a second emission control line is applied.
  • An image based on the input image signal DIN is displayed on the display unit 200 by applying the second emission control signal to EM2(1) to EM2(i).
  • the pixel circuit 20 shown in FIG. 3 includes one organic EL element (organic light emitting diode) 21 as a display element, and six transistors T1 to T6 (write control transistor T1, drive transistor T2, threshold voltage compensation transistor T3, It includes a power supply control transistor T4, a light emission control transistor T5, an initialization transistor T6), and one holding capacitor Cst.
  • the transistors T1 to T6 are thin film transistors (hereinafter referred to as "oxide TFTs") having channel regions made of an oxide semiconductor, and are of the N-channel type.
  • a thin film transistor having a channel region formed of an oxide semiconductor containing indium, gallium, zinc, and oxygen is typically employed as the oxide TFT.
  • the holding capacitor Cst is a capacitive element consisting of two electrodes (first electrode and second electrode).
  • the control terminal is connected to the second scanning signal line SCAN2, the first conduction terminal is connected to the data signal line D, and the second conduction terminal is connected to the second conduction terminal of the drive transistor T2 and the light emission control transistor. It is connected to the first conducting terminal of T5.
  • the control terminal is connected to the second conduction terminal of the threshold voltage compensation transistor T3 and the first electrode of the holding capacitor Cst, and the first conduction terminal is connected to the first conduction terminal of the threshold voltage compensation transistor T3.
  • the second conduction terminal of the control transistor T4 is connected to the second conduction terminal of the write control transistor T1 and the first conduction terminal of the light emission control transistor T5.
  • the control terminal is connected to the first scanning signal line SCAN1
  • the first conduction terminal is connected to the second conduction terminal of the power supply control transistor T4 and the first conduction terminal of the drive transistor T2
  • the second conductive terminal is connected to the control terminal of the driving transistor T2 and the first electrode of the holding capacitor Cst.
  • the control terminal is connected to the second emission control line EM2
  • the first conduction terminal is connected to the high level power supply line
  • the second conduction terminal is connected to the first conduction terminal of the drive transistor T2 and the threshold voltage It is connected to the first conduction terminal of the compensation transistor T3.
  • the emission control transistor T5 the control terminal is connected to the first emission control line EM1
  • the first conduction terminal is connected to the second conduction terminal of the write control transistor T1 and the second conduction terminal of the drive transistor T2
  • the second conduction terminal is connected to the second conduction terminal of the drive transistor T2.
  • the conduction terminal is connected to the first conduction terminal of the initialization transistor T6, the anode terminal of the organic EL element 21, and the second electrode of the holding capacitor Cst.
  • the initialization transistor T6 has a control terminal connected to the first scanning signal line SCAN1, and a first conduction terminal connected to the second conduction terminal of the light emission control transistor T5, the anode terminal of the organic EL element 21, and the second electrode of the holding capacitor Cst. and the second conduction terminal is connected to the initialization power supply line.
  • the first electrode is connected to the control terminal of the drive transistor T2 and the second conduction terminal of the threshold voltage compensation transistor T3, and the second electrode is connected to the second conduction terminal of the emission control transistor T5 and the initialization transistor T6. and the anode terminal of the organic EL element 21 .
  • the anode terminal is connected to the second conduction terminal of the light emission control transistor T5, the first conduction terminal of the initialization transistor T6, and the second electrode of the holding capacitor Cst, and the cathode terminal is connected to the low level power supply line. It is connected.
  • the anode terminal corresponds to the first terminal
  • the cathode terminal corresponds to the second terminal.
  • the node connected to the first conduction terminal of the drive transistor T2, the first conduction terminal of the threshold voltage compensation transistor T3, and the second conduction terminal of the power supply control transistor T4 is denoted by N1.
  • a node connected to the control terminal of the drive transistor T2, the second conduction terminal of the threshold voltage compensating transistor T3, and the first electrode of the holding capacitor Cst is denoted by N2.
  • a node connected to the first conduction terminal of the conversion transistor T6, the anode terminal of the organic EL element 21, and the second electrode of the holding capacitor Cst is denoted by N3.
  • pause drive also called intermittent drive or low-frequency drive
  • a drive period (refresh period) and a rest period (non-refresh period) are provided.
  • This is a drive method that stops the operation. In this way, during the idle period, the writing of the data signal D to all the pixel circuits 20 is stopped for a period of one frame period or longer.
  • Pause driving can be applied when the transistors in the pixel circuit 20 have good off-leak characteristics (low off-leak current). Therefore, as described above, oxide TFTs are employed for the transistors T1 to T6 in the pixel circuit 20 in this embodiment.
  • the operation of the pixel circuit 20 shown in FIG. 3 will be described.
  • the first scanning signal lines SCAN1(1) to SCAN1(i) are driven one by one.
  • (1) to EM1(i) and the second emission control lines EM2(1) to EM2(i) are driven two by two. Therefore, here, where n is an even number, two pixel circuits 20 adjacent to each other in the direction in which the data signal line D extends are focused on the pixel circuit 20 on the (n ⁇ 1)th row and the pixel circuit 20 on the nth row. do.
  • the pixel circuit 20 in the (n-1)th row will be referred to as the "first pixel circuit”
  • the pixel circuit 20 in the nth row will be referred to as the "second pixel circuit”.
  • FIG. 4 does not accurately represent the length of the period during which each signal is maintained at high level or low level (the same applies to other drawings showing timing charts).
  • a data write step is realized by the operation during this driving period.
  • the first scanning signal SCAN1(n-1), the first scanning signal SCAN1(n), the second scanning signal SCAN2(n-1), and the second scanning signal SCAN2(n) are is low level, and the first emission control signal EM1(n-1), the first emission control signal EM1(n), the second emission control signal EM2(n-1), and the second emission control signal EM2(n) are High level.
  • the write control transistor T1, the threshold voltage compensation transistor T3, and the initialization transistor T6 are in the off state, and the power supply control transistor T4 and the light emission control transistor T5 are in the on state. be. Therefore, the organic EL element 21 emits light according to the magnitude of the drive current.
  • the first emission control signal EM1(n-1) and the first emission control signal EM1(n) change from high level to low level.
  • the light emission control transistor T5 is turned off in the first pixel circuit and the second pixel circuit.
  • the current supply to the organic EL element 21 is cut off, and the organic EL element 21 is turned off.
  • the first scanning signal SCAN1(n-1) changes from low level to high level.
  • the threshold voltage compensation transistor T3 and the initialization transistor T6 are turned on in the first pixel circuit.
  • the power supply control transistor T4 is maintained in the ON state.
  • the node N2 is supplied with the high-level power supply voltage ELVDD, and the node N3 is supplied with the initialization voltage Vini.
  • the holding voltage of the holding capacitor Cst and the anode voltage of the organic EL element 21 are initialized in the first pixel circuit.
  • the first scanning signal SCAN1(n-1) changes from high level to low level.
  • the threshold voltage compensation transistor T3 and the initialization transistor T6 are turned off in the first pixel circuit.
  • the first scanning signal SCAN1(n) changes from low level to high level.
  • the threshold voltage compensation transistor T3 and the initialization transistor T6 are turned on in the second pixel circuit.
  • the power supply control transistor T4 is maintained in the ON state.
  • the high-level power supply voltage ELVDD is applied to the node N2
  • the initialization voltage Vini is applied to the node N3.
  • the holding voltage of the holding capacitor Cst and the anode voltage of the organic EL element 21 are initialized in the second pixel circuit.
  • the first scanning signal SCAN1(n) changes from high level to low level.
  • the threshold voltage compensation transistor T3 and the initialization transistor T6 are turned off.
  • the second emission control signal EM2(n-1) and the second emission control signal EM2(n) change from high level to low level.
  • the power supply control transistor T4 is turned off in the first pixel circuit and the second pixel circuit.
  • the second scanning signal SCAN2(n-1) and the second scanning signal SCAN2(n) change from low level to high level.
  • the write control transistor T1 is turned on in the first pixel circuit and the second pixel circuit.
  • the first scanning signal SCAN1(n-1) changes from low level to high level.
  • the threshold voltage compensation transistor T3 and the initialization transistor T6 are turned on in the first pixel circuit.
  • the power supply control transistor T4 and the light emission control transistor T5 are in an off state.
  • the data signal D is applied to the node N2 through the write control transistor T1, the drive transistor T2, and the threshold voltage compensation transistor T3, and the initialization voltage Vini is applied to the node N2 through the initialization transistor T6. Given to N3.
  • the holding capacitor Cst is charged with a voltage corresponding to the data signal D so as to compensate for variations in the threshold voltage of the driving transistor T2.
  • reference numeral 61 is attached to the portion where the data signal D is the voltage for the first pixel circuit.
  • the first scanning signal SCAN1(n-1) changes from high level to low level.
  • the threshold voltage compensation transistor T3 and the initialization transistor T6 are turned off in the first pixel circuit.
  • the first scanning signal SCAN1(n) changes from low level to high level.
  • the threshold voltage compensation transistor T3 and the initialization transistor T6 are turned on in the second pixel circuit.
  • the power supply control transistor T4 and the light emission control transistor T5 are in an off state.
  • the data signal D is applied to the node N2 through the write control transistor T1, the drive transistor T2, and the threshold voltage compensation transistor T3, and the initialization voltage Vini is applied to the node N2 through the initialization transistor T6. Given to N3.
  • the holding capacitor Cst is charged with a voltage corresponding to the data signal D so as to compensate for variations in the threshold voltage of the driving transistor T2.
  • reference numeral 62 is attached to the portion where the data signal D is the voltage for the second pixel circuit.
  • the first scanning signal SCAN1(n) changes from high level to low level.
  • the threshold voltage compensation transistor T3 and the initialization transistor T6 are turned off.
  • the second scanning signal SCAN2(n-1) and the second scanning signal SCAN2(n) change from high level to low level.
  • the write control transistor T1 is turned off in the first pixel circuit and the second pixel circuit.
  • the first emission control signal EM1(n-1) and the first emission control signal EM1(n) change from low level to high level.
  • the light emission control transistor T5 is turned on in the first pixel circuit and the second pixel circuit.
  • the power supply control transistor T4 is kept off. Therefore, in the first pixel circuit and the second pixel circuit, the organic EL element 21 is maintained in the off state.
  • the second emission control signal EM2(n-1) and the second emission control signal EM2(n) change from low level to high level.
  • the power supply control transistor T4 is turned on in the first pixel circuit and the second pixel circuit.
  • a driving current corresponding to the charging voltage (holding voltage) of the holding capacitor Cst is supplied to the organic EL element 21, and the organic EL element is driven according to the magnitude of the driving current. 21 emits light.
  • the organic light is emitted in the first pixel circuit and the second pixel circuit.
  • the EL element 21 emits light.
  • An anode reset voltage (a voltage for initializing the anode voltage of the organic EL element 21) is applied to the data signal line D throughout the pause period.
  • the low-level power supply voltage ELVSS is applied to the data signal line D as the anode reset voltage.
  • the first scanning signal SCAN1(n ⁇ 1) and the first scanning signal SCAN1(n) are maintained at a low level throughout the idle period, and the first emission control signal EM1(n ⁇ 1) and the first emission control signal EM1 are maintained at a low level. (n) is maintained at a high level.
  • a rest step is realized by the operation during this rest period.
  • the organic EL element 21 is driven in accordance with the magnitude of the drive current, similarly to the time just before time t01 (see FIG. 4) in the drive period. It is emitting light.
  • the second emission control signal EM2(n-1) and the second emission control signal EM2(n) change from high level to low level.
  • the power supply control transistor T4 is turned off in the first pixel circuit and the second pixel circuit.
  • the current supply to the organic EL element 21 is cut off, and the organic EL element 21 is turned off.
  • the second scanning signal SCAN2(n-1) and the second scanning signal SCAN2(n) change from low level to high level.
  • the write control transistor T1 is turned on in the first pixel circuit and the second pixel circuit.
  • the light emission control transistor T5 is in the ON state, and the low level power supply voltage ELVSS is applied to the data signal line D as described above.
  • the low-level power supply voltage ELVSS is applied to the node N3 through the write control transistor T1 and the light emission control transistor T5.
  • the anode voltage of the organic EL element 21 is initialized in the first pixel circuit and the second pixel circuit.
  • the second scanning signal SCAN2(n-1) and the second scanning signal SCAN2(n) change from high level to low level.
  • the write control transistor T1 is turned off in the first pixel circuit and the second pixel circuit.
  • the second emission control signal EM2(n-1) and the second emission control signal EM2(n) change from low level to high level.
  • the power supply control transistor T4 is turned on in the first pixel circuit and the second pixel circuit.
  • a drive current corresponding to the charging voltage of the holding capacitor Cst is supplied to the organic EL element 21, and the organic EL element 21 emits light according to the magnitude of the drive current.
  • the organic light is emitted in the first pixel circuit and the second pixel circuit.
  • the EL element 21 emits light.
  • the threshold voltage compensating transistor T3 is kept off during the rest period, the potential of the node N2 does not change. Therefore, the charging voltage of the holding capacitor Cst is equal to the voltage charged in the holding capacitor Cst based on the data signal D in the immediately preceding driving period.
  • FIG. 1 is a block diagram showing a schematic configuration of a scanning-side drive circuit 300 according to this embodiment.
  • the scanning-side driving circuit 300 is composed of a first scanning signal line driving circuit 31 , a second scanning signal line driving circuit 32 , a first emission control line driving circuit 33 and a second emission control line driving circuit 34 .
  • the first scanning signal line driving circuit 31 applies the first scanning signal SCAN1 to the first scanning signal line
  • the second scanning signal line driving circuit 32 applies the second scanning signal SCAN2 to the second scanning signal line
  • the emission control line drive circuit 33 applies the first emission control signal EM1 to the first emission control line
  • the second emission control line drive circuit 34 applies the second emission control signal EM2 to the second emission control line.
  • the first scanning signal line drive circuit 31 is composed of a shift register including the unit circuits 310 in number equal to the number of the first scanning signal lines SCAN1. That is, each unit circuit included in the shift register forming the first scanning signal line driving circuit 31 corresponds to one first scanning signal line SCAN1. Therefore, the i first scanning signal lines SCAN1(1) to SCAN1(i) are driven one by one by the first scanning signal line driving circuit 31.
  • FIG. 1 A first scanning signal line drive circuit 31 is composed of a shift register including the unit circuits 310 in number equal to the number of the first scanning signal lines SCAN1. That is, each unit circuit included in the shift register forming the first scanning signal line driving circuit 31 corresponds to one first scanning signal line SCAN1. Therefore, the i first scanning signal lines SCAN1(1) to SCAN1(i) are driven one by one by the first scanning signal line driving circuit 31.
  • the second scanning signal line driving circuit 32 is composed of a shift register including unit circuits 320 whose number is equal to half the number of second scanning signal lines SCAN2. That is, each unit circuit included in the shift register forming the second scanning signal line driving circuit 32 corresponds to two second scanning signal lines SCAN2. Therefore, the i second scanning signal lines SCAN2(1) to SCAN2(i) are driven two by two by the second scanning signal line drive circuit 32 .
  • the first emission control line drive circuit 33 is configured by a shift register including unit circuits 330 whose number is equal to half the number of the first emission control lines EM1. That is, each unit circuit included in the shift register forming the first emission control line drive circuit 33 corresponds to two first emission control lines EM1. Therefore, the i first emission control lines EM1(1) to EM1(i) are driven two by two by the first emission control line drive circuit 33.
  • FIG. 1 A first emission control line drive circuit 33.
  • the second emission control line drive circuit 34 is configured by a shift register including unit circuits 340 whose number is equal to half the number of the second emission control lines EM2. That is, each unit circuit included in the shift register forming the second emission control line drive circuit 34 corresponds to two second emission control lines EM2. Accordingly, the i second emission control lines EM2(1) to EM2(i) are driven two by two by the second emission control line driving circuit .
  • FIG. 6 is a block diagram showing the configuration of the first scanning signal line driving circuit 31.
  • the first scanning signal line driving circuit 31 is composed of a shift register consisting of i stages (i unit circuits 310) corresponding to the i first scanning signal lines SCAN1(1) to SCAN1(i) on a one-to-one basis. It is In FIG. 6, where n is an even number, unit circuits 310(n ⁇ 1), 310(n) at (n ⁇ 1), n, (n+1), and (n+2) stages are shown. , 310(n+1), and 310(n+2) are shown.
  • a clock signal S1CK1, a clock signal S1CK2, a start pulse S1SP (not shown in FIG. 6), a high-level power supply voltage GVDD, and a low-level power supply voltage GVSS are applied to the shift register constituting the first scanning signal line driving circuit 31. .
  • Each unit circuit 310 has an input terminal for receiving a clock signal CKA1, a clock signal CKA2, a set signal SA, a high-level power supply voltage GVDD, and a low-level power supply voltage GVSS, and an output terminal for outputting an output signal OUTA. contains.
  • the clock signal S1CK1 is given as the clock signal CKA1
  • the clock signal S1CK2 is given as the clock signal CKA2.
  • clock signal S1CK2 is applied as clock signal CKA1
  • clock signal S1CK1 is applied as clock signal CKA2.
  • High-level power supply voltage GVDD and low-level power supply voltage GVSS are commonly applied to all unit circuits 310 .
  • the output signal OUTA from the unit circuit 310 of the preceding stage is applied as the set signal SA to the unit circuit 310 of each stage.
  • the unit circuit 310(1) of the first stage is supplied with the start pulse S1SP as the set signal SA.
  • the output signal OUTA from the unit circuit 310 of each stage is applied to the corresponding first scanning signal line SCAN1 as a first scanning signal and is also applied to the unit circuit 310 of the next stage as a set signal SA.
  • FIG. 7 is a circuit diagram showing a configuration of unit circuit 310.
  • the unit circuit 310 includes eight transistors M11 to M18 and two capacitors C11 and C12.
  • the transistors M11 to M18 are N-channel oxide TFTs.
  • the reference numeral 319 is attached to the output terminal for outputting the output signal OUTA.
  • the node connected to the first conduction terminal of the transistor M11, the second conduction terminal of the transistor M12, the control terminal of the transistor M13 and the first conduction terminal of the transistor M16 is labeled NA1.
  • a node connected to the second conduction terminal and the first conduction terminal of transistor M14 is labeled NA2 and is connected to the second conduction terminal of transistor M16, the control terminal of transistor M18 and the first electrode of capacitor C12.
  • a node connected to the first conduction terminal of the transistor M13, the control terminal of the transistor M14, the second conduction terminal of the transistor M15, the control terminal of the transistor M17 and the first electrode of the capacitor C11. is given the code NA4.
  • the unit circuit 310 includes three control circuits 311 to 313 and one output circuit 314 .
  • the control circuit 311 includes a transistor M12.
  • Control circuit 312 includes transistor M13 and transistor M15.
  • the control circuit 313 includes a transistor M11 and a transistor M14.
  • Output circuit 314 includes transistor M17, transistor M18, capacitor C11 and capacitor C12.
  • the clock signal CKA2 is applied to the control terminal, the first conduction terminal is connected to the node NA1, and the second conduction terminal is connected to the node NA2.
  • the transistor M12 has a control terminal supplied with the clock signal CKA1, a first conduction terminal supplied with the set signal SA, and a second conduction terminal connected to the node NA1.
  • the control terminal is connected to the node NA1, the first conduction terminal is connected to the node NA4, and the clock signal CKA1 is applied to the second conduction terminal.
  • the control terminal is connected to the node NA4, the first conduction terminal is connected to the node NA2, and the low level power supply voltage GVSS is applied to the second conduction terminal.
  • the clock signal CKA1 is applied to the control terminal
  • the high level power supply voltage GVDD is applied to the first conduction terminal
  • the second conduction terminal is connected to the node NA4.
  • the transistor M16 has a control terminal supplied with the high-level power supply voltage GVDD, a first conduction terminal connected to the node NA1, and a second conduction terminal connected to the node NA3.
  • the control terminal is connected to the node NA4, the first conduction terminal is connected to the output terminal 319, and the low level power supply voltage GVSS is applied to the second conduction terminal.
  • Transistor M18 has a control terminal connected to node NA3, a first conduction terminal supplied with clock signal CKA2, and a second conduction terminal connected to output terminal 319.
  • the first electrode is connected to the control terminal of the transistor M17, and the second electrode is connected to the second conduction terminal of the transistor M17.
  • Capacitor C12 has a first electrode connected to the control terminal of transistor M18 and a second electrode connected to the second conduction terminal of transistor M18.
  • the clock signal CKA1 changes from low level to high level.
  • the transistor M12 is turned on.
  • the set signal SA changes from low level to high level.
  • the potential of node NA1 rises.
  • the transistor M16 is on, and the potential of the node NA3 increases as the potential of the node NA1 increases.
  • the transistor M18 is turned on.
  • the clock signal CKA2 is maintained at low level
  • the output signal OUTA is maintained at low level.
  • the transistor M13 and the transistor M15 are turned on, the potential of the node NA4 is maintained at the high level because the clock signal CKA1 is at the high level.
  • the clock signal CKA1 changes from high level to low level.
  • the transistor M12 and the transistor M15 are turned off.
  • the transistor M13 is kept on and the clock signal CKA1 is at low level, so the potential of the node NA4 changes from high level to low level.
  • the transistor M14 and the transistor M17 are turned off.
  • the set signal SA changes from high level to low level.
  • the clock signal CKA2 changes from low level to high level.
  • the potential of the output terminal 319 (potential of the output signal OUTA) rises as the potential of the first conduction terminal of the transistor M18 rises. Accordingly, the potential of node NA3 further increases via capacitor C12.
  • a large voltage is applied to the control terminal of the transistor M18 to a level sufficient to turn on the threshold voltage compensation transistor T3 and the initialization transistor T6 (see FIG. 3) to which the output terminal 319 is connected.
  • the potential of the output signal OUTA rises.
  • the potential of the node NA3 becomes higher than the potential of the high-level power supply voltage GVDD, but the potential of the node NA1 does not change because the transistor M16 is turned off. This prevents application of a high voltage to the first conduction terminal or the second conduction terminal of the transistor connected to the node NA1.
  • the transistor M11 is turned on. At this time, since the potential of the node NA1 is high level, the potential of the node NA2 also becomes high level.
  • the clock signal CKA2 changes from high level to low level.
  • the potential of the output terminal 319 (potential of the output signal OUTA) drops as the potential of the first conductive terminal of the transistor M18 drops.
  • the potential of node NA3 also drops via capacitor C12.
  • the clock signal CKA1 changes from low level to high level.
  • the transistor M12 is turned on.
  • the potential of the node NA1 becomes low level.
  • the potential of the node NA3 also becomes low level.
  • the transistor M13 is turned off.
  • the transistor M15 is turned on by the clock signal CKA1 going high.
  • the potential of the node NA4 becomes high level, and the transistor M14 and the transistor M17 are turned on.
  • the transistor M14 When the transistor M14 is turned on, the potential of the node NA2 becomes low, and when the transistor M17 is turned on, the potential of the output terminal 319 (the potential of the output signal OUTA) is maintained at a low level even if noise occurs. be done.
  • the transistor M11 is turned on when the clock signal CKA2 becomes high level.
  • the transistor M14 is maintained in the ON state and the potential of the node NA2 is maintained at a low level, so the potential of the node NA1 is reliably maintained at a low level even if noise occurs. This prevents the occurrence of abnormal operations.
  • FIG. 9 is a block diagram showing the configuration of the second scanning signal line driving circuit 32.
  • a clock signal S2CK1, a clock signal S2CK2, a start pulse S2SP (not shown in FIG. 9), a high-level power supply voltage GVDD, and a low-level power supply voltage GVSS are applied to the shift register constituting the second scanning signal line driving circuit 32. .
  • Each unit circuit 320 includes input terminals for receiving the clock signal CKB1, the set signal SB, the high-level power supply voltage GVDD, and the low-level power supply voltage GVSS, respectively, and an output terminal for outputting the output signal OUTB. .
  • the clock signal S2CK1 is given as the clock signal CKB1.
  • clock signal S2CK2 is applied as clock signal CKB1.
  • High-level power supply voltage GVDD and low-level power supply voltage GVSS are commonly applied to all unit circuits 320 .
  • the output signal OUTB from the unit circuit 320 of the preceding stage is applied as the set signal SB to the unit circuit 320 of each stage.
  • a start pulse S2SP is given as the set signal SB to the unit circuit 320(1) of the first stage.
  • the output signal OUTB from the unit circuit 320 of each stage is applied to the corresponding two second scanning signal lines SCAN2 as a second scanning signal, and is also applied to the unit circuit 320 of the next stage as a set signal SB.
  • two second scanning signal lines SCAN2 adjacent to each other form one pair, and the second scanning signal SCAN2 having the same waveform is applied to the two second scanning signal lines SCAN2 forming each pair. be done.
  • FIG. 10 is a circuit diagram showing a configuration of unit circuit 320.
  • the unit circuit 320 includes seven transistors M21-M27 and three capacitors C21-C23.
  • the transistors M21 to M27 are N-channel oxide TFTs.
  • reference numeral 329 is attached to the output terminal for outputting the output signal OUTB.
  • the node connected to the second conduction terminal of the transistor M22, the control terminal of the transistor M24 and the first conduction terminal of the transistor M25 is labeled NB1, and the control terminal of the transistor M21 and the first conduction terminal of the transistor M23 are connected to each other.
  • a node connected to the conduction terminal and the first electrode of the capacitor C23 is denoted by NB2
  • a node connected to the second conduction terminal of the transistor M25, the control terminal of the transistor M27 and the first electrode of the capacitor C22 is denoted by NB2.
  • NB3 a node connected to the second conductive terminal of the transistor M21, the first conductive terminal of the transistor M24, the control terminal of the transistor M26 and the first electrode of the capacitor C21 is labeled NB4.
  • the unit circuit 320 includes two control circuits 321 and 322 and one output circuit 323 .
  • the control circuit 321 includes a transistor M22.
  • the control circuit 322 includes a transistor M21, a transistor M23, a transistor M24 and a capacitor C23.
  • the output circuit 323 includes a transistor M26, a transistor M27, a capacitor C21 and a capacitor C22.
  • the control terminal is connected to the node NB2, the clock signal CKB1 is applied to the first conduction terminal, and the second conduction terminal is connected to the node NB4.
  • the transistor M22 has a control terminal supplied with the clock signal CKB1, a first conduction terminal supplied with the set signal SB, and a second conduction terminal connected to the node NB1.
  • the transistor M23 has a control terminal supplied with the set signal SB, a first conduction terminal connected to the node NB2, and a second conduction terminal supplied with the low level power supply voltage GVSS.
  • the control terminal is connected to the node NB1, the first conduction terminal is connected to the node NB4, and the low level power supply voltage GVSS is applied to the second conduction terminal.
  • the transistor M25 has a control terminal supplied with the high-level power supply voltage GVDD, a first conduction terminal connected to the node NB1, and a second conduction terminal connected to the node NB3.
  • the control terminal is connected to the node NB4
  • the first conduction terminal is connected to the output terminal 329
  • the low level power supply voltage GVSS is applied to the second conduction terminal.
  • the transistor M27 has a control terminal connected to the node NB3, a first conduction terminal supplied with the high level power supply voltage GVDD, and a second conduction terminal connected to the output terminal 329.
  • the first electrode is connected to the control terminal of the transistor M26, and the second electrode is connected to the second conduction terminal of the transistor M26.
  • Capacitor C22 has a first electrode connected to the control terminal of transistor M27 and a second electrode connected to the second conduction terminal of transistor M27.
  • the first electrode is connected to the control terminal of the transistor M21 and the second electrode is connected to the first conduction terminal of the transistor M21. It is assumed that the capacitance of capacitor C23 is sufficiently larger than the parasitic capacitance of node NB2.
  • the transistor M21 implements the first transistor
  • the transistor M22 implements the second transistor
  • the transistor M23 implements the third transistor
  • the transistor M24 implements the fourth transistor
  • the transistor M25 implements the third transistor.
  • 5 transistors are implemented
  • a sixth transistor is implemented by transistor M26
  • a seventh transistor is implemented by transistor M27
  • a first capacitor is implemented by capacitor C21
  • a second capacitor is implemented by capacitor C22
  • a second capacitor is implemented by capacitor C23.
  • 3 capacitors are implemented, node NB1 implements a first internal node, node NB2 implements a second internal node, node NB3 implements a third internal node, node NB4 implements a fourth internal node,
  • a control clock signal is realized by the clock signal CKB1.
  • the set signal SB changes from low level to high level.
  • the clock signal CKB1 is maintained at the low level and the transistor M22 is off, so the potential of the node NB1 is maintained at the low level.
  • the transistor M23 is maintained in the ON state. The potential is maintained at a low level.
  • the clock signal CKB1 changes from low level to high level.
  • the transistor M22 is turned on. Since the set signal SB is maintained at the high level, the potential of the node NB1 rises. As a result, the transistor M24 is turned on, and the potential of the node NB4 changes from high level to low level. As a result, the transistor M26 is turned off. Further, at time t42, the transistor M25 is on, and the potential of the node NB3 rises as the potential of the node NB1 rises. As a result, the transistor M27 is turned on, and the potential of the output terminal 329 (the potential of the output signal OUTB) rises.
  • the potential of node NB3 further increases through capacitor C22.
  • a large voltage is applied to the control terminal of the transistor M27, and the potential of the output signal OUTB rises to a level sufficient to turn on the write control transistor T1 (see FIG. 3) connected to the output terminal 329.
  • the potential of the output signal OUTB rises to a level sufficient to turn on the write control transistor T1 (see FIG. 3) connected to the output terminal 329. rise.
  • the clock signal CKB1 changes from high level to low level.
  • the transistor M22 is turned off.
  • the set signal SB changes from high level to low level.
  • the transistor M23 is turned off.
  • the potential of the node NB2 is maintained at the low level.
  • the clock signal CKB1 changes from low level to high level.
  • the transistor M22 is turned on.
  • the set signal SB is at low level
  • the potential of the node NB1 is lowered.
  • the transistor M24 is turned off.
  • the potential of the node NB2 changes from low level to high level via the capacitor C23 when the clock signal CKB1 changes from low level to high level.
  • the transistor M21 is turned on
  • the potential of the node NB4 changes from low level to high level.
  • the transistor M26 is turned on.
  • the potential of the node NB3 also drops as the potential of the node NB1 drops.
  • the transistor M27 is turned off. Since the transistor M27 is turned off and the transistor M26 is turned on as described above, the potential of the output terminal 329 (the potential of the output signal OUTB) becomes low level.
  • the potential of the node NB4 is maintained at the high level by turning on the transistor M21 each time the clock signal CKB1 changes from the low level to the high level. be.
  • the transistor M26 is maintained in the ON state, the output signal OUTB is reliably maintained at a low level even if noise occurs. This prevents the occurrence of abnormal operations.
  • FIG. 12 is a block diagram showing the configuration of the first emission control line drive circuit 33.
  • a clock signal E1CK1, a clock signal E1CK2, a start pulse E1SP (not shown in FIG. 12), a high level power supply voltage GVDD, and a low level power supply voltage GVSS are applied to the shift register constituting the first emission control line driving circuit 33. .
  • Each unit circuit 330 includes input terminals for receiving the clock signal ECK, set signal SE, high-level power supply voltage GVDD, and low-level power supply voltage GVSS, respectively, and output terminals for outputting the output signal EOUT. .
  • the clock signal E1CK1 is given as the clock signal ECK to the unit circuits 330 of the odd-numbered stages.
  • clock signal E1CK2 is applied as clock signal ECK.
  • High-level power supply voltage GVDD and low-level power supply voltage GVSS are commonly applied to all unit circuits 330 .
  • the output signal EOUT from the unit circuit 330 of the previous stage is applied as the set signal SE to the unit circuit 330 of each stage.
  • the unit circuit 330(1) of the first stage is supplied with the start pulse E1SP as the set signal SE.
  • An output signal EOUT from the unit circuit 330 in each stage is applied to the corresponding two first emission control lines EM1 as a first emission control signal, and is also applied to the unit circuit 330 in the next stage as a set signal SE.
  • first emission control lines EM1 adjacent to each other form one pair, and the first emission control signals EM1 having the same waveform are applied to the two first emission control lines EM1 forming each pair. Given.
  • FIG. 13 is a block diagram showing the configuration of the second emission control line drive circuit 34.
  • a shift register constituting the second emission control line driving circuit 34 is supplied with a clock signal E2CK1, a clock signal E2CK2, a start pulse E2SP (not shown in FIG. 13), a high level power supply voltage GVDD, and a low level power supply voltage GVSS.
  • Other points are the same as the first emission control line drive circuit 33, so detailed description of the second emission control line drive circuit 34 is omitted.
  • FIG. 14 is a circuit diagram showing a configuration of unit circuit 330.
  • the unit circuit 330 includes seven transistors M31-M37 and three capacitors C31-C33. 10 and 14, the unit circuit 330 included in the shift register forming the first emission control line drive circuit 33 is a unit included in the shift register forming the second scanning signal line drive circuit 32. It has the same configuration as circuit 320 .
  • the set signal SE changes from high level to low level.
  • the transistor M33 is turned off.
  • the clock signal ECK is maintained at low level and the transistor M32 is off, so the potential of the node NC1 is maintained at high level.
  • the clock signal ECK changes from low level to high level.
  • the transistor M32 is turned on.
  • the set signal SE is at low level
  • the potential of the node NC1 is lowered.
  • the transistor M34 is turned off.
  • the change of the clock signal ECK from low level to high level changes the potential of the node NC2 from low level to high level via the capacitor C33.
  • the transistor M31 is turned on, and the potential of the node NC4 changes from low level to high level.
  • the transistor M36 is turned on.
  • the potential of the node NC3 also drops as the potential of the node NC1 drops.
  • the transistor M37 is turned off. Since the transistor M37 is turned off and the transistor M36 is turned on as described above, the potential of the output terminal 339 (the potential of the output signal EOUT) becomes low level.
  • the clock signal ECK changes from high level to low level.
  • the transistor M32 is turned off.
  • the potential of the node NC2 changes from high level to low level via the capacitor C33.
  • the clock signal ECK changes from low level to high level.
  • the transistor M32 is turned on.
  • the set signal SE is at low level
  • the potential of the node NC1 is maintained at low level.
  • the transistor M33 is off
  • the change of the clock signal ECK from low level to high level changes the potential of the node NC2 from low level to high level via the capacitor C33.
  • the transistor M31 is turned on, and the potential of the node NC4 is maintained at a high level.
  • the output signal EOUT is reliably maintained at a low level even if noise occurs.
  • the clock signal ECK changes from high level to low level.
  • the transistor M32 is turned off.
  • the potential of the node NC2 changes from high level to low level via the capacitor C33.
  • the set signal SE changes from low level to high level.
  • the clock signal ECK is maintained at the low level and the transistor M32 is off, so the potential of the node NC1 is maintained at the low level.
  • the clock signal ECK changes from low level to high level.
  • the transistor M32 is turned on. Since the set signal SE is maintained at high level, the potential of the node NC1 rises. As a result, the transistor M34 is turned on, and the potential of the node NC4 changes from high level to low level. As a result, the transistor M36 is turned off.
  • the transistor M35 is on, and the potential of the node NC3 rises as the potential of the node NC1 rises.
  • the transistor M37 is turned on, and the potential of the output terminal 339 (the potential of the output signal EOUT) rises. Accordingly, the potential of node NC3 further increases through capacitor C32. As a result, a large voltage is applied to the control terminal of the transistor M37, and the potential of the output signal EOUT reaches a level sufficient to turn on the light emission control transistor T5 (see FIG. 3) connected to the output terminal 339. Rise.
  • the potentials of the nodes NC1 and NC3 are maintained at high level, the potentials of the nodes NC2 and NC4 are maintained at low level, and the output signal EOUT is maintained at high level.
  • the pulse width (length of high level period) of the start pulses S1SP and S2SP is 2H.
  • the clock signals S1CK1 and S1CK2 have a high level period of 0.5H and a low level period of 1.5H.
  • the clock signals S2CK1 and S2CK2 have a high level period of 0.5H and a low level period of 3.5H.
  • the pulse width (length of period of low level) of the start pulses E1SP and E2SP is 8H.
  • the clock signals E1CK1 and E1CK2 have a high level period of 1H and a low level period of 3H.
  • the clock signals E2CK1 and E2CK2 have a high level period of 1H and a low level period of 3H.
  • the clock signal E1CK1 changes from low level to high level, whereby the emission control signals EM1(1) and EM1(2) change from high level to low level.
  • the emission control transistors T5 are turned off, and the organic EL elements 21 are turned off. Note that the start pulse S1SP changes from low level to high level before the start pulse E1SP changes from high level to low level.
  • the first scanning signal SCAN1(1) changes from low level to high level.
  • the threshold voltage compensation transistor T3 and the initialization transistor T6 are turned on, and the holding voltage of the holding capacitor Cst and the anode voltage of the organic EL element 21 are initialized.
  • the clock signal S1CK2 changes from low level to high level, thereby changing the first scanning signal SCAN1(2) from low level to high level.
  • the threshold voltage compensation transistor T3 and the initialization transistor T6 are turned on, and the holding voltage of the holding capacitor Cst and the anode voltage of the organic EL element 21 are initialized.
  • the start pulse E2SP changes from high level to low level at the timing when the first scanning signal SCAN1 (2) changes from low level to high level.
  • the second emission control signals EM2(1) and EM2(2) change from high level to low level.
  • the power supply control transistors T4 are turned off.
  • the clock signal S2CK1 changes from low level to high level after the start pulse S2SP changes from low level to high level, whereby the second scanning signals SCAN2(1) and SCAN2(2) change from low level to high level. Change.
  • the write control transistors T1 are turned on in the pixel circuits 20 on the first row and the pixel circuits 20 on the second row.
  • the start pulse S1SP changes from low level to high level again.
  • the clock signal S1CK1 changes from low level to high level
  • the first scanning signal SCAN1(1) changes from low level to high level.
  • the threshold voltage compensation transistor T3 and the initialization transistor T6 are turned on.
  • the power supply control transistor T4 and the light emission control transistor T5 are in an off state. Therefore, in the pixel circuit 20 of the first row, the holding capacitor Cst is charged with a voltage corresponding to the data signal D so as to compensate for variations in the threshold voltage of the driving transistor T2.
  • the clock signal S1CK2 changes from low level to high level, thereby changing the first scanning signal SCAN1(2) from low level to high level.
  • the holding capacitor Cst is charged with a voltage corresponding to the data signal D so as to compensate for variations in the threshold voltage of the driving transistor T2.
  • the first scanning signal line SCAN1 is driven one by one, and the second scanning signal line SCAN2, the first emission control line EM1, and the second emission control line EM2 are driven two times. Driven one by one.
  • the second scanning signal lines SCAN2 are driven two by two, but the first scanning signal lines SCAN1 are driven one by one, thereby initializing the state of the pixel circuit 20 and writing data into the pixel circuit 20. is done line by line.
  • the pulse width (length of high level period) of the start pulse S2SP is 2H.
  • the clock signals S2CK1 and S2CK2 have a high level period of 0.5H and a low level period of 3.5H.
  • the clock signals E1CK1 and E1CK2 have a high level period of 1H and a low level period of 3H.
  • the pulse width (length of low level period) of the start pulse E2SP is 8H.
  • the clock signals E2CK1 and E2CK2 have a high level period of 1H and a low level period of 3H.
  • start pulse S1SP and the clock signals S1CK1 and S1CK2 are maintained at a low level throughout the idle period, and the start pulse E1SP is maintained at a high level throughout the idle period. Further, as described above, the anode reset voltage (low level power supply voltage ELVSS in this embodiment) is applied to all the data signal lines D throughout the pause period.
  • ELVSS low level power supply voltage
  • the clock signal E2CK1 changes from low level to high level, whereby the second emission control signals EM2(1) and EM2(2) change from high level to low level. do.
  • the power supply control transistors T4 are turned off, and the organic EL elements 21 are turned off.
  • the clock signal S2CK1 changes from low level to high level after the start pulse S2SP changes from low level to high level, whereby the second scanning signals SCAN2(1) and SCAN2(2) change from low level to high level. Change.
  • the write control transistors T1 are turned on in the pixel circuits 20 on the first row and the pixel circuits 20 on the second row.
  • the power supply control transistor T4 is in the OFF state, but the light emission control transistor T5 is in the ON state.
  • the data signal line D is applied with an anode reset voltage. As described above, the anode voltages of the organic EL elements 21 are initialized in the pixel circuits 20 on the first row and the pixel circuits 20 on the second row.
  • the second scanning signal line driving circuit 32 includes unit circuits 320 whose number is equal to half the number of the second scanning signal lines SCAN2 so that the second scanning signal lines SCAN2 are driven two by two. and the first emission control line driving circuit 33 has the number of unit circuits equal to half the number of the first emission control lines EM1 so that the first emission control lines EM1 are driven two by two. 330, and the second emission control line drive circuit 34 has a number equal to half the number of the second emission control lines EM2 so that the second emission control lines EM2 are driven two by two. It is composed of a shift register consisting of a circuit 340 .
  • FIG. 18 is a block diagram showing a schematic configuration of the scanning side drive circuit 300 in the first modified example.
  • the first scanning signal line driving circuit 31 is the same as in the first embodiment.
  • the second scanning signal line driving circuit 32 is composed of a shift register including unit circuits 320 in a number equal to one-third the number of the second scanning signal lines SCAN2. However, only one unit circuit 320 is shown in FIG.
  • Each unit circuit included in the shift register forming the second scanning signal line driving circuit 32 corresponds to three second scanning signal lines SCAN2. Accordingly, the i second scanning signal lines SCAN2(1) to SCAN2(i) are driven three by three by the second scanning signal line drive circuit 32 .
  • the first emission control line drive circuit 33 is configured by a shift register including unit circuits 330 in a number equal to one-third the number of the first emission control lines EM1. However, only one unit circuit 330 is shown in FIG. Each unit circuit included in the shift register forming the first emission control line drive circuit 33 corresponds to three first emission control lines EM1. Accordingly, the i first emission control lines EM1(1) to EM1(i) are driven three by three by the first emission control line driving circuit 33 .
  • the second emission control line drive circuit 34 is configured by a shift register including unit circuits 340 in a number equal to one-third the number of the second emission control lines EM2. However, only one unit circuit 340 is shown in FIG.
  • Each unit circuit included in the shift register forming the second emission control line drive circuit 34 corresponds to three second emission control lines EM2. Accordingly, the i second emission control lines EM2(1) to EM2(i) are driven three by three by the second emission control line driving circuit .
  • first emission control signals EM1(n ⁇ 2), EM1(n ⁇ 2) and EM1( n ⁇ 1), and EM1(n) are low level
  • the second emission control signals EM2(n ⁇ 2), EM2(n ⁇ 1), and during the period in which EM2(n) is at high level the period indicated by the arrow with reference numeral 71
  • the three first scanning signal lines corresponding to the (n ⁇ 2) to n-th rows The first scanning signal SCAN1(n-2), the first scanning signal SCAN1(n-1), and the first scanning signal SCAN1(n) supplied to SCAN1 are sequentially turned on for a predetermined period.
  • the holding voltage of the holding capacitor Cst is initialized and the organic EL element is initialized. 21 anode voltage initialization is performed. Further, during the driving period, as shown in FIG.
  • the first emission control signals EM1(n ⁇ 2), EM1(n ⁇ 1), and EM1(n) are at low level
  • the second emission control signal EM2 (n-2), EM2(n-1), and EM2(n) are at low level, during a part of the period, three lines corresponding to the (n-2) to n-th rows
  • the second scanning signal SCAN2(n-2), the second scanning signal SCAN2(n-1), and the second scanning signal SCAN2(n) supplied to the second scanning signal line SCAN2 are maintained at a high level. In this way, the second scanning signal SCAN2(n-2), the second scanning signal SCAN2(n-1), and the second scanning signal SCAN2(n) are maintained at the high level (reference numeral 72).
  • the first scanning signal SCAN1(n-2), the first scanning signal SCAN1(n-1), and the first scanning signal SCAN1(n) are sequentially turned on again for each predetermined period. Become.
  • the (n-2)th pixel circuit 20 the (n-1)th pixel circuit 20, and the nth pixel circuit 20
  • variations in the threshold voltage of the driving transistor T2 are compensated.
  • a voltage corresponding to the data signal D is charged in the holding capacitor Cst.
  • second emission control signals EM2(n ⁇ 2), EM2( n-1), and EM2(n) are at low level, during a part of the period (the period indicated by the arrow labeled 73), corresponding to the (n-2) to n-th rows
  • the second scanning signal SCAN2(n-2), the second scanning signal SCAN2(n-1), and the second scanning signal SCAN2(n) supplied to the three second scanning signal lines SCAN2 are maintained at a high level. be done.
  • the anode voltages of the organic EL elements 21 are initialized in the pixel circuits 20 on the (n-2)th row, the pixel circuits 20 on the (n-1)th row, and the pixel circuits 20 on the nth row.
  • FIG. 21 is a block diagram showing a schematic configuration of a scanning-side drive circuit 300 in the second modified example.
  • the first scanning signal line driving circuit 31 is the same as in the first embodiment.
  • the second scanning signal line driving circuit 32 is configured by a shift register including unit circuits 320 in a number equal to one fourth of the number of second scanning signal lines SCAN2. However, only one unit circuit 320 is shown in FIG.
  • Each unit circuit included in the shift register forming the second scanning signal line driving circuit 32 corresponds to four second scanning signal lines SCAN2. Therefore, the i second scanning signal lines SCAN2(1) to SCAN2(i) are driven four by four by the second scanning signal line drive circuit 32 .
  • the first emission control line drive circuit 33 is configured by a shift register including unit circuits 330 in a number equal to one quarter of the number of the first emission control lines EM1. However, only one unit circuit 330 is shown in FIG. Each unit circuit included in the shift register forming the first emission control line drive circuit 33 corresponds to four first emission control lines EM1. Therefore, the i first emission control lines EM1(1) to EM1(i) are driven four by four by the first emission control line driving circuit 33 .
  • the second emission control line drive circuit 34 is configured by a shift register including unit circuits 340 in a number equal to one quarter of the number of the second emission control lines EM2. However, only one unit circuit 340 is shown in FIG.
  • Each unit circuit included in the shift register forming the second emission control line drive circuit 34 corresponds to four second emission control lines EM2. Therefore, the i second emission control lines EM2(1) to EM2(i) are driven four by four by the second emission control line driving circuit .
  • first emission control signals EM1(n ⁇ 3), EM1(n ⁇ 3) and EM1( n-2), EM1(n-1), and EM1(n) are low level
  • the second emission control signals EM2(n- 3) During the period in which EM2(n-2), EM2(n-1), and EM2(n) are at high level (the period indicated by the arrow labeled 74), (n-3) to
  • the first scanning signals SCAN1(n-3), SCAN1(n-2), the first scanning signal SCAN1(n-1), and the first scanning signal SCAN1(n-1) respectively supplied to the four first scanning signal lines SCAN1 corresponding to the n-th row.
  • One scanning signal SCAN1(n) is sequentially turned on for a predetermined period.
  • the (n-3)-th pixel circuit 20 the (n-2)-th pixel circuit 20, the (n-1)-th pixel circuit 20, and the n-th pixel circuit 20, the holding Initialization of the holding voltage of the capacitor Cst and initialization of the anode voltage of the organic EL element 21 are performed. Further, during the driving period, as shown in FIG.
  • the first emission control signals EM1(n-3), EM1(n-2), EM1(n-1), and EM1(n) are at low level and ( n-3) to the second scanning signal SCAN2(n-3), the second scanning signal SCAN2(n-2), the second scanning signal respectively supplied to the four second scanning signal lines SCAN2 corresponding to the n-th row SCAN2(n-1) and the second scan signal SCAN2(n) are maintained at a high level.
  • the second scanning signal SCAN2(n-3), the second scanning signal SCAN2(n-2), the second scanning signal SCAN2(n-1), and the second scanning signal SCAN2(n) are at high level.
  • the first scanning signal SCAN1(n-3), the first scanning signal SCAN1(n-2), the first scanning signal SCAN1(n -1), and the first scanning signal SCAN1(n) are sequentially turned on for a predetermined period.
  • the (n ⁇ 3)th pixel circuit 20, the (n ⁇ 2)th pixel circuit 20, the (n ⁇ 1)th pixel circuit 20, and the nth pixel circuit 20 are driven.
  • a holding capacitor Cst is charged with a voltage corresponding to the data signal D so as to compensate for variations in the threshold voltage of the transistor T2.
  • second emission control signals EM2(n ⁇ 3), EM2( (n-3 ) to the second scanning signal SCAN2(n ⁇ 3), the second scanning signal SCAN2(n ⁇ 2), the second scanning signal SCAN2(n -1), and the second scan signal SCAN2(n) are maintained at a high level. Accordingly, in the (n ⁇ 3)-th pixel circuit 20, the (n ⁇ 2)-th pixel circuit 20, the (n ⁇ 1)-th pixel circuit 20, and the n-th pixel circuit 20, the organic The anode voltage of EL element 21 is initialized.
  • the first emission control line drive circuit 33 that drives the first emission control line EM1 and the second emission control line drive circuit 34 that drives the second emission control line EM2 are provided separately.
  • the waveforms of the first emission control signals EM1(n+1) and EM1(n+2) are the same as those of the second emission control signals EM2(n-1) and EM2(n). Therefore, in the organic EL display device according to this embodiment, a configuration is adopted in which the first emission control line EM1 and the second emission control line EM2 are driven by one shift register.
  • the overall configuration and operation of the organic EL display device are the same as in the first embodiment (see FIG. 2).
  • the configuration and operation of the pixel circuit 20 are also the same as in the first embodiment (see FIG. 3). That is, the organic EL display device according to the present embodiment also has a pixel circuit 20 composed of one organic EL element 21, six N-channel transistors T1 to T6, and one holding capacitor Cst. ing.
  • FIG. 24 is a block diagram showing a schematic configuration of the scanning side drive circuit 300 in this embodiment.
  • the scanning-side driving circuit 300 is composed of a first scanning signal line driving circuit 31 , a second scanning signal line driving circuit 32 and a light emission control line driving circuit 35 .
  • the first scanning signal line driving circuit 31 applies the first scanning signal SCAN1 to the first scanning signal line
  • the second scanning signal line driving circuit 32 applies the second scanning signal SCAN2 to the second scanning signal line to control light emission.
  • the line driving circuit 35 applies the first emission control signal EM1 to the first emission control line and the second emission control signal EM2 to the second emission control line.
  • the first scanning signal line driving circuit 31 and the second scanning signal line driving circuit 32 have the same configuration as in the first embodiment. Therefore, the i first scanning signal lines SCAN1(1) to SCAN1(i) are driven one by one by the first scanning signal line driving circuit 31, and the i second scanning signal lines SCAN2(1) to SCAN2(i) are driven one by one. i) is driven two by two by the second scanning signal line drive circuit 32 .
  • the emission control line drive circuit 35 is configured by a shift register including unit circuits 350 whose number is equal to half the number of the first emission control lines EM1. As shown in FIG. 24, each unit circuit included in the shift register constituting the emission control line drive circuit 35 corresponds to two second emission control lines EM2 and two first emission control lines EM1. there is therefore, in the present embodiment, the i first emission control lines EM1(1) to EM1(i) are driven two by two by the emission control line drive circuit 35, and the i second emission control lines EM2 ( 1) to EM2(i) are driven two by two by the emission control line drive circuit . That is, four light emission control lines (two first light emission control lines EM1 and two second light emission control lines EM2) are grouped by each unit circuit included in the shift register that constitutes the light emission control line driving circuit 35. driven by
  • FIG. 25 is a block diagram showing the configuration of the light emission control line driving circuit 35.
  • the emission control line drive circuit 35 is composed of a shift register consisting of p stages (p unit circuits 350). Each stage (each unit circuit 350) corresponds to two adjacent second emission control lines EM2 and two adjacent first emission control lines EM1.
  • the k-th unit circuit 350(k) includes the second emission control line EM2(n ⁇ 1), the second emission control line EM2(n), and the first emission control line EM2(n ⁇ 1).
  • FIG. 25 shows four lines corresponding to the eight second emission control lines EM2(n ⁇ 1) to EM2(n+6) and the eight first emission control lines EM1(n+1) to EM1(n+8). Only unit circuits 350(k) to 350(k+3) are shown. Each unit circuit 350 has the configuration shown in FIG.
  • a clock signal ECK1, a clock signal ECK2, a start pulse ESP (not shown in FIG. 25), a high-level power supply voltage GVDD, and a low-level power supply voltage GVSS are applied to the shift register forming the emission control line drive circuit 35.
  • each unit circuit 350 has the configuration shown in FIG. That is, each unit circuit 350 includes input terminals for receiving clock signal ECK, set signal SE, high-level power supply voltage GVDD, and low-level power supply voltage GVSS, and an output terminal for outputting output signal EOUT. I'm in.
  • the clock signal ECK1 is given as the clock signal ECK.
  • the even-numbered unit circuits 350 are supplied with the clock signal ECK2 as the clock signal ECK.
  • High-level power supply voltage GVDD and low-level power supply voltage GVSS are commonly applied to all unit circuits 350 .
  • the output signal EOUT from the unit circuit 350 of the preceding stage is applied as the set signal SE to the unit circuit 350 of each stage.
  • the unit circuit 350(1) of the first stage is supplied with the start pulse ESP as the set signal SE.
  • the output signal EOUT from the unit circuit 350 of each stage is applied to the corresponding two second emission control lines EM2 as the second emission control signal, and the corresponding two first emission control lines EM1 are provided with the first emission control signal. It is given as a signal and given to the unit circuit 350 in the next stage as a set signal SE.
  • each set consists of four emission control lines.
  • each set consists of four emission control lines.
  • K is an integer
  • the K-th stage unit circuit 350(K) included in the shift register constituting the emission control line drive circuit 35 is the (2K-1)th second emission control line EM2(2K- 1), the 2K-th second emission control line EM2 (2K), the (2K+1)-th first emission control line EM1 (2K+1), and the (2K+2)-th first emission control line EM1 (2K+2). Drive them together by giving.
  • the operation of the pixel circuit 20 during the idle period will be described with reference to the timing chart shown in FIG.
  • the low-level power supply voltage ELVSS is applied to the data signal line D as the anode reset voltage throughout the idle period.
  • the first scanning signal SCAN1(n-1) and the first scanning signal SCAN1(n) are maintained at a low level throughout the idle period.
  • the first scanning signal SCAN1(n-1), the first scanning signal SCAN1(n), the second scanning signal SCAN1(n-1), and the second scanning signal SCAN1(n) are is low level, and the first emission control signal EM1(n-1), the first emission control signal EM1(n), the second emission control signal EM2(n-1), and the second emission control signal EM2(n) are High level.
  • the write control transistor T1, the threshold voltage compensation transistor T3, and the initialization transistor T6 are in the off state, and the power supply control transistor T4 and the light emission control transistor T5 are in the on state. be. Therefore, the organic EL element 21 emits light according to the magnitude of the drive current.
  • the first emission control signal EM1(n-1) and the first emission control signal EM1(n) change from high level to low level.
  • the light emission control transistor T5 is turned off in the first pixel circuit and the second pixel circuit.
  • the current supply to the organic EL element 21 is cut off, and the organic EL element 21 is turned off.
  • the second emission control signal EM2(n-1) and the second emission control signal EM2(n) change from high level to low level.
  • the power supply control transistor T4 is turned off in the first pixel circuit and the second pixel circuit.
  • the first emission control signal EM1(n-1) and the first emission control signal EM1(n) change from low level to high level.
  • the light emission control transistor T5 is turned on in the first pixel circuit and the second pixel circuit.
  • the power supply control transistor T4 is in the off state, so the organic EL element 21 is maintained in the off state.
  • the second scanning signal SCAN2(n-1) and the second scanning signal SCAN2(n) change from low level to high level.
  • the write control transistor T1 is turned on in the first pixel circuit and the second pixel circuit.
  • the light emission control transistor T5 is in the ON state, and the low level power supply voltage ELVSS is applied to the data signal line D as described above.
  • the low-level power supply voltage ELVSS is applied to the node N3 through the write control transistor T1 and the light emission control transistor T5.
  • the anode voltage of the organic EL element 21 is initialized in the first pixel circuit and the second pixel circuit.
  • the second scanning signal SCAN2(n-1) and the second scanning signal SCAN2(n) change from high level to low level.
  • the write control transistor T1 is turned off in the first pixel circuit and the second pixel circuit.
  • the second emission control signal EM2(n-1) and the second emission control signal EM2(n) change from low level to high level.
  • the power supply control transistor T4 is turned on in the first pixel circuit and the second pixel circuit.
  • a drive current corresponding to the charging voltage of the holding capacitor Cst is supplied to the organic EL element 21, and the organic EL element 21 emits light according to the magnitude of the drive current.
  • the organic light is emitted in the first pixel circuit and the second pixel circuit.
  • the EL element 21 emits light.
  • the first emission control line EM1 and the second emission control line EM2 are driven by one shift register. Therefore, unlike the first embodiment, the first emission control signal EM1 cannot be maintained at high level during the rest period. However, by driving the second scanning signal line SCAN2, the first emission control line EM1, and the second emission control line EM2 as described above, the anode voltage of the organic EL element 21 in each pixel circuit 20 is can be initialized.
  • the number of the first emission control lines EM1 and the second emission control lines EM2 arranged in the display section 200 is the same as the number of the first emission control lines EM1 (the number of the second emission control lines EM2 is the first It is driven by one shift register consisting of the number of unit circuits equal to one-half of the number of light emission control lines EM1. Therefore, the area of the circuit region required around the display section 200 to drive the first emission control line EM1 and the second emission control line EM2 is smaller than that in the first embodiment.
  • the organic EL display device having the pixel circuit 20 configured by one organic EL element 21, six N-channel transistors T1 to T6, and one holding capacitor Cst is described in the first embodiment. It is possible to reduce the frame area compared to the form.
  • Q is an integer of 2 or more
  • the second scanning signal line SCAN2 the first emission control line EM1, and the second emission control line EM2 may be driven Q times.
  • (Q ⁇ 2) emission control lines Q first emission control lines EM1 and Q These second emission control lines EM2) are driven collectively.
  • the emission control line drive circuit 35 is configured by a shift register including unit circuits 350 in a number equal to one third of the number of first emission control lines EM1.
  • Six light emission control lines (three first light emission control lines EM1 and three second light emission control lines EM2) form one set, and the six light emission control lines forming each set are the same.
  • a waveform emission control signal is provided.
  • the K-th stage unit circuit 350(K) included in the shift register constituting the emission control line drive circuit 35 is the (3K-2)th second emission control line EM2(3K- 2) and the (3K ⁇ 1)th second emission control line EM2(3K ⁇ 1), the 3Kth second emission control line EM2(3K) and the (3K+1)th first emission control line EM1(3K+1)
  • K is an integer
  • the K-th stage unit circuit 350(K) included in the shift register constituting the emission control line drive circuit 35 is the (3K-2)th second emission control line EM2(3K- 2) and the (3K ⁇ 1)th second emission control line EM2(3K ⁇ 1)
  • the 3Kth second emission control line EM2(3K) and the (3K+1)th first emission control line EM1(3K+1) By applying the same signal to the (3K+2)th first emission control line EM1(3K+2) and the (3K+3)th first emission control line EM1(3K+3), they are collectively driven
  • the emission control line drive circuit 35 is configured by a shift register including unit circuits 350 in a number equal to one quarter of the number of first emission control lines EM1. Eight light emission control lines (four first light emission control lines EM1 and four second light emission control lines EM2) form one set, and the eight light emission control lines forming each set are the same. A waveform emission control signal is provided.
  • the K-th stage unit circuit 350(K) included in the shift register constituting the emission control line driving circuit 35 is the (4K-3)-th second emission control line EM2(4K- 3) and the (4K-2)th second emission control line EM2 (4K-2), the (4K-1)th second emission control line EM2 (4K-1) and the 4Kth second emission control line EM2
  • the emission control line drive circuit 35 is configured by a shift register including the unit circuits 350 in a number equal to 1/Q the number of the first emission control lines EM1. Then, where K is an integer, the K-th stage unit circuit 350 (K) included in the shift register constituting the emission control line driving circuit 35 is (Q ⁇ K-(Q ⁇ 1))-th to (Q ⁇ K )-th second emission control lines EM2 and (Q ⁇ K+1)-th to (Q ⁇ K+Q)-th first emission control lines EM1 are collectively driven.
  • the threshold voltage compensating transistor T3 and the initialization transistor T6 are controlled by the same signal (first scanning signal SCAN1). However, it is not limited to this, and a configuration (configuration of the present embodiment) in which the threshold voltage compensating transistor T3 and the initialization transistor T6 are controlled by different signals can also be adopted. This will be explained below.
  • the threshold voltage compensating transistor T3 is controlled by the first scanning signal SCAN1, and the initialization transistor T6 is controlled by the third scanning signal SCAN3.
  • a third scanning signal SCAN3 is transmitted by a third scanning signal line.
  • the overall configuration and operation of the organic EL display device according to the present embodiment are the same as those described above, except that i third scanning signal lines SCAN3(1) to SCAN3(i) are provided in the display unit 200. It is similar to the first embodiment (see FIG. 2).
  • FIG. 27 is a circuit diagram showing the configuration of the pixel circuit 20 in this embodiment.
  • the pixel circuit 20 in this embodiment includes one organic EL element 21 and six N-channel transistors T1 to T6 (write control transistor T1, drive transistor T2, threshold voltage compensation transistor T3, power supply control transistor T4, light emission control transistor T5, initialization transistor T6) and one holding capacitor Cst.
  • the control terminal of the initialization transistor T6 is connected to the third scanning signal line SCAN3. Other points are the same as those of the first embodiment.
  • the operation of the pixel circuit 20 shown in FIG. 27 will be described. It should be noted that the pause drive is employed in this embodiment as well. Here, too, attention is paid to the first pixel circuit which is the pixel circuit 20 in the (n ⁇ 1)th row and the second pixel circuit which is the pixel circuit 20 in the nth row.
  • the first scanning signal SCAN1(n-1), the first scanning signal SCAN1(n), the second scanning signal SCAN1(n-1), the second scanning signal SCAN1(n), the 3 scanning signal SCAN3(n-1) and third scanning signal SCAN3(n) are at low level, first emission control signal EM1(n-1), first emission control signal EM1(n) and second emission control signal EM1(n-1).
  • the control signal EM2(n-1) and the second emission control signal EM2(n) are at high level.
  • the write control transistor T1, the threshold voltage compensation transistor T3, and the initialization transistor T6 are in the off state, and the power supply control transistor T4 and the light emission control transistor T5 are in the on state. be. Therefore, the organic EL element 21 emits light according to the magnitude of the drive current.
  • the first emission control signal EM1(n-1) and the first emission control signal EM1(n) change from high level to low level.
  • the light emission control transistor T5 is turned off in the first pixel circuit and the second pixel circuit.
  • the current supply to the organic EL element 21 is cut off, and the organic EL element 21 is turned off.
  • the third scanning signal SCAN3(n ⁇ 1) and the third scanning signal SCAN3(n) change from low level to high level.
  • the initialization transistor T6 is turned on, and the initialization voltage Vini is applied to the node N3.
  • the anode voltage of the organic EL element 21 is initialized in the first pixel circuit and the second pixel circuit.
  • the first scanning signal SCAN1(n-1) changes from low level to high level.
  • the threshold voltage compensation transistor T3 is turned on in the first pixel circuit.
  • the power supply control transistor T4 is maintained in the ON state.
  • the initialization transistor T6 is turned on at time t71.
  • the high-level power supply voltage ELVDD is applied to the node N2 while the initialization voltage Vini is applied to the node N3.
  • the holding voltage of the holding capacitor Cst is initialized in the first pixel circuit.
  • the first scanning signal SCAN1(n-1) changes from high level to low level.
  • the threshold voltage compensation transistor T3 is turned off in the first pixel circuit.
  • the first scanning signal SCAN1(n) changes from low level to high level.
  • the threshold voltage compensation transistor T3 is turned on in the second pixel circuit.
  • the power supply control transistor T4 is maintained in the ON state.
  • the initialization transistor T6 is turned on at time t71.
  • the high-level power supply voltage ELVDD is applied to the node N2 while the initialization voltage Vini is applied to the node N3.
  • the holding voltage of the holding capacitor Cst is initialized in the second pixel circuit.
  • the first scanning signal SCAN1(n) changes from high level to low level.
  • the threshold voltage compensation transistor T3 is turned off in the second pixel circuit.
  • the second emission control signal EM2(n-1) and the second emission control signal EM2(n) change from high level to low level.
  • the power supply control transistor T4 is turned off in the first pixel circuit and the second pixel circuit.
  • the second scanning signal SCAN2(n-1) and the second scanning signal SCAN2(n) change from low level to high level.
  • the write control transistor T1 is turned on in the first pixel circuit and the second pixel circuit.
  • the first scanning signal SCAN1(n-1) changes from low level to high level.
  • the threshold voltage compensation transistor T3 is turned on in the first pixel circuit.
  • the power supply control transistor T4 and the light emission control transistor T5 are in an off state.
  • An initialization voltage Vini is applied to the node N3.
  • the data signal D is applied to the node N2 through the write control transistor T1, the drive transistor T2, and the threshold voltage compensation transistor T3.
  • the holding capacitor Cst is charged with a voltage corresponding to the data signal D so as to compensate for variations in the threshold voltage of the driving transistor T2.
  • the first scanning signal SCAN1(n-1) changes from high level to low level.
  • the threshold voltage compensation transistor T3 is turned off in the first pixel circuit.
  • the first scanning signal SCAN1(n) changes from low level to high level.
  • the threshold voltage compensation transistor T3 is turned on in the second pixel circuit.
  • the power supply control transistor T4 and the light emission control transistor T5 are in an off state.
  • An initialization voltage Vini is applied to the node N3.
  • the data signal D is applied to the node N2 through the write control transistor T1, the drive transistor T2, and the threshold voltage compensation transistor T3.
  • the holding capacitor Cst is charged with a voltage corresponding to the data signal D so as to compensate for variations in the threshold voltage of the driving transistor T2.
  • the first scanning signal SCAN1(n) changes from high level to low level.
  • the threshold voltage compensation transistor T3 is turned off in the second pixel circuit.
  • the second scanning signal SCAN2(n-1) and the second scanning signal SCAN2(n) change from high level to low level.
  • the write control transistor T1 is turned off in the first pixel circuit and the second pixel circuit.
  • the first emission control signal EM1(n-1) and the first emission control signal EM1(n) change from low level to high level.
  • the light emission control transistor T5 is turned on in the first pixel circuit and the second pixel circuit.
  • the power supply control transistor T4 is kept off. Therefore, in the first pixel circuit and the second pixel circuit, the organic EL element 21 is maintained in the off state.
  • the third scanning signal SCAN3(n-1) and the third scanning signal SCAN3(n) change from high level to low level.
  • the initialization transistor T6 is turned off in the first pixel circuit and the second pixel circuit.
  • the second emission control signal EM2(n-1) and the second emission control signal EM2(n) change from low level to high level.
  • the power supply control transistor T4 is turned on in the first pixel circuit and the second pixel circuit.
  • a drive current corresponding to the charging voltage of the holding capacitor Cst is supplied to the organic EL element 21, and the organic EL element 21 emits light according to the magnitude of the drive current.
  • the organic light is emitted in the first pixel circuit and the second pixel circuit.
  • the EL element 21 emits light.
  • the operation of the pixel circuit 20 during the idle period will be described with reference to the timing chart shown in FIG.
  • the data signal line D is maintained in a high impedance state throughout the idle period.
  • a rest step is realized by the operation during this rest period.
  • the organic EL element 21 changes according to the magnitude of the drive current, as in the time just before time t71 (see FIG. 28) in the drive period. It is emitting light.
  • the first emission control signal EM1(n-1) and the first emission control signal EM1(n) change from high level to low level.
  • the light emission control transistor T5 is turned off in the first pixel circuit and the second pixel circuit.
  • the current supply to the organic EL element 21 is cut off, and the organic EL element 21 is turned off.
  • the third scanning signal SCAN3(n ⁇ 1) and the third scanning signal SCAN3(n) change from low level to high level.
  • the initialization transistor T6 is turned on, and the initialization voltage Vini is applied to the node N3.
  • the anode voltage of the organic EL element 21 is initialized in the first pixel circuit and the second pixel circuit.
  • the first emission control signal EM1(n-1) and the first emission control signal EM1(n) change from low level to high level.
  • the light emission control transistor T5 is turned on in the first pixel circuit and the second pixel circuit.
  • the third scanning signal SCAN3(n-1) and the third scanning signal SCAN3(n) change from high level to low level.
  • the initialization transistor T6 is turned off in the first pixel circuit and the second pixel circuit.
  • the power supply control transistor T4 is maintained in the ON state.
  • a drive current corresponding to the charging voltage of the holding capacitor Cst is supplied to the organic EL element 21, and the organic EL element 21 emits light according to the magnitude of the drive current.
  • the organic light is emitted in the first pixel circuit and the second pixel circuit.
  • the EL element 21 emits light.
  • FIG. 30 is a block diagram showing a schematic configuration of the scanning side drive circuit 300 in this embodiment.
  • the scanning-side driving circuit 300 includes a first scanning signal line driving circuit 31, a second scanning signal line driving circuit 32, a third scanning signal line driving circuit 36, a first emission control line driving circuit 33, and a second emission control line driving circuit. 34.
  • the first scanning signal line driving circuit 31 applies the first scanning signal SCAN1 to the first scanning signal line
  • the second scanning signal line driving circuit 32 applies the second scanning signal SCAN2 to the second scanning signal line
  • the third scanning signal line The scanning signal line driving circuit 36 applies the third scanning signal SCAN3 to the third scanning signal line
  • the first emission control line driving circuit 33 applies the first emission control signal EM1 to the first emission control line
  • the second emission is performed.
  • the control line drive circuit 34 applies the second emission control signal EM2 to the second emission control line.
  • the first scanning signal line driving circuit 31, the second scanning signal line driving circuit 32, the first emission control line driving circuit 33, and the second emission control line driving circuit 34 have the same configuration as in the first embodiment. are doing. Therefore, detailed description of those configurations is omitted.
  • the third scanning signal line driving circuit 36 is configured by a shift register including unit circuits 360 whose number is equal to half the number of the third scanning signal lines SCAN3. That is, each unit circuit included in the shift register forming the third scanning signal line driving circuit 36 corresponds to two third scanning signal lines SCAN3. Therefore, the i third scanning signal lines SCAN3(1) to SCAN3(i) are driven two by two by the third scanning signal line driving circuit .
  • FIG. 31 is a block diagram showing the configuration of the third scanning signal line driving circuit 36.
  • the shift register constituting the third scanning signal line driving circuit 36 includes a clock signal S3CK1, a clock signal S3CK2, a start pulse E3SP (not shown in FIG. 31), a high-level power supply voltage GVDD, and a low-level power supply voltage GVDD.
  • a level power supply voltage GVSS is applied.
  • Other points are the same as the second scanning signal line driving circuit 32, so detailed description of the third scanning signal line driving circuit 36 is omitted.
  • the pulse width (length of high level period) of the start pulse S3SP is 5H.
  • the clock signals S3CK1 and S3CK2 have a high level period of 0.5H and a low level period of 3.5H. Other signals are the same as those in the first embodiment.
  • the clock signal E1CK1 changes from low level to high level, whereby the emission control signals EM1(1) and EM1(2) change from high level to low level.
  • the emission control transistors T5 are turned off, and the organic EL elements 21 are turned off.
  • the clock signal S3CK1 changes from low level to high level after the start pulse S3SP changes from low level to high level, whereby the third scanning signals SCAN3(1) and SCAN3(2) change from low level to high level. Change.
  • the initialization transistors T6 are turned on, and the anode voltages of the organic EL elements 21 are initialized.
  • the timing at which the emission control signals EM1(1) and EM1(2) change from high level to low level and the timing at which the third scanning signals SCAN3(1) and SCAN3(2) change from low level to high level is the same as Note that the start pulse S1SP changes from low level to high level before the start pulse E1SP changes from high level to low level.
  • the first scanning signal SCAN1(1) changes from low level to high level.
  • the threshold voltage compensation transistor T3 is turned on, and the holding voltage of the holding capacitor Cst is initialized.
  • the clock signal S1CK2 changes from low level to high level, thereby changing the first scanning signal SCAN1(2) from low level to high level.
  • the threshold voltage compensation transistor T3 is turned on, and the holding voltage of the holding capacitor Cst is initialized.
  • the start pulse E2SP changes from high level to low level at the timing when the first scanning signal SCAN1 (2) changes from low level to high level.
  • the second emission control signals EM2(1) and EM2(2) change from high level to low level.
  • the power supply control transistors T4 are turned off.
  • the clock signal S2CK1 changes from low level to high level after the start pulse S2SP changes from low level to high level, whereby the second scanning signals SCAN2(1) and SCAN2(2) change from low level to high level. Change.
  • the write control transistors T1 are turned on in the pixel circuits 20 on the first row and the pixel circuits 20 on the second row.
  • the start pulse S1SP changes from low level to high level again.
  • the clock signal S1CK1 changes from low level to high level
  • the first scanning signal SCAN1(1) changes from low level to high level.
  • the threshold voltage compensation transistor T3 is turned on in the pixel circuit 20 of the first row.
  • the power supply control transistor T4 and the light emission control transistor T5 are in the OFF state, and the initialization transistor T6 is in the ON state. Therefore, in the pixel circuit 20 of the first row, the holding capacitor Cst is charged with a voltage corresponding to the data signal D so as to compensate for variations in the threshold voltage of the driving transistor T2.
  • the clock signal S1CK2 changes from low level to high level
  • the first scanning signal SCAN1(2) changes from low level to high level.
  • a holding capacitor Cst is charged with a voltage corresponding to the data signal D so as to compensate for variations.
  • the anode voltage of the organic EL element 21 is initialized and the lighting state/state of the organic EL element 21 is changed. Switching of the off state is performed every two rows.
  • the second scanning signal lines SCAN2 and the third scanning signal lines SCAN3 are driven two by two, the first scanning signal lines SCAN1 are driven one by one. Data is written into the circuit 20 row by row.
  • the pulse width (length of high level period) of the start pulse S3SP is 5H.
  • the clock signals S3CK1 and S3CK2 have a high level period of 0.5H and a low level period of 3.5H.
  • the pulse width (length of low level period) of the start pulse E1SP is 8H.
  • the clock signals S2CK1, S2CK2, E1CK1, E1CK2, E2CK1, and E2CK2 are the same as in the first embodiment. Note that the start pulses S1SP and S2SP and the clock signals S1CK1 and S1CK2 are maintained at low level throughout the idle period, and the start pulse E2SP is maintained at high level throughout the idle period. Also, as described above, all data signal lines D are maintained in a high impedance state throughout the idle period.
  • the clock signal E1CK1 changes from low level to high level, whereby the emission control signals EM1(1) and EM1(2) change from high level to low level.
  • the emission control transistors T5 are turned off, and the organic EL elements 21 are turned off.
  • the clock signal S3CK1 changes from low level to high level after the start pulse S3SP changes from low level to high level, whereby the third scanning signals SCAN3(1) and SCAN3(2) change from low level to high level. Change.
  • the initialization transistors T6 are turned on, and the anode voltages of the organic EL elements 21 are initialized.
  • the clock signal S3CK1 changes from low level to high level, whereby the third scanning signals SCAN3(1) and SCAN3(2) change from high level to low level. Change.
  • the initialization transistors T6 are turned off.
  • the emission control signals EM1(1) and EM1(2) change from low level to high level. do.
  • the light emission control transistors T5 are turned on.
  • the driving current corresponding to the charging voltage of the holding capacitor Cst is supplied to the organic EL element 21, and the organic EL element 21 emits light according to the magnitude of the driving current. .
  • the pixel circuit 20 is composed of one organic EL element 21, six N-channel transistors T1 to T6, and one holding capacitor Cst. (See FIG. 27).
  • the first emission control line drive circuit 33 that drives the first emission control line EM1 and the second emission control line drive circuit 34 that drives the second emission control line EM2 are provided separately.
  • the organic EL display device has been described as an example in each of the above-described embodiments (including modifications), the present invention is not limited to this.
  • the above disclosure can be applied to an inorganic EL display device, a QLED display device, or the like as long as the display device uses a display element driven by current.
  • Organic EL display panel 20 Pixel circuit 21 Organic EL element 31 First scanning signal line driving circuit 32 Second scanning signal line driving circuit 33 First emission control line driving circuit 34 Second emission control line driving Circuit 35 -- Emission control line drive circuit 36 -- Third scanning signal line drive circuit 100 -- Display control circuit 200 -- Display section 300 -- Scan side drive circuit 310, 320, 330, 340, 350, 360 -- Unit circuit 400 -- Data side Drive circuit SCAN1...first scanning signal line, first scanning signal SCAN2...second scanning signal line, second scanning signal SCAN3...third scanning signal line, third scanning signal EM1...first emission control line, first emission control Signal EM2 Second emission control line Second emission control signal T1 Write control transistor T2 Drive transistor T3 Threshold voltage compensation transistor T4 Power supply control transistor T5 Light emission control transistor T6 Initialization transistor

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
  • Electroluminescent Light Sources (AREA)
  • Shift Register Type Memory (AREA)
  • Thin Film Transistor (AREA)
PCT/JP2021/025247 2021-07-05 2021-07-05 表示装置およびその駆動方法 Ceased WO2023281556A1 (ja)

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US18/566,949 US12190828B2 (en) 2021-07-05 2021-07-05 Display device and method for driving same
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