WO2023279606A1 - 复合信号复位电路、方法及服务器 - Google Patents

复合信号复位电路、方法及服务器 Download PDF

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WO2023279606A1
WO2023279606A1 PCT/CN2021/129247 CN2021129247W WO2023279606A1 WO 2023279606 A1 WO2023279606 A1 WO 2023279606A1 CN 2021129247 W CN2021129247 W CN 2021129247W WO 2023279606 A1 WO2023279606 A1 WO 2023279606A1
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signal
reset
circuit
signal input
input circuit
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PCT/CN2021/129247
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English (en)
French (fr)
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王凯博
张晓梅
王秋娟
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南昌华勤电子科技有限公司
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Publication of WO2023279606A1 publication Critical patent/WO2023279606A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • the present application relates to the technical field of reset circuits, in particular to a composite signal reset circuit, method and server.
  • the reset circuit belongs to the basic part of the hardware circuit architecture, especially for servers with a main control system and a programmable control system, the reset circuit generally needs to be reset according to two signals, such as with a programmable controller (CPLD) and a board
  • CPLD programmable controller
  • BMC level controller
  • the reset circuit should reset the server according to the comprehensive effect of the power-on reset signal and the active reset signal sent by the CPLD, that is, the power-on reset signal and the active reset signal line sent by the CPLD are connected with the target reset Signal.
  • CPLD programmable controller
  • BMC level controller
  • the target reset signal has been kept in a low level state, and the reset cannot be completed, so that the BMC cannot work, which will cause the entire server system with the CPLD to fail to work, and then cause the FW (firmware, written into the CPLD) of the CPLD to be unable to re-upgrade. ), and the user prefers that when the CPLD is abnormal, the BMC can work normally, so that the upgrade of the CPLD can be carried out again.
  • the embodiment of the present application discloses a composite signal reset circuit, which includes a first signal input circuit and a second signal input circuit, the first signal input circuit is used to collect the first reset signal, and the second signal input circuit is used to For collecting the second reset signal, the output end of the first signal input circuit is electrically connected to the output end of the second reset circuit to form a target reset signal output end; the signal input end of the second signal input circuit A differential circuit is provided.
  • the differential circuit includes a capacitor and an operational amplifier connected in series.
  • the capacitor is 0.8-2uF, and the feedback resistance between the output terminal and the inverting input terminal of the operational amplifier is 0.8-1.5K ⁇ .
  • the second signal input circuit further includes a first switch tube electrically connected to the output terminal of the operational amplifier.
  • the first signal input circuit includes a second switch tube and a third switch tube, and both the second switch tube and the third switch tube are reverse output switch elements; the second switch tube The control terminal is electrically connected to the signal input terminal for receiving the first reset signal; the output terminal of the second switching tube is electrically connected to the control terminal of the third switching tube, and the output terminal of the third switching tube The output end is electrically connected with the output end of the first signal input circuit.
  • the first reset signal is a power reset signal
  • the second reset signal is a reset signal output by a programmable controller.
  • the first switch transistor is a triode.
  • the embodiment of the present application also discloses a composite signal reset method, which includes:
  • the second reset signal is collected through a second signal input circuit, and a differential circuit for judging the second reset signal is provided in the second signal input circuit.
  • the present application also discloses a server, which includes a main body, a system main board is arranged in the main body, a main control system and a programmable control system are arranged on the system main board, and the composite signal reset circuit as described above, the first A signal input circuit is electrically connected to the main control system, and the second signal input circuit is electrically connected to the programmable control system.
  • the beneficial technical effect of adopting the composite signal reset circuit in the server of the present application is: when the server needs to generate the first reset signal according to the main control system (BMC) and the first reset signal generated by the programmable control system (CPLD).
  • BMC main control system
  • CPLD programmable control system
  • Two reset signals When two reset signals are combined to generate the target reset signal, if the second reset signal is abnormal (continuously maintained at high or low level), then the differential circuit set at the signal input terminal of the second signal input circuit The second reset signal is shielded, so that the server can be reset according to the first reset signal alone without being affected by the abnormal second reset signal, and the BMC can work normally, so that the upgrading work of the CPLD can be carried out again.
  • FIG. 1 is a schematic diagram of the principle of a composite signal reset method in an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a composite signal reset circuit in an embodiment of the present application.
  • Fig. 3 is a diagram of the impulse response of the differential circuit in the embodiment of the present application.
  • the server includes a main body, a system main board is arranged in the main body, a main control system (BMC) and a programmable control system (CPLD) are arranged on the system main board, both BMC and CPLD can issue Reset signal, the server resets according to the composite reset signal of BMC and CPLD, BMC can not work normally when avoiding CPLD to appear abnormal (as upgrade hanging dead), adopt following composite reset method to reset server in the present embodiment.
  • BMC main control system
  • CPLD programmable control system
  • the composite reset method includes:
  • the first reset signal is sent by the BMC
  • the second reset signal is sent by the CPLD
  • the BMC After the last power output of the server's power-on sequence is normal, the BMC outputs the first reset signal ALL_PWR_GOOD signal, and the second reset signal is the CPLD_RST signal actively sent by the CPLD.
  • the target reset signal is the low-level active IC_RST_N signal.
  • ALL_PWR_GOOD When both the signal and the CPLD_RST signal are in a normal state, the IC_RST_N signal used to reset the server is generated by performing a wired AND logic operation on the ALL_PWR_GOOD signal and the CPLD_RST signal.
  • the CPLD_RST signal When the CPLD upgrade fails and enters the hang state, the CPLD_RST signal is abnormal, which will make the BMC unable to work, and then cause the FW (firmware, written into the CPLD) of the CPLD to be unable to re-upgrade.
  • the CPLD_RST signal It is shielded to eliminate its influence on the IC_RST_N signal, so that the IC_RST_N signal can be generated normally according to the ALL_PWR_GOOD signal, so that the server can be reset normally, and the BMC can work normally, so that the upgrade of the CPLD can be carried out again.
  • the application also discloses a composite signal reset circuit, which includes two signal input circuits, respectively a first signal input circuit 10 and a second signal input circuit 20, the first signal input circuit 10 is used to collect the first reset signal, and the second signal input circuit 20 is used to collect the second reset signal.
  • the output terminal of the first signal input circuit 10 is electrically connected to the output terminal of the second reset circuit to form a target reset signal output Terminal OUT.
  • the signal input terminal of the second signal input circuit 20 is provided with a differentiating circuit CW. Through the differential circuit CW, there is output only when the input waveform of the second reset signal changes abruptly, and there is no output for the constant part, thereby forming a shield for the constant part.
  • the first signal input circuit 10 is electrically connected to the main control system
  • the second signal input circuit 20 is electrically connected to the programmable control system.
  • the differential circuit CW includes a capacitor C1 and an operational amplifier U1 connected in series, thereby forming an operational amplifier differential circuit.
  • the capacitor C1 is electrically connected to the signal input terminal IN2 for receiving the second reset signal.
  • Figure 3 According to the impulse response diagram of the operational amplifier differential circuit CW, it can be seen that when the CPLD is required to actively reset the server, the CPLD sends a CPLD_RST signal (pulse signal), and the CPLD_RST signal passes through the differential circuit CW to reset the server.
  • the capacitor C1 plays the role of isolation, so that the output of the operational amplifier U1 is zero, thereby completing the shielding of the CPLD_RST signal.
  • the capacitor C1 is 0.8-2uF
  • the feedback resistor R6 between the output terminal and the inverting input terminal of the operational amplifier U1 is 0.8-1.5K ⁇ .
  • the capacitor C1 is preferably 1uF
  • the feedback resistor R6 is preferably 1K ⁇ .
  • those skilled in the art can also make adjustments to the composition of the differential circuit CW, such as using RC elements to form the differential circuit CW.
  • the second signal input circuit 20 further includes a first switch tube Q1 electrically connected to the output terminal of the operational amplifier U1 .
  • the first switching tube Q1 is an NPN transistor
  • the output terminal of the operational amplifier U1 is electrically connected to the base of the first switching tube Q1
  • the emitter of the first switching tube Q1 is grounded
  • the collector is The output terminal
  • the first switch tube Q1 is electrically connected to the output terminal of the first signal input circuit 10 .
  • the operational amplifier UI is electrically connected to the first switch tube Q1 through a current limiting resistor R5.
  • the first signal input circuit 10 includes a second switching tube Q2 and a third switching tube Q3. Both the second switching tube Q2 and the third switching tube Q3 are inverting output switching elements. , that is, the output level state is opposite to the input level state. When the input bit is low, the output is high level, and when the input bit is high level, the output is low level.
  • the control terminal of the second switch tube Q2 is electrically connected to the signal input terminal IN1 for receiving the first reset signal.
  • the output terminal of the second switching tube Q2 is electrically connected to the control terminal of the third switching tube Q3.
  • a current limiting resistor R1 is arranged between the second switching tube Q2 and the third switching tube Q3, and the second switching tube Q2 and the third switching tube Q3 are connected electrically.
  • a current limiting resistor R3 is set between the signal input terminals IN1.
  • the output end of the third switching transistor Q3 is electrically connected to the output end of the first signal input circuit 10 .
  • both the second switching transistor Q2 and the third switching transistor Q3 are N-channel MOS transistors, and a voltage source VCC1 is provided between the gate and the source of the second switching transistor Q2 and the third switching transistor Q3,
  • the voltage source VCC1 is electrically connected to the gates of the second switching transistor Q2 and the third switching transistor Q3 through the current limiting resistors R4 and R2 respectively.
  • the target reset signal output terminal OUT is also electrically connected to a voltage source VCC2, and the voltage source VCC2 is electrically connected to the target reset signal output terminal OUT through a current limiting resistor R7.
  • the first reset signal is active at a high level, thus, when the first reset signal is a power-on completion signal, it can effectively ensure the automatic power-on completion signal. reset.
  • the working process of the composite signal reset circuit disclosed in the above embodiment is: after the power-on sequence in the server is completed, the ALL_PWR_GOOD signal is at a high level, and the ALL_PWR_GOOD signal is passed through the second switch tube Q2 After that, it becomes a low level, and then becomes a high level after passing through the third switch tube Q3.
  • a CPLD_RST signal (low level pulse of 200ms) is sent out.
  • the CPLD_RST signal passes through the differential circuit CW and then turns on the first switch tube Q1.
  • the first switch tube Q1 outputs a low level , the IC_RST_N signal is pulled low, and then, at the rising edge of the CPLD_RST signal, the first switching tube Q1 outputs a high level to complete the reset operation.
  • the CPLD_RST signal continues to be at a high level, and the first switch Q1 cannot be turned on through the differential circuit CW, so that the server can be reset normally under the action of the ALL_PWR_GOOD signal to ensure the normal operation of the BMC.

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Abstract

一种复合信号复位电路、方法及服务器，其中该复位电路包括用于采集第一复位信号的第一信号输入电路(10)和用于采集第二复位信号的第二信号输入电路(20)，第一信号输入电路(10)的输出端与第二复位电路的输出端电性连接，以形成目标复位信号输出端；第二信号输入电路(20)的信号输入端设置有微分电路；当服务器需要根据第一复位信号和第二复位信号两路复位信号来生成目标复位信号时，如果第二复位信号发生异常(持续保持在高电平或低电平)，那么通过第二信号输入电路(20)的信号输入端设置的微分电路将该第二复位信号屏蔽，从而使得服务器可不受异常的第二复位信号的影响而单独根据第一复位信号进行复位，进而使得服务器可正常工作。

Description

复合信号复位电路、方法及服务器
本申请要求于2021年07月08日提交中国专利局、申请号为202110775070.4、发明名称为“复合信号复位电路、方法及服务器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及复位电路技术领域，尤其涉及一种复合信号复位电路、方法及服务器。
背景技术
复位电路，属于硬件电路架构的基础部分，特别是对于带有主控系统和可编程控制系统的服务器，复位电路一般要根据两种信号进行复位，如带有可编程控制器(CPLD)和板级控制器(BMC)的服务器，复位电路要根据上电复位信号和CPLD发出的主动复位信号综合作用对服务器进行复位，也即将上电复位信号和CPLD发出的主动复位信号线与后生成目标复位信号。在使用过程中，对于这种复位电路，存在下述弊端：在CPLD挂死或者升级CPLD软件中途卡死时，CPLD会随机保持在高电平或低电平，如果是高电平，会使得目标复位信号一直保持在低电平状态，不能完成复位，使得BMC无法工作，这将导致连带CPLD的整个服务器系统都无法工作，进而导致无法重新升级CPLD的FW(固件，写入CPLD中的程序)，而用户更希望在CPLD出现异常时，BMC可以正常工作，使得CPLD的升级工作可以从新进行。
发明内容
本申请实施例公开了一种复合信号复位电路，其包括第一信号输入电路和第二信号输入电路，所述第一信号输入电路用于采集第一复位信号，所述第二信号输入电路用于采集第二复位信号，所述第一信号输入电路的输出端与所述第二复位电路的输出端电性连接，以形成目标复位信号输出端；所述第二信号输入电路的信号输入端设置有微分电路。
较佳的，所述微分电路包括串联连接的电容器和运算放大器。
较佳的，所述电容器为0.8～2uF，所述运算放大器的输出端与反向输入端之间的反馈电阻为0.8～1.5KΩ。
较佳的，所述第二信号输入电路还包括与所述运算放大器的输出端电性连接的第一开关管。
较佳的，所述第一信号输入电路包括第二开关管和第三开关管，所述第二开关管和所述第三开关管皆为反向输出开关元件；所述第二开关管的控制端与信号输入端电性连接，用于接收所述第一复位信号；所述第二开关管的输出端与所述第三开关管的控制端电性连接，所述第三开关管的输出端与所述第一信号输入电路的输出端电性连接。
较佳的，所述第一复位信号为电源复位信号，所述第二复位信号为可编程控制器输出的复位信号。
较佳的，所述第一开关管为三极管。
本申请实施例还公开一种复合信号复位方法，其包括：
实时采集两复位信号，分别为第一复位信号和第二复位信号；
判断所述第二复位信号是否为状态变化波形信号，如果是，
则将所述第一复位信号和所述第二复位信号做线与逻辑运算后输出，以得到目标复位信号；如果否，
则屏蔽所述第二复位信号，根据所述第一复位信号输出所述目标复位信号。
较佳的，通过第二信号输入电路采集所述第二复位信号，所述第二信号输入电路中设置有用于对所述第二复位信号进行判断处理的微分电路。
本申请还公开一种服务器，其包括主体，所述主体中设置有系统主板，所述系统主板上设置有主控系统和可编程控制系统，以及如上所述的复合信号复位电路，所述第一信号输入电路与所述主控系统电性连接，所述第二信号输入电路与所述可编程控制系统电性连接。
与现有技术相比，本申请的服务器采用上述复合信号复位电路的有益技术效果是：当服务器需要根据主控系统(BMC)产生的第一复位信号和可编程控制系统(CPLD)产生的第二复位信号两路复位信号来综合生成目 标复位信号时，如果第二复位信号发生异常(持续保持在高电平或低电平)，那么通过第二信号输入电路的信号输入端设置的微分电路将该第二复位信号屏蔽，从而使得服务器可不受异常的第二复位信号的影响而单独根据第一复位信号进行复位，BMC可以正常工作，进而使得CPLD的升级工作可以从新进行。
附图说明
图1为本申请实施例中复合信号复位方法的原理示意图。
图2为本申请实施例中复合信号复位电路的原理结构示意图。
图3为本申请实施例中微分电路冲击响应图。
具体实施方式
为详细说明本申请的技术内容、构造特征、所实现目的及效果，以下结合实施方式并配合附图详予说明。
本实施例公开了本申请公开一种服务器，该服务器包括主体，主体中设置有系统主板，系统主板上设置有主控系统(BMC)和可编程控制系统(CPLD)，BMC和CPLD均可发出复位信号，服务器根据BMC和CPLD的复合复位信号进行复位，为避免CPLD出现异常(如升级挂死)时BMC不能正常工作，本实施例中采用下述复合复位方法对服务器进行复位。
如图1，该复合复位方法包括：
实时采集两复位信号，分别为第一复位信号和第二复位信号，对于上述服务器来说，第一复位信号由BMC发出，第二复位信号由CPLD发出；
判断第二复位信号是否为状态变化波形信号，也即是否处于高低电平变化的状态，如果是，
则将第一复位信号和第二复位信号做线与逻辑运算后输出，以得到目标复位信号，通过该目标复位信号对服务器进行复位；如果否，
则屏蔽第二复位信号，根据第一复位信号输出目标复位信号。
下面具体说明服务器采用上述复合复位方法的工作原理：
服务器的电源上电时序的最后一个电源输出正常后，BMC输出第一复 位信号ALL_PWR_GOOD信号，第二复位信号是由CPLD主动发出的CPLD_RST信号，目标复位信号为低电平有效的IC_RST_N信号，当ALL_PWR_GOOD信号和CPLD_RST信号都处于正常状态时，用于对服务器进行复位的IC_RST_N信号是由ALL_PWR_GOOD信号和CPLD_RST信号做线与逻辑运算后生成。当CPLD升级失败而进入挂死状态时，CPLD_RST信号出现异常，这将使得BMC无法工作，进而导致无法重新升级CPLD的FW(固件，写入CPLD中的程序)，而此时，由于对CPLD_RST信号进行了屏蔽，消除了其对IC_RST_N信号造成的影响，使得IC_RST_N信号可根据ALL_PWR_GOOD信号正常产生，从而使得服务器可正常复位，BMC可以正常工作，进而使得CPLD的升级工作可以从新进行。
如图2，为有效实施上述复位方法，本申请还公开一种复合信号复位电路，其包括两信号输入电路，分别为第一信号输入电路10和第二信号输入电路20，第一信号输入电路10用于采集第一复位信号，第二信号输入电路20用于采集第二复位信号，第一信号输入电路10的输出端与第二复位电路的输出端电性连接，以形成目标复位信号输出端OUT。第二信号输入电路20的信号输入端设置有微分电路CW。通过该微分电路CW，只有第二复位信号的输入波形发生突变的瞬间才有输出，而对恒定部分则没有输出，从而形成对恒定部分的屏蔽。对于上述实施例中的服务器来说，第一信号输入电路10与主控系统电性连接，第二信号输入电路20与可编程控制系统电性连接。
具体的，微分电路CW包括串联连接的电容器C1和运算放大器U1，从而构成运放微分电路。电容器C1与信号输入端IN2电性连接，用于接收第二复位信号。请结合参阅图3，根据该运放微分电路CW的冲击响应图可知，在需要CPLD主动复位服务器时，CPLD发出CPLD_RST信号(脉冲信号)，CPLD_RST信号通过该微分电路CW后去复位服务器。在CPLD挂死时，CPLD_RST信号处于固定的电平，电容器C1起到了隔离的作用，使得运算放大器U1的输出为零，从而完成对CPLD_RST信号的屏蔽。更具体的，电容器C1为0.8～2uF，运算放大器U1的输出端与反向输入端之间的反馈电阻R6为0.8～1.5KΩ，本实施例中，电容器C1优选为1uF，反馈电阻R6优选为 1KΩ。另外需要说明的是，本领域技术人员也可对微分电路CW的构成做出调整，如采用RC元件构成微分电路CW。
进一步的，如图2，第二信号输入电路20还包括与运算放大器U1的输出端电性连接的第一开关管Q1。本实施例中，该第一开关管Q1为NPN型三极管，运算放大器U1的输出端与该第一开关管Q1的基极电性连接，该第一开关管Q1的发射极接地，集电极为输出端，该第一开关管Q1与第一信号输入电路10的输出端电性连接。具体的，运算放大器UI通过一限流电阻R5与第一开关管Q1电性连接。
更进一步的，请再次参阅图2，对于第一信号输入电路10，其包括第二开关管Q2、第三开关管Q3，第二开关管Q2和第三开关管Q3皆为反向输出开关元件，也即输出电平状态与输入电平状态相反，当输入位低电平，输出则为高电平，当输入位高电平，则输出为低电平。第二开关管Q2的控制端与信号输入端IN1电性连接，用于接收第一复位信号。第二开关管Q2的输出端与第三开关管Q3的控制端电性连接，具体地，第二开关管Q2与第三开关管Q3之间设置有一限流电阻R1，第二开关管Q2与信号输入端IN1之间设置一限流电阻R3。第三开关管Q3的输出端与第一信号输入电路10的输出端电性连接。本实施例中，第二开关管Q2和第三开关管Q3皆为N沟道MOS管，第二开关管Q2和第三开关管Q3的栅极和源极之间均设置有电压源VCC1，电压源VCC1分别通过限流电阻R4、R2与第二开关管Q2和第三开关管Q3的栅极电性连接。另外，目标复位信号输出端OUT还电性连接有电压源VCC2，该电压源VCC2通过限流电阻R7与目标复位信号输出端OUT电性连接。
通过第二开关管Q2和第三开关管Q3的串联设计，使得第一复位信号高电平有效，从而，当第一复位信号为电源上电完成信号时，可有效保证电源上电完成的自动复位。
综上，如图1至图3，上述实施例公开的复合信号复位电路的工作过程为：当服务器中的上电时序完成后，ALL_PWR_GOOD信号为高电平，该ALL_PWR_GOOD信号通过第二开关管Q2后变为低电平，再通过第三开关管Q3后又变为高电平。CPLD主动复位时，发出CPLD_RST信号(200ms 的低电平脉冲)，CPLD_RST信号通过微分电路CW后开启第一开关管Q1，因此，从CPLD_RST信号的下降沿开始，第一开关管Q1输出低电平，将IC_RST_N信号拉低，然后，在CPLD_RST信号的上升沿，第一开关管Q1输出高电平，完成复位动作。而当CPLD出现异常时，CPLD_RST信号持续处于高电平，不能通过微分电路CW开启第一开关管Q1，从而使得服务器在ALL_PWR_GOOD信号的作用下可正常复位，保证BMC的正常工作。
以上所揭露的仅为本申请的优选实施例而已，当然不能以此来限定本申请之权利范围，因此依本申请专利范围所作的等同变化，仍属本申请所涵盖的范围。

Claims (10)

  1. 一种复合信号复位电路，其特征在于，包括第一信号输入电路和第二信号输入电路，所述第一信号输入电路用于采集第一复位信号，所述第二信号输入电路用于采集第二复位信号，所述第一信号输入电路的输出端与所述第二复位电路的输出端电性连接，以形成目标复位信号输出端；所述第二信号输入电路的信号输入端设置有微分电路。
  2. 根据权利要求1所述的复合信号复位电路，其特征在于，所述微分电路包括串联连接的电容器和运算放大器。
  3. 根据权利要求2所述的复合信号复位电路，其特征在于，所述电容器为0.8～2uF，所述运算放大器的输出端与反向输入端之间的反馈电阻为0.8～1.5KΩ。
  4. 根据权利要求2所述的复合信号复位电路，其特征在于，所述第二信号输入电路还包括与所述运算放大器的输出端电性连接的第一开关管。
  5. 根据权利要求1所述的复合信号复位电路，其特征在于，所述第一信号输入电路包括第二开关管和第三开关管，所述第二开关管和所述第三开关管皆为反向输出开关元件；所述第二开关管的控制端与信号输入端电性连接，用于接收所述第一复位信号；所述第二开关管的输出端与所述第三开关管的控制端电性连接，所述第三开关管的输出端与所述第一信号输入电路的输出端电性连接。
  6. 根据权利要求1所述的复合信号复位电路，其特征在于，所述第一复位信号为电源复位信号，所述第二复位信号为可编程控制器输出的复位信号。
  7. 根据权利要求4所述的复合信号复位电路，其特征在于，所述第一开关管为三极管。
  8. 一种复合信号复位方法，其特征在于，包括：
    实时采集第一复位信号和第二复位信号；
    判断所述第二复位信号是否为状态变化波形信号，如果是，
    则将所述第一复位信号和所述第二复位信号做线与逻辑运算后输出，以得到目标复位信号；如果否，
    则屏蔽所述第二复位信号，根据所述第一复位信号输出所述目标复位信号。
  9. 根据权利要求8所述的复合信号复位方法，其特征在于，通过第二信号输入电路采集所述第二复位信号，所述第二信号输入电路中设置有用于对所述第二复位信号进行判断处理的微分电路。
  10. 一种服务器，其特征在于，包括主体，所述主体中设置有系统主板，所述系统主板上设置有主控系统和可编程控制系统，以及如权利要求1至7任一项所述的复合信号复位电路，所述第一信号输入电路与所述主控系统电性连接，所述第二信号输入电路与所述可编程控制系统电性连接。
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