WO2023279484A1 - 半导体存储器的制作方法及半导体存储器 - Google Patents

半导体存储器的制作方法及半导体存储器 Download PDF

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Publication number
WO2023279484A1
WO2023279484A1 PCT/CN2021/113067 CN2021113067W WO2023279484A1 WO 2023279484 A1 WO2023279484 A1 WO 2023279484A1 CN 2021113067 W CN2021113067 W CN 2021113067W WO 2023279484 A1 WO2023279484 A1 WO 2023279484A1
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WIPO (PCT)
Prior art keywords
contact
bit line
protrusion
substrate
isolation layer
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Application number
PCT/CN2021/113067
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English (en)
French (fr)
Inventor
刘翔
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长鑫存储技术有限公司
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Priority to US17/647,469 priority Critical patent/US11792975B2/en
Publication of WO2023279484A1 publication Critical patent/WO2023279484A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Definitions

  • the present application relates to the technical field of storage devices, and in particular to a method for manufacturing a semiconductor memory and the semiconductor memory.
  • DRAM Dynamic random access memory
  • DRAM Dynamic random access memory
  • DRAM generally consists of a plurality of storage units, and each storage unit usually includes a capacitor and a transistor.
  • the capacitor stores data information, and the transistor controls the reading and writing of the data information in the capacitor.
  • the DRAM includes a substrate, the substrate includes an active region, the active region includes a first contact region and a second contact region, and the substrate is provided with bit line structures arranged at intervals and covered by the bit line structure. Isolation layer.
  • the bit line structure is electrically connected with the first contact area of the active area, a contact hole is formed in the isolation layer, the contact hole is filled with wires, and the wires are used to electrically connect the capacitor with the second contact area of the active area.
  • the contact hole In order to increase the contact area of the wire and the second contact region, the contact hole usually extends into the substrate, so as to increase the surface area of the second contact region exposed in the contact hole.
  • the contact hole In the process of manufacturing the DRAM, holes or gaps are likely to appear in the conductive wires filled in the contact holes, which affects the yield rate of the memory.
  • an embodiment of the present application provides a method for manufacturing a semiconductor memory, which includes: providing a substrate, the substrate is provided with a plurality of active regions arranged at intervals, and the active region includes a first contact region and a A second contact area outside the first contact area, the second contact area is exposed on the surface of the substrate; a protrusion is formed on each of the second contact areas; a plurality of intervals are formed on the substrate A bit line structure is provided, each of the bit line structures is electrically connected to at least one of the first contact regions; a first isolation layer covering the bit line structure and the substrate is formed, and the first isolation layer is provided with A plurality of filling holes, each of the filling holes exposes one of the protrusions, and the surface area of the protrusions exposed in the filling holes is larger than the orthographic projection of the filling holes on the base and the second The overlapping area of the contact area; a wire is formed in the filled hole, and the wire is electrically connected to the protrusion.
  • an embodiment of the present application provides a semiconductor memory, which includes: a substrate, a plurality of active regions arranged at intervals are arranged in the substrate, and the active region includes a first contact region and a A second contact area outside the contact area; a plurality of bit line structures arranged at intervals on the substrate, each of the bit line structures is electrically connected to at least one of the first contact areas; The protrusion on the contact region; the first isolation layer covering the bit line structure, the protrusion and the substrate, the first isolation layer is provided with a plurality of filling holes, and the plurality of filling holes extend to the The above-mentioned protrusion; a wire arranged in the filling hole, the wire is electrically connected to the protrusion, and the contact area between the wire and the protrusion is larger than the orthographic projection of the filling hole on the substrate The overlapping area with the second contact area.
  • Fig. 3 is the plan view of the substrate in the embodiment of the present application.
  • FIG. 4 is a top view of a word line structure in an embodiment of the present application.
  • Figure 5 is a schematic structural view of the substrate in the embodiment of the present application.
  • Fig. 6 is a top view after forming a protrusion in the embodiment of the present application.
  • FIG. 7 is a schematic structural view of the bumps formed in the embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a bit line structure formed in an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram after forming a first isolation layer in an embodiment of the present application.
  • FIG. 10 is a schematic structural view of the filling hole formed in the embodiment of the present application.
  • FIG. 11 is a schematic structural view after forming a third conductive layer in the embodiment of the present application.
  • FIG. 12 is a schematic diagram of the structure after the formation of wires in the embodiment of the present application.
  • FIG. 13 is a schematic structural view of the formation of the fifth conductive layer in the embodiment of the present application.
  • FIG. 14 is a schematic structural diagram after forming a contact pad in an embodiment of the present application.
  • FIG. 15 is a flow chart of forming a bit line structure in an embodiment of the present application.
  • FIG. 16 is a schematic structural diagram after forming the first conductive layer in the embodiment of the present application.
  • FIG. 17 is a schematic structural diagram of the bit line contact window formed in the embodiment of the present application.
  • FIG. 18 is a schematic structural diagram after forming a bit line contact in an embodiment of the present application.
  • FIG. 19 is a top view after forming bit line contacts in the embodiment of the present application.
  • the base is etched along the filling hole 510 so that the bottom of the filling hole 510 is located in the base;
  • a wire 530 is formed in the hole 510 .
  • the conductive wire 530 is deposited and formed in the filled hole 510, the depth of the filled hole 510 is relatively large, and holes or gaps are easily formed in the conductive wire 530, as shown in the area shown by a dotted line circle in FIG.
  • the ability to transmit charges leads to a decrease in the performance of the semiconductor memory, and even affects the yield rate of the semiconductor memory.
  • the embodiment of the present application provides a method for manufacturing a semiconductor memory, by forming a bump on the area corresponding to the base and the filling hole (the second contact area); and then forming a first isolation layer covering the base and the bump, the second An isolation layer has a filling hole, the filling hole exposes the protrusion, and the surface area of the protrusion exposed in the filling hole is greater than the overlapping area of the orthographic projection of the filling hole on the base and the second contact area; and then a wire is formed in the filling hole.
  • the contact area between the wire and the protrusion is larger than the overlapping area between the wire and the second contact area when no protrusion is provided, which reduces the contact resistance between the wire and the protrusion.
  • a protrusion on the base is formed in the filling hole, so that the depth of the filling hole is reduced compared with the related art, so that there are fewer holes or gaps in the conductive wire arranged in the filling hole, and the formation of the conductive wire is improved. Quality, thereby improving the yield rate of the memory.
  • an embodiment of the present application provides a method for manufacturing a semiconductor memory, which includes the following steps:
  • Step S101 providing a substrate, the substrate is provided with a plurality of active regions arranged at intervals, the active region includes a first contact region and a second contact region located outside the first contact region, and the second contact region is exposed on the surface of the substrate.
  • the substrate 100 is used to support various film layers thereon, and the substrate 100 is provided with an active region 110, and the number of the active regions 110 can be provided in multiples. As shown in FIG. Arrangement in an array, it can be understood that the central regions of the multiple active regions 110 are arranged in a dot matrix.
  • the active region 110 is arranged obliquely and extends along the direction D shown in FIG.
  • the first contact region 111 and the second contact region 112 are exposed on the surface of the substrate 100
  • the first contact region 111 is used for electrically connecting the bit line structure
  • the second contact region 112 is used for electrically connecting the capacitor.
  • the first contact region 111 is located in the middle region of the active region 110
  • the second contact region 112 is located in the edge region of the active region 110, that is, the two sides of the first contact region 111 can be provided separately
  • the cross section shown in FIG. 5 is a plane perpendicular to the X direction in FIG. Line (Buried Word Line, referred to as BWL) structure 130
  • the buried word line structure 130 can be provided with multiple, the multiple buried word line structures 130 extend along the second direction, and across the active region 110, so that The first contact region 111 and the second contact region 112 of the active region 110 are spaced apart.
  • a plurality of buried word line structures 130 are shown in the area surrounded by dotted lines in FIG. 4, which extend along the X direction, and each buried word line structure 130 passes through the There are a plurality of active regions 110 , and each active region 110 corresponds to two buried word line structures 130 .
  • the area indicated by the dotted line in FIG. 4 is an active region 110, and two buried word line structures 130 divide the active region 110 into a first contact region 111 in the center and two second contact regions 112 on both sides. .
  • the buried word line structure 130 includes a second insulating layer 131, a fourth conductive layer 132 and a capping layer 133, wherein the second insulating layer 131 is in contact with the active region 110, and the second insulating layer 131
  • the layer 131 surrounds a filling groove, and a fourth conductive layer 132 and a cover layer 133 located on the fourth conductive layer 132 are arranged in the filling groove, and the upper surface of the cover layer 133 is flush with the upper surface of the substrate 100, as shown in FIG.
  • the upper surface of the cover layer 133 and the upper surface of the second insulating layer 131 are exposed, and the cover layer 133 is located in the middle of the second insulating layer 131 .
  • the material of the second insulating layer 131 includes silicon oxide
  • the material of the fourth conductive layer 132 includes one or more of titanium, tantalum, titanium nitride, tungsten nitride, tantalum nitride, tungsten nitride silicon compound, and the capping layer 133
  • the material includes silicon nitride.
  • Step S102 forming a protrusion on each second contact area.
  • a plurality of protrusions 200 are provided, and the plurality of protrusions 200 correspond to the plurality of second contact areas 112 one by one, that is, one protrusion 200 is formed on each second contact area 112 .
  • the orthographic projection of the protrusion 200 on the substrate 100 at least covers the second contact region 112, that is, the second contact region 112 is located within the orthographic projection of the protrusion 200 on the substrate 100.
  • the second contact region 112 is a dotted line, that is, the second contact region 112 is located under the protrusion 200 , and the second contact region 112 is not exposed.
  • the shape of the orthographic projection of the protrusion 200 on the substrate 100 is the same as that of the second contact area 112 , for example, both are parallelograms. As shown in FIG. 7 , the distance L between the edge of the orthographic projection of the protrusion 200 on the substrate 100 and the edge of the second contact region 112 is 3-5 nm.
  • the plane shown in FIG. 7 is a cross section perpendicular to the extending direction of the word line structure 130 (direction X in FIG. 6), and the surface of the protrusion 200 away from the substrate 100 is a curved surface to ensure The surface area of the surface of the protrusion 200 away from the substrate 100 is larger than the surface area of the second contact region 112 exposed to the substrate 100, so that there is a larger contact area between the subsequently formed wire 530 and the protrusion 200, thereby reducing the contact area between the wire 530 and the protrusion 200. contact resistance between them.
  • the surface of the protrusion 200 facing away from the base 100 is arc-shaped.
  • the cross-sectional shape of the protrusion 200 is arc, semicircle or semi-ellipse.
  • the protrusion 200 can be formed by epitaxial growth (Epitaxial Growth) on the second contact region 112 , that is, a protrusion 200 is formed by epitaxial growth on each second contact region 112 .
  • Epitaxial growth can make the protrusion 200 different from the second contact region 112 in terms of conductivity type, resistivity, type and concentration of dopant ions, and the like.
  • the material of the protrusion 200 and the active region 110 can be the same, for example, both are silicon, the protrusion 200 and the active region 110 are doped with predetermined ions, and the predetermined ions in the protrusion 200 and the active region
  • the preset ions in 110 may be of the same type, for example, the preset ions are one of N-type ions or P-type ions.
  • the doping concentration of the bump 200 is greater than that of the active region 110 , so that the electrical contact resistance of the wire 530 in electrical contact with the bump 200 is lower than that of the wire 530 in electrical contact with the second contact region 112 of the active region 110 .
  • a bump 200 is also formed on each first contact region 111, that is, a bump 200 is formed on the first contact region 111 and the second contact region 112 at the same time, so as to reduce the difficulty of forming the bump 200 and facilitate the manufacture of semiconductor memory.
  • the protrusions 200 are distributed in a dot matrix.
  • Step S103 forming a plurality of bit line structures arranged at intervals on the substrate, and each bit line structure is electrically connected to at least one first contact region.
  • bit line Bit Line, BL for short
  • the plurality of bit line structures 400 are parallel and extend along the first direction, and each bit line is electrically connected to at least one first bit line. a contact area 111 .
  • the bit line structures 400 extend along a direction perpendicular to the paper (the Y direction shown in FIG. 6 ), and each bit line structure 400 is connected to the first contact regions 111 of a plurality of active regions 110 in the same column. (as shown by the dotted line in FIG. 6 ) are in contact, and the first contact region 111 of each active region 110 corresponds to one bit line structure 400 .
  • the bit line structure 400 is electrically connected to the first contact region 111 through the bit line structure 400 being in contact with the first contact region 111 .
  • first direction and the second direction may be perpendicular, for example, in the top view shown in FIG. 6, the first direction is the vertical direction (Y direction), and the second direction is the horizontal direction (X direction),
  • the active region 110 is arranged obliquely.
  • the word line structure 130 is located in the substrate 100 and passes through the active region 110 along the second direction;
  • the bit line structure 400 is located on the substrate 100 and contacts the active region 110 along the first direction.
  • a first insulating layer 300 is disposed between the bit line structure 400 and other regions of the substrate 100 to ensure that the bit line structure 400 is only electrically connected to the first contact region 111 .
  • Step S104 forming a first isolation layer covering the bit line structure and the substrate, a plurality of filling holes are provided in the first isolation layer, each filling hole exposes a protrusion, and the surface area of the protrusion exposed in the filling hole is larger than that of the filling hole The overlapping area of the orthographic projection on the substrate and the second contact area.
  • the first isolation layer 500 is disposed on the substrate 100 and covers the bit line structure 400 , supports and isolates the bit line structure 400 , and acts as a base for filling the hole 510 .
  • the material of the first isolation layer 500 may be an insulating material, such as silicon nitride.
  • a plurality of filling holes 510 are formed in the first isolation layer 500, and the plurality of filling holes 510 are arranged at intervals, and each filling hole 510 exposes a protrusion 200, that is, between the plurality of filling holes 510 and the plurality of protrusions 200.
  • the surface area of the protrusion 200 exposed in the filling hole 510 is greater than the overlapping area of the orthographic projection of the filling hole 510 on the substrate 100 and the second contact region 112 , so that there is a larger contact between the subsequently formed wire 530 and the protrusion 200 The area improves the electrical performance between the wire 530 and the bump 200 .
  • a first isolation layer 500 is deposited on the bit line structure 400 , and the first isolation layer 500 covers the bit line structure 400 and the first insulating layer 300 .
  • the first isolation layer 500 covers the bit line structure 400 , and the surface of the first isolation layer 500 away from the substrate 100 is flush.
  • the first isolation layer 500 is deposited on the bit line structure 400 , the first isolation layer 500 is etched to form a filling hole 510 penetrating through the first isolation layer 500 and opposite to the protrusion 200 .
  • the first insulating layer 300 is etched along the filling hole 510 , and the filling hole 510 penetrates the first insulating layer 300 so that the filling hole 510 exposes the protrusion 200 .
  • the protrusion 200 as an etching stop layer, etch the first insulating layer 300 along the filled hole 510, the bottom of the filled hole 510 is the surface of the protrusion 200, for example, the part of the curved surface of the protrusion 200 is exposed in the filled hole 510, and the protrusion The exposed surface area of the hole 200 is larger than the cross-sectional area of the filled hole 510.
  • Step S105 forming wires in the filled holes, and the wires are electrically connected to the bumps.
  • the conductive wire 530 fills the filling hole 510 and is in contact with the protrusion 200 . Both the conductive material 530 and the protrusion 200 are electrically connected through contact.
  • forming a wire 530 in the filling hole 510, and the step of electrically connecting the wire 530 to the protrusion 200 includes:
  • a third conductive layer 520 is deposited in the filling hole 510 and on the first isolation layer 500 , the third conductive layer 520 fills the filling hole 510 and covers the first isolation layer 500 .
  • the third conductive layer 520 covers the first isolation layer 500 and the base 100, and the top surface of the third conductive layer 520 is higher than the top surface of the first isolation layer 500, wherein, the height direction refers to away from the base 100 direction.
  • the material of the third conductive layer 520 may be polysilicon.
  • the third conductive layer 520 After depositing the third conductive layer 520, etch the third conductive layer 520, remove the third conductive layer 520 located on the first isolation layer 500 and part of the third conductive layer 520 located in the filled hole 510, and the remaining third conductive layer 520 forms a wire 530 . As shown in FIG. 12 , by depositing a third conductive layer 520 and performing etching back on the third conductive layer 520, after removing part of the third conductive layer 520, the remaining third conductive layer 520 forms a plurality of conductive wires 530 arranged at intervals, The top surface of the wire 530 is lower than the surface of the first isolation layer 500 .
  • the manufacturing method of the semiconductor memory further includes: forming on the wires 530 in each filling hole 510 Contact pads 610 , a plurality of contact pads 610 are arranged at intervals, and each contact pad 610 is partially located in the filling hole 510 and partially located on the first isolation layer 500 .
  • a fifth conductive layer 600 is formed in the remaining filling holes 510 and on the first isolation layer 500 , the fifth conductive layer 600 fills the remaining filling holes 510 and covers the first isolation layer 500 .
  • the fifth conductive layer 600 includes a cobalt silicide layer, a titanium nitride layer and a tungsten layer stacked in sequence.
  • the fifth conductive layer 600 on the first isolation layer 500 is then etched to form a plurality of contact pads 610 arranged at intervals. As shown in FIG.
  • the lower part of the contact pads 610 is located in the filling hole 510 , the upper part of the contact pads 610 is located on the first isolation layer 500 , and there is an interval between each contact pad 610 to electrically isolate each contact pad 610 .
  • the substrate 100 is provided first, and the substrate 100 is provided with a plurality of active regions 110 arranged at intervals.
  • the active region 110 includes the first contact region 111 and the first contact region 111
  • the second contact region 112, the second contact region 112 is exposed on the surface of the substrate 100;
  • a protrusion 200 is formed on each second contact region 112;
  • a plurality of bit line structures 400 arranged at intervals are formed on the substrate 100, each The bit line structure 400 is electrically connected to at least one first contact region 111;
  • a first isolation layer 500 covering the bit line structure 400 and the substrate 100 is formed, and a plurality of filling holes 510 are arranged in the first isolation layer 500, and each filling hole 510 is exposed
  • a protrusion 200, and the surface area of the protrusion 200 exposed in the filling hole 510 is greater than the overlapping area of the orthographic projection of the filling hole 510 on the substrate 100 and the second contact region 112;
  • a wire 530 is formed in the filling
  • the protrusion 200 By forming the protrusion 200 on the second contact region 112, and the surface area of the protrusion 200 exposed in the filling hole 510 is greater than the overlapping area of the orthographic projection of the filling hole 510 on the substrate 100 and the second contact region 112, so that the filling The contact area between the wire 530 in the hole 510 and the protrusion 200 is larger, which reduces the contact resistance between the wire 530 and the protrusion 200 .
  • the protrusion 200 on the substrate 100 is formed in the filling hole 510, so that the depth of the filling hole 510 is reduced compared with the related art, so that when the wire 530 is formed in the filling hole 510, the hole in the wire 530 Or there are fewer gaps, which improves the formation quality of the conductive wire 530, thereby improving the yield rate of the memory.
  • forming a plurality of bit line structures 400 arranged at intervals on the substrate 100, and the step of connecting each bit line structure 400 to at least one first contact region 111 includes:
  • Step S1031 forming a stack of a first insulating layer, a second isolation layer and a first conductive layer on the substrate, and the first insulating layer covers the protrusion.
  • a first insulating layer 300 is deposited on the substrate 100, and the first insulating layer 300 covers the protrusion 200; a second isolation layer 410 is deposited on the first insulating layer 300; A conductive layer 420 .
  • the first insulating layer 300, the second insulating layer 410 and the first conductive layer 420 are stacked, the material of the first insulating layer 300 includes silicon oxide, the material of the second insulating layer 410 includes silicon nitride, and the material of the first conductive layer includes polysilicon .
  • Step S1032 forming a bit line contact window in the first conductive layer, the second isolation layer and the first insulating layer, the bit line contact window penetrates the first conductive layer, the second isolation layer and the first insulating layer and extends to the substrate, the bit line contact window is The line contact exposes the first contact region.
  • the bottom of the bit line contact window 430 is located in the substrate 100 and exposes the first contact region 111 .
  • the remaining first conductive layer 420 , second isolation layer 410 and first insulating layer 300 form a plurality of cylindrical protrusions, which are arranged at intervals, and the bit line contact window 430 surrounds each cylindrical protrusion.
  • Step S1033 forming a bit line contact in the bit line contact window, and removing the first conductive layer and the bit line contact on the second isolation layer, and the remaining bit line contact is flush with the second isolation layer.
  • bit line contact 440 Bit Line Contact, BLC for short
  • the material of the bit line contact 440 may be polysilicon.
  • Step S1034 forming a stacked second conductive layer and a third isolation layer on the bit line contact and the second isolation layer, the second conductive layer covering the bit line contact and the second isolation layer.
  • the material of the layer 460 and the third isolation layer 460 may include silicon nitride.
  • the second conductive layer 450 includes a titanium layer, a metal compound layer and a tungsten layer, the titanium layer, the metal compound layer and the tungsten layer are stacked in sequence, and the titanium layer is in contact with the bit line contact 440 .
  • the material of the metal compound layer can be a cobalt-silicon compound.
  • metal cobalt is deposited on the bit line contact 440, and the metal cobalt is combined with the silicon in the bit line contact 440 under high temperature conditions to form a cobalt-silicon compound to improve the first The electrical properties of the second conductive layer 450 .
  • Step S1035 etching the third isolation layer, the second conductive layer, the second isolation layer and the bit line contact to form a bit line structure extending along the first direction, and the bit line structure passes through a plurality of second isolation layers located in the first direction. a contact zone.
  • the bit line structure 400 extends along the first direction, the bit line structure 400 is in contact with multiple active regions 110 located in the same row or column through bit line contacts 440 .
  • a part of the region is in contact with the first contact region 111, and another part of the region is in contact with the first insulating layer 300, that is, along the extending direction of the bit line structure 400, the first contact region 111 and the first insulating layer 300 are alternately in contact with bit line structures 400 .
  • the embodiment of the present application provides a semiconductor memory
  • the semiconductor memory includes a substrate 100
  • the substrate 100 is used to support the film layers thereon
  • the substrate 100 is provided with an active region 110
  • the active region 110 The number of active regions 110 can be set in multiples, and the active regions 110 are arranged at intervals.
  • shallow trench isolation structures are arranged between the active regions 110 , and the active regions 110 are separated by the shallow trench isolation structures 120 .
  • the active region 110 includes a first contact region 111 and a second contact region 112, the second contact region 112 is located outside the first contact region 111, and the first contact region 111 and the second contact region 112 are exposed on the surface of the substrate 100.
  • a contact region 111 is used for electrically connecting the bit line structure 400, and a second contact region 112 is used for electrically connecting the capacitor.
  • the first contact region 111 is located in the middle region of the active region 110
  • the second contact region 112 is located in the edge region of the active region 110, that is, a second contact region may be provided on both sides of the first contact region 111 112.
  • the substrate 100 is also provided with a word line structure 130, the word line structure 130 is generally a buried word line structure 130 structure, and there may be multiple buried word line structures 130, and the multiple buried word line structures 130 are arranged along the first The two directions (X direction shown in FIG. 6 ) extend across the active region 110 , thereby separating the first contact region 111 and the second contact region 112 of the active region 110 .
  • the second contact region 112 of the substrate 100 is provided with a protrusion 200, and there are multiple protrusions 200, and the plurality of protrusions 200 correspond to the plurality of second contact regions 112 one by one, that is, each second contact region 112 is formed on the second contact region 112.
  • the orthographic projection of the protrusion 200 on the substrate 100 at least covers the second contact area 112 , that is, the second contact area 112 is located within the orthographic projection of the protrusion 200 on the substrate 100 .
  • the section shape of the protrusion 200 is arcuate.
  • the first direction is the extending direction of the bit line structure 400 disposed on the substrate 100 .
  • the orthographic projection of the protrusion 200 on the substrate 100 has the same shape as the second contact area 112, for example, both are parallelograms, and the distance between the edge of the orthographic projection of the protrusion 200 on the substrate 100 and the edge of the second contact area 112 L is 3-5nm.
  • the surface of the protrusion 200 facing away from the substrate 100 is a curved surface, so as to ensure that the surface area of the surface of the protrusion 200 facing away from the substrate 100 is greater than the surface area of the second contact region 112 exposed to the substrate 100, so that the subsequently formed wire 530 There is a larger contact area with the protrusion 200 , reducing the contact resistance between the wire 530 and the protrusion 200 .
  • the substrate 100 is provided with a plurality of bit line structures 400 arranged at intervals.
  • the plurality of bit line structures 400 are parallel and extend along a first direction.
  • Each bit line is electrically connected to at least one first contact region 111 .
  • the bit line structure 400 is electrically connected to the first contact area 111 through the bit line structure 400 being in contact with the first contact area 111 .
  • the bit line structure 400 includes a third isolation layer 460 , a second conductive layer 450 , a second isolation layer 410 and bit line contacts 440 , and the bit line contacts 440 and the second isolation layers 410 are arranged alternately.
  • the bit line contact 440 is in contact with the first contact region 111
  • the second isolation layer 410 is in contact with the first insulating layer 300 .
  • the top surface of the bit line contact 440 is flush with the top surface of the second isolation layer 410
  • the second conductive layer 450 is disposed on the bit line contact 440 and the second isolation layer 410
  • the third isolation layer 460 is disposed on the second conductive layer 450 superior.
  • the second conductive layer 450 includes a titanium layer, a metal compound layer and a tungsten layer, the titanium layer, the metal compound layer and the tungsten layer are stacked in sequence, and the titanium layer is in contact with the bit line contact 440 .
  • the material of the metal compound layer can be metal silicide.
  • the first isolation layer 500 is disposed on the substrate 100 and covers the bit line structure 400 , supports and isolates the bit line structure 400 , and serves as a base for filling the hole 510 .
  • the material of the first isolation layer 500 can be an insulating material, such as silicon nitride.
  • a plurality of filling holes 510 are formed in the first isolation layer 500, and the plurality of filling holes 510 are arranged at intervals, and each filling hole 510 exposes a protrusion 200, that is, there is a one-to-one correspondence between the plurality of filling holes 510 and the plurality of protrusions 200 .
  • the wire 530 is filled in the filling hole 510 , and the top surface of the wire 530 is lower than the top surface of the first isolation layer 500 .
  • the wire 530 is in contact with the protrusion 200 , and both the wire 530 and the protrusion 200 are made of conductive material, and the electrical connection between the wire 530 and the protrusion 200 is realized.
  • the contact area between the conductive wire 530 and the protrusion 200 is greater than the overlapping area of the orthographic projection of the filling hole 510 on the substrate 100 and the second contact area 112, so that there is a larger contact area between the conductive wire 530 and the protrusion 200, which improves the contact area of the conductive wire 530.
  • the electrical performance between the protrusion 200 and the protrusion 200 is filled in the filling hole 510 , and the top surface of the wire 530 is lower than the top surface of the first isolation layer 500 .
  • the wire 530 is in contact with the protrusion 200 , and both the wire 530 and the pro
  • the protrusion 200 on the base 100 is formed in the filling hole 510, so that the depth of the filling hole 510 is reduced compared with the related art, so that there are fewer holes or gaps in the conductive wire 530 disposed in the filling hole 510. , improving the formation quality of the conductive wire 530, thereby improving the yield rate of the memory.

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Abstract

本申请提供一种半导体存储器的制作方法及半导体存储器，涉及存储设备技术领域。该半导体存储器的制作方法包括：提供基底，基底内设有多个间隔设置的有源区，有源区包括第一接触区和第二接触区；在每个第二接触区上形成凸起；在基底上形成多条间隔设置的位线结构；形成覆盖位线结构和基底的第一隔离层，第一隔离层的每个填充孔暴露一个凸起，且凸起暴露在填充孔内的表面积大于填充孔在基底上的正投影与第二接触区的重合面积；在填充孔内形成导线，导线电连接凸起。通过在基底上形成凸起，且凸起与导线电连接，在增大导线与凸起的接触面积的同时减小填充孔的深度，形成在填充孔内的导线的孔洞或缝隙较少。

Description

半导体存储器的制作方法及半导体存储器
本申请要求于2021年07月09日提交中国专利局、申请号为202110779768.3、申请名称为“半导体存储器的制作方法及半导体存储器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及存储设备技术领域，尤其涉及一种半导体存储器的制作方法及半导体存储器。
背景技术
动态随机存储器(Dynamic random access memory，简称DRAM)是一种高速地、随机地写入和读取数据的半导体存储器，被广泛地应用到数据存储设备或装置中。动态随机存储器一般由多个存储单元组成，每个存储单元通常包括电容器和晶体管，电容器存储数据信息，晶体管控制电容器中的数据信息的读写。
相关技术中，动态随机存储器包括基底，基底包括有源区，有源区包括第一接触区和第二接触区，基底上设置有间隔排布的位线结构以及包覆于位线结构外的隔离层。位线结构与有源区的第一接触区电连接，隔离层内形成有接触孔，接触孔中填充有导线，导线用于电连接电容器与有源区的第二接触区。
为了增大导线与第二接触区的接触面积，接触孔通常延伸至基底中，以增加第二接触区暴露在接触孔内的表面积。然而，在制作动态随机存储器的过程中，填充在接触孔内的导线易出现孔洞或者缝隙，影响存储器的良品率。
发明内容
第一方面，本申请实施例提供一种半导体存储器的制作方法，其包括：提供基底，所述基底内设有多个间隔设置的有源区，所述有源区包括第一 接触区和位于所述第一接触区外的第二接触区，所述第二接触区暴露于所述基底的表面；在每个所述第二接触区上形成凸起；在所述基底上形成多条间隔设置的位线结构，每条所述位线结构至少电连接一个所述第一接触区；形成覆盖所述位线结构和所述基底的第一隔离层，所述第一隔离层内设有多个填充孔，每个所述填充孔暴露一个所述凸起，且所述凸起暴露在所述填充孔内的表面积大于所述填充孔在所述基底上的正投影与所述第二接触区的重合面积；在所述填充孔内形成导线，所述导线电连接所述凸起。
第二方面，本申请实施例的提供一种半导体存储器，其包括：基底，所述基底内设有多个间隔设置的有源区，所述有源区包括第一接触区和位于所述第一接触区外的第二接触区；设置在所述基底上的多条间隔设置的位线结构，每条所述位线结构至少电连接一个所述第一接触区；设置在所述第二接触区上的凸起；覆盖所述位线结构、所述凸起和所述基底的第一隔离层，所述第一隔离层设有多个填充孔，多个所述填充孔延伸至所述凸起；设置在所述填充孔内的导线，所述导线与所述凸起电连接，且所述导线与所述凸起的接触面积大于所述填充孔在所述基底上的正投影与所述第二接触区的重合面积。
附图说明
图1为相关技术中的半导体存储器的结构示意图；
图2为本申请实施例中的半导体存储器的制作方法的流程图；
图3为本申请实施例中的基底的俯视图；
图4为本申请实施例中的字线结构的俯视图；
图5为本申请实施例中的基底的结构示意图；
图6为本申请实施例中的形成凸起后的俯视图；
图7为本申请实施例中的形成凸起后的结构示意图；
图8为本申请实施例中的形成位线结构后的结构示意图；
图9为本申请实施例中的形成第一隔离层后的结构示意图；
图10为本申请实施例中的形成填充孔后的结构示意图；
图11为本申请实施例中的形成第三导电层后的结构示意图；
图12为本申请实施例中的形成导线后的结构示意图；
图13为本申请实施例中的形成第五导电层后的结构示意图；
图14为本申请实施例中的形成接触垫后的结构示意图；
图15为本申请实施例中的形成位线结构的流程图；
图16为本申请实施例中的形成第一导电层后的结构示意图；
图17为本申请实施例中的形成位线接触窗后的结构示意图；
图18为本申请实施例中的形成位线接触后的结构示意图；
图19为本申请实施例中的形成位线接触后的俯视图。
具体实施方式
相关技术中，参照图1，在制作半导体存储器的过程中，第一隔离层500中形成填充孔510后，沿填充孔510刻蚀基底，使得填充孔510的孔底位于基底内；再在填充孔510内形成导线530。在填充孔510内沉积形成导线530时，填充孔510的深度较大，导线530内易形成孔洞或者缝隙，如图1中点划线圆形所示区域，孔洞或者缝隙的存在会影响导线530传送电荷的能力，导致半导体存储器的性能降低，甚至影响半导体存储器的良品率。
鉴于此，本申请实施例提供一种半导体存储器的制作方法，通过在基底与填充孔对应的区域(第二接触区)上形成凸起；再形成覆盖基底和凸起的第一隔离层，第一隔离层具有填充孔，填充孔暴露凸起，且凸起暴露在填充孔内的表面积大于填充孔在基底上的正投影与第二接触区的重合面积；再在填充孔内形成导线。导线与凸起的接触面积大于未设置凸起时导线与第二接触区的重合面积，减少了导线与凸起之间的接触电阻。此外，填充孔内形成有位于基底上的凸起，使得填充孔的深度相较于相关技术有所减小，从而使得设置在填充孔内的导线的孔洞或者缝隙较少，提高了导线的形成质量，进而提高了存储器的良品率。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
参照图2，本申请实施例提供一种半导体存储器的制作方法，具有包括以下步骤：
步骤S101、提供基底，基底内设有多个间隔设置的有源区，有源区包括第一接触区和位于第一接触区外的第二接触区，第二接触区暴露于基底的表面。
参照图3，基底100用于支撑其上的各膜层，基底100内设有源区110，有源区110的数量可以设置有多个，如图3所示，多个有源区110呈阵列排布，可以理解的是，多个有源区110中的中心区域呈点阵排布。
多个有源区110间隔设置，例如，各有源区110之间设置浅沟槽隔离(Shallow Trench Isolation，简称STI)结构120，通过浅沟槽隔离结构120将多个有源区110之间隔开。基底100可以为半导体基底，例如，硅基底、锗基底、碳化硅(SiC)基底、锗化硅(SiGe)基底或者绝缘体上硅(Silicon on Insulator，简称SOI)基底。
通过图案化制作工艺在基底100内形成沟槽，并在沟槽内填充绝缘材料(例如氧化硅或者氮氧化硅)，从而在基底100上定义出多个由浅沟槽隔离结构120分离的有源区110。示例性的，图案化制作工艺可以为自对准双图形(Self-Aligned Double Patterning，简称SADP)工艺或者自对准四重图形(Self-Aligned Quadruple Patterning，简称SAQP)工艺。
继续参照图3，有源区110倾斜设置，沿图3中所示D方向延伸，有源区110包括第一接触区111和第二接触区112，第二接触区112位于第一接触区111外，第一接触区111和第二接触区112暴露于基底100的表面，第一接触区111用于电连接位线结构，第二接触区112用于电连接电容器。示例性的，如图3所示，第一接触区111位于有源区110的中间区域，第二接触区112位于有源区110的边缘区域，即第一接触区111的两侧可以各设置有一个第二接触区112。
需要说明的是，参照图4和图5，图5所示的截面为图4中垂直于X方向的平面，基底100内还设有字线结构130，字线结构130通常为埋入式字线(Buried Word Line，简称BWL)结构130，埋入式字线结构130可以设置有多条，多条埋入式字线结构130沿第二方向延伸，且横跨有源区110，从而将有源区110的第一接触区111和第二接触区112隔开。
如图4所示，多条埋入式字线结构130如图4中点划线所围合的区域 所示，其沿X方向延伸，每条埋入式字线结构130穿过位于同一行多个有源区110，且每个有源区110对应两条埋入式字线结构130。图4中虚线所示区域为一个有源区110，两条埋入式字线结构130将有源区110分成位于中心的一个第一接触区111和位于两侧的两个第二接触区112。
如图4和图5所示，埋入式字线结构130包括第二绝缘层131、第四导电层132和盖层133，其中，第二绝缘层131与有源区110接触，第二绝缘层131围合成填充槽，填充槽内设置有第四导电层132和位于第四导电层132上的盖层133，盖层133的上表面与基底100的上表面齐平，如图4所示的俯视图中，盖层133的上表面与第二绝缘层131的上表面显露，且盖层133位于第二绝缘层131的中间。第二绝缘层131的材质包括氧化硅，第四导电层132的材质包括钛、钽、氮化钛、氮化钨、氮化钽、钨氮硅化合物中的一种或者多种，盖层133的材质包括氮化硅。
步骤S102、在每个第二接触区上形成凸起。
参照图6，凸起200设置有多个，多个凸起200与多个第二接触区112一一对应，即每个第二接触区112上形成一个凸起200。凸起200在基底100上的正投影至少覆盖第二接触区112，即第二接触区112位于凸起200在基底100的正投影之内，如图6所示的俯视图中，第二接触区112为虚线，即第二接触区112位于凸起200的下方，第二接触区112未暴露。
示例性的，凸起200在基底100上的正投影与第二接触区112的形状相同，例如均为平行四边形。如图7所示，凸起200在基底100上的正投影的边缘与第二接触区112的边缘之间的距离L为3-5nm。
在一些可能的示例中，参照图7，图7所示平面为垂直于字线结构130延伸方向(图6中的X方向)的截面，凸起200背离基底100的表面为曲面，以保证凸起200背离基底100的表面的表面积大于第二接触区112暴露于基底100的表面积，以使后续形成的导线530与凸起200之间具有较大的接触面积，从而减少导线530与凸起200之间的接触电阻。如图7所示，凸起200背离基底100的表面为弧形，示例性的，凸起200的截面形状为弓形、半圆形或者半椭圆形。
凸起200可以通过在第二接触区112上外延生长(Epitaxial Growth)形成，即每个第二接触区112上外延生长形成一个凸起200。通过外延生长可以使得凸起200在导电类型、电阻率、掺杂离子的种类和浓度等方面 与第二接触区112不同。示例性的，凸起200与有源区110的材质可以相同，例如均为硅，凸起200和有源区110中掺杂有预设离子，凸起200中的预设离子和有源区110的预设离子可以为同一类型，例如，预设离子为N型离子或者P型离子中的一种。凸起200的掺杂浓度大于有源区110的掺杂浓度，使得导线530与凸起200电接触相较于导线530与有源区110的第二接触区112电接触的接触电阻减小。
需要说明的是，如图6和图7所示，第一接触区111和第二接触区112均暴露于基底100的表面时，在每个第二接触区112上形成凸起200的同时，还在每个第一接触区111上形成凸起200，即同时在第一接触区111和第二接触区112上形成凸起200，以降低凸起200形成的难度，易于半导体存储器的制作。如图6所示，形成凸起200后，凸起200呈点阵式分布。
步骤S103、在基底上形成多条间隔设置的位线结构，每条位线结构至少电连接一个第一接触区。
参照图8，在基底100上形成多条间隔设置的位线(Bit Line，简称BL)结构，多条位线结构400相平行，且沿第一方向延伸，每条位线至少电连接一个第一接触区111。如图8所示，位线结构400沿垂直于纸面的方向(图6所示Y方向)延伸，每个位线结构400与位于同一列的多个有源区110的第一接触区111(如图6点划线所示)相接触，且每个有源区110的第一接触区111对应一条位线结构400。通过位线结构400与第一接触区111相接触，将位线结构400与第一接触区111电连接。
可以理解的是，第一方向与第二方向可以相垂直，例如，如图6所示的俯视图中，第一方向为竖直方向(Y方向)，第二方向为水平方向(X方向)，有源区110倾斜设置。参照图6至图8，字线结构130位于基底100内，沿第二方向穿过有源区110；位线结构400位于基底100上，沿第一方向接触有源区110。位线结构400与基底100的其他区域之间设置有第一绝缘层300，以保证位线结构400仅与第一接触区111电连接。
位线结构400可以通过沉积工艺形成，例如，位线结构400通过化学气相沉积(Chemical Vapor Deposition，简称CVD)、物理气相沉积(Physical Vapor Deposition，简称PVD)或者原子层沉积(Atomic Layer Deposition，简称ALD)工艺形成。
步骤S104、形成覆盖位线结构和基底的第一隔离层，第一隔离层内设有多个填充孔，每个填充孔暴露一个凸起，且凸起暴露在填充孔内的表面积大于填充孔在基底上的正投影与第二接触区的重合面积。
参照图9，第一隔离层500设置在基底100上且覆盖位线结构400，对位线结构400进行支撑和隔离，并作为填充孔510的基体。第一隔离层500的材质可以为绝缘材料，例如氮化硅等。
参照图10，第一隔离层500内形成多个填充孔510，多个填充孔510间隔设置，且每个填充孔510暴露一个凸起200，即多个填充孔510与多个凸起200之间一一对应。凸起200暴露在填充孔510内的表面积大于填充孔510在基底100上的正投影与第二接触区112的重合面积，以使后续形成的导线530与凸起200之间具有较大的接触面积，改善导线530与凸起200之间的电性能。
在一些可能的示例中，形成覆盖位线结构400和基底100的第一隔离层500，第一隔离层500内设有多个填充孔510，每个填充孔510暴露一个凸起200，且凸起200暴露在填充孔510内的表面积大于填充孔510在基底100上的正投影与第二接触区112的重合面积的步骤包括：
在位线结构400上沉积第一隔离层500，第一隔离层500覆盖位线结构400和第一绝缘层300。第一隔离层500覆盖位线结构400，且第一隔离层500背离基底100的表面齐平。
在位线结构400上沉积第一隔离层500之后，刻蚀第一隔离层500，以形成填充孔510，填充孔510贯穿第一隔离层500且与凸起200相对。
形成填充孔510后，沿填充孔510刻蚀第一绝缘层300，填充孔510贯穿第一绝缘层300，以使填充孔510暴露凸起200。以凸起200为刻蚀停止层，沿填充孔510刻蚀第一绝缘层300，填充孔510的孔底为凸起200的表面，例如，填充孔510内暴露凸起200的部分曲面，凸起200暴露的表面积大于填充孔510的截面积。
步骤S105、在填充孔内形成导线，导线电连接凸起。
参照图11至图12，导线530填充满填充孔510，且与凸起200相接触，导线530与凸起200均为导电材质，通过接触实现两者的电连接。在一些可能的示例中，在填充孔510内形成导线530，导线530电连接凸起200的步骤包括：
在填充孔510内和第一隔离层500上沉积第三导电层520，第三导电层520填充满填充孔510，且覆盖第一隔离层500。如图11所示，第三导电层520覆盖第一隔离层500和基底100，且第三导电层520的顶面高于第一隔离层500的顶面，其中，高度方向是指背离基底100的方向。第三导电层520的材质可以为多晶硅。
沉积第三导电层520之后，刻蚀第三导电层520，去除位于第一隔离层500上的第三导电层520以及位于填充孔510内的部分第三导电层520，保留的第三导电层520形成导线530。如图12所示，通过沉积第三导电层520，并对第三导电层520进行回刻，去除部分第三导电层520后，保留的第三导电层520形成多个间隔设置的导线530，导线530的顶面低于第一隔离层500的表面。
需要说明的是，参照图13和图14，在填充孔510内形成导线530，导线530电连接凸起200之后，半导体存储器的制作方法还包括：在每个填充孔510内的导线530上形成接触垫610，多个接触垫610间隔设置，且每个接触垫610部分位于填充孔510内，部分位于第一隔离层500上。
如图13所示，在剩余的填充孔510内和第一隔离层500上形成第五导电层600，第五导电层600填充满剩余的填充孔510，且覆盖第一隔离层500。第五导电层600包括依次层叠设置的硅化钴层、氮化钛层和钨层。再刻蚀位于第一隔离层500上的第五导电层600，以形成多个间隔设置的接触垫610。如图14所示，接触垫610的下部位于填充孔510内，接触垫610的上部位于第一隔离层500上，各个接触垫610之间具有间隔，以使各接触垫610之间电气隔离。
本申请实施例中的存储器的制作方法中，先提供基底100，基底100内设有多个间隔设置的有源区110，有源区110包括第一接触区111和位于第一接触区111外的第二接触区112，第二接触区112暴露于基底100的表面；在每个第二接触区112上形成凸起200；在基底100上形成多条间隔设置的位线结构400，每条位线结构400至少电连接一个第一接触区111；形成覆盖位线结构400和基底100的第一隔离层500，第一隔离层500内设有多个填充孔510，每个填充孔510暴露一个凸起200，且凸起200暴露在填充孔510内的表面积大于填充孔510在基底100上的正投影与第二接触区112的重合面积；在填充孔510内形成导线530，导线530电连 接凸起200。通过在第二接触区112上形成凸起200，且凸起200暴露在填充孔510内的表面积大于填充孔510在基底100上的正投影与第二接触区112的重合面积，使得形成在填充孔510内的导线530与凸起200的接触面积较大，减少了导线530与凸起200之间的接触电阻。此外，填充孔510内形成有位于基底100上的凸起200，使得填充孔510的深度相较于相关技术有所减小，从而使得在填充孔510内形成导线530时，导线530内的孔洞或者缝隙较少，提高了导线530的形成质量，进而提高了存储器的良品率。
需要说明的是，参照图15，在基底100上形成多条间隔设置的位线结构400，每条位线结构400至少连接一个第一接触区111的步骤包括：
步骤S1031、在基底上形成堆叠的第一绝缘层、第二隔离层和第一导电层，第一绝缘层覆盖凸起。
参照图16，在基底100上沉积第一绝缘层300，第一绝缘层300覆盖凸起200；再在第一绝缘层300上沉积第二隔离层410；之后在第二隔离层410上沉积第一导电层420。第一绝缘层300、第二隔离层410和第一导电层420堆叠设置，第一绝缘层300的材质包括氧化硅，第二隔离层410的材质包括氮化硅，第一导电的材质包括多晶硅。
步骤S1032、在第一导电层、第二隔离层和第一绝缘层内形成位线接触窗，位线接触窗贯穿第一导电层、第二隔离层和第一绝缘层且延伸至基底，位线接触窗暴露第一接触区。
参照图17，位线接触窗430的底部位于基底100中，并暴露第一接触区111。保留的第一导电层420、第二隔离层410和第一绝缘层300形成多个圆柱形凸台，多个圆柱形凸台间隔设置，位线接触窗430环绕各圆柱形凸台。
步骤S1033、在位线接触窗内形成位线接触，并去除第二隔离层上的第一导电层和位线接触，保留的位线接触与第二隔离层齐平。
参照图18和图19，位线接触440(Bit Line Contact，简称BLC)填充于位线接触窗430内，位线接触440的材质可以为多晶硅。去除第二隔离层410上的第一导电层420和部分位线接触440后，保留的位线接触440的顶面与第二隔离层410的顶面齐平，以便于在其上形成较为平整的其他膜层。
步骤S1034、在位线接触和第二隔离层上形成堆叠的第二导电层和第三隔离层，第二导电层覆盖位线接触和第二隔离层。
在保留的位线接触440和第二隔离层410上沉积第二导电层450，第二导电层450覆盖位线接触440和第二隔离层410；再在第二导电层450上沉积第三隔离层460，第三隔离层460的材质可以包括氮化硅。
在一些可能的示例中，第二导电层450包括钛层、金属化合物层和钨层，钛层、金属化合物层和钨层依次堆叠设置，且钛层与位线接触440相接触。金属化合物层的材质可以为钴硅化合物，例如，在位线接触440上沉积金属钴，并在高温条件下使金属钴与位线接触440中的硅发生结合，生成钴硅化合物，以改善第二导电层450的电性能。
步骤S1035、刻蚀第三隔离层、第二导电层、第二隔离层和位线接触，形成沿第一方向延伸的位线结构，且位线结构穿过位于第一方向上的多个第一接触区。
刻蚀第三隔离层460、第二导电层450、第二隔离层410和位线接触440，以形成图8所示的位线结构400，位线结构400沿第一方向延伸，位线结构400通过位线接触440与位于同一行或者同一列的多个有源区110相接触。一条位线结构400中，部分区域与第一接触区111相接触，另一部分区域与第一绝缘层300相接触，即沿位线结构400的延伸方向，第一接触区111和第一绝缘层300交替与位线结构400接触。
参照图1至图14，本申请实施例提供一种半导体存储器，该半导体存储器包括基底100，基底100用于支撑其上的各膜层，基底100内设有有源区110，有源区110的数量可以设置有多个，多个有源区110间隔设置，例如，各有源区110之间设置浅槽隔离结构，通过浅槽隔离结构120将多个有源区110之间隔开。
有源区110包括第一接触区111和第二接触区112，第二接触区112位于第一接触区111外，且第一接触区111和第二接触区112暴露于基底100的表面，第一接触区111用于电连接位线结构400，第二接触区112用于电连接电容器。示例性的，第一接触区111位于有源区110的中间区域，第二接触区112位于有源区110的边缘区域，即第一接触区111的两侧可以各设置有一个第二接触区112。
基底100内还设有字线结构130，字线结构130通常为埋入式字线结 构130结构，埋入式字线结构130可以设置有多条，多条埋入式字线结构130沿第二方向(图6所示X方向)延伸，且横跨有源区110，从而将有源区110的第一接触区111和第二接触区112隔开。
基底100的第二接触区112上设置有凸起200，凸起200设置有多个，多个凸起200与多个第二接触区112一一对应，即每个第二接触区112上形成一个凸起200。凸起200在基底100上的正投影至少覆盖第二接触区112，即第二接触区112位于凸起200在基底100的正投影之内。
示例性的，以平行于第一方向(图6所示Y方向)的平面为截面，凸起200的截面形状为弓形。第一方向为设置在基底100上的位线结构400的延伸方向。凸起200在基底100上的正投影与第二接触区112的形状相同，例如均为平行四边形，凸起200在基底100上的正投影的边缘与第二接触区112的边缘之间的距离L为3-5nm。
在一些可能的示例中，凸起200背离基底100的表面为曲面，以保证凸起200背离基底100的表面的表面积大于第二接触区112暴露于基底100的表面积，以使后续形成的导线530与凸起200之间具有较大的接触面积，减少导线530与凸起200之间的接触电阻。
基底100上设有多条间隔设置的位线结构400，多条位线结构400相平行，且沿第一方向延伸，每条位线至少电连接一个第一接触区111。通过位线结构400与第一接触区111相接触，从而将位线结构400与第一接触区111电连接。
位线结构400包括第三隔离层460、第二导电层450、第二隔离层410和位线接触440，位线接触440与第二隔离层410交替设置。位线接触440与第一接触区111相接触，第二隔离层410与第一绝缘层300相接触。位线接触440的顶面与第二隔离层410的顶面齐平，第二导电层450设置在位线接触440和第二隔离层410上，第三隔离层460设置在第二导电层450上。
在一些可能的示例中，第二导电层450包括钛层、金属化合物层和钨层，钛层、金属化合物层和钨层依次堆叠设置，且钛层与位线接触440相接触。金属化合物层的材质可以为金属硅化物。
第一隔离层500设置在基底100上且覆盖位线结构400，对位线结构400进行支撑和隔离，并作为填充孔510的基体。第一隔离层500的材质 可以为绝缘材料，例如氮化硅等。第一隔离层500内形成多个填充孔510，多个填充孔510间隔设置，且每个填充孔510暴露一个凸起200，即多个填充孔510与多个凸起200之间一一对应。
导线530填充于填充孔510，导线530的顶面低于第一隔离层500的顶面。导线530与凸起200相接触，导线530与凸起200均为导电材质，通过导线530与凸起200相接触实现两者的电连接。导线530与凸起200的接触面积大于填充孔510在基底100上的正投影与第二接触区112的重合面积，从而使得导线530与凸起200之间具有较大的接触面积，改善导线530与凸起200之间的电性能。
每个导线530上设置有与其相对应的一个接触垫610，多个接触垫610间隔设置，以使各接触垫610之间电气隔离。接触垫610的下部位于填充孔510内，且与导线530相接触，接触垫610的上部位于第一隔离层500上，接触垫610上可以设置电容器，电容器通过接触垫610和导线530与第二接触区112电连接。
本申请实施例中的存储器包括：基底100、位线结构400、第一隔离层500和导线530；其中，基底100内设有多个间隔设置的有源区110，有源区110包括第一接触区111和第二接触区112，第二接触区112位于第一接触区111外，且第二接触区112上设有凸起200；位线结构400设置在基底100上，间隔设置的多条位线结构400中的每条位线结构400至少电连接一个第一接触区111；第一隔离层500设置在基底100上，且覆盖位线结构400、凸起200和基底100，第一隔离层500内设有多个填充孔510，填充孔510内暴露凸起200；导线530设置在填充孔510内，且与凸起200电连接，导线530与凸起200的接触面积大于填充孔510在基底100上的正投影与第二接触区112的重合面积，使得导线530与凸起200的接触面积大于未设置凸起200时导线530与第二接触区112的重合面积，减少了导线530与凸起200之间的接触电阻。此外，填充孔510内形成有位于基底100上的凸起200，使得填充孔510的深度相较于相关技术有所减小，从而使得设置在填充孔510内的导线530的孔洞或者缝隙较少，提高了导线530的形成质量，进而提高了存储器的良品率。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相 互参见即可。
在本说明书的描述中，参考术“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (16)

  1. 一种半导体存储器的制作方法，包括：
    提供基底，所述基底内设有多个间隔设置的有源区，所述有源区包括第一接触区和位于所述第一接触区外的第二接触区，所述第二接触区暴露于所述基底的表面；
    在每个所述第二接触区上形成凸起；
    在所述基底上形成多条间隔设置的位线结构，每条所述位线结构至少电连接一个所述第一接触区；
    形成覆盖所述位线结构和所述基底的第一隔离层，所述第一隔离层内设有多个填充孔，每个所述填充孔暴露一个所述凸起，且所述凸起暴露在所述填充孔内的表面积大于所述填充孔在所述基底上的正投影与所述第二接触区的重合面积；
    在所述填充孔内形成导线，所述导线电连接所述凸起。
  2. 根据权利要求1所述的半导体存储器的制作方法，其中，所述位线结构沿第一方向延伸；
    以平行于所述第一方向的平面为截面，所述凸起的截面形状为弓形。
  3. 根据权利要求1所述的半导体存储器的制作方法，其中，所述凸起在所述基底上的正投影至少覆盖所述第二接触区。
  4. 根据权利要求3所述的半导体存储器的制作方法，其中，所述凸起在所述基底上的正投影的边缘与所述第二接触区的边缘之间的距离为3-5nm。
  5. 根据权利要求1所述的半导体存储器的制作方法，其中，在每个所述第二接触区上形成凸起的步骤包括：
    在每个所述第二接触区上外延生长，形成所述凸起。
  6. 根据权利要求5所述的半导体存储器的制作方法，其中，所述凸起的材质与所述有源区的材质相同，所述凸起和所述有源区中掺杂有预设离子，且所述凸起的掺杂浓度大于所述有源区的掺杂浓度。
  7. 根据权利要求1所述的半导体存储器的制作方法，其中，所述第一接触区暴露于所述基底的表面；
    在每个所述第二接触区上形成凸起的同时，还在每个所述第一接触区 上形成凸起。
  8. 根据权利要求7所述的半导体存储器的制作方法，其中，所述基底内还形成有沿第二方向延伸的字线结构，所述字线结构将每个所述有源区的所述第一接触区和所述第二接触区隔开，所述第一接触区和所述第二接触区呈点阵式排布。
  9. 根据权利要求1所述的半导体存储器的制作方法，其中，在所述基底上形成多条间隔设置的位线结构，每条所述位线结构至少连接一个所述第一接触区的步骤包括：
    在所述基底上形成堆叠的第一绝缘层、第二隔离层和第一导电层，所述第一绝缘层覆盖所述凸起；
    在所述第一导电层、所述第二隔离层和所述第一绝缘层内形成位线接触窗，所述位线接触窗贯穿所述第一导电层、所述第二隔离层和所述第一绝缘层且延伸至所述基底，所述位线接触窗暴露所述第一接触区；
    在所述位线接触窗内形成位线接触，并去除所述第二隔离层上的所述第一导电层和所述位线接触，保留的所述位线接触与所述第二隔离层齐平；
    在所述位线接触和所述第二隔离层上形成堆叠的第二导电层和第三隔离层，所述第二导电层覆盖所述位线接触和所述第二隔离层；
    刻蚀所述第三隔离层、所述第二导电层、所述第二隔离层和所述位线接触，形成沿第一方向延伸的位线结构，且所述位线结构穿过位于所述第一方向上的多个所述第一接触区。
  10. 根据权利要求9所述的半导体存储器的制作方法，其中，所述第二导电层包括形成在所述位线接触上的钛层、形成在所述钛层上的金属化合物层，以及形成在所述金属化合物层上的钨层。
  11. 根据权利要求9所述的半导体存储器的制作方法，其中，形成覆盖所述位线结构和所述基底的第一隔离层，所述第一隔离层内设有多个填充孔，每个所述填充孔暴露一个所述凸起，且所述凸起暴露在所述填充孔内的表面积大于所述填充孔在所述基底上的正投影与所述第二接触区的重合面积的步骤包括：
    在所述位线结构上沉积所述第一隔离层，所述第一隔离层覆盖所述位线结构和所述第一绝缘层；
    刻蚀所述第一隔离层，以形成所述填充孔，所述填充孔贯穿所述第一 隔离层且与所述凸起相对；
    沿所述填充孔刻蚀所述第一绝缘层，所述填充孔贯穿所述第一绝缘层，以使所述填充孔暴露所述凸起。
  12. 根据权利要求1所述的半导体存储器的制作方法，其中，在所述填充孔内形成导线，所述导线电连接所述凸起的步骤包括：
    在所述填充孔内和所述第一隔离层上沉积第三导电层，所述第三导电层填充满所述填充孔，且覆盖所述第一隔离层；
    刻蚀所述第三导电层，去除位于所述第一隔离层上的所述第三导电层以及位于所述填充孔内的部分所述第三导电层，保留的所述第三导电层形成所述导线。
  13. 根据权利要求12所述的半导体存储器的制作方法，其中，在所述填充孔内形成导线，所述导线电连接所述凸起的步骤之后，所述存储器的制作方法还包括：
    在每个所述填充孔内的所述导线上形成接触垫，多个所述接触垫间隔设置，且每个所述接触垫部分位于所述填充孔内，部分位于所述第一隔离层上。
  14. 一种半导体存储器，其中，包括：
    基底，所述基底内设有多个间隔设置的有源区，所述有源区包括第一接触区和位于所述第一接触区外的第二接触区；
    设置在所述基底上的多条间隔设置的位线结构，每条所述位线结构至少电连接一个所述第一接触区；
    设置在所述第二接触区上的凸起；
    覆盖所述位线结构、所述凸起和所述基底的第一隔离层，所述第一隔离层设有多个填充孔，多个所述填充孔延伸至所述凸起；
    设置在所述填充孔内的导线，所述导线与所述凸起电连接，且所述导线与所述凸起的接触面积大于所述填充孔在所述基底上的正投影与所述第二接触区的重合面积。
  15. 根据权利要求14所述的半导体存储器，其中，所述位线结构沿第一方向延伸；
    以平行于所述第一方向的平面为截面，所述凸起的截面形状为弓形。
  16. 根据权利要求14所述的半导体存储器，其中，所述凸起在所述基 底上的正投影至少覆盖所述第二接触区。
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