WO2023272439A1 - 芯片和芯片测试装置 - Google Patents

芯片和芯片测试装置 Download PDF

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Publication number
WO2023272439A1
WO2023272439A1 PCT/CN2021/102774 CN2021102774W WO2023272439A1 WO 2023272439 A1 WO2023272439 A1 WO 2023272439A1 CN 2021102774 W CN2021102774 W CN 2021102774W WO 2023272439 A1 WO2023272439 A1 WO 2023272439A1
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Prior art keywords
circuit
test
chip
signal
multiplexer
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PCT/CN2021/102774
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English (en)
French (fr)
Inventor
付海涛
王韧
杨昊
黄俊林
王国玺
Original Assignee
华为技术有限公司
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Priority to CN202180098096.8A priority Critical patent/CN117396764A/zh
Priority to PCT/CN2021/102774 priority patent/WO2023272439A1/zh
Publication of WO2023272439A1 publication Critical patent/WO2023272439A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3173—Marginal testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning

Definitions

  • the embodiments of the present application relate to the field of circuit technology, and in particular to a chip and a chip testing device.
  • SOC system-on-chip
  • IO input and output
  • InOut The port communicates signals with external chips or circuits.
  • each logic unit circuit integrated in the chip needs to be tested before the chip leaves the factory, so as to detect the performance of each logic unit circuit.
  • the performance of each logic unit circuit inside the chip since the fewer IO ports of the chip cannot satisfy the parallel testing of multiple logic units, in the current technology for testing logic units, it is usually necessary to form a serial scan test chain pair inside the chip. Multiple logic units are tested. However, since more and more logic units are integrated in the chip, the serial scan test chain becomes longer and longer, which leads to low efficiency of testing the logic unit circuit. Therefore, how to improve the efficiency of testing each logic unit in the chip becomes a problem to be solved.
  • the chip and the chip testing device provided by the application can improve the testing efficiency of testing each logic unit in the chip.
  • the embodiment of the present application provides a chip, the chip includes: an input port, an output port, a serial deserializer and a scan test chain; the serial deserializer includes a receiving circuit and a transmitting circuit, so The receiving circuit is connected to the input port and the input end of the scan test chain, and the transmitting circuit is connected to the output port and the output end of the scan test chain; the receiving circuit includes a boundary scan circuit and a first A multiplexer, the first input of the first multiplexer is connected to the input port, and the second input of the first multiplexer is connected to the input port through the boundary scan circuit ; The first multiplexer is used to transmit the first test signal to the scan test chain through the first input terminal of the first multiplexer, the first test signal is the input port Received from test equipment.
  • the path of inputting the test signal to the scan test chain usually needs to go through the boundary scan circuit, since the hysteresis comparator and other devices are set in the boundary scan circuit, the transmission bandwidth of the test signal is reduced after the test signal passes through the hysteresis comparator and other devices. For example, the signal transmission bandwidth is limited between 25Mhz and 100Mhz.
  • the transmitted test signal is input into the serial scan test chain, which greatly reduces the transmission rate of the test signal.
  • the test signal can be provided to the scan test chain without passing through devices that limit the signal transmission rate such as hysteresis comparators, which can greatly increase the transmission rate of the test signal, thereby improving the test of each logic unit. test efficiency.
  • the receiving circuit further includes a buffer circuit, and the first input end of the first multiplexer is connected to the input port through the buffer circuit.
  • the buffer circuit is arranged between the input port and the first multiplexer, which can reduce the test signal transmission time delay, thereby further increasing the signal transmission rate.
  • the buffer circuit includes one of a high-pass filter and a capacitor circuit, and the capacitor circuit includes multiple capacitors connected in parallel.
  • the receiving circuit further includes an impedance matching circuit; the input port is connected to the boundary scan circuit and the buffer circuit through the impedance matching circuit.
  • the energy loss in the signal transmission process can be reduced, so that the signal input at the input port can be effectively transmitted to the subsequent stage circuit, so that the transmission performance of the test signal can be further improved.
  • the impedance matching circuit includes a first resistor and a second resistor.
  • the first resistor is connected in series between the input port and the buffer circuit; one end of the second resistor is connected to the input end of the buffer circuit, and the other end of the second resistor is connected to the common ground.
  • the scan test chain is obtained by cascading a plurality of logic units in the chip; the receiving circuit further includes: a deserialization circuit, configured to serialize the first The data signal is converted into multiple parallel first data signals and transmitted to the plurality of logic units, and the serial first data signal is received by the input port from the first chip.
  • the transmitting circuit includes a parallel-to-serial conversion circuit, a second multiplexer, and a driving circuit; both the parallel-serial conversion circuit and the second multiplexer are connected to the driving circuit connection; the parallel-serial conversion circuit is used to receive multiple parallel second data signals from the plurality of logic units, and convert the multiple parallel second data signals into serial second data signals; The second multiplexer is used to receive a second test signal from the scan test chain and output the second test signal, and the second test signal is the response of the scan test chain to the first test signal Obtained after performing shift scanning; the drive circuit is configured to selectively output the serial second data signal or the second test signal through the output port.
  • the data signal output by the parallel-to-serial conversion circuit can be directly provided to the driving circuit, which can improve the signal transmission performance of the transmitting circuit.
  • the chip further includes a control circuit; the second multiplexer is further configured to: receive a parameter configuration signal from the control circuit, and provide the parameter configuration signal to the driver circuit, the parameter configuration signal is used to configure at least one of the signal output power, signal amplitude and signal polarity of the driving circuit; the driving circuit is also used to: adjust the driving circuit based on the parameter configuration signal parameters of the circuit.
  • the chip includes multiple scan test chains; the chip further includes: a splitter, arranged between the transmitting circuit and the multiple scan test chains, for The first test signal is divided into multiple first test signals, which are respectively provided to the multiple scan test chains; the combiner is arranged between the multiple scan test chains and the receiving circuit, and is used to combine the multiple scan test chains and the receiving circuit.
  • the multiple second test signals output by the plurality of scan test chains are synthesized into one second test signal and provided to the receiving circuit.
  • a test signal input by the input port can be It is converted into multiple parallel test signals, and the scan test is performed on multiple scan test chains at the same time. After the scan test of multiple scan test chains is completed, it is combined into a serial signal through the combiner and output from the output port, so that each scan can be reduced. The number of logical units scanned for testing by the test chain.
  • a splitter to convert high-frequency signals into multiple low-frequency signals, the difficulty of implementing the scan test chain can also be reduced.
  • the chip further includes: a boundary scan test chain, the boundary scan test chain includes a plurality of boundary scan units, the plurality of boundary scan units are connected to the output end of the receiving circuit and the The input terminal of the transmitting circuit is connected; each boundary scanning unit in the plurality of boundary scan units is used for receiving a third test signal from the receiving circuit, and outputting a fourth test signal to the transmitting circuit.
  • the embodiment of the present application provides a chip testing device, the chip testing device includes testing equipment and the chip according to the first aspect; the input port and the output port of the chip are both connected to the testing equipment.
  • FIG. 1 is a schematic structural diagram of a chip 100 provided in an embodiment of the present application.
  • FIG. 2A is a schematic diagram of an application scenario of the chip 100 provided by the embodiment of the present application.
  • FIG. 2B is a schematic structural diagram of the connection between the chip 100 and the testing equipment provided by the embodiment of the present application;
  • FIG. 2C is a schematic structural diagram of the scan test chain provided by the embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of the receiving circuit RX in the SerDes provided by the embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a boundary scan circuit in a receiving circuit RX provided by an embodiment of the present application;
  • FIG. 5 is another structural schematic diagram of the receiving circuit RX in the SerDes provided by the embodiment of the present application.
  • FIG. 6 is another structural schematic diagram of the receiving circuit RX in the SerDes provided by the embodiment of the present application.
  • FIG. 8 is another structural schematic diagram of the transmitting circuit TX in the SerDes provided by the embodiment of the present application.
  • FIG. 9 is another schematic structural diagram of the chip 100 provided by the embodiment of the present application.
  • FIG. 10 is another schematic structural diagram of the chip 100 provided by the embodiment of the present application.
  • FIG. 11 is another schematic structural diagram of the chip 100 provided by the embodiment of the present application.
  • words such as “exemplary” or “for example” are used as examples, illustrations or illustrations. Any embodiment or design scheme described as “exemplary” or “for example” in the embodiments of the present application shall not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Rather, the use of words such as “exemplary” or “such as” is intended to present related concepts in a concrete manner.
  • “plurality” means two or more. For example, a plurality of logical units refers to two or more logical units.
  • FIG. 1 is a schematic structural diagram of a chip 100 provided by an embodiment of the present application.
  • chip 100 comprises serializer and deserializer (SerDes, Serializer and DeSerializar) 1 and logic circuit Lo, and this logic circuit Lo comprises logic unit 01, logic unit 02, logic unit On, logic unit m1, logic unit Multiple logic units such as m2, logic unit mn, m and n are integers greater than or equal to 2, and n is less than m. These multiple logic units are used to implement various logic functions of the chip 100.
  • the logic functions may include but are not limited to: Computing and storage etc.
  • the plurality of logic units may include, but not limited to, arithmetic units (such as adders, multipliers, etc.), registers, and so on.
  • SerDes1 can also be regarded as a logic unit disposed outside the logic circuit Lo in the chip 100 .
  • the chip 100 also includes an input port In and an output port Out, and the input port In and the output port Out are a pair of IO ports connected to SerDes1.
  • the input port In is used to input signals to SerDes1, and the output port Out is used to output signals from SerDes1.
  • SerDes1 includes a receiving circuit RX and a transmitting circuit TX, and a logic circuit Lo is arranged between the receiving circuit RX and the transmitting circuit TX.
  • the receiving circuit RX can also be called a deserializer.
  • the receiving circuit RX is arranged between the input port In and the input terminal of the logic circuit Lo.
  • the receiving circuit RX is used to obtain a serial signal from the input port In and convert the serial signal
  • Multiple parallel signals are provided to multiple logic units in the logic circuit Lo;
  • the transmission circuit TX can also be called a serializer, and the transmission circuit TX is arranged between the output terminal of the logic circuit Lo and the output port Out, and the transmission circuit TX is used for To convert the multiple parallel signals to be output in the chip 100 into serial signals and output them through the output port Out.
  • the input port In of the chip 100 can be connected to the chip 200, and the output port Out of the chip 100 can be connected to the chip 300 to realize cascade connection between multiple chips, as shown in FIG. 2A .
  • the chip 200 inputs serial data signals to SerDes1 through the input port In, and the receiving circuit RX in SerDes1 converts the serial data signals into multiple parallel data signals, and converts multiple parallel data signals through the output terminal Ir1 in the receiving circuit RX.
  • the performance of each logic unit in the chip 100 needs to be tested before the chip 100 leaves the factory. Testing the performance of each logic unit in the chip 100 may be said that the chip 100 is in the first test mode.
  • the input port In and the output port Out of the chip 100 can be connected to the test equipment, as shown in FIG. 2B .
  • the input port In and the output port Out are not only used for data signal transmission between the above chips, but also used for inputting the test signal A to the chip 100 and outputting the test signal B from the chip 100 .
  • each logic unit in the scan test chain performs a shift scan test based on the test signal A, and generates a test signal B based on the scan test result;
  • the transmitting circuit TX in SerDes1 receives the test signal B from the logic circuit Lo through the input port It2 , the transmitting circuit TX outputs the test signal B to the test equipment through the output port Out.
  • the number of logic units included in each scan test chain in the logic circuit Lo can be the same or different, and the number of logic units included in the scan test chain can be set according to the needs of the application scenario.
  • signals are not necessarily transmitted sequentially along the logic units connected in series in the scan test chain. For example, when the logic circuit Lo is in the working mode, the logic unit 01 may process the received signal and provide it to the logic unit m1 , and the logic unit m1 further processes the received signal and then provide it to the logic unit 01 .
  • each logic unit in the scan test chain 0 includes a register, for example, logic unit 01 includes a register SF01 , logic unit 02 includes a register SF02 , and logic unit 0n includes a register SF0n.
  • Each register includes a working signal input terminal D, a test signal input terminal SI, an enable terminal SE, a clock signal input terminal CK and a signal output terminal Q.
  • the signal output terminal Q of the register SF01 can be connected to the working signal input terminal D of the register SF02 through more circuit registers, and the signal output terminal Q of the register SF01 is directly connected to the test signal input terminal SI of the register SF02.
  • the enabling terminal SE of each register can input a first level signal, for example, it can be logic "1", and the working signal input terminal D and signal output terminal Q of each register form a signal transmission path,
  • the signal received by the working signal input terminal D of each register is provided to the signal output terminal Q;
  • the enable terminal SE of each register can input a second level signal, for example, it can be a logic " 0"
  • the test signal input terminal SI of each register and the signal output terminal Q form a signal transmission path
  • the test signal received by the test signal input terminal SI of the register SF01 is provided to the test signal input terminal SI of the register SF02 through the signal output terminal Q , so as to gradually shift
  • the chip 100 is cascaded with other chips (such as the chip 200 and the chip 300 shown in FIG. Whether the signals between the chips are circulating, the signal transmission performance, and whether the chip pins are broken, etc., have an impact on the interconnection performance between the chip 100 and other chips (such as the interconnection performance between the chip 100 and the chip 200, the chip 100 and the chip 300).
  • the interconnection performance between the chips 100 can be said to be in the second test mode. When the chip 100 is in the second test mode, the input port In and the output port Out of the chip 100 are respectively connected to the chip 200 and the chip 300 shown in FIG. 2A .
  • the input port In and the output port Out are also used to input the test signal C to the chip 100 and output the test signal D from the chip 100 .
  • the chip 100 also includes a boundary scan test chain, which includes a plurality of boundary scan units connected in series, and the plurality of boundary scan units can be correspondingly arranged next to a plurality of pins of the chip 100, and each boundary scan Each scan unit includes a boundary scan register. A plurality of scan registers are connected in series through input terminals and output terminals. The input end of the boundary scan test chain is connected to the input port In1 of the chip 100 , and the output end of the boundary scan test chain is connected to the output port O1 .
  • test equipment inputs a test signal C to the boundary scan test chain through the input port In1 of the chip 100, and each boundary scan unit in the boundary scan test chain performs a shift scan process on the test signal C to generate a test signal D from the output port O1 of the chip 100 output.
  • each boundary scan unit in the boundary scan test chain is also respectively connected to the receiving circuit RX and the transmitting circuit TX in SerDes1, so that signals can be input to and output from a single boundary scan unit, so as to Separate pins on the chip 100 are tested, and Fig.
  • FIG. 1 schematically shows the situation that the boundary scan unit is connected with the output terminal Ir2 of the receiving circuit RX and the input terminal It2 of the transmitting circuit TX; Multiple Boundary Scan Units input multiple parallel signals, and the transmitting circuit TX may also receive multiple parallel signals from multiple Boundary Scan Units to test multiple independent pins on the chip 100 .
  • FIG. 3 is a schematic structural diagram of the receiving circuit RX shown in FIG. 1 .
  • the reception circuit RX includes a boundary scan circuit 11 , a deserialization circuit 12 and a multiplexer 13 .
  • the signal input end of the boundary scan circuit 11, the signal input end of the deserialization circuit 12 and the first input end of the multiplexer 13 are all connected to the input port In, and the signal output end of the boundary scan circuit 11 is connected to the multiplexer 13
  • the second input terminal of the deserialization circuit 12 is connected to the output terminal Ir1 of the receiving circuit RX, and the output terminal of the multiplexer 13 is connected to the output terminal Ir2 of the receiving circuit RX.
  • the multiplexer 13 gated the second input of the multiplexer 13 (that is, the gate boundary scan circuit 11), and the test signal received by the input port In E is provided to the multiplexer 13 after being processed by the boundary scan circuit 11, and the multiplexer 13 outputs the received test signal E to the boundary scan unit in the boundary scan test chain through the output terminal Ir2.
  • the boundary scan circuit 11 described in the embodiment of the present application may be set based on the standard 1149.6 formulated by the Institute of Electrical and Electronics Engineers (IEEE).
  • the test signal A can be provided to the scan test chain without passing through a device that limits the signal transmission rate such as a hysteresis comparator, thereby greatly improving the transmission of the test signal A for testing each logic unit in the chip 100 rate, thereby improving the test efficiency of testing each logic unit.
  • the first input terminal of the multiplexer 13 is directly connected to the input port In through an electronic transmission line.
  • the input port In and the multiplexer A buffer circuit 10 is also provided between the first input terminals of the way selector 13, as shown in FIG. 5 .
  • the buffer circuit 10 can reduce the transmission delay of the test signal A, thereby further increasing the signal transmission rate.
  • the buffer circuit 10 described in the embodiment of the present application can be implemented in various ways. In a possible implementation manner, the buffer circuit 10 may include a high-pass filter circuit.
  • the receiving circuit RX also includes an impedance matching circuit 14 .
  • the impedance matching circuit 14 is used to realize the impedance matching between the transmission line impedance and the excitation source impedance.
  • the excitation source can be a test device for inputting a test signal to the input port In or the previous stage chip 200 for inputting a data signal to the input port In; the transmission line can be from the excitation source to the input port In and the input port In to the latter Transmission lines between stage circuits. As shown in FIG.
  • the impedance matching circuit 14 includes a resistor R1 and a resistor R2 .
  • the resistor R1 is connected in series between the input port In and the buffer circuit.
  • the resistor R2 is a variable resistor, one end of the resistor R2 is connected to the input end of the buffer circuit 10 , the input end of the boundary scan circuit 11 and the input end of the deserialization circuit 12 , and the other end of the resistor R2 is connected to the common ground Gnd.
  • the receiving circuit RX described in the embodiment of the present application further includes other circuits or components, for example, the receiving circuit RX further includes a buffer circuit 15 disposed at the output end of the multiplexer 13 .
  • the buffer circuit 15 buffers the signal output from the multiplexer 13 and outputs it.
  • the buffer circuit 15 is the same as the buffer circuit used in the conventional technology, and will not be repeated here.
  • the signals transmitted between the chips may be differential signals.
  • the input ports connected to the same SerDes may include There are two input ports In1 and In2, and the two input ports are used to input a pair of differential signals.
  • the structure of the receiving circuit RX described in the embodiment of the present application is shown in FIG. 6 .
  • the receiving circuit RX includes a buffer circuit 101 , a buffer circuit 102 , a boundary scan circuit 111 , a boundary scan circuit 112 , a deserialization circuit 12 , a multiplexer 131 and a multiplexer 132 .
  • the input end of the buffer circuit 101, the input end of the boundary scan circuit 111 and the first input end of the deserialization circuit 12 are all connected to the input port In1, and the output end of the buffer circuit 101 and the output end of the boundary scan circuit 111 are connected to the multiplexer respectively.
  • the first input terminal and the second input terminal of the device 131; the output terminal of the multiplexer 131 is connected to the output terminal Ir21 of the receiving circuit RX through the buffer circuit 151 .
  • the second input terminals of the buffer circuit 102, the boundary scan circuit 112 and the deserialization circuit 12 are all connected to the input port In2, and the output terminals of the buffer circuit 102 and the output terminal of the boundary scan circuit 112 are respectively connected to the first input of the multiplexer 132 terminal and the second input terminal.
  • the output terminal of the multiplexer 132 is connected to the output terminal Ir22 of the receiving circuit RX through the buffer circuit 152 .
  • the two output terminals of the deserialization circuit 12 are respectively connected to the output terminals Ir11 and Ir12 of the receiving circuit RX.
  • the output terminals Ir11, Ir12, Ir21 and Ir22 of the receiving circuit RX are all connected to the logic circuit Lo as shown in FIG. 1 .
  • the input port In1 and the input port In2 are used to receive the serial differential signal, and the received serial differential signal Converted into parallel differential signals and provided to the logic units in the logic circuit Lo; when it is necessary to test each logic unit in the chip 100, the first signal transmission path from the input port In1 to the output terminal Ir21 can be used as shown in Fig.
  • the scan test chain shown in 1 inputs the test signal, or the second signal transmission path from the input port In2 to the output terminal Ir22 can be used to input the test signal to the scan test chain shown in Figure 1, or the above two signals can be used at the same time
  • the transmission path inputs test signals to the scan test chain shown in Figure 1; when it is necessary to test the interconnection performance between the chip 100 and other chips, the first signal transmission path from the input port In1 to the output port Ir21 can be used Input the test signal to the boundary scan test chain shown in Figure 1, or use the second signal transmission path from the input port In2 to the output terminal Ir22 to input the test signal to the boundary scan test chain shown in Figure 1, or use it at the same time
  • the above two signal transmission paths input test signals to the boundary scan test chain shown in FIG.
  • the input port In1 and the input port In2 can receive different test signals respectively, and then the received different test signals Provide different scan test chains to perform scan tests on multiple logic units in parallel at the same time, thereby improving signal test efficiency.
  • the transmitting circuit TX as shown in FIG. 1 includes a parallel-to-serial conversion circuit 30, a multiplexer 31, a multiplexer 32, and a driving circuit 33, as shown in FIG. A specific structural schematic diagram of the transmission circuit TX shown.
  • the input terminal of the parallel-to-serial conversion circuit 30 is connected to the input terminal It1 of the transmitting circuit TX, and the input terminal It1 of the transmitting circuit TX is connected to one of the input terminals of the logic circuit Lo for receiving multiple signals from the logic circuit Lo.
  • a data signal, the multi-channel data signal is obtained after each logic unit in the logic circuit Lo processes the data signals input by other chips; the first input terminal and the second input terminal of the multiplexer 31 are connected with the transmission circuit TX respectively.
  • the input terminal It2 is connected to the input terminal It3, the input terminal It2 of the transmitting circuit TX is connected to the scan test chain and the boundary scan test chain in the logic circuit Lo, and is used to receive the test signal from the scan test chain or the boundary scan test chain, and the transmission circuit TX
  • the input end It3 is connected with the control circuit (wherein the control circuit refers to the relevant description in the embodiment shown in FIG.
  • At least one of the amplitude and the polarity of the output signal is connected to the first input end of the multiplexer 32, and the output end of the multiplexer 31 is connected to the first input end of the multiplexer 32
  • Two input terminals, the output terminal of the multiplexer 32 is connected to the input terminal of the driving circuit 33, and the output terminal of the driving circuit 33 is connected to the output port Out.
  • the multiplexer 31 selects the first input terminal, and the multiplexer 32 selects the second input terminal, which is used to configure the parameter configuration of the parameters of the drive circuit 33
  • the signal is input from the input terminal It3, and is provided to the drive circuit 33 after passing through the multiplexer 31 and the multiplexer 32, and the drive circuit 33 adjusts parameters such as amplitude and power based on the parameter configuration signal; then, the multiplexer 32 gates
  • the parallel-to-serial conversion circuit 30 receives multiple parallel signals from the logic circuit Lo, converts the multiple parallel signals into serial signals and provides them to the multiplexer 32, and the multiplexer 32 converts the multiplexer signals
  • the received serial signal is provided to the driving circuit 33 , and the driving circuit 33 performs processing such as power amplification and amplitude adjustment on the signal provided by the multiplexer 32 and then outputs it.
  • the driving circuit 33 When each logic unit in the chip 100 needs to be tested, the driving circuit 33 first configures the parameters of the driving circuit 33 based on the parameter configuration signal input by the input terminal It3, and then the multiplexer 31 selects the first gate of the multiplexer 31.
  • One input terminal, multiplexer 32 gates the second input terminal of multiplexer 32, the test signal B output from the scan test chain in the logic circuit Lo is input from input terminal It2, passes through multiplexer 31 and multiplexer
  • the selector 32 is provided to the drive circuit 33 , and is output after being processed by the drive circuit 33 such as power amplification.
  • the driver circuit 33 When it is necessary to test the interconnection performance between the chip 100 and the remaining chips, the driver circuit 33 first configures the parameters of the driver circuit 33 based on the parameter configuration signal input by the input terminal It3, and then the multiplexer 31 selects the multiplexer.
  • the output end of the parallel-to-serial conversion circuit 30 is set at the first input end of the multiplexer 32, and when the chip 100 is in the working mode, the data signal passes through the parallel-serial conversion circuit 30 It also needs to be provided to the driving circuit through the multiplexer 32 .
  • Setting the multiplexer 32 on the data signal transmission path usually affects the performance of the data signal transmitted on the data signal transmission path, such as causing signal attenuation or a decrease in signal transmission rate.
  • the embodiment of the present application also provides a second possible implementation manner of the transmitting circuit TX, as shown in FIG. 8 . In FIG.
  • the transmitting circuit TX includes a parallel-to-serial conversion circuit 30 , a multiplexer 31 and a driving circuit 33 .
  • the output terminal of the parallel-to-serial conversion circuit 30 is directly connected to an input terminal of the driving circuit 33 .
  • the drive circuit 33 includes two input terminals, one of which is connected to the parallel-to-serial conversion circuit 30, and the other is connected to the output terminal of the multiplexer 31, so that the data signal output by the parallel-to-serial conversion circuit 30 It can be directly provided to the driving circuit 33 without going through the multiplexer 32, thereby improving the signal transmission performance of the transmitting circuit TX.
  • the driving circuit 33 can output the signal provided by the parallel-to-serial conversion circuit 30 or the signal provided by the multiplexer 31 based on the control of the control circuit (for the description of the control circuit, refer to the embodiment shown in FIG. 11 ). It should be noted that the functions of the parallel-to-serial conversion circuit 30 and the multiplexer 31 shown in FIG. 31 are the same, and will not be repeated here.
  • the drive circuit 33 may include an output terminal Out1 and an output terminal Out2, and when it is necessary to output the data signal processed by the logic circuit Lo, the output The terminal Ou1 and the output terminal Ou2 are used to output a pair of differential signals; when it is necessary to output the test signal provided by the scan test chain or the test signal provided by the boundary scan test chain, one of the output terminal Ou1 and the output terminal Ou2 can be selected output.
  • the signal transmission frequency of each scan test chain in the multiple scan test chains included in the logic circuit Lo is usually between 100MHz and 200MHz.
  • the signal transmission frequency of each boundary scan unit in the boundary scan test chain The frequency is also between 100MHz and 200MHz, and the frequency of the signal output from the output terminal of the receiving circuit RX is usually between 800MHz and 1GHz.
  • a shunt is further provided between the output terminal Ir2 of the receiving circuit RX and the logic circuit Lo (or between the output terminal Ir2 of the receiving circuit RX and the boundary scan test chain).
  • device D as shown in Figure 9.
  • Multiple output terminals of the splitter D can be connected to multiple scan test chains in the logic circuit Lo correspondingly, so as to respectively provide test signals to the multiple scan test chains.
  • multiple output ends of the splitter D are also correspondingly connected to multiple boundary scan units of the boundary scan test chain, so as to respectively provide test signals to multiple independent boundary scan units.
  • the splitter D can divide the higher frequency test signal into multiple lower frequency test signals. For example, the splitter D splits the 800MHz test signal into eight parallel test signals, each of which has a frequency of 100MHz.
  • a combiner M is also provided between the input terminal It2 of the transmitting circuit TX and the logic circuit Lo (or between the input terminal It2 of the transmitting circuit TX and the boundary scan test chain), as shown in FIG. 9 .
  • the multiple input terminals of the combiner M can be respectively connected to multiple scan test chains in the logic circuit Lo, so as to respectively receive shifted and scanned test signals from the multiple scan test chains.
  • the multiple input terminals of the combiner M are respectively connected to multiple boundary scan units of the boundary scan test chain, so as to respectively receive test signals from multiple independent boundary scan units.
  • the combiner M can convert multiple parallel transmissions of lower frequency test signals into one serial transmission of higher frequency test signals.
  • the number of output terminals of the splitter D and the number of parallel signals output, the number of input terminals of the combiner M and the number of parallel input signals are based on the number of logic units in the chip 100, the number of scanning
  • the number of test chains and the number of logic units connected in series to each test chain are determined, which is not specifically limited in this embodiment of the present application. It can be seen from FIG. 9 that, in the embodiment of the present application, by setting the splitter D and the combiner M, without changing the number of input ports of the chip 100, by multiplexing the input ports In and The output port Out can convert one test signal input by the input port In into multiple parallel test signals, and scan and test multiple scan test chains at the same time.
  • the serial signal is output from the output port Out, so that the number of logic units scanned and tested by each scan test chain can be reduced.
  • the splitter D to convert the high-frequency signal into multiple low-frequency signals, the difficulty of implementing the scan test chain can also be reduced.
  • a decompression circuit can also be set at the output end of the splitter D and multiple scan test chains, and the scan test can be provided to more boundary scan test chains by setting the decompression circuit. signal; in addition, a compression circuit is set between the multiple scanning test chains and the combiner, thereby compressing more test signals into one test signal.
  • the structure of the decompression circuit and the compression circuit can adopt the structure of the decompression circuit and the compression circuit adopted in the traditional scanning test circuit, and the embodiment of the present application will not repeat them in detail.
  • the chip 100 further includes a control circuit C, as shown in FIG. 10 .
  • the control circuit C can control the input terminal selected by the multiplexer 13 in the receiving circuit RX as shown in Figure 3, Figure 5 or Figure 6, and can also control the multiplexer as shown in Figure 7 or Figure 8
  • the input terminal 31 is selected, and the control circuit C is also used to control the driving circuit 33 to output the signal provided by the parallel-to-serial conversion circuit 30 or the signal provided by the multiplexer 31 .
  • control circuit C is also used to input control signals to the receiving circuit RX and the transmitting circuit TX, so as to control the deserialization circuit 12, the boundary scan circuit 11 and the parallel-to-serial conversion Circuit 30 is disabled.
  • the disabling enable described here can be understood as powering off, entering a sleep mode or a high-impedance mode, and the like.
  • the chip 100 includes one SerDes.
  • the chip 100 may also include multiple SerDes, and a shunt may be provided between the receiving circuit RX and the transmitting circuit TX of each SerDes.
  • FIG. 11 schematically shows that the chip 100 includes 2 SerDes, 2 splitters and 2 combiners.
  • the chip 100 also includes two input ports, an input port In1 and an input port In2, and two output ports, an output port Out1 and an output port Out2.
  • the receiving circuit RX1 and transmitting circuit TX1 of one of the SerDes are respectively connected to the input port In1 and the output port Out1, and the output terminal of the receiving circuit RX1 inputs the test signal to the scan test chain 0 ⁇ scan test chain t respectively through the splitter D1, and the scan test
  • the signal output from chain 0 to scan test chain t is provided to the transmitting circuit TX1 through the combiner M1 to be output from the transmitting circuit TX1;
  • the receiving circuit RX2 and the transmitting circuit TX2 of another SerDes are respectively connected to the input port In2 and the output port Out2,
  • the output terminal of the receiving circuit RX2 inputs test signals to the scan test chain t+1 ⁇ scan test chain m respectively through the splitter D2, and the output signal of the scan test chain t+1 ⁇ scan test chain m is provided to the transmitter through the combiner M2 circuit TX2 to output from the transmitting circuit TX2.
  • t is an integer smaller than m.
  • the embodiment of the present application also provides an electronic device, which may include but not limited to: portable computers (such as mobile phones), notebook computers, wearable electronic devices (such as smart watches), tablet computers, augmented reality (augmented reality, AR) Or virtual reality (virtual reality, VR) equipment, etc.
  • the electronic device described in the embodiment of the present application may include the chip 100 as described in any embodiment shown in FIG. 1 , FIG. 9 , FIG. 10 or FIG. 11 .
  • the chip 100 described in the above embodiments may include, but is not limited to: an artificial intelligence processor chip, a memory chip, a digital signal processor chip, a tensor processor chip, or a system-on-chip.
  • the electronic device described in the embodiment of the present application may further include a chip 200 and a chip 300 , and the chip 100 is used for receiving signals from the chip 200 and transmitting signals to the chip 300 .

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Abstract

一种芯片和芯片测试装置，该芯片(100)包括输入端口(In)、输出端口(Out)、串行解串行器(1)和扫描测试链；串行解串行器(1)包括接收电路(RX)和发射电路(TX)，接收电路(RX)与输入端口(In)和扫描测试链的输入端连接，发射电路(TX)与输出端口(Out)和扫描测试链的输出端连接；接收电路(RX)包括边界扫描电路(11)和第一多路选择器(13)，第一多路选择器(13)的第一输入端与输入端口(In)连接，第一多路选择器(13)的第二输入端通过边界扫描电路(11)与输入端口(In)连接；第一多路选择器(13)，用于将第一测试信号通过第一多路选择器(13)的第一输入端传输至扫描测试链，第一测试信号是输入端口从测试设备接收的，可以提高对芯片中各逻辑单元进行测试的测试效率。

Description

芯片和芯片测试装置 技术领域
本申请实施例涉及电路技术领域，尤其涉及一种芯片和芯片测试装置。
背景技术
随着电子技术的发展，集成电路的功能显著的提升，诸如系统级芯片(SOC，System on chip)、大规模逻辑电路等被广泛应用。当前SOC或者大规模逻辑电路中，为了实现更多以及更复杂的逻辑功能，在同一个芯片中通常集成越来越多的逻辑单元电路，而芯片通常设置较少的输入输出(IO，InOut)端口与外部芯片或电路进行信号交流。
通常，在芯片出厂前需要对芯片内集成的每一个逻辑单元电路进行测试，以检测各逻辑单元电路的性能。对芯片内部各逻辑单元电路进行性能测试时，由于芯片较少的IO端口无法满足对多个逻辑单元的并行测试，当前对逻辑单元测试的技术中，通常需要在芯片内部形成串联扫描测试链对多个逻辑单元进行测试。然而，由于芯片内部集成的逻辑单元越来越多导致串联扫描测试链越来越长，从而导致对逻辑单元电路测试效率低下。由此，如何提高对芯片中各逻辑单元进行测试的效率成为需要解决的问题。
发明内容
本申请提供的芯片和芯片测试装置，可以提高对芯片中各逻辑单元进行测试的测试效率。
为达到上述目的，本申请采用如下技术方案：
第一方面，本申请实施例提供一种芯片，该芯片包括：输入端口、输出端口、串行解串行器和扫描测试链；所述串行解串行器包括接收电路和发射电路，所述接收电路与所述输入端口和所述扫描测试链的输入端连接，所述发射电路与所述输出端口和所述扫描测试链的输出端连接；所述接收电路包括边界扫描电路和第一多路选择器，所述第一多路选择器的第一输入端与所述输入端口连接，所述第一多路选择器的第二输入端通过所述边界扫描电路与所述输入端口连接；所述第一多路选择器，用于将第一测试信号通过所述第一多路选择器的第一输入端传输至所述扫描测试链，所述第一测试信号是所述输入端口从测试设备接收的。
通常，业界复用芯片中现有的串行解串行器，向扫描测试链输入测试信号以及从扫描测试链获得测试结果时，向扫描测试链输入测试信号的通路中，通常需要经过边界扫描电路，由于边界扫描电路中设置有迟滞比较器等器件，测试信号经过迟滞比较器等器件后降低了测试信号的传输带宽，例如信号传输带宽被限制在25Mhz～100Mhz之间，采用该信号传输带宽传输的测试信号输入至串行的扫描测试链中，极大降低了测试信号的传输速率。本申请实施例中，通过在串行解串行器的信号接收端设置第一多路选择器，第一多路选择器的第一输入端通过电子线路与输入端口连接，在对芯片内各逻辑单元进行测试时，测试 信号可以不需要经过诸如迟滞比较器等限制信号传输速率的器件即可提供至扫描测试链，从而可以极大提高测试信号的传输速率，进而提高对各逻辑单元进行测试的测试效率。
在一种可能的实现方式中，所述接收电路还包括缓冲电路，所述第一多路选择器的第一输入端通过所述缓冲电路与所述输入端口连接。
在输入端口和第一多路选择器之间设置缓冲电路，可以降低测试信号传输时延，从而进一步提高信号传输速率。
在一种可能的实现方式中，所述缓冲电路包括高通滤波器和电容电路中的一项，所述电容电路包括多个并联连接的电容。
在一种可能的实现方式中，所述接收电路还包括阻抗匹配电路；所述输入端口通过所述阻抗匹配电路与所述边界扫描电路以及所述缓冲电路连接。
本申请实施例通过设置阻抗匹配电路，可以降低信号传输过程中能量的损耗，使得输入端口输入的信号可以有效传递至后一级电路，从而可以进一步提高测试信号的传输性能。
进一步的，阻抗匹配电路包括第一电阻和第二电阻。所述第一电阻串联在所述输入端口以及所述缓冲电路之间；所述第二电阻的一端与所述缓冲电路的输入端连接，所述第二电阻的另外一端与公共地连接。
在一种可能的实现方式中，所述扫描测试链是对所述芯片中的多个逻辑单元级联得到的；所述接收电路还包括：解串行电路，用于将串行的第一数据信号转换成多路并行的第一数据信号传输至所述多个逻辑单元，所述串行的第一数据信号是所述输入端口从第一芯片接收的。
在一种可能的实现方式中，所述发射电路包括并串转换电路、第二多路选择器和驱动电路；所述并串转换电路和所述第二多路选择器均与所述驱动电路连接；所述并串转换电路，用于从所述多个逻辑单元接收多路并行的第二数据信号，将所述多路并行的第二数据信号转换成串行的第二数据信号；所述第二多路选择器，用于从所述扫描测试链接收第二测试信号，将所述第二测试信号输出，所述第二测试信号是所述扫描测试链对所述第一测试信号进行移位扫描后得到的；所述驱动电路，用于选择性的将所述串行的第二数据信号或者所述第二测试信号通过所述输出端口输出。
本申请实施例所述的发射电路，并串转换电路输出的数据信号可以直接提供至驱动电路，可以提高发射电路的信号传输性能。
在一种可能的实现方式中，所述芯片还包括控制电路；所述第二多路选择器还用于：从所述控制电路接收参数配置信号，将所述参数配置信号提供至所述驱动电路，所述参数配置信号用于配置所述驱动电路的信号输出功率、信号幅度以及信号极性中的至少一项；所述驱动电路还用于：基于所述参数配置信号，调节所述驱动电路的参数。
在一种可能的实现方式中，所述芯片包括多条扫描测试链；所述芯片还包括：分路器，设置于所述发射电路和所述多条扫描测试链之间，用于将所述第一测试信号功分成多路第一测试信号，分别提供至所述多条扫描测试链；合路器，设置于所述多条扫描测试链和所述接收电路之间，用于将所述多条扫描测试链输出的多路第二测试信号合成一路第二测试信号，提供至所述接收电路。
本申请实施例通过设置分路器和合路器，在不改变芯片的输入端口数目的情况下，通过复用串行解串行器的输入端口和输出端口，可以将输入端口输入的一路测试信号转换成 多路并行测试信号，对多条扫描测试链同时进行扫描测试，在多条扫描测试链扫描测试完成后通过合路器合为一路串行信号从输出端口输出，从而可以降低每一条扫描测试链所扫描测试的逻辑单元的数目。另外，通过利用分路器将高频率信号转换成多路低频率信号，还可以降低扫描测试链的实现难度。
在一种可能的实现方式中，所述芯片还包括：边界扫描测试链，所述边界扫描测试链包括多个边界扫描单元，所述多个边界扫描单元与所述接收电路的输出端和所述发射电路的输入端连接；所述多个边界扫描单元中的每一个边界扫描单元用于从所述接收电路接收第三测试信号，以及向所述发射电路输出第四测试信号。
第二方面，本申请实施例提供一种芯片测试装置，该芯片测试装置包括测试设备以及如第一方面所述的芯片；所述芯片的输入端口和输出端口均与所述测试设备连接。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例的描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的芯片100的一个结构示意图；
图2A是本申请实施例提供的芯片100的应用场景示意图；
图2B是本申请实施例提供的芯片100与测试设备连接的结构示意图；
图2C是本申请实施例提供的扫描测试链的一个结构示意图；
图3是本申请实施例提供的串行解串行器中接收电路RX的一个结构示意图；
图4是本申请实施例提供的接收电路RX中的边界扫描电路的一个结构示意图；
图5是本申请实施例提供的串行解串行器中接收电路RX的又一个结构示意图；
图6是本申请实施例提供的串行解串行器中接收电路RX的又一个结构示意图；
图7是本申请实施例提供的串行解串行器中发射电路TX的又一个结构示意图；
图8是本申请实施例提供的串行解串行器中发射电路TX的又一个结构示意图；
图9是本申请实施例提供的芯片100的又一个结构示意图；
图10是本申请实施例提供的芯片100的又一个结构示意图；
图11是本申请实施例提供的芯片100的又一个结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本文所提及的"第一"、"第二"以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，"一个"或者"一"等类似词语也不表示数量限制，而是表示存在至少一个。"连接"等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的，等同于广义上的联通。
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。在本申请实施例的描述中，除非另有说明，“多个”的含义是指两个或两个以上。例如，多个逻辑单元是指两个或两个以上的逻辑单元。
请参考图1，图1是本申请实施例提供的芯片100的一个结构示意图。在图1中，芯片100包括串行和解串行器(SerDes，Serializer and DeSerializar)1以及逻辑电路Lo，该逻辑电路Lo包括逻辑单元01、逻辑单元02、逻辑单元0n、逻辑单元m1、逻辑单元m2、逻辑单元mn等多个逻辑单元，m和n为大于等于2的整数，n小于m，该多个逻辑单元用于实现芯片100的多种逻辑功能，该逻辑功能可以包括但不限于：运算和存储等。多个逻辑单元可以包括但不限于运算器(例如加法器、乘法器等)、缓存器等。需要说明的是，SerDes1也可以看成是芯片100中设置于逻辑电路Lo之外的一个逻辑单元。芯片100还包括输入端口In和输出端口Out，输入端口In和输出端口Out为一对IO端口均连接至SerDes1。输入端口In用于向SerDes1输入信号，输出端口Out用于从SerDes1输出信号。SerDes1包括接收电路RX和发射电路TX，逻辑电路Lo设置于接收电路RX和发射电路TX之间。接收电路RX也可以称为解串行器，接收电路RX设置于输入端口In与逻辑电路Lo的输入端之间，接收电路RX用于从输入端口In获得串行信号，以及将串行信号转换成多路并行信号提供至逻辑电路Lo中的多个逻辑单元；发射电路TX也可以称为串行器，发射电路TX设置于逻辑电路Lo的输出端与输出端口Out之间，发射电路TX用于将芯片100中待输出的多路并行信号转换成串行信号通过输出端口Out输出。
本申请实施例中，芯片100的输入端口In可以与芯片200连接，芯片100的输出端口Out可以与芯片300连接，实现多个芯片之间的级联，如图2A所示。芯片200通过输入端口In向SerDes1输入串行的数据信号，SerDes1中的接收电路RX将串行的数据信号转换成多路并行的数据信号，通过接收电路RX中的输出端Ir1将多路并行的数据信号提供至逻辑电路Lo；芯片100中的多个逻辑单元对该多路并行的数据信号进行处理，生成多路处理后的信号；SerDes1中的发射电路TX通过输入端口It1从逻辑电路Lo接收多路处理后的信号，发射电路TX将多路处理后的信号转换成串行的信号通过输出端口Out提供至芯片300。以上所介绍的芯片100与其他芯片之间进行信号交互可以称芯片100处于工作模式。
本申请实施例中，芯片100在出厂前需要对芯片100中的各逻辑单元的性能进行测试。对芯片100中的各逻辑单元的性能进行测试可以称芯片100处于第一测试模式。当芯片100处于第一测试模式时，芯片100的输入端口In和输出端口Out可以与测试设备连接，如图2B所示。此时，输入端口In和输出端口Out除了用于上述各芯片之间的数据信号传输外，还用于向芯片100输入测试信号A、以及从芯片100输出测试信号B。具体的，图1所示的芯片100所述的逻辑电路Lo中，还包括扫描测试链0、扫描测试链m等m条扫描测试链，m为大于等于2的整数。其中，每一条扫描测试链是将多个逻辑单元的输入端和输出端串联在一起所形成的。例如，扫描测试链0包括n个串联连接的逻辑单元，扫描测试链m包括n个串联连接的逻辑单元。当芯片100处于第一测试模式时，测试设备通过芯片100的输入端口In向SerDes1中的接收电路RX输入测试信号A，接收电路RX通 过输出端Ir2将测试信号A提供至逻辑电路Lo中的至少一条扫描测试链；扫描测试链中的各逻辑单元基于测试信号A进行移位扫描测试，基于扫描测试结果生成测试信号B；SerDes1中的发射电路TX通过输入端口It2从逻辑电路Lo接收测试信号B，发射电路TX将测试信号B通过输出端口Out输出至测试设备。需要说明的是，逻辑电路Lo中的各条扫描测试链所包括的逻辑单元的数目可以相同，也可以不同，根据应用场景的需要设置扫描测试链所包括的逻辑单元的数目。还需要说明的是，芯片100在工作模式下，信号不一定沿扫描测试链中所串联的逻辑单元依次传输。例如，当逻辑电路Lo处于工作模式时，逻辑单元01可以对所接收到的信号处理后提供至逻辑单元m1，逻辑单元m1对所接收到的信号进一步处理后进一步提供至逻辑单元01。
下面以扫描测试链0为例，结合图2C，对加入扫描测试链后的各逻辑单元的结构进行描述。在图2C中，扫描测试链0中每一个逻辑单元均包括一个寄存器，例如逻辑单元01包括寄存器SF01，逻辑单元02包括寄存器SF02，逻辑单元0n包括寄存器SF0n。每一个寄存器均包括工作信号输入端D、测试信号输入端SI、使能端SE、时钟信号输入端CK和信号输出端Q。寄存器SF01的信号输出端Q可以经过更多电路寄存器与寄存器SF02的工作信号输入端D连接，寄存器SF01的信号输出端Q直接与寄存器SF02的测试信号输入端SI连接。当芯片100处于上述工作模式时，各寄存器的使能端SE可以输入第一电平信号，例如可以为逻辑“1”，各寄存器的工作信号输入端D与信号输出端Q形成信号传输通路，各寄存器的工作信号输入端D接收到的信号提供至信号输出端Q；当芯片100处于上述第一测试模式时，各寄存器的使能端SE可以输入第二电平信号，例如可以为逻辑“0”，各寄存器的测试信号输入端SI与信号输出端Q形成信号传输通路，寄存器SF01的测试信号输入端SI接收到的测试信号通过信号输出端Q，提供至寄存器SF02的测试信号输入端SI，从而逐渐移位扫描至寄存器SF0n，通过寄存器SF0n的信号输出端Q输出。
请继续参考图1，本申请实施例中，芯片100与其他芯片(如图2A所示的芯片200和芯片300)级联后，还需要对各芯片之间的互联性能进行测试，以检测个芯片之间的信号是否流通、信号传输性能以及芯片管脚是否有无断裂等，对芯片100与其他芯片之间的互联性能(例如芯片100与芯片200之间的互联性能、芯片100与芯片300之间的互联性能)进行测试可以称芯片100处于第二测试模式。当芯片100处于第二测试模式时，芯片100的输入端口In和输出端口Out分别与图2A所示的芯片200和芯片300连接。此时，输入端口In和输出端口Out还用于向芯片100输入测试信号C、以及从芯片100输出测试信号D。具体的，芯片100还包括边界扫描测试链，该边界扫描测试链中包括串联连接的多个边界扫描单元，多个边界扫描单元可以对应设置于芯片100的多个引脚的旁边，每一个边界扫描单元均包括边界扫描寄存器。多个扫描寄存器通过输入端和输出端串联连接。边界扫描测试链的输入端与芯片100的输入端口In1连接，边界扫描测试链的输出端与输出端口O1连接。测试设备通过芯片100的输入端口In1向边界扫描测试链输入测试信号C，边界扫描测试链中的各边界扫描单元对测试信号C进行移位扫描处理，生成测试信号D从芯片100的输出端口O1输出。此外，边界扫描测试链中的每一个边界扫描单元还分别与SerDes1中的接收电路RX以及发射电路TX的连接，从而，可以向单独的边界扫描单元输入信号以及从边界扫描单元输出信号，以对芯片100上单独的引脚进行测试，图1中示意性的示出了边界扫描单元分别与接收电路RX的输出端Ir2连接以及发射电路TX 的输入端It2连接的情况；接收电路RX还可以向多个边界扫描单元输入多路并行的信号，发射电路TX还可以从多个边界扫描单元接收多路并行的信号，以对芯片100上多个独立的引脚进行测试。
基于图1所示的芯片100的结构，下面通过图3-图8所示的实施例，对本申请实施例所述的SerDes1中各电路的结构以及工作原理进行更为详细的描述。
请参考图3，图3是如图1所示的接收电路RX的结构示意图。在图3中，接收电路RX包括边界扫描电路11、解串行电路12和多路选择器13。边界扫描电路11的信号输入端、解串行电路12的信号输入端和多路选择器13的第一输入端均连接至输入端口In，边界扫描电路11的信号输出端连接至多路选择器13的第二输入端，解串行电路12的信号输出端连接至接收电路RX的输出端Ir1，多路选择器13的输出端连接至接收电路RX的输出端Ir2。当芯片100处于如上所述的工作模式时，解串行电路12用于通过输入端口In获得串行的数据信号，将串行的数据信号解串行生成多路并行的数据信号，通过输出端Ir1提供至逻辑电路Lo中的多个逻辑单元；当芯片100处于如上所述的第一测试模式时，多路选择器13选通多路选择器13的第一输入端，输入端口In接收到的如上所述的测试信号A，通过图3所示的电子线路直接提供至多路选择器13，多路选择器13将测试信号A通过输出端Ir2输出至逻辑电路Lo中的扫描测试链。当芯片100处于如上所述的第二测试模式时，多路选择器13选通多路选择器13的第二输入端(也即选通边界扫描电路11)，输入端口In接收到的测试信号E，通过边界扫描电路11处理后提供至多路选择器13，多路选择器13将所接收到的测试信号E通过输出端Ir2输出至边界扫描测试链中的边界扫描单元。需要说明的是，本申请实施例中所述的边界扫描电路11，可以是基于美国电子和电气工程师协会(IEEE，Institute of Electrical and Electronics Engineers)制定的标准1149.6而设置的。
基于标准1149.6的规定，如图3所示的边界扫描电路11设置有迟滞比较器F以用于接收测试信号，如图4所示，图4示意性的示出了边界扫描电路11的一个结构示意图。传统技术中，在接收电路RX内部，对芯片100内各逻辑单元的性能进行测试的测试信号传输通路，与对各芯片之间的互联性能进行测试的测试信号传输通路相同，即均通过如图4所示的边界扫描电路11将测试信号提供至输出端Ir2。测试信号经过迟滞比较器F后，信号传输带宽被限制在25Mhz～100Mhz之间，极大降低了测试信号的传输速率。本申请实施例中，通过在SerDes1的信号接收端RX设置多路选择器13，多路选择器13的第一输入端通过电子线路与输入端口In连接，在对芯片100内各逻辑单元进行测试时，测试信号A可以不需要经过诸如迟滞比较器等限制信号传输速率的器件即可提供至扫描测试链，从而可以极大提高用于对芯片100内各逻辑单元进行测试的测试信号A的传输速率，进而提高对各逻辑单元进行测试的测试效率。
如图3所示的接收电路RX中，多路选择器13的第一输入端通过电子传输线直接连接至输入端口In，在本申请实施例一种可选的实现方式中，输入端口In和多路选择器13的第一输入端之间还设置有缓冲电路10，如图5所示。该缓冲电路10可以降低测试信号A传输时延，从而进一步提高信号传输速率。本申请实施例所述的缓冲电路10可以通过多种方式实现。在一种可能的实现方式中，缓冲电路10可以包括高通滤波电路。在另外一种可能的实现方式中，缓冲电路10可以包括电容电路，该电容电路可以包括多个并联 设置的电容，该多个并联设置的电容均设置于输入端口In与多路选择器13的第一输入端之间。
请继续参考图5，本申请实施例中，为了提高信号传输性能，使得输入端口In输入的信号可以有效传递至后一级电路(例如缓冲电路10或者边界扫描电路11)，降低信号传输过程中能量的损耗，接收电路RX还包括阻抗匹配电路14。阻抗匹配电路14用于实现传输线阻抗与激励源阻抗之间的阻抗匹配。激励源可以是用于向输入端口In输入测试信号的测试设备或者用于向输入端In输入数据信号的前一级芯片200；传输线可以是从激励源至输入端口In和输入端口In至后一级电路之间的传输线。如图5所示，阻抗匹配电路14包括电阻R1和电阻R2。电阻R1串联在输入端口In以及缓冲电路之间。电阻R2为可变电阻，电阻R2的一端与缓冲电路10的输入端、边界扫描电路11的输入端以及解串行电路12的输入端连接，电阻R2的另一端连接至公共地Gnd。通过调节电阻R2的阻抗，即可实现激励源阻抗与传输线阻抗之间的阻抗匹配。此外，本申请实施例中所述的接收电路RX还包括其他电路或部件，例如，接收电路RX还包括设置于多路选择器13的输出端的缓冲电路15。缓冲电路15对多路选择器13输出的信号进行缓冲后输出。其中，缓冲电路15与传统技术中采用的缓冲电路相同，不再赘述。
本申请实施例一种可能的实现方式中，当芯片100处于如上所述的工作模式时，各芯片之间所传输的信号可以为差分信号，此时，与同一个SerDes连接的输入端口可以包括输入端口In1和输入端口In2两个，该两个输入端口用于输入一对差分信号。在此情况下，本申请实施例所述的接收电路RX的结构如图6所示。在图6中，接收电路RX包括缓冲电路101、缓冲电路102、边界扫描电路111、边界扫描电路112、解串行电路12、多路选择器131和多路选择器132。缓冲电路101的输入端、边界扫描电路111的输入端和解串行电路12的第一输入端均连接至输入端口In1，缓冲电路101的输出端和边界扫描电路111的输出端分别连接至多路选择器131的第一输入端和第二输入端；多路选择器131的输出端通过缓冲电路151连接至接收电路RX的输出端Ir21。缓冲电路102、边界扫描电路112和解串行电路12的第二输入端均连接至输入端口In2，缓冲电路102的输出端和边界扫描电路112的输出端分别连接至多路选择器132的第一输入端和第二输入端。多路选择器132的输出端通过缓冲电路152连接至接收电路RX的输出端Ir22。解串行电路12的两个输出端分别连接至接收电路RX的输出端Ir11和Ir12。此外，接收电路RX的输出端Ir11、Ir12、Ir21和Ir22均连接至如图1所示的逻辑电路Lo。在图6所示的接收电路RX中，当芯片100与其他芯片之间进行信号传输时，输入端口In1和输入端口In2用于接收串行的差分信号，将所接收到的串行的差分信号转换成并行的差分信号提供至逻辑电路Lo中的逻辑单元中；当需要对芯片100中的各逻辑单元进行测试时，可以采用由输入端口In1至输出端Ir21该条第一信号传输通路向图1所示的扫描测试链输入测试信号，也可以采用由输入端口In2至输出端Ir22该条第二信号传输通路向图1所示的扫描测试链输入测试信号，也可以同时采用上述两条信号传输通路向图1所示的扫描测试链输入测试信号；当需要对芯片100与其余各芯片之间的互联性能进行测试时，可以采用由输入端口In1至输出端Ir21该条第一信号传输通路向图1所示的边界扫描测试链输入测试信号，也可以采用由输入端口In2至输出端Ir22该条第二信号传输通路向图1所示的边界扫描测试链输入测试信号，也可以同时采用上述两条信号传输通路向图1所示的边界扫描测试链输入测 试信号。当同时采用上述第一信号传输通道和上述第二信号传输通道向扫描测试链输入测试信号时，输入端口In1和输入端口In2可以分别接收不同的测试信号，然后将所接收到的不同的测试信号提供至不同的扫描测试链，以同时并行对多个逻辑单元进行扫描测试，从而可以提高信号测试效率。
本申请实施例中，如图1所述的发射电路TX包括并串转换电路30、多路选择器31、多路选择器32和驱动电路33，如图7所示，图7是如图1所示的发射电路TX的一个具体结构示意图。在图7中，并串转换电路30的输入端连接至发射电路TX的输入端It1，发射电路TX的输入端It1与逻辑电路Lo的其中一个输入端连接，用于从逻辑电路Lo接收多路数据信号，该多路数据信号是逻辑电路Lo中的各逻辑单元对其他芯片输入的数据信号处理后得到的；多路选择器31的第一输入端和第二输入端分别与发射电路TX的输入端It2和输入端It3连接，发射电路TX的输入端It2与逻辑电路Lo中的扫描测试链以及边界扫描测试链连接，用于从扫描测试链或者边界扫描测试链接收测试信号，发射电路TX的输入端It3与控制电路连接(其中控制电路参考图11所示的实施例中的相关描述)，该控制电路用于配置驱动电路33的参数，该参数例如可以包括信号输出功率、输出信号的幅值和输出信号的极性中的至少一项；并串转换电路30的输出端连接至多路选择器32的第一输入端，多路选择器31的输出端连接至多路选择器32的第二输入端，多路选择器32的输出端连接至驱动电路33的输入端，驱动电路33的输出端连接至输出端口Out。当芯片100与其他芯片之间进行信号传输时，首先，多路选择器31选通第一输入端、多路选择器32选通第二输入端，用于配置驱动电路33的参数的参数配置信号从输入端It3输入，经过多路选择器31和多路选择器32后提供至驱动电路33，驱动电路33基于参数配置信号调节幅值、功率等参数；然后，多路选择器32选通多路选择器32的第一输入端，并串转换电路30从逻辑电路Lo接收多路并行信号，将多路并行信号转换成串行信号提供至多路选择器32，多路选择器32将所接收到的串行信号提供提供至驱动电路33，驱动电路33对多路选择器32提供的信号进行诸如功率放大、幅度调节等处理后输出。当需要对芯片100中的各逻辑单元进行测试时，驱动电路33首先基于输入端It3输入的参数配置信号，配置驱动电路33的参数，然后多路选择器31选通多路选择器31的第一输入端、多路选择器32选通多路选择器32的第二输入端，从逻辑电路Lo中的扫描测试链输出的测试信号B从输入端It2输入，通过多选择器31和多路选择器32提供至驱动电路33，经过驱动电路33进行诸如功率放大等处理后输出。当需要对芯片100与其余各芯片之间的互联性能进行测试时，驱动电路33首先基于输入端It3输入的参数配置信号，配置驱动电路33的参数，然后多路选择器31选通多路选择器31的第一输入端、多路选择器32选通多路选择器32的第二输入端，从边界扫描测试链的边界扫描单元输出的测试信号从输入端It2输入，通过多选择器31和多路选择器32提供至驱动电路33，经过驱动电路33进行诸如功率放大等处理后输出。
在如图7所示的发射电路TX中，并串转换电路30的输出端设置于多路选择器32的第一输入端，在芯片100处于工作模式时，数据信号通过并串转换电路30后还需要通过多路选择器32提供至驱动电路。在数据信号传输通路上设置多路选择器32，通常会影响数据信号传输通路上所传输的数据信号的性能，例如导致信号衰减或者信号传输速率下降等。为了进一步提高发射电路TX的性能，本申请实施例还提供了发射电路TX的第二种 可能的实现方式，如图8所示。在图8中，发射电路TX包括并串转换电路30、多路选择器31和驱动电路33。与图7所示的发射电路TX不同的是，在图8中，并串转换电路30的输出端直接连接至驱动电路33的一个输入端。也即在图8中，驱动电路33包括两个输入端，其中一个与并串转换电路30连接，另外一个与多路选择器31的输出端连接，从而，并串转换电路30输出的数据信号可以不需要经过多路选择器32，直接提供至驱动电路33，从而提高发射电路TX的信号传输性能。其中，驱动电路33可以基于控制电路(对控制电路的描述具体参考图11所示的实施例)的控制将并串转换电路30提供的信号或者将多路选择器31提供的信号输出。需要说明的是，图8中所示的并串转换电路30、多路选择器31的功能以及与发射电路TX输入端的连接关系与图7中所示的并串转换电路30和多路选择器31相同，在此不再赘述。
在一种可能的实现方式中，当各芯片之间传输的信号为差分信号时，驱动电路33可以包括输出端Out1和输出端Out2，当需要对逻辑电路Lo处理后的数据信号输出时，输出端Ou1和输出端Ou2用于输出一对差分信号；当需要对扫描测试链提供的测试信号或者边界扫描测试链提供的测试信号输出时，可以选择输出端Ou1和输出端Ou2中的一个输出端输出。
本申请实施例中，逻辑电路Lo所包括的多条扫描测试链中每一条扫描测试链的信号传输频率通常在100MHz～200MHz之间，同样，边界扫描测试链中每一个边界扫描单元的信号传输频率也在100MHz～200MHz之间，而接收电路RX的输出端输出的信号频率通常在800MHz～1GHz之间。当采用SerDes1中的接收电路RX直接向扫描测试链或者边界扫描测试链传输信号、采用SerDes1中的发射电路TX直接从扫描测试链或者边界扫描测试链接收信号时，容易造成信号传输带宽的浪费。因此，本申请实施例一种可能的实现方式中，在接收电路RX的输出端Ir2与逻辑电路Lo之间(或者接收电路RX的输出端Ir2与边界扫描测试链之间)还设置有分路器D，如图9所示。分路器D的多个输出端可以分别对应连接至逻辑电路Lo中的多条扫描测试链上，以分别向多条扫描测试链提供测试信号。此外，分路器D的多个输出端还分别对应连接至边界扫描测试链的多个边界扫描单元，以分别向多个独立的边界扫描单元提供测试信号。分路器D可以将较高频率的测试信号分频成多路较低频率的测试信号。例如，分路器D将800MHz的测试信号分成并行的八路测试信号，每一路测试信号的频率为100MHz。
进一步的，在发射电路TX的输入端It2与逻辑电路Lo之间(或者发射电路TX的输入端It2与边界扫描测试链之间)还设置有合路器M，如图9所示。合路器M的多个输入端可以分别对应连接至逻辑电路Lo中的多条扫描测试链上，以分别从多条扫描测试链接收移位扫描后的测试信号。此外，合路器M的多个输入端还分别对应连接至边界扫描测试链的多个边界扫描单元，以分别从多个独立的边界扫描单元接收测试信号。合路器M可以将多路并行传输的较低频率的测试信号转换成一路串行传输的较高频率的测试信号。
需要说明的是，分路器D的输出端的数目以及所输出的并行信号的路数、合路器M输入端的数目以及并行输入的信号的路数，根据芯片100中的逻辑单元的数目、扫描测试链的条数以及每一条测试链所串联的逻辑单元的数目确定，本申请实施例对此不做具体限定。从图9中可以看出，本申请实施例通过设置分路器D和合路器M，在不改变芯片100的输入端口数目的情况下，通过复用串行解串行器的输入端口In和输出端口Out，可以将 输入端口In输入的一路测试信号转换成多路并行测试信号，对多条扫描测试链同时进行扫描测试，在多条扫描测试链扫描测试完成后通过合路器合为一路串行信号从输出端口Out输出，从而可以降低每一条扫描测试链所扫描测试的逻辑单元的数目。另外，通过利用分路器D将高频率信号转换成多路低频率信号，还可以降低扫描测试链的实现难度。
本申请实施例一种可能的实现方式中，在分路器D的输出端与多条扫描测试链还可以设置解压缩电路，通过设置解压缩电路可以向更多路边界扫描测试链提供扫描测试信号；此外，多条扫描测试链与合路器之间还设置有压缩电路，从而将更多路测试信号压缩为一路测试信号。其中，解压缩电路和压缩电路可以采用传统扫描测试电路中所采用的解压缩电路和压缩电路的结构，本申请实施例不再详细赘述。
在图1、图3-图9任意所示的芯片100的结构的基础上，本申请实施例中，芯片100还包括控制电路C，如图10所示。控制电路C可以控制如图3、图5或图6所示的接收电路RX中的多路选择器13所选通的输入端，还可以控制如图7或图8所示的多路选择器31所选通的输入端，控制电路C还用于控制驱动电路33将并串转换电路30提供的信号或者将多路选择器31提供的信号输出。进一步的，当芯片100处于对逻辑单元进行测试的模式时，控制电路C还用于向接收电路RX以及发射电路TX输入控制信号，以控制解串行电路12、边界扫描电路11以及并串转换电路30停止使能。这里所述的停止使能可以理解为下电、进入休眠模式或者高阻态模式等。
以上各实施例中，示出了芯片100包括一个SerDes，在其他可能的场景中，芯片100还可以包括多个SerDes，每一个SerDes的接收电路RX和发射电路TX之间均可以设置有分路器、扫描测试链和合路器，从而可以形成更多路并行的扫描测试链，进而提高对逻辑电路Lo内部各逻辑单元的扫描测试速度。请参考图11，图11中示意性的示出了芯片100包括2个SerDes，2个分路器和2个合路器。此外，在图11中，芯片100还包括输入端口In1和输入端口In2两个输入端口，以及输出端口Out1和输出端口Out2两个输出端口。其中一个SerDes的接收电路RX1和发射电路TX1分别与输入端口In1和输出端口Out1连接，接收电路RX1的输出端通过分路器D1分别向扫描测试链0～扫描测试链t输入测试信号，扫描测试链0～扫描测试链t输出的信号通过合路器M1提供至发射电路TX1，以从发射电路TX1输出；另外一个SerDes的接收电路RX2和发射电路TX2分别与输入端口In2和输出端口Out2连接，接收电路RX2的输出端通过分路器D2分别向扫描测试链t+1～扫描测试链m输入测试信号，扫描测试链t+1～扫描测试链m输出的信号通过合路器M2提供至发射电路TX2，以从发射电路TX2输出。其中，t为小于m的整数。
本申请实施例还提供一种电子设备，该电子设备可以包括但不限于：便携式计算机(如手机)、笔记本电脑、可穿戴电子设备(如智能手表)、平板电脑、增强现实(augmentedreality，AR)或虚拟现实(virtual reality，VR)设备等。具体的，本申请实施例所述的电子设备可以包括如图1、图9、图10或图11任意实施例所述的芯片100。如上各实施例所述的芯片100可以包括但不限于：人工智能处理器芯片、存储器芯片、数字信号处理器芯片、张量处理器芯片或者系统级芯片等。此外，本申请实施例所述的电子设备还可以包括芯片200和芯片300，芯片100用于从芯片200接收信号，以及向芯片300传输信号。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管 参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (10)

  1. 一种芯片，其特征在于，包括输入端口、输出端口、串行解串行器和扫描测试链；
    所述串行解串行器包括接收电路和发射电路，所述接收电路与所述输入端口和所述扫描测试链的输入端连接，所述发射电路与所述输出端口和所述扫描测试链的输出端连接；
    所述接收电路包括边界扫描电路和第一多路选择器，所述第一多路选择器的第一输入端与所述输入端口连接，所述第一多路选择器的第二输入端通过所述边界扫描电路与所述输入端口连接；
    所述第一多路选择器，用于将第一测试信号通过所述第一多路选择器的第一输入端传输至所述扫描测试链，所述第一测试信号是所述输入端口从测试设备接收的。
  2. 根据权利要求1所述的芯片，其特征在于，所述接收电路还包括缓冲电路，所述第一多路选择器的第一输入端通过所述缓冲电路与所述输入端口连接。
  3. 根据权利要求2所述的芯片，其特征在于，所述缓冲电路包括高通滤波器和电容电路中的一项，所述电容电路包括多个并联连接的电容。
  4. 根据权利要求1-3任一项所述的芯片，其特征在于，所述接收电路还包括阻抗匹配电路；
    所述输入端口通过所述阻抗匹配电路与所述边界扫描电路以及所述缓冲电路连接。
  5. 根据权利要求1-4任一项所述的芯片，其特征在于，所述扫描测试链是对所述芯片中的多个逻辑单元级联得到的；所述接收电路还包括：
    解串行电路，用于将串行的第一数据信号转换成多路并行的第一数据信号传输至所述多个逻辑单元，所述串行的第一数据信号是所述输入端口从第一芯片接收的。
  6. 根据权利要求1-5任一项所述的芯片，其特征在于，所述发射电路包括并串转换电路、第二多路选择器和驱动电路；
    所述并串转换电路和所述第二多路选择器均与所述驱动电路连接；
    所述并串转换电路，用于从所述多个逻辑单元接收多路并行的第二数据信号，将所述多路并行的第二数据信号转换成串行的第二数据信号；
    所述第二多路选择器，用于从所述扫描测试链接收第二测试信号，将所述第二测试信号输出，所述第二测试信号是所述扫描测试链对所述第一测试信号进行移位扫描后得到的；
    所述驱动电路，用于选择性的将所述串行的第二数据信号或者所述第二测试信号通过所述输出端口输出。
  7. 根据权利要求6所述的芯片，其特征在于，所述芯片还包括控制电路；
    所述第二多路选择器还用于：从所述控制电路接收参数配置信号，将所述参数配置信号提供至所述驱动电路，所述参数配置信号用于配置所述驱动电路的信号输出功率、信号幅度以及信号极性中的至少一项；
    所述驱动电路还用于：基于所述参数配置信号，调节所述驱动电路的参数。
  8. 根据权利要求1-7任一项所述的芯片，其特征在于，所述芯片包括多条扫描测试链；所述芯片还包括：
    分路器，设置于所述发射电路和所述多条扫描测试链之间，用于将所述第一测试信号 功分成多路第一测试信号，分别提供至所述多条扫描测试链；
    合路器，设置于所述多条扫描测试链和所述接收电路之间，用于将所述多条扫描测试链输出的多路第二测试信号合成一路第二测试信号，提供至所述接收电路。
  9. 根据权利要求1-8任一项所述的芯片，其特征在于，所述芯片还包括：
    边界扫描测试链，所述边界扫描测试链包括多个边界扫描单元，所述多个边界扫描单元与所述接收电路的输出端和所述发射电路的输入端连接；
    所述多个边界扫描单元中的每一个边界扫描单元用于从所述接收电路接收第三测试信号，以及向所述发射电路输出第四测试信号。
  10. 一种芯片测试装置，其特征在于，包括测试设备以及如权利要求1-9任一项所述的芯片；
    所述芯片的输入端口和输出端口均与所述测试设备连接。
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