WO2023240728A1 - 可编程存储器及其驱动方法 - Google Patents

可编程存储器及其驱动方法 Download PDF

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Publication number
WO2023240728A1
WO2023240728A1 PCT/CN2022/105262 CN2022105262W WO2023240728A1 WO 2023240728 A1 WO2023240728 A1 WO 2023240728A1 CN 2022105262 W CN2022105262 W CN 2022105262W WO 2023240728 A1 WO2023240728 A1 WO 2023240728A1
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WIPO (PCT)
Prior art keywords
type transistor
voltage
pole
word line
signal
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PCT/CN2022/105262
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English (en)
French (fr)
Inventor
季汝敏
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长鑫存储技术有限公司
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Priority to US18/155,692 priority Critical patent/US20230402118A1/en
Publication of WO2023240728A1 publication Critical patent/WO2023240728A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory

Definitions

  • the present disclosure relates to the field of storage technology, and in particular, to a programmable memory and a driving method thereof.
  • a programmable memory generally includes a plurality of antifuse units distributed in an array.
  • the antifuse unit includes an antifuse and a switching transistor. The first end of the antifuse is connected to the first pole of the switching transistor.
  • antifuses have the risk of being misprogrammed, and switching transistors are easily broken down.
  • a programmable memory including: a plurality of anti-fuse units, a plurality of word lines, and a control circuit.
  • the plurality of anti-fuse units are distributed in an array along the row and column directions, and the anti-fuse units
  • the unit includes an antifuse and a switching transistor, the first end of the antifuse is connected to the first pole of the switching transistor; the word line is connected to the gates of the switching transistors located in the same row; the control circuit is connected
  • the word line is configured to provide a first voltage to the word line connected to the target anti-fuse unit in the programming mode, and to provide a third voltage to the word line connected to the target anti-fuse unit in the read mode. Two voltages; wherein the first voltage is greater than the second voltage.
  • the programmable memory further includes: a plurality of bit lines and a precharge circuit, the bit lines are connected to the second poles of the switching transistors located in the same column; the precharge circuit is connected to the plurality of bit lines.
  • the bit line is connected to provide a precharge voltage to the bit line in the programming mode.
  • the precharge circuit includes: a plurality of first switch units, the plurality of first switch units are arranged in one-to-one correspondence with the plurality of bit lines, and the first switch unit has a One end is connected to the corresponding bit line, the second end is used to receive the precharge voltage, the control end is connected to a precharge signal terminal, and the precharge signal terminal is used to output an effective level in the programming mode.
  • the programmable memory further includes: a column selection circuit, the column selection circuit is connected to the bit line, and is used to pull down the target antifuse unit according to the column selection signal in the programming mode. The voltage of the connected bit line.
  • the column selection circuit includes: a plurality of second switch units, the plurality of second switch units are arranged in one-to-one correspondence with the plurality of bit lines, and the third switch unit of the second switch unit One end is connected to the corresponding bit line, the second end is used to receive a low-level voltage, and the control end is used to receive the column selection signal.
  • the control circuit includes: a plurality of word line control circuits and a voltage adjustment circuit.
  • the plurality of word line control circuits are arranged in one-to-one correspondence with the plurality of word lines.
  • the line control circuit is used to transmit the power supply voltage to the word line connected to the target antifuse unit according to the word line address signal;
  • the voltage adjustment circuit is used to provide the power supply voltage to the word line control circuit, wherein, The power supply voltage is the first voltage in the programming mode, and the power supply voltage is the second voltage in the read mode.
  • the word line address signal includes a first address signal and a second address signal
  • the word line control circuit includes: a first N-type transistor, a second N-type transistor, a third N-type transistor, and a third N-type transistor. type transistor, a fourth P-type transistor, a fifth P-type transistor, and a sixth P-type transistor.
  • the first electrode of the first N-type transistor is connected to ground, and the gate of the first N-type transistor is used to receive the first address signal; the first electrode of the second N-type transistor is connected to the first N-type transistor.
  • the second pole of the second N-type transistor is connected to the first node, and the gate of the second N-type transistor is used to receive the second address signal;
  • the second pole of the third N-type transistor is One pole is connected to ground, the second pole of the third N-type transistor is connected to the word line, the gate of the third N-type transistor is connected to the first node; the first pole of the fourth P-type transistor is connected to the word line.
  • the second electrode of the fourth P-type transistor is connected to the word line, the gate electrode of the fourth P-type transistor is connected to the first node; the third electrode of the fifth P-type transistor is connected to the word line.
  • One pole is used to receive the power supply voltage
  • the second pole of the fifth P-type transistor is connected to the first node, and the gate of the fifth P-type transistor is used to receive the first address signal
  • the first pole of the sixth P-type transistor is used to receive the power supply voltage
  • the second pole of the sixth P-type transistor is connected to the first node
  • the gate of the sixth P-type transistor is used to receive the power supply voltage.
  • the first address signal is a row address signal
  • the second address signal is a sub-array address signal
  • the voltage adjustment circuit includes: a comparator, a seventh P-type transistor, a first variable resistor, a second variable resistor, and an adjustment circuit.
  • the inverting input terminal of the comparator For receiving the reference voltage, the non-inverting input terminal of the comparator is connected to the second node, and the output terminal of the comparator is connected to the third node; the first pole of the seventh P-type transistor is connected to the power supply terminal, and the first pole of the seventh P-type transistor is connected to the power supply terminal.
  • the second pole of the seventh P-type transistor is used to output the power supply voltage, the gate of the seventh P-type transistor is connected to the third node; the first variable resistor is connected to the second pole of the seventh P-type transistor. between the pole and the second node; a second variable resistor is connected between the second node and the ground terminal; the adjustment circuit is used to adjust the reference voltage, the first variable resistor or the at least one of the second variable resistors.
  • the voltage adjustment circuit includes: a control signal generation circuit and a voltage selection circuit.
  • the control signal generation circuit is used to output the first control signal or the second control signal according to the programming flag signal; the voltage selection circuit for receiving the first control signal or the second control signal, and for outputting the first voltage to the word line control circuit according to the first control signal, or for outputting the first voltage to the word line control circuit according to the second control signal A signal outputs the second voltage to the word line control circuit.
  • the control signal generation circuit includes: an eighth N-type transistor, an inverter, a ninth N-type transistor, a tenth N-type transistor, and an eleventh N-type transistor.
  • the first pole of the eight N-type transistors is connected to the low-level signal terminal, the gate of the eighth N-type transistor is used to receive the programming flag signal, and the second pole of the eighth N-type transistor is used to output the The first control signal;
  • the input end of the inverter is used to receive the programming flag signal;
  • the first electrode of the ninth N-type transistor is connected to the high-level signal end, and the gate electrode of the ninth N-type transistor Connected to the output end of the inverter, the second pole of the ninth N-type transistor is connected to the second pole of the eighth N-type transistor;
  • the first pole of the tenth N-type transistor is connected to the low voltage
  • the flat signal terminal the gate of the tenth N-type transistor is connected to the output terminal of the inverter, and the second pole of the ten
  • the voltage selection circuit includes: a twelfth P-type transistor and a thirteenth P-type transistor.
  • the first pole of the twelfth P-type transistor is used to receive the first voltage.
  • the twelfth P-type transistor The gate electrode of the eighth N-type transistor and the second electrode of the ninth N-type transistor are used to output the power supply voltage; the second electrode of the twelfth P-type transistor is used to output the power supply voltage;
  • the first pole of the thirteenth P-type transistor is used to receive the second voltage, and the gate of the thirteenth P-type transistor is connected to the second pole of the tenth N-type transistor and the eleventh N-type transistor.
  • the second pole of the thirteenth P-type transistor is used to output the power supply voltage.
  • a programmable memory driving method where the programmable memory includes:
  • a plurality of anti-fuse units are arranged in an array along the row and column directions.
  • the anti-fuse unit includes an anti-fuse and a switching transistor. The first end of the anti-fuse and the switching transistor are The first pole is connected;
  • word lines connecting the gates of the switching transistors located in the same row;
  • the driving method includes:
  • the first voltage is greater than the second voltage.
  • Figure 1 is a schematic structural diagram of an exemplary embodiment of the programmable memory of the present disclosure
  • Figure 2 is a schematic structural diagram of an antifuse array in an exemplary embodiment of the programmable memory of the present disclosure
  • Figure 3 is a schematic structural diagram of another exemplary embodiment of the programmable memory of the present disclosure.
  • Figure 4 is a schematic structural diagram of a word line control circuit in an exemplary embodiment of the programmable memory of the present disclosure
  • Figure 5 is a schematic structural diagram of a voltage adjustment circuit in an exemplary embodiment of the programmable memory of the present disclosure
  • Figure 6 is a schematic structural diagram of another exemplary voltage adjustment circuit in the programmable memory of the present disclosure.
  • Figure 7 is a timing diagram of each signal in Figure 6;
  • FIG. 8 is a schematic structural diagram of a voltage adjustment circuit in another exemplary embodiment of the programmable memory of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments. To those skilled in the art.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • the programmable memory may include an antifuse array 01 , a row decoder 02 , a column decoder 03 , a sensing circuit 04 , a logic circuit 05 , and a boost circuit 06 .
  • the row decoder 02 is used to latch and decode the row address information of the antifuse array 01; the column decoder 03 is used to latch and decode the column address information of the antifuse array 01; boosting Circuit 06 is used to generate high voltage to program the fuse; sensing circuit 04 is used to detect and judge the information stored in the fuse unit in read mode; logic circuit 05 is used to coordinate and control various operations, such as Switching control between different modes, addressing control of the anti-fuse unit, anti-fuse status reading control, enable control of the high-voltage circuit, etc.
  • the antifuse array may include multiple antifuse units Cell1, Cell2, Cell3, and Cell4. Multiple antifuse units Cell1, Cell2, Cell3, and Cell4 can be distributed in an array along the row and column directions.
  • Each antifuse unit may include an antifuse ATF and a switching transistor T, and a first end of the antifuse ATF is connected to a first pole of the switching transistor T.
  • the programmable memory may also include a plurality of bit lines BL1 and BL2, a plurality of word lines WL1 and WL2, a plurality of fuse lines FsBln1 and FsBln2, and a column selection circuit 2.
  • the switching transistor T may be an N-type transistor. It should be understood that in other exemplary embodiments, the switching transistor T may also be a P-type transistor.
  • one column of anti-fuse cells is provided with a bit line corresponding to it.
  • the second pole of the switching transistor T located in the same column of anti-fuse cells is connected to its corresponding bit line; one row of anti-fuse cells is provided with a corresponding word line.
  • the gate of the switching transistor T located in the same row of anti-fuse units is connected to its corresponding word line; a row of anti-fuse units is provided with a fuse line, and the second end of the anti-fuse ATF located in the same row of anti-fuse units is connected to its corresponding word line.
  • Corresponding fusible link it should be noted that in this exemplary embodiment, the number of anti-fuse units may be multiple. This exemplary embodiment only shows four anti-fuse units distributed in a two-by-two array.
  • the driving method of the programmable memory may include a programming mode and a reading mode.
  • the programming mode the antifuse in the target antifuse unit needs to be blown; in the read mode, the signal in the target antifuse unit needs to be read.
  • This exemplary embodiment uses the antifuse unit Cell3 as the target antifuse unit as an example to explain the programming mode and read mode of the programmable memory.
  • the word line WL2 is used to turn on the switching transistor T in the target anti-fuse cell Cell3.
  • the voltage of the word line WL2 can be 1.2-1.5V
  • the column selection circuit 2 is used according to the column selection signal.
  • the fuse line FsBln2 is used to input a high level signal to the second end of the anti-fuse ATF in the target anti-fuse unit Cell3.
  • the voltage of the fuse line FsBln2 can be 5V-6V.
  • the voltage of the fuse line FsBln2 can be 5V, 5.5 V, 6V, etc., thus causing a higher voltage difference across the antifuse ATF in the target antifuse unit Cell3.
  • the voltage difference across the antifuse ATF can reach 5V-6V.
  • the voltage across the antifuse ATF The difference can reach 5V, 5.5V, 6V.
  • the insulation layer between the two ends of the anti-fuse ATF is melted under the action of high voltage, thereby connecting the two ends of the anti-fuse ATF in the target anti-fuse unit Cell3.
  • the word line WL2 is used to turn on the switching transistor T in the target antifuse cell Cell3.
  • the voltage of the word line WL2 at this time can be the same as its voltage in the programming mode.
  • the fuse line FsBln2 is used to output a low voltage.
  • the column selection circuit 2 may include a plurality of second switch units T2, and the plurality of second switch units T2 may be provided in one-to-one correspondence with the plurality of bit lines.
  • the first terminal of the second switch unit T2 can be connected to its corresponding bit line
  • the second terminal of the second switch unit T2 can be connected to the low-level voltage terminal FaCom
  • the control terminal of the second switch unit T2 can be connected to the column selection signal terminal.
  • the control terminal of the second switch unit T2 corresponding to the bit line BL1 is connected to the column selection signal terminal CSL1
  • the control terminal of the second switch unit T2 corresponding to the bit line BL2 is connected to the column selection signal terminal CSL2.
  • the low-level voltage terminal FaCom can be used to output a low-level voltage
  • the column selection signal terminal can be used to output the above-mentioned column selection signal.
  • the effective level is the level that turns on the target circuit. For example, when the second switch unit T2 is an N-type transistor, the effective level is high level. When the second switch unit T2 is a P-type transistor, the effective level is Level is low level.
  • the programmable memory in this embodiment may further include a precharge circuit 1 .
  • the precharge circuit 1 may be connected to a plurality of bit lines BL1 and BL2, and the precharge circuit 1 may be used to provide a precharge voltage to the bit lines in the programming mode.
  • the precharge circuit 1 Before the column selection circuit 2 pulls down the voltage of the bit line BL1 connected to the target antifuse cell Cell3, the precharge circuit 1 can be used to provide a precharge voltage to all bit lines.
  • the precharge voltage can be a high level, for example, precharge The charging voltage is 2-3V. This setting can reduce the voltage across the antifuse ATF in the non-target antifuse cell (for example, Cell4) in programming mode, thereby reducing the risk of the non-target antifuse cell Cell4 being misprogrammed.
  • the precharge circuit 1 may include multiple first switch units T1 , and the multiple first switch units T1 may be arranged in one-to-one correspondence with multiple bit lines.
  • the first end is connected to its corresponding bit line
  • the second end of the first switch unit T1 is connected to the precharge voltage terminal PreDrain
  • the control end of the first switch unit T1 is connected to the precharge signal terminal PreGate.
  • the precharge voltage terminal PreDrain is used to output the above-mentioned precharge voltage
  • the precharge signal terminal PreGate can be used to output an effective level in the programming mode to turn on the first switch unit T1.
  • the first switching unit T1 may be an N-type transistor or a P-type transistor.
  • the precharge circuit 1 can also have other structures.
  • the precharge circuit 1 can only include a switch unit, the first end of the switch unit is connected to the precharge voltage terminal, and the The second end of the switch unit is connected to all bit lines, and the control end of the switch unit is connected to the precharge signal end.
  • the switching transistor T in this exemplary embodiment may be a thin gate oxide layer transistor.
  • a thin gate oxide layer transistor has a smaller breakdown voltage, in order to ensure the reliability of the programmable memory, this exemplary embodiment needs to reduce the turn-on voltage of the switching transistor T in the antifuse unit.
  • this exemplary embodiment provides another programmable memory, as shown in FIG. 3 , which is a schematic structural diagram of another exemplary embodiment of the programmable memory of the present disclosure.
  • the programmable memory shown in Figure 3 can also include: a control circuit 3.
  • the control circuit 3 can be connected to the word lines WL1 and WL2.
  • the control circuit 3 can be used to provide The word line connected to the target anti-fuse unit provides a first voltage, and is used to provide a second voltage to the word line connected to the target anti-fuse unit in the read mode; wherein the first voltage is greater than the the second voltage.
  • the control circuit 3 can utilize a larger first voltage to fully turn on the switching transistor T in the antifuse unit in the programming mode, and the precharge voltage on the bit line can be fully transmitted to the antifuse.
  • the first end of the ATF, this setting can reduce the voltage difference across the non-programmed target antifuse, thereby reducing the risk of the non-programmed target antifuse being misprogrammed; at the same time, the control circuit 3 can also utilize a smaller The second voltage turns on the switching transistor T in the antifuse unit, thereby reducing the risk of breakdown of the switching transistor.
  • the first voltage may be 2.5V-3V.
  • the first voltage may be 2.5V, 2.7V, 3V, etc.
  • the second voltage may be 1.2V-1.5V.
  • the second voltage may be 1.2V, 1.3V, 1.4V, 1.5V, etc.
  • the precharge voltage can be 2V-2.5V, for example, the precharge voltage can be 2V, 2.3V, 2.5V, etc.
  • the control circuit 3 may include: a plurality of word line control circuits 31, a voltage adjustment circuit 32, a plurality of the word line control circuits 31 and a plurality of the word lines.
  • WL1 and WL2 are set in one-to-one correspondence.
  • the word line control circuit 31 can be used to transmit the power voltage to the word line WL2 connected to the target anti-fuse unit Cell3 according to the word line address signal;
  • the voltage adjustment circuit 32 can be used to transmit the power supply voltage to the word line WL2 connected to the target anti-fuse unit Cell3.
  • the word line control circuit 31 provides the power supply voltage, wherein the power supply voltage is the first voltage in the programming mode and the power supply voltage is the second voltage in the read mode.
  • FIG. 4 it is a schematic structural diagram of a word line control circuit in an exemplary embodiment of the programmable memory of the present disclosure.
  • the word line control circuit includes: a first N-type transistor M1, a second N-type transistor M2, a third N-type transistor M3, a fourth P-type transistor M4, a fifth P-type transistor M5, and a sixth P-type transistor M6.
  • the first pole of the first N-type transistor M1 is connected to the low-level signal terminal VSS, the gate of the first N-type transistor M1 is connected to the first address signal terminal XADD; the first pole of the second N-type transistor M2 is connected to The second pole of the first N-type transistor M1 and the second pole of the second N-type transistor M2 are connected to the first node N1, and the gate of the second N-type transistor M2 is connected to the second address signal terminal XSEG;
  • the first pole of the third N-type transistor M3 is connected to the low-level signal terminal VSS, and the second pole of the third N-type transistor M3 is connected to the word line WL corresponding to the word line control circuit.
  • the gate of the transistor M3 is connected to the first node N1; the first electrode of the fourth P-type transistor M4 is connected to the power supply voltage terminal VFSWL, and the second electrode of the fourth P-type transistor M4 is connected to the word line WL.
  • the gate of the fourth P-type transistor M4 is connected to the first node N1; the first electrode of the fifth P-type transistor M5 is connected to the power supply voltage terminal VFSW, and the second electrode of the fifth P-type transistor M5 is connected to the The first node N1, the gate of the fifth P-type transistor M5 is connected to the first address signal terminal XADD; the first electrode of the sixth P-type transistor M6 is connected to the power supply voltage terminal VFSW, and the sixth P-type transistor M6 The second electrode of is connected to the first node N1, and the gate of the sixth P-type transistor M6 is connected to the second address signal terminal XSEG.
  • the word line address signal may include a first address signal and a second address signal
  • the first address signal terminal XADD is used to output the first address signal
  • the second address signal terminal XSEG is used to output the second address signal
  • the power supply voltage terminal VFSW Used to output the power supply voltage
  • the low-level signal terminal VSS can be the ground terminal.
  • the word line control circuit only inputs the power supply voltage to the corresponding word line WL through the power supply voltage terminal VFSW when both the first address signal and the second address signal are high level. It should be understood that in other exemplary embodiments, the word line control circuit may also have other structures. For example, the first pole of the fifth P-type transistor M5 and the first pole of the sixth P-type transistor M6 in FIG. 4 may also have other structures. Other high-level signal terminals can be connected.
  • the antifuse array may be divided into multiple subarrays, and each subarray may include multiple array-distributed antifuse units.
  • the second address signal may be a subarray address signal, that is, the second address signal may be used to represent the address of a certain subarray.
  • the first address signal may be a row address signal, that is, the first address signal may be used to characterize a certain row of antifuse units in the subarray.
  • the second address signal can be used to first define the sub-array, and then the first address signal can be used to determine a certain row of anti-fuse units in the sub-array. This setting can reduce the information content of the address signal itself, thereby improving the address The speed of signal transmission.
  • the voltage adjustment circuit may include: a comparator 321, a seventh P-type transistor M7, a first variable resistor R1, a second variable resistor R2, an adjustment circuit (not shown), an inverting input of the comparator 321 terminal is connected to the reference voltage terminal Vref, the non-inverting input terminal of the comparator 321 is connected to the second node N2, the output terminal of the comparator 321 is connected to the third node N3; the first stage of the seventh P-type transistor M7 is connected The power terminal VPP, the second pole of the seventh P-type transistor M7 can be used to connect to the power supply voltage terminal VFSW, the gate of the seventh P-type transistor M7 is connected to the third node N3; the first variable resistor R1 is connected between the second pole of the seventh P-type transistor M7 and the second node N2; the second variable resistor R2 is connected
  • the comparator 321 amplifies the voltage difference between its non-inverting input terminal and the inverting input terminal and then inputs it to the third node N3.
  • the third node N3 controls the output current of the seventh P-type transistor M7, Thereby, the power supply voltage is supplied to the power supply voltage terminal VFSW.
  • the voltages of the non-inverting input terminal and the inverting input terminal of the comparator 321 are the same in the steady state, that is, the voltage of the reference voltage terminal Vref and the voltage of the second node N2 are the same in the steady state, and the voltage of the power supply voltage terminal VFSW is the same.
  • the adjustment circuit can adjust the voltage of the power supply voltage terminal VFSW by adjusting at least one of the reference voltage, the first variable resistor, and the second variable resistor according to the programming flag signal.
  • the programming flag signal when the programmable memory enters the programming mode, the programming flag signal is high level, and the adjustment circuit can control the power supply voltage terminal VFSW to output the first voltage; when the programmable memory enters the read mode, the programming flag signal is low level, The adjustment circuit can control the power supply voltage terminal VFSW to output the second voltage.
  • the voltage adjustment circuit may also include a capacitor C.
  • the capacitor C is connected between the power supply voltage terminal VFSW and the ground terminal GND.
  • the capacitor C can compensate a left half-plane zero point for the system to Used to improve system stability.
  • the voltage adjustment circuit may also have other structures.
  • FIG. 6 it is a schematic structural diagram of another exemplary voltage adjustment circuit in the programmable memory of the present disclosure.
  • the voltage adjustment circuit may include: a control signal generation circuit 322 and a voltage selection circuit 323.
  • the control signal generation circuit 322 is used to output the first control signal CN1 or the second control signal CN2 according to the programming flag signal PGM;
  • the voltage selection circuit 323 is used to receive
  • the first control signal CN1 or the second control signal CN2 is used to output the first voltage to the word line control circuit 31 according to the first control signal CN1, or to output the first voltage to the word line control circuit 31 according to the second control signal CN1.
  • the control signal CN2 outputs the second voltage to the word line control circuit 31 .
  • the control signal generation circuit 322 may include: an eighth N-type transistor M8, an inverter PI, a ninth N-type transistor M9, a tenth N-type transistor M10, Eleven N-type transistor M11.
  • the first electrode of the eighth N-type transistor M8 is connected to the low-level signal terminal VSS.
  • the gate of the eighth N-type transistor M8 is used to receive the programming flag signal PGM.
  • the second pole of the eighth N-type transistor M8 is used to output the first control signal CN1; the input end of the inverter PI is used to receive the programming flag signal PGM; the ninth N-type transistor M9 One pole is connected to the high-level signal terminal VDD, the gate of the ninth N-type transistor M9 is connected to the output terminal of the inverter PI, and the second pole of the ninth N-type transistor M9 is connected to the eighth N
  • the second pole of the N-type transistor M8; the first pole of the tenth N-type transistor M10 is connected to the low-level signal terminal VSS, and the gate of the tenth N-type transistor M10 is connected to the output of the inverter PI terminal, the second pole of the tenth N-type transistor M10 is used to output the second control signal CN2; the first pole of the eleventh N-type transistor M11 is connected to the high-level signal terminal VDD, and the tenth N-type transistor M11 is connected to the high-level signal terminal VDD.
  • the gate of an N-type transistor M11 is used to receive the programming flag signal PGM, and the second electrode of the eleventh N-type transistor M11 is connected to the second electrode of the tenth N-type transistor M10.
  • the voltage selection circuit includes: a twelfth P-type transistor M12 and a thirteenth P-type transistor M13. The first pole of the twelfth P-type transistor M12 is used to receive the first voltage V1.
  • the gates of the two P-type transistors M12 are connected to the second pole of the eighth N-type transistor M8 and receive the first control signal CN1, and the second pole of the twelfth P-type transistor M12 is connected to the power supply voltage terminal VFSWL;
  • the first electrode of the thirteenth P-type transistor M13 is used to receive the second voltage V2, and the gate electrode of the thirteenth P-type transistor M13 is connected to the second electrode of the tenth N-type transistor M10.
  • the second pole of the thirteenth P-type transistor M13 is connected to the power supply voltage terminal VFSWL.
  • the power supply voltage terminal VFSWL is used to output the power supply voltage.
  • PGM is the timing diagram of the programming mark signal
  • CN1 is the timing diagram of the first control signal
  • CN2 is the timing diagram of the second control signal
  • VFSWL is the timing diagram of the power supply voltage.
  • the programming flag signal is high level.
  • the eighth N-type transistor M8 is turned on, the ninth N-type transistor M9 is turned off, the first control signal CN1 is low level, and the first control signal CN1
  • the twelfth P-type transistor M12 is turned on to transmit the first voltage of the first voltage terminal V1 to the power supply voltage terminal VFSWL; at the same time, the tenth N-type transistor M10 is turned off, and the eleventh N-type transistor M11 is turned on.
  • the second control signal CN2 is high level, the thirteenth P-type transistor M13 is turned off.
  • the programming flag signal is low level
  • the tenth N-type transistor M10 is turned on
  • the eleventh N-type transistor M11 is turned off
  • the second control signal is low level
  • the second control signal CN2 is turned on.
  • the thirteenth P-type transistor M13 is used to transmit the second voltage of the second voltage terminal V2 to the power supply voltage terminal VFSWL; at the same time, the eighth N-type transistor M8 is turned off, the ninth N-type transistor M9 is turned on, and the first control signal CN1 is high level, and the twelfth P-type transistor M12 is turned off.
  • the difference between the programming flag signal potential minus the high-level signal terminal VDD potential needs to be greater than the threshold voltages of the eighth N-type transistor M8 and the eleventh N-type transistor M11 at the same time.
  • the voltage of the high-level signal terminal VDD is greater than the first voltage and the second voltage.
  • FIG. 8 it is a schematic structural diagram of a voltage adjustment circuit in another exemplary embodiment of the programmable memory of the present disclosure.
  • the voltage adjustment circuit may also include: a control signal generation circuit 322 and a voltage selection circuit 323.
  • the control signal generation circuit 322 may include a fourteenth P-type transistor M14 and a fifteenth N-type transistor M15.
  • the first electrode of the fourteenth P-type transistor M14 is connected to the high-level signal terminal VDD.
  • the second electrode is connected to the fourth node N4, and the gate of the fourteenth P-type transistor M14 is used to receive the programming flag signal PGM; the first electrode of the fifteenth N-type transistor M15 is connected to the low-level signal terminal VSS, and the fifteenth N-type transistor M15 is connected to the low-level signal terminal VSS.
  • the second electrode of the N-type transistor M15 is connected to the fourth node N4, and the gate electrode of the fifteenth N-type transistor M15 is used to receive the programming flag signal.
  • the voltage selection circuit 323 may include a sixteenth P-type transistor M16 and a seventeenth N-type transistor M17.
  • the first electrode of the sixteenth P-type transistor M16 is connected to the first voltage terminal V1, and the second electrode of the sixteenth P-type transistor M16 is connected to the first voltage terminal V1.
  • the gate electrode of the sixteenth P-type transistor M16 is connected to the fourth node N4; the first electrode of the seventeenth N-type transistor M17 is connected to the second voltage terminal V2, and the gate electrode of the seventeenth N-type transistor M17 is connected to the second voltage terminal V2.
  • the two electrodes are connected to the power supply voltage terminal VFSWL, and the gate of the seventeenth N-type transistor M17 is connected to the fourth node N4.
  • the programming flag signal is high level, the fifteenth N-type transistor M15 is turned on, the fourth node N4 is low level, the sixteenth P-type transistor M16 is turned on, and the first voltage terminal V1 is turned on to the power supply voltage.
  • the terminal VFSWL inputs the first voltage.
  • the programming flag signal is low level, the fourteenth P-type transistor M14 is turned on, the fourth node N4 is high level, the seventeenth N-type transistor M17 is turned on, and the second voltage terminal V2 is turned on to the power supply.
  • the voltage terminal VFSWL inputs the second voltage.
  • the voltage of the high-level signal terminal VDD minus the voltage of the second voltage terminal V2 may be greater than the threshold voltage of the seventeenth N-type transistor M17, so that the seventeenth N-type transistor M17 M17 is fully turned on in the read mode; the voltage of the high-level signal terminal VDD can be greater than or equal to the voltage of the first voltage terminal V1, so that the sixteenth P-type transistor is completely turned off in the read mode.
  • This exemplary embodiment also provides a programmable memory driving method, where the programmable memory includes:
  • a plurality of anti-fuse units are arranged in an array along the row and column directions.
  • the anti-fuse unit includes an anti-fuse and a switching transistor. The first end of the anti-fuse and the switching transistor are The first pole is connected;
  • word lines connecting the gates of the switching transistors located in the same row;
  • the driving method includes:
  • the first voltage is greater than the second voltage.

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Abstract

本发明涉及存储技术领域，提出一种可编程存储器及其驱动方法，可编程存储器包括：多个反熔丝单元、多条字线、控制电路，多个所述反熔丝单元沿行列方向阵列分布，所述反熔丝单元包括反熔丝和开关晶体管，所述反熔丝的第一端和所述开关晶体管的第一极相连接；所述字线连接位于同一行的所述开关晶体管的栅极；控制电路连接所述字线，用于在编程模式下向目标反熔丝单元连接的所述字线提供第一电压，以及用于在读取模式下向目标反熔丝单元连接的所述字线提供第二电压；其中，所述第一电压大于所述第二电压。该可编程存储器即可以避免反熔丝误编程，同时可以降低开关晶体管被击穿的风险。 (图3)

Description

可编程存储器及其驱动方法
相关申请的交叉引用
本申请要求于2022年06月14日递交的、名称为《可编程存储器及其驱动方法》的中国专利申请第202210674391.X号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及存储技术领域，尤其涉及一种可编程存储器及其驱动方法。
背景技术
相关技术中，可编程存储器一般包括多个阵列分布的反熔丝单元，反熔丝单元包括反熔丝和开关晶体管，反熔丝的第一端和开关晶体管的第一极相连接。相关技术中，反熔丝具有被误编程的风险，且开关晶体管容易被击穿。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
根据本公开的一个方面，提供一种可编程存储器，包括：多个反熔丝单元、多条字线、控制电路，多个所述反熔丝单元沿行列方向阵列分布，所述反熔丝单元包括反熔丝和开关晶体管，所述反熔丝的第一端和所述开关晶体管的第一极相连接；所述字线连接位于同一行的所述开关晶体管的栅极；控制电路连接所述字线，用于在编程模式下向目标反熔丝单元连接的所述字线提供第一电压，以及用于在读取模式下向目标反熔丝单元连接的所述字线提供第二电压；其中，所述第一电压大于所述第二电压。
本公开一种示例性实施例中，所述可编程存储器还包括：多条位线、预充电电路，所述位线连接位于同一列的所述开关晶体管的第二极；预充电电路与多条所述位线连接，用于在编程模式下向所述位线提供预充电电压。
本公开一种示例性实施例中，所述预充电电路包括：多个第一开关单元，多个第一开关单元与多条所述位线一一对应设置，所述第一开关单元的第一端连接与其对应的所述位线，第二端用于接收所述预充电电压，控制端连接预充信号端，所述预充信号端用于在编程模式下输出有效电平。
本公开一种示例性实施例中，所述可编程存储器还包括：列选择电路，列选择电路连接所述位线，用于在编程模式下根据列选择信号拉低所述目标反熔丝单元所连接 的所述位线的电压。
本公开一种示例性实施例中，所述列选择电路包括：多个第二开关单元，多个第二开关单元与多条所述位线一一对应设置，所述第二开关单元的第一端连接与其对应的所述位线，第二端用于接收低电平电压，控制端用于接收所述列选择信号。
本公开一种示例性实施例中，所述控制电路包括：多个字线控制电路、电压调节电路，多个所述字线控制电路与多条所述字线一一对应设置，所述字线控制电路用于根据字线地址信号将电源电压传输到所述目标反熔丝单元连接的所述字线；电压调节电路用于向所述字线控制电路提供所述电源电压，其中，在所述编程模式下所述电源电压为所述第一电压，在所述读取模式下所述电源电压为所述第二电压。
本公开一种示例性实施例中，所述字线地址信号包括第一地址信号和第二地址信号，所述字线控制电路包括：第一N型晶体管、第二N型晶体管、第三N型晶体管、第四P型晶体管、第五P型晶体管、第六P型晶体管。所述第一N型晶体管的第一极接地，第一N型晶体管的栅极用于接收所述第一地址信号；所述第二N型晶体管的第一极连接所述第一N型晶体管的第二极，所述第二N型晶体管的第二极连接第一节点，所述第二N型晶体管的栅极用于接收所述第二地址信号；所述第三N型晶体管的第一极接地，所述第三N型晶体管的第二极连接所述字线，所述第三N型晶体管的栅极连接所述第一节点；所述第四P型晶体管的第一极用于接收所述电源电压，所述第四P型晶体管的第二极连接所述字线，所述第四P型晶体管的栅极连接所述第一节点；所述第五P型晶体管的第一极用于接收所述电源电压，所述第五P型晶体管的第二极连接所述第一节点，所述第五P型晶体管的栅极用于接收所述第一地址信号；所述第六P型晶体管的第一极用于接收所述电源电压，所述第六P型晶体管的第二极连接所述第一节点，所述第六P型晶体管的栅极用于接收所述第二地址信号。
本公开一种示例性实施例中，所述第一地址信号为行地址信号，所述第二地址信号为子阵列地址信号。
本公开一种示例性实施例中，所述电压调节电路包括：比较器、第七P型晶体管、第一可变电阻、第二可变电阻、调整电路，所述比较器的反相输入端用于接收参考电压，所述比较器的正相输入端连接第二节点，所述比较器的输出端连接第三节点；所述第七P型晶体管的第一极连接电源端，所述第七P型晶体管的第二极用于输出所述电源电压，所述第七P型晶体管的栅极连接所述第三节点；第一可变电阻连接于所述第七P型晶体管的第二极和所述第二节点之间；第二可变电阻连接于所述第二节点和接地端之间；调整电路用于根据编程标志信号调整所述参考电压、所述第一可变电阻或所述第二可变电阻中的至少一个。
本公开一种示例性实施例中，所述电压调节电路包括：控制信号生成电路、电压选择电路，控制信号生成电路用于根据编程标志信号输出第一控制信号或第二控制信号；电压选择电路用于接收所述第一控制信号或所述第二控制信号，且用于根据所述 第一控制信号输出所述第一电压至所述字线控制电路，或用于根据所述第二控制信号输出所述第二电压至所述字线控制电路。
本公开一种示例性实施例中，所述控制信号生成电路包括：第八N型晶体管、反相器、第九N型晶体管、第十N型晶体管、第十一N型晶体管，所述第八N型晶体管的第一极连接低电平信号端，所述第八N型晶体管的栅极用于接收所述编程标志信号，所述第八N型晶体管的第二极用于输出所述第一控制信号；所述反相器的输入端用于接收所述编程标志信号；所述第九N型晶体管的第一极连接高电平信号端，所述第九N型晶体管的栅极连接所述反相器的输出端，所述第九N型晶体管的第二极连接所述第八N型晶体管的第二极；所述第十N型晶体管的第一极连接所述低电平信号端，所述第十N型晶体管的栅极连接所述反相器的输出端，所述第十N型晶体管的第二极用于输出所述第二控制信号；所述第十一N型晶体管的第一极连接高电平信号端，所述第十一N型晶体管的栅极用于接收所述编程标志信号，所述第十一N型晶体管的第二极连接所述第十N型晶体管的第二极。所述电压选择电路包括：第十二P型晶体管、第十三P型晶体管，所述第十二P型晶体管的第一极用于接收所述第一电压，所述第十二P型晶体管的栅极所述第八N型晶体管的第二极和所述第九N型晶体管的第二极，所述第十二P型晶体管的第二极用于输出所述电源电压；所述第十三P型晶体管的第一极用于接收所述第二电压，所述第十三P型晶体管的栅极连接所述第十N型晶体管的第二极和所述第十一N型晶体管的第二极，所述第十三P型晶体管的第二极用于输出所述电源电压。
根据本公开的一个方面，提供一种可编程存储器驱动方法，所述可编程存储器包括：
多个反熔丝单元，多个所述反熔丝单元沿行列方向阵列分布，所述反熔丝单元包括反熔丝和开关晶体管，所述反熔丝的第一端和所述开关晶体管的第一极相连接；
多条字线，所述字线连接位于同一行的所述开关晶体管的栅极；
所述驱动方法包括：
在编程模式下，向目标反熔丝单元连接的所述字线提供第一电压；
在读取模式下，向目标反熔丝单元连接的所述字线提供第二电压；
其中，所述第一电压大于所述第二电压。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的 前提下，还可以根据这些附图获得其他的附图。
图1为本公开可编程存储器一种示例性实施例的结构示意图；
图2为本公开可编程存储器一种示例性实施例中反熔丝阵列的结构示意图；
图3为本公开可编程存储器另一种示例性实施例的结构示意图；
图4为本公开可编程存储器一种示例性实施例中字线控制电路的结构示意图；
图5为本公开可编程存储器一种示例性实施例中电压调节电路的结构示意图；
图6为本公开可编程存储器另一种示例性中电压调节电路的结构示意图；
图7为图6中各信号的时序图；
图8为本公开可编程存储器另一种示例性实施例中电压调节电路的结构示意图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
如图1所示，为本公开可编程存储器一种示例性实施例的结构示意图。该可编程存储器可以包括反熔丝阵列01、行译码器02、列译码器03、感测电路04、逻辑电路05、升压电路06。行译码器02用于对反熔丝阵列01的行地址信息进行锁存和译码；列译码器03用于对反熔丝阵列01的列地址信息进行锁存和译码；升压电路06用于产生高压以对熔丝进行编程；感测电路04用于在读取模式下对熔丝单元存储的信息进行检测和判断；逻辑电路05用于对各种操作进行协调控制，例如不同的模式之间的切换控制，反熔丝单元的寻址控制，反熔丝状态读取控制，高压电路的使能控制等。
如图2所示，为本公开可编程存储器一种示例性实施例中反熔丝阵列的结构示意图。如图2所示，反熔丝阵列可以包括多个反熔丝单元Cell1、Cell2、Cell3、Cell4。多个反熔丝单元Cell1、Cell2、Cell3、Cell4可以沿行列方向阵列分布。每个反熔丝单元可以包括反熔丝ATF和开关晶体管T，反熔丝ATF的第一端和开关晶体管T的第一极相连接。该可编程存储器还可以包括多条位线BL1、BL2、多条字线WL1、WL2、多条熔断线FsBln1、FsBln2、列选择电路2。开关晶体管T可以为N型晶体管。应该理解的是，在其他示例性实施例中，开关晶体管T也可以为P型晶体管。
如图2所示，一列反熔丝单元对应设置一条位线，位于同一列反熔丝单元中开关晶体管T的第二极连接与其对应的位线；一行反熔丝单元对应设置一条字线，位于同一行反熔丝单元中开关晶体管T的栅极连接与其对应的字线；一行反熔丝单元对应设 置一条熔断线，位于同一行反熔丝单元中反熔丝ATF的第二端连接与其对应的熔断线。需要说明的是，本示例性实施例中，反熔丝单元的个数可以为多个，本示例性实施例仅示出了二乘二阵列分布的四个反熔丝单元。
本示例性实施例中，该可编程存储器的驱动方法可以包括编程模式和读取模式。在编程模式下，需要将目标反熔丝单元中的反熔丝熔断；在读取模式下，需要读取目标反熔丝单元中的信号。本示例性实施例以反熔丝单元Cell3为目标反熔丝单元为例，对可编程存储器的编程模式和读取模式进行说明。
如图2所示，在编程模式下，利用字线WL2导通目标反熔丝单元Cell3中的开关晶体管T，字线WL2的电压可以为1.2-1.5V，利用列选择电路2根据列选择信号拉低目标反熔丝单元Cell3所连接的位线BL1的电压。此外利用熔断线FsBln2向目标反熔丝单元Cell3中反熔丝ATF的第二端输入高电平信号，熔断线FsBln2的电压可以为5V-6V，例如，熔断线FsBln2的电压可以为5V、5.5V、6V等，从而使得目标反熔丝单元Cell3中反熔丝ATF两端形成较高的电压差，反熔丝ATF两端的电压差可以达到5V-6V，例如，反熔丝ATF两端的电压差可以达到5V、5.5V、6V。反熔丝ATF两端之间的绝缘层在高压作用下被熔断，从而使得目标反熔丝单元Cell3中反熔丝ATF的两端连通。在读取模式下，利用字线WL2导通目标反熔丝单元Cell3中的开关晶体管T，字线WL2此时的电压可以和其在编程模式下的电压相同，同时利用熔断线FsBln2输出低电平信号，通过检测位线BL1上的信号可以判断目标反熔丝单元Cell3中的反熔丝ATF是否被熔断。
本示例性实施例中，列选择电路2可以包括多个第二开关单元T2，多个第二开关单元T2可以与多条位线一一对应设置。第二开关单元T2的第一端可以连接与其对应的位线，第二开关单元T2的第二端可以连接低电平电压端FaCom，第二开关单元T2的控制端可以连接列选择信号端，例如，与位线BL1对应的第二开关单元T2的控制端连接列选择信号端CSL1，与位线BL2对应的第二开关单元T2的控制端连接列选择信号端CSL2。低电平电压端FaCom可以用于输出低电平电压，列选择信号端可以用于输出上述的列选择信号。其中，有效电平为导通目标电路的电平，例如，当第二开关单元T2为N型晶体管时，有效电平为高电平，当第二开关单元T2为P型晶体管时，有效电平为低电平。
本示例性实施例中，为了使得非目标反熔丝单元Cell4在编程模式下不会被误编程，如图2所示，本实施例实施例中的可编程存储器还可以包括预充电电路1。预充电电路1可以与多条位线BL1、BL2连接，预充电电路1可以用于在编程模式下向所述位线提供预充电电压。在列选择电路2拉低目标反熔丝单元Cell3所连接的位线BL1的电压前，可以利用预充电电路1向所有位线提供预充电电压，预充电电压可以为高电平，例如，预充电电压为可以2-3V。该设置可以降低编程模式下非目标反熔丝单元(例如，Cell4)中反熔丝ATF两端的电压，从而降低了非目标反熔丝单元Cell4被误 编程的风险。
本示例性实施例中，如图2所示，预充电电路1可以包括多第一开关单元T1，多个第一开关单元T1可以与多条位线一一对应设置，第一开关单元T1的第一端连接与其对应的位线，第一开关单元T1的第二端连接预充电电压端PreDrain，第一开关单元T1的控制端连接预充信号端PreGate。预充电电压端PreDrain用于输出上述预充电电压，预充信号端PreGate可以用于在编程模式下输出有效电平，以导通第一开关单元T1。第一开关单元T1可以为N型晶体管或P型晶体管。应该理解的是，在其他示例性实施例中，预充电电路1还可以为其他结构，例如，预充电电路1可以仅包括一个开关单元，该开关单元的第一端连接预充电电压端，该开关单元的第二端连接所有的位线，该开关单元的控制端连接预充信号端。
为了缩小反熔丝单元的面积，降低芯片制造成本，本示例性实施例中的开关晶体管T可以为薄的栅氧化层晶体管。然而，由于薄的栅氧化层晶体管具有较小的击穿电压，为了保证可编程存储器的可靠性，本示例性实施例需要降低反熔丝单元中开关晶体管T的开启电压。然而，降低反熔丝单元中开关晶体管T的开启电压会造成开关晶体管T导通不彻底，位线上的电压无法完全传输到反熔丝ATF的第一端，从而使得非目标反熔丝单元中反熔丝两端的电压差较大，最终导致非目标反熔丝单元被误编程。
基于此，本示例性实施例提供另一种可编程存储器，如图3所示，为本公开可编程存储器另一种示例性实施例的结构示意图。相较于图2所示可编程存储器，图3所示可编程存储器还可以包括：控制电路3，控制电路3可以连接所述字线WL1、WL2，控制电路3可以用于在编程模式下向目标反熔丝单元连接的所述字线提供第一电压，以及用于在读取模式下向目标反熔丝单元连接的所述字线提供第二电压；其中，所述第一电压大于所述第二电压。
本示例性实施例中，控制电路3可以在编程模式下利用较大的第一电压较充分的导通反熔丝单元中开关晶体管T，位线上的预充电电压可以充分传输到反熔丝ATF的第一端，该设置可以降低非编程目标反熔丝两端的电压差，从而降低非编程目标反熔丝被误编程的风险；同时，控制电路3还可以在读取模式下利用较小的第二电压导通反熔丝单元中开关晶体管T，从而降低开关晶体管被击穿的风险。
本示例性实施例中，第一电压可以为2.5V-3V，例如，第一电压可以为2.5V、2.7V、3V等。第二电压可以为1.2V-1.5V，例如，第二电压可以为1.2V、1.3V、1.4V、1.5V等。预充电电压可以为2V-2.5V，例如，预充电电压可以为2V、2.3V、2.5V等。
本示例性实施例中，如图3所示，所述控制电路3可以包括：多个字线控制电路31、电压调节电路32，多个所述字线控制电路31与多条所述字线WL1、WL2一一对应设置，所述字线控制电路31可以用于根据字线地址信号将电源电压传输到所述目标反熔丝单元Cell3连接的字线WL2；电压调节电路32可以用于向所述字线控制电路31提供所述电源电压，其中，在所述编程模式下所述电源电压为所述第一电压，在所述 读取模式下所述电源电压为所述第二电压。
如图4所示，为本公开可编程存储器一种示例性实施例中字线控制电路的结构示意图。所述字线控制电路包括：第一N型晶体管M1、第二N型晶体管M2、第三N型晶体管M3、第四P型晶体管M4、第五P型晶体管M5、第六P型晶体管M6。所述第一N型晶体管M1的第一极连接低电平信号端VSS，第一N型晶体管M1的栅极连接第一地址信号端XADD；所述第二N型晶体管M2的第一极连接所述第一N型晶体管M1的第二极，所述第二N型晶体管M2的第二极连接第一节点N1，所述第二N型晶体管M2的栅极连接第二地址信号端XSEG；所述第三N型晶体管M3的第一极连接低电平信号端VSS，所述第三N型晶体管M3的第二极连接该字线控制电路对应的字线WL，所述第三N型晶体管M3的栅极连接所述第一节点N1；所述第四P型晶体管M4的第一极连接电源电压端VFSWL，所述第四P型晶体管M4的第二极连接字线WL，所述第四P型晶体管M4的栅极连接所述第一节点N1；所述第五P型晶体管M5的第一极连接电源电压端VFSW，所述第五P型晶体管M5的第二极连接所述第一节点N1，所述第五P型晶体管M5的栅极连接第一地址信号端XADD；所述第六P型晶体管M6的第一极连接电源电压端VFSW，所述第六P型晶体管M6的第二极连接所述第一节点N1，所述第六P型晶体管M6的栅极连接第二地址信号端XSEG。
其中，字线地址信号可以包括第一地址信号和第二地址信号，第一地址信号端XADD用于输出第一地址信号，第二地址信号端XSEG用于输出第二地址信号，电源电压端VFSW用于输出电源电压，低电平信号端VSS可以是接地端。
该字线控制电路仅在第一地址信号和第二地址信号均为高电平时，通过电源电压端VFSW向对其对应的字线WL输入电源电压。应该理解的是，在其他示例性实施例中，字线控制电路还可以为其他结构，例如，图4中第五P型晶体管M5的第一极、第六P型晶体管M6的第一极还可以连接其他高电平信号端。
本示例性实施例中，可以将反熔丝阵列划分为多个子阵列，每个子阵列可以包括多个阵列分布的反熔丝单元。本示例性实施例中，所述第二地址信号可以为子阵列地址信号，即第二地址信号可以用于表征某一子阵列的地址。所述第一地址信号可以为行地址信号，即第一地址信号可以用于表征子阵列中的某一行反熔丝单元。本示例性实施例可以先通过第二地址信号限定子阵列，再通过第一地址信号确定该子阵列中的某一行反熔丝单元，该设置可以降低地址信号自身的信息量，从而可以提高地址信号的传输速度。
如图5所示，为本公开可编程存储器一种示例性实施例中电压调节电路的结构示意图。所述电压调节电路可以包括：比较器321、第七P型晶体管M7、第一可变电阻R1、第二可变电阻R2、调整电路(未画出)，所述比较器321的反相输入端连接参考电压端Vref，所述比较器321的正相输入端连接第二节点N2，所述比较器321的输出端连接第三节点N3；所述第七P型晶体管M7的第一级连接电源端VPP，所述第七P 型晶体管M7的第二极可以用于连接电源电压端VFSW，所述第七P型晶体管M7的栅极连接所述第三节点N3；第一可变电阻R1连接于所述第七P型晶体管M7的第二极和所述第二节点N2之间；第二可变电阻R2连接于所述第二节点N2和接地端GND之间；调整电路可以用于根据编程标志信号调整所述参考电压端的参考电压、所述第一可变电阻、所述第二可变电阻中的至少一个。
在该电压调节电路中，比较器321将其正相输入端和反相输入端之间的电压差进行放大后输入到第三节点N3，第三节点N3控制第七P型晶体管M7输出电流，从而向电源电压端VFSW提供电源电压。根据虚短的原理，比较器321在稳态下其正相输入端和反相输入端的电压相同，即稳态下参考电压端Vref的电压和第二节点N2的电压相同，电源电压端VFSW的电源电压Vf＝(R1+R2)Vref/R2，其中，R1为第一可变电阻R1的电阻，R2为第二可变电阻R2的电阻，Vref为参考电压端Vref的电压。从而本示例性实施例中调整电路可以根据编程标志信号通过调整参考电压、第一可变电阻、所述第二可变电阻中的至少一个来调节电源电压端VFSW的电压。例如，当可编程存储器进入编程模式时，编程标志信号为高电平，调整电路可以控制电源电压端VFSW输出第一电压；当可编程存储器进入读取模式时，编程标志信号为低电平，调整电路可以控制电源电压端VFSW输出第二电压。
本示例性实施例中，如图5所示，电压调节电路还可以包括电容C，电容C连接于电源电压端VFSW和接地端GND之间，电容C可以为系统补偿一个左半平面零点，以用于提高系统的稳定性。
应该理解的是，在其他示例性实施例中，电压调节电路还可以为其他结构。例如，如图6所示，为本公开可编程存储器另一种示例性中电压调节电路的结构示意图。该电压调节电路可以包括：控制信号生成电路322、电压选择电路323，控制信号生成电路322用于根据编程标志信号PGM输出第一控制信号CN1或第二控制信号CN2；电压选择电路323用于接收所述第一控制信号CN1或所述第二控制信号CN2，且用于根据所述第一控制信号CN1输出所述第一电压至所述字线控制电路31，或用于根据所述第二控制信号CN2输出所述第二电压至所述字线控制电路31。
本示例性实施例中，如图6所示，所述控制信号生成电路322可以包括：第八N型晶体管M8、反相器PI、第九N型晶体管M9、第十N型晶体管M10、第十一N型晶体管M11，所述第八N型晶体管M8的第一极连接低电平信号端VSS，所述第八N型晶体管M8的栅极用于接收所述编程标志信号PGM，所述第八N型晶体管M8的第二极用于输出所述第一控制信号CN1；所述反相器PI的输入端用于接收所述编程标志信号PGM；所述第九N型晶体管M9的第一极连接高电平信号端VDD，所述第九N型晶体管M9的栅极连接所述反相器PI的输出端，所述第九N型晶体管M9的第二极连接所述第八N型晶体管M8的第二极；所述第十N型晶体管M10的第一极连接所述低电平信号端VSS，所述第十N型晶体管M10的栅极连接所述反相器PI的输出端，所述第十N型晶体管 M10的第二极用于输出所述第二控制信号CN2；所述第十一N型晶体管M11的第一极连接高电平信号端VDD，所述第十一N型晶体管M11的栅极用于接收所述编程标志信号PGM，所述第十一N型晶体管M11的第二极连接所述第十N型晶体管M10的第二极。所述电压选择电路包括：第十二P型晶体管M12、第十三P型晶体管M13，所述第十二P型晶体管M12的第一极用于接收所述第一电压V1，所述第十二P型晶体管M12的栅极连接所述第八N型晶体管M8的第二极并接收所述第一控制信号CN1，所述第十二P型晶体管M12的第二极连接电源电压端VFSWL；所述第十三P型晶体管M13的第一极用于接收所述第二电压V2，所述第十三P型晶体管M13的栅极连接连接所述第十N型晶体管M10的第二极并接收所述第二控制信号CN2，所述第十三P型晶体管M13的第二极连接电源电压端VFSWL。电源电压端VFSWL用于输出电源电压。
如图7所示，为图6中各信号的时序图。PGM为编程标志信号的时序图，CN1为第一控制信号的时序图，CN2为第二控制信号的时序图，VFSWL为电源电压的时序图。在编程模式阶段t1，编程标志信号为高电平，此时，第八N型晶体管M8导通，第九N型晶体管M9关断，第一控制信号CN1为低电平，第一控制信号CN1导通第十二P型晶体管M12，以将第一电压端V1的第一电压传输到电源电压端VFSWL；同时，第十N型晶体管M10关断，第十一N型晶体管M11导通，此时第二控制信号CN2为高电平，第十三P型晶体管M13关断。在读取模式阶段t2，编程标志信号为低电平，第十N型晶体管M10导通，第十一N型晶体管M11关断，第二控制信号为低电平，第二控制信号CN2导通第十三P型晶体管M13，以将第二电压端V2的第二电压传输到电源电压端VFSWL；同时，第八N型晶体管M8关断，第九N型晶体管M9导通，第一控制信号CN1为高电平，第十二P型晶体管M12关断。需要说明的是，当编程标志信号为高电平时，编程标志信号电位减去高电平信号端VDD电位的差需要同时大于第八N型晶体管M8、第十一N型晶体管M11的阈值电压，且高电平信号端VDD的电压大于第一电压、第二电压。
如图8所示，为本公开可编程存储器另一种示例性实施例中电压调节电路的结构示意图。该电压调节电路同样可以包括：控制信号生成电路322、电压选择电路323。控制信号生成电路322可以包括第十四P型晶体管M14、第十五N型晶体管M15，第十四P型晶体管M14的第一极连接高电平信号端VDD，第十四P型晶体管M14的第二极连接第四节点N4，第十四P型晶体管M14的栅极用于接收编程标志信号PGM；第十五N型晶体管M15的第一极连接低电平信号端VSS，第十五N型晶体管M15的第二极连接第四节点N4，第十五N型晶体管M15的栅极用于接收编程标志信号。电压选择电路323可以包括第十六P型晶体管M16、第十七N型晶体管M17，第十六P型晶体管M16的第一极连接第一电压端V1，第十六P型晶体管M16的第二极连接电源电压端VFSWL，第十六P型晶体管M16的栅极连接第四节点N4；第十七N型晶体管M17的第一极连接第二电压端V2，第十七N型晶体管M17的第二极连接电源电压端VFSWL，第十七N型晶 体管M17的栅极连接第四节点N4。在编程模式下，编程标志信号为高电平，第十五N型晶体管M15导通，第四节点N4为低电平，第十六P型晶体管M16导通，第一电压端V1向电源电压端VFSWL输入第一电压。在读取模式下，编程标志信号为低电平，第十四P型晶体管M14导通，第四节点N4为高电平，第十七N型晶体管M17导通，第二电压端V2向电源电压端VFSWL输入第二电压。需要说明的是，本示例性实施例中，高电平信号端VDD的电压减去第二电压端V2的电压可以大于第十七N型晶体管M17的阈值电压，以使得第十七N型晶体管M17在读取模式下充分导通；高电平信号端VDD的电压可以大于等于第一电压端V1的电压，以使得第十六P型晶体管在读取模式下彻底关断。
本示例性实施例还提供一种可编程存储器驱动方法，所述可编程存储器包括：
多个反熔丝单元，多个所述反熔丝单元沿行列方向阵列分布，所述反熔丝单元包括反熔丝和开关晶体管，所述反熔丝的第一端和所述开关晶体管的第一极相连接；
多条字线，所述字线连接位于同一行的所述开关晶体管的栅极；
所述驱动方法包括：
在编程模式下，向目标反熔丝单元连接的所述字线提供第一电压；
在读取模式下，向目标反熔丝单元连接的所述字线提供第二电压；
其中，所述第一电压大于所述第二电压。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (12)

  1. 一种可编程存储器，其中，包括：
    多个反熔丝单元，多个所述反熔丝单元沿行列方向阵列分布，所述反熔丝单元包括反熔丝和开关晶体管，所述反熔丝的第一端和所述开关晶体管的第一极相连接；
    多条字线，所述字线连接位于同一行的所述开关晶体管的栅极；
    控制电路，连接所述字线，用于在编程模式下向目标反熔丝单元连接的所述字线提供第一电压，以及用于在读取模式下向目标反熔丝单元连接的所述字线提供第二电压；
    其中，所述第一电压大于所述第二电压。
  2. 根据权利要求1所述的可编程存储器，其中，所述可编程存储器还包括：
    多条位线，所述位线连接位于同一列的所述开关晶体管的第二极；
    预充电电路，与多条所述位线连接，用于在编程模式下向所述位线提供预充电电压。
  3. 根据权利要求2所述的可编程存储器，其中，所述预充电电路包括：
    多个第一开关单元，与多条所述位线一一对应设置，所述第一开关单元的第一端连接与其对应的所述位线，第二端用于接收所述预充电电压，控制端连接预充信号端，所述预充信号端用于在编程模式下输出有效电平。
  4. 根据权利要求2所述的可编程存储器，其中，所述可编程存储器还包括：
    列选择电路，连接所述位线，用于在编程模式下根据列选择信号拉低所述目标反熔丝单元所连接的所述位线的电压。
  5. 根据权利要求4所述的可编程存储器，其中，所述列选择电路包括：
    多个第二开关单元，与多条所述位线一一对应设置，所述第二开关单元的第一端连接与其对应的所述位线，第二端用于接收低电平电压，控制端用于接收所述列选择信号。
  6. 根据权利要求1所述的可编程存储器，其中，所述控制电路包括：
    多个字线控制电路，多个所述字线控制电路与多条所述字线一一对应设置，所述字线控制电路用于根据字线地址信号将电源电压传输到所述目标反熔丝单元连接的所述字线；
    电压调节电路，用于向所述字线控制电路提供所述电源电压，其中，在所述编程模式下所述电源电压为所述第一电压，在所述读取模式下所述电源电压为所述第二电压。
  7. 根据权利要求6所述的可编程存储器，其中，所述字线地址信号包括第一地址信号和第二地址信号，所述字线控制电路包括：
    第一N型晶体管，所述第一N型晶体管的第一极接地，第一N型晶体管的栅极用于接收所述第一地址信号；
    第二N型晶体管，所述第二N型晶体管的第一极连接所述第一N型晶体管的第二极，所述第二N型晶体管的第二极连接第一节点，所述第二N型晶体管的栅极用于接收所述第二地址信号；
    第三N型晶体管，所述第三N型晶体管的第一极接地，所述第三N型晶体管的第二极连接所述字线，所述第三N型晶体管的栅极连接所述第一节点；
    第四P型晶体管，所述第四P型晶体管的第一极用于接收所述电源电压，所述第四P型晶体管的第二极连接所述字线，所述第四P型晶体管的栅极连接所述第一节点；
    第五P型晶体管，所述第五P型晶体管的第一极用于接收所述电源电压，所述第五P型晶体管的第二极连接所述第一节点，所述第五P型晶体管的栅极用于接收所述第一地址信号；
    第六P型晶体管，所述第六P型晶体管的第一极用于接收所述电源电压，所述第六P型晶体管的第二极连接所述第一节点，所述第六P型晶体管的栅极用于接收所述第二地址信号。
  8. 根据权利要求7所述的可编程存储器，其中，所述第一地址信号为行地址信号，所述第二地址信号为子阵列地址信号。
  9. 根据权利要求6所述的可编程存储器，其中，所述电压调节电路包括：
    比较器，所述比较器的反相输入端用于接收参考电压，所述比较器的正相输入端连接第二节点，所述比较器的输出端连接第三节点；
    第七P型晶体管，所述第七P型晶体管的第一极连接电源端，所述第七P型晶体管的第二极用于输出所述电源电压，所述第七P型晶体管的栅极连接所述第三节点；
    第一可变电阻，连接于所述第七P型晶体管的第二极和所述第二节点之间；
    第二可变电阻，连接于所述第二节点和接地端之间；
    调整电路，用于根据编程标志信号调整所述参考电压、所述第一可变电阻、所述第二可变电阻中的至少一个。
  10. 根据权利要求6所述的可编程存储器，其中，所述电压调节电路包括：
    控制信号生成电路，用于根据编程标志信号输出第一控制信号或第二控制信号；
    电压选择电路，用于接收所述第一控制信号或所述第二控制信号，且用于根据所述第一控制信号输出所述第一电压至所述字线控制电路，或用于根据所述第二控制信号输出所述第二电压至所述字线控制电路。
  11. 根据权利要求10所述的可编程存储器，其中，所述控制信号生成电路包括：
    第八N型晶体管，所述第八N型晶体管的第一极连接低电平信号端，所述第八N型晶体管的栅极用于接收所述编程标志信号，所述第八N型晶体管的第二极用于输出所述第一控制信号；
    反相器，所述反相器的输入端用于接收所述编程标志信号；
    第九N型晶体管，所述第九N型晶体管的第一极连接高电平信号端，所述第九N型晶体管的栅极连接所述反相器的输出端，所述第九N型晶体管的第二极连接所述第八N型晶体管的第二极；
    第十N型晶体管，所述第十N型晶体管的第一极连接所述低电平信号端，所述第十N型晶体管的栅极连接所述反相器的输出端，所述第十N型晶体管的第二极用于输出所述第二控制信号；
    第十一N型晶体管，所述第十一N型晶体管的第一极连接高电平信号端，所述第十一N型晶体管的栅极用于接收所述编程标志信号，所述第十一N型晶体管的第二极连接所述第十N型晶体管的第二极；
    所述电压选择电路包括：
    第十二P型晶体管，所述第十二P型晶体管的第一极用于接收所述第一电压，所述第十二P型晶体管的栅极连接所述第八N型晶体管的第二极和所述第九N型晶体管的第二极，所述第十二P型晶体管的第二极用于输出所述电源电压；
    第十三P型晶体管，所述第十三P型晶体管的第一极用于接收所述第二电压，所述第十三P型晶体管的栅极连接所述第十N型晶体管的第二极和所述第十一N型晶体管的第二极，所述第十三P型晶体管的第二极用于输出所述电源电压。
  12. 一种可编程存储器驱动方法，其中，所述可编程存储器包括：
    多个反熔丝单元，多个所述反熔丝单元沿行列方向阵列分布，所述反熔丝单元包括反熔丝和开关晶体管，所述反熔丝的第一端和所述开关晶体管的第一极相连接；
    多条字线，所述字线连接位于同一行的所述开关晶体管的栅极；
    所述驱动方法包括：
    在编程模式下，向目标反熔丝单元连接的所述字线提供第一电压；
    在读取模式下，向目标反熔丝单元连接的所述字线提供第二电压；
    其中，所述第一电压大于所述第二电压。
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