WO2023236281A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2023236281A1
WO2023236281A1 PCT/CN2022/102507 CN2022102507W WO2023236281A1 WO 2023236281 A1 WO2023236281 A1 WO 2023236281A1 CN 2022102507 W CN2022102507 W CN 2022102507W WO 2023236281 A1 WO2023236281 A1 WO 2023236281A1
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layer
semiconductor
active pillar
storage node
semiconductor structure
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PCT/CN2022/102507
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English (en)
French (fr)
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唐怡
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长鑫存储技术有限公司
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Priority to US17/951,017 priority Critical patent/US20230018059A1/en
Publication of WO2023236281A1 publication Critical patent/WO2023236281A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a semiconductor structure and a method of forming the same.
  • DRAM Dynamic Random Access Memory
  • Each storage unit usually includes a capacitor and a transistor.
  • the source of the transistor is connected to the capacitor through the storage node contact and the landing pad, thereby reading the data information stored in the capacitor, or writing the data information into the capacitor for storage.
  • DRAM is mostly made using the 6F 2 arrangement and the buried word line process.
  • New materials are also used to improve the performance of DRAM.
  • This undoubtedly improves the performance of DRAM.
  • the process complexity and manufacturing cost of DRAM are reduced.
  • vertical transistors are also used to produce 4F 2 arrangement DRAM.
  • a large amount of charges (or holes) will accumulate in the channels of the vertical transistors, and none of these charges (or holes) can be leaked.
  • Path the accumulation of more and more charges (or holes) will cause the vertical transistors to fail to work properly. Therefore, there is a certain degree of floating body effect (Floating Body Effect) in the DRAM structures formed by vertical transistors in related technologies. FBE), affecting the performance of DRAM.
  • FBE floating Body Effect
  • embodiments of the present disclosure provide a semiconductor structure and a method of forming the same.
  • an embodiment of the present disclosure provides a method for forming a semiconductor structure, the method including:
  • the semiconductor substrate including a plurality of spaced-apart active pillars
  • a first semiconductor layer is formed in the annular groove to form the semiconductor structure; wherein the bandgap width of the first semiconductor layer is smaller than the bandgap width of the active pillar.
  • forming a first semiconductor layer in the annular groove to form the semiconductor structure includes:
  • a bit line metal layer is formed on the surface of the second semiconductor layer to form a bit line structure.
  • etching the active pillar to form an annular groove includes:
  • Part of the active pillar is etched through the first groove to form the annular groove.
  • an etch selectivity ratio between the first sacrificial layer and the active pillar is greater than an etch selectivity ratio between the second sacrificial layer and the active pillar.
  • the method further includes:
  • the surface treatment of the first semiconductor layer to form the second semiconductor layer includes:
  • the metal layer and the first semiconductor layer are annealed to form the second semiconductor layer.
  • the method before forming the first semiconductor layer, the method further includes:
  • the unetched portion of the active pillar located in the middle of the annular groove is first heavily doped to form a first heavily doped region.
  • the method further includes:
  • the full-circle gate structure is formed by the following steps:
  • a first insulating layer covering part of the active pillar is formed in the gap between the bit line structures and on the surface of the bit line metal layer;
  • a gate oxide layer and a gate metal layer covering part of the active pillars are sequentially formed on the surface of the first insulating layer to form the full gate-all-around structure.
  • the method further includes:
  • a second insulating layer covering part of the active pillar is formed in the gap between the full-circle gate structure, the surface of the gate oxide layer, and the surface of the gate metal layer.
  • the storage node contacts are formed by:
  • the annular pillar is heavily doped a second time to form the storage node contact.
  • the first heavy doping is of an opposite doping type than the second heavy doping.
  • the method further includes:
  • Conductive material is filled in the second groove to form a conductive layer.
  • the capacitor structure is formed by the following steps:
  • a first electrode layer, a dielectric layer and a second electrode layer are sequentially formed on the surface of the storage node contact and the third insulating layer to form the capacitor structure.
  • the capacitor structure is formed by the following steps:
  • a first electrode layer, a dielectric layer and a second electrode layer are sequentially formed on the surface of the storage node contact and the conductive layer to form the capacitor structure.
  • inventions of the present disclosure provide a semiconductor structure, which is formed by the above-mentioned method for forming a semiconductor structure.
  • the semiconductor structure includes:
  • a semiconductor substrate a plurality of active pillars arranged at intervals are formed on the semiconductor substrate; each of the active pillars includes an annular groove, and the annular groove does not expose the top of the active pillar. surface and bottom surfaces;
  • a first semiconductor layer, the first semiconductor layer is located in the annular groove, and the bandgap width of the first semiconductor layer is smaller than the bandgap width of the active pillar.
  • the semiconductor structure further includes: a second semiconductor layer and a bit line metal layer;
  • the second semiconductor layer is located on the surface of the first semiconductor layer, and the bit line metal layer is located on the surface of the second semiconductor layer.
  • the semiconductor structure further includes: a full gate-all-around structure
  • the full-all-around gate structure is located on part of the surface of the active pillar, and the full-all-around gate structure includes a gate oxide layer and a gate metal layer.
  • the semiconductor structure further includes: a first insulating layer and a second insulating layer;
  • the first insulating layer is located on the surface of the bit line structure and in the gap between the bit line structures;
  • the second insulating layer is located on the surface of the full ring gate structure and in the gap between the full ring gate structure.
  • the semiconductor structure further includes: a storage node contact and a capacitive structure
  • the capacitive structure is located on a surface of the storage node contact, and the capacitive structure is electrically connected to the storage node contact.
  • the semiconductor structure further includes: a third insulating layer
  • the third insulating layer is located inside the storage node contact, and a top surface of the third insulating layer is flush with a top surface of the storage node contact.
  • the semiconductor structure further includes: a conductive layer
  • the conductive layer is located inside the storage node contact, and a top surface of the conductive layer is flush with a top surface of the storage node contact.
  • the semiconductor structure further includes: a first heavily doped region
  • the first heavily doped region is located inside the first semiconductor layer.
  • the semiconductor structure and its formation method includes: providing a semiconductor substrate including a plurality of active pillars arranged at intervals; etching the active pillars to form annular grooves; The groove does not expose the top surface and the bottom surface of the active pillar; a first semiconductor layer is formed in the annular groove to form a semiconductor structure; wherein the bandgap width of the first semiconductor layer is smaller than the bandgap width of the active pillar.
  • the first semiconductor layer can serve as the source of the transistor. Since the bandgap width of the first semiconductor layer is smaller than the bandgap width of the active pillar, the potential barrier between the source electrode and the semiconductor substrate is reduced. The holes accumulated in the channel are easily exported, and the parasitic bipolar transistor effect is weakened, which can effectively suppress the occurrence of the floating body effect of the formed semiconductor structure, and improve the electrical performance and production yield of the semiconductor structure.
  • Figure 1 is a schematic flowchart of a semiconductor structure forming method provided by an embodiment of the present disclosure
  • FIGS. 2a to 2r are schematic structural diagrams of the semiconductor structure formation process provided by embodiments of the present disclosure.
  • Figure 3a is a schematic three-dimensional structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figures 3b and 3c are cross-sectional views along b-b' of the semiconductor structure in Figure 3a provided by an embodiment of the present disclosure
  • 100 semiconductor substrate; 101—active pillar; 102—isolation layer; 103—first sacrificial layer; 104—second sacrificial layer; 105—first semiconductor layer; 106—second semiconductor layer; 107—bit line metal layer; 108—first insulating layer; 109—gate oxide layer; 110—gate metal layer; 111—second insulating layer; 101a—annular pillar; 101b—storage node contact; 30—full all-around gate structure; 112— Third insulating layer; 113—first electrode layer; 114—dielectric layer; 115—second electrode layer; 116—conductive layer; 117—first heavily doped region; 40—capacitor structure; 300—semiconductor structure; A— The first groove; B—annular groove; C—the second groove.
  • FIG. 1 is a schematic flowchart of a method for forming a semiconductor structure provided by an embodiment of the disclosure. As shown in Figure 1, the method for forming a semiconductor structure includes the following steps: Step S101, providing a semiconductor The semiconductor substrate includes a plurality of active pillars arranged at intervals.
  • the semiconductor substrate may include a top surface on the front side and a bottom surface opposite to the front side; neglecting the flatness of the top surface and the bottom surface, two mutually intersecting (for example, each other) planes may be defined on the plane where the semiconductor substrate is located.
  • the first direction and the second direction are vertical), and the direction perpendicular to the top surface and the bottom surface of the semiconductor substrate is defined as a third direction.
  • the first direction is defined as the X-axis direction
  • the second direction is defined as the Y-axis direction
  • the third direction is defined as the Z-axis direction.
  • the semiconductor substrate may be a silicon substrate, and the semiconductor substrate may also include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs) ), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenic phosphide (GaAsP) ), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and/or gallium indium arsenide phosphide (GaInAsP) or combinations thereof.
  • germanium germanium
  • semiconductor compounds such as silicon carbide (SiC), gallium arsenide (G
  • the semiconductor substrate includes a plurality of active pillars arranged in an array along the first direction and the second direction, and the active pillars are used to form transistors of the semiconductor structure.
  • the active pillar may be a square prism (for example, a four-sided prism, a six-sided prism, or an eight-sided prism) or a cylinder.
  • the semiconductor substrate and the active pillar can be formed in one step through an etching process, and both the semiconductor substrate and the active pillar can be P-type doped.
  • the active pillar may be a P-type doped silicon pillar, and the bandgap width of the active pillar is between 1.0 electron volt (Electron Volt, eV) and 1.3 eV.
  • Step S102 Etch the active pillar to form an annular groove; the annular groove does not expose the top surface and bottom surface of the active pillar.
  • part of the active pillars can be laterally etched and removed in the second direction through wet etching technology to form an annular groove.
  • the annular groove is formed in the middle part of the active pillar. Therefore, the annular groove is not exposed.
  • the top and bottom surfaces of the active pillars are shown.
  • some active pillars remain in the middle of the annular groove and have not been etched away.
  • the remaining active pillars that is, the active pillars located in the projection area of the annular groove along the second direction
  • Step S103 Form a first semiconductor layer in the annular groove to form a semiconductor structure; the bandgap width of the first semiconductor layer is smaller than the bandgap width of the active pillar.
  • the first semiconductor layer may serve as the source of the transistor, and the first semiconductor layer may be an N-type doped semiconductor layer, for example, an N-type doped silicon germanium layer.
  • the bandgap width of the first semiconductor layer It is between 0.7eV ⁇ 0.97eV.
  • the material of the first semiconductor layer may also be a metal sulfide material, such as iron sulfide, manganese sulfide, titanium sulfide or nickel sulfide.
  • the bandgap width of the first semiconductor layer is smaller than the bandgap width of the active pillar, the potential barrier between the source electrode and the semiconductor substrate can be reduced, making it easier for holes accumulated in the transistor channel to Being dissipated, the parasitic bipolar transistor effect is weakened, which can effectively suppress the occurrence of the floating body effect of the formed semiconductor structure, and improve the electrical performance and manufacturing yield of the semiconductor structure.
  • FIGS. 2a to 2r are schematic structural diagrams of the semiconductor structure formation process provided by embodiments of the present disclosure. The formation process of the semiconductor structure provided by the embodiment of the present disclosure will be described in detail below with reference to FIGS. 2a to 2r.
  • step S101 is performed to provide a semiconductor substrate 100 .
  • the semiconductor substrate 100 includes a plurality of active pillars 101 arranged at intervals.
  • the semiconductor substrate 100 includes a plurality of active pillars 101 arranged in an array along the X-axis direction (first direction) and the Y-axis direction (second direction).
  • Figure 2b only shows a cross-sectional view of one active pillar 101 along a-a' in Figure 2a, and Figures 2c to 2r in the subsequent formation process are all shown from a cross-sectional perspective of a-a'.
  • step S102 to etch the active pillar to form an annular groove B; the annular groove B does not expose the top and bottom surfaces of the active pillar 101 .
  • the annular groove B may be formed by the following steps: forming an isolation layer 102 on the surface of the semiconductor substrate 100; forming a first sacrificial layer 103 covering part of the active pillar 101 on the surface of the isolation layer 102; The second sacrificial layer 104 is formed on the surface of the layer 102, the first sacrificial layer 103 and the active pillar 101; the first sacrificial layer 103 is removed to form the first groove A; through the first groove A, part of the active pillar 101 is etched , forming an annular groove B.
  • an isolation layer 102 is formed on the surface of the semiconductor substrate 100.
  • the isolation layer 102 is used to isolate the semiconductor substrate 100 and the active pillar 101 to prevent the semiconductor substrate 100 from leaking electricity.
  • the material of the isolation layer 102 may be an oxide or silicon oxynitride, such as silicon oxide.
  • a first sacrificial layer 103 covering part of the active pillar 101 is formed on the surface of the isolation layer 102 .
  • the height h1 of the first sacrificial layer 103 is less than the height h2 of the active pillar 101.
  • the first sacrificial layer 103 is used to define the position of the bit line structure in the subsequent process. Therefore, the first sacrificial layer 103 is relatively It has a high wet etching selectivity ratio between the semiconductor substrate 100 (or the active pillar 101) and the isolation layer 102.
  • the material of the first sacrificial layer 103 may be one or any combination of silicon nitride (SiN), silicon oxynitride (SiON), amorphous carbon (Amorphous Carbon, a-C) or silicon oxynitride carbon (SiOCN).
  • a second sacrificial layer 104 is formed on the surfaces of the isolation layer 102, the first sacrificial layer 103 and the active pillar 101.
  • the second sacrificial layer 104 is used to protect the active pillar 101 when forming the bit line structure. Therefore, the second sacrificial layer 104 has an
  • the material of the second sacrificial layer 104 may be one or any combination of silicon nitride, silicon oxynitride, amorphous carbon, or silicon oxynitride.
  • the etching selectivity ratio between the first sacrificial layer 103 and the active pillar 101 is greater than the etching selectivity ratio between the second sacrificial layer 104 and the active pillar 101 , that is, under the same etching conditions,
  • the first sacrificial layer 103 is easier to be removed by etching than the second sacrificial layer 104 .
  • the first sacrificial layer 103 is removed to form the first groove A.
  • wet etching technology can be used to remove the first sacrificial layer 103.
  • strong acids such as concentrated sulfuric acid, hydrofluoric acid, concentrated nitric acid, etc. can be used to etch away the first sacrificial layer 103 to form the first groove A.
  • a portion of the active pillar 101 is etched through the first groove A to form an annular groove B.
  • part of the active pillar 101 can be removed by etching using lateral dry etching technology to form an annular groove B.
  • the annular groove B is located in the middle and lower part of the active pillar 101 and does not expose the bottom surface and the top surface of the active pillar 101 .
  • the isolation layer 102, the first sacrificial layer 103 and the second sacrificial layer 104 can be formed by any suitable deposition process, such as chemical vapor deposition process (Chemical Vapor Deposition), physical vapor deposition (Physical Vapor Deposition). Vapor Deposition (PVD) process, Atomic Layer Deposition (ALD) process, spin coating process, coating process or furnace tube process.
  • CVD chemical vapor deposition
  • PVD Physical vapor deposition
  • ALD Atomic Layer Deposition
  • spin coating process coating process or furnace tube process.
  • the method of forming the semiconductor structure further includes: performing a first step on the unetched portion of the active pillar 101 located in the middle of the annular groove B. Doping to form a first heavily doped region 117.
  • the first heavy doping may be P-type doping of the active pillar 101.
  • the active pillar 101 is doped with trivalent impurity elements such as boron, gallium, and indium.
  • the purpose of forming the first heavily doped region 117 is to form a conductive channel.
  • This conductive channel can allow holes accumulated in the transistor channel to enter the semiconductor through band to band tunneling.
  • the conduction of the parasitic transistor is avoided, and the electrical performance of the semiconductor structure is improved.
  • step S103 is performed to form a first semiconductor layer 105 in the annular groove B to form a semiconductor structure; the bandgap width of the first semiconductor layer 105 is smaller than the bandgap width of the active pillar 101.
  • the first semiconductor layer 105 is the source of the semiconductor structure.
  • the formation process of the first semiconductor layer 105 may include the following steps: filling the annular groove B with semiconductor material to form the first semiconductor layer 105 ; the first semiconductor layer 105 fills the annular groove B.
  • the semiconductor material forming the first semiconductor layer 105 may be silicon germanium.
  • the bandgap width of the first semiconductor layer 105 is smaller than the bandgap width of the active pillar 101 , the hole current of the transistor in the finally formed semiconductor structure increases, and the gap between the source electrode and the semiconductor substrate 100 The potential barrier is reduced, causing the holes accumulated in the transistor channel to be easily dispersed, the parasitic bipolar transistor effect is weakened, and the breakdown voltage increases, which can effectively suppress the occurrence of the floating body effect.
  • the method of forming the semiconductor structure further includes: removing the second sacrificial layer 104.
  • the second sacrificial layer 104 may be removed by wet etching technology or dry etching technology (for example, plasma etching technology, ion milling technology, or reactive ion etching technology).
  • the semiconductor structure at least includes a bit line structure.
  • Step S103 may include the following steps: surface treatment of the first semiconductor layer 105 to form a second semiconductor layer 106; A bit line metal layer 107 is formed on the surface of 106 to form a bit line structure.
  • the material of the bit line metal layer 107 includes: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), titanium-containing metal layer, polysilicon or other Any combination.
  • the first semiconductor layer 105 is subjected to surface treatment, and the second semiconductor layer 106 can be formed by the following steps: depositing a metal material on the surface of the first semiconductor layer 105 to form a metal layer (not shown in the figure); The metal layer and the first semiconductor layer 105 are annealed to form the second semiconductor layer 106.
  • the metal material forming the second semiconductor layer 106 may be any one of titanium (Ti), tantalum (Ta), nickel (Ni), tungsten, platinum (Pt), and palladium (Pd).
  • Metal silicide is formed as the second semiconductor layer 106 by depositing a metal material on the surface of the first semiconductor layer 105 and causing the metal material to react with the first semiconductor layer 105 through a rapid thermal annealing process.
  • the bit line structure ie, the bit line metal layer 107) and the first semiconductor layer 105 are connected through the second semiconductor layer 106 (ie, metal silicide). Since the metal silicide has a lower resistance, it can The contact resistance between the bit line metal layer 107 and the first semiconductor layer 105 is reduced, thereby reducing the power consumption of the formed semiconductor structure.
  • the method of forming the semiconductor structure further includes forming a full gate-all-around structure, a storage node contact, and a capacitor structure.
  • the full-circle gate 30 structure can be formed by the following steps: forming a first insulating layer 108 covering part of the active pillar 101 in the gap between the bit line structures and the surface of the bit line metal layer 107; A gate oxide layer 109 and a gate metal layer 110 covering part of the active pillars are formed on the surfaces of the insulating layer 108 and the active pillars 101 in sequence to form a full gate structure 30; wherein the top surface of the gate oxide layer 109 is lower than The top surface of the active pillar 101 .
  • the first insulating layer 108 is used to isolate adjacent bit line structures and prevent leakage of the bit line structures, thereby making it impossible to perform read or write operations on a specific transistor; on the other hand, the third insulating layer 108 An insulating layer 108 can also achieve isolation between the bit line structure and the subsequently formed full-circuit gate structure.
  • the first insulating layer 108, the gate oxide layer 109 and the gate metal layer 110 can be formed through any suitable deposition process.
  • the material of the first insulating layer 108 can be silicon nitride; the material of the gate oxide layer 109 can be an oxide, such as silicon oxide; the material of the gate metal layer 110 can be any material with good conductive properties, such as It is titanium nitride.
  • the full-circle gate structure 30 has a wide channel region, which can reduce the short channel effect and improve the gate control capability, thereby improving the performance of the formed semiconductor structure.
  • the formation method of the semiconductor structure further includes: the gaps between the full-all-around gate structures 30, the surface of the gate oxide layer 109, and the gate.
  • the surface of the pole metal layer 110 forms a second insulating layer 111 covering part of the active pillar 101 .
  • the second insulating layer 111 is used to isolate the adjacent full-circle gate structure 30 on the one hand and prevent the adjacent full-circuit gate structure 30 from being turned on, thereby making it impossible to control a single transistor; on the other hand, The second insulating layer 111 can also achieve isolation between the full-circle gate structure 30 and the capacitor structure subsequently formed.
  • the material of the second insulating layer 111 may be silicon nitride, silicon oxide or silicon oxynitride.
  • the storage node contact 101b can be formed by the following steps: etching the active pillar 101, forming a second groove C and an annular pillar 101a, the bottom surface of the second groove C and the second insulating layer 111 The top surface is flush; annular pillar 101a is heavily doped a second time to form storage node contact 101b.
  • a dry etching process (such as a plasma etching process, a reactive ion etching process, or an ion milling process) may be used to etch the active pillar 101 to form the annular pillar 101a and the second groove C.
  • the second heavy doping can be N-type doping of the annular pillar 101a.
  • the active pillar 101 is doped with pentavalent impurity elements such as phosphorus, antimony, arsenic, etc. to improve the conductivity of the annular pillar 101a.
  • the doping types of the first heavy doping and the second heavy doping are opposite.
  • the purpose of performing the second heavy doping on the annular pillar 101a is to reduce the internal resistance of the annular pillar 101a, improve the conductivity of the storage node contact 101b, and thereby reduce the relationship between the formed storage node contact 101b and the drain and capacitance.
  • the contact resistance between structures improves the electrical properties of semiconductor structures.
  • the active pillar 101 located in the projection area of the second insulating layer 111 constitutes the drain D of the semiconductor structure.
  • the storage node contact is made into a hollow structure, that is, the second groove C is formed in the active pillar 101 in order to increase the doping area of the second heavy doping, that is, in order to realize the annular pillar 101a. More fully heavily doped, thereby reducing the contact resistance between the storage node contact 101b and the drain D and capacitor structure.
  • the method of forming the semiconductor structure further includes: filling the second groove with an insulating material to form a third insulating layer 112.
  • the third insulating layer 112 fills the second groove, and the top surface of the third insulating layer 112 is flush with the top surface of the storage node contact 101b.
  • the insulating material may be an oxide or a nitride, such as silicon oxide, silicon nitride or silicon oxynitride.
  • the third insulating layer 112 is located inside the storage node contact 101b, and a capacitive structure is subsequently formed on the surface of the third insulating layer 112 and the storage node contact 101b.
  • the third insulating layer 112 can prevent leakage of the capacitive structure. .
  • the capacitor structure 40 may be formed by the following steps: first electrode layer 113, dielectric layer 114 and second electrode layer 115 are sequentially formed on the surface of the storage node contact 101b and the third insulating layer 112. , to form the capacitor structure 40 .
  • the first electrode layer 113, the dielectric layer 114 and the second electrode material can be formed by sequentially depositing the first electrode material, the dielectric material and the second electrode material on the surface of the storage node contact 101b and the third insulating layer 112. Electrode layer 115.
  • the first electrode material, dielectric material and second electrode material can be formed by any one of the following deposition processes: chemical vapor deposition process, physical vapor deposition process, and atomic layer deposition process.
  • the first electrode material and the second electrode material may include metal nitride or metal suicide, for example, titanium nitride.
  • the dielectric material may include a high-K dielectric material, such as lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), hafnium oxynitride (HfON), hafnium silicate (HfSiO x ) or zirconium oxide (ZrO 2 ) or any combination thereof.
  • a high-K dielectric material such as lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), hafnium oxynitride (HfON), hafnium silicate (HfSiO x ) or zirconium oxide (ZrO 2 ) or any combination thereof.
  • the first electrode material and the second electrode material may also be polysilicon.
  • the method of forming the semiconductor structure further includes: filling the second groove with conductive material to form the conductive layer 116 .
  • the conductive layer 116 fills the second groove, and the top surface of the conductive layer 116 is flush with the top surface of the storage node contact 101b.
  • the conductive material can be any one of titanium, tantalum, nickel, tungsten, platinum, palladium and polysilicon.
  • the capacitor structure 40 can also be formed by the following steps: first electrode layer 113, dielectric layer 114 and second electrode layer 115 are sequentially formed on the surface of the storage node contact 101b and the conductive layer 116 to form the capacitor structure 40.
  • the first electrode layer 113, the dielectric layer 114 and the second electrode layer can be formed by sequentially depositing the first electrode material, the dielectric material and the second electrode material on the surfaces of the storage node contact 101b and the conductive layer 116. 115.
  • Both the first electrode material and the second electrode material may include metal nitride or metal suicide, for example, titanium nitride.
  • the dielectric material may include a high-K dielectric material, such as one or any combination of lanthanum oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, hafnium silicate or zirconium oxide.
  • the first electrode material, dielectric material and second electrode material can be formed by any one of the following deposition processes: chemical vapor deposition process, physical vapor deposition process, and atomic layer deposition process.
  • the first electrode material and the second electrode material may include metal nitride or metal suicide, for example, titanium nitride.
  • the dielectric material may include a high-K dielectric material, such as one or any combination of lanthanum oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, hafnium silicate or zirconium oxide.
  • the first electrode material and the second electrode material may also be polysilicon.
  • the conductive layer 116 is located between the storage node contacts 101b.
  • the storage node contacts 101b and the conductive layer 116 are used to electrically connect the drain of the semiconductor structure and the capacitor structure. Therefore, the conductive layer 116 can improve the performance of the storage node contacts 101b. conductivity, thereby reducing the contact resistance between the storage node contact 101b and the capacitor structure, and improving the electrical performance of the semiconductor structure.
  • a transistor structure is formed on the surface of each active pillar, and the drawings in the description only show the formation process of one transistor.
  • the transistor since the transistor has a vertical structure, the integration level of the semiconductor structure can be improved and the size of the semiconductor structure can be reduced.
  • the active pillar of the source is thinned and P-type heavily doped (i.e., the first heavy doping) is performed to form a conductive channel.
  • P-type heavily doped i.e., the first heavy doping
  • N-type SiGe i.e., the first semiconductor layer
  • the source pillar serves as the source. Due to the narrow bandgap of N-type SiGe, the hole current increases.
  • the potential barrier between the source and the semiconductor substrate decreases, causing the holes accumulated in the transistor channel to be easily dissipated, so the parasitic
  • the bipolar transistor effect weakens and the breakdown voltage increases, effectively suppressing the occurrence of the floating body effect; in addition, P-type heavy doping can cause the holes accumulated in the transistor channel to enter the semiconductor substrate through inter-band tunneling, thus avoiding The conduction of the parasitic transistor is reduced, and the electrical performance of the prepared semiconductor structure is improved.
  • FIGS. 3a to 3c The embodiment of the present disclosure provides a semiconductor structure.
  • Figure 3a is a schematic diagram of the three-dimensional structure of the semiconductor structure provided by the embodiment of the present disclosure.
  • Figures 3b and 3c are cross-sections along b-b' of the semiconductor structure in Figure 3a provided by the embodiment of the present disclosure.
  • the semiconductor structure 300 includes: a semiconductor substrate 100 and a first semiconductor layer 105 .
  • each active pillar 101 includes an annular groove.
  • the grooves do not expose the top and bottom surfaces of the active pillars 101 .
  • the active pillar 101 is used to form a transistor of the semiconductor structure 300 .
  • the active pillar may be a P-type doped silicon pillar, and the bandgap width of the active pillar is between 1.0eV and 1.3eV.
  • the first semiconductor layer 105 is located in the annular groove, and the bandgap width of the first semiconductor layer 105 is smaller than the bandgap width of the active pillar 101 .
  • the first semiconductor layer 105 may serve as the source of the transistor, and the first semiconductor layer 105 may be an N-type doped semiconductor layer, for example, an N-type doped silicon germanium layer.
  • the bandgap width is between 0.7eV and 0.97eV.
  • the bandgap width of the first semiconductor layer 105 is smaller than the bandgap width of the active pillar 101, the potential barrier between the source electrode and the semiconductor substrate can be reduced, so that holes accumulated in the transistor channel It is easily dissipated and the parasitic bipolar transistor effect is weakened, which can effectively suppress the occurrence of the floating body effect of the semiconductor structure and improve the electrical performance of the semiconductor structure 300 .
  • the semiconductor structure 300 further includes: a second semiconductor layer 106 and a bit line metal layer.
  • the second semiconductor layer 106 is located on the surface of the first semiconductor layer 105
  • the bit line metal layer 107 is located on the surface of the second semiconductor layer 106 .
  • the second semiconductor layer and the bit line metal layer 107 constitute a bit line structure.
  • the second semiconductor layer 106 is a metal silicide layer. Since the metal silicide has a lower resistance, the contact resistance between the bit line metal layer 107 and the first semiconductor layer 105 can be reduced, thereby enabling The power consumption of the semiconductor structure 300 is reduced.
  • the semiconductor structure 300 further includes: a full-surround gate structure 30 ; the full-surround gate structure 30 is located on the surface of part of the active pillars 101 , and the full-surround gate structure 30 includes a gate oxide layer. 109 and gate metal layer 110.
  • the full-circle gate structure 30 has a wide channel region, which can reduce the short channel effect and improve the gate control capability, thereby improving the performance of the semiconductor structure 300 .
  • the semiconductor structure 300 also includes: a first insulating layer 108 and a second insulating layer 111; wherein the first insulating layer 108 is located on the surface of the bit line structure, and the bit line structure In the gap between them; the second insulating layer 111 is located on the surface of the full-all-around gate structure 30 and in the gap between the full-all-around gate structure 30 .
  • the first insulating layer 108 is used to isolate adjacent bit line structures and prevent leakage of the bit line structures, thereby making it impossible to perform read or write operations on a specific transistor; on the other hand, the third insulating layer 108 An insulating layer 108 can also achieve isolation between the bit line structure and the full-circle gate structure 30 .
  • the second insulating layer 111 is used to isolate the adjacent full-ring gate structures 30 and prevent the adjacent full-ring gate structures 30 from being turned on, thereby making it impossible to control a single transistor; on the other hand, the second insulating layer 111 also The isolation effect between the all-around gate structure 30 and the capacitor structure can be achieved.
  • the semiconductor structure 300 also includes: a storage node contact 101b and a capacitive structure 40; wherein the capacitive structure 40 is located on the surface of the storage node contact 101b, and the capacitive structure 40 is in contact with the storage node. 101b electrical connection.
  • the active pillar 101 is doped with a second heavy level to form the storage node contact 101b.
  • the second heavy doping may be an N-type doping of the annular pillar 101a.
  • doping in the active pillar 101 Pentavalent impurity elements such as phosphorus, antimony, and arsenic.
  • the storage node contact 101b formed after the second heavy doping has lower internal resistance and higher conductivity, which reduces the contact resistance between the storage node contact 101b and the drain and capacitor structures, thereby improving the semiconductor structure. 300 electrical properties.
  • the semiconductor structure 300 further includes: a third insulating layer 112; the third insulating layer 112 is located inside the storage node contact 101b; the top surface of the third insulating layer 112 is in contact with the storage node 101b. The top surface of the third insulating layer 112 is flush with the bottom surface of the storage node contact 101 b.
  • the third insulating layer 112 can prevent leakage of the capacitor structure 40 .
  • the semiconductor structure 300 further includes: a conductive layer 116; the conductive layer 116 is located inside the storage node contact 101b; the top surface of the conductive layer 116 is flush with the top surface of the storage node contact 101b, And the bottom surface of the conductive layer 116 is flush with the bottom surface of the storage node contact 101b.
  • the conductive layer 116 can improve the conductivity of the storage node contact 101b, thereby reducing the contact resistance between the storage node contact 101b and the capacitor structure 40, and improving the electrical performance of the semiconductor structure 300.
  • the semiconductor structure 300 further includes a first heavily doped region 117; Region formed by heavy doping.
  • the first heavy doping may be P-type doping of the active pillar 101.
  • the active pillar 101 is doped with trivalent impurity elements such as boron, gallium, and indium.
  • the first heavily doped region 117 can serve as a conductive channel, allowing holes accumulated in the transistor channel to enter the semiconductor substrate 100 through inter-band tunneling, thereby avoiding the conduction of the parasitic transistor and improving the efficiency of the semiconductor structure 300 electrical properties.
  • the semiconductor structure 300 further includes a drain D; the active pillar 101 located in the projection area of the second insulating layer 111 constitutes the drain D of the semiconductor structure.
  • the semiconductor structure provided by the embodiments of the present disclosure is similar to the formation method of the semiconductor structure provided by the above-mentioned embodiments.
  • the semiconductor structure provided by the embodiments of the present disclosure on the one hand, because the transistor has a vertical structure, can improve the integration level of the semiconductor structure and achieve shrinkage of the size of the semiconductor structure; on the other hand, due to the bandgap width of the first semiconductor layer in the semiconductor structure is smaller than the bandgap width of the active pillar. Therefore, the hole current of the transistor increases and the potential barrier between the source and the semiconductor substrate decreases. As a result, the holes accumulated in the transistor channel are easily dissipated and the parasitic bipolar transistor effect is weakened. , the breakdown voltage increases, which can effectively suppress the occurrence of the floating body effect and improve the performance of the semiconductor structure.
  • the disclosed devices and methods can be implemented in a non-target manner.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • the first semiconductor layer can serve as the source of the transistor. Since the bandgap width of the first semiconductor layer is smaller than the bandgap width of the active pillar, the potential barrier between the source electrode and the semiconductor substrate is reduced. The holes accumulated in the channel are easily exported, and the parasitic bipolar transistor effect is weakened, which can effectively suppress the occurrence of the floating body effect of the formed semiconductor structure, and improve the electrical performance and production yield of the semiconductor structure.

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Abstract

本公开实施例提供一种半导体结构及其形成方法，其中，所述方法包括：提供半导体衬底，所述半导体衬底包括多个间隔排布的有源柱；刻蚀所述有源柱，形成环形凹槽；所述环形凹槽未暴露出所述有源柱的顶表面和底表面；在所述环形凹槽中形成第一半导体层，以形成所述半导体结构；其中，所述第一半导体层的禁带宽度小于所述有源柱的禁带宽度。

Description

半导体结构及其形成方法
相关申请的交叉引用
本公开基于申请号为202210656240.1、申请日为2022年06月10日、发明名称为“半导体结构及其形成方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，涉及但不限于一种半导体结构及其形成方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。每一个存储单元通常包括电容器和晶体管，晶体管的源极通过存储节点接触和着陆焊盘与电容器连接，进而实现读取存储在电容器中的数据信息，或者，将数据信息写入电容器中进行存储。
当前，多采用6F 2的排布方式和掩埋字线工艺来制作DRAM，然而，在这种工艺下DRAM的微缩变得十分困难，也有通过使用新材料来改善DRAM的性能，然而，这无疑提高了DRAM的工艺复杂度和制造成本。基于此，相关技术中，亦有采用垂直晶体管制作4F 2排布的DRAM，然而，垂直晶体管的沟道中会聚集大量的电荷(或空穴)，而这些电荷(或空穴)没有一个可以泄露的路径，越来越多的电荷(或空穴)的积累会导致垂直晶体管无法正常工作，因此，相关技术中采用垂直晶体管所形成的DRAM结构中均存在一定程度的浮体效应(Floating Body Effect，FBE)，影响DRAM的性能。
发明内容
有鉴于此，本公开实施例提供一种半导体结构及其形成方法。
第一方面，本公开实施例提供一种半导体结构的形成方法，所述方法包括：
提供半导体衬底，所述半导体衬底包括多个间隔排布的有源柱；
刻蚀所述有源柱，形成环形凹槽；所述环形凹槽未暴露出所述有源柱的顶表面和底表面；
在所述环形凹槽中形成第一半导体层，以形成所述半导体结构；其中，所述第一半导体层的禁带宽度小于所述有源柱的禁带宽度。
在一些实施例中，所述在所述环形凹槽中形成第一半导体层，以形成所述半导体结构，包括：
对所述第一半导体层进行表面处理，形成第二半导体层；
在所述第二半导体层的表面形成位线金属层，以形成位线结构。
在一些实施例中，所述刻蚀所述有源柱，形成环形凹槽，包括：
在所述半导体衬底的表面形成隔离层；
在部分所述隔离层的表面形成覆盖部分所述有源柱的第一牺牲层；
在所述隔离层、所述第一牺牲层和所述有源柱的表面形成第二牺牲层；
去除所述第一牺牲层，形成第一凹槽；
通过所述第一凹槽，刻蚀部分所述有源柱，形成所述环形凹槽。
在一些实施例中，所述第一牺牲层与所述有源柱之间的刻蚀选择比大于所述第二牺牲层与所述有源柱之间的刻蚀选择比。
在一些实施例中，在形成所述第一半导体层之后，且在形成所述第二半导体层之前，所述方法还包括：
去除所述第二牺牲层。
在一些实施例中，所述对所述第一半导体层进行表面处理，形成所述第二半导体层，包括：
在所述第一半导体层表面淀积金属材料，形成金属层；
对所述金属层和所述第一半导体层进行退火处理，形成所述第二半导体层。
在一些实施例中，在形成所述第一半导体层之前，所述方法还包括：
对位于所述环形凹槽中间的、未被刻蚀的部分有源柱进行第一重掺杂，形成第一重掺杂区。
在一些实施例中，所述方法还包括：
形成全环栅结构、存储节点接触和电容结构。
在一些实施例中，所述全环栅结构通过以下步骤形成：
在所述位线结构之间的空隙、以及所述位线金属层的表面形成覆盖部分所述有源柱的第一绝缘层；
在所述第一绝缘层的表面依次形成覆盖部分有源柱的栅极氧化层和栅极金属层，以形成所述全环栅结构。
在一些实施例中，在形成所述全环栅结构以后，所述方法还包括：
在所述全环栅结构之间的空隙、所述栅极氧化层的表面、以及所述栅极金属层的表面形成覆盖部分所述有源柱的第二绝缘层。
在一些实施例中，所述存储节点接触通过以下步骤形成：
刻蚀所述有源柱，形成第二凹槽和环形柱，所述第二凹槽的底表面与所述第二绝缘层的顶表面平齐；
对所述环形柱进行第二重掺杂，形成所述存储节点接触。
在一些实施例中，所述第一重掺杂与所述第二重掺杂的掺杂类型相反。
在一些实施例中，所述方法还包括：
在所述第二凹槽中填充绝缘材料，形成第三绝缘层；或者，
在所述第二凹槽中填充导电材料，形成导电层。
在一些实施例中，所述电容结构通过以下步骤形成：
在所述存储节点接触和所述第三绝缘层的表面依次形成第一电极层、电介质层和第二电极层，以形成所述电容结构。
在一些实施例中，所述电容结构通过以下步骤形成：
在所述存储节点接触和所述导电层的表面依次形成第一电极层、电介质层和第二电极层，以形成所述电容结构。
第二方面，本公开实施例提供一种半导体结构，所述半导体结构通过上述半导体结构的形成方法形成，所述半导体结构包括：
半导体衬底，所述半导体衬底上形成有多个间隔排布的有源柱；每一所述有源柱包括一环形凹槽，所述环形凹槽未暴露出所述有源柱的顶表面和底表面；
第一半导体层，所述第一半导体层位于所述环形凹槽中，且所述第一半导体层的禁带宽度小于所述有源柱的禁带宽度。
在一些实施例中，所述半导体结构还包括：第二半导体层和位线金属层；
其中，所述第二半导体层位于所述第一半导体层的表面、且所述位线金属层位于所述第二半导体层的表面。
在一些实施例中，所述半导体结构还包括：全环栅结构；
所述全环栅结构位于部分所述有源柱的表面，所述全环栅结构包括栅极氧化层和栅极金属层。
在一些实施例中，所述半导体结构还包括：第一绝缘层和第二绝缘层；
其中，所述第一绝缘层位于所述位线结构的表面、以及所述位线结构之间的空隙中；
所述第二绝缘层位于所述全环栅结构的表面、以及所述全环栅结构之间的空隙中。
在一些实施例中，所述半导体结构还包括：存储节点接触和电容结构；
其中，所述电容结构位于所述存储节点接触的表面、且所述电容结构与所述存储节点接触电连接。
在一些实施例中，所述半导体结构还包括：第三绝缘层；
其中，所述第三绝缘层位于所述存储节点接触的内部，且所述第三绝缘层的顶表面与所述存储节点接触的顶表面平齐。
在一些实施例中，所述半导体结构还包括：导电层；
所述导电层位于所述存储节点接触的内部，且所述导电层的顶表面与所述存储节点接触的顶表面平齐。
在一些实施例中，所述半导体结构还包括：第一重掺杂区；
其中，所述第一重掺杂区位于所述第一半导体层的内部。
本公开实施例提供的半导体结构及其形成方法，其中，方法包括：提供半导体衬底，半导体衬底包括多个间隔排布的有源柱；刻蚀有源柱，形成环形凹槽；环形凹槽未暴露出有源柱的顶表面和底表面；在环形凹槽中形成第一半导体层，以形成半导体结构；其中，第一半导体层的禁带宽度小于有源柱的禁带宽度。本公开实施例中，第一半导体层可以作为晶体管的源极，由于第一半导体层的禁带宽度小于有源柱的禁带宽度，因此，源极与半导体衬底之间的势垒降低，沟道中积累的空穴很容易被导出，寄生双极晶体管效应减弱，能够有效地抑制所形成的半导体结构浮体效应的发生，提高了半导体结构的电性能和制备良率。
附图说明
在附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
图1为本公开实施例提供的半导体结构形成方法的流程示意图；
图2a～2r为本公开实施例提供的半导体结构形成过程中的结构示意图；
图3a为本公开实施例提供的半导体结构的三维结构示意图；
图3b和3c为本公开实施例提供的图3a中的半导体结构沿b-b’的剖面图；
附图标记说明如下：
100—半导体衬底；101—有源柱；102—隔离层；103—第一牺牲层；104—第二牺牲层；105—第一半导体层；106—第二半导体层；107—位线金属层；108—第一绝缘层；109—栅极氧化层；110—栅极金属层；111—第二绝缘层；101a—环形柱；101b—存储 节点接触；30—全环栅结构；112—第三绝缘层；113—第一电极层；114—电介质层；115—第二电极层；116-导电层；117-第一重掺杂区；40—电容结构；300—半导体结构；A—第一凹槽；B—环形凹槽；C—第二凹槽。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其它的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
本公开实施例提供一种半导体结构的形成方法，图1为本公开实施例提供的半导体结构形成方法的流程示意图，如图1所示，半导体结构的形成方法包括以下步骤：步骤S101，提供半导体衬底，半导体衬底包括多个间隔排布的有源柱。
半导体衬底可以包括处于正面的顶表面以及处于与正面相对的底表面；在忽略顶表面和底表面的平整度的情况下，可以在半导体衬底所在的平面上定义两个彼此相交(例如彼此垂直)的第一方向和第二方向，定义垂直半导体衬底顶表面和底表面的方向为第三方向。本公开实施例中，定义第一方向为X轴方向，第二方向为Y轴方向，第三方向为Z轴方向。
本公开实施例中，半导体衬底可以是硅衬底，半导体衬底也可以包括其它半导体元素，例如：锗(Ge)，或包括半导体化合物，例如：碳化硅(SiC)、砷化镓(GaAs)、磷化镓(GaP)、磷化铟(InP)、砷化铟(InAs)或锑化铟(InSb)，或包括其它半导体合金，例如：硅锗(SiGe)、磷化砷镓(GaAsP)、砷化铟铝(AlInAs)、砷化镓铝(AlGaAs)、 砷化铟镓(GaInAs)、磷化铟镓(GaInP)、及/或磷砷化铟镓(GaInAsP)或其组合。
本公开实施例中，半导体衬底包括沿第一方向和第二方向阵列排布的多个有源柱，有源柱用于形成半导体结构的晶体管。
本公开实施例中，有源柱可以是方形棱柱(例如，四棱柱、六棱柱、八棱柱)或者圆柱。
本公开实施例中，可以通过刻蚀工艺一步形成半导体衬底和有源柱，半导体衬底和有源柱均可以为P型掺杂。例如，本公开实施例中，有源柱可以是P型掺杂的硅柱，有源柱的禁带宽度位于1.0电子伏特(Electron Volt，eV)～1.3eV之间。
步骤S102、刻蚀有源柱，形成环形凹槽；环形凹槽未暴露出有源柱的顶表面和底表面。
本公开实施例中，可以通过湿法刻蚀技术沿第二方向横向刻蚀去除部分有源柱，形成环形凹槽，环形凹槽形成于有源柱的中间部分，因此，环形凹槽未暴露出有源柱的顶表面和底表面。
本公开实施例中，环形凹槽中间还保留有部分有源柱未被刻蚀掉，保留的这部分有源柱(即位于环形凹槽沿第二方向的投影区域的有源柱)后续用于形成半导体结构的晶体管的源极。
步骤S103、在环形凹槽中形成第一半导体层，以形成半导体结构；第一半导体层的禁带宽度小于有源柱的禁带宽度。
本公开实施例中，第一半导体层可以作为晶体管的源极，第一半导体层可以是N型掺杂的半导体层，例如，N型掺杂的硅锗层，第一半导体层的禁带宽度位于0.7eV～0.97eV之间。
在其它实施例中，第一半导体层的材料还可以是金属硫化物材料，例如，硫化铁、硫化锰、硫化钛或者硫化镍。
本公开实施例中，由于第一半导体层的禁带宽度小于有源柱的禁带宽度，如此，可以降低源极与半导体衬底之间的势垒，使得晶体管沟道中积累的空穴很容易被驱散，寄生双极晶体管效应减弱，能够有效地抑制所形成的半导体结构的浮体效应的发生，提高了半导体结构的电性能和制备良率。
图2a～2r为本公开实施例提供的半导体结构形成过程中的结构示意图。下面结合图2a～2r对本公开实施例提供的半导体结构的形成过程进行详细的说明。
首先，可以参考图2a和2b，执行步骤S101、提供半导体衬底100，半导体衬底100包括多个间隔排布的有源柱101。
本公开实施例中，如图2a所示，半导体衬底100包括多个沿X轴方向(第一方向)和Y轴方向(第二方向)阵列排布的有源柱101。
为便于理解，图2b中仅示出了一个有源柱101沿图2a中a-a’的剖面图，后续形成过程中的图2c至2r均以a-a’的剖面图视角示出。
接下来，可以参考图2c至2g，执行步骤S102、刻蚀有源柱，形成环形凹槽B；环形凹槽B未暴露出有源柱101的顶表面和底表面。
在一些实施例中，环形凹槽B可以通过以下步骤形成：在半导体衬底100的表面形成隔离层102；在隔离层102的表面形成覆盖部分有源柱101的第一牺牲层103；在隔离层102、第一牺牲层103和有源柱101的表面形成第二牺牲层104；去除第一牺牲层103，形成第一凹槽A；通过第一凹槽A，刻蚀部分有源柱101，形成环形凹槽B。
如图2c所示，在半导体衬底100的表面形成隔离层102。本公开实施例中，隔离层102的是为了隔离半导体衬底100和有源柱101，以防止半导体衬底100漏电。隔离层102的材料可以是氧化物或者氮氧化硅，例如为氧化硅。
如图2d所示，在隔离层102的表面形成覆盖部分有源柱101的第一牺牲层103。本公开实施例中，第一牺牲层103的高度h1小于有源柱101的高度h2，第一牺牲层103用于在后续工艺过程中定义位线结构的位置，因此，第一牺牲层103相对于半导体衬底100(或有源柱101)和隔离层102具有高湿法刻蚀选择比。第一牺牲层103的材料可以是氮化硅(SiN)、氮氧化硅(SiON)、无定型碳(Amorphous Carbon，a-C)或者碳氮氧化硅(SiOCN)中的一种或任意组合。
如图2e所示，在隔离层102、第一牺牲层103和有源柱101的表面形成第二牺牲层104。本公开实施例中，第二牺牲层104用于在形成位线结构时保护有源柱101，因此，第二牺牲层104相对于半导体衬底100(或有源柱101)和隔离层102具有高湿法刻蚀选择比，第二牺牲层104的材料可以是氮化硅、氮氧化硅、无定型碳或者碳氮氧化硅中的一种或任意组合。
需要说明的是，第一牺牲层103与有源柱101之间的刻蚀选择比大于第二牺牲层104与有源柱101之间的刻蚀选择比，即在相同的刻蚀条件下，第一牺牲层103比第二牺牲层104更容易被刻蚀去除。
如图2f所示，去除第一牺牲层103，形成第一凹槽A。本公开实施例中，可以采用湿法刻蚀技术去除第一牺牲层103，例如，采用浓硫酸、氢氟酸、浓硝酸等强酸刻蚀掉第一牺牲层103，形成第一凹槽A。
如图2g所示，通过第一凹槽A，刻蚀部分有源柱101，形成环形凹槽B。本公开实施例中，可以通过横向干法刻蚀技术，刻蚀去除部分有源柱101，形成环形凹槽B。环形凹槽B位于有源柱101的中下部，并未暴露出有源柱101的底表面和顶表面。
本公开实施例中，隔离层102、第一牺牲层103和第二牺牲层104均可以通过任意一种合适的沉积工艺形成，例如，化学气相沉积工艺(Chemical Vapor Deposition)、物理气相沉积(Physical Vapor Deposition，PVD)工艺、原子层沉积(Atomic Layer Deposition，ALD)工艺、旋涂工艺、涂敷工艺或者炉管工艺。
在一些实施例中，请参见图2h，在形成环形凹槽B之后，半导体结构的形成方法还包括：对位于环形凹槽B中间的、未被刻蚀的部分有源柱101进行第一重掺杂，形成第一重掺杂区117。本公开实施例中，第一重掺杂可以是对有源柱101进行P型掺杂，例如，在有源柱101中掺杂硼、镓、铟等三价杂质元素。
本公开实施例，形成第一重掺杂区117的目的是为了形成一个导电的通道，这个导电通道可以使得晶体管沟道中积累的空穴通过带间隧穿(Band to band tunneling)的方式进入半导体衬底100中，从而避免了寄生三极管的导通，提高了半导体结构的电性能。
接下来，可以参考图2i，执行步骤S103、在环形凹槽B中形成第一半导体层105，以形成半导体结构；第一半导体层105的禁带宽度小于有源柱101的禁带宽度。
本公开实施例中，第一半导体层105为半导体结构的源极。
在一些实施例中，第一半导体层105的形成过程可以包括以下步骤：在环形凹槽B中填充半导体材料，形成第一半导体层105；第一半导体层105充满环形凹槽B。本公开实施例中，形成第一半导体层105的半导体材料可以是锗化硅。
本公开实施例中，由于第一半导体层105的禁带宽度小于有源柱101的禁带宽度，因此，最终形成的半导体结构中晶体管的空穴电流增加，源极与半导体衬底100之间的势垒降低，导致晶体管沟道中积累的空穴很容易被驱散，寄生双极晶体管效应减弱，击穿电压上升，能够有效地抑制浮体效应的发生。
在一些实施例中，请继续参考图2i，在形成第一半导体层105之后，半导体结构的形成方法还包括：去除第二牺牲层104。
本公开实施例中，可以通过湿法刻蚀技术或者干法刻蚀技术(例如，等离子刻蚀技 术、离子铣技术或者反应离子刻蚀技术)去除第二牺牲层104。
在一些实施例中，请参考图2j和2k，半导体结构至少包括位线结构，步骤S103可以包括以下步骤：对第一半导体层105进行表面处理，形成第二半导体层106；在第二半导体层106的表面形成位线金属层107，以形成位线结构。
本公开实施例中，位线金属层107的材料包括：钨(W)、钴(Co)、铜(Cu)、铝(Al)、氮化钛(TiN)、含钛金属层、多晶硅或其任何组合。
在一些实施例中，对第一半导体层105进行表面处理，第二半导体层106可以通过以下步骤形成：在第一半导体层105表面淀积金属材料，形成金属层(图中未示出)；对金属层和第一半导体层105进行退火处理，形成第二半导体层106。
本公开实施例中，形成第二半导体层106的金属材料可以是钛(Ti)、钽(Ta)、镍(Ni)、钨、铂(Pt)以及钯(Pd)中的任意一种。通过在第一半导体层105的表面淀积金属材料，并通过快速热退火处理使金属材料与第一半导体层105相互反应，形成金属硅化物作为第二半导体层106。
本公开实施例中，通过第二半导体层106(即金属硅化物)连接位线结构(即位线金属层107)和第一半导体层105,，由于金属硅化物具有较低的阻值，因此可以降低位线金属层107与第一半导体层105之间的接触电阻，进而可以降低形成的半导体结构的功耗。
在一些实施例中，在形成位线结构之后，半导体结构的形成方法还包括：形成全环栅结构、存储节点接触和电容结构。
请参考图2l，全环栅30结构可以通过以下步骤形成：在位线结构之间的空隙、以及位线金属层107的表面形成覆盖部分有源柱101的第一绝缘层108；在第一绝缘层108和有源柱101的表面依次形成覆盖部分有源柱的栅极氧化层109和栅极金属层110，以形成全环栅结构30；其中，栅极氧化层109的顶表面低于有源柱101的顶表面。
本公开实施例中，第一绝缘层108一方面用于隔离相邻的位线结构，防止位线结构的漏电，进而无法实现对特定的晶体管进行读取或者写入操作；另一方面，第一绝缘层108还可以实现位线结构和后续形成全环栅结构之间的隔离作用。
本公开实施例中，可以通过任意一种合适的沉积工艺形成第一绝缘层108、栅极氧化层109和栅极金属层110。第一绝缘层108的材料可以是氮化硅；栅极氧化层109的材料可以是氧化物，例如为氧化硅；栅极金属层110的材料可以是任意一种导电性能较好的材料，例如为氮化钛。
本公开实施例中，全环栅结构30具有宽的沟道区，从而可以降低短沟道效应，提高栅极的控制能力，进而可以提高所形成的半导体结构的性能。
在一些实施例中，请继续参考图2l，在形成全环栅结构30以后，半导体结构的形成方法还包括：在全环栅结构30之间的空隙、栅极氧化层109的表面、以及栅极金属层110的表面形成覆盖部分有源柱101的第二绝缘层111。
本公开实施例中，第二绝缘层111一方面用于隔离相邻的全环栅30结构，防止相邻的全环栅结构30导通，进而无法实现对单个晶体管进行控制；另一方面，第二绝缘层111还可以实现全环栅结构30和后续形成电容结构之间的隔离作用。第二绝缘层111的材料可以是氮化硅、氧化硅或者氮氧化硅。
请参考图2m和2n，存储节点接触101b可以通过以下步骤形成：刻蚀有源柱101，形成第二凹槽C和环形柱101a，第二凹槽C的底表面与第二绝缘层111的顶表面平齐；对环形柱101a进行第二重掺杂，形成存储节点接触101b。
本公开实施例中，可以采用干法刻蚀工艺(例如等离子体刻蚀工艺、反应离子刻蚀工艺或者离子铣工艺)刻蚀有源柱101形成环形柱101a和第二凹槽C。第二重掺杂可 以是对环形柱101a进行N型掺杂，例如，在有源柱101中掺杂磷、锑、砷等五价杂质元素，提高环形柱101a的导电能力。
本公开实施例中，第一重掺杂与第二重掺杂的掺杂类型相反。
本公开实施例中，对环形柱101a进行第二重掺杂的目的是降低环形柱101a的内阻，提高存储节点接触101b的导电能力，进而降低所形成的存储节点接触101b与漏极和电容结构之间的接触电阻，提高半导体结构的电性能。
请继续参见图2n，位于第二绝缘层111投影区域中的有源柱101构成半导体结构的漏极D。
本公开实施例中，将存储节点接触做成中空结构，即在有源柱101中形成第二凹槽C是为了增大第二重掺杂的掺杂面积，即为了实现对环形柱101a进行更充分的重掺杂，进而降低存储节点接触101b与漏极D和电容结构之间的接触电阻。
在一些实施例中，请参考图2o，半导体结构的形成方法还包括：在第二凹槽中填充绝缘材料，形成第三绝缘层112。
本公开实施例中，第三绝缘层112充满第二凹槽，第三绝缘层112的顶表面与存储节点接触101b的顶表面平齐。绝缘材料可以是氧化物或者氮化物，例如氧化硅、氮化硅或者氮氧化硅。
本公开实施例中，第三绝缘层112位于存储节点接触101b的内部、且后续在第三绝缘层112和存储节点接触101b的表面会形成电容结构，第三绝缘层112可以防止电容结构的漏电。
在一些实施例中，请参考图2p，电容结构40可以通过以下步骤形成，在存储节点接触101b和第三绝缘层112的表面依次形成第一电极层113、电介质层114和第二电极层115，以形成电容结构40。
本公开实施例中，可以通过在存储节点接触101b和第三绝缘层112的表面依次沉积第一电极材料、电介质材料和第二电极材料，来形成第一电极层113、电介质层114和第二电极层115。其中，第一电极材料、电介质材料和第二电极材料可以通过以下任意一种沉积工艺形成：化学气相沉积工艺、物理气相沉积工艺、原子层沉积工艺。第一电极材料和第二电极材料可以包括金属氮化物或金属硅化物，例如，氮化钛。电介质材料可以包括高K介质材料，例如可以是氧化镧(La 2O 3)、氧化铝(Al 2O 3)、氧化铪(HfO 2)、氮氧化铪(HfON)、硅酸铪(HfSiO x)或氧化锆(ZrO 2)中的一种或任意组合。在其它实施例中，第一电极材料和第二电极材料还可以是多晶硅。
在一些实施例中，请参考图2q，半导体结构的形成方法还包括：在第二凹槽中填充导电材料，形成导电层116。
本公开实施例中，导电层116充满第二凹槽，导电层116的顶表面与存储节点接触101b的顶表面平齐。导电材料可以是钛、钽、镍、钨、铂、钯以及多晶硅以中的任意一种。
请参考图2r，电容结构40还可以通过以下步骤形成，在存储节点接触101b和导电层116的表面依次形成第一电极层113、电介质层114和第二电极层115，以形成电容结构40。
本公开实施例中，可以通过在存储节点接触101b和导电层116的表面依次沉积第一电极材料、电介质材料和第二电极材料，来形成第一电极层113、电介质层114和第二电极层115。第一电极材料和第二电极材料均可以包括金属氮化物或金属硅化物，例如，氮化钛。电介质材料可以包括高K介质材料，例如可以是氧化镧、氧化铝、氧化铪、氮氧化铪、硅酸铪或氧化锆中的一种或任意组合。其中，第一电极材料、电介质材料和第二电极材料可以通过以下任意一种沉积工艺形成：化学气相沉积工艺、物理气相沉积 工艺、原子层沉积工艺。第一电极材料和第二电极材料可以包括金属氮化物或金属硅化物，例如，氮化钛。电介质材料可以包括高K介质材料，例如可以是氧化镧、氧化铝、氧化铪、氮氧化铪、硅酸铪或氧化锆中的一种或任意组合。在其它实施例中，第一电极材料和第二电极材料还可以是多晶硅。
本公开实施例中，导电层116位于存储节点接触101b之间，存储节点接触101b和导电层116用于电连接半导体结构的漏极和电容结构，因此，导电层116可以提高存储节点接触101b的导电性，进而降低存储节点接触101b与电容结构之间的接触电阻，提高半导体结构的电性能。
需要说明的是，本公开实施例中，在每一有源柱的表面均形成了晶体管结构，说明书附图仅仅示出了一个晶体管的形成过程。
本公开实施例所形成的半导体结构，由于晶体管为竖直结构，如此，可以提高半导体结构的集成度，实现半导体结构尺寸的微缩。
本公开实施例中，将源极的有源柱减薄并进行P型重掺杂(即第一重掺杂)，形成一个导电通道，同时采用N型SiGe(即第一半导体层)代替有源柱作为源极，由于N型SiGe的禁带窄，空穴电流增加，因此，源极与半导体衬底之间的势垒降低，导致晶体管沟道中积累的空穴很容易被驱散，所以寄生双极晶体管效应减弱，击穿电压上升，有效地抑制了浮体效应的发生；另外，P型重掺杂可以使晶体管沟道中累积的空穴通过带间隧穿的方式进入半导体衬底，从而避免了寄生三极管的导通，提高了制备的半导体结构的电性能。
本公开实施例提供一种半导体结构，图3a为本公开实施例提供的半导体结构的三维结构示意图，图3b和3c为本公开实施例提供的图3a中的半导体结构沿b-b’的剖面图，如图3a～3c所示，半导体结构300包括：半导体衬底100和第一半导体层105。
其中，半导体衬底100上形成有多个沿X轴方向(第一方向)和Y轴方向(第二方向)排布的有源柱101；每一有源柱101包括一环形凹槽，环形凹槽未暴露出有源柱101的顶表面和底表面。
本公开实施例中，有源柱101用于形成半导体结构300的晶体管。有源柱可以是P型掺杂的硅柱，有源柱的禁带宽度位于1.0eV～1.3eV之间。
第一半导体层105位于环形凹槽中，且第一半导体层105的禁带宽度小于有源柱101的禁带宽度。
本公开实施例中，第一半导体层105可以作为晶体管的源极，第一半导体层105可以是N型掺杂的半导体层，例如，N型掺杂的硅锗层，第一半导体层105的禁带宽度位于0.7eV～0.97eV之间。
本公开实施例中，由于第一半导体层105的禁带宽度小于有源柱101的禁带宽度，如此，可以降低源极与半导体衬底之间的势垒，使得晶体管沟道中积累的空穴很容易被驱散，寄生双极晶体管效应减弱，能够有效地抑制半导体结构的浮体效应的发生，提高了半导体结构300的电性能。
在一些实施例中，请继续参考图3a～3c，半导体结构300还包括：第二半导体层106和位线金属层。其中，第二半导体层106位于第一半导体层105的表面、且位线金属层107位于第二半导体层106的表面。本公开实施例中，第二半导体层、位线金属层107构成位线结构。
本公开实施例中，第二半导体层106为金属硅化物层，由于金属硅化物具有较低的阻值，因此可以降低位线金属层107与第一半导体层105之间的接触电阻，进而可以降低半导体结构300的功耗。
在一些实施例中，请继续参考图3a～3c，半导体结构300还包括：全环栅结构30； 全环栅结构30位于部分有源柱101的表面，全环栅结构30包括栅极氧化层109和栅极金属层110。
本公开实施例中，全环栅结构30具有宽的沟道区，从而可以降低短沟道效应，提高栅极的控制能力，进而可以提高半导体结构300的性能。
在一些实施例中，请继续参考图3a～3c，半导体结构300还包括：第一绝缘层108和第二绝缘层111；其中，第一绝缘层108位于位线结构的表面、以及位线结构之间的空隙中；第二绝缘层111位于全环栅结构30的表面、以及全环栅结构30之间的空隙中。
本公开实施例中，第一绝缘层108一方面用于隔离相邻的位线结构，防止位线结构的漏电，进而无法实现对特定的晶体管进行读取或者写入操作；另一方面，第一绝缘层108还可以实现位线结构与全环栅结构30之间的隔离作用。第二绝缘层111一方面用于隔离相邻的全环栅30结构，防止相邻的全环栅结构30导通，进而无法实现对单个晶体管进行控制；另一方面，第二绝缘层111还可以实现全环栅结构30和电容结构之间的隔离作用。
在一些实施例中，请继续参考图3a～3c，半导体结构300还包括：存储节点接触101b和电容结构40；其中，电容结构40位于存储节点接触101b的表面、且电容结构40与存储节点接触101b电连接。
本公开实施例中，对有源柱101进行第二重掺杂构成存储节点接触101b，第二重掺杂可以是对环形柱101a进行N型掺杂，例如，在有源柱101中掺杂磷、锑、砷等五价杂质元素。第二重掺杂后形成的存储节点接触101b，具有较低的内阻和较高的导电性，使得存储节点接触101b与漏极和电容结构之间的接触电阻降低了，进而可以提高半导体结构300的电性能。
在一些实施例中，请继续参考图3b，半导体结构300还包括：第三绝缘层112；第三绝缘层112位于存储节点接触101b的内部；第三绝缘层112的顶表面与存储节点接触101b的顶表面平齐，且第三绝缘层112的底表面与存储节点接触101b的底表面平齐。
本公开实施例中，第三绝缘层112可以防止电容结构40的漏电。
在一些实施例中，请继续参考图3c，半导体结构300还包括：导电层116；导电层116位于存储节点接触101b的内部；导电层116的顶表面与存储节点接触101b的顶表面平齐，且导电层116的底表面与存储节点接触101b的底表面平齐。
本公开实施例中，导电层116可以提高存储节点接触101b的导电性，进而降低存储节点接触101b与电容结构40之间的接触电阻，提高半导体结构300的电性能。
在一些实施例中，请继续参考图3b和3c，半导体结构300还包括第一重掺杂区117；第一重掺杂区117是对第一半导体层105内部的有源柱101进行第一重掺杂形成的区域。本公开实施例中，第一重掺杂可以是对有源柱101进行P型掺杂，例如，在有源柱101中掺杂硼、镓、铟等三价杂质元素。第一重掺杂区117可以作为一个导电通道，使得晶体管沟道中积累的空穴通过带间隧穿的方式进入半导体衬底100中，从而避免了寄生三极管的导通，提高了半导体结构300的电性能。
在一些实施例中，请继续参考图3b和3c，半导体结构300还包括漏极D；位于第二绝缘层111投影区域的有源柱101构成半导体结构漏极D。
本公开实施例提供的半导体结构与上述实施例提供的半导体结构的形成方法类似，对于本公开实施例未详尽披露的技术特征，请参照上述实施例进行理解，这里，不再赘述。
本公开实施例提供的半导体结构，一方面由于晶体管为垂直结构，如此，可以提高半导体结构的集成度，实现半导体结构尺寸的微缩；另一方面，由于半导体结构中第一半导体层的禁带宽度小于有源柱的禁带宽度，因此，晶体管的空穴电流增加，源极与半 导体衬底之间的势垒降低，导致晶体管沟道中积累的空穴很容易被驱散，寄生双极晶体管效应减弱，击穿电压上升，能够有效地抑制浮体效应的发生，提高半导体结构的性能。
在本公开所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过非目标的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。
本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上所述，仅为本公开的一些实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
本公开实施例中，第一半导体层可以作为晶体管的源极，由于第一半导体层的禁带宽度小于有源柱的禁带宽度，因此，源极与半导体衬底之间的势垒降低，沟道中积累的空穴很容易被导出，寄生双极晶体管效应减弱，能够有效地抑制所形成的半导体结构浮体效应的发生，提高了半导体结构的电性能和制备良率。

Claims (23)

  1. 一种半导体结构的形成方法，所述方法包括：
    提供半导体衬底，所述半导体衬底包括多个间隔排布的有源柱；
    刻蚀所述有源柱，形成环形凹槽；所述环形凹槽未暴露出所述有源柱的顶表面和底表面；
    在所述环形凹槽中形成第一半导体层，以形成所述半导体结构；其中，所述第一半导体层的禁带宽度小于所述有源柱的禁带宽度。
  2. 根据权利要求1所述的方法，其中，所述在所述环形凹槽中形成第一半导体层，以形成所述半导体结构，包括：
    对所述第一半导体层进行表面处理，形成第二半导体层；
    在所述第二半导体层的表面形成位线金属层，以形成位线结构。
  3. 根据权利要求2所述的方法，其中，所述刻蚀所述有源柱，形成环形凹槽，包括：
    在所述半导体衬底的表面形成隔离层；
    在部分所述隔离层的表面形成覆盖部分所述有源柱的第一牺牲层；
    在所述隔离层、所述第一牺牲层和所述有源柱的表面形成第二牺牲层；
    去除所述第一牺牲层，形成第一凹槽；
    通过所述第一凹槽，刻蚀部分所述有源柱，形成所述环形凹槽。
  4. 根据权利要求3所述的方法，其中，所述第一牺牲层与所述有源柱之间的刻蚀选择比大于所述第二牺牲层与所述有源柱之间的刻蚀选择比。
  5. 根据权利要求3所述的方法，其中，在形成所述第一半导体层之后，且在形成所述第二半导体层之前，所述方法还包括：
    去除所述第二牺牲层。
  6. 根据权利要求5所述的方法，其中，所述对所述第一半导体层进行表面处理，形成所述第二半导体层，包括：
    在所述第一半导体层表面淀积金属材料，形成金属层；
    对所述金属层和所述第一半导体层进行退火处理，形成所述第二半导体层。
  7. 根据权利要求1至6任一项所述的方法，其中，在形成所述第一半导体层之前，所述方法还包括：
    对位于所述环形凹槽中间的、未被刻蚀的部分有源柱进行第一重掺杂，形成第一重掺杂区。
  8. 根据权利要求7所述的方法，其中，所述方法还包括：
    形成全环栅结构、存储节点接触和电容结构。
  9. 根据权利要求8所述的方法，其中，所述全环栅结构通过以下步骤形成：
    在所述位线结构之间的空隙、以及所述位线金属层的表面形成覆盖部分所述有源柱的第一绝缘层；
    在所述第一绝缘层的表面依次形成覆盖部分有源柱的栅极氧化层和栅极金属层，以形成所述全环栅结构。
  10. 根据权利要求9所述的方法，其中，在形成所述全环栅结构以后，所述方法还包括：
    在所述全环栅结构之间的空隙、所述栅极氧化层的表面、以及所述栅极金属层的表面形成覆盖部分所述有源柱的第二绝缘层。
  11. 根据权利要求10所述的方法，其中，所述存储节点接触通过以下步骤形成：
    刻蚀所述有源柱，形成第二凹槽和环形柱，所述第二凹槽的底表面与所述第二绝缘层的顶表面平齐；
    对所述环形柱进行第二重掺杂，形成所述存储节点接触。
  12. 根据权利要求11所述的方法，其中，所述第一重掺杂与所述第二重掺杂的掺杂类型相反。
  13. 根据权利要求11或12所述的方法，其中，所述方法还包括：
    在所述第二凹槽中填充绝缘材料，形成第三绝缘层；或者，
    在所述第二凹槽中填充导电材料，形成导电层。
  14. 根据权利要求13所述的方法，其中，所述电容结构通过以下步骤形成：
    在所述存储节点接触和所述第三绝缘层的表面依次形成第一电极层、电介质层和第二电极层，以形成所述电容结构。
  15. 根据权利要求13所述的方法，其中，所述电容结构通过以下步骤形成：
    在所述存储节点接触和所述导电层的表面依次形成第一电极层、电介质层和第二电极层，以形成所述电容结构。
  16. 一种半导体结构，所述半导体结构通过上述权利要求1至15任一项提供的半导体结构的形成方法形成，包括：
    半导体衬底，所述半导体衬底上形成有多个间隔排布的有源柱；每一所述有源柱包括一环形凹槽，所述环形凹槽未暴露出所述有源柱的顶表面和底表面；
    第一半导体层，所述第一半导体层位于所述环形凹槽中，且所述第一半导体层的禁带宽度小于所述有源柱的禁带宽度。
  17. 根据权利要求16所述的半导体结构，其中，所述半导体结构还包括：第二半导体层和位线金属层；
    其中，所述第二半导体层位于所述第一半导体层的表面、且所述位线金属层位于所述第二半导体层的表面。
  18. 根据权利要求17所述的半导体结构，其中，所述半导体结构还包括：全环栅结构；
    所述全环栅结构位于部分所述有源柱的表面，所述全环栅结构包括栅极氧化层和栅极金属层。
  19. 根据权利要求18所述的半导体结构，其中，所述半导体结构还包括：第一绝缘层和第二绝缘层；
    其中，所述第一绝缘层位于所述位线结构的表面、以及所述位线结构之间的空隙中；
    所述第二绝缘层位于所述全环栅结构的表面、以及所述全环栅结构之间的空隙中。
  20. 根据权利要求16至19任一项所述的半导体结构，其中，所述半导体结构还包括：存储节点接触和电容结构；
    其中，所述电容结构位于所述存储节点接触的表面、且所述电容结构与所述存储节点接触电连接。
  21. 根据权利要求20所述的半导体结构，其中，所述半导体结构还包括：第三绝缘层；
    其中，所述第三绝缘层位于所述存储节点接触的内部，且所述第三绝缘层的顶表面与所述存储节点接触的顶表面平齐。
  22. 根据权利要求20所述的半导体结构，其中，所述半导体结构还包括：导电层；
    所述导电层位于所述存储节点接触的内部，且所述导电层的顶表面与所述存储节点接触的顶表面平齐。
  23. 根据权利要求21或22所述的半导体结构，其中，所述半导体结构还包括：第一重掺杂区；
    其中，所述第一重掺杂区位于所述第一半导体层的内部。
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