WO2024045210A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2024045210A1
WO2024045210A1 PCT/CN2022/117852 CN2022117852W WO2024045210A1 WO 2024045210 A1 WO2024045210 A1 WO 2024045210A1 CN 2022117852 W CN2022117852 W CN 2022117852W WO 2024045210 A1 WO2024045210 A1 WO 2024045210A1
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gate
layer
dielectric layer
conductive layer
gate conductive
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PCT/CN2022/117852
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English (en)
French (fr)
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廖昱程
刘文杰
文浚硕
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长鑫科技集团股份有限公司
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Priority to US18/162,818 priority Critical patent/US20240074143A1/en
Publication of WO2024045210A1 publication Critical patent/WO2024045210A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a semiconductor structure and a method of forming the same.
  • DRAM Dynamic Random Access Memory
  • the length of the gate channel also shrinks, so that the gate induced drain leakage current (Gate Induced Drain Leakage, GIDL ) becomes larger and larger, and the gate control ability gradually weakens.
  • GIDL Gate Induced Drain Leakage
  • embodiments of the present disclosure provide a semiconductor structure and a method of forming the same.
  • embodiments of the present disclosure provide a semiconductor structure, including: a gate structure located on a substrate;
  • the gate structure includes at least two gate conductive layers
  • the at least two gate conductive layers have the same composition and different characteristic parameters; the characteristic parameters include at least one of thickness, component content or shape.
  • the gate structure further includes: a first semiconductor layer and a first conductor layer located on the surface of the at least two gate conductive layers.
  • the first surface and the second surface of each layer of the gate conductive layer along the thickness direction of the substrate have a preset shape; the preset shape includes a planar shape and an arc shape.
  • the components in each layer of the gate conductive layer include nitrogen components and metal components; wherein the concentration of the nitrogen component in each layer of the gate conductive layer is different.
  • the gate structure further includes: a first gate dielectric layer and a second gate dielectric layer;
  • the second gate dielectric layer is located between the gate conductive layer and the first gate dielectric layer, and the second gate dielectric layer includes N-type doped silicon carbide.
  • the substrate includes a plurality of gate trenches
  • the first gate dielectric layer is located on the inner wall of the gate trench, and the at least two gate conductive layers are located at the bottom of the gate trench with the second gate dielectric layer;
  • the size of the at least two gate conductive layers is smaller than the size of the gate trench.
  • the work functions of the at least two gate conductive layers gradually decrease from the bottom of the gate trench to the top of the gate trench.
  • the first gate dielectric layer located at the bottom of the gate trench has a first thickness
  • the first gate dielectric layer located at the sidewalls of the gate trench has a second thickness.
  • the second thickness is greater than the first thickness
  • the second gate dielectric layer located at the bottom of the gate trench has a third thickness
  • the second gate dielectric layer located at the sidewall of the gate trench has a fourth thickness.
  • the fourth thickness is greater than the third thickness
  • the semiconductor structure further includes a gate insulating layer
  • the gate insulating layer is located on the surface of the first gate dielectric layer and the gate conductive layer, and the top surface of the gate insulating layer is flush with the top surface of the substrate.
  • the substrate further includes a source electrode and a drain electrode, wherein the source electrode and/or the drain electrode include: a first doped region and a surface located on the first doped region The second doped region;
  • the doping concentration of the second doping region is greater than the doping concentration of the first doping region, and the work function of the second gate dielectric layer is less than the work function of the second doping region.
  • the substrate includes a plurality of well regions, and the well regions serve as sources or drains of transistors;
  • the second gate dielectric layer is located on the upper surface of the substrate and between the source electrode and the drain electrode;
  • the first gate dielectric layer is located between the second gate dielectric layer and the substrate.
  • the substrate includes a plurality of mutually isolated active pillars
  • the first gate dielectric layer, the second gate dielectric layer and the at least two gate conductive layers sequentially annularly cover part of the active pillar, and the remaining active pillar serves as the source or source of the transistor. drain.
  • embodiments of the present disclosure provide a method for forming a semiconductor structure, the method including:
  • At least two gate conductive layers are formed on the substrate to form a gate structure; wherein the at least two gate conductive layers have the same composition and different characteristic parameters; the characteristic parameters include thickness, At least one of component content or shape.
  • the method before forming the at least two gate conductive layers, the method further includes:
  • a first gate dielectric layer and a second gate dielectric layer located between the gate conductive layer and the first gate dielectric layer are formed in sequence.
  • the method before forming the gate structure, the method further includes:
  • the substrate is doped to form a first doped region and a second doped region located on the surface of the first doped region.
  • the doping concentration of the second doped region is greater than that of the first doped region. doping concentration;
  • the work function of the second gate dielectric layer is smaller than the work function of the second doped region.
  • the gate structure is formed in a gate trench of the substrate; the gate structure at least includes a first gate conductive layer and a second gate conductive layer.
  • the pole structure is formed by the following steps:
  • the first gate dielectric layer and the second initial gate dielectric layer are sequentially formed on the inner wall of the gate trench;
  • the second initial gate conductive layer and the second initial gate dielectric layer are etched back to expose part of the first gate dielectric layer to form the second gate conductive layer and the second gate electrode. media layer.
  • the method further includes:
  • a gate insulating layer is formed on the surface of the second gate dielectric layer and the gate conductive layer; the top surface of the gate insulating layer is flush with the top surface of the substrate.
  • the substrate includes a plurality of well regions; the gate structure is formed on the substrate surface between two adjacent well regions; the gate structure at least includes a first layer of gate electrode A conductive layer and a second gate conductive layer, the gate structure is formed by the following steps:
  • first initial gate dielectric layer Form a first initial gate dielectric layer, a second initial gate dielectric layer, a first initial gate conductive layer and a second initial gate conductive layer on the surface of the substrate in order from bottom to top;
  • the second initial gate conductive layer, the first initial gate conductive layer, the second initial gate dielectric layer and the first initial gate conductive layer are etched sequentially through a mask with a preset window.
  • the gate structure includes at least a first gate conductive layer and a second gate conductive layer, and the gate structure is formed around each active pillar in the substrate;
  • the gate structure is formed by the following steps:
  • a first initial gate dielectric layer, a second initial gate dielectric layer, a first initial gate conductive layer and a second initial gate conductive layer are formed on the sidewalls of the active pillars in sequence from the inside to the outside;
  • the first initial gate dielectric layer, the second initial gate dielectric layer, the first initial gate conductive layer and the second initial gate conductive layer are etched back to expose part of the Source pillars form the first gate dielectric layer, the second gate dielectric layer, the first gate conductive layer and the second gate conductive layer.
  • Embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, wherein the semiconductor structure includes a gate structure located on a substrate, because the gate structure includes at least two gate conductive layers, and the at least two gate conductive layers have The same components and different characteristic parameters.
  • the characteristic parameters include thickness, component content or shape. In this way, different thicknesses, different component contents or different shapes make the work function and threshold voltage of each gate conductive layer in the gate structure All become adjustable, thereby effectively reducing the gate-induced drain leakage current of the semiconductor structure and improving the performance of the semiconductor structure.
  • Figure 1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 2a is a schematic structural diagram of a semiconductor structure with a buried gate structure provided by an embodiment of the present disclosure
  • Figure 2b is a second structural schematic diagram of a semiconductor structure with a buried gate structure provided by an embodiment of the present disclosure
  • Figure 3 is a schematic structural diagram of a semiconductor structure with a planar gate structure provided by an embodiment of the present disclosure
  • Figure 4a is a schematic structural diagram 1 of a semiconductor structure with a full gate all-around provided by an embodiment of the present disclosure
  • Figure 4b is a second structural schematic diagram of a semiconductor structure with a full gate all-around provided by an embodiment of the present disclosure
  • Figure 5 is a schematic flowchart of a method for forming a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 6a is a structural schematic diagram 1 of the semiconductor structure formation process provided by an embodiment of the present disclosure.
  • Figure 6b is a second structural schematic diagram of the semiconductor structure formation process provided by an embodiment of the present disclosure.
  • Figure 6c is a structural schematic diagram three of the semiconductor structure formation process provided by the embodiment of the present disclosure.
  • Figure 6d is a structural schematic diagram 4 of the semiconductor structure formation process provided by an embodiment of the present disclosure.
  • Figure 6e is a schematic diagram 5 of a structure during the formation of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 6f is a schematic diagram 6 of the structure during the formation of a semiconductor structure provided by an embodiment of the present disclosure.
  • Figure 6g is a schematic diagram 7 of the structure during the formation of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • the semiconductor structure 100 includes: a gate structure 20 located on a substrate 10; 20 includes at least two gate conductive layers; wherein the at least two gate conductive layers have the same composition and different characteristic parameters; the characteristic parameters include at least one of thickness, component content, or shape.
  • the substrate may be a silicon substrate, and the substrate may also include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), Gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), Aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and/or gallium indium arsenide phosphide (GaInAsP), or combinations thereof.
  • the substrate may also be an N-type doped or P-type doped substrate.
  • the gate structure 20 includes at least two gate conductive layers. For example, it may include 2, 3, 5, 6 or more layers. In the embodiment of the present disclosure, the gate structure 20 includes multiple gate conductive layers. By matching each other and adjusting the composition and concentration changes between the gate conductive layers, the threshold voltage (Threshold Voltage, Vt) of the gate structure at different positions in the substrate can be effectively adjusted, as well as the work function of the gate structure. , thereby improving the gate induced drain leakage (GIDL), which can adapt to the increasingly smaller size of semiconductor memory devices and have higher efficiency and higher density. Further, in a specific embodiment, the gate conductive layer is composed of a nitrogen component and a metal component.
  • the metal component in the gate conductive layer can be, for example, tungsten (W), cobalt (Co), or titanium. (Ti), tantalum (Ta), the content or concentration of the nitrogen component in each gate conductive layer is different, so that the carrier concentration in the metal component is different. In this way, the concentration of the nitrogen component can be adjusted to change the resistance and work function.
  • the gate structure 20 includes, for example, two gate conductive layers, namely a first gate conductive layer 201 a and a second gate conductive layer 201 b.
  • the first gate conductive layer 201a and the second gate conductive layer 201b have the same composition.
  • the first gate conductive layer 201a and the second gate conductive layer 201b may both be titanium nitride.
  • the first gate conductive layer 201a and the second gate conductive layer 201b may both be titanium-containing metal layers, wherein the titanium-containing metal layer may be a composite layer of a titanium nitride layer and a titanium metal layer.
  • the thicknesses of the first gate conductive layer 201a and the second gate conductive layer 201b are different. , or the first gate conductive layer 201a and the second gate conductive layer 201b have different component contents (such as Ti content, N content), or the first gate conductive layer 201a and the second gate conductive layer
  • Different shapes of the conductive layer 201b for example, the surface of the first gate conductive layer 201a is arc-shaped, and the surface of the second gate conductive layer 201b is planar and arc-shaped) will make the first gate conductive layer.
  • the work functions of the layer 201a and the second gate conductive layer 201b are adjustable, so that the threshold voltage of the gate structure in the embodiment of the present disclosure is adjustable. In this way, the gate-induced drain leakage of the semiconductor structure can be effectively reduced. current to improve the retention performance of the semiconductor structure.
  • the gate structure 20 further includes a first gate dielectric layer 203 and a second gate dielectric layer 202 ; the second gate dielectric layer 202 is located on the gate conductive layer (i.e., the first gate dielectric layer 203 ). between the first gate conductive layer 201a and the second gate conductive layer 201b) and the first gate dielectric layer 203.
  • the second gate dielectric layer 202 includes N-type doped silicon carbide.
  • the first gate dielectric layer 203 may be a silicon oxide layer. Since both the second gate dielectric layer 202 and the first gate dielectric layer 203 contain tetravalent silicon, the second gate dielectric layer 202 and the first gate dielectric layer 203 will be combined more closely, thereby making the second gate dielectric layer 202 and the first gate dielectric layer 203 more tightly combined. The defects between the gate dielectric layer and the first gate dielectric layer are smaller, which further reduces the gate-induced drain leakage current of the gate structure and improves the electrical performance of the semiconductor structure.
  • the semiconductor structure 100 further includes a gate insulating layer 204 located on the surface of the second gate dielectric layer 202 and the first gate dielectric layer 203 , wherein the top of the gate insulating layer 204 The surface is flush with the top surface of substrate 10 .
  • the gate insulating layer 204 may be silicon nitride or silicon oxide.
  • the semiconductor structure 100 may also include a bit line structure, a capacitor structure or other functional structures.
  • the gate structure in the semiconductor structure may be a buried gate structure. In other embodiments, the gate structure in the semiconductor structure may also be a flat gate (Flat Gate) structure or an ⁇ gate. (Omega Gate) structure, Gate All Around (GAA) structure or Double Gate (Double Gate) structure.
  • the semiconductor structure 100 includes: a gate structure 20 located on the substrate 10 ;
  • the gate structure 20 includes, for example, three gate conductive layers, namely a first gate conductive layer 201a, a second gate conductive layer 201b and a third gate conductive layer 201c; wherein, the first gate conductive layer
  • the conductive layer 201a, the second gate conductive layer 201b and the third gate conductive layer 201c have the same composition
  • the first gate conductive layer 201a, the second gate conductive layer 201b and the third gate conductive layer 201a have the same composition.
  • the extremely conductive layer 201c has different characteristic parameters; for example, the first gate conductive layer 201a, the second gate conductive layer 201b and the third gate conductive layer 201c have different thicknesses, or the first gate conductive layer 201c has different characteristic parameters.
  • the conductive layer 201a, the second gate conductive layer 201b and the third gate conductive layer 201c have different component contents, or the first gate conductive layer 201a, the second gate conductive layer 201b and the third gate conductive layer 201c have different composition contents.
  • the layer gate conductive layer 201c has different shapes.
  • the first gate conductive layer 201a, the second gate conductive layer 201b and the third gate conductive layer 201c have the same composition.
  • the first gate conductive layer 201a, the second gate conductive layer 201c have the same composition.
  • the gate conductive layer 201b and the third gate conductive layer 201c may both be titanium nitride, and the first gate conductive layer 201a, the second gate conductive layer 201b and the third gate conductive layer 201c
  • the components all include nitrogen components and metal titanium components, and the nitrogen components in the first gate conductive layer 201a, the second gate conductive layer 201b, and the third gate conductive layer 201c are different.
  • Three layers of titanium nitride with appropriate word line resistance are used as the gate conductive layer, which will not cause capacitive resistance delay.
  • the gate structure 20 may also include a second gate dielectric layer 202 and a first gate dielectric layer 203; a first gate conductive layer 201a, a second gate conductive layer
  • the gate conductive layer 201b and the third gate conductive layer 201c are located on the surface of the second gate dielectric layer 202, and the second gate dielectric layer 202 is located on the surface of the first gate dielectric layer 203.
  • the substrate 10 includes multiple gate trenches (only one gate trench is shown in FIGS. 2a and 2b ); the first gate dielectric layer 203 is located on the inner wall of the gate trench, and the first layer of gate conductive layer 201a, the second layer of gate conductive layer 201b and the third layer of gate conductive layer 201c are located on the inner wall of the gate trench with the first gate dielectric layer 203 bottom.
  • the total size D1 of the first gate conductive layer 201a, the second gate conductive layer 201b and the third gate conductive layer 201c is smaller than the size D2 of the gate trench. .
  • the work function of the gate conductive layer gradually decreases in a direction from the bottom of the gate trench to the top of the gate trench.
  • the work function is located at The first gate conductive layer at the bottom has the largest work function, and the second gate conductive layer at the top is the smallest.
  • the work function at the bottom is the largest.
  • the work functions of the first gate conductive layer 201a, the second gate conductive layer 201b in the middle layer, and the third gate conductive layer 201c on the top layer gradually decrease.
  • the work function of each gate conductive layer can be adjusted accordingly by adjusting the nitrogen component concentration of the gate conductive layer in each layer, so that in the gate structure, along the gate trench, In the direction from the bottom to the top of the gate trench, the work function of the gate conductive layer gradually decreases, so that the bottom gate conductive layer (such as TiN gate electrode) has the highest work function, and the top gate conductive layer (such as TiN gate electrode) has the highest work function. For example, TiN gate electrode) has the lowest work function.
  • This combination can not only solve row hammering (Row hammer), but also improve the gate induced drain leakage current (GIDL) problem. At the same time, this combination makes the resistance of the gate structure lower.
  • the semiconductor structure in the embodiment of the present disclosure is a dynamic random access memory
  • the DRAM programming and erasing processes both need to operate through the word line (ie, the gate structure)
  • the word line of a DRAM memory cell keeps repeating operations At this time, the charge in the adjacent memory cell may be attracted and the data will be lost. This will lead to serious row hammering problems.
  • the work function of the gate conductive layer and the threshold voltage of the gate structure are adjusted by arranging multi-layer gate conductive layers with different thicknesses, different component contents, or different shapes, so that along the gate trench From the bottom to the top of the gate trench, the work functions of at least two gate conductive layers decrease sequentially (that is, the threshold voltage decreases sequentially).
  • the Row hammer phenomenon in DRAM can be effectively suppressed; in addition, it can also be improved.
  • GIDL compared with the Hybrid Burried Word-Line (HBW) in related technologies, the resistance of the modulated metal gate word line is lower and the resistance-capacitance delay phenomenon is better.
  • the first gate dielectric layer located at the bottom of the gate trench has a first thickness
  • the first gate dielectric layer located at the sidewall of the gate trench has a second thickness
  • the second thickness is greater than the first thickness.
  • a first gate dielectric layer with low step coverage is formed in the gate trench, that is, the thickness of the first gate dielectric layer at the bottom of the gate trench is smaller than that of the sidewalls of the gate trench.
  • the thickness of the first gate dielectric layer on the one hand, can reduce the gate-induced drain leakage current and improve the gate control capability.
  • the first gate dielectric layer at the bottom of the trench can be made relatively thin, which can The gate conductive layer leaves enough space to improve the conductivity of the gate channel.
  • a relatively uniform first gate dielectric layer may also be formed in the gate trench, that is, the first gate dielectric layer located at the bottom of the gate trench and the first gate dielectric layer located at the bottom of the gate trench
  • the first gate dielectric layer on the sidewall has the same thickness.
  • the second gate dielectric layer 202 is located in the gate trench, and the second gate dielectric layer 202 is located between the first gate conductive layer 201a and the first gate trench. between the gate dielectric layer 203, the second gate conductive layer 201b and the first gate dielectric layer 203, and between the third gate conductive layer 201c and the first gate dielectric layer 203.
  • the second gate dielectric layer located at the bottom of the gate trench has a third thickness
  • the second gate dielectric layer located at the sidewall of the gate trench has a fourth thickness
  • the fourth thickness is greater than the third thickness.
  • a second gate dielectric layer with low step coverage is formed in the gate trench, that is, the thickness of the second gate dielectric layer at the bottom of the gate trench is smaller than that of the sidewalls of the gate trench.
  • the thickness of the second gate dielectric layer on the one hand, can reduce the gate-induced drain leakage current and improve the gate control capability.
  • the second gate dielectric layer at the bottom of the trench can be made relatively thin, which can The gate conductive layer leaves enough space to improve the conductivity of the gate channel.
  • a relatively uniform second gate dielectric layer can also be formed in the gate trench, that is, the second gate dielectric layer located at the bottom of the gate trench and the second gate dielectric layer located at the bottom of the gate trench.
  • the second gate dielectric layer on the sidewall has the same thickness.
  • the semiconductor structure 100 further includes a gate insulating layer 204; the gate insulating layer 204 is located in the first gate dielectric layer 203 and the gate conductive layer (ie, the third gate layer). The top surface of the gate insulating layer 204 is flush with the top surface of the substrate 10 .
  • the substrate 10 further includes a first doped region 205 and a second doped region 206 located on the surface of the first doped region 205;
  • the doping concentration is greater than that of the first doping region 205 , and the gate trench penetrates the second doping region 206 and the first doping region 205 , and the bottom of the gate trench is located in the substrate 10 .
  • the first doped region 205 and the second doped region 206 together form the source and drain of the semiconductor structure.
  • the work function of the second gate dielectric layer 202 is smaller than the work function of the second doped region 206.
  • the second gate dielectric layer 202 can be, for example, N-type doped silicon carbide.
  • the work function ( ⁇ ) of silicon carbide (N+SiC) is 3.1 electron volts (eV);
  • the second doped region 206 can be an N-type doped silicon substrate, and the N-type doped silicon substrate (N+Si ) has a work function ( ⁇ ) of 4.17eV.
  • the work function of the second gate dielectric layer is smaller than the work function of the second doped region, which can reduce interband leakage that causes gate-induced drain leakage current and improve the electrical performance of the semiconductor structure. .
  • a first doped region and a second doped region with different concentrations are provided.
  • the first doped region is an N-type lightly doped region, which can effectively reduce the cost between the gate and the source or between the gate and the drain.
  • the electric field between the electrodes improves GIDL and reduces the drain current.
  • the substrate 10 may also include only the second doped region 206, and the second doped region 206 constitutes the source and drain of the semiconductor structure.
  • the gate structure 20 also includes: a first semiconductor layer 301 and a first conductor layer 302.
  • the first semiconductor layer 301 is located on the outermost gate conductive layer, for example, on the third gate conductive layer 201c.
  • the first semiconductor layer 301 is used to connect the third gate conductive layer 201c and the first conductor layer 302.
  • the first semiconductor layer 301 can be a metal silicide layer. Since metal silicide has a lower resistance, the contact resistance between the third gate conductive layer 201c and the first conductor layer 302 can be reduced, so that further Reduce power consumption in semiconductor structures.
  • the first conductor layer 302 may be a polysilicon layer or any metal layer, for example, any one or any combination of cobalt, titanium, tantalum, nickel (Ni), tungsten, platinum (Pt) and palladium (Pd). .
  • the gate insulating layer 204 is also located on the surfaces of the first gate dielectric layer 203 and the first conductor layer 302, and the top surface of the gate insulating layer 204 is in contact with the top surface of the substrate 10. The surface is flush.
  • each gate conductive layer has a preset shape on the first surface and the second surface along the substrate thickness direction; the preset shape includes a planar shape, and/or an arc shape, such as an arc shape. It is an ⁇ shape and a concave shape.
  • the first gate conductive layer 201a, the second gate conductive layer 201b and the third gate conductive layer 201c are all on both surfaces along the thickness direction (X-axis direction) of the substrate 10. arc.
  • the first gate conductive layer 201a has an arc shape and a planar shape respectively on the first surface and the second surface along the X-axis direction.
  • the second gate conductive layer 201b and the third gate conductive layer 201a are respectively
  • the layer 201c has a planar shape on both surfaces along the X-axis direction.
  • each gate conductive layer has an arc or a planar shape.
  • the gate conductive layer has an arc surface, there can be more gate dielectric layer materials on both sides of the gate conductive layer, so that Increase the distance between the gate conductive layer and the source and drain to improve leakage current problems such as GIDL.
  • the two surfaces of the gate insulating layer 204 along the substrate thickness direction may be arc-shaped and planar respectively (as shown in FIG. 2a) or both may be planar. shape (as shown in Figure 2b).
  • the first gate conductive layer 201a, the second gate conductive layer 201b and the third gate conductive layer 201c have the same composition.
  • the gate conductive layer 201b and the third gate conductive layer 201c have different characteristic parameters (such as at least one of thickness, component content, and shape), so that the first gate conductive layer 201a and the second gate conductive layer 201c have different characteristic parameters (such as at least one of thickness, component content, and shape).
  • the work functions of the conductive layer 201b and the third gate conductive layer 201c are adjustable, thereby making the threshold voltage of the gate structure in the embodiment of the present disclosure adjustable. In this way, the gate-induced drain of the semiconductor structure can be effectively reduced. leakage current and improve the retention performance of the semiconductor structure.
  • FIG 3 is a schematic structural diagram of a semiconductor structure with a planar gate structure provided by an embodiment of the present disclosure.
  • the semiconductor structure 100 includes: a gate structure 20 located on a substrate 10; the gate structure 20 includes three layers
  • the gate conductive layers are respectively the first gate conductive layer 201a, the second gate conductive layer 201b and the third gate conductive layer 201c; among which, the first gate conductive layer 201a, the second gate conductive layer 201c
  • the conductive layer 201b and the third gate conductive layer 201c have the same composition, and the first gate conductive layer 201a, the second gate conductive layer 201b and the third gate conductive layer 201c have different characteristic parameters.
  • the first gate conductive layer 201a, the second gate conductive layer 201b and the third gate conductive layer 201c have different thicknesses, or the first gate conductive layer 201a, the second gate conductive layer 201c have different thicknesses;
  • the conductive layer 201b and the third gate conductive layer 201c have different component contents, or the first gate conductive layer 201a, the second gate conductive layer 201b and the third gate conductive layer 201c have different compositions. shape.
  • the gate structure 20 may also include a second gate dielectric layer 202 and a first gate dielectric layer 203; a first gate conductive layer 201a, a second gate conductive layer
  • the layer 201b and the third gate conductive layer 201c are both located on the surface of the second gate dielectric layer 202, and the second gate dielectric layer 202 is located on the surface of the first gate dielectric layer 203.
  • the work function of the second gate dielectric layer 202 is smaller than the work function of the substrate 10 . In this way, the gate-induced drain leakage current of the gate structure can be further reduced and the electrical performance of the semiconductor structure can be improved.
  • the substrate 10 includes multiple well regions (only two well regions are shown in FIG. 3 ), and the two adjacent well regions can serve as the source 207 or drain of the transistor. Extreme 208.
  • the second gate dielectric layer 202 is located on the upper surface of the substrate 10 and between the source electrode 207 and the drain electrode 208 ; the first gate dielectric layer 203 is located on the second gate electrode. between the polar dielectric layer 202 and the substrate 10 .
  • the semiconductor The structure 100 includes: a gate structure 20 located on the substrate 10; the gate structure 20 includes two gate conductive layers, namely a first gate conductive layer 201a and a second gate conductive layer 201b; wherein, the gate conductive layer 201a and the gate conductive layer 201b.
  • One gate conductive layer 201a and the second gate conductive layer 201b have the same composition, and the first gate conductive layer 201a and the second gate conductive layer 201b have different characteristic parameters; the characteristic parameters include thickness , component content or shape.
  • the gate structure 20 may also include a second gate dielectric layer 202 and a first gate dielectric layer 203; a first gate conductive layer 201a and a second layer.
  • the gate conductive layer 201b is located on the surface of the second gate dielectric layer 202, and the second gate dielectric layer 202 is located on the surface of the first gate dielectric layer 203.
  • the work function of the second gate dielectric layer 202 is smaller than the work function of the substrate 10 . In this way, the gate-induced drain leakage current of the gate structure can be further reduced and the electrical performance of the semiconductor structure can be improved.
  • the substrate 10 includes a plurality of mutually isolated active pillars 101 (only one active pillar is shown in Figures 4a and 4b); the first gate dielectric layer 203.
  • the second gate dielectric layer 202, the first gate conductive layer 201a and the second gate conductive layer 201b sequentially annularly cover part of the active pillars 101, and the remaining active pillars 101 serve as the source or drain of the transistor. .
  • the characteristic parameters of the first gate conductive layer 201a and the second gate conductive layer 201b are (for example, at least one of thickness, component content, surface shape) is different, so that the work function of the first gate conductive layer 201a and the second gate conductive layer 201b is adjustable, and makes the work function in the embodiment of the present disclosure adjustable.
  • the threshold voltage of the gate structure is adjustable. In this way, leakage current problems such as GIDL of the semiconductor structure can be effectively reduced, and the retention performance of the semiconductor structure can be improved.
  • FIG. 5 is a schematic flowchart of a method for forming a semiconductor structure provided by an embodiment of the disclosure. As shown in Figure 5, the method for forming a semiconductor structure includes the following steps. :
  • Step S501 Provide a substrate.
  • the substrate may be an N-type doped silicon substrate or a P-type doped silicon substrate.
  • Step S502 Form at least two gate conductive layers on the substrate to form a gate structure; wherein the at least two gate conductive layers have the same composition and different characteristic parameters; the characteristic parameters include thickness, component content or at least one of the shapes.
  • the gate structure further includes a first gate dielectric layer and a second gate dielectric layer.
  • the method for forming the semiconductor structure further includes: sequentially forming the first gate electrode. a dielectric layer, and a second gate dielectric layer located between the gate conductive layer and the first gate dielectric layer.
  • FIGS. 6a to 6g are structural schematic diagrams of the formation process of the semiconductor structure provided by embodiments of the present disclosure. The following is combined with 6a to 6g illustrate in detail the formation process of the semiconductor structure provided by the embodiment of the present disclosure.
  • the substrate is doped to form a first doped region and a second doped region located on the surface of the first doped region; the doping concentration of the second doped region is greater than the doping concentration of the first doped region.
  • the first doped region and the second doped region together constitute the source and drain of the semiconductor structure.
  • the work function of the second gate dielectric layer is smaller than the work function of the second doped region. In this way, inter-band leakage that causes gate-induced drain leakage current can be reduced and the electrical performance of the semiconductor structure can be improved.
  • a first doped region and a second doped region with different concentrations are provided.
  • the first doped region is an N-type lightly doped region, which can effectively reduce the cost between the gate and the source or the gate and the drain.
  • the electric field between the electrodes improves GIDL and reduces the drain current.
  • arsenic ions or phosphorus ions are used to dope the substrate 10 with the first size d3 along the surface of the substrate 10 to form a first initial doping region 205a; secondly, as shown in Figure 6b, continue Using arsenic ions or phosphorus ions, the first initial doping region 205a with the second size d4 is doped for the second time along the surface of the first initial doping region 205a to form the second doping region 206, and the rest is not performed.
  • the first initial doping region 205a doped for the second time constitutes the first doping region 205; wherein the first dimension d3 is larger than the second dimension d4.
  • the gate structure includes a first gate conductive layer and a second gate conductive layer.
  • the gate structure can be formed by the following steps: sequentially etching the second doped region, the first doped region and the substrate to form a gate trench; sequentially forming a first gate dielectric layer and a third gate dielectric layer on the inner wall of the gate trench.
  • the second doped region 206, the first doped region 205 and the substrate 10 are sequentially etched using the surface of the second doped region 206 as the etching starting point to form the gate trench H;
  • a first dielectric material is deposited on the inner wall of the gate trench H to form the first gate dielectric layer 203.
  • a second dielectric material is deposited on the surface of the first gate dielectric layer 203, and arsenic ions or phosphorus ions are used to treat the first dielectric material.
  • Doping is performed to form a second initial gate dielectric layer 202a; a first gate conductive material is deposited in the gate trench having the first gate dielectric layer 203 and the second initial gate dielectric layer 202a to form the first layer Initial gate conductive layer 210; etching back the first layer of initial gate conductive layer 210 to expose part of the second initial gate dielectric layer 202a to form the first layer of gate conductive layer 201a; with the first layer of gate A second gate conductive material is deposited in the gate trench of the conductive layer 201a to form a second initial gate conductive layer 211; the second initial gate conductive layer 211 and the second initial gate dielectric layer 202a are etched back. , a portion of the first gate dielectric layer 203 is exposed, and a second gate conductive layer 201b and a second gate dielectric layer 202 are formed.
  • the first dielectric material may be silicon oxide or silicon oxynitride
  • the second dielectric material may be silicon carbide
  • the first gate conductive material and the second gate conductive material may be titanium nitride or titanium nitride. and titanium composite materials.
  • the work function of the second gate conductive layer 201b can be smaller than the work function of the first gate conductive layer 201a. In this way, the row hammer problem can not only be solved, but also the GIDL can be improved.
  • both the second gate dielectric layer and the first gate dielectric layer contain tetravalent silicon, the second gate dielectric layer and the first gate dielectric layer will be combined more closely, thereby making The defects between the second gate dielectric layer and the first gate dielectric layer are smaller, which further reduces the gate-induced drain leakage current of the gate structure and improves the electrical performance of the semiconductor structure.
  • the first gate dielectric layer, the second initial gate dielectric layer, the first initial gate conductive layer and the second initial gate conductive layer can be formed through any suitable deposition process.
  • any suitable deposition process for example, chemical Vapor Deposition process (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD) process, atomic layer deposition (Atomic Layer Deposition, ALD) process, spin coating process or coating process.
  • the surfaces of the first gate conductive layer 201a and the second gate conductive layer 201b formed in the embodiment of the present disclosure are both arc-shaped.
  • the gate conductive layer with arc-shaped surfaces can have more gate dielectrics on both sides. layer material, thereby increasing the distance between the gate conductive layer and the source and drain electrodes, and improving leakage current problems such as GIDL.
  • the formed first gate conductive layer 201a and the second gate conductive layer 201b may also have a planar shape.
  • the method of forming the semiconductor structure further includes: An insulating material is deposited on the surface to form a gate insulating layer 204; the top surface of the gate insulating layer 204 is flush with the top surface of the second doped region 206.
  • the first gate dielectric layer 203, the second gate dielectric layer 202, the first gate conductive layer 201a, the second gate conductive layer 201b and the gate insulating layer 204 together form the gate structure 20.
  • the insulating material may be silicon oxide, silicon nitride, or silicon oxynitride.
  • the insulating material may be deposited through any suitable deposition process to form the gate insulating layer.
  • the gate structure may also be a planar gate structure.
  • the substrate includes a plurality of well regions; two adjacent well regions respectively constitute the source and drain of the semiconductor structure.
  • the gate structure may be formed on the substrate surface between two adjacent well regions.
  • the gate structure may include a first gate conductive layer and a second gate conductive layer, and the gate structure may be formed by the following steps:
  • Step 1 Form a first initial gate dielectric layer, a second initial gate dielectric layer, a first initial gate conductive layer and a second initial gate conductive layer on the substrate surface in order from bottom to top.
  • Step 2 Etch the second initial gate conductive layer, the first initial gate conductive layer, the second initial gate dielectric layer and the first initial gate dielectric layer sequentially through the mask layer with the preset window. The well region is exposed, and a second gate conductive layer, a first gate conductive layer, a second gate dielectric layer and a first gate dielectric layer are formed.
  • the gate structure may also be a full-all-around gate.
  • the substrate includes a plurality of active pillars, and the gate structure can be formed around each active pillar; the gate structure can include a first gate conductive layer and a second gate conductive layer; the gate structure can also be formed by The following steps form:
  • Step 1 Form a first initial gate dielectric layer, a second initial gate dielectric layer, a first initial gate conductive layer and a second initial gate conductive layer on the sidewall of the active pillar in order from the inside to the outside.
  • Step 2 Carry back the first initial gate dielectric layer, the second initial gate dielectric layer, the first initial gate conductive layer and the second initial gate conductive layer to expose part of the active pillars to form a third A gate dielectric layer, a second gate dielectric layer, a first gate conductive layer and a second gate conductive layer.
  • the method for forming a semiconductor structure provided by the embodiments of the present disclosure can produce a gate structure with an adjustable threshold voltage composed of a plurality of gate conductive layers with adjustable work functions through a simple process flow, which can effectively reduce the The gate of the prepared semiconductor structure induces drain leakage current, thereby improving the retention performance of the semiconductor structure.
  • Embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, wherein the semiconductor structure includes a gate structure located on a substrate, because the gate structure includes at least two gate conductive layers, and the at least two gate conductive layers have The same components and different characteristic parameters.
  • the characteristic parameters include thickness, component content or shape. In this way, different thicknesses, different component contents or different shapes make the work function and threshold voltage of each gate conductive layer in the gate structure All become adjustable, thereby effectively reducing the gate-induced drain leakage current of the semiconductor structure and improving the performance of the semiconductor structure.

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Abstract

本公开实施例涉及半导体技术领域，目前由于存储单元尺寸的不断缩小，栅极沟道的长度也随之缩减，导致栅极的控制能力越来越弱，因此，本公开实施例提供一种半导体结构及其形成方法，其中，半导体结构包括：位于衬底上的栅极结构；栅极结构包括至少两层栅极导电层；至少两层栅极导电层具有相同的组分和不同的特征参数；特征参数包括厚度、组分含量或形状中的至少一种。

Description

半导体结构及其形成方法
相关申请的交叉引用
本公开基于申请号为202211045210.3、申请日为2022年08月30日、发明名称为“半导体结构及其形成方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，涉及但不限于一种半导体结构及其形成方法。
背景技术
随着动态随机存取存储器(Dynamic Random Access Memory，DRAM)存储单元尺寸的不断缩小，栅极沟道的长度也随之缩减，如此，使得栅极感应漏极漏电流(Gate Induced Drain Leakage，GIDL)越来越大，栅极控制能力也逐渐减弱。
发明内容
有鉴于此，本公开实施例提供一种半导体结构及其形成方法。
第一方面，本公开实施例提供一种半导体结构，包括：位于衬底上的栅极结构；
所述栅极结构包括至少两层栅极导电层；
其中，所述至少两层栅极导电层具有相同的组分和不同的特征参数；所述特征参数包括厚度、组分含量或形状中的至少一种。
在一些实施例中，所述栅极结构还包括：位于所述至少两层栅极导电层表面的第一半导体层和第一导体层。
在一些实施例中，每一层所述栅极导电层在沿所述衬底厚度方向上的第一表面和第二表面具有预设形状；所述预设形状包括平面形和弧形。
在一些实施例中，每一层所述栅极导电层中的组分包括氮组分和金属组分；其中，每一层所述栅极导电层中的所述氮组分浓度不同。
在一些实施例中，所述栅极结构还包括：第一栅极介质层和第二栅极介质层；
所述第二栅极介质层位于所述栅极导电层与所述第一栅极介质层之间，且所述第二栅极介质层包括N型掺杂的碳化硅。
在一些实施例中，所述衬底内包括多个栅极沟槽；
所述第一栅极介质层位于所述栅极沟槽的内壁，且所述至少两层栅极导电层位于具有所述第二栅极介质层的栅极沟槽的底部；
其中，在垂直于所述衬底表面的方向上，所述至少两层栅极导电层的尺寸小于所述栅极沟槽的尺寸。
在一些实施例中，沿所述栅极沟槽的底部至所述栅极沟槽的顶部，所述至少两层栅极导电层的功函数逐渐减小。
在一些实施例中，位于所述栅极沟槽底部的所述第一栅极介质层具有第一厚度，位于所述栅极沟槽侧壁的所述第一栅极介质层具有第二厚度，所述第二厚度大于所述第一厚度。
在一些实施例中，位于所述栅极沟槽底部的所述第二栅极介质层具有第三厚度，位于所述栅极沟槽侧壁的所述第二栅极介质层具有第四厚度，所述第四厚度大于所述第三厚度。
在一些实施例中，所述半导体结构还包括栅极绝缘层；
所述栅极绝缘层位于所述第一栅极介质层和所述栅极导电层的表面，且所述栅极绝缘层的顶表面与所述衬底的顶表面平齐。
在一些实施例中，所述衬底还包括源极和漏极，其中，所述源极，和/或，所述漏极包括：第一掺杂区和位于所述第一掺杂区表面的第二掺杂区；
所述第二掺杂区的掺杂浓度大于所述第一掺杂区的掺杂浓度，所述第二栅极介质层的功函数小于所述第二掺杂区的功函数。
在一些实施例中，所述衬底内包括多个阱区，所述阱区作为晶体管的源极或漏极；
其中，所述第二栅极介质层位于所述衬底的上表面，且位于所述源极和所述漏极之间；
所述第一栅极介质层位于所述第二栅极介质层与所述衬底之间。
在一些实施例中，所述衬底包括多个相互隔离的有源柱；
所述第一栅极介质层、所述第二栅极介质层和所述至少两层栅极导电层依次环形覆盖部分所述有源柱，剩余的所述有源柱作为晶体管的源极或漏极。
第二方面，本公开实施例提供一种半导体结构的形成方法，所述方法包括：
提供衬底；
在所述衬底上形成至少两层栅极导电层，以形成栅极结构；其中，所述至少两层栅极导电层具有相同的组分和不同的特征参数；所述特征参数包括厚度、组分含量或形状中的至少一种。
在一些实施例中，在形成所述至少两层栅极导电层之前，所述方法还包括：
依次形成第一栅极介质层、以及位于所述栅极导电层和所述第一栅极 介质层之间的第二栅极介质层。
在一些实施例中，在形成所述栅极结构之前，所述方法还包括：
对所述衬底进行掺杂形成第一掺杂区和位于所述第一掺杂区表面的第二掺杂区，所述第二掺杂区的掺杂浓度大于所述第一掺杂区的掺杂浓度；
其中，所述第二栅极介质层的功函数小于所述第二掺杂区的功函数。
在一些实施例中，所述栅极结构形成于所述衬底的栅极沟槽中；所述栅极结构至少包括第一层栅极导电层和第二层栅极导电层，所述栅极结构通过以下步骤形成：
依次刻蚀所述第二掺杂区、所述第一掺杂区和所述衬底，形成所述栅极沟槽；
在所述栅极沟槽的内壁依次形成所述第一栅极介质层和第二初始栅极介质层；
在具有所述第一栅极介质层和所述第二初始栅极介质层的栅极沟槽中形成第一层初始栅极导电层；
对所述第一层初始栅极导电层进行回刻，暴露出部分第二初始栅极介质层，形成所述第一层栅极导电层；
在具有所述第一层栅极导电层的栅极沟槽中形成第二层初始栅极导电层；
对所述第二层初始栅极导电层和所述第二初始栅极介质层进行回刻，暴露出部分第一栅极介质层，形成所述第二层栅极导电层和第二栅极介质层。
在一些实施例中，所述方法还包括：
在所述第二栅极介质层和所述栅极导电层的表面形成栅极绝缘层；所述栅极绝缘层的顶表面与所述衬底的顶表面平齐。
在一些实施例中，所述衬底包括多个阱区；所述栅极结构形成于相邻两个所述阱区之间的衬底表面；所述栅极结构至少包括第一层栅极导电层和第二层栅极导电层，所述栅极结构通过以下步骤形成：
在所述衬底表面由下至上依次形成第一初始栅极介质层、第二初始栅极介质层、第一层初始栅极导电层和第二层初始栅极导电层；
通过具有预设窗口的掩膜版，依次刻蚀所述第二层初始栅极导电层、所述第一层初始栅极导电层、所述第二初始栅极介质层和所述第一初始栅极介质层，暴露出所述阱区，形成所述第二层栅极导电层、所述第一层栅极导电层、所述第二栅极介质层和所述第一栅极介质层。
在一些实施例中，所述栅极结构至少包括第一层栅极导电层和第二层栅极导电层，所述栅极结构形成于所述衬底中每一有源柱的周围；所述栅极结构通过以下步骤形成：
在所述有源柱的侧壁由内至外依次形成第一初始栅极介质层、第二初始栅极介质层、第一层初始栅极导电层和第二层初始栅极导电层；
对所述第一初始栅极介质层、所述第二初始栅极介质层、所述第一层初始栅极导电层和所述第二层初始栅极导电层进行回刻，暴露出部分有源柱，形成所述第一栅极介质层、所述第二栅极介质层、所述第一层栅极导电层和所述第二层栅极导电层。
本公开实施例提供一种半导体结构及其形成方法，其中，半导体结构包括位于衬底上的栅极结构，由于栅极结构包括至少两层栅极导电层，且至少两层栅极导电层具有相同的组分和不同的特征参数，特征参数包括厚度、组分含量或者形状，如此，不同厚度、不同组分含量或者不同形状使得栅极结构中的各个栅极导电层的功函数、阈值电压均变得可调，从而可以有效地减小半导体结构的栅极感应漏极漏电流，提高半导体结构的性能。
附图说明
在附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
图1为本公开实施例提供的半导体结构的结构示意图；
图2a为本公开实施例提供的具有埋入式栅极结构的半导体结构的结构示意图一；
图2b为本公开实施例提供的具有埋入式栅极结构的半导体结构的结构示意图二；
图3为本公开实施例提供的具有平面栅极结构的半导体结构的结构示意图；
图4a为本公开实施例提供的具有全环栅的半导体结构的结构示意图一；
图4b为本公开实施例提供的具有全环栅的半导体结构的结构示意图二；
图5为本公开实施例提供的半导体结构形成方法的流程示意图；
图6a为本公开实施例提供的半导体结构形成过程中的结构示意图一；
图6b为本公开实施例提供的半导体结构形成过程中的结构示意图二；
图6c为本公开实施例提供的半导体结构形成过程中的结构示意图三；
图6d为本公开实施例提供的半导体结构形成过程中的结构示意图四；
图6e为本公开实施例提供的半导体结构形成过程中的结构示意图五；
图6f为本公开实施例提供的半导体结构形成过程中的结构示意图六；
图6g为本公开实施例提供的半导体结构形成过程中的结构示意图七。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其它的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
本公开实施例提供一种半导体结构，图1为本公开实施例提供的半导体结构的结构示意图，如图1所示，半导体结构100包括：位于衬底10上的栅极结构20；栅极结构20包括至少两层栅极导电层；其中，至少两层栅极导电层具有相同的组分和不同的特征参数；特征参数包括厚度、组分含量或形状中的至少一种。
在一些实施例中，衬底可以是硅衬底，衬底也可以包括其它半导体元素，例如：锗(Ge)，或包括半导体化合物，例如：碳化硅(SiC)、砷化镓(GaAs)、磷化镓(GaP)、磷化铟(InP)、砷化铟(InAs)或锑化铟(InSb)，或包括其它半导体合金，例如：硅锗(SiGe)、磷化砷镓(GaAsP)、砷化铟铝(AlInAs)、砷化镓铝(AlGaAs)、砷化铟镓(GaInAs)、磷化铟镓(GaInP)、和/或磷砷化铟镓(GaInAsP)或其组合。在其它实施例中，衬底也可以是N型掺杂或者P型掺杂的衬底。
本公开实施例，栅极结构20包括至少两层栅极导电层，例如可以包括2层、3层、5层、6层或者更多的层，本公开实施例中通过多层栅极导电层的互相搭配，并调整栅极导电层之间的组分和浓度的变化，可以有效地调整衬底中不同位置处的栅极结构的阈值电压(Threshold Voltage，Vt)，以及栅极结构功函数，从而改善栅极感应漏极漏电(GIDL)，可以适应半导体存储器件尺寸越来越小的同时，具有更高效率和更高密度。进一步地，在具体的实施例中，栅极导电层例如由氮组分和金属组分组成，在栅极导电层中的金属组分，例如可以选择钨(W)、钴(Co)、钛(Ti)、钽(Ta)，每一栅极导电层中氮组分的含量或浓度不同，从而使得金属组分中的载流子浓度有所不同，如此，可以通过调整氮组分的浓度来改变阻值与功函数。
请继续参见图1，栅极结构20例如包括两层栅极导电层，分别为第一层栅极导电层201a和第二层栅极导电层201b。第一层栅极导电层201a和第二层栅极导电层201b的组分相同，例如，第一层栅极导电层201a和第二层栅极导电层201b可以均为氮化钛，第一层栅极导电层201a和第二层栅极导电层201b也可以均为含钛金属层，其中，含钛金属层可以是氮化钛层和金属钛层的复合层。
本公开实施例中，由于第一层栅极导电层201a和第二层栅极导电层201b的组分相同，但是第一层栅极导电层201a和第二层栅极导电层201b的厚度不同，或者，第一层栅极导电层201a和第二层栅极导电层201b的组分含量(例如Ti含量、N含量)不同，或者，第一层栅极导电层201a和第二层栅极导电层201b的形状不同(例如，第一层栅极导电层201a的表面为弧形，第二层栅极导电层201b的表面为平面形和弧形)，均会使得第一层栅极导电层201a和第二层栅极导电层201b的功函数可调，从而使得本公开实施例中的栅极结构的阈值电压可调，如此，可以有效地减小半导体结构的栅极感应漏极漏电流，提高半导体结构的保持性能。
在一些实施例中，请继续参见图1，栅极结构20还包括第一栅极介质层203和第二栅极介质层202；第二栅极介质层202位于栅极导电层(即第一层栅极导电层201a和第二层栅极导电层201b)与第一栅极介质层203之间。
本公开实施例中，第二栅极介质层202包括N型掺杂的碳化硅。
本公开实施例中，第一栅极介质层203可以是氧化硅层。由于第二栅 极介质层202和第一栅极介质层203均包含4价的硅，因此，第二栅极介质层202与第一栅极介质层203会结合的更加紧密，进而使得第二栅极介质层和第一栅极介质层之间的缺陷更小，进一步降低了栅极结构的栅极感应漏极漏电流，提高半导体结构的电性能。
在一些实施例中，请继续参见图1，半导体结构100还包括位于第二栅极介质层202和第一栅极介质层203表面的栅极绝缘层204，其中，栅极绝缘层204的顶表面与衬底10的顶表面平齐。
本公开实施例中，栅极绝缘层204可以是氮化硅或者氧化硅。
在其它实施例中，半导体结构100还可以包括位线结构、电容结构或者其它功能结构。
在一些实施例中，半导体结构中的栅极结构可以是埋入式栅极结构，在其它实施例中，半导体结构中的栅极结构还可以是平面栅极(Flat Gate)结构、Ω栅极(Omega Gate)结构、全环栅(Gate All Around，GAA)结构或者双栅(Double Gate)结构。
图2a和图2b为本公开实施例提供的具有埋入式栅极结构的半导体结构的结构示意图，如图2a和图2b所示，半导体结构100包括：位于衬底10上的栅极结构20；栅极结构20例如包括三层栅极导电层，分别为第一层栅极导电层201a、第二层栅极导电层201b和第三层栅极导电层201c；其中，第一层栅极导电层201a、第二层栅极导电层201b和第三层栅极导电层201c具有相同的组分，且第一层栅极导电层201a、第二层栅极导电层201b和第三层栅极导电层201c具有不同的特征参数；例如，第一层栅极导电层201a、第二层栅极导电层201b和第三层栅极导电层201c具有不同的厚度，或者，第一层栅极导电层201a、第二层栅极导电层201b和第三层栅极导电层201c具有不同的组分含量，或者，第一层栅极导电层201a、第二层栅极导电层201b和第三层栅极导电层201c具有不同的形状。
本公开实施例中，第一层栅极导电层201a、第二层栅极导电层201b和第三层栅极导电层201c的组分相同，例如，第一层栅极导电层201a、第二层栅极导电层201b和第三层栅极导电层201c可以均为氮化钛，第一层栅极导电层201a、第二层栅极导电层201b和第三层栅极导电层201c中的组分均包括氮组分和金属钛组分，且第一层栅极导电层201a、第二层栅极导电层201b和第三层栅极导电层201c中的氮组分不同。具有合适字元线阻值的三层氮化钛作为栅极导电层，不会引起电容电阻延迟现象。
在一些实施例中，请继续参见图2a和图2b，栅极结构20还可以包括第二栅极介质层202和第一栅极介质层203；第一层栅极导电层201a、第二层栅极导电层201b和第三层栅极导电层201c位于第二栅极介质层202的表面，且第二栅极介质层202位于第一栅极介质层203的表面。
在一些实施例中，请继续参见图2a和图2b，衬底10内包括多个栅极沟槽(图2a和图2b中仅示出一个栅极沟槽)；第一栅极介质层203位于栅 极沟槽的内壁，且第一层栅极导电层201a、第二层栅极导电层201b和第三层栅极导电层201c位于具有第一栅极介质层203的栅极沟槽的底部。其中，在垂直于衬底表面的方向上，第一层栅极导电层201a、第二层栅极导电层201b和第三层栅极导电层201c的总尺寸D1小于栅极沟槽的尺寸D2。
在一些实施例中，在沿栅极沟槽的底部至栅极沟槽的顶部的方向上，栅极导电层的功函数逐渐减少，例如，栅极结构包括两层栅极导电层时，位于底层的第一层栅极导电层的功函数最大，位于顶层的第二层栅极导电层最小，又例如，在其他的实施例中，栅极结构包括三层栅极导电层时，位于底层的第一层栅极导电层201a、中间层的第二层栅极导电层201b、顶层的第三层栅极导电层201c的功函数逐渐减小。本公开实施例中，可以通过调节每一层中栅极导电层的氮组分浓度，来相应地调节每一层栅极导电层功函数，使得在栅极结构中，沿栅极沟槽的底部至栅极沟槽的顶部的方向上，栅极导电层的功函数逐渐减少，这样最底层的栅极导电层(例如TiN栅电极)的功函数最高，而最上层的栅极导电层(例如TiN栅电极)的功函数最低，这样的组合不仅可以解决行锤击(Row hammer)，还可以改善栅极感应漏极漏电流(GIDL)问题，同时这样的组合使得栅极结构的阻值更低。
当本公开实施例中的半导体结构为动态随机存取存储器时，由于DRAM编程和擦除过程都需要通过字线(即栅极结构)进行操作，当一个DRAM存储单元的字线在一直重复操作时，可能会导致隔壁存储单元内的电荷被吸引，数据遗失，如此，将会导致严重的行锤击问题。本公开实施例中，通过设置具有不同厚度、不同组分含量或者不同形状的多层栅极导电层，来调节栅极导电层的功函数和栅极结构的阈值电压，使得沿栅极沟槽的底部至栅极沟槽的顶部，至少两层栅极导电层的功函数依次减小(即阈值电压依次减小)，如此，可以有效地抑制DRAM中的Row hammer现象；另外，还可以改善GIDL，相较于相关技术中的混合埋入式字线(Hybrid Burried Word-Line，HBW)，调制金属栅极字线的阻值更低，电阻电容延迟现象更好。
在一些实施例中，位于栅极沟槽底部的第一栅极介质层具有第一厚度，位于栅极沟槽侧壁的第一栅极介质层具有第二厚度，第二厚度大于第一厚度。
本公开实施例中，在栅极沟槽中形成具有低台阶覆盖率的第一栅极介质层，即使得栅极沟槽底部的第一栅极介质层的厚度小于栅极沟槽侧壁的第一栅极介质层的厚度，一方面，可以降低栅极感应漏极漏电流，提高栅极的控制能力，另一方面，沟槽底部的第一栅极介质层做的比较薄，可以为栅极导电层留出足够大的空间，提高栅极沟道的导通能力。
需要说明的是，在其它实施例中，还可以在栅极沟槽中形成比较均匀的第一栅极介质层，即位于栅极沟槽底部的第一栅极介质层与位于栅极沟 槽侧壁的第一栅极介质层具有同样的厚度。
在一些实施例中，请继续参见图2a和图2b，第二栅极介质层202位于栅极沟槽中，且第二栅极介质层202位于第一层栅极导电层201a与第一栅极介质层203、第二层栅极导电层201b与第一栅极介质层203、以及第三层栅极导电层201c与第一栅极介质层203之间。
在一些实施例中，位于栅极沟槽底部的第二栅极介质层具有第三厚度，位于栅极沟槽侧壁的第二栅极介质层具有第四厚度，第四厚度大于第三厚度。
本公开实施例中，在栅极沟槽中形成具有低台阶覆盖率的第二栅极介质层，即使得栅极沟槽底部的第二栅极介质层的厚度小于栅极沟槽侧壁的第二栅极介质层的厚度，一方面，可以降低栅极感应漏极漏电流，提高栅极的控制能力，另一方面，沟槽底部的第二栅极介质层做的比较薄，可以为栅极导电层留出足够大的空间，提高栅极沟道的导通能力。
需要说明的是，在其它实施例中，还可以在栅极沟槽中形成比较均匀的第二栅极介质层，即位于栅极沟槽底部的第二栅极介质层与位于栅极沟槽侧壁的第二栅极介质层具有同样的厚度。
在一些实施例中，请继续参见图2a和图2b，半导体结构100还包括栅极绝缘层204；栅极绝缘层204位于第一栅极介质层203和栅极导电层(即第三层栅极导电层201c)的表面，且栅极绝缘层204的顶表面与衬底10的顶表面平齐。
在一些实施例中，请继续参见图2a和图2b，衬底10还包括第一掺杂区205和位于第一掺杂区205表面的第二掺杂区206；第二掺杂区206的掺杂浓度大于第一掺杂区205的掺杂浓度，且栅极沟槽贯穿第二掺杂区206和第一掺杂区205，栅极沟槽的底部位于衬底10中。
本公开实施例中，第一掺杂区205和第二掺杂区206共同构成半导体结构的源极和漏极。
本公开实施例中，第二栅极介质层202的功函数小于第二掺杂区206的功函数，第二栅极介质层202例如可以为N型掺杂的碳化硅，N型掺杂的碳化硅(N+SiC)的功函数(Φ)为3.1电子伏(eV)；第二掺杂区206可以是N型掺杂的硅衬底，N型掺杂的硅衬底(N+Si)的功函数(Φ)为4.17eV，第二栅极介质层的功函数小于第二掺杂区的功函数可以减少导致栅极感应漏极漏电流的带间泄露，提高半导体结构的电性能。
本公开实施例中，设置具有不同浓度的第一掺杂区和第二掺杂区，第一掺杂区为N型的轻掺杂区，可以有效降低栅极与源极或者栅极与漏极之间的电场，改善GIDL，并且减小漏极电流。
在一些实施例中，衬底10还可以只包括第二掺杂区206，第二掺杂区206构成半导体结构的源极和漏极。
在一些实施例中，请继续参见图2b，栅极结构20还包括：第一半导体 层301和第一导体层302。
第一半导体层301位于最外层的栅极导电层上，例如位于第三层栅极导电层201c上，第一半导体层301用于连接第三层栅极导电层201c和第一导体层302，第一半导体层301可以是金属硅化物层，由于金属硅化物具有较低的阻值，因此可以降低第三层栅极导电层201c与第一导体层302之间的接触电阻，从而可以进一步降低半导体结构的功耗。这里，第一导体层302可以是多晶硅层或者任意一种金属层，例如，钴、钛、钽、镍(Ni)、钨、铂(Pt)以及钯(Pd)中的任意一种或任意组合。
在一些实施例中，请继续参见图2b，栅极绝缘层204还位于第一栅极介质层203和第一导体层302的表面，且栅极绝缘层204的顶表面与衬底10的顶表面平齐。
在一些实施例中，每一层栅极导电层在沿衬底厚度方向上的第一表面和第二表面具有预设形状；预设形状包括平面形，和/或，弧形，弧形例如为Ω形状、凹陷形状。
如图2a所示，第一层栅极导电层201a、第二层栅极导电层201b和第三层栅极导电层201c在沿衬底10厚度方向(X轴方向)的两个表面均为弧形。如图2b所示，第一层栅极导电层201a在沿X轴方向的第一表面和第二表面分别为弧形和平面形，第二层栅极导电层201b、第三层栅极导电层201c在沿X轴方向的两个表面均为平面形。
本公开实施例中，每一层栅极导电层具有弧形或者平面形形状，当栅极导电层具有弧形表面时，栅极导电层两侧可以具有更多的栅极介质层材料，从而增加栅极导电层与源极、漏极之间的距离，改善GIDL等漏电流的问题。
在一些实施例中，请继续参见图2a和图2b，栅极绝缘层204在沿衬底厚度方向上的两个表面可以分别为弧形和平面形(如图2a所示)或者均为平面形(如图2b所示)。
本公开实施例中，由于第一层栅极导电层201a、第二层栅极导电层201b和第三层栅极导电层201c的组分相同，但是第一层栅极导电层201a、第二层栅极导电层201b和第三层栅极导电层201c的特征参数(例如厚度、组分含量、形状中的至少一种)不同，使得第一层栅极导电层201a、第二层栅极导电层201b和第三层栅极导电层201c的功函数可调，进而使得本公开实施例中的栅极结构的阈值电压可调，如此，可以有效地减小半导体结构的栅极感应漏极漏电流，提高半导体结构的保持性能。
图3为本公开实施例提供的具有平面栅极结构的半导体结构的结构示意图，如图3所示，半导体结构100包括：位于衬底10上的栅极结构20；栅极结构20包括三层栅极导电层，分别为第一层栅极导电层201a、第二层栅极导电层201b和第三层栅极导电层201c；其中，第一层栅极导电层201a、第二层栅极导电层201b和第三层栅极导电层201c具有相同的组分，且第 一层栅极导电层201a、第二层栅极导电层201b和第三层栅极导电层201c具有不同的特征参数；例如，第一层栅极导电层201a、第二层栅极导电层201b和第三层栅极导电层201c具有不同的厚度，或者，第一层栅极导电层201a、第二层栅极导电层201b和第三层栅极导电层201c具有不同的组分含量，或者，第一层栅极导电层201a、第二层栅极导电层201b和第三层栅极导电层201c具有不同的形状。
在一些实施例中，请继续参见图3，栅极结构20还可以包括第二栅极介质层202和第一栅极介质层203；第一层栅极导电层201a、第二层栅极导电层201b和第三层栅极导电层201c均位于第二栅极介质层202的表面，且第二栅极介质层202位于第一栅极介质层203的表面。
本公开实施例中，第二栅极介质层202的功函数小于衬底10的功函数，如此，可以进一步降低栅极结构的栅极感应漏极漏电流，提高半导体结构的电性能。
在一些实施例中，请继续参见图3，衬底10内包括多个阱区(图3中仅示出两个阱区)，相邻的两个阱区可以作为晶体管的源极207或漏极208。
在一些实施例中，请继续参见图3，第二栅极介质层202位于衬底10的上表面，且位于源极207和漏极208之间；第一栅极介质层203位于第二栅极介质层202与衬底10之间。
图4a和图4b为本公开实施例提供的具有全环栅的半导体结构的结构示意图，其中，图4a为剖视图，图4b为全环栅结构的俯视图，如图4a和图4b所示，半导体结构100包括：位于衬底10上的栅极结构20；栅极结构20包括两层栅极导电层，分别为第一层栅极导电层201a和第二层栅极导电层201b；其中，第一层栅极导电层201a和第二层栅极导电层201b具有相同的组分，且第一层栅极导电层201a和第二层栅极导电层201b具有不同的特征参数；特征参数包括厚度、组分含量或者形状。
在一些实施例中，请继续参见图4a和图4b，栅极结构20还可以包括第二栅极介质层202和第一栅极介质层203；第一层栅极导电层201a和第二层栅极导电层201b位于第二栅极介质层202的表面，且第二栅极介质层202位于第一栅极介质层203的表面。
本公开实施例中，第二栅极介质层202的功函数小于衬底10的功函数，如此，可以进一步降低栅极结构的栅极感应漏极漏电流，提高半导体结构的电性能。
在一些实施例中，请继续参见图4a和图4b，衬底10包括多个相互隔离的有源柱101(图4a和图4b中仅示出一个有源柱)；第一栅极介质层203、第二栅极介质层202、第一层栅极导电层201a和第二层栅极导电层201b依次环形覆盖部分有源柱101，剩余的有源柱101作为晶体管的源极或漏极。
本公开实施例中，由于第一层栅极导电层201a和第二层栅极导电层201b的组分相同，但是第一层栅极导电层201a和第二层栅极导电层201b 的特征参数(例如厚度、组分含量、表面形状中的至少一种)不同，使得第一层栅极导电层201a和第二层栅极导电层201b的功函数可调，以及使得本公开实施例中的栅极结构的阈值电压可调，如此，可以有效地减小半导体结构的改善GIDL等漏电流的问题，提高半导体结构的保持性能。
除此之外，本公开实施例还提供一种半导体结构的形成方法，图5为本公开实施例提供的半导体结构形成方法的流程示意图，如图5所示，半导体结构的形成方法包括以下步骤：
步骤S501、提供衬底。
在一些实施例中，衬底可以是N型掺杂的硅衬底或者是P型掺杂的硅衬底。
步骤S502、在衬底上形成至少两层栅极导电层，以形成栅极结构；其中，至少两层栅极导电层具有相同的组分和不同的特征参数；特征参数包括厚度、组分含量或形状中的至少一种。
在一些实施例中，栅极结构还包括第一栅极介质层和第二栅极介质层，在形成至少两层栅极导电层之前，半导体结构的形成方法还包括：依次形成第一栅极介质层、以及位于栅极导电层和第一栅极介质层之间的第二栅极介质层。
下面以半导体结构的栅极结构为埋入式栅极结构为例，说明栅极结构的详细形成过程，图6a～图6g为本公开实施例提供的半导体结构形成过程中的结构示意图，下面结合图6a～图6g对本公开实施例提供的半导体结构的形成过程进行详细的说明。
首先，对衬底进行掺杂形成第一掺杂区和位于第一掺杂区表面的第二掺杂区；第二掺杂区的掺杂浓度大于第一掺杂区的掺杂浓度。
本公开实施例中，第一掺杂区和第二掺杂区共同构成半导体结构的源极和漏极。
本公开实施例中，第二栅极介质层的功函数小于第二掺杂区的功函数，如此，可以减少导致栅极感应漏极漏电流的带间泄露，提高半导体结构的电性能。
本公开实施例中，设置具有不同浓度的第一掺杂区和第二掺杂区，第一掺杂区为N型的轻掺杂区，可以有效降低栅极与源极或者栅极与漏极之间的电场，改善GIDL，并且减小漏极电流。
如图6a所示，采用砷离子或者磷离子，沿衬底10表面对具有第一尺寸d3的衬底10进行掺杂，形成第一初始掺杂区205a；其次，如图6b所示，继续采用砷离子或者磷离子，沿第一初始掺杂区205a的表面对具有第二尺寸d4的第一初始掺杂区205a进行第二次掺杂，形成第二掺杂区206，剩余的未进行第二次掺杂的第一初始掺杂区205a构成第一掺杂区205；其中，第一尺寸d3大于第二尺寸d4。
接下来，参考图6c～图6g，说明栅极结构的形成过程。
本公开实施例中，栅极结构包括第一层栅极导电层和第二层栅极导电层。栅极结构可以通过以下步骤形成：依次刻蚀第二掺杂区、第一掺杂区和衬底，形成栅极沟槽；在栅极沟槽的内壁依次形成第一栅极介质层和第二初始栅极介质层；在具有第一栅极介质层和第二初始栅极介质层的栅极沟槽中形成第一层初始栅极导电层；对第一层初始栅极导电层进行回刻，暴露出部分第二初始栅极介质层，形成第一层栅极导电层；在具有第一层栅极导电层的栅极沟槽中形成第二层初始栅极导电层；对第二层初始栅极导电层和第二初始栅极介质层进行回刻，暴露出部分第一栅极介质层，形成第二层栅极导电层和第二栅极介质层。
如图6c～图6g所示，以第二掺杂区206的表面为刻蚀起点依次刻蚀第二掺杂区206、第一掺杂区205和衬底10，形成栅极沟槽H；在栅极沟槽H的内壁沉积第一介质材料形成第一栅极介质层203，在第一栅极介质层203的表面沉积第二介质材料，并采用砷离子或者磷离子对第一介质材料进行掺杂，形成第二初始栅极介质层202a；在具有第一栅极介质层203和第二初始栅极介质层202a的栅极沟槽中沉积第一栅极导电材料，形成第一层初始栅极导电层210；对第一层初始栅极导电层210进行回刻，暴露出部分第二初始栅极介质层202a，形成第一层栅极导电层201a；在具有第一层栅极导电层201a的栅极沟槽中沉积第二栅极导电材料，形成第二层初始栅极导电层211；对第二层初始栅极导电层211和第二初始栅极介质层202a进行回刻，暴露出部分第一栅极介质层203，形成第二层栅极导电层201b和第二栅极介质层202。
本公开实施例中，第一介质材料可以是氧化硅或者氮氧化硅；第二介质材料可以是碳化硅；第一栅极导电材料和第二栅极导电材料可以为氮化钛、氮化钛和金属钛的复合材料。
在一些实施例中，第二层栅极导电层201b的功函数可以小于第一层栅极导电层201a的功函数，如此，不仅可以解决Row hammer的问题，还可以改善GIDL。
本公开实施例中，由于第二栅极介质层和第一栅极介质层均包含4价的硅，因此，第二栅极介质层与第一栅极介质层会结合的更加紧密，进而使得第二栅极介质层和第一栅极介质层之间的缺陷更小，进一步降低了栅极结构的栅极感应漏极漏电流，提高半导体结构的电性能。
本公开实施例中，可以通过任意一种合适的沉积工艺形成第一栅极介质层、第二初始栅极介质层、第一层初始栅极导电层和第二层初始栅极导电层。例如，化学气相沉积工艺(Chemical Vapor Deposition，CVD)、物理气相沉积(Physical Vapor Deposition，PVD)工艺、原子层沉积(Atomic Layer Deposition，ALD)工艺、旋涂工艺或者涂敷工艺。
本公开实施例中形成的第一层栅极导电层201a和第二层栅极导电层201b的表面均为弧形，具有弧形表面的栅极导电层两侧可以具有更多的栅 极介质层材料，从而增加栅极导电层与源极、漏极之间的距离，改善GIDL等漏电流的问题。
在其它实施例中，形成的第一层栅极导电层201a和第二层栅极导电层201b也可以具有平面形形状。
在一些实施例中，请继续参见图6g，在形成第二层栅极导电层201b之后，半导体结构的形成方法还包括：在第二栅极介质层202和第二层栅极导电层201b的表面沉积绝缘材料，形成栅极绝缘层204；栅极绝缘层204的顶表面与第二掺杂区206的顶表面平齐。第一栅极介质层203、第二栅极介质层202、第一层栅极导电层201a、第二层栅极导电层201b和栅极绝缘层204共同构成栅极结构20。
本公开实施例中，绝缘材料可以是氧化硅、氮化硅或者氮氧化硅，可以通过任意一种合适的沉积工艺沉积绝缘材料，形成栅极绝缘层。
在其它实施例中，栅极结构还可以是平面栅极结构。衬底包括多个阱区；相邻的两个阱区分别构成了半导体结构的源极和漏极。栅极结构可以形成于相邻两个阱区之间的衬底表面。
在一些实施例中，栅极结构可以包括第一层栅极导电层和第二层栅极导电层，栅极结构可以通过以下步骤形成：
步骤一：在衬底表面由下至上依次形成第一初始栅极介质层、第二初始栅极介质层、第一层初始栅极导电层和第二层初始栅极导电层。
步骤二：通过具有预设窗口的掩膜层，依次刻蚀第二层初始栅极导电层、第一层初始栅极导电层、第二初始栅极介质层和第一初始栅极介质层，暴露出阱区，形成第二层栅极导电层、第一层栅极导电层、第二栅极介质层和第一栅极介质层。
在其它实施例中，栅极结构还可以是全环栅。衬底包括多个有源柱，栅极结构可以形成于每一有源柱的周围；栅极结构可以包括第一层栅极导电层和第二层栅极导电层；栅极结构还可以通过以下步骤形成：
步骤一：在有源柱的侧壁由内至外依次形成第一初始栅极介质层、第二初始栅极介质层、第一层初始栅极导电层和第二层初始栅极导电层。
步骤二：对第一初始栅极介质层、第二初始栅极介质层、第一层初始栅极导电层和第二层初始栅极导电层进行回刻，暴露出部分有源柱，形成第一栅极介质层、第二栅极介质层、第一层栅极导电层和第二层栅极导电层。
本公开实施例提供的半导体结构的形成过程与上述实施例中的半导体结构类似，对于本公开实施例未详尽披露的技术特征，请参考上述实施例进行理解，这里不再赘述。
本公开实施例提供的半导体结构的形成方法，通过简便的工艺流程即可制备出由多个功函数可调的栅极导电层构成的阈值电压可调的栅极结构，可以有效地减小所制备的半导体结构的栅极感应漏极漏电流，提高半 导体结构的保持性能。
在本公开所提供的几个实施例中，应该理解到，所揭露的结构和方法，可以通过非目标的方式实现。以上所描述的结构实施例仅仅是示意性的，例如，单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。
本公开所提供的几个方法或结构实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或结构实施例。
以上，仅为本公开的一些实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例提供一种半导体结构及其形成方法，其中，半导体结构包括位于衬底上的栅极结构，由于栅极结构包括至少两层栅极导电层，且至少两层栅极导电层具有相同的组分和不同的特征参数，特征参数包括厚度、组分含量或者形状，如此，不同厚度、不同组分含量或者不同形状使得栅极结构中的各个栅极导电层的功函数、阈值电压均变得可调，从而可以有效地减小半导体结构的栅极感应漏极漏电流，提高半导体结构的性能。

Claims (20)

  1. 一种半导体结构，包括：位于衬底上的栅极结构；
    所述栅极结构包括至少两层栅极导电层；
    其中，所述至少两层栅极导电层具有相同的组分和不同的特征参数；所述特征参数包括厚度、组分含量或形状中的至少一种。
  2. 根据权利要求1所述的半导体结构，其中，所述栅极结构还包括：位于所述至少两层栅极导电层表面的第一半导体层和第一导体层。
  3. 根据权利要求1所述的半导体结构，其中，每一层所述栅极导电层在沿所述衬底厚度方向上的第一表面和第二表面具有预设形状；所述预设形状包括平面形和弧形。
  4. 根据权利要求1所述的半导体结构，其中，每一层所述栅极导电层中的组分包括氮组分和金属组分；其中，每一层所述栅极导电层中的所述氮组分浓度不同。
  5. 根据权利要求1至4任一项所述的半导体结构，其中，所述栅极结构还包括：第一栅极介质层和第二栅极介质层；
    所述第二栅极介质层位于所述栅极导电层与所述第一栅极介质层之间，且所述第二栅极介质层包括N型掺杂的碳化硅。
  6. 根据权利要求5所述的半导体结构，其中，所述衬底内包括多个栅极沟槽；
    所述第一栅极介质层位于所述栅极沟槽的内壁，且所述至少两层栅极导电层位于具有所述第二栅极介质层的栅极沟槽的底部；
    其中，在垂直于所述衬底表面的方向上，所述至少两层栅极导电层的尺寸小于所述栅极沟槽的尺寸。
  7. 根据权利要求6所述的半导体结构，其中，沿所述栅极沟槽的底部至所述栅极沟槽的顶部，所述至少两层栅极导电层的功函数逐渐减小。
  8. 根据权利要求7所述的半导体结构，其中，位于所述栅极沟槽底部的所述第一栅极介质层具有第一厚度，位于所述栅极沟槽侧壁的所述第一栅极介质层具有第二厚度，所述第二厚度大于所述第一厚度。
  9. 根据权利要求8所述的半导体结构，其中，位于所述栅极沟槽底部的所述第二栅极介质层具有第三厚度，位于所述栅极沟槽侧壁的所述第二栅极介质层具有第四厚度，所述第四厚度大于所述第三厚度。
  10. 根据权利要求9所述的半导体结构，其中，所述半导体结构还包括栅极绝缘层；
    所述栅极绝缘层位于所述第一栅极介质层和所述栅极导电层的表面，且所述栅极绝缘层的顶表面与所述衬底的顶表面平齐。
  11. 根据权利要求10所述的半导体结构，其中，所述衬底还包括源极 和漏极，其中，所述源极，和/或，所述漏极包括：
    第一掺杂区和位于所述第一掺杂区表面的第二掺杂区；
    所述第二掺杂区的掺杂浓度大于所述第一掺杂区的掺杂浓度，所述第二栅极介质层的功函数小于所述第二掺杂区的功函数。
  12. 根据权利要求5所述的半导体结构，其中，所述衬底内包括多个阱区，所述阱区作为晶体管的源极或漏极；
    其中，所述第二栅极介质层位于所述衬底的上表面，且位于所述源极和所述漏极之间；
    所述第一栅极介质层位于所述第二栅极介质层与所述衬底之间。
  13. 根据权利要求5所述的半导体结构，其中，所述衬底包括多个相互隔离的有源柱；
    所述第一栅极介质层、所述第二栅极介质层和所述至少两层栅极导电层依次环形覆盖部分所述有源柱，剩余的所述有源柱作为晶体管的源极或漏极。
  14. 一种半导体结构的形成方法，所述方法包括：
    提供衬底；
    在所述衬底上形成至少两层栅极导电层，以形成栅极结构；其中，所述至少两层栅极导电层具有相同的组分和不同的特征参数；所述特征参数包括厚度、组分含量或形状中的至少一种。
  15. 根据权利要求14所述的方法，其中，在形成所述至少两层栅极导电层之前，所述方法还包括：
    依次形成第一栅极介质层、以及位于所述栅极导电层和所述第一栅极介质层之间的第二栅极介质层。
  16. 根据权利要求15所述的方法，其中，在形成所述栅极结构之前，所述方法还包括：
    对所述衬底进行掺杂形成第一掺杂区和位于所述第一掺杂区表面的第二掺杂区，所述第二掺杂区的掺杂浓度大于所述第一掺杂区的掺杂浓度；
    其中，所述第二栅极介质层的功函数小于所述第二掺杂区的功函数。
  17. 根据权利要求16所述的方法，其中，所述栅极结构形成于所述衬底的栅极沟槽中；所述栅极结构至少包括第一层栅极导电层和第二层栅极导电层，所述栅极结构通过以下步骤形成：
    依次刻蚀所述第二掺杂区、所述第一掺杂区和所述衬底，形成所述栅极沟槽；
    在所述栅极沟槽的内壁依次形成所述第一栅极介质层和第二初始栅极介质层；
    在具有所述第一栅极介质层和所述第二初始栅极介质层的栅极沟槽中形成第一层初始栅极导电层；
    对所述第一层初始栅极导电层进行回刻，暴露出部分第二初始栅极介 质层，形成所述第一层栅极导电层；
    在具有所述第一层栅极导电层的栅极沟槽中形成第二层初始栅极导电层；
    对所述第二层初始栅极导电层和所述第二初始栅极介质层进行回刻，暴露出部分第一栅极介质层，形成所述第二层栅极导电层和第二栅极介质层。
  18. 根据权利要求17所述的方法，其中，所述方法还包括：
    在所述第二栅极介质层和所述栅极导电层的表面形成栅极绝缘层；所述栅极绝缘层的顶表面与所述衬底的顶表面平齐。
  19. 根据权利要求15所述的方法，其中，所述衬底包括多个阱区；所述栅极结构形成于相邻两个所述阱区之间的衬底表面；所述栅极结构至少包括第一层栅极导电层和第二层栅极导电层，所述栅极结构通过以下步骤形成：
    在所述衬底表面由下至上依次形成第一初始栅极介质层、第二初始栅极介质层、第一层初始栅极导电层和第二层初始栅极导电层；
    通过具有预设窗口的掩膜版，依次刻蚀所述第二层初始栅极导电层、所述第一层初始栅极导电层、所述第二初始栅极介质层和所述第一初始栅极介质层，暴露出所述阱区，形成所述第二层栅极导电层、所述第一层栅极导电层、所述第二栅极介质层和所述第一栅极介质层。
  20. 根据权利要求15所述的方法，其中，所述栅极结构至少包括第一层栅极导电层和第二层栅极导电层，所述栅极结构形成于所述衬底中每一有源柱的周围；所述栅极结构通过以下步骤形成：
    在所述有源柱的侧壁由内至外依次形成第一初始栅极介质层、第二初始栅极介质层、第一层初始栅极导电层和第二层初始栅极导电层；
    对所述第一初始栅极介质层、所述第二初始栅极介质层、所述第一层初始栅极导电层和所述第二层初始栅极导电层进行回刻，暴露出部分有源柱，形成所述第一栅极介质层、所述第二栅极介质层、所述第一层栅极导电层和所述第二层栅极导电层。
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