WO2023245755A1 - 半导体结构及其形成方法、版图结构 - Google Patents

半导体结构及其形成方法、版图结构 Download PDF

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WO2023245755A1
WO2023245755A1 PCT/CN2022/105094 CN2022105094W WO2023245755A1 WO 2023245755 A1 WO2023245755 A1 WO 2023245755A1 CN 2022105094 W CN2022105094 W CN 2022105094W WO 2023245755 A1 WO2023245755 A1 WO 2023245755A1
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layer
semiconductor
active
gate
gate structure
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PCT/CN2022/105094
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English (en)
French (fr)
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唐怡
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长鑫存储技术有限公司
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Priority to EP22924562.6A priority Critical patent/EP4329455A1/en
Priority to KR1020237026956A priority patent/KR20240001311A/ko
Priority to US17/954,480 priority patent/US20230018639A1/en
Publication of WO2023245755A1 publication Critical patent/WO2023245755A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a semiconductor structure, its formation method, and layout structure.
  • DRAM Dynamic Random Access Memory
  • the full gate or double gate process is used to produce 4F 2 DRAM.
  • the 4F 2 DRAM needs to form bit line steps or word line steps.
  • the bit line steps have a relatively large impact in the use of DRAM. Sensing Noise, word line coupling (Word Line Coupling) in word line steps, and the interconnection of word lines on the same plane in the process are difficult to achieve for multi-layer stacking.
  • embodiments of the present disclosure provide a semiconductor structure, a method of forming the same, and a layout structure.
  • an embodiment of the present disclosure provides a method for forming a semiconductor structure, the method including:
  • the substrate includes a first region and a second region arranged sequentially along a second direction; the first region includes active layers spaced apart along a third direction;
  • the first direction, the second direction and the third direction are each perpendicular to each other, and the first direction and the second direction are parallel to the substrate surface;
  • a bit line structure extending along the third direction and a capacitor structure extending along the second direction are formed in the second region, and both the bit line structure and the capacitor structure are connected to the first gate structure. .
  • embodiments of the present disclosure provide a semiconductor structure, including:
  • the semiconductor substrate including a first region and a second region sequentially arranged along a second direction;
  • An active structure located on the surface of the semiconductor substrate; the active structure is arranged in an array along the first direction and the third direction;
  • a comb gate structure located on the surface of the active structure in the first region, and the comb gate structure at least includes first gate structures spaced apart in the first direction;
  • bit line structure extending along the third direction
  • the bit line structure and the capacitor structure are both located on the second area, and both are connected to the first gate structure; the first direction, the second The first direction and the third direction are perpendicular to each other, and the first direction and the second direction are parallel to the surface of the semiconductor substrate.
  • embodiments of the present disclosure provide a layout structure, including: the above-mentioned semiconductor structures arranged at intervals along the second direction;
  • the semiconductor structure includes memory cells arranged in an array along a first direction and a third direction; the memory unit includes a first gate structure and a capacitor structure;
  • the two adjacent memory cells in the second direction are centrally symmetrical, and the projection areas of the capacitive structures of the two adjacent memory cells in the second direction in the first direction at least partially overlap.
  • the gate metal layer outside the comb-shaped gate structure can be used as a word line of the semiconductor structure, not only the multi-layer stacked structure can be realized through the comb-shaped gate structure
  • the interconnection of word lines on the same plane can also control the size of the word lines, thereby reducing the coupling effect between word line steps.
  • Figure 1 is a schematic flowchart of a semiconductor structure forming method provided by an embodiment of the present disclosure
  • FIGS 2a to 2m and Figures 3a to 3i are schematic structural diagrams of the semiconductor structure formation process provided by embodiments of the present disclosure
  • Figures 4a to 4c are schematic structural diagrams of semiconductor structures provided by embodiments of the present disclosure.
  • 5a and 5b are schematic planar structural diagrams of semiconductor structures provided by embodiments of the present disclosure.
  • Figures 6a and 6b are plan layout views of the layout structure provided by the embodiment of the present disclosure.
  • the three directions may include the X-axis, Y-axis, and Z-axis directions.
  • the substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side; when flatness of the top surface and the bottom surface is ignored, a direction perpendicular to the top surface and the bottom surface of the substrate is defined as a third direction.
  • a direction perpendicular to the top surface and the bottom surface of the substrate is defined as a third direction.
  • the direction of the top surface and the bottom surface of the substrate ie, the plane on which the substrate is located
  • define two directions that intersect each other for example, are perpendicular to each other).
  • the direction in which the word line extends can be defined as the first direction
  • the extension direction of the capacitor structure can be defined as The second direction
  • the planar direction of the substrate can be determined based on the first direction and the second direction.
  • the first direction, the second direction and the third direction are perpendicular to each other.
  • the first direction is defined as the X-axis direction
  • the second direction is defined as the Y-axis direction
  • the third direction is defined as the Z-axis direction.
  • FIG. 1 is a schematic flowchart of a method for forming a semiconductor structure provided by an embodiment of the disclosure. As shown in Figure 1, the method for forming a semiconductor structure includes the following steps:
  • Step S101 Provide a substrate; the substrate includes a first region and a second region arranged sequentially along the second direction; the first region includes active layers spaced apart along the third direction.
  • the substrate at least includes a semiconductor substrate.
  • the semiconductor substrate may be a silicon substrate.
  • the semiconductor substrate may also include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC). ), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or include other semiconductor alloys, such as silicon germanium (SiGe) , gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), and/or indium gallium arsenide phosphide ( GaInAsP) or a combination thereof.
  • germanium germanium
  • GaP gallium ar
  • the first region and the second region can be used to form different functional structures respectively.
  • the first region can be used to form a gate structure and a stepped word line structure
  • the second region can be used to form a capacitor. structure and bit line structure.
  • Step S102 Form an initial gate structure located on the surface of the active layer in the first region.
  • the initial gate structure includes a gate dielectric layer and a gate conductive layer located on the surface of the gate dielectric layer.
  • Step S103 Etch the initial gate structure to form a comb-shaped gate structure stacked along a third direction; wherein the comb-shaped gate structure at least includes first gate structures spaced apart in the first direction.
  • the first gate structure may be a double gate structure, and the first gate structure covers the first surface and the second surface of the active layer along the third direction.
  • the projection of the first gate structure on the substrate surface may be U-shaped. In other embodiments, the projection of the first gate structure on the substrate surface may also be rectangular.
  • the comb gate structure further includes: a second gate structure connected to the first gate structure located on the same layer.
  • the second gate structure may be a three-sided gate structure.
  • the second gate structure covers the first surface and the second surface of the active layer along the third direction, and covers one surface of the active layer along the second direction.
  • the size of the first gate structure in the second direction may be 2 to 3 times the size of the second gate structure in the second direction.
  • multiple comb-shaped gate structures located on the same layer in the first direction are connected to each other through the second gate structure, and the gate metal layer of the comb-shaped gate structure can be used as a word line of the semiconductor structure.
  • the gate metal layer of the comb-shaped gate structure can be used as a word line of the semiconductor structure.
  • Step S104 Form a bit line structure extending along the third direction and a capacitor structure extending along the second direction in the second region.
  • the bit line structure and the capacitor structure are both connected to the first gate structure.
  • the capacitor structures formed in the embodiments of the present disclosure extend along the second direction. That is to say, the capacitor structures formed in the embodiments of the present disclosure are arranged horizontally.
  • the horizontal capacitor structures can reduce the possibility of tipping or breaking, thereby reducing the possibility of tipping or breaking.
  • the stability of the capacitor structure can be improved.
  • multiple horizontal capacitor structures and comb-shaped gate structures can be stacked to form a three-dimensional semiconductor structure, thereby improving the integration of the semiconductor structure and achieving shrinkage.
  • Figures 2a-2m and Figures 3a-3i are structural schematic diagrams of the formation process of the semiconductor structure provided by the embodiment of the present disclosure. The following is a detailed description of the formation process of the semiconductor structure provided by the embodiment of the present disclosure in conjunction with Figures 2a-2m and Figures 3a-3i. illustrate.
  • step S101 is performed to provide a substrate; the substrate includes a first region A and a second region B sequentially arranged along the second direction; the first region A includes active layers spaced apart along the third direction. 13.
  • the substrate may be formed by the following steps: providing a semiconductor substrate 10; forming a stacked structure 11 located in the first region A and the second region B on the surface of the semiconductor substrate 10; the stacked structure 11 includes alternating stacks the first semiconductor layer 111 and the second semiconductor layer 112; remove the first semiconductor layer 111 in the first region A to expose the second semiconductor layer 112 in the first region A; to the exposed second semiconductor layer 112 A thinning process is performed to form the initial active layer 12; the initial active layer 12 is processed to form the active layer 13.
  • a stacked structure 11 located in the first region A and the second region B is formed on the surface of the semiconductor substrate 10; the stacked structure 11 includes alternately stacked first semiconductor layers 111 and second semiconductor layers. 112.
  • the material of the first semiconductor layer 111 may be germanium (Ge), silicon germanium (SiGe), or silicon carbide; it may also be silicon-on-insulator (SOI) or germanium-on-insulator. (Germanium-on-Insulator, GOI).
  • the second semiconductor layer 112 may be a silicon layer, or may include other semiconductor elements, such as germanium, or semiconductor compounds, such as silicon carbide, gallium arsenide, gallium indium phosphide, indium arsenide or indium antimonide, Or include other semiconductor alloys, such as: silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, indium gallium phosphide, and/or indium gallium arsenide phosphide or combinations thereof.
  • the materials of the first semiconductor layer 111 and the second semiconductor layer 112 are different because the first semiconductor layer 111 needs to be removed later and the second semiconductor layer 112 remains. Therefore, the first semiconductor layer 111 has a larger etching selectivity ratio relative to the second semiconductor layer 112.
  • the etching selectivity ratio of the first semiconductor layer 111 relative to the second semiconductor layer 112 can be 5 to 15, so that during etching During the etching process, the first semiconductor layer 111 is easier to be removed by etching than the second semiconductor layer 112 .
  • the thickness of the first semiconductor layer 111 may be 5-50 nanometers (nm), such as 8 nm or 45 nm; the thickness of the second semiconductor layer 112 may be 15-100 nm, such as 20 nm or 75 nm.
  • the number of layers of the first semiconductor layer 111 and the second semiconductor layer 112 in the stacked structure 11 can be set according to the required capacitance density (or storage density). The greater the number of layers of the first semiconductor layer 111 and the second semiconductor layer 112, the higher the number of layers. The resulting semiconductor structure has a higher degree of integration and a greater capacitance density.
  • the first semiconductor layer 111 and the second semiconductor layer 112 can be formed by any of the following deposition processes: chemical vapor deposition (Chemical Vapor Deposition, CVD) process, physical vapor deposition (Physical Vapor Deposition, PVD) process, Atomic Layer Deposition (ALD) process, spin coating process, coating process or thin film process, etc.
  • CVD chemical Vapor Deposition
  • PVD physical vapor deposition
  • ALD Atomic Layer Deposition
  • spin coating process coating process or thin film process, etc.
  • the first semiconductor layer 111 in the first region A is removed to expose the second semiconductor layer 112 in the first region A.
  • the first semiconductor layer 111 in the stacked structure 11 can be removed by wet etching (for example, using strong acid etching such as concentrated sulfuric acid, hydrofluoric acid, concentrated nitric acid, etc.) or dry etching technology. Since the first semiconductor layer 111 has a high etching selectivity ratio relative to the second semiconductor layer 112, the second semiconductor layer 112 may not be damaged when the first semiconductor layer 111 is removed.
  • the exposed second semiconductor layer 112 is thinned to form an initial active layer 12 .
  • the second semiconductor layer 112 can be thinned in the following two ways to form the initial active layer 12:
  • Method 1 Directly dry-etch the second semiconductor layer 112 until the required thickness is formed, and then stop etching.
  • Method two oxidize the second semiconductor layer 112 in situ, oxidize part of the second semiconductor layer 112 into a silicon oxide layer, and remove the silicon oxide layer through wet etching or dry etching technology.
  • the second semiconductor layer 112 is thinned to 15-20 nm to form the initial active layer 12.
  • the thickness of the formed initial active layer 12 can be 18 nm. In this way, a fully depleted semiconductor layer can be formed.
  • holes are easily recombined in the source area without accumulation, so the floating body effect can be improved; in addition, since the gap between two adjacent initial active layers 12 becomes larger, so, A larger space can be reserved for the subsequent formation of the gate structure and the word line structure, thereby reducing the word line coupling effect, the complexity of the preparation process and the manufacturing cost of the gate structure and the word line structure.
  • the second semiconductor layer 112 may not be thinned.
  • processing the initial active layer 12 to form the active layer 13 may include the following steps: sequentially forming a sacrificial layer 121 and a first isolation layer 122 on the surface of the initial active layer 12; wherein, the first isolation layer 122 fills the gaps between the sacrificial layers 121.
  • the initial active layer 12 with the first length in the second direction is removed to form a first space; the sacrificial layer 121 with the second length in the second direction is removed to expose part of the initial active layer 12 to form the second space.
  • the second space includes the first space, and the second length is greater than the first length, and the exposed part of the initial active layer 12 constitutes the active layer 13.
  • a sacrificial layer 121 and a first isolation layer 122 are sequentially formed on the surface of the initial active layer 12, and the initial active layer 12 with a first length L1 in the Y-axis direction is removed to form a first space.
  • the material of the sacrificial layer 121 may be silicon oxide or other suitable materials.
  • the material of the first isolation layer 122 may be silicon nitride or other suitable materials.
  • the sacrificial layer 121 has different etching selectivity ratios relative to the first isolation layer 122.
  • the etching selectivity ratio between the sacrificial layer 121 and the semiconductor substrate 10 is the same as the etching selectivity ratio between the first isolation layer 122 and the semiconductor substrate 10.
  • the etching selectivity ratio is 5 to 10 times.
  • Both the sacrificial layer 121 and the first isolation layer 122 can be formed by any suitable deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a spin coating process, a coating process, or a furnace tube process.
  • a chemical vapor deposition process such as a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a spin coating process, a coating process, or a furnace tube process.
  • the thickness of the sacrificial layer 121 may be 15-20 nm, for example, 17 nm; the thickness of the first isolation layer 122 may be 10-20 nm, for example, 15 nm.
  • the first isolation layer 122 can, on the one hand, isolate two adjacent comb-shaped gate structures, and on the other hand, it can serve as a support structure for the semiconductor structure together with the subsequently formed support layer, thereby improving the stability of the semiconductor structure. sex.
  • a wet etching process may be used to remove the initial active layer 12 having the first length L1 by lateral etching.
  • the etching solution used in wet etching can be a hydrofluoric acid solution or a mixed solution of dilute hydrofluoric acid and ammonia.
  • the sacrificial layer 121 with the second length L2 in the second direction is removed to expose part of the initial active layer 12 to form a second space D; where the second space D includes the first space C, and The second length L2 is greater than the first length L1 , and the exposed portion of the initial active layer 12 constitutes the active layer 13 .
  • a wet etching process can be used to remove the sacrificial layer 121 with the second length L2 laterally to form the active layer 13.
  • the etching solution used in the wet etching can be dilute hydrofluoric acid and Mixed solution of ammonia and water.
  • the sacrificial layer 121 is not completely removed, and the remaining part of the sacrificial layer 121 is used to isolate the comb-shaped gate structure and the bit line structure formed later, and the comb-shaped gate structure and the bit line structure. capacitor structure to reduce the generation of leakage current.
  • step S102 is performed to form an initial gate structure 14 located on the surface of the active layer 13 in the first region A.
  • the initial gate structure 14 may be formed by the following steps: sequentially forming a gate dielectric layer 141 and a gate conductive layer 142 on the surface of the active layer 13 , and the gate conductive layer 142 fills the second space D.
  • the material used for the gate dielectric layer 141 may be silicon oxide or other suitable materials; the material used for the gate conductive layer 142 may include polysilicon, metal (such as tungsten, copper, aluminum, titanium, tantalum, ruthenium). , etc.), metal alloys, metal silicides, titanium nitride, one or any combination.
  • the gate dielectric layer 141 can be formed through an in-situ steam generation (ISSG,) process, and the thickness of the gate dielectric layer 141 can be 4.5 to 10 nm, such as 5 nm or 9 nm.
  • the gate conductive layer 142 can be formed by any suitable deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, and an atomic layer deposition process.
  • FIGS. 2j and 2k are cross-sectional views of the comb-shaped gate structure.
  • the comb gate structure 17 may at least include first gate structures spaced apart in the first direction. In other embodiments, the comb gate structure 17 may further include: The first gate structures 171 are connected to the second gate structures 172 .
  • the comb gate structure 17 includes: a first gate structure 171 and a second gate structure 172.
  • the second gate structure 172 is connected to the first gate structure 171 located on the same layer.
  • the projection of the first gate structure 171 on the substrate surface may be U-shaped; the first gate structure 171 may be a double gate structure, for example, the first gate structure 171 covers On the top and bottom surfaces of the active layer, the size of the first gate structure 171 in the Y-axis direction may be 2 to 3 times the size of the second gate structure 172 in the Y-axis direction.
  • the projection of the first gate structure 171 on the substrate surface may also be rectangular.
  • the comb gate structure 17 can be formed by the following steps: simultaneously removing part of the initial gate structure and part of the stacked structure 11 in the second region B to form a L-shaped grooves 15 and isolation grooves 16 are arranged alternately in directions, and the remaining initial gate structure forms a comb-shaped gate structure 17; wherein, the size L3 of the isolation groove 16 in the second direction is larger than the size L3 of the L-shaped groove 15 in the second direction. Dimension L4 in the second direction.
  • the isolation groove 16 divides the active layer into a plurality of active structures 130 arranged along the X-axis direction.
  • the two laminated structures located on both sides of the L-shaped groove 15 along the X-axis direction have different sizes in the second direction, for example, the first laminated structure 11a and the second laminated structure 11b is located on both sides of the L-shaped groove 15 along the X-axis direction, and the dimension L5 of the first laminated structure 11a in the Y-axis direction is larger than the dimension L6 of the second laminated structure 11b in the Y-axis direction.
  • a dry method such as a plasma etching process, a reactive ion etching process, or an ion milling process
  • a wet etching process may be used to etch the initial gate structure and part of the stack in the second region B.
  • the gases used in dry etching can be trifluoromethane (CHF 3 ), carbon tetrafluoride (CF 4 ), difluoromethane (CH 2 F 2 ), hydrobromic acid (HBr), chlorine (Cl 2 ) Or one of sulfur hexafluoride (SF 6 ) or their combination.
  • the formed comb-shaped gate structure 17 has a wider channel region, which can reduce the short channel effect, thereby improving the performance of the formed semiconductor structure.
  • the method of forming the semiconductor structure further includes: forming word line steps 18 sequentially stacked along the third direction; wherein, in the word line steps 18 Each layer of word lines is electrically connected to a plurality of second gate structures 172 in the corresponding comb-shaped gate structures arranged along the first direction.
  • a photoresist layer with a first opening is formed on the surface of the first region A; the first opening exposes one end of the first region A; through the photoresist layer with the first opening Etch the first region A to form a first ladder structure; secondly, form a photoresist layer with a second opening on the surface of the first ladder structure, and the second opening exposes part of the first ladder structure, and use photolithography with the second opening to
  • the first step structure is etched into the glue layer to form a second step structure, in which the size of the second opening in the first direction is larger than the size of the first opening; again, a photoresist layer with a third opening is formed on the surface of the second step structure.
  • the third opening exposes part of the second step structure, and the second step structure is etched through the photoresist layer of the third opening to form a third step structure, wherein the size of the third opening in the first direction is larger than the size of the second opening; Repeat the above steps and undergo multiple etching processes to finally form word line steps 18 , which have a length that decreases layer by layer from bottom to top along the Z-axis direction.
  • the word line step 18 may also be formed by the following steps: first, forming a first word line with a first length on the substrate surface in the first region A, wherein the first word line is aligned with the X-axis direction.
  • the first layer comb gate structure 17 on the bottom layer is electrically connected; secondly, a first isolation unit with a second length is formed on the surface of the first word line; a second word with a second length is formed on the surface of the first isolation unit.
  • the second word line is electrically connected to the second layer comb gate structure 17 of the previous bottom layer along the first direction, wherein the first length is greater than the second length, and the first isolation unit is configured to isolate the adjacent first word line and the second word line; again, a second isolation unit with a third length is formed on the surface of the second word line; a third word line with a third length is formed on the surface of the second isolation unit, wherein the third word line is The third layer comb gate structure 17 is electrically connected from bottom to top along the X-axis direction, wherein the second length is greater than the third length, and the second isolation unit is configured to isolate the adjacent second word line and the third word line. ; Repeat the above steps, and after multiple forming processes, a word line step 18 composed of multiple word lines is formed.
  • the comb-shaped gate structure 17 is formed and the word line side connection method is used, which not only solves the problem that the interconnection of word lines on the same plane is difficult to achieve for multi-layer stacking, but also can control the side connection by wordline size to control wordline coupling.
  • step S104 is performed to form a bit line structure 22 extending along the third direction and a capacitance structure 24 extending along the second direction in the second area B.
  • the bit line structure 22 and the capacitance structure 24 are both similar to The first gate structure 171 is connected.
  • the formation method of the semiconductor structure includes: filling the L-shaped groove 15 and the isolation groove 16 with isolation material, forming Second isolation layer 19.
  • the isolation material may be silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials.
  • the second isolation layer 19 can be formed by any deposition process.
  • the second isolation layer 19 and the first semiconductor layer 111 located in the second region B are removed to expose the second semiconductor layer in the first stacked structure 11a and the second stacked structure 11b. 112.
  • the exposed second semiconductor layer 112 respectively forms first active pillars 131 and second active pillars 132 arranged alternately along the X-axis direction; wherein, the first active pillars 131 include The second active pillar 132 is within the projection area of the first sub-pillar 1311 along the X-axis direction.
  • the second sub-pillar 1312 is used to form a capacitor structure; the second active pillar 132 is used to form a bit line structure.
  • the second isolation layer 19 and the first semiconductor layer 111 located in the second region B can be removed by dry etching technology or wet etching technology.
  • the first active pillar 131 and the second active pillar 132 can also be thinned.
  • the thinning process includes the following two methods:
  • Method 1 Directly dry-etch the first active pillar 131 and the second active pillar 132 until the required thickness is formed, then stop etching.
  • Method two oxidize the first active pillar 131 and the second active pillar 132 in situ, oxidize part of the first active pillar 131 and part of the second active pillar 132 into a silicon oxide layer, and use wet etching or dry etching. Etching technology removes the silicon oxide layer.
  • the gap between the adjacent first active pillar 131 and the second active pillar 132 becomes larger.
  • the effective area between the electrodes of the formed capacitor structure can be increased, thereby increasing the capacitance of the formed capacitor structure; on the other hand, the process complexity of the capacitor structure and the bit line structure can be reduced, and the manufacturing cost of the semiconductor structure can be reduced.
  • the method of forming the semiconductor structure further includes: forming a support layer 23 on the surface of the first sub-pillar 1311 . ; The support layer 23 is filled between the first sub-pillars 1311.
  • the material of the support layer 23 can be silicon nitride or silicon carbonitride; on the one hand, the support layer 23 is used to support the subsequent formation of the capacitor structure, prevent the collapse of the capacitor structure, and improve the stability of the formed semiconductor structure. ; On the other hand, it can isolate adjacent capacitor structures, as well as capacitor structures and bit line structures, to reduce the generation of leakage current.
  • the method of forming the semiconductor structure further includes: forming a first protective layer 21 on the surface of the first region A and the second active pillar 132.
  • the layer 21 is used to protect the already formed comb-shaped gate structure 17 and the second active pillar 132 in the first region A from damage when forming the capacitor structure 24 .
  • the material of the first protective layer 21 may be a low dielectric constant (Low K) material, for example, it may be doped silicon dioxide, organic polymer or porous material.
  • the capacitor structure 24 can be formed by the following steps: sequentially forming a first electrode layer 241, a dielectric layer 242 and a second electrode layer 243 on the surface of the second sub-pillar 1312, so as to Capacitor structure 24 is formed.
  • the first electrode layer 241, the dielectric layer 242 and the second electrode layer 243 can be formed by any one of the following deposition processes: selective atomic layer deposition process, chemical vapor deposition process, physical vapor deposition process and spin coating. Craftsmanship.
  • the material of the first electrode layer 241 and the second electrode layer 243 may include metal or metal nitride, for example, ruthenium (Ru) or titanium nitride.
  • the material of the dielectric layer 242 may include a high-K dielectric material, such as lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), hafnium oxynitride (HfON), or hafnium silicate.
  • lanthanum oxide La 2 O 3
  • Al 2 O 3 aluminum oxide
  • hafnium oxide HfO 2
  • hafnium oxynitride HfON
  • hafnium silicate One or any combination of (HfSiOx) or zirconium oxide (ZrO 2 ).
  • the material of the first electrode layer and the second electrode layer may also be polysilicon.
  • the capacitor structure 24 extends along the Y-axis direction, that is to say, the capacitor structure 24 is horizontal.
  • the horizontal capacitor structure can reduce the possibility of tipping or breaking, thereby improving the stability of the capacitor structure;
  • the stacked structure formed by stacking multiple capacitor structures in the vertical direction can form a three-dimensional semiconductor structure, which can improve the semiconductor structure.
  • the degree of integration enables microcomputerization.
  • the method of forming the semiconductor structure before forming the first electrode layer 241 , further includes: forming metal silicide on the surface of the second sub-pillar 1312 .
  • a layer of metal material may be deposited on the surface of the second sub-pillar 1312, for example, it may be cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), tungsten (W), platinum (Pt) ) and palladium (Pd); then rapid thermal annealing is performed to cause the metal material to react with the second sub-pillar 1312, thereby forming metal silicide on the surface of the second sub-pillar 1312. Since the metal silicide has a lower resistance value, the contact resistance between the lower electrode and the second sub-pillar can be reduced, thereby reducing the power consumption of the semiconductor structure.
  • the method further includes: removing the first protective layer 21 .
  • removing the first protective layer 21 For example, a dry or wet etching process may be used to remove the first protective layer 21 .
  • the method of forming a semiconductor structure further includes: forming a conductive layer on the surface of the second electrode layer 243, and filling the conductive layer between adjacent second electrode layers 243.
  • the material of the conductive layer may be polysilicon or any other suitable conductive material, such as doped polysilicon.
  • the forming method of the semiconductor structure further includes: forming a second protective layer 20 on the surface of the first region A, the support layer 23 and the capacitor structure 24.
  • the two protective layers 20 are used to protect the formed comb gate structure 17, the support layer 23 and the capacitor structure 24 from damage when forming the bit line structure 22.
  • the material of the second protective layer 20 may be a low dielectric constant material, for example, it may be doped silicon dioxide, organic polymer or porous material.
  • the bit line structure 22 may be formed by the following steps: forming a third semiconductor layer 221 and a bit line metal layer 222 on the surface of the second active pillar 132 in sequence.
  • the material of the third semiconductor layer 221 may be metal silicide. Since metal silicide has a lower resistance, the contact resistance between the bit line metal layer 222 and the second active pillar 132 can be reduced, thereby further enabling Reduce power consumption in semiconductor structures.
  • the material of the bit line metal layer 222 can be any material with good electrical conductivity, such as tungsten, cobalt, copper, aluminum, titanium nitride, titanium-containing metal layer, polysilicon, or any combination thereof.
  • the method of forming the semiconductor structure further includes: removing the second protective layer 20 .
  • a comb-shaped gate structure is formed and the word line side connection method is used, which not only solves the problem that the interconnection of word lines on the same plane is difficult to achieve for multi-layer stacking, but also can control the side connection by word line size to reduce word line coupling.
  • the capacitor structure in the embodiment of the present disclosure extends along the second direction, that is, the capacitor structure in the embodiment of the present disclosure is horizontal, compared with the vertical capacitor structure with a high aspect ratio, the horizontal capacitor structure can reduce the risk of tipping or The possibility of breaking can improve the stability of the capacitor structure, and the stacked structure formed by stacking multiple capacitor structures in the third direction can form a three-dimensional semiconductor structure, thereby improving the integration of the semiconductor structure and achieving shrinkage.
  • Embodiments of the present disclosure also provide a semiconductor structure.
  • Figures 4a to 4c are schematic structural diagrams of the semiconductor structure provided by embodiments of the present disclosure, wherein Figure 4a is a three-dimensional view.
  • the semiconductor structure 100 at least includes: a semiconductor substrate 10.
  • the semiconductor substrate 10 includes a first region A and a second region B sequentially arranged along the second direction (Y-axis direction); located on the semiconductor substrate 10 active structures 130 on the surface; the active structures 130 are arranged in an array along the first direction (X-axis direction) and the third direction (Z-axis direction); the comb-shaped gate structure 17 is an active structure located on the first area A surface, and the comb-shaped gate structure 17 at least includes first gate structures 171 spaced apart in the X-axis direction.
  • the semiconductor structure 100 further includes: a bit line structure 22 extending along the Z-axis direction and a capacitor structure 24 extending along the Y-axis direction; both the bit line structure 22 and the capacitor structure 24 are located on the second region B, and are connected to the first gate structure 171 .
  • the capacitor structure 24 includes a first electrode layer 241 , a dielectric layer 242 and a second electrode layer 243 .
  • the bit line structure 22 includes a third semiconductor layer 221 and a bit line metal layer 222.
  • the comb gate structure 17 further includes: a second gate structure 172 connected to the first gate structure 171 located on the same layer.
  • the active structure 130 includes a first active pillar 131 and a second active pillar 132 located on the second area B and arranged along the X-axis direction, and located on the second area B.
  • the channel pillar 25 on an area A; the first active pillar 131 and the second active pillar 132 are both connected to the channel pillar 25 .
  • the first gate structure 171 at least covers the first surface and the second surface of the channel pillar 25 along the Z-axis direction; wherein the first gate structure 171 includes a stacked gate dielectric layer 141 and a gate conductive layer 142 .
  • the projection of the channel pillar 25 on the semiconductor substrate 10 is U-shaped. In other embodiments, the projection of the channel pillar 25 on the semiconductor substrate 10 may also be rectangular.
  • the first active pillar 131 includes a first sub-pillar (not shown) and a second sub-pillar 1312.
  • the capacitive structure 24 is formed on the second sub-pillar 1312; the bit line structure 22 is formed on the second active pillar 132; there is an L-shaped groove 15 between the first active pillar 131 and the second active pillar 132 of the same active structure 130.
  • the semiconductor structure 100 further includes: a support layer 23, the support layer 23 is located on the surface of the first sub-pillars, and the support layer 23 is filled between the first sub-pillars.
  • the support layer 23 is used to support a plurality of capacitor structures 24 , a plurality of bit line structures 22 , and a plurality of comb gate structures 17 stacked along the Z-axis direction.
  • the semiconductor structure 100 further includes: word line steps 18; the word line steps 18 are stacked sequentially along the Z-axis direction, and each layer of word lines in the word line steps is connected to the corresponding word line along the X-axis.
  • a plurality of second gate structures 172 in the comb-shaped gate structures 17 arranged in the axial direction are connected.
  • the first gate structure may be a double gate structure, and the size of the first gate structure 171 in the Y-axis direction may be 2 to 3 times the size of the second gate structure 172 in the Y-axis direction. .
  • the comb-shaped gate structure formed has a very wide channel area, which can reduce the short channel effect.
  • the double gate structure formed can further improve the control capability of the gate, thereby improving the formed Properties of Semiconductor Structures.
  • the semiconductor structure provided by the embodiments of the present disclosure is similar to the formation method of the semiconductor structure provided by the above-mentioned embodiments.
  • the semiconductor structure provided by the embodiments of the present disclosure forms a comb-shaped gate structure, and the word line structure is located outside the comb-shaped gate structure, which can realize the interconnection of word lines on the same plane in a multi-layer stacked structure; in addition, the implementation of the present disclosure
  • the capacitor structure in the example is horizontal and arranged in an array along the first and third directions.
  • the horizontal capacitor structure can reduce the possibility of tipping or breaking.
  • the stacked structure formed by stacking multiple capacitor structures in the third direction can Forming a three-dimensional semiconductor structure can improve the integration of the semiconductor structure and achieve shrinkage.
  • Figures 5a and 5b are schematic planar structural views of a semiconductor structure provided by embodiments of the present disclosure.
  • the semiconductor structure 100 includes: a first gate structure 171 arranged in an array along the X-axis direction and the Z-axis direction.
  • the bit line structure 22 and the capacitor structure 24 are connected to the comb gate structure 17 .
  • a first gate structure 171 and a capacitor structure 24 constitute a memory unit; memory cells adjacent along the X-axis direction have the same layout (as shown in Figure 5a), or are adjacent along the X-axis direction.
  • the memory unit is axially symmetrical (as shown in Figure 5b).
  • the semiconductor structure 100 includes: a second gate structure 172 connected to the first gate structure 171 of the same layer, a second gate structure 172 arranged along the X-axis direction and located on the same layer.
  • a gate structure 171 and a second gate structure 172 form a comb gate structure 17 .
  • the semiconductor structure 100 further includes word line steps 18 extending along the X-axis direction, wherein each layer of word lines in the word line steps 18 has a corresponding word line along the X-axis direction.
  • the plurality of arranged first gate structures 171 are electrically connected.
  • Figures 6a and 6b are planar layout diagrams of the layout structure provided by the embodiment of the present disclosure.
  • the layout structure 200 includes: the above-mentioned semiconductors arranged at intervals along the Y-axis direction. Structure 100.
  • the semiconductor structure 100 includes a plurality of memory cells arranged in an array along the X-axis direction and the Z-axis direction; the memory unit includes at least a first gate structure 171 and a capacitor structure 24; wherein, the Y-axis Two adjacent memory cells in the direction are centrally symmetrical; and the projection areas of the capacitive structures 24 of the two adjacent memory cells in the Y-axis direction in the X-axis direction at least partially overlap.
  • the memory cell further includes a second gate structure 172 , wherein the first gate structure 171 and the second gate structure 172 constitute a comb-shaped gate structure 17 .
  • the semiconductor structure 100 also includes a bit line structure 22 and a word line step 18 .
  • two adjacent memory cells in the X-axis direction have the same layout.
  • the layout of two adjacent memory cells in the X-axis direction is axially symmetrical.
  • the layout structure provided by the embodiments of the present disclosure can effectively utilize the space in the semiconductor structure and realize the shrinkage of the semiconductor structure.
  • the disclosed devices and methods can be implemented in a non-target manner.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • the gate metal layer outside the comb-shaped gate structure can be used as a word line of the semiconductor structure, not only the multi-layer stacked structure can be realized through the comb-shaped gate structure
  • the interconnection of word lines on the same plane can also control the size of the word lines, thereby reducing the coupling effect between word line steps.

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Abstract

本公开实施例提供一种半导体结构及其形成方法、版图结构，其中，所述方法包括：提供基底；基底包括沿第二方向依次排列的第一区域和第二区域；第一区域包括沿第三方向间隔排列的有源层；在第一区域中形成位于有源层表面的初始栅极结构；刻蚀初始栅极结构，形成沿第三方向堆叠的梳状栅极结构；其中，梳状栅极结构至少包括在第一方向上间隔排列的第一栅极结构；第一方向、第二方向和第三方向两两相互垂直，且第一方向与第二方向平行于基底表面；在第二区域形成沿第三方向延伸的位线结构和沿第二方向延伸的电容结构，位线结构与电容结构均与第一栅极结构连接。

Description

半导体结构及其形成方法、版图结构
相关申请的交叉引用
本公开基于申请号为202210730342.3、申请日为2022年06月24日、发明名称为“半导体结构及其形成方法、版图结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，涉及但不限于一种半导体结构及其形成方法、版图结构。
背景技术
当前，多采用6F 2的排布方式和掩埋字线工艺来制作动态随机存储器(Dynamic Random Access Memory，DRAM)，然而，在这种工艺下DRAM的微缩变得十分困难，也有通过使用新材料来改善DRAM的性能，然而，这无疑提高了DRAM的工艺复杂度和制造成本。
基于此，相关技术中，采用全环栅或双栅工艺制作4F 2的DRAM，4F 2的DRAM需要形成位线台阶或者字线台阶，然而，位线台阶在DRAM的使用中存在比较大的感测噪音(Sensing Noise)，字线台阶存在字线耦合(Word Line Coupling)以及工艺上同一平面上字线的互联对于多层堆叠来说难以实现的问题。
发明内容
有鉴于此，本公开实施例提供一种半导体结构及其形成方法、版图结构。
第一方面，本公开实施例提供一种半导体结构的形成方法，所述方法包括：
提供基底；所述基底包括沿第二方向依次排列的第一区域和第二区域；所述第一区域包括沿第三方向间隔排列的有源层；
在所述第一区域中形成位于所述有源层表面的初始栅极结构；
刻蚀所述初始栅极结构，形成沿所述第三方向堆叠的梳状栅极结构；其中，所述梳状栅极结构至少包括在第一方向上间隔排列的第一栅极结构；所述第一方向、所述第二方向和所述第三方向两两相互垂直，且所述第一方向与所述第二方向平行于所述基底表面；
在所述第二区域形成沿所述第三方向延伸的位线结构和沿所述第二方向延伸的电容结构，所述位线结构与所述电容结构均与所述第一栅极结构连接。
第二方面，本公开实施例提供一种半导体结构，包括：
半导体衬底，所述半导体衬底包括沿第二方向依次排列的第一区域和第二区域；
位于所述半导体衬底表面的有源结构；所述有源结构沿第一方向和第三方向阵列排布；
梳状栅极结构，位于所述第一区域上所述有源结构的表面，且所述梳状栅极结构至少包括在第一方向间隔排列的第一栅极结构；
沿所述第三方向延伸的位线结构；
沿第二方向延伸的电容结构；所述位线结构与所述电容结构均位于所述第二区域上，且均与所述第一栅极结构连接；所述第一方向、所述第二方向和所述第三方向两两相互垂直，且所述第一方向与所述第二方向平行于所述半导体衬底表面。
第三方面，本公开实施例提供一种版图结构，包括：沿第二方向依次间隔排布的上述半导体结构；
所述半导体结构包括沿第一方向和第三方向阵列排布的存储单元；所述存储单元包括一个第一栅极结构和一个电容结构；
其中，所述第二方向上相邻两个存储单元呈中心对称，且所述第二方向上相邻两个存储单元的电容结构在所述第一方向上的投影区域至少部分重合。
本公开实施例中，由于形成了梳状栅极结构，且梳状栅极结构外侧的栅极金属层可以作为半导体结构的字线，如此，通过梳状栅极结构不仅可以实现多层堆叠结构中同一平面上字线的互联，还可以实现控制字线的尺寸，进而减小字线台阶之间的耦合作用。
附图说明
在附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。具 有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
图1为本公开实施例提供的半导体结构形成方法的流程示意图；
图2a～2m、图3a～3i为本公开实施例提供的半导体结构形成过程中的结构示意图；
图4a～4c为本公开实施例提供的半导体结构的结构示意图；
图5a和5b为本公开实施例提供的半导体结构的平面结构示意图；
图6a和6b为本公开实施例提供的版图结构的平面布局图；
附图标记说明如下：
10—半导体衬底；11—叠层结构；11a—第一个叠层结构；11b—第二个叠层结构；111—第一半导体层；112—第二半导体层；12—初始有源层；121—牺牲层；122—第一隔离层；13—有源层；130—有源结构；14—初始栅极结构；141—栅极介质层；142—栅极导电层；15—L型凹槽；16—隔离凹槽；17—梳状栅极结构；171—第一栅极结构；172—第二栅极结构；18—字线台阶；19—第二隔离层；131—第一有源柱；1311—第一子柱；1312—第二子柱；132—第二有源柱；20—第二保护层；21—第一保护层；221—第三半导体层；222—位线金属层；22—位线结构；23—支撑层；24—电容结构；241—第一电极层；242—电介质层；243—第二电极层；25—沟道柱；100—半导体结构；200—版图结构。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其它的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
在介绍本公开实施例之前，先定义一下以下实施例可能用到的描述立体结构的三个方向，以笛卡尔坐标系为例，三个方向可以包括X轴、Y轴和Z轴方向。基底可以包括处于正面的顶表面以及处于与正面相对的背面的底表面；在忽略顶表面和底表面的平整度的情况下，定义垂直基底顶表面和底表面的方向为第三方向。在基底的顶表面和底表面(即基底所在的平面)方向上，定义两彼此相交(例如彼此垂直)的方向，例如可以定义字线延伸的方向为第一方向，定义电容结构的延伸方向为第二方向，基于第一方向和第二方向可以确定基底的平面方向。这里，第一方向、第二方向和第三方向两两垂直。本公开实施例中，定义第一方向为X轴方向，定义第二方向为Y轴方向，定义第三方向为Z轴方向。
本公开实施例提供一种半导体结构的形成方法，图1为本公开实施例提供的半导体结构形成方法的流程示意图，如图1所示，半导体结构的形成方法包括以下步骤：
步骤S101，提供基底；基底包括沿第二方向依次排列的第一区域和第二区域；第一区域包括沿第三方向间隔排列的有源层。
本公开实施例中，基底至少包括半导体衬底，半导体衬底可以是硅衬底，半导体衬底也可以包括其它半导体元素，例如：锗(Ge)，或包括半导体化合物，例如：碳化硅(SiC)、砷化镓(GaAs)、 磷化镓(GaP)、磷化铟(InP)、砷化铟(InAs)或锑化铟(InSb)，或包括其它半导体合金，例如：硅锗(SiGe)、磷化砷镓(GaAsP)、砷化铟铝(AlInAs)、砷化镓铝(AlGaAs)、砷化铟镓(GaInAs)、磷化铟镓(GaInP)、及/或磷砷化铟镓(GaInAsP)或其组合。
本公开实施例中，第一区域和第二区域可以分别用于形成不同的功能结构，例如，第一区域可以用于形成栅极结构和阶梯状字线结构，第二区域可以用于形成电容结构和位线结构。
步骤S102、在第一区域中形成位于有源层表面的初始栅极结构。
本公开实施例中，初始栅极结构包括栅极介质层和位于栅极介质层表面的栅极导电层。
步骤S103、刻蚀初始栅极结构，形成沿第三方向堆叠的梳状栅极结构；其中，梳状栅极结构至少包括在第一方向上间隔排列的第一栅极结构。
本公开实施例中，第一栅极结构可以为双栅结构，第一栅极结构覆盖有源层沿第三方向上的第一表面和第二表面。第一栅极结构在基底表面上的投影可以为U型，在其它实施例中，第一栅极结构在基底表面上的投影也可以为矩形。
在一些实施例中，梳状栅极结构还包括：与位于同一层的第一栅极结构均连接的第二栅极结构。第二栅极结构可以是三面环栅结构，例如，第二栅极结构覆盖有源层沿第三方向上的第一表面和第二表面、且覆盖有源层沿第二方向上的一个表面。
本公开实施例中，第一栅极结构在第二方向上的尺寸可以为第二栅极结构在第二方向上的尺寸的2～3倍。
本公开实施例中，位于第一方向上同一层的多个梳状栅极结构通过第二栅极结构互相连接，梳状栅极结构的栅极金属层可以作为半导体结构的字线，如此，不仅可以实现多层堆叠结构中同一平面上字线的互联，还可以实现控制字线的尺寸，进而减小字线台阶之间的耦合作用。
步骤S104、在第二区域形成沿第三方向延伸的位线结构和沿第二方向延伸的电容结构，位线结构与电容结构均与第一栅极结构连接。
本公开实施例中所形成的电容结构沿第二方向延伸，也就是说，本公开实施例中形成的电容结构呈水平状排布，水平状的电容结构可以减少倾倒或者折断的可能性，从而可以提高电容结构的稳定性。另外，多个水平状的电容结构和梳状栅极结构可以堆叠形成三维的半导体结构，进而可以提高半导体结构的集成度，实现微缩。
图2a～2m、图3a～3i为本公开实施例提供的半导体结构形成过程中的结构示意图，下面结合图2a～2m、图3a～3i对本公开实施例提供的半导体结构的形成过程进行详细的说明。
首先，可以参考图2a～2g，执行步骤S101、提供基底；基底包括沿第二方向依次排列的第一区域A和第二区域B；第一区域A包括沿第三方向间隔排列的有源层13。
在一些实施例中，基底可以通过以下步骤形成：提供半导体衬底10；在半导体衬底10的表面形成位于第一区域A和第二区域B的叠层结构11；叠层结构11包括交替堆叠的第一半导体层111和第二半导体层112；去除第一区域A中的第一半导体层111，以暴露出第一区域A的第二半导体层112；对暴露出的第二半导层112进行减薄处理，以形成初始有源层12；处理初始有源层12，以形成有源层13。
如图2a和2b所示，在半导体衬底10的表面形成位于第一区域A和第二区域B的叠层结构11；叠层结构11包括交替堆叠的第一半导体层111和第二半导体层112。
本公开实施例中，第一半导体层111的材料可以是锗(Ge)、或锗化硅(SiGe)、碳化硅；也可以是绝缘体上硅(Silicon-On-Insulator，SOI)或者绝缘体上锗(Germanium-on-Insulator，GOI)。第二半导体层112可以为硅层，也可以包括其它半导体元素，例如：锗，或包括半导体化合物，例如：碳化硅、砷化镓、磷化镓磷化铟、砷化铟或锑化铟，或包括其它半导体合金，例如：硅锗、磷化砷镓、砷化铟铝、砷化镓铝、砷化铟镓、磷化铟镓、及/或磷砷化铟镓或其组合。
本公开实施例中，第一半导体层111和第二半导体层112的材料不同，因为后续需要去除第一半导体层111，保留第二半导体层112。因此，第一半导体层111相对于第二半导体层112具有较大的选择刻蚀比，例如第一半导体层111相对于第二半导体层112的刻蚀选择比可以为5～15，从而在刻蚀过程中第一半导体层111相对于第二半导体层112更容易被刻蚀去除。
本公开实施例中，第一半导体层111的厚度可以是5～50纳米(nm)，例如为8nm或者45nm；第二半导体层112的厚度可以是15～100nm，例如为20nm或者75nm。叠层结构11中第一半导体层111和第二半导体层112的层数可以根据需要的电容密度(或存储密度)来设置，第一半导体层111和第二半导体层112的层数越多，形成的半导体结构的集成度更高且电容密度越大。
本公开实施例中，第一半导体层111和第二半导体层112可以通过以下任一沉积工艺形成：化学气相沉积(Chemical Vapor Deposition，CVD)工艺、物理气相沉积(Physical Vapor Deposition，PVD)工艺、原子层沉积(Atomic Layer Deposition，ALD)工艺、旋涂工艺、涂敷工艺或薄膜工艺等。
如图2c所示，去除第一区域A中的第一半导体层111，以暴露出第一区域A的第二半导体层112。
本公开实施例中，可以通过湿法(例如，采用浓硫酸、氢氟酸、浓硝酸等强酸刻蚀)或者干法刻蚀技术去除叠层结构11中的第一半导体层111。由于第一半导体层111相对于第二半导体层112具有 高刻蚀选择比，如此，在去除第一半导体层111时可以不损伤第二半导体层112。
如图2d所示，对暴露出的第二半导体层112进行减薄处理，以形成初始有源层12。
本公开实施例中，可以通过以下两种方式对第二半导体层112进行减薄处理，以形成初始有源层12：
方式一：对第二半导体层112直接进行干法刻蚀，直至形成所需要的厚度时，停止刻蚀。
方式二：原位氧化第二半导体层112，将部分第二半导体层112氧化为氧化硅层，通过湿法刻蚀或者干法刻蚀技术去除氧化硅层。
本公开实施例中，将第二半导体层112减薄至15～20nm，形成初始有源层12，例如形成的初始有源层12的厚度可以为18nm，如此，可以形成由全耗尽半导体层形成的沟道区，此时，空穴容易在源区被复合而不会发生累积，所以可以改善浮体效应；另外，由于相邻两个初始有源层12之间的间隙变大，如此，可以为后续栅极结构和字线结构的形成预留出更大的空间，降低了字线耦合作用、以及栅极结构和字线结构的制备工艺复杂度和制造成本。
需要说明的是，在其它实施例中，也可以不对第二半导体层112进行减薄处理。
在一些实施例中，处理初始有源层12，以形成有源层13可以包括以下步骤：在初始有源层12的表面依次形成牺牲层121和第一隔离层122；其中，第一隔离层122充满牺牲层121之间的空隙。去除在第二方向上具有第一长度的初始有源层12，形成第一空间；去除在第二方向上具有第二长度的牺牲层121，暴露出部分初始有源层12，形成第二空间；其中，第二空间包括第一空间、且第二长度大于第一长度，暴露出的部分初始有源层12构成有源层13。
如图2e和2f所示，在初始有源层12的表面依次形成牺牲层121和第一隔离层122，去除在Y轴方向上具有第一长度L1的初始有源层12，形成第一空间C。
本公开实施例中，牺牲层121的材料可以是氧化硅或其它适合的材料。第一隔离层122的材料可以是氮化硅或者其它适合的材料。这里，牺牲层121相对于第一隔离层122具有不同的刻蚀选择比，例如，牺牲层121与半导体衬底10之间的刻蚀选择比是第一隔离层122与半导体衬底10之间的刻蚀选择比的5～10倍。牺牲层121和第一隔离层122均可以通过任意一种合适的沉积工艺形成，例如，化学气相沉积工艺、物理气相沉积工艺、原子层沉积工艺、旋涂工艺、涂敷工艺或者炉管工艺。
本公开实施例中，牺牲层121的厚度可以是15～20nm，例如为17nm；第一隔离层122的厚度可以是10～20nm，例如为15nm。
本公开实施例中，第一隔离层122一方面可以隔离相邻的两个梳状栅极结构，另一方面可以与后续形成的支撑层共同作为半导体结构的支撑结构，从而提高半导体结构的稳定性。
本公开实施例中，可以采用湿法刻蚀工艺侧向刻蚀去除具有第一长度L1的初始有源层12。湿法刻蚀采用的刻蚀溶液可以是氢氟酸溶液，也可以是稀释氢氟酸与氨水的混合溶液。
如图2g所示，去除在第二方向上具有第二长度L2的牺牲层121，暴露出部分初始有源层12，形成第二空间D；其中，第二空间D包括第一空间C、且第二长度L2大于第一长度L1，暴露出的部分初始有源层12构成有源层13。
本公开实施例中，可以采用湿法刻蚀工艺侧向刻蚀去除具有第二长度L2的牺牲层121，形成有源层13，湿法刻蚀采用的刻蚀溶液可以是稀释氢氟酸与氨水的混合溶液。
需要说明的是，在形成有源层13时，牺牲层121未被完全去除，保留的部分牺牲层121用于隔离之后形成的梳状栅极结构与位线结构，以及梳状栅极结构与电容结构，以减少漏电流的产生。
接下来，可以参考图2h和2l，执行步骤S102，在第一区域A中形成位于有源层13表面的初始栅极结构14。
在一些实施例中，初始栅极结构14可以通过以下步骤形成：在有源层13的表面依次形成栅极介质层141和栅极导电层142，栅极导电层142充满第二空间D。
本公开实施例中，栅极介质层141采用的材料可以是氧化硅或者其它适合的材料；栅极导电层142采用的材料可以包括多晶硅、金属(例如钨、铜、铝、钛、钽、钌、等)、金属合金、金属硅化物、氮化钛、中的一种或者任意组合。
本公开实施例中，栅极介质层141可以通过原位水汽生成工艺(In-Situ Steam Generation，ISSG，)形成，栅极介质层141的厚度可以是4.5～10nm，例如为5nm或者9nm。栅极导电层142可以通过任意一种合适的沉积工艺形成，例如，化学气相沉积工艺、物理气相沉积工艺、原子层沉积工艺。
接下来，可以参考图2j和2k，执行步骤S103，刻蚀初始栅极结构14，形成沿第三方向堆叠的梳状栅极结构17。其中，图2j为部分梳状栅极结构的三维视图，图2k和2l为形成梳状栅极结构的剖视图。
在一些实施例中，梳状栅极结构17至少可以包括在第一方向上间隔排列的第一栅极结构，在其它实施例中，梳状栅极结构17还可以包括：与位于同一层的第一栅极结构171均连接的第二栅极结构172。
如图2j所示，梳状栅极结构17包括：第一栅极结构171和第二栅极结构172，第二栅极结构172与位于同一层的第一栅极结构171连接。
本公开实施例中，第一栅极结构171在基底表面(即半导体衬底10)上的投影可以为U型；第一栅极结构171可以为双栅结构，例如第一栅极结构171覆盖有源层的顶面和底面，第一栅极结构171在Y轴方向上的尺寸可以为第二栅极结构172在Y轴方向上的尺寸的2～3倍。
在其它实施例中，第一栅极结构171在基底表面(即半导体衬底10)上的投影还可以为矩形。
在一些实施例中，如图2k和2l所示，梳状栅极结构17可以通过以下步骤形成：同时去除部分初始栅极结构和第二区域B中的部分叠层结构11，形成沿X轴方向交替排列的L型凹槽15和隔离凹槽16，剩余的初始栅极结构构成梳状栅极结构17；其中，隔离凹槽16在第二方向上的尺寸L3大于L型凹槽15在第二方向上的尺寸L4。
本公开实施例中，隔离凹槽16将有源层分割为沿X轴方向排列的多个有源结构130。
本公开实施例中，沿X轴方向位于L型凹槽15两侧的两个叠层结构，在第二方向具有不同的尺寸，例如，第一个叠层结构11a和第二个叠层结构11b沿X轴方向位于L型凹槽15两侧，第一个叠层结构11a在Y轴方向上的尺寸L5大于第二个叠层结构11b在Y轴方向上的尺寸L6。
本公开实施例中，可以采用干法(例如等离子刻蚀工艺、反应离子刻蚀工艺或者离子铣工艺)或者湿法刻蚀工艺来刻蚀初始栅极结构和第二区域B中的部分叠层结构11。其中，干法刻蚀采用的气体可以为三氟甲烷(CHF 3)、四氟化碳(CF 4)、二氟甲烷(CH 2F 2)、氢溴酸(HBr)、氯气(Cl 2)或六氟化硫(SF 6)中的一种或它们的组合。
在本公开实施例中，形成的梳状栅极结构17具有较宽的沟道区，从而可以降低短沟道效应，进而可以提高所形成半导体结构的性能。
在一些实施例中，如图2m所示，在形成梳状栅极结构17之后，半导体结构的形成方法还包括：形成沿第三方向依次堆叠的字线台阶18；其中，字线台阶18中的每一层字线与对应的沿第一方向排列的梳状栅极结构中的多个第二栅极结构172电连接。
在本公开实施例中，首先，在第一区域A的表面形成具有第一开口的光刻胶层；第一开口暴露出第一区域A的一端；通过具有第一开口的光刻胶层的刻蚀第一区域A，形成第一阶梯结构；其次，在第一阶梯结构表面形成具有第二开口的光刻胶层，第二开口暴露部分第一阶梯结构，通过具有第二开口的光刻胶层刻蚀第一阶梯结构形成第二阶梯结构，其中，第二开口在第一方向的尺寸大于第一开口的尺寸；再次，在第二阶梯结构表面形成具有第三开口的光刻胶层，第三开口暴露部分第二阶梯结构，通过第三开口的光刻胶层刻蚀第二阶梯结构形成第三阶梯结构，其中，第三开口在第一方向的尺寸大于第二开口的尺寸；循环上述步骤，经过多次刻蚀过程，最终形成字线台阶18，字线台阶18在沿Z轴方向从下至上具有逐层减小的长度。
在其它实施例中，字线台阶18还可以通过以下步骤形成：首先，在第一区域A的衬底表面形成具有第一长度的第一字线，其中，第一字线与沿X轴方向上最底层的第一层梳状栅极结构17电连接；其次，在第一字线表面形成具有第二长度的第一隔离单元；在第一隔离单元表面形成具有第二长度的第二字线，第二字线与沿第一方向上次底层的第二层梳状栅极结构17电连接，其中，第一长度大于第二长度，第一隔离单元配置为隔离相邻的第一字线和第二字线；再次，在第二字线表面形成具有第三长度的第二隔离单元；在第二隔离单元表面形成具有第三长度的第三字线，其中，第三字线与沿X轴方向自下而上的第三层梳状栅极结构17电连接，其中，第二长度大于第三长度，第二隔离单元配置为隔离相邻的第二字线和第三字线；循环上述步骤，经过多次形成过程，形成由多条字线构成字线台阶18。
本公开实施例中，形成梳状栅极结构17，并采用字线侧接的方法，不仅解决了同一平面上字线的互联对于多层堆叠来说难以实现的问题，还可以通过控制侧接的字线尺寸来控制字线耦合。
最后，可以参考图3a～3i，执行步骤S104、在第二区域B形成沿第三方向延伸的位线结构22和沿第二方向延伸的电容结构24，位线结构22与电容结构24均与第一栅极结构171连接。
在一些实施例中，如图3a和3b所示，在形成位线结构22和电容结构24之前，半导体结构的形成方法包括：在L型凹槽15和隔离凹槽16中填充隔离材料，形成第二隔离层19。
本公开实施例中，隔离材料可以是氧化硅、氮化硅、氮氧化硅或者其它合适的材料。第二隔离层19可以通过任意一种沉积工艺形成。
如图3c和3d所示，去除位于第二区域B的第二隔离层19和第一半导体层111，暴露出第一个叠层结构11a和第二个叠层结构11b中的第二半导体层112，暴露出的第二半导体层112，分别形成沿X轴方向交替排列的第一有源柱131和第二有源柱132；其中，第一有源柱131包括沿X轴方向依次排布的第一子柱1311和第二子柱1312，第二有源柱132在第一子柱1311沿X轴方向上的投影区域内。本公开实施例中，第二子柱1312用于形成电容结构；第二有源柱132用于形成位线结构。
本公开实施例中，可以通过干法刻蚀技术刻蚀技术或湿法刻蚀技术去除位于第二区域B中的第二隔离层19和第一半导体层111。
在其它实施例中，还可以对第一有源柱131和第二有源柱132进行减薄处理，减薄处理的方式包括以下两种：
方式一：对第一有源柱131和第二有源柱132直接进行干法刻蚀，直至形成所需要的厚度时，停 止刻蚀。
方式二：原位氧化第一有源柱131和第二有源柱132，将部分第一有源柱131和部分第二有源柱132氧化为氧化硅层，通过湿法刻蚀或者干法刻蚀技术去除氧化硅层。
本公开实施例中，通过对第一有源柱131和第二有源柱132进行减薄处理，使得相邻的第一有源柱131和第二有源柱132之间的空隙变大，一方面，可以提高形成的电容结构电极之间的有效面积，进而提高形成的电容结构的电容量；另一方面，可以降低电容结构和位线结构的工艺复杂度，降低半导体结构的制造成本。
在一些实施例中，如图3e所示，在形成电容结构24之前，且在形成第一有源柱131之后，半导体结构的形成方法还包括：在第一子柱1311的表面形成支撑层23；支撑层23填充于第一子柱1311之间。
本公开实施例中，支撑层23的材料可以是氮化硅或者碳氮化硅；支撑层23一方面用于支撑后续形成电容结构，防止电容结构的坍塌，提高了形成的半导体结构的稳定性；另一方面，可以隔离相邻的电容结构，以及电容结构与位线结构，减少漏电流的产生。
本公开实施例中，如图3f所示，在形成电容结构之前，半导体结构的形成方法还包括：在第一区域A和第二有源柱132的表面形成第一保护层21，第一保护层21用于在形成电容结构24时保护第一区域A已经形成的梳状栅极结构17和第二有源柱132部分不受损伤。第一保护层21的材料可以为低介电常数(Low K)材料，例如，可以是掺杂二氧化硅、有机聚合物或者多孔材料。
在一些实施例中，如图3g和3h所示，电容结构24可以通过以下步骤形成：在第二子柱1312的表面依次形成第一电极层241、电介质层242和第二电极层243，以形成电容结构24。
本公开实施例中，第一电极层241、电介质层242和第二电极层243可以通过以下任意一种沉积工艺形成：选择性原子层沉积工艺、化学气相沉积工艺、物理气相沉积工艺和旋涂工艺。第一电极层241和第二电极层243的材料可以包括金属或者金属氮化物，例如，钌(Ru)或者氮化钛。电介质层242的材料可以包括高K介质材料，例如可以是氧化镧(La 2O 3)、氧化铝(Al 2O 3)、氧化铪(HfO 2)、氮氧化铪(HfON)、硅酸铪(HfSiOx)或氧化锆(ZrO 2)中的一种或任意组合。在其它实施例中，第一电极层和第二电极层的材料还可以是多晶硅。
本公开实施例中，电容结构24沿Y轴方向延伸，也就是说，电容结构24是水平的，一方面，相较于高纵横比(即高度与宽度或者直径之比)的垂直电容结构，水平电容结构可以减少倾倒或者折断的可能性，从而可以提高电容结构的稳定性；另一方面，多个电容结构在垂直方向上堆叠形成的堆叠结构可以形成三维的半导体结构，进而可以提高半导体结构的集成度，实现微缩。
在一些实施例中，在形成第一电极层241之前，半导体结构的形成方法还包括：在第二子柱1312的表面形成金属硅化物。实施时，可以在第二子柱1312的表面上沉积一层金属材料，例如可以是钴(Co)、钛(Ti)、钽(Ta)、镍(Ni)、钨(W)、铂(Pt)以及钯(Pd)中的任何一种；之后通过快速热退火处理使得金属材料与第二子柱1312相互反应，从而在第二子柱1312的表面形成金属硅化物。由于金属硅化物具有较低的阻值，因此可以降低下电极与第二子柱之间的接触电阻，进而可以降低半导体结构的功耗。
在一些实施例中，在形成电容结构24之后，方法还包括：去除第一保护层21。例如，可以采用干法或者湿法刻蚀工艺来去除第一保护层21。
在一些实施例中，半导体结构的形成方法还包括：在第二电极层243表面形成导电层，导电层填充于相邻的第二电极层243之间。导电层的材料可以是多晶硅，也可以是其它任意一种合适的导电材料，例如，掺杂多晶硅。
本公开实施例中，如图3i所示，在形成位线结构之前，半导体结构的形成方法还包括：在第一区域A、支撑层23和电容结构24的表面形成第二保护层20，第二保护层20用于在形成位线结构22时保护已经形成的梳状栅极结构17、支撑层23和电容结构24不受损伤。第二保护层20的材料可以为低介电常数材料，例如，可以是掺杂二氧化硅、有机聚合物或者多孔材料。
在一些实施例中，请继续参见图3i，位线结构22可以通过以下步骤形成：在第二有源柱132的表面形成依次形成第三半导体层221和位线金属层222。
其中，第三半导体层221的材料可以是金属硅化物，由于金属硅化物具有较低的阻值，因此可以降低位线金属层222与第二有源柱132之间的接触电阻，从而可以进一步降低半导体结构的功耗。位线金属层222的材料可以是任意一种导电性能较好的材料，例如可以为钨、钴、铜、铝、氮化钛、含钛金属层、多晶硅或其任何组合。
在一些实施例中，在形成位线结构22之后，半导体结构的形成方法还包括：去除第二保护层20。
本公开实施例中，形成梳状栅极结构，并采用字线侧接的方法，不仅解决了同一平面上字线的互联对于多层堆叠来说难以实现的问题，还可以通过控制侧接的字线尺寸来减小字线的耦合作用。另外，由于本公开实施例中的电容结构沿第二方向延伸，即本公开实施例中的电容结构呈水平状，相较于高深宽比的垂直电容结构，水平状的电容结构可以减少倾倒或者折断的可能性，从而可以提高电容结构的稳定性，且多个电容结构在第三方向上堆叠形成的堆叠结构可以形成三维的半导体结构，进而可以 提高半导体结构的集成度，实现微缩。
本公开实施例还提供一种半导体结构，图4a～4c为本公开实施例提供的半导体结构的结构示意图，其中，图4a为三维视图。如图4a～4c所示，半导体结构100至少包括：半导体衬底10，半导体衬底10包括沿第二方向(Y轴方向)依次排列的第一区域A和第二区域B；位于半导体衬底10表面的有源结构130；有源结构130沿第一方向(X轴方向)和第三方向(Z轴方向)阵列排布；梳状栅极结构17，位于第一区域A上有源结构的表面，且梳状栅极结构17至少包括在X轴方向间隔排列的第一栅极结构171。
在一些实施例中，请继续参见图4a～4c，半导体结构100还包括：沿Z轴方向延伸的位线结构22和沿Y轴方向延伸的电容结构24；位线结构22与电容结构24均位于第二区域B上，且均与第一栅极结构171连接。
在一些实施例中，请继续参见图4b和4c，电容结构24包括第一电极层241、电介质层242和第二电极层243。位线结构22包括第三半导体层221和位线金属层222。
在一些实施例中，请继续参见图4a～4c，梳状栅极结构17还包括：与位于同一层的第一栅极结构171均连接的第二栅极结构172。
在一些实施例中，请继续参见图4b和4c，有源结构130包括位于第二区域B上、且沿X轴方向排列的第一有源柱131和第二有源柱132、以及位于第一区域A上的沟道柱25；第一有源柱131和第二有源柱132均与沟道柱25连接。第一栅极结构171至少覆盖沟道柱25沿Z轴方向上的第一表面和第二表面；其中，第一栅极结构171包括层叠设置的栅极介质层141和栅极导电层142。
在一些实施例中，沟道柱25在半导体衬底10上的投影为U型。在其它实施例中，沟道柱25在半导体衬底10上的投影还可以为矩形。
在一些实施例中，请继续参见图4b，第一有源柱131包括第一子柱(未示出)和第二子柱1312，电容结构24形成于第二子柱1312上；位线结构22形成于第二有源柱132上；同一有源结构130的第一有源柱131和第二有源柱132之间具有L型凹槽15。沿X轴方向相邻的有源结构130之间具有隔离凹槽16；其中，隔离凹槽16在Y轴方向上的尺寸L3大于L型凹槽15在Y轴方向上的尺寸L4。
在一些实施例中，请继续参见图4b，半导体结构100还包括：支撑层23，支撑层23位于第一子柱的表面，且支撑层23呈填充于第一子柱之间。支撑层23用于支撑沿Z轴方向堆叠的多个电容结构24、多个位线结构22，以及多个梳状栅极结构17。
在一些实施例中，请继续参见图4a，半导体结构100还包括：字线台阶18；字线台阶18沿Z轴方向依次堆叠，且字线台阶中的每一层字线与对应的沿X轴方向排列的梳状栅极结构17中的多个第二栅极结构172连接。
本公开实施例中，第一栅极结构可以是双栅结构，第一栅极结构171在Y轴方向上的尺寸可以为第二栅极结构172在Y轴方向上的尺寸的2～3倍。
本公开实施例中，形成的梳状栅级结构具有很宽的沟道区，从而可以降低短沟道效应，同时，形成的双栅结构可以进一步提高栅极的控制能力，进而可以提高所形成半导体结构的性能。
本公开实施例提供的半导体结构与上述实施例提供的半导体结构的形成方法类似，对于本公开实施例未详尽披露的技术特征，请参照上述实施例进行理解，这里不再赘述。
本公开实施例提供的半导体结构，形成了梳状栅极结构，且字线结构位于梳状栅极结构的外侧，可以实现多层堆叠结构中同一平面上字线的互联；另外，本公开实施例中的电容结构呈水平状、且沿第一方向和第三方向阵列排布，水平状的电容结构可以减少倾倒或者折断的可能性，多个电容结构在第三方向上堆叠形成的堆叠结构可以形成三维的半导体结构，进而可以提高半导体结构的集成度，实现微缩。
图5a和5b为本公开实施例提供的半导体结构的平面结构示意图，如图5a和5b所示，半导体结构100包括：沿X轴方向和Z轴方向阵列排布的第一栅极结构171、位线结构22和电容结构24；其中，位线结构22和电容结构24均与梳状栅极结构17连接。
本公开实施例中，一个第一栅极结构171和一个电容结构24构成一个存储单元；沿X轴方向相邻的存储单元布局相同(如图5a所示)，或者，沿X轴方向相邻的存储单元呈轴对称(如图5b所示)。
在一些实施例中，请继续参见5a和图5b，半导体结构100包括：与同一层的第一栅极结构171均连接的第二栅极结构172，沿X轴方向排列的位于同一层的第一栅极结构171和第二栅极结构172构成梳状栅极结构17。
在一些实施例中，请继续参见5a和图5b，半导体结构100还包括沿X轴方向延伸的字线台阶18，其中，字线台阶18中的每一层字线与对应的沿X轴方向排列的多个第一栅极结构171电连接。
除此之外，本公开实施例还提供一种版图结构，图6a和6b为本公开实施例提供的版图结构的平面布局图，版图结构200包括：沿Y轴方向依次间隔排布的上述半导体结构100。
如图6a和6b所示，半导体结构100包括多个沿X轴方向和Z轴方向阵列排布的存储单元；存储单元至少包括一个第一栅极结构171和一个电容结构24；其中，Y轴方向上相邻两个存储单元呈中心对称；且Y轴方向上相邻两个存储单元的电容结构24在X轴方向上的投影区域至少部分重合。
本公开实施例中，存储单元还包括第二栅极结构172，其中，第一栅极结构171和第二栅极结构172构成梳状栅极结构17。
在一些实施例中，请继续参见图6a和6b，半导体结构100还包括位线结构22和字线台阶18。
在一些实施例中，请继续参见图6a，X轴方向上相邻的两个存储单元布局相同。
在一些实施例中，请继续参见图6b，X轴方向上相邻的两个存储单元布局呈轴对称。
本公开实施例提供的版图结构可以有效利用半导体结构中的空间，实现半导体结构的微缩。
在本公开所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过非目标的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。
本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上所述，仅为本公开的一些实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。
工业实用性
本公开实施例中，由于形成了梳状栅极结构，且梳状栅极结构外侧的栅极金属层可以作为半导体结构的字线，如此，通过梳状栅极结构不仅可以实现多层堆叠结构中同一平面上字线的互联，还可以实现控制字线的尺寸，进而减小字线台阶之间的耦合作用。

Claims (21)

  1. 一种半导体结构的形成方法，所述方法包括：
    提供基底；所述基底包括沿第二方向依次排列的第一区域和第二区域；所述第一区域包括沿第三方向间隔排列的有源层；
    在所述第一区域中形成位于所述有源层表面的初始栅极结构；
    刻蚀所述初始栅极结构，形成沿所述第三方向堆叠的梳状栅极结构；其中，所述梳状栅极结构至少包括在第一方向上间隔排列的第一栅极结构；所述第一方向、所述第二方向和所述第三方向两两相互垂直，且所述第一方向与所述第二方向平行于所述基底表面；
    在所述第二区域形成沿所述第三方向延伸的位线结构和沿所述第二方向延伸的电容结构，所述位线结构与所述电容结构均与所述第一栅极结构连接。
  2. 根据权利要求1所述的方法，其中，所述梳状栅极结构还包括：与位于同一层的所述第一栅极结构均连接的第二栅极结构。
  3. 根据权利要求2所述的方法，其中，所述第一栅极结构在所述基底表面上的投影为U型。
  4. 根据权利要求1至3任一项所述的方法，其中，所述有源层通过以下步骤形成：
    提供半导体衬底；
    在所述半导体衬底的表面形成位于所述第一区域和所述第二区域的叠层结构；所述叠层结构包括交替堆叠的第一半导体层和第二半导体层；
    去除所述第一区域中的第一半导体层，以暴露出所述第一区域的第二半导体层；
    对暴露出的所述第二半导体层进行减薄处理，以形成初始有源层；
    处理所述初始有源层，以形成所述有源层。
  5. 根据权利要求4所述的方法，其中，所述处理所述初始有源层，以形成所述有源层，包括：
    在所述初始有源层的表面依次形成牺牲层和第一隔离层；其中，所述第一隔离层填充于所述牺牲层之间；
    去除在所述第二方向上具有第一长度的初始有源层，形成第一空间；
    去除在所述第二方向上具有第二长度的牺牲层，暴露出部分初始有源层，形成第二空间；其中，所述第二空间包括所述第一空间、且所述第二长度大于所述第一长度，暴露出的所述部分初始有源层构成所述有源层。
  6. 根据权利要求5所述的方法，其中，在所述第一区域中形成位于所述有源层表面的初始栅极结构，包括：
    在所述有源层的表面依次形成栅极介质层和栅极导电层；其中，所述栅极导电层充满所述第二空间。
  7. 根据权利要求6所述的方法，其中，在形成所述梳状栅极结构之后，所述半导体结构的形成方法还包括：
    形成沿所述第三方向依次堆叠的字线台阶；
    其中，所述字线台阶中的每一层字线与对应的沿所述第一方向排列的梳状栅极结构中的第二栅极结构电连接。
  8. 根据权利要求7所述的方法，其中，所述梳状栅极结构通过以下步骤形成：
    同时去除部分所述初始栅极结构和所述第二区域中的部分叠层结构，形成沿所述第一方向交替排列的L型凹槽和隔离凹槽，剩余的所述初始栅极结构构成所述梳状栅极结构；
    其中，所述隔离凹槽在所述第二方向上的尺寸大于所述L型凹槽在所述第二方向上的尺寸；所述隔离凹槽将所述有源层分割为在所述第一方向排列的多个有源结构。
  9. 根据权利要求8所述的方法，其中，位于所述L型凹槽所述第一方向两侧的叠层结构，在所述第二方向具有不同的尺寸；在所述第二区域形成沿所述第三方向延伸的位线结构和沿所述第二方向延伸的电容结构，包括：
    在所述L型凹槽和所述隔离凹槽中填充隔离材料，形成第二隔离层；
    去除位于所述第二区域的第二隔离层和第一半导体层，剩余的所述第二半导体层，形成沿所述第一方向交替排列的第一有源柱和第二有源柱；其中，所述第一有源柱包括第一子柱和第二子柱；
    在所述第二子柱的表面形成所述电容结构；
    在所述第二有源柱的表面形成所述位线结构。
  10. 根据权利要求9所述的方法，其中，在形成所述电容结构之前，所述方法还包括：
    在所述第一子柱的表面形成支撑层；其中，所述支撑层填充于所述第一子柱之间。
  11. 根据权利要求10所述的方法，其中，在所述第二子柱的表面形成所述电容结构，包括：
    在所述第二子柱的表面依次形成第一电极层、电介质层和第二电极层，以形成所述电容结构。
  12. 一种半导体结构，至少包括：
    半导体衬底，所述半导体衬底包括沿第二方向依次排列的第一区域和第二区域；
    位于所述半导体衬底表面的有源结构；所述有源结构沿第一方向和第三方向阵列排布；
    梳状栅极结构，位于所述第一区域上所述有源结构的表面，且所述梳状栅极结构至少包括在第一方向间隔排列的第一栅极结构；
    沿所述第三方向延伸的位线结构；
    沿第二方向延伸的电容结构；所述位线结构与所述电容结构均位于所述第二区域上，且均与所述第一栅极结构连接；所述第一方向、所述第二方向和所述第三方向两两相互垂直，且所述第一方向与所述第二方向平行于所述半导体衬底表面。
  13. 根据权利要求12所述的半导体结构，其中，所述梳状栅极结构还包括：与位于同一层的所述第一栅极结构均连接的第二栅极结构。
  14. 根据权利要求13所述的半导体结构，其中，所述有源结构包括位于所述第二区域上、且沿所述第一方向排列的第一有源柱和第二有源柱、以及位于所述第一区域上的沟道柱；
    所述第一有源柱和所述第二有源柱均与所述沟道柱连接。
  15. 根据权利要求14所述的半导体结构，其中，所述第一栅极结构覆盖所述沟道柱沿所述第三方向上的第一表面和第二表面；
    其中，所述第一栅极结构包括层叠设置的栅极介质层和栅极导电层。
  16. 根据权利要求15所述的半导体结构，其中，所述沟道柱在所述半导体衬底上的投影为U型。
  17. 根据权利要求14至16任一项所述的半导体结构，其中，所述电容结构形成于所述第一有源柱上；所述位线结构形成于所述第二有源柱上；
    同一所述有源结构的所述第一有源柱和所述第二有源柱之间具有L型凹槽。
  18. 根据权利要求17所述的半导体结构，其中，沿所述第一方向相邻的所述有源结构之间具有隔离凹槽；
    其中，所述隔离凹槽在所述第二方向上的尺寸大于所述L型凹槽在所述第二方向上的尺寸。
  19. 根据权利要求13所述的半导体结构，其中，所述半导体结构还包括：字线台阶；
    所述字线台阶沿所述第三方向依次堆叠，且所述字线台阶中的每一层字线与对应的沿所述第一方向排列的梳状栅极结构中的多个第二栅极结构连接。
  20. 一种版图结构，包括：沿第二方向依次间隔排布的、如上述权利要求12至19任一项所述半导体结构；
    所述半导体结构包括沿第一方向和第三方向阵列排布的存储单元；所述存储单元包括一个第一栅极结构和一个电容结构；
    其中，所述第二方向上相邻两个存储单元呈中心对称，且所述第二方向上相邻两个存储单元的电容结构在所述第一方向上的投影区域至少部分重合。
  21. 根据权利要求20所述的版图结构，其中，所述第一方向上相邻的两个存储单元布局相同或者呈轴对称。
PCT/CN2022/105094 2022-06-24 2022-07-12 半导体结构及其形成方法、版图结构 WO2023245755A1 (zh)

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