WO2024026940A1 - 半导体结构的形成方法 - Google Patents

半导体结构的形成方法 Download PDF

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Publication number
WO2024026940A1
WO2024026940A1 PCT/CN2022/113254 CN2022113254W WO2024026940A1 WO 2024026940 A1 WO2024026940 A1 WO 2024026940A1 CN 2022113254 W CN2022113254 W CN 2022113254W WO 2024026940 A1 WO2024026940 A1 WO 2024026940A1
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layer
along
semiconductor
connection layer
virtual connection
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PCT/CN2022/113254
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English (en)
French (fr)
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林超
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长鑫存储技术有限公司
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Priority to US18/150,850 priority Critical patent/US20240047558A1/en
Publication of WO2024026940A1 publication Critical patent/WO2024026940A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a method of forming a semiconductor structure.
  • Three Dimensions Dynamic Random Access Memory can extend in the vertical direction and is the direction of future DRAM technology development.
  • the gate structure of 3D DRAM can choose a gate all around (GAA) structure or a dual gate (dual gate) structure; it is located between the gate structures of two adjacent transistors in the same layer of transistors. Isolation is performed by an electron barrier layer, for example, through air or dielectric, and the gate structures of two adjacent transistors in the same layer of transistors require the same gate metal layer (ie, word line) to be drawn out.
  • GAA gate all around
  • dual gate dual gate
  • the gate structures of two adjacent transistors in the same layer of transistors require the same gate metal layer (ie, word line) to be drawn out.
  • the gate metal layer connecting the gate structures of two adjacent transistors in the same layer of transistors and the gate structure of each transistor on the same layer cannot be formed at the same time, and the preparation process is complicated.
  • embodiments of the present disclosure provide a method for forming a semiconductor structure.
  • An embodiment of the present disclosure provides a method for forming a semiconductor structure.
  • the method includes:
  • a substrate is provided, the substrate includes a first region and a second region located outside the first region, the first region includes stacked structures and isolation trenches alternately arranged along a first direction; the first direction is any direction in the plane where the base is located;
  • a gate structure is formed on the surface of the active dummy connection layer.
  • the stacked structure includes first semiconductor layers and second semiconductor layers alternately stacked along a third direction;
  • the active virtual connection layer includes active layers alternately arranged along the first direction and Virtual connection layer;
  • the active layer and the virtual connection layer are formed by the following steps:
  • the ion implantation of a predetermined depth is performed on both ends of the second semiconductor layer in the stacked structure along the first direction to form the virtual connection layer.
  • Two semiconductor layers constitute the active layer;
  • the preset depth is smaller than the initial size of the second semiconductor layer in the stacked structure; and the third direction intersects a plane on which the substrate is located.
  • the method further includes:
  • the second semiconductor layer after the ion implantation is annealed.
  • the second semiconductor layer includes a first surface and a second surface along the first direction; the virtual connection layer is formed by the following steps:
  • the first virtual connection layer and the second virtual connection layer located in the same isolation trench constitute the virtual connection layer.
  • the isolation trench has a first dimension along the first direction
  • the virtual connection layer has a second size along the first direction
  • the first size is less than or equal to a preset multiple of the second size.
  • the preset multiple is 0.54.
  • the method further includes:
  • the active virtual connection layer is thinned.
  • the substrate further includes a sacrificial structure and a support structure, and the sacrificial structure and the support structure are formed by the following steps:
  • the initial stacked structure includes the first semiconductor layer and the second semiconductor layer alternately stacked along the third direction;
  • Part of the initial stacked structure is removed to form two etching grooves arranged along the second direction and extending along the first direction and the third direction; the second direction and the first direction are located between in the same plane;
  • a support structure and sacrificial structures located on both sides of the support structure along the second direction are formed in the etching groove; wherein the area between the support structures constitutes the first area.
  • the sacrificial structure includes a first sacrificial layer located in the first region and a second sacrificial layer located in the second region.
  • an etch selectivity ratio between the sacrificial structure and the second semiconductor layer is greater than an etch selectivity ratio between the support structure and the second semiconductor layer.
  • the stacked structure and the isolation trench are formed;
  • the stacked structure and the isolation trench are formed by the following steps:
  • a mask layer with a preset pattern is formed on the surface of the initial stacked structure.
  • the preset pattern includes a plurality of sub-patterns arranged along the first direction; the sub-patterns expose the areas located in the first area. Part of the initial stacked structure;
  • the portion of the initial stacked structure exposed by the sub-pattern is removed to form the stacked structure and the isolation trench alternately arranged along the first direction.
  • the method further includes:
  • the second sacrificial layer located in the projection area of the first semiconductor layer along the second direction in the first area is removed to form a plurality of first openings.
  • the method further includes:
  • the first semiconductor layer is removed.
  • the gate structure is formed by the following steps:
  • a gate dielectric layer and a gate conductive layer located on the surface of the gate dielectric layer are sequentially formed on the third surface and the fourth surface of the active dummy connection layer along the third direction.
  • the method further includes:
  • the gap between the gate conductive layers forms a second isolation structure.
  • the first semiconductor layer includes a silicon germanium layer; the second semiconductor layer includes a silicon layer.
  • a dummy connection layer is formed that connects the two active layers in the first direction.
  • the dummy connection layer can facilitate the subsequent formation of a gate metal layer that connects the gate structure of the same layer. It simplifies the process of the gate structure and reduces the preparation cost of the semiconductor structure; in addition, the virtual connection layer can also be used as an electron blocking layer to isolate adjacent gate structures in the same layer, reducing the generation of leakage current, thereby improving Yield of prepared semiconductor structures.
  • Figure 1 is a schematic flowchart of a semiconductor structure forming method provided by an embodiment of the present disclosure
  • FIGS. 2a to 2p are schematic structural diagrams of the semiconductor structure formation process provided by embodiments of the present disclosure.
  • 3a and 3b are schematic structural diagrams of semiconductor structures provided by embodiments of the present disclosure.
  • the three directions may include the X-axis, Y-axis, and Z-axis directions.
  • the substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side; ignoring the flatness of the top and bottom surfaces, the direction of intersection (eg, perpendicular) with the top and bottom surfaces of the substrate is defined as third direction.
  • the direction of intersection eg, perpendicular
  • the top surface and the bottom surface of the base that is, the plane where the base is located
  • define two directions that intersect each other for example, are perpendicular to each other).
  • the direction in which the support structure extends can be defined as the first direction
  • the direction in which the support structure is arranged can be defined as The second direction
  • the planar direction of the substrate can be determined based on the first direction and the second direction.
  • the first direction, the second direction and the third direction may be perpendicular to each other. In other embodiments, the first direction, the second direction and the third direction may not be perpendicular to each other.
  • the first direction is defined as the X-axis direction
  • the second direction is defined as the Y-axis direction
  • the third direction is defined as the Z-axis direction.
  • FIG. 1 is a schematic flowchart of a method for forming a semiconductor structure provided by an embodiment of the disclosure. As shown in Figure 1, the method for forming a semiconductor structure includes the following steps:
  • Step S101 Provide a substrate.
  • the substrate includes a first region and a second region located outside the first region.
  • the first region includes stacked structures and isolation trenches alternately arranged along a first direction.
  • the substrate at least includes a semiconductor substrate; the semiconductor substrate may be a silicon substrate, and the semiconductor substrate may also include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC). ), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or other semiconductor alloys, such as silicon germanium (SiGe) , gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), and/or indium gallium arsenide phosphide ( GaInAsP) or a combination thereof.
  • germanium germanium
  • GaAs gallium arsenide
  • the first region and the second region can be used to form different functional structures respectively.
  • the first region can be used to form a gate structure
  • the second region can be used to form other semiconductor structures, such as word structures. Line structure, capacitive structure or bit line structure.
  • the stacked structure includes first semiconductor layers and second semiconductor layers alternately stacked from bottom to top along the third direction.
  • the material of the first semiconductor layer may be germanium (Ge), silicon germanium (SiGe), or silicon carbide; it may also be silicon-on-insulator (SOI) or germanium-on-insulator (Germanium-on-Insulator, GOI).
  • the material of the second semiconductor layer may be a silicon layer, or may include other semiconductor elements, such as germanium, or semiconductor compounds, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide or antimonide.
  • Indium, or other semiconductor alloys such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, indium gallium arsenide, and/or indium gallium arsenide phosphide, or combinations thereof.
  • the materials of the first semiconductor layer and the second semiconductor layer are different because part of the first semiconductor layer needs to be removed later and the second semiconductor layer remains. Therefore, the first semiconductor layer has a larger etching selectivity ratio relative to the second semiconductor layer.
  • the etching selectivity ratio of the first semiconductor layer relative to the second semiconductor layer can be 5 to 15, so that during the etching process The first semiconductor layer is easier to be removed by etching than the second semiconductor layer.
  • Step S102 Perform ion implantation on the sidewalls of the stacked structure along the first direction to form an active dummy connection layer extending along the first direction and partially located in the isolation trench.
  • the active virtual connection layer includes active layers and virtual connection layers alternately arranged along the first direction.
  • the active layer and the virtual connection layer can be formed through the following steps: using plasma doping (PLAD) technology to perform ion implantation at a preset depth on both ends of the second semiconductor layer in the stacked structure along the first direction, A virtual connection layer is formed, and the second semiconductor layer that has not been ion implanted constitutes the active layer; wherein the preset depth is smaller than the initial size of the second semiconductor layer in the stacked structure, and the material used for ion implantation can be oxygen atoms or Other materials containing oxygen atoms.
  • PAD plasma doping
  • an annealing process is performed, so that the injected ions react with the second semiconductor layer with the preset depth to form A virtual connection layer extending along the first direction.
  • the second semiconductor layer includes a first surface and a second surface along the first direction; the second semiconductor layer is ion implanted and annealed along the first surface to form a first surface extending along the first direction.
  • Virtual connection layer ; perform ion implantation and annealing on the second semiconductor layer along the second surface to form a second virtual connection layer extending along the first direction, the first virtual connection layer and the second virtual connection located in the same trench
  • the layers constitute the virtual connection layer.
  • the first virtual connection layer and the second virtual connection layer are formed at the same time. That is to say, the ion implantation process along the first surface and the second surface is performed simultaneously and subsequently. The annealing process is also carried out simultaneously.
  • consuming the second semiconductor layer of the first preset size will generate a first virtual connection layer of a second preset size or a second virtual connection layer of the second preset size.
  • the second preset size is larger than the first virtual connection layer.
  • a preset size Therefore, the size of the isolation trench along the first direction in the embodiment of the present disclosure has a maximum value. Otherwise, the first virtual connection layer and the second virtual connection located in the same isolation trench will not be connected. Unable to form virtual connection layer.
  • the second semiconductor layer when the material of the second semiconductor layer is silicon, the second semiconductor layer is doped with oxygen atoms.
  • the doping depth is 1 nanometer (nm)
  • 1 nanometer (nm) of silicon is consumed, which will Silicon oxide is formed to about 2.17nm
  • the maximum size of the isolation groove along the first direction is 2.34nm.
  • the size of the isolation groove along the first direction exceeds 2.34nm, the first virtual connection layer and the second virtual connection layer cannot be connected together. Therefore, the first size of the isolation trench along the first direction is less than or equal to a preset multiple of the second size of the dummy connection layer along the first direction, where the preset multiple may be 0.54 times.
  • the first semiconductor layer when the stack is plasma doped, the first semiconductor layer is also doped. However, due to the different materials of the first semiconductor layer and the second semiconductor layer, the annealing process , the first semiconductor layer does not react with the doped ions, therefore, the first semiconductor layer remains unchanged.
  • the virtual connection layer in the embodiment of the present disclosure can, on the one hand, connect two active layers arranged along the first direction to facilitate the subsequent formation of a gate metal layer connecting the same gate structure; on the other hand, it can serve as an electronic
  • the barrier layer is used to isolate two adjacent gate structures along the first direction to reduce the generation of leakage current, thereby improving the yield of the prepared semiconductor structure.
  • Step S103 Form a gate structure on the surface of the active dummy connection layer.
  • the gate structure includes: a gate dielectric layer, and a gate conductive layer located on the surface of the gate dielectric layer.
  • the material of the gate dielectric layer can be silicon oxide or other suitable materials; the material of the gate conductive layer can be any material with good conductivity, such as titanium (Ti), titanium nitride Any one of (TiN), tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), and copper (Cu).
  • the gate dielectric layer and the gate conductive layer can be formed by any suitable deposition process, such as chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD) process, Atomic Layer Deposition (ALD) process, spin coating process, coating process or furnace tube process.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • ALD Atomic Layer Deposition
  • a stacked structure formed by stacking multiple gate structures in a third direction can form a three-dimensional semiconductor structure, which can improve the integration of the semiconductor structure and achieve shrinkage.
  • a dummy connection layer is formed that connects the two active layers in the first direction.
  • the dummy connection layer can facilitate the subsequent formation of a gate metal layer that connects the gate structure of the same layer. It simplifies the process of the gate structure and reduces the preparation cost of the semiconductor structure; in addition, the virtual connection layer can also be used as an electron blocking layer to isolate adjacent gate structures in the same layer, reducing the generation of leakage current, thereby improving Yield of prepared semiconductor structures.
  • FIGS. 2a to 2p are schematic structural diagrams of the semiconductor structure formation process provided by the embodiment of the present disclosure.
  • the formation process of the semiconductor structure provided by the embodiment of the present disclosure will be described in detail below with reference to FIGS. 2a to 2p.
  • Figures 2a, 2c, 2e, and 2i are three-dimensional views
  • Figures 2b, 2d, 2f ⁇ 2h, 2j ⁇ 2p are along a-a', b-b', c-c' and d- during the formation process of the semiconductor structure. Sectional view of d'.
  • step S101 is to provide a substrate.
  • the substrate includes a first region and a second region located outside the first region.
  • the first region includes a stacked structure and isolation trenches alternately arranged along a first direction. .
  • the substrate includes a sacrificial structure and a support structure.
  • the sacrificial structure and the support structure may be formed by: forming an initial stacked structure on the semiconductor substrate, wherein the initial stacked structure includes alternately stacked stacked layers along a third direction. The first semiconductor layer and the second semiconductor layer; remove part of the initial stacked structure to form two etching grooves arranged along the second direction and extending along the first direction and the third direction; forming a support in the etching groove structure and sacrificial structures located on both sides of the supporting structure along the second direction; wherein the area located between the supporting structures constitutes the first area.
  • an initial stacked structure 11a is formed on the surface of the semiconductor substrate 10; wherein the initial stacked structure 11a includes first semiconductor layers 111 and second semiconductor layers alternately stacked from bottom to top along the Z-axis direction. Layer 112.
  • the material of the first semiconductor layer 111 may be germanium, silicon germanium, or silicon carbide; it may also be silicon on insulator or germanium on insulator.
  • the second semiconductor layer 112 may be a silicon layer, or may include other semiconductor elements, such as germanium, or semiconductor compounds, such as silicon carbide, gallium arsenide, gallium indium phosphide, indium arsenide or indium antimonide, Or include other semiconductor alloys, such as: silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, indium gallium phosphide, and/or indium gallium arsenide phosphide or combinations thereof.
  • the number of layers of the first semiconductor layer 111 and the second semiconductor layer 112 in the initial stacked structure 11a can be set according to the required storage density. More, the semiconductor structure is more integrated.
  • the first semiconductor layer 111 and the second semiconductor layer 112 can be formed by any of the following deposition processes: epitaxial process, chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process, spin coating process, coating process or thin film process; for example, the first semiconductor layer 111 and the second semiconductor layer 112 can be sequentially formed on the semiconductor substrate 10 through an epitaxial process.
  • a dielectric layer 12 can also be formed on the surface of the initial stacked structure 11a (as shown in Figures 2c and 2d); the dielectric layer 12 is at least used for subsequent alignment of the stacked layers.
  • the second semiconductor layer 112 on the top surface of the stacked structure 11 is protected from damage.
  • the dielectric layer 12 can be formed by any suitable deposition process, such as chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process, spin coating process, coating process or furnace tube process.
  • part of the initial stacked structure 11a is removed to form two etching grooves 15 arranged along the Y-axis direction and extending along the X-axis direction; the etching grooves 15 include Two intersecting sub-grooves extending in the direction of the Cut to the sub-groove extending along the Z-axis direction.
  • part of the initial stacked structure 11a can be removed through a selective etching process.
  • etching grooves 15 are also formed in the dielectric layer 12 (as shown in Figures 2e to 2g).
  • sacrificial material is deposited on the two sidewalls of the etching groove 15 along the Y-axis direction to form a sacrificial structure 16.
  • the sacrificial structure 16 includes a first sacrificial layer 161 and a second sacrificial layer 162; next, in The gap between the first sacrificial layer 161 and the second sacrificial layer 162 is filled with support material to form the support structure 17 .
  • the area between the support structures 17 along the Y-axis direction constitutes the first area A, and other areas located outside the first area A constitute the second area B.
  • the first sacrificial layer 161 is located in the second area B, and the second sacrificial layer 162 is located in the first area A.
  • both the sacrificial structure 16 and the supporting structure 17 can be formed by any suitable deposition process.
  • the sacrificial material can be a Spin On Hard Mask (SOH) material, a low dielectric constant (Low K) material, or other suitable materials.
  • the support material can be silicon nitride or silicon carbonitride.
  • the support structure 17 can be used to support a subsequently formed gate structure or other functional structure, thereby improving the stability of the semiconductor structure.
  • the substrate is divided into a first region and a second region through a support structure. Since the size of the first region along two directions determines the size of the channel in the gate structure, the position of the support structure can be adjusted, By adjusting the size of the channel in the gate structure, the control capability of the gate structure can be adjusted and the performance of the formed semiconductor structure can be improved.
  • the etching selectivity ratio between the sacrificial structure 16 and the second semiconductor layer 112 is greater than the etching selectivity ratio between the supporting structure 17 and the second semiconductor layer 112 .
  • the first sacrificial layer 161 in the sacrificial structure 16 can be used to define the positions of the source and drain electrodes, and the second sacrificial layer 162 in the sacrificial structure 16 is used to facilitate subsequent removal of the second semiconductor in the stacked structure. Therefore, during implementation, the second sacrificial layer 162 and the first sacrificial layer 161 need to be removed to implement the subsequent process.
  • the etching selectivity ratio between the sacrificial structure 16 and the second semiconductor layer 112 it is necessary to set the etching selectivity ratio between the sacrificial structure 16 and the second semiconductor layer 112 to be greater than the etching selectivity ratio between the supporting structure 17 and the second semiconductor layer 112 , that is, to set the second sacrificial layer 162 and the second semiconductor layer
  • the etching selectivity ratio between the layers 112 is greater than the etching selectivity ratio between the support structure 17 and the second semiconductor layer 112, and the etching selectivity ratio between the first sacrificial layer 161 and the second semiconductor layer 112 is set to be greater than the support structure. 17 and the second semiconductor layer 112, so that the second sacrificial layer 162 and the first sacrificial layer 161 are easier to be removed by etching relative to the support structure 17 during the etching process.
  • the stacked structure and the isolation trench are formed; the stacked structure and the isolation trench can be formed by the following steps: forming a preset pattern on the surface of the initial stacked structure Mask layer, the preset pattern includes a plurality of sub-patterns arranged along the first direction, and the sub-patterns expose part of the initial stacked structure located in the first area; through the mask layer, remove part of the initial stacked structure exposed by the sub-patterns , forming stacked structures and isolation trenches alternately arranged along the first direction.
  • the dielectric layer 12 is located on the surface of the initial stacked structure 11a.
  • a mask layer 14 with a preset pattern is formed on the surfaces of the dielectric layer 12, the support structure 17 and the sacrificial structure 16; preset The pattern exposes a portion of the dielectric layer 12 located in the first area A.
  • the mask layer 14 with the preset pattern includes a plurality of sub-preset patterns F arranged along the first direction.
  • the material used for the mask layer 14 with the preset pattern may be one or more of silicon oxide, silicon nitride, silicon carbide, and silicon oxynitride.
  • the dielectric layer 12 and the initial stacked structure 11a exposed by the preset pattern are sequentially removed to form the stacked structure 11 and the isolation trench 13.
  • the exposed dielectric layer 12 and the initial stacked structure 11a can be etched and removed through high aspect ratio etching (HAR) technology to form the stacked structure 11 and the isolation trench 13.
  • HAR high aspect ratio etching
  • the second semiconductor layer 112 in the formed stacked structure 11 includes a first surface 18a and a second surface 18b along the X-axis direction.
  • step S102 to perform ion implantation on the sidewalls of the stacked structure along the first direction to form an active dummy connection layer extending along the first direction and partially located in the isolation trench.
  • ion implantation of a predetermined depth is performed on both ends of the second semiconductor layer 112 in the stacked structure 11 along the X-axis direction, that is, the first surface 18a and the second surface are implanted.
  • 18b performs ion implantation at a predetermined depth to form a dummy connection layer 192, and the second semiconductor layer 112 that has not been ion implanted constitutes the active layer 191.
  • PLAD technology is used to perform ion implantation on the second semiconductor layer 112 of a predetermined depth along the first surface 18a, and is annealed to form a first virtual connection layer extending into the isolation trench 13;
  • the second semiconductor layer 112 with a preset depth is ion implanted and annealed to form a second virtual connection layer extending into the isolation trench 13; that is, ion implantation is performed simultaneously along the first surface 18a and the second surface 18b, and simultaneously
  • An annealing process is performed to form a first dummy connection layer and a second dummy connection layer extending into the isolation trench 13 .
  • the first virtual connection layer and the second virtual connection layer located in the same isolation trench 13 constitute the virtual connection layer 192 .
  • the isolation trench 13 has a first dimension d1 along the first direction; the virtual connection layer 192 has a second dimension d2 along the first direction; the first dimension d1 is less than or equal to the second dimension d2 of a preset multiple,
  • the preset multiple may be 0.54.
  • the method of forming the semiconductor structure further includes: removing the second sacrificial layer in the first region located in the projection region of the first semiconductor layer along the second direction.
  • the layer 162 forms a plurality of first openings 23 arranged along the X-axis direction, the Y-axis direction and the Z-axis direction.
  • the first opening 23 is formed to facilitate subsequent removal of the first semiconductor layer 111 .
  • the method of forming the semiconductor structure further includes: removing the first semiconductor layer 111 .
  • a selective etching process may be used to remove the first semiconductor layer 111 located in the first region A through the first opening 23 .
  • the forming method of the semiconductor structure further includes: removing the first opening 23 in the projection area along the X-axis direction.
  • the second sacrificial layer 162 and the remaining second sacrificial layer 162 also form a part of the virtual connection layer 192.
  • the active virtual connection layer 19 has a third surface 20a and a fourth surface 20b along the Z-axis direction.
  • the method of forming the semiconductor structure further includes: thinning the active virtual connection layer 19 .
  • the thinning process can make the formed active dummy connection layer cylindrical, that is, make the cross section of the active dummy connection layer along the third direction closer to a circle. In this way, the leakage of the semiconductor structure can be reduced.
  • the thinning process can enlarge the gap between adjacent active layers along the third direction, making it easier to subsequently form the gate structure, thereby reducing the process complexity of the gate structure and reducing the manufacturing cost of the semiconductor structure.
  • step S103 is performed to form a gate structure on the surface of the active dummy connection layer.
  • the gate structure is formed by the following steps: sequentially forming a gate dielectric layer and a gate conductive layer located on the surface of the gate dielectric layer on the third surface and the fourth surface of the active dummy connection layer along the third direction. .
  • a gate dielectric material and a gate conductive material are sequentially deposited on the third surface 20a and the fourth surface 20b of the active dummy connection layer 19 along the Z-axis direction to form a gate dielectric layer 211 and a gate conductive material.
  • the gate structure 21 includes a gate dielectric layer 211 and a gate conductive layer 212 located on the surface of the gate dielectric layer 211 .
  • the gate dielectric material can be silicon oxide or other suitable materials; the gate conductive material can be any material with good conductivity, such as titanium, titanium nitride, tungsten, cobalt, platinum, Palladium, ruthenium or copper.
  • the gate dielectric layer 211 and the gate conductive layer 212 can be formed by any suitable deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, and an atomic layer deposition process.
  • the gate structure 21 may be a double gate structure.
  • the gate conductive layer 212 located on the surface of the dummy connection layer 192 can be used as a word line to connect two adjacent gate structures on the same layer.
  • a gate conductive layer is formed on the surface of the active dummy connection layer.
  • the gate conductive layer located on the surface of the dummy connection layer can be used as a word line to realize the connection between two adjacent gate structures on the same layer. connect.
  • the method of forming the semiconductor structure further includes: forming a second isolation structure 22 in the gap between the gate conductive layers 212 .
  • the second isolation material is filled in the gaps of the gate conductive layer 212 to form the second isolation structure 22 .
  • the second isolation material may be the same as the first isolation material, or may be different.
  • the second isolation structure 22 is used to isolate two adjacent gate structures 21 along the third direction, reducing the generation of leakage current, thereby improving the yield of the semiconductor structure.
  • the method of forming the semiconductor structure further includes: removing the first sacrificial layer 161 , forming a second opening (not shown), and conducting the active layer 191 through the second opening. Ion implantation to form source and drain electrodes.
  • a dummy connection layer is formed that connects the two active layers along the first direction, and the dummy connection layer facilitates the subsequent formation of a gate metal layer that connects the gate structure of the same layer; in addition, , the virtual connection layer can serve as an electron blocking layer to isolate two adjacent gate structures along the first direction, reduce the generation of leakage current, and thus improve the yield of the prepared semiconductor structure.
  • the formed semiconductor structure has a horizontal gate structure, and the gate structures are stacked along the third direction. The stacked structure formed by stacking multiple gate structures in the third direction can form a three-dimensional semiconductor structure, and then It can improve the integration level of semiconductor structures and achieve shrinkage.
  • the embodiment of the present disclosure also provides a semiconductor structure.
  • Figures 3a and 3b are schematic structural diagrams of the semiconductor structure provided by the embodiment of the present disclosure.
  • the semiconductor structure 100 at least includes: a semiconductor substrate 10.
  • the semiconductor substrate 10 includes a first region A and a second region B located outside the first region A; an active dummy connection layer 19 extending along the X-axis direction, and the active dummy connection layer 19 is located in the first region A, And arranged at intervals along the Z-axis direction; the gate structures 21 are located on the surface of the active dummy connection layer 19 .
  • the active virtual connection layer 19 includes an active layer 191 and a virtual connection layer 192 alternately arranged along the X-axis direction.
  • the virtual connection layer 192 is located on the active layer 191 along the X-axis. direction projection area.
  • the semiconductor structure 100 further includes: support structures 17.
  • the support structures 17 are arranged at intervals along the Y-axis direction and extend along the X-axis direction; wherein, two supporting structures 17 arranged along the Y-axis direction The area between the two supporting structures 17 constitutes the first area A.
  • the semiconductor structure 100 further includes: first sacrificial layers 161.
  • the first sacrificial layers 161 are arranged at intervals along the Y-axis direction and extend along the X-axis direction and the Z-axis direction; wherein, The first sacrificial layer 161 is located in the second region B and is located on one side of the support structure 17 along the Y-axis direction.
  • the semiconductor structure 100 further includes a second sacrificial layer 162 , and the second sacrificial layer 162 forms a part of the active virtual connection layer 19 .
  • the gate structure 21 covers the third surface 20a and the fourth surface 20b of the active dummy connection layer 19 along the Z-axis direction; the gate structure 21 includes a gate dielectric layer 211 and the gate conductive layer 212 located on the surface of the gate dielectric layer 211.
  • the gate conductive layer 212 located on the surface of the dummy connection layer 192 can serve as a word line.
  • the semiconductor structure 100 further includes: a second isolation structure 22 located between the gate conductive layers 212 .
  • the semiconductor structure provided by the embodiments of the present disclosure is similar to the formation method of the semiconductor structure in the above-mentioned embodiments.
  • the semiconductor structure provided by the embodiment of the present disclosure at least includes a dummy connection layer.
  • the dummy connection layer can connect two active layers arranged along the first direction to facilitate the subsequent formation of a gate metal layer connecting the gate structure of the same layer; on the other hand, the dummy connection layer can connect two active layers arranged along the first direction.
  • the virtual connection layer can serve as an electron blocking layer to isolate two adjacent gate structures along the first direction, reducing the generation of leakage current, thereby improving the yield of the prepared semiconductor structure; in addition, embodiments of the present disclosure
  • the gate structure is horizontal, and the stacked structure formed by stacking multiple horizontal gate structures in the third direction can form a three-dimensional semiconductor structure, which can improve the integration of the semiconductor structure and achieve shrinkage.
  • the disclosed devices and methods can be implemented in a non-target manner.
  • the device embodiments described above are only illustrative.
  • the division of units is only a logical function division.
  • the components shown or discussed are coupled to each other, or directly coupled.
  • a dummy connection layer is formed that connects the two active layers in the first direction.
  • the dummy connection layer can facilitate the subsequent formation of a gate metal layer that connects the gate structure of the same layer. It simplifies the process of the gate structure and reduces the preparation cost of the semiconductor structure; in addition, the virtual connection layer can also be used as an electron blocking layer to isolate adjacent gate structures in the same layer, reducing the generation of leakage current, thereby improving Yield of prepared semiconductor structures.

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Abstract

本公开实施例提供一种半导体结构的形成方法，所述方法包括：提供基底，所述基底包括第一区域和位于所述第一区域之外的第二区域，所述第一区域包括沿第一方向交替排列的叠层结构和隔离沟槽；所述第一方向为所述基底所在平面内任意的一个方向；对所述叠层结构沿所述第一方向的侧壁进行离子注入，形成沿所述第一方向延伸、且部分位于所述隔离沟槽中的有源虚拟连接层；在所述有源虚拟连接层的表面形成栅极结构。

Description

半导体结构的形成方法
相关申请的交叉引用
本公开基于申请号为202210933222.3、申请日为2022年08月04日、发明名称为“半导体结构的形成方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，涉及但不限于一种半导体结构的形成方法。
背景技术
三维动态随机存储器(Three Dimensions Dynamic Random Access Memory，3D DRAM)能够在垂直方向上延伸，是未来DRAM技术发展的方向。相关技术中，3D DRAM的栅极结构可以选择全环栅(Gate All Around，GAA)结构或者是双栅(dual gate)结构；位于同一层的晶体管中相邻两个晶体管的栅极结构之间通过电子阻挡层(barrier layer)进行隔离，例如，通过空气或介质进行隔离，且位于同一层的晶体管中相邻两个晶体管的栅极结构需要相同的栅极金属层(即字线)引出。然而，相关技术中的3D DRAM，连接同一层晶体管中相邻两个晶体管的栅极结构的栅极金属层与位于同一层的每个晶体管的栅极结构不能同时形成，制备工艺复杂。
发明内容
有鉴于此，本公开实施例提供一种半导体结构的形成方法。
本公开实施例提供一种半导体结构的形成方法，所述方法包括：
提供基底，所述基底包括第一区域和位于所述第一区域之外的第二区域，所述第一区域包括沿第一方向交替排列的叠层结构和隔离沟槽；所述第一方向为所述基底所在平面内任意的一个方向；
对所述叠层结构沿所述第一方向的侧壁进行离子注入，形成沿所述第一方向延伸、且部分位于所述隔离沟槽中的有源虚拟连接层；
在所述有源虚拟连接层的表面形成栅极结构。
在一些实施例中，所述叠层结构包括沿第三方向交替堆叠的第一半导体层和第二半导体层；所述有源虚拟连接层包括沿所述第一方向交替排列的有源层和虚拟连接层；所述有源层和所述虚拟连接层通过以下步骤形成：
对所述叠层结构中的所述第二半导体层沿所述第一方向的两端进行预设深度的所述离子注入，形成所述虚拟连接层，未进行所述离子注入的所述第二半导体层构成所述有源层；
其中，所述预设深度小于所述叠层结构中的所述第二半导体层的初始尺寸；所述第三方向与所述基底所在的平面相交。
在一些实施例中，对所述叠层结构中的所述第二半导体层沿所述第一方向的两端进行预设深度的所述离子注入之后，所述方法还包括：
对所述离子注入后的所述第二半导体层进行退火处理。
在一些实施例中，所述第二半导体层包括沿所述第一方向上的第一表面和第二表面；所述虚拟连接层通过以下步骤形成：
沿所述第一表面对所述第二半导体层进行所述离子注入和所述退火处理，形成沿所述第一方向延伸的第一虚拟连接层；
沿所述第二表面对所述第二半导体层进行所述离子注入和所述退火处理，形成沿所述第一方向延伸的第二虚拟连接层；
位于同一所述隔离沟槽中的所述第一虚拟连接层和所述第二虚拟连接层构成所述虚拟连接层。
在一些实施例中，所述隔离沟槽沿所述第一方向具有第一尺寸；
所述虚拟连接层沿所述第一方向具有第二尺寸；
所述第一尺寸小于或者等于预设倍数的所述第二尺寸。
在一些实施例中，所述预设倍数为0.54。
在一些实施例中，在形成所述有源虚拟连接层之后，且在形成所述栅极结构之前，所述方法还包括：
对所述有源虚拟连接层进行减薄处理。
在一些实施例中，所述基底还包括牺牲结构和支撑结构，所述牺牲结构和所述支撑结构通过以下步骤形成：
在半导体衬底上形成初始叠层结构，其中，所述初始叠层结构包括沿所述第三方向交替堆叠的所述第一半导体层和所述第二半导体层；
去除部分所述初始叠层结构，形成沿第二方向排列、且沿所述第一方向和所述第三方向延伸的两个刻蚀凹槽；所述第二方向与所述第一方向位于同一平面内；
在所述刻蚀凹槽中形成支撑结构和位于所述支撑结构沿所述第二方向两侧的牺牲结构；其中，位于所述支撑结构之间的区域构成所述第一区域。
在一些实施例中，所述牺牲结构包括位于所述第一区域的第一牺牲层和位于所述第二区域的第二牺牲层。
在一些实施例中，所述牺牲结构与所述第二半导体层之间的刻蚀选择比大于所述支撑结构与所述第二半导体层之间的刻蚀选择比。
在一些实施例中，在形成所述牺牲结构和所述支撑结构之后，形成所述叠层结构和所述隔离沟槽；
所述叠层结构和所述隔离沟槽通过以下步骤形成：
在所述初始叠层结构的表面形成具有预设图案的掩膜层，所述预设图案包括沿所述第一方向排列的多个子图案；所述子图案暴露出位于所述第一区域的部分所述初始叠层结构；
通过所述掩膜层，去除所述子图案暴露出的部分所述初始叠层结构，形成沿所述第一方向交替排列的所述叠层结构和所述隔离沟槽。
在一些实施例中，在形成所述有源虚拟连接层之后，所述方法还包括：
去除所述第一区域中位于所述第一半导体层沿所述第二方向投影区域内的所述第二牺牲层，形成多个第一开口。
在一些实施例中，去除所述第二牺牲层之后，所述方法还包括：
去除所述第一半导体层。
在一些实施例中，所述栅极结构通过以下步骤形成：
在所述有源虚拟连接层沿所述第三方向上的第三表面和第四表面依次形成栅极介质层和位于所述栅极介质层表面的栅极导电层。
在一些实施例中，形成所述栅极结构之后，所述方法还包括：
在所述栅极导电层之间的空隙形成第二隔离结构。
在一些实施例中，所述第一半导体层包括锗化硅层；所述第二半导体层包括硅层。
本公开实施例中，在形成半导体结构的过程中，形成了连接第一方向上两个有源层的虚拟连接层，虚拟连接层可以方便后续形成连接同一层栅极结构的栅极金属层，简化了栅极结构的工艺过程，降低了半导体结构的制备成本；另外，虚拟连接层还可以作为电子阻挡层，来隔离位于同一层中相邻的栅极结构，减少漏电流的产生，从而提高所制备的半导体结构的良率。
附图说明
在附图(其不一定是按比例绘制的)中，相似的附图标记可在不同的视图中描述相似的部件。具有不同字母后缀的相似附图标记可表示相似部件的不同示例。附图以示例而非限制的方式大体示出了本文中所讨论的各个实施例。
图1为本公开实施例提供的半导体结构形成方法的流程示意图；
图2a～2p为本公开实施例提供的半导体结构形成过程中的结构示意图；
图3a和3b为本公开实施例提供的半导体结构的结构示意图；
附图标记说明如下：
10—半导体衬底；11—叠层结构；11a—初始叠层结构；111—第一半导体层；112—第二半导体层；12—介质层；13—隔离沟槽；14—具有预设图案的掩膜层；15—刻蚀凹槽；16—牺牲结构；161—第一牺牲层；162—第 二牺牲层；17—支撑结构；18a—第一表面；18b—第二表面；19—有源虚拟连接层；191—有源层；192—虚拟连接层；20a—第三表面；20b—第四表面；21—栅极结构；211—栅极介质层；212—栅极导电层；22—第二隔离结构；23—第一开口；100—半导体结构；A—第一区域；B—第二区域；F—子预设图案。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列 项目的任何及所有组合。
在介绍本公开实施例之前，先定义一下以下实施例可能用到的描述立体结构的三个方向，以笛卡尔坐标系为例，三个方向可以包括X轴、Y轴和Z轴方向。基底可以包括处于正面的顶表面以及处于与正面相对的背面的底表面；在忽略顶表面和底表面的平整度的情况下，定义与基底顶表面和底表面的相交(例如垂直)的方向为第三方向。在基底的顶表面和底表面(即基底所在的平面)方向上，定义两彼此相交(例如彼此垂直)的方向，例如可以定义支撑结构延伸的方向为第一方向，定义支撑结构排列的方向为第二方向，基于第一方向和第二方向可以确定基底的平面方向。本公开实施例中，第一方向、第二方向和第三方向可以两两相互垂直，在其它实施例中，第一方向、第二方向和第三方向也可以不垂直。本公开实施例中，定义第一方向为X轴方向，定义第二方向为Y轴方向，定义第三方向为Z轴方向。
本公开实施例提供一种半导体结构的形成方法，图1为本公开实施例提供的半导体结构形成方法的流程示意图，如图1所示，半导体结构的形成方法包括以下步骤：
步骤S101，提供基底，基底包括第一区域和位于第一区域之外的第二区域，第一区域包括沿第一方向交替排列的叠层结构和隔离沟槽。
本公开实施例中，基底至少包括半导体衬底；半导体衬底可以是硅衬底，半导体衬底也可以包括其它半导体元素，例如：锗(Ge)，或包括半导体化合物，例如：碳化硅(SiC)、砷化镓(GaAs)、磷化镓(GaP)、磷化铟(InP)、砷化铟(InAs)或锑化铟(InSb)，或包括其它半导体合金，例如：硅锗(SiGe)、磷化砷镓(GaAsP)、砷化铟铝(AlInAs)、砷化镓铝(AlGaAs)、砷化铟镓(GaInAs)、磷化铟镓(GaInP)、和/或磷砷化铟镓(GaInAsP)或其组合。
本公开实施例中，第一区域和第二区域可以分别用于形成不同的功能结构，例如，第一区域可以用于形成栅极结构，第二区域可以用于形成其他半导体结构，例如，字线结构、电容结构或位线结构。
本公开实施例中，叠层结构包括沿第三方向自下而上交替堆叠的第一半导体层和第二半导体层。第一半导体层的材料可以是锗(Ge)、或锗化硅(SiGe)、碳化硅；也可以是绝缘体上硅(Silicon-On-Insulator，SOI)或者绝缘体上锗(Germanium-on-Insulator，GOI)。第二半导体层的材料可以为硅层，也可以包括其它半导体元素，例如：锗，或包括半导体化合物，例如：碳化硅、砷化镓、磷化镓、磷化铟、砷化铟或锑化铟，或包括其它半导体合金，例如：硅锗、磷化砷镓、砷化铟铝、砷化镓铝、砷化铟镓、磷化铟镓、和/或磷砷化铟镓或其组合。
本公开实施例中，第一半导体层和第二半导体层的材料不同，因为后续需要去除部分第一半导体层，保留第二半导体层。因此，第一半导体层 相对于第二半导体层具有较大的刻蚀选择比，例如，第一半导体层相对于第二半导体层的刻蚀选择比可以为5～15，从而在刻蚀过程中第一半导体层相对于第二半导体层更容易被刻蚀去除。
步骤S102，对叠层结构沿第一方向的侧壁进行离子注入，形成沿第一方向延伸、且部分位于隔离沟槽中的有源虚拟连接层。
在一些实施例中，有源虚拟连接层包括沿第一方向交替排列的有源层和虚拟连接层。有源层和虚拟连接层可以通过以下步骤形成：采用等离子体掺杂(Plasma Doping，PLAD)技术对叠层结构中的第二半导体层沿第一方向的两端进行预设深度的离子注入，形成虚拟连接层，未进行离子注入的第二半导体层构成有源层；其中，预设深度小于叠层结构中的第二半导体层的初始尺寸，进行离子注入所采用的材料可以是氧原子或者其它含氧原子的材料。
本公开实施例中，在对叠层结构沿第一方向的两端进行预设深度的离子注入之后，会进行退火处理，使得注入的离子与具有预设深度的第二半导体层发生反应，形成沿第一方向延伸的虚拟连接层。
在一些实施例中，第二半导体层包括沿第一方向上的第一表面和第二表面；沿第一表面对第二半导体层进行离子注入和退火处理，形成沿第一方向延伸的第一虚拟连接层；沿第二表面对第二半导体层进行离子注入和退火处理，形成沿第一方向延伸的第二虚拟连接层，位于同一离沟槽中的第一虚拟连接层和第二虚拟连接层构成虚拟连接层。
需要说明的是，本公开实施例中，第一虚拟连接层和第二虚拟连接层是同时形成的，也就是说，沿第一表面和第二表面的离子注入过程是同时进行的、后续的退火过程也是同时进行的。
本公开实施例中，消耗第一预设尺寸的第二半导体层会生成第二预设尺寸的第一虚拟连接层或第二预设尺寸的第二虚拟连接层，第二预设尺寸大于第一预设尺寸，因此，本公开实施例中的隔离沟槽沿第一方向的尺寸有一个最大值，否则位于同一隔离沟槽中的第一虚拟连接层和第二虚拟连接会连接不上而无法形成虚拟连接层。
在一些实施例中，当第二半导体层的材料为硅，采用氧原子对第二半导体层进行掺杂，当掺杂深度为1纳米(nm)时，消耗1纳米(nm)的硅，会形成约2.17nm的氧化硅，那么，隔离凹槽沿第一方向的最大尺寸为2.34纳米，当隔离凹槽沿第一方向的尺寸超过2.34nm时，第一虚拟连接层和第二虚拟连接层则不能连接在一起。因此，隔离沟槽沿第一方向的第一尺寸小于或者等于虚拟连接层沿第一方向上第二尺寸的预设倍数，其中，预设倍数可以是0.54倍。
需要说明的是，本公开实施例中，在对叠层进行等离子掺杂时，对第一半导体层也进行了掺杂，但是，由于第一半导体层和第二半导体层的材料不同，退火过程中，第一半导体层不与掺杂的离子发生反应，因此，第 一半导体层仍然保持不变。
本公开实施例中的虚拟连接层，一方面，可以实现连接沿第一方向排列的两个有源层，方便后续形成连接同一层栅极结构的栅极金属层；另一方面，可以作为电子阻挡层，来隔离沿第一方向的相邻两个栅极结构，减少漏电流的产生，从而提高所制备的半导体结构的良率。
步骤S103，在有源虚拟连接层的表面形成栅极结构。
本公开实施例中，栅极结构包括：栅极介质层，以及位于栅极介质层表面的栅极导电层。
本公开实施例中，栅极介质层的材料可以是氧化硅或者其它适合的材料；栅极导电层的材料可以是任意一种导电性能较好的材料，例如为钛(Ti)、氮化钛(TiN)、氮化钨(WN)、钨(W)、钴(Co)、铂(Pt)、钯(Pd)、钌(Ru)、铜(Cu)中的任意一种。
本公开实施例中，栅极介质层和栅极导电层可以通过任意一种合适的沉积工艺形成，例如，化学气相沉积工艺(Chemical Vapor Deposition，CVD)、物理气相沉积(Physical Vapor Deposition，PVD)工艺、原子层沉积(Atomic Layer Deposition，ALD)工艺、旋涂工艺、涂敷工艺或者炉管工艺。
本公开实施例中，多个栅极结构在第三方向上堆叠形成的堆叠结构可以形成三维的半导体结构，可以提高半导体结构的集成度，实现微缩。
本公开实施例中，在形成半导体结构的过程中，形成了连接第一方向上两个有源层的虚拟连接层，虚拟连接层可以方便后续形成连接同一层栅极结构的栅极金属层，简化了栅极结构的工艺过程，降低了半导体结构的制备成本；另外，虚拟连接层还可以作为电子阻挡层，来隔离位于同一层中相邻的栅极结构，减少漏电流的产生，从而提高所制备的半导体结构的良率。
图2a～2p为本公开实施例提供的半导体结构形成过程中的结构示意图，下面结合图2a～2p对本公开实施例提供的半导体结构的形成过程进行详细的说明。其中，图2a、2c、2e、2i为三维视图，图2b、2d、2f～2h、2j～2p为半导体结构形成过程中沿a-a'、b-b'、c-c'和d-d'的剖视图。
首先，可以参考图2a～2k，步骤S101，提供基底，基底包括第一区域和位于第一区域之外的第二区域，第一区域包括沿第一方向交替排列的叠层结构和隔离沟槽。
在一些实施例中，基底包括牺牲结构和支撑结构，牺牲结构和支撑结构可以通过以下步骤形成：在半导体衬底上形成初始叠层结构，其中，初始叠层结构包括沿第三方向交替堆叠的第一半导体层和第二半导体层；去除部分初始叠层结构，形成沿第二方向排列、且沿第一方向和第三方向延伸的两个刻蚀凹槽；在刻蚀凹槽中形成支撑结构和位于支撑结构沿第二方向两侧的牺牲结构；其中，位于支撑结构之间的区域构成第一区域。
如图2a和2b所示，在半导体衬底10的表面形成初始叠层结构11a； 其中，初始叠层结构11a包括沿Z轴方向自下而上交替堆叠的第一半导体层111和第二半导体层112。
本公开实施例中，第一半导体层111的材料可以是锗、或锗化硅、碳化硅；也可以是绝缘体上硅或者绝缘体上锗。第二半导体层112可以为硅层，也可以包括其它半导体元素，例如：锗，或包括半导体化合物，例如：碳化硅、砷化镓、磷化镓磷化铟、砷化铟或锑化铟，或包括其它半导体合金，例如：硅锗、磷化砷镓、砷化铟铝、砷化镓铝、砷化铟镓、磷化铟镓、和/或磷砷化铟镓或其组合。
本公开实施例中，初始叠层结构11a中第一半导体层111和第二半导体层112的层数可以根据需要的存储密度来设置，第一半导体层111和第二半导体层112的层数越多，半导体结构的集成度更高。
本公开实施例中，第一半导体层111和第二半导体层112可以通过以下任一沉积工艺形成：外延工艺、化学气相沉积工艺、物理气相沉积工艺、原子层沉积工艺、旋涂工艺、涂敷工艺或薄膜工艺等；例如可以通过外延工艺在半导体衬底10上依次形成第一半导体层111和第二半导体层112。
在一些实施例中，在形成初始叠层结构11a之后，还可以在初始叠层结构11a的表面形成介质层12(如图2c和2d所示)；介质层12至少用于在后续对叠层结构11进行处理时，保护叠层结构11顶表面的第二半导体层112不受损伤。
本公开实施例，介质层12可以通过任意一种合适的沉积工艺形成，例如，化学气相沉积工艺、物理气相沉积工艺、原子层沉积工艺、旋涂工艺、涂敷工艺或者炉管工艺。
接下来，如图2e～2g所示，去除部分初始叠层结构11a，形成沿Y轴方向排列、且沿X轴方向延伸的两个刻蚀凹槽15；刻蚀凹槽15包括沿X轴方向延伸和Z轴方向延伸的两个交叉的子凹槽，其中，图2e中的b-b'仅剖至沿X轴方向延伸的子凹槽上，而图2e中的c-c'仅剖至沿Z轴方向延伸的子凹槽上。本公开实施例中，可以通过选择性刻蚀工艺去除部分初始叠层结构11a。
需要说明的是，在介质层12中也形成了刻蚀凹槽15(如图2e～2g所示)。
如图2h所示，在刻蚀凹槽15沿Y轴方向的两个侧壁沉积牺牲材料，形成牺牲结构16，牺牲结构16包括第一牺牲层161和第二牺牲层162；接下来，在第一牺牲层161和第二牺牲层162之间的间隙填充支撑材料，形成支撑结构17。本公开实施例中，位于支撑结构17沿Y轴方向之间的区域构成第一区域A，位于第一区域A之外的其它区域构成第二区域B。其中，第一牺牲层161位于第二区域B中，第二牺牲层162位于第一区域A中。
本公开实施例中，牺牲结构16和支撑结构17均可以通过任意一种合适的沉积工艺形成。牺牲材料可以是旋涂硬掩膜(Spin On Hard Mask，SOH) 材料、低介电常数(Low K)材料或者其他适合的材料。支撑材料可以是氮化硅或者碳氮化硅。
本公开实施例中，支撑结构17可以用于支撑后续形成的栅极结构或其它功能结构，从而提高半导体结构的稳定性。
本公开实施例中，通过支撑结构将基底划分第一区域和第二区域，由于第一区域沿二方向的尺寸决定了栅极结构中沟道的尺寸，因此，可以通过调节支撑结构的位置，实现调节栅极结构中沟道的尺寸，从而可以实现调节栅极结构的控制能力，提高所形成半导体结构的性能。
在一些实施例中，牺牲结构16与第二半导体层112的刻蚀选择比大于支撑结构17与第二半导体层112的刻蚀选择比。
本公开实施例中，牺牲结构16中的第一牺牲层161可以用于定义源极和漏极的位置，牺牲结构16中第二牺牲层162用于方便后续去除叠层结构中的第二半导体层，因此，在实施时，需要去除第二牺牲层162和第一牺牲层161，来实现后续的工艺过程。如此，则需要设置牺牲结构16与第二半导体层112之间的刻蚀选择比大于支撑结构17与第二半导体层112之间的刻蚀选择比，即设置第二牺牲层162与第二半导体层112之间的刻蚀选择比大于支撑结构17与第二半导体层112之间的刻蚀选择比，且设置第一牺牲层161与第二半导体层112之间的刻蚀选择比大于支撑结构17与第二半导体层112之间的刻蚀选择比，从而在刻蚀的过程中使得第二牺牲层162和第一牺牲层161相对于支撑结构17更容易被刻蚀去除。
在一些实施例中，在形成牺牲结构和支撑结构之后，形成叠层结构和隔离沟槽；叠层结构和隔离沟槽可以通过以下步骤形成：在初始叠层结构的表面形成具有预设图案的掩膜层，预设图案包括沿第一方向排列的多个子图案，且子图案暴露出位于第一区域的部分初始叠层结构；通过掩膜层，去除子图案暴露出的部分初始叠层结构，形成沿第一方向交替排列的叠层结构和隔离沟槽。
本公开实施例中，请参考图2i，介质层12位于初始叠层结构11a的表面，在介质层12、支撑结构17和牺牲结构16的表面形成具有预设图案的掩膜层14；预设图案暴露出部分位于第一区域A中的介质层12。其中，具有预设图案的掩膜层14包括多个沿第一方向排列的子预设图案F。
本公开实施例中，具有预设图案的掩膜层14采用的材料可以是氧化硅、氮化硅、碳化硅、氮氧化硅中的一种或几种。
如图2j和2k所示，通过具有预设图案的掩膜层14，依次去除预设图案暴露出的介质层12和初始叠层结构11a，形成叠层结构11和隔离沟槽13。
本公开实施例中，可以通过高纵横比刻蚀(High Aspect Ratio，HAR)技术刻蚀去除暴露出的介质层12和初始叠层结构11a，形成叠层结构11和隔离沟槽13。
本公开实施例中，形成的叠层结构11中的第二半导体层112包括沿X 轴方向上的第一表面18a和第二表面18b。
接下来，可以参考图2l～2n，执行步骤S102，对叠层结构沿第一方向的侧壁进行离子注入，形成沿第一方向延伸、且部分位于隔离沟槽中的有源虚拟连接层。
本公开实施例中，如图2l所示，对叠层结构11中的第二半导体层112沿X轴方向的两端分别进行预设深度的离子注入，即对第一表面18a和第二表面18b进行预设深度的离子注入，形成虚拟连接层192，未进行离子注入的第二半导体层112构成有源层191。
实施时，采用PLAD技术沿第一表面18a对预设深度的第二半导体层112进行离子注入，并进行退火处理，形成延伸进入隔离沟槽13的第一虚拟连接层；沿第二表面18b对预设深度的第二半导体层112进行离子注入，并进行退火处理，形成延伸进入隔离沟槽13的第二虚拟连接层；即同时沿第一表面18a和第二表面18b进行离子注入，并同时进行退火处理，形成延伸进入隔离沟槽13的第一虚拟连接层和第二虚拟连接层。其中，位于同一隔离沟槽13中的第一虚拟连接层和第二虚拟连接层构成虚拟连接层192。
在一些实施例中，隔离沟槽13沿第一方向具有第一尺寸d1；虚拟连接层192沿第一方向具有第二尺寸d2；第一尺寸d1小于或者等于预设倍数的第二尺寸d2，例如，预设倍数例如可以是0.54。
在一些实施例中，如图2m所示，在形成有源虚拟连接层之后，半导体结构的形成方法还包括：去除第一区域中位于第一半导体层沿第二方向投影区域内的第二牺牲层162，形成沿X轴方向、Y轴方向和Z轴方向排列的多个第一开口23。
本公开实施例中，形成的第一开口23用于方便后续去除第一半导体层111。
在一些实施例中，如图2n所示，去除第二牺牲层之后，半导体结构的形成方法还包括：去除第一半导体层111。
本公开实施例中，可以采用选择性刻蚀工艺，通过第一开口23，去除位于第一区域A中的第一半导体层111。
本公开实施例中，请继续参考图2n，在去除位于第一区域A中的第一半导体层111之后，半导体结构的形成方法还包括：去除第一开口23沿X轴方向投影区域内的第二牺牲层162，剩余的第二牺牲层162也构成了虚拟连接层192的一部分。
本公开实施例中，请继续参考图2n，有源虚拟连接层19沿Z轴方向具有第三表面20a和第四表面20b。
在其他实施例中，半导体结构的形成方法还包括：对有源虚拟连接层19进行减薄处理。减薄处理可以使得形成的有源虚拟连接层变得圆柱化，即使得有源虚拟连接层沿第三方向的截面更接近圆形，如此，可以减少半导体结构的漏电。另外，减薄处理可以使得沿第三方向相邻的有源层之间 的空隙变大，更便于后续形成栅极结构，从而可以降低栅极结构的工艺复杂度，降低半导体结构的制造成本。
最后，可以参考图2o和2p，执行步骤S103，在有源虚拟连接层的表面形成栅极结构。
在一些实施例中，栅极结构通过以下步骤形成：在有源虚拟连接层沿第三方向上的第三表面和第四表面依次形成栅极介质层和位于栅极介质层表面的栅极导电层。
结合图2n、2o和2p，在有源虚拟连接层19沿Z轴方向上的第三表面20a和第四表面20b依次沉积栅极介质材料和栅极导电材料，形成栅极介质层211和栅极导电层212，栅极结构21包括栅极介质层211和和位于栅极介质层211表面的栅极导电层212。
本公开实施例中，栅极介质材料可以是氧化硅或者其它适合的材料；栅极导电材料可以是任意一种导电性能较好的材料，例如为钛、氮化钛、钨、钴、铂、钯、钌或铜。
本公开实施例中，栅极介质层211和栅极导电层212可以通过任意一种合适的沉积工艺形成，例如，化学气相沉积工艺、物理气相沉积工艺、原子层沉积工艺。
本公开实施例中，栅极结构21可以是双栅结构。位于虚拟连接层192表面的栅极导电层212可以作为字线，来连接同一层相邻的两个栅极结构。
本公开实施例中，在有源虚拟连接层的表面形成了栅极导电层，位于虚拟连接层表面的栅极导电层可以作为字线，实现同一层相邻的两个栅极结构之间的连接。
在一些实施例中，请继续参考图2o和2p，在形成栅极结构21之后，半导体结构的形成方法还包括：在栅极导电层212之间的空隙形成第二隔离结构22。
本公开实施例中，在栅极导电层212的空隙中填充第二隔离材料，形成第二隔离结构22。其中，第二隔离的材料可以与第一隔离材料相同，也可以不同。
本公开实施例中，第二隔离结构22用于隔离沿第三方向的相邻两个栅极结构21，减少漏电流的产生，从而提高了半导体结构的良率。
本公开实施例中，在形成第二隔离结构22之后，半导体结构的形成方法还包括：去除第一牺牲层161，形成第二开口(未示出)，通过第二开口对有源层191进行离子注入，形成源极和漏极。
本公开实施例中，在形成半导体结构的过程中，形成沿第一方向连接两个有源层的虚拟连接层，通过虚拟连接层方便后续形成连接同一层栅极结构的栅极金属层；另外，虚拟连接层可以作为电子阻挡层，以隔离沿第一方向的相邻两个栅极结构，减少漏电流的产生，从而提高所制备的半导体结构的良率。本公开实施例中，形成的半导体结构具有水平状的栅极结 构，并且栅极结构沿第三方向堆叠，多个栅极结构在第三方向上堆叠形成的堆叠结构可以形成三维的半导体结构，进而可以提高半导体结构的集成度，实现微缩。
除此之外，本公开实施例还提供一种半导体结构，图3a和3b为本公开实施例提供的半导体结构的结构示意图，如图3a和3b所示，半导体结构100至少包括：半导体衬底10，半导体衬底10包括第一区域A和位于第一区域A之外的第二区域B；沿X轴方向延伸的有源虚拟连接层19，有源虚拟连接层19位于第一区域A、且沿Z轴方向间隔排布；位于有源虚拟连接层19表面的栅极结构21。
在一些实施例中，请继续参考图3a和3b，有源虚拟连接层19包括沿X轴方向交替排列的有源层191和虚拟连接层192，虚拟连接层192位于有源层191沿X轴方向投影区域中。
在一些实施例中，请继续参考图3b，半导体结构100还包括：支撑结构17，支撑结构17沿Y轴方向间隔排布、且沿X轴方向延伸；其中，沿Y轴方向排布的两个支撑结构17之间的区域构成第一区域A。
在一些实施例中，请继续参考图3b，半导体结构100还包括：第一牺牲层161，第一牺牲层161沿Y轴方向间隔排布、且沿X轴向和Z轴方向延伸；其中，第一牺牲层161位于第二区域B，且位于支撑结构17沿Y轴方向一侧。
在一些实施例中，请继续参考图3b，半导体结构100还包括第二牺牲层162，第二牺牲层162构成了有源虚拟连接层19的一部分。
在一些实施例中，请继续参考图3a和3b，栅极结构21覆盖有源虚拟连接层19沿Z轴方向上的第三表面20a和第四表面20b；栅极结构21包括栅极介质层211和位于栅极介质层211表面的栅极导电层212。其中，位于虚拟连接层192表面栅极导电层212可以作为字线。
在一些实施例中，请继续参考图3a和3b，半导体结构100还包括：位于栅极导电层212之间的第二隔离结构22。
本公开实施例提供的半导体结构与上述实施例中的半导体结构的形成方法类似，对于本公开实施例未详尽披露的技术特征，请参照上述实施例进行理解，这里，不再赘述。
本公开实施例提供的半导体结构至少包括虚拟连接层，一方面，虚拟连接层可以连接沿第一方向排列的两个有源层，方便后续形成连接同一层栅极结构的栅极金属层；另一方面，虚拟连接层可以作为电子阻挡层，来隔离沿第一方向的相邻两个栅极结构，减少漏电流的产生，从而提高所制备的半导体结构的良率；另外，本公开实施例中的栅极结构呈水平状，多个水平状栅极结构在第三方向上堆叠形成的堆叠结构可以形成三维的半导体结构，可以提高半导体结构的集成度，实现微缩。
在本公开所提供的几个实施例中，应该理解到，所揭露的设备和方法， 可以通过非目标的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合。
本公开所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上，仅为本公开的一些实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例中，在形成半导体结构的过程中，形成了连接第一方向上两个有源层的虚拟连接层，虚拟连接层可以方便后续形成连接同一层栅极结构的栅极金属层，简化了栅极结构的工艺过程，降低了半导体结构的制备成本；另外，虚拟连接层还可以作为电子阻挡层，来隔离位于同一层中相邻的栅极结构，减少漏电流的产生，从而提高所制备的半导体结构的良率。

Claims (16)

  1. 一种半导体结构的形成方法，所述方法包括：
    提供基底，所述基底包括第一区域和位于所述第一区域之外的第二区域，所述第一区域包括沿第一方向交替排列的叠层结构和隔离沟槽；所述第一方向为所述基底所在平面内任意的一个方向；
    对所述叠层结构沿所述第一方向的侧壁进行离子注入，形成沿所述第一方向延伸、且部分位于所述隔离沟槽中的有源虚拟连接层；
    在所述有源虚拟连接层的表面形成栅极结构。
  2. 根据权利要求1所述的方法，其中，所述叠层结构包括沿第三方向交替堆叠的第一半导体层和第二半导体层；所述有源虚拟连接层包括沿所述第一方向交替排列的有源层和虚拟连接层；所述有源层和所述虚拟连接层通过以下步骤形成：
    对所述叠层结构中的所述第二半导体层沿所述第一方向的两端进行预设深度的所述离子注入，形成所述虚拟连接层，未进行所述离子注入的所述第二半导体层构成所述有源层；
    其中，所述预设深度小于所述叠层结构中的所述第二半导体层的初始尺寸；所述第三方向与所述基底所在的平面相交。
  3. 根据权利要求2所述的方法，其中，对所述叠层结构中的所述第二半导体层沿所述第一方向的两端进行预设深度的所述离子注入之后，所述方法还包括：
    对所述离子注入后的所述第二半导体层进行退火处理。
  4. 根据权利要求3所述的方法，其中，所述第二半导体层包括沿所述第一方向上的第一表面和第二表面；所述虚拟连接层通过以下步骤形成：
    沿所述第一表面对所述第二半导体层进行所述离子注入和所述退火处理，形成沿所述第一方向延伸的第一虚拟连接层；
    沿所述第二表面对所述第二半导体层进行所述离子注入和所述退火处理，形成沿所述第一方向延伸的第二虚拟连接层；
    位于同一所述隔离沟槽中的所述第一虚拟连接层和所述第二虚拟连接层构成所述虚拟连接层。
  5. 根据权利要求4所述的方法，其中，所述隔离沟槽沿所述第一方向具有第一尺寸；
    所述虚拟连接层沿所述第一方向具有第二尺寸；
    所述第一尺寸小于或者等于预设倍数的所述第二尺寸。
  6. 根据权利要求5所述的方法，其中，所述预设倍数为0.54。
  7. 根据权利要求2至6任一项所述的方法，其中，在形成所述有源虚拟连接层之后，且在形成所述栅极结构之前，所述方法还包括：
    对所述有源虚拟连接层进行减薄处理。
  8. 根据权利要求7所述的方法，其中，所述基底还包括牺牲结构和支撑结构，所述牺牲结构和所述支撑结构通过以下步骤形成：
    在半导体衬底上形成初始叠层结构，其中，所述初始叠层结构包括沿所述第三方向交替堆叠的所述第一半导体层和所述第二半导体层；
    去除部分所述初始叠层结构，形成沿第二方向排列、且沿所述第一方向和所述第三方向延伸的两个刻蚀凹槽；所述第二方向与所述第一方向位于同一平面内；
    在所述刻蚀凹槽中形成支撑结构和位于所述支撑结构沿所述第二方向两侧的牺牲结构；其中，位于所述支撑结构之间的区域构成所述第一区域。
  9. 根据权利要求8所述的方法，其中，所述牺牲结构包括位于所述第一区域的第一牺牲层和位于所述第二区域的第二牺牲层。
  10. 根据权利要求9所述的方法，其中，所述牺牲结构与所述第二半导体层之间的刻蚀选择比大于所述支撑结构与所述第二半导体层之间的刻蚀选择比。
  11. 根据权利要求10所述的方法，其中，在形成所述牺牲结构和所述支撑结构之后，形成所述叠层结构和所述隔离沟槽；
    所述叠层结构和所述隔离沟槽通过以下步骤形成：
    在所述初始叠层结构的表面形成具有预设图案的掩膜层，所述预设图案包括沿所述第一方向排列的多个子图案；所述子图案暴露出位于所述第一区域的部分所述初始叠层结构；
    通过所述掩膜层，去除所述子图案暴露出的部分所述初始叠层结构，形成沿所述第一方向交替排列的所述叠层结构和所述隔离沟槽。
  12. 根据权利要求9所述的方法，其中，在形成所述有源虚拟连接层之后，所述方法还包括：
    去除所述第一区域中位于所述第一半导体层沿所述第二方向投影区域内的所述第二牺牲层，形成多个第一开口。
  13. 根据权利要求12所述的方法，其中，去除所述第二牺牲层之后，所述方法还包括：
    去除所述第一半导体层。
  14. 根据权利要求13所述的方法，其中，所述栅极结构通过以下步骤形成：
    在所述有源虚拟连接层沿所述第三方向上的第三表面和第四表面依次形成栅极介质层和位于所述栅极介质层表面的栅极导电层。
  15. 根据权利要求14所述的方法，其中，形成所述栅极结构之后，所述方法还包括：
    在所述栅极导电层之间的空隙形成第二隔离结构。
  16. 根据权利要求8至15任一项所述的方法，其中，所述第一半导体 层包括锗化硅层；所述第二半导体层包括硅层。
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