WO2023225955A1 - 一种像素电路、其驱动方法及显示装置 - Google Patents

一种像素电路、其驱动方法及显示装置 Download PDF

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Publication number
WO2023225955A1
WO2023225955A1 PCT/CN2022/095311 CN2022095311W WO2023225955A1 WO 2023225955 A1 WO2023225955 A1 WO 2023225955A1 CN 2022095311 W CN2022095311 W CN 2022095311W WO 2023225955 A1 WO2023225955 A1 WO 2023225955A1
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Prior art keywords
transistor
light
stage
terminal
reset
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PCT/CN2022/095311
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English (en)
French (fr)
Inventor
张竞文
郭永林
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to PCT/CN2022/095311 priority Critical patent/WO2023225955A1/zh
Priority to CN202280001450.5A priority patent/CN117461075A/zh
Publication of WO2023225955A1 publication Critical patent/WO2023225955A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel circuit, a driving method thereof and a display device.
  • AMOLED Active Matrix Organic Light Emitting Diode
  • people have higher and higher requirements for its image quality.
  • the manufacturing process leads to problems with the uniformity of the threshold voltage of the Driver Thin Film Transistor (DTFT).
  • DTFT hysteresis leads to afterimages, abnormal brightness of the first frame, and when switching between different driving frequencies. Problems such as low grayscale flickering need to be solved urgently.
  • the present disclosure provides a pixel circuit, its driving method and a display device, which are used to improve the display effect of the display device.
  • an embodiment of the present disclosure provides a pixel circuit, which includes: a first reset transistor, a compensation transistor, a driving transistor, a data writing transistor, a first light emitting control transistor, a second light emitting control transistor, a light emitting device, and The first capacitor;
  • the first reset transistor is coupled between the first pole of the light-emitting device and the first initialization signal terminal, and the gate is coupled to the first light-emitting control terminal;
  • the second pole of the light-emitting device is coupled to the first power terminal
  • the compensation transistor is coupled between the gate electrode and the first electrode of the driving transistor, and the gate electrode is coupled to the first scan control terminal;
  • the data writing transistor is coupled between the second pole of the driving transistor and the data signal terminal, and the gate is coupled to the second scan control terminal;
  • the first light-emitting control transistor is coupled between the second power terminal and the second electrode of the driving transistor, and the gate is coupled with the first light-emitting control terminal;
  • the second light-emitting control transistor is coupled between the first electrode of the driving transistor and the first electrode of the light-emitting device, and the gate electrode is coupled to the second light-emitting control terminal;
  • the first capacitor is coupled between the second power terminal and the gate of the driving transistor
  • the first light-emitting control transistor and the second light-emitting control transistor are of the same type and are opposite to the first reset transistor; the first light-emitting control terminal is used to receive the first light-emitting control signal, so The second light-emitting control terminal is used to receive a second light-emitting control signal.
  • the first light-emitting control signal and the second light-emitting control signal are provided by different-level output terminals of the same light-emitting driving unit, and the second light-emitting control signal earlier than the first lighting control signal.
  • a second reset transistor is further included, the second reset transistor is coupled between the first pole and the second initialization signal terminal of the driving transistor, and the gate is coupled to the initialization control terminal. catch.
  • the second reset transistor and the data writing transistor are of the same type; the second scan control terminal is used to receive the first scan control signal, and the initialization control terminal is used to receive A second scan control signal.
  • the first scan control signal and the second scan control signal are provided by different stage output terminals of the same gate driving unit, and the second scan control signal is earlier than the first scan control signal. Signal.
  • the first initialization signal terminal and the second initialization signal terminal are the same signal terminal or different signal terminals.
  • the method further includes: a second capacitor coupled between the second power terminal and the second pole of the driving transistor.
  • the capacitance value of the second capacitor is smaller than the capacitance value of the first capacitor.
  • the first luminescence control transistor, the second luminescence control transistor, the driving transistor and the data writing transistor are all P-type transistors; the compensation transistor and the third luminescence control transistor are P-type transistors.
  • a reset transistor is an N-type transistor.
  • the active layer of the compensation transistor and the first reset transistor is a metal oxide semiconductor material
  • the active layer of the second light emission control transistor is made of low-temperature polysilicon material.
  • embodiments of the present disclosure also provide a display device, which includes a pixel circuit as described in any one of the above.
  • embodiments of the present disclosure also provide a driving method for a pixel circuit as described in any one of the above, which includes:
  • the current display frame of the display device is divided into one writing frame and N holding frames, where N is an integer greater than 1; wherein the writing frame includes The first stage, the second stage, the third stage, the fourth stage and the fifth stage are set in sequence;
  • the first light emitting control transistor, the driving transistor and the compensation transistor are controlled to be turned on, and the first electrode, gate electrode and third electrode of the driving transistor are reset through the second power supply terminal.
  • the first reset transistor, the compensation transistor and the second light emitting control transistor are controlled to be turned on, and the potentials of the first pole, gate electrode and second pole of the driving transistor are reset, And resetting the potential of the first pole of the light-emitting device through the first initialization signal terminal;
  • the first reset transistor, the compensation transistor, the driving transistor and the data writing transistor are controlled to be turned on, the potential of the first pole of the light-emitting device is reset, and the The data signal provided by the data signal terminal is loaded to the second electrode of the driving transistor, and the threshold voltage of the driving transistor and the data signal are written into the gate of the driving transistor through the compensation transistor, and stored to the first capacitor;
  • the first reset transistor and the second light emitting control transistor are controlled to be turned on, and the potential of the first pole of the driving transistor is reset through the first initialization signal terminal.
  • the hold frame includes a sixth stage and a seventh stage set in sequence
  • the second light-emitting control transistor and the first light-emitting control transistor are controlled to be turned off successively, and the first reset transistor is turned on, and the light-emitting device is reset through the first initialization signal terminal.
  • the first reset transistor and the second light emission control transistor are controlled to be turned on, and the potential of the second pole of the driving transistor is reset through the first power supply terminal.
  • the first stage and the second stage are regarded as a repeating unit, and the writing frame includes M repeating units arranged in sequence, where M is a positive integer greater than 1.
  • the M repeating units include two repeating units including a first repeating unit and a second repeating unit, and the occupation of the second luminescence control signal in the first repeating unit The duration is greater than the occupation duration in the second repeating unit.
  • the pixel circuit further includes a second reset transistor
  • the writing frame further includes an eighth stage located between the third stage and the fourth stage
  • the method further include:
  • the first lighting control terminal, the second lighting control terminal, the first scanning control terminal and the second scanning control are maintained.
  • the signal loaded on the terminal is in a stable voltage state, and the potential of the gate of the driving transistor is kept the same as the control signal provided by the second initialization signal terminal coupled to the second reset transistor.
  • the pixel circuit further includes a second capacitor coupled between the second power terminal and the second pole of the driving transistor, and the method further includes:
  • the data signal is loaded to the second pole of the driving transistor and stored in the second capacitor;
  • the second electrode of the driving transistor is continuously charged through the second capacitor.
  • Figure 1 is a schematic structural diagram of one of the pixel circuits used in related technologies
  • Figure 2 is one of the timing diagrams used in the pixel circuit shown in Figure 1;
  • Figure 3 is a schematic structural diagram of one of the pixel circuits used in related technologies
  • Figure 4 is one of the timing diagrams used in the pixel circuit shown in Figure 3;
  • Figure 5 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • Figure 6 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • Figure 7 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • Figure 8 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • Figure 9 is one of the timing diagrams of the writing frame corresponding to the pixel circuit shown in Figure 5;
  • Figure 10 is one of the timing diagrams of the hold frame corresponding to the pixel circuit shown in Figure 5;
  • Figure 11 is one of the timing diagrams of the write frame corresponding to the pixel circuit shown in Figure 5;
  • Figure 12 is one of the timing diagrams of the write frame corresponding to the pixel circuit shown in Figure 5;
  • Figure 13 is one of the timing diagrams of the write frame corresponding to the pixel circuit shown in Figure 6;
  • Figure 14 is a method flow chart of a driving method for a pixel circuit provided by an embodiment of the present disclosure
  • Figure 15 is a method flow chart of a driving method for a pixel circuit provided by an embodiment of the present disclosure
  • FIG. 16 is a method flow chart of a driving method for a pixel circuit provided by an embodiment of the present disclosure.
  • the pixel circuit shown in Figure 1 and the timing diagram shown in Figure 2 are often used, where M3 represents the DTFT, L represents the light-emitting device, n01, n02 and n03 respectively represent each transistor and each pole of the DTFT.
  • M1 and M2 are N-type transistors
  • M3, M4, M5, M6 and M7 are P-type transistors
  • M1 and M2 are metal oxide transistors
  • M3 to M7 are low-temperature polysilicon transistors. Compensate the DTFT threshold voltage to ensure the uniformity of the DTFT threshold voltage and improve the problem of low-frequency flicker.
  • the n01 node is reset; in the 02 stage, the data signal is written to compensate the threshold voltage of the DTFT; in the 03 stage, the anode of the light-emitting device L (corresponding to the figure n04 node in 1) is reset; in the 04 stage, the light-emitting device L emits light.
  • the pixel circuit shown in Figure 1 reference can be made to the specific implementation in related technologies, and will not be described in detail here.
  • NR and NG are driven by the same set of gate drive circuits (Gate on Array, GOA), PG and PR are driven by the same set of GOA, and V1 and V2 can use the same signal or different signals.
  • the pixel circuit requires a total of three sets of GOA and one or two reset signals.
  • the threshold voltage of the DTFT can be compensated.
  • M1 and M2 are metal oxide transistors, the anode can be reset during the hold frame, thereby avoiding low-frequency flickering.
  • the pixel circuit shown in FIG. 3 can be used in combination with the timing diagram shown in FIG. 4 to improve the above problems.
  • the pixel circuit includes eight transistors including m1, m2, m3, m4, m5, m6, m7 and m8, m3 represents DTFT, n1, n2 and n3 respectively represent each transistor coupled to each pole of DTFT.
  • Nodes, m1 and m2 are metal oxide transistors, and m3 to m8 are low-temperature polysilicon transistors.
  • n1, n2, and n3 are reset to a high level and emit light; in the 2 stage, n1 is reset to a low level, and DTFT has a larger Vgs; in the 3 stage, n1, n2, and n3 are reset to a low level; in the 4 stage , DATA writing, DTFT threshold voltage compensation; in the 5 stage, the anode (corresponding to the n4 node in Figure 3) is reset at a low level, and n3 is reset at a high level; in the 6 stage, the pulse modulation technology of the light-emitting control signal em (Pulse Width Modulation, PWM) adjustment; in the 7 stage, the anode reset (Anode Reset), n3 high level reset, this time and the n3 low level reset in the 5 stage can improve the frequency cut flicker.
  • PWM Pulse Width Modulation
  • the n1, n2 and n3 nodes can all be reset, and the n1, n2 and n3 nodes can also be reset using high and low levels alternately, and Increase the Vgs voltage of DTFT, etc., thereby further improving the hysteresis problem of DTFT and ensuring the display effect.
  • the pixel circuit is essentially an 8T1C structure, which requires five sets of GOA and three reset signals. In this case, the pixel circuit requires more than the pixel circuit shown in Figure 1. transistors and require more GOA and reset signals, which is detrimental to increasing pixel density (Pixels Per Inch, PPI), narrowing borders and reducing GOA power consumption.
  • embodiments of the present disclosure provide a pixel circuit, a driving method thereof and a display device to improve the display effect of the display device.
  • an embodiment of the present disclosure provides a pixel circuit, which includes:
  • the first reset transistor T1 is coupled between the first electrode of the light-emitting device 10 and the first initialization signal terminal Vinit1, and the gate is coupled to the first light-emitting control terminal EM(n+x);
  • the second pole of the light-emitting device 10 is coupled to the first power terminal VSS;
  • the compensation transistor T2 is coupled between the gate and the first electrode of the driving transistor T3, and the gate is coupled to the first scan control terminal N_Gate;
  • the data writing transistor T4 is coupled between the second electrode of the driving transistor T3 and the data signal terminal Data, and its gate is coupled to the second scan control terminal P_Gate;
  • the first light-emitting control transistor T5 is coupled between the second power supply terminal VDD and the second electrode of the driving transistor T3, and its gate is coupled with the first light-emitting control terminal EM(n+x);
  • the second light-emitting control transistor T6 is coupled between the first electrode of the driving transistor T3 and the first electrode of the light-emitting device 10, and its gate is coupled to the second light-emitting control terminal EM(n);
  • the first capacitor C1 is coupled between the second power terminal VDD and the gate of the driving transistor T3;
  • the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are of the same type, and are of the opposite type to the first reset transistor T1; the first light-emitting control terminal EM(n+x) is In order to receive the first light-emitting control signal, the second light-emitting control terminal EM(n) is used to receive the second light-emitting control signal.
  • the first light-emitting control signal and the second light-emitting control signal are different from the same light-emitting driving unit.
  • the stage output terminal is provided, and the second lighting control signal is earlier than the first lighting control signal.
  • the pixel circuit provided by the embodiment of the present disclosure may include a first reset transistor T1 , a compensation transistor T2 , a driving transistor T3 , a data writing transistor T4 , a first light-emitting control transistor T5 , and a second light-emitting control transistor.
  • the six transistors including T6 reduce the number of transistors in the pixel circuit compared to the pixel circuit shown in Figures 1 and 3, which is conducive to narrow bezel design.
  • the first reset transistor T1 is coupled between the first electrode of the light-emitting device 10 and the first initialization signal terminal Vinit1, and the gate is coupled with the first light-emitting control terminal EM(n+x).
  • the first pole of the light-emitting device 10 (i.e., the N4 node in FIG. 5) can be reset through the first initialization signal terminal Vinit1.
  • the first pole of the light-emitting device 10 is an anode, this is achieved. Anode reset, thus improving cut frequency flicker.
  • the second pole of the light-emitting device 10 is coupled to the first power terminal VSS.
  • the first power terminal VSS can be a low-potential power terminal and can provide a constant low-potential signal.
  • the compensation transistor T2 is coupled between the gate and the first electrode of the driving transistor T3, and the gate is coupled to the first scan control terminal N_Gate.
  • the data writing transistor T4 is coupled between the second electrode of the driving transistor T3 and the data signal terminal Data, and its gate is coupled to the second scan control terminal P_Gate.
  • the compensation transistor T2 the driving transistor T3 and the data writing transistor T4 are all turned on, the threshold voltage of the driving transistor T3 and the data signal provided by the data signal terminal Data can be written into the first capacitor C1, thus realizing the control of the driving transistor. Compensation for the threshold voltage of T3.
  • the first light-emitting control transistor T5 is coupled between the second power supply terminal VDD and the second electrode of the driving transistor T3, and the gate is connected to the first light-emitting control terminal EM(n+x)EM(n +x) coupling.
  • the second power terminal VDD can be a high-potential power terminal and can provide a constant high-potential signal.
  • the second light emitting control transistor T6 is coupled between the first electrode of the driving transistor T3 and the first electrode of the light emitting device 10 , and its gate is coupled to the second light emitting control terminal EM(n).
  • the first capacitor C1 is coupled between the second power terminal VDD and the gate of the driving transistor T3.
  • the first light emitting control transistor T5 and the second light emitting control transistor T6 are of the same type, and are of the opposite type to the first reset transistor T1.
  • the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are both P-type transistors
  • the first reset transistor T1 is an N-type transistor.
  • the first light-emitting control terminal EM(n+x) is used to receive the first light-emitting control signal
  • the second light-emitting control terminal EM(n) is used to receive the second light-emitting control signal.
  • the first light-emitting control signal and the second light-emitting control signal are provided by Different levels of output terminals of the same light-emitting driving unit are provided, and the second light-emitting control signal is earlier than the first light-emitting control signal.
  • the entire pixel circuit requires two light-emitting driving units and two gate driving units respectively coupled to the first scan control terminal N_Gate and the second scan control terminal P_Gate, and only needs the first initialization signal terminal Vinit1. Provides a reset signal.
  • the pixel circuit shown in Figure 5 can not only compensate the threshold voltage of the driving transistor T3, but also realize simultaneous reset and alternate reset of each pole of the driving transistor T3, thus simplifying the pixel circuit.
  • the structure reduces the number of transistors, ensuring a narrow frame design while improving the hysteresis problem of the driving transistor T3, avoiding afterimages, abnormal brightness of the first frame, and low grayscale flickering when switching between different driving frequencies. and other problems, improving the display effect of the display device.
  • the pixel circuit further includes a second reset transistor T7 , which is coupled between the first electrode of the driving transistor T3 and the second initialization signal. between the terminals, and the gate is coupled to the initialization control terminal P_Gate(n-y).
  • the pixel circuit further includes a second reset transistor T7.
  • the second reset transistor T7 is coupled between the first electrode of the driving transistor T3 and the second initialization signal terminal Vinit2, and the gate is connected to the initialization control terminal P_Gate. (n-y).
  • the second reset transistor T7 when the second reset transistor T7 is turned on, the first pole of the driving transistor T3 can be reset through the second initialization signal terminal Vinit2, thereby improving the hysteresis problem of the driving transistor T3.
  • the second reset transistor T7 and the data writing transistor T4 are of the same type; the second scan control terminal P_Gate is used to receive the first scan control signal, and the initialization control terminal P_Gate ( n-y) is used to receive a second scan control signal, the first scan control signal and the second scan control signal are provided by different stage output terminals of the same gate driving unit, and the second scan control signal is earlier than the The first scan control signal.
  • the second reset transistor T7 and the data writing transistor T4 are of the same type.
  • the second reset transistor T7 and the data writing transistor T4 may both be P-type transistors.
  • the second scan control terminal P_Gate is used to receive the first scan control signal
  • the initialization control terminal P_Gate(n-y) is used to receive the second scan control signal.
  • the first scan control signal and the second scan control signal are generated by different signals of the same gate driving unit.
  • the stage output terminal is provided, and the second scan control signal is earlier than the first scan control signal.
  • the first initialization signal terminal Vinit1 and the second initialization signal terminal are the same signal terminal or different signal terminals.
  • the entire pixel circuit requires two light-emitting driving units and two gate driving units, and requires at most two reset signals provided by the first initialization signal terminal Vinit1 and the second initialization signal terminal.
  • the pixel circuit shown in Figure 6 can not only compensate the threshold voltage of the driving transistor T3, but also realize simultaneous reset and alternate reset of each pole of the driving transistor T3, thus simplifying the structure of the pixel circuit. , reducing the number of transistors, ensuring a narrow frame design while improving the hysteresis problem of the driving transistor T3, avoiding problems such as afterimages, abnormal brightness of the first frame, and low grayscale flickering when switching between different driving frequencies. , improving the display effect of the display device.
  • a second capacitor C2 coupled between the second power terminal VDD and the second pole of the driving transistor T3 is further included.
  • the pixel circuit further includes a second capacitor C2 coupled between the second power terminal VDD and the second electrode of the driving transistor T3.
  • the capacitance of the second capacitor C2 The value is smaller than the capacitance value of the first capacitor C1.
  • the pixel circuit further includes a second capacitor C2 coupled between the second power terminal VDD and the second electrode of the driving transistor T3.
  • the capacitance of the second capacitor C2 The value is smaller than the capacitance value of the first capacitor C1.
  • the capacitance value of the second capacitor C2 is greater than 10 fF.
  • the second capacitor C2 can charge the N2 node through the data writing transistor T4, thereby The performance of the pixel circuit is guaranteed.
  • the capacitance value of the second capacitor C2 can be set to be smaller than the capacitance value of the first capacitor C1, thereby ensuring the layout space of the pixel circuit.
  • the first light emission control transistor T5, the second light emission control transistor T6, the driving transistor T3 and the data writing transistor T4 are all P-type transistors; the compensation transistors T2 and The first reset transistors T1 are all N-type transistors.
  • the first light-emitting control transistor T5 , the second light-emitting control transistor T6 , the driving transistor T3 and the data writing transistor T4 are all P-type transistors, and the compensation transistors T2 and The first reset transistors T1 are all N-type transistors.
  • the first light-emitting control transistor T5 will be turned on only when the first light-emitting control signal provided by the first light-emitting control terminal EM(n+x) is low level; only when the second light-emitting control terminal EM(n)
  • the second light-emitting control transistor T6 will be turned on when the second light-emitting control signal provided is low level; the data writing transistor T4 will be turned on only when the first scan control signal provided by the second scan control terminal P_Gate is low level.
  • the compensation transistor T2 On; only when the second scan control signal provided by the first scan control terminal N_Gate is high level, the compensation transistor T2 will be turned on; only when the second scan control signal provided by the initialization control terminal P_Gate (n-y) is high level Normally, the first reset transistor T1 will be turned on.
  • the first lighting control terminal EM(n+x), the second lighting control terminal EM(n), the first scanning control terminal N_Gate, the second scanning control terminal P_Gate and the initialization control terminal P_Gate(n-y) can be Corresponding signals are loaded respectively to control the on and off of the corresponding transistors, thus improving the control effect of the pixel circuit.
  • the active layers of the compensation transistor T2 and the first reset transistor T1 are made of metal oxide semiconductor materials, and the driving transistor T3, the data writing transistor T4, the first light-emitting transistor T1 are made of metal oxide semiconductor material.
  • the active layers of the control transistor T5 and the second light emission control transistor T6 are made of low-temperature polysilicon material.
  • the active layers of the compensation transistor T2 and the first reset transistor T1 are metal oxide semiconductor materials, and the driving transistor T3, the data writing transistor T4, and the first light emitting control transistor T2 are made of metal oxide semiconductor materials.
  • the active layers of the transistor T5 and the second light emission control transistor T6 are made of low-temperature polysilicon material.
  • the compensation transistor T2 and the first reset transistor T1 may be N-type transistors using metal oxide semiconductor materials as active layers, so that the compensation transistor T2 and the first reset transistor T1 have smaller leakage current.
  • the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 may be P-type transistors (ie, LTPS type transistors) using low-temperature polysilicon material as the active layer, so that the driving transistor T3, the data The writing transistor T4, the first light emission control transistor T5 and the second light emission control transistor T6 have higher mobility, and can be made thinner and smaller, with lower power consumption, etc.
  • the pixel circuit provided by the embodiment of the present disclosure is essentially a low temperature polysilicon + oxide (Low Temperature Poly-silicon + oxide) that combines the two transistor preparation processes of LTPS transistor and oxide transistor to prepare low-temperature polysilicon oxide. +Oxide, LTPO) pixel circuit, thereby ensuring that the leakage current of the gate of the driving transistor T3 is small and the power consumption is low.
  • the light emitting device 10 in the embodiment of the present disclosure can be configured as an electroluminescent diode, such as an organic light emitting diode (OLED), a quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, QLED), a micro At least one of inorganic light emitting diodes (micro Light Emitting Diode/Mini Light Emitting Diode), which is not limited here.
  • the light-emitting device 10 may include a stacked anode, a light-emitting layer, and a cathode.
  • the light-emitting layer may also include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.
  • the light-emitting device 10 can be designed according to the requirements of the actual application environment, and there is no limitation here.
  • the first pole and the second pole of each transistor mentioned above can be interchangeable according to the corresponding type and the signal at the signal end.
  • the first pole can be the source, and the second pole can be the drain.
  • the first pole can be the drain, and the second pole can be the source.
  • Each transistor can be a thin film transistor (TFT, Thin Film Transistor) or a metal oxide semiconductor field effect transistor (MOS, Metal Oxide Semiconductor), which is not limited here.
  • TFT Thin Film Transistor
  • MOS Metal Oxide Semiconductor
  • the above are only examples to illustrate the specific structure of the pixel circuit provided by the embodiments of the present disclosure.
  • the specific structure of the above-mentioned pixel circuit is not limited to the above-mentioned structure provided by the embodiments of the present disclosure, and may also be other structures known to those skilled in the art. , these are all within the protection scope of the present invention and are not specifically limited here.
  • Figure 9 is one of the timing diagrams of the write frame corresponding to the pixel circuit shown in Figure 5
  • Figure 10 is One of the timing diagrams of the holding frame corresponding to the pixel circuit shown in 5 illustrates the working process of the pixel circuit provided by the embodiment of the present disclosure.
  • the potential signal provided by the first power supply terminal VSS is low level
  • the potential signal provided by the second power supply terminal VDD is high level.
  • the current display frame of the display device can be divided into one writing frame and N holding frames according to the current refresh frequency and the reference refresh frequency of the display device, where N is an integer greater than 1.
  • the current display frame can be divided into one write frame and two hold frames.
  • the current refresh frequency is 60Hz
  • the baseline refresh frequency is 120Hz
  • the baseline refresh frequency is twice the current refresh frequency.
  • the current display frame can be divided into a write frame and a hold frame in sequence.
  • the current display frame can also be divided according to actual application needs, which is not limited here.
  • a write frame includes a first stage t1, a second stage t2, a third stage t3, a fourth stage t4 and a fifth stage t5 which are arranged in sequence. It should be noted that the embodiments of the present disclosure are to better explain the pixel circuit provided by the present disclosure and do not limit the specific implementation of the present disclosure, where "0" represents a low level and "1" represents a high level.
  • the first light-emitting control transistor T5 is turned on under the control of the low level of the first light-emitting control signal provided by the first light-emitting control terminal EM(n+x), and the compensation transistor T2 is turned on at the first scan control terminal It is turned on under the control of the high level provided by N_Gate, and when the driving transistor T3 is turned on, N1, N2 and N3 are reset to the high level by the second power supply terminal VDD.
  • the implementation process of the first stage t1 is the same as the aforementioned 1 The stages are roughly the same.
  • the second light emission control transistor T6 is turned off under the control of the high level of the second light emission control signal provided by the second light emission control terminal EM(n), and the light emitting device 10 does not emit light.
  • the first reset transistor T1 is turned on under the control of the high level of the first light-emitting control signal provided by the first light-emitting control terminal EM(n+x), and the compensation transistor T2 is turned on by the first scan control terminal N_Gate.
  • the second light emitting control transistor T6 is turned on under the control of the low level of the second light emitting control signal provided by the second light emitting control terminal EM(n).
  • the first light emission control transistor T5 is turned off under the high level control of the first light emission control signal provided by the first light emission control terminal EM(n+x).
  • N4 is reset to the potential of the signal provided by the first initialization signal terminal Vinit1, the light-emitting device 10 does not emit light, and N1, N2 and N3 are reset to low level.
  • the implementation process is roughly the same as the aforementioned 3 stage.
  • the first light-emitting control transistor T5 is turned on under the control of the low level of the first light-emitting control signal provided by the first light-emitting control terminal EM(n+x), and the driving transistor T3 is at the low level of N1.
  • the compensation transistor T2 is turned off under the control of low level provided by the first scan control terminal N_Gate, N1 still remains low level, at this time, the driving transistor T3 With a larger Vgs, the hysteresis problem of the driving transistor T3 is improved.
  • the second light emission control transistor T6 is turned off under the control of the high level of the second light emission control signal provided by the second light emission control terminal EM(n), and the light emitting device 10 does not emit light.
  • the implementation process of the third stage t3 is roughly the same as the aforementioned stage 2.
  • the first light-emitting control transistor T5 is turned off under the control of the high level of the first light-emitting control signal provided by the first light-emitting control terminal EM(n+x), and the second light-emitting control transistor T6 is turned off under the second light-emitting control transistor T5.
  • the second light-emitting control signal provided by the control terminal EM(n) is turned off under the control of a high level, and the light-emitting device 10 does not emit light.
  • the first reset transistor T1 is turned on under the control of the high level of the first light-emitting control signal provided by the first light-emitting control terminal EM(n+x), and the first pole (ie, N4) of the light-emitting device 10 is reset to the first An initialization signal potential provided by the signal terminal Vinit1.
  • the compensation transistor T2 is turned on under the control of the high level provided by the first scan control terminal N_Gate
  • the data writing transistor T4 is turned on under the control of the low level of the second scan control terminal P_Gate
  • the driving transistor T3 is turned on under the control of the low level of N1. It is turned on under the control of the level, loading the data signal provided by the data signal terminal Data to the second pole (i.e.
  • the gate electrode of T3 (that is, N1) is stored in the first capacitor C1, thereby realizing compensation for the threshold voltage of the driving transistor T3 and improving uniformity.
  • the implementation process of the fourth stage t4 is roughly the same as the aforementioned stage 4.
  • the first reset transistor T1 is turned on under the control of the high level of the first light-emitting control signal provided by the first light-emitting control terminal EM(n+x), and the second light-emitting control transistor T6 is turned on in the second light-emitting control terminal EM(n+x).
  • the first light-emitting control transistor T5 is turned on under the control of a low level provided by the control terminal EM(n), and the first light-emitting control transistor T5 is turned off under the control of a high-level of the first light-emitting control signal provided by the first light-emitting control terminal EM(n+x).
  • the first pole of the driving transistor T3 (that is, N3) is reset to the potential of the signal provided by the first initialization signal terminal Vinit1.
  • N3 is reset to a low level, and the light-emitting device 10 does not emit light.
  • the implementation process of the fifth stage t5 is roughly the same as the aforementioned stage 5. Moreover, the entire reset process does not pass through the driving transistor T3. Therefore, no matter what kind of picture is written, N3 can be reset to a low level, thus ensuring the performance of the pixel circuit.
  • the hold frame includes a sixth stage and a seventh stage set in sequence
  • EM(n) and EM(n+x) are set high successively.
  • the second light-emitting control transistor T6 is controlled by the second light-emitting control signal provided by the second light-emitting control terminal EM(n).
  • the first light-emitting control transistor T5 is turned off successively under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM(n+x).
  • the first reset transistor T1 is turned on under the control of the high level of the first light-emitting control signal provided by the first light-emitting control terminal EM(n+x).
  • the first pole (ie N4) of the light-emitting device 10 is reset to the potential of the signal provided by the first initialization signal terminal Vinit1, completing the anode reset (Anode Reset), and the light-emitting device 10 does not emit light.
  • the occupancy of the light-emitting phase can be controlled by controlling the length of time the light-emitting control signal is set high.
  • the space ratio enables flexible adjustment to maintain frame luminous brightness.
  • the implementation process of the sixth stage t6 is roughly the same as the aforementioned stage 6.
  • the second light-emitting control transistor T6 is turned on under the low-level control of the second light-emitting control signal provided by the second light-emitting control terminal EM(n), and the first light-emitting control transistor T5 is turned on under the first light-emitting control terminal EM(n).
  • the first light-emitting control signal provided by (n+x) is turned off under the control of a high level, and the light-emitting device 10 does not emit light.
  • the first reset transistor T1 is turned on under the control of the high level of the first light-emitting control signal provided by the first light-emitting control terminal EM(n+x), and the first pole (ie, N4) of the light-emitting device 10 is reset to the first As soon as the potential of the signal provided by the initialization signal terminal Vinit1 is reset, the first pole (ie, N3) of the driving transistor T3 is reset to a low level.
  • the implementation process of stage t7 is roughly the same as the aforementioned stage 7.
  • the control signals provided by the first scan control terminal N_Gate and the second scan control terminal P_Gate remain in a stable state.
  • the control signal provided by the first scan control terminal N_Gate is a constant low potential signal
  • the first scan control signal provided by the second scan control terminal P_Gate is a constant high potential signal.
  • the display driver chip coupled to the pixel circuit cannot implement different output implementations for writing frames and holding frames, it can only maintain the signal output of the light-emitting control terminal.
  • the first scan control terminal N_Gate and the second scan control terminal P_Gate still maintain low level and high level respectively, and can still meet the functions of the sixth stage t6 and the seventh stage t7, which will not be described in detail here. .
  • each pole of the driving transistor T3 may be repeatedly refreshed multiple times.
  • N1, N2 and N3 can be repeatedly refreshed with high levels and refreshed with low levels multiple times.
  • Figure 11 shows that the first phase t1 and the second phase t2 are A repeating unit, the writing frame includes two repeating units set in sequence.
  • multiple repeating units can also be set according to actual application needs, and other stages can also be repeated, which will not be described in detail here. In this way, the problem of afterimage is improved.
  • the duty cycle of the light-emitting phase can be changed by adjusting the width of the high level of the light-emitting control signal, thereby adjusting the brightness of the pixel circuit.
  • the adjustment can be performed by moving the rising edge of the lighting control signal forward.
  • the writing frame includes two repeating units including a first repeating unit and a second repeating unit set in sequence.
  • the occupation time of the second light-emitting control signal in the first repeating unit is, It is longer than the occupation time in the second repeating unit; the occupation time of the first light-emitting control signal in the first repeating unit is greater than the occupation time in the second repeating unit. In this way, the adjustment of the duty cycle of the light-emitting phase is achieved.
  • the pixel circuit shown in FIG. 6 can also adopt the timing diagram shown in FIG. 13, wherein the writing frame further includes an eighth step between the third stage t3 and the fourth stage t4. Stage t8.
  • the first lighting control terminal EM(n+x), the second lighting control terminal EM(n), the first scanning control terminal N_Gate and the second scanning are maintained.
  • the signal loaded on the control terminal P_Gate is in a stable voltage state and maintains the potential of the gate of the driving transistor T3 to be the same as the control signal provided by the second initialization signal terminal coupled to the second reset transistor T7.
  • the first light emission control transistor T5, the second light emission control transistor T6, the driving transistor T3 and the data writing transistor T4 are all P-type transistors; the compensation transistors T2 and The first reset transistors T1 are all N-type transistors.
  • the active layers of the compensation transistor T2 and the first reset transistor T1 are made of metal oxide semiconductor materials
  • the driving transistor T3, the data writing transistor T4, the first light-emitting transistor T1 are made of metal oxide semiconductor material.
  • the active layers of the control transistor T5 and the second light emission control transistor T6 are made of low-temperature polysilicon material.
  • transistors whose active layer is made of metal oxide semiconductor material have lower leakage current
  • transistors whose active layer is made of low-temperature polysilicon material have high mobility and can speed up charging.
  • the pixel circuit provided by the embodiments of the present disclosure can combine the advantages of these two transistors and contribute to the development of high-resolution, low-power consumption, and high-quality display products.
  • embodiments of the present disclosure also provide a display device, which includes any of the above pixel circuits.
  • the display device may be a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • Other essential components of the display device are understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used to limit the present disclosure.
  • an embodiment of the present disclosure also provides a driving method for the above-mentioned pixel circuit.
  • the driving method includes:
  • S101 According to the current refresh frequency and the reference refresh frequency of the display device, divide the current display frame of the display device into one writing frame and N holding frames, where N is an integer greater than 1; wherein, the writing The frame includes the first stage, the second stage, the third stage, the fourth stage and the fifth stage set in sequence;
  • S102 In the first stage, control the first light emitting control transistor, the driving transistor and the compensation transistor to be turned on, and reset the first pole and gate of the driving transistor through the second power supply terminal. and the potential of the second pole;
  • S103 In the second stage, control the first reset transistor, the compensation transistor and the second light emitting control transistor to be turned on, and reset the first electrode, gate electrode and second electrode of the driving transistor. potential, and resets the potential of the first pole of the light-emitting device through the first initialization signal terminal;
  • S104 In the third stage, control the first light-emitting control transistor and the driving transistor to be turned on, and reset the potentials of the first and second poles of the driving transistor;
  • S105 In the fourth stage, control the first reset transistor, the compensation transistor, the driving transistor and the data writing transistor to turn on, reset the potential of the first pole of the light-emitting device, and Load the data signal provided by the data signal terminal to the second electrode of the driving transistor, and write the threshold voltage of the driving transistor and the data signal into the gate of the driving transistor through the compensation transistor, and stored in the first capacitor;
  • S106 In the fifth stage, control the first reset transistor and the second light emission control transistor to be turned on, and reset the potential of the first pole of the driving transistor through the first initialization signal terminal.
  • the holding frame includes a sixth stage and a seventh stage set in sequence, and the method further includes:
  • S202 In the seventh stage, control the first reset transistor and the second light-emitting control transistor to be turned on, and reset the potential of the second pole of the driving transistor through the first power supply terminal.
  • the first stage and the second stage are taken as a repeating unit, and the writing frame includes M repeating units arranged in sequence, where M is a positive integer greater than 1.
  • the M repeating units include two repeating units including a first repeating unit and a second repeating unit, and the duration of the second luminescence control signal occupying the first repeating unit is, is greater than the occupation time in the second repeating unit.
  • the pixel circuit further includes a second reset transistor
  • the writing frame further includes an eighth stage located between the third stage and the fourth stage
  • the method further includes:
  • the first lighting control terminal, the second lighting control terminal, the first scanning control terminal and the second scanning control are maintained.
  • the signal loaded on the terminal is in a stable voltage state, and the potential of the gate of the driving transistor is kept the same as the control signal provided by the second initialization signal terminal coupled to the second reset transistor.
  • the pixel circuit further includes a second capacitor coupled between the second power terminal and the second electrode of the driving transistor, and the method further includes:
  • S301 In the fourth stage, load the data signal to the second pole of the driving transistor and store it in the second capacitor;
  • steps S301 to S302 For the specific implementation process of steps S301 to S302, reference may be made to the description of the relevant parts of the pixel circuit, and no further description will be given here.

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Abstract

本公开提供了一种像素电路、其驱动方法及显示装置，在该像素电路中，第一复位晶体管耦接于发光器件的第一极与第一初始化信号端之间，栅极与第一发光控制端耦接；发光器件的第二极与第一电源端耦接；补偿晶体管耦接于驱动晶体管的栅极和第一极之间，栅极与第一扫描控制端耦接；数据写入晶体管耦接于驱动晶体管的第二极和数据信号端之间，栅极与第二扫描控制端耦接；第一发光控制晶体管耦接于第二电源端和驱动晶体管的第二极之间，栅极与第一发光控制端耦接；第二发光控制晶体管耦接于驱动晶体管的第一极和发光器件的第一极之间，栅极与第二发光控制端耦接；第一电容耦接于第二电源端和驱动晶体管的栅极之间。

Description

一种像素电路、其驱动方法及显示装置 技术领域
本公开涉及显示技术领域，特别涉及一种像素电路、其驱动方法及显示装置。
背景技术
随着有源矩阵有机发光二极体(Active Matrix Organic Light Emitting Diode，AMOLED)技术的发展，人们对其画质的要求也越来越高。在追求更高画质的过程中，制造工艺导致驱动薄膜晶体管(Driver Thin Film Transistor，DTFT)阈值电压均一性的问题，DTFT磁滞导致残像、首帧亮度异常，以及不同驱动频率切换时，出现低灰阶闪烁等问题亟待解决。
发明内容
本公开提供了一种像素电路、其驱动方法及显示装置，用于提高显示装置的显示效果。
第一方面，本公开实施例提供了一种像素电路，其中，包括：第一复位晶体管、补偿晶体管、驱动晶体管、数据写入晶体管、第一发光控制晶体管、第二发光控制晶体管、发光器件和第一电容；其中：
所述第一复位晶体管耦接于所述发光器件的第一极与第一初始化信号端之间，且栅极与第一发光控制端耦接；
所述发光器件的第二极与第一电源端耦接；
所述补偿晶体管耦接于所述驱动晶体管的栅极和第一极之间，且栅极与第一扫描控制端耦接；
所述数据写入晶体管耦接于所述驱动晶体管的第二极和数据信号端之间，且栅极与第二扫描控制端耦接；
所述第一发光控制晶体管耦接于第二电源端和所述驱动晶体管的第二极 之间，且栅极与所述第一发光控制端耦接；
所述第二发光控制晶体管耦接于所述驱动晶体管的第一极和所述发光器件的第一极之间，且栅极与第二发光控制端耦接；
所述第一电容耦接于所述第二电源端和所述驱动晶体管的栅极之间；
其中，所述第一发光控制晶体管和所述第二发光控制晶体管的类型相同，且和所述第一复位晶体管的类型相反；所述第一发光控制端用于接收第一发光控制信号，所述第二发光控制端用于接收第二发光控制信号，所述第一发光控制信号和所述第二发光控制信号由同一发光驱动单元的不同级输出端提供，且所述第二发光控制信号早于所述第一发光控制信号。
在一种可能的实现方式中，还包括第二复位晶体管，所述第二复位晶体管耦接于所述驱动晶体管的第一极与第二初始化信号端之间，且栅极与初始化控制端耦接。
在一种可能的实现方式中，所述第二复位晶体管和所述数据写入晶体管的类型相同；所述第二扫描控制端用于接收第一扫描控制信号，所述初始化控制端用于接收第二扫描控制信号，所述第一扫描控制信号和所述第二扫描控制信号由同一栅极驱动单元的不同级输出端提供，且所述第二扫描控制信号早于所述第一扫描控制信号。
在一种可能的实现方式中，所述第一初始化信号端和所述第二初始化信号端为同一信号端或不同信号端。
在一种可能的实现方式中，还包括：耦接于所述第二电源端和所述驱动晶体管的第二极之间的第二电容。
在一种可能的实现方式中，所述第二电容的电容值小于所述第一电容的电容值。
在一种可能的实现方式中，所述第一发光控制晶体管、所述第二发光控制晶体管、所述驱动晶体管和所述数据写入晶体管均为P型晶体管；所述补偿晶体管和所述第一复位晶体管均为N型晶体管。
在一种可能的实现方式中，所述补偿晶体管和所述第一复位晶体管的有 源层为金属氧化物半导体材料，所述驱动晶体管、所述数据写入晶体管、所述第一发光控制晶体管和所述第二发光控制晶体管的有源层为低温多晶硅材料。
第二方面，本公开实施例还提供了一种显示装置，其中，包括如上面任一项所述的像素电路。
第三方面，本公开实施例还提供了一种如上面任一项所述的像素电路的驱动方法，其中，包括：
根据显示装置的当前刷新频率与基准刷新频率，将所述显示装置的当前显示帧划分为一个写入帧和N个保持帧，其中，N为大于1的整数；其中，所述写入帧包括依次设置的第一阶段、第二阶段、第三阶段、第四阶段和第五阶段；
在所述第一阶段，控制所述第一发光控制晶体管、所述驱动晶体管和所述补偿晶体管导通，通过所述第二电源端重置所述驱动晶体管的第一极、栅极和第二极的电位；
在所述第二阶段，控制所述第一复位晶体管、所述补偿晶体管和所述第二发光控制晶体管导通，重置所述驱动晶体管的第一极、栅极和第二极的电位，且通过所述第一初始化信号端重置所述发光器件的第一极的电位；
在所述第三阶段，控制所述第一发光控制晶体管和所述驱动晶体管导通，重置所述驱动晶体管的第一极和第二极的电位；
在所述第四阶段，控制所述第一复位晶体管、所述补偿晶体管、所述驱动晶体管和所述数据写入晶体管导通，重置所述发光器件的第一极的电位，并将所述数据信号端提供的数据信号加载至所述驱动晶体管的第二极，且通过所述补偿晶体管将所述驱动晶体管的阈值电压以及所述数据信号写入所述驱动晶体管的栅极，以及存储至所述第一电容；
在所述第五阶段，控制所述第一复位晶体管和所述第二发光控制晶体管导通，通过所述第一初始化信号端重置所述驱动晶体管的第一极的电位。
在一种可能的实现方式中，所述保持帧包括依次设置的第六阶段和第七 阶段；
在所述第六阶段，控制所述第二发光控制晶体管和所述第一发光控制晶体管先后截止，以及所述第一复位晶体管导通，通过所述第一初始化信号端重置所述发光器件的第一极的电位；
在所述第七阶段，控制所述第一复位晶体管和所述第二发光控制晶体管导通，通过所述第一电源端重置所述驱动晶体管的第二极的电位。
在一种可能的实现方式中，以所述第一阶段和所述第二阶段为一个重复单元，所述写入帧包括依次设置的M个所述重复单元，M为大于1的正整数。
在一种可能的实现方式中，所述M个重复单元包括第一重复单元和第二重复单元在内的两个重复单元，所述第二发光控制信号在所述第一重复单元中的占用时长，大于在所述第二重复单元中的占用时长。
在一种可能的实现方式中，所述像素电路还包括第二复位晶体管，所述写入帧还包括位于所述第三阶段和所述第四阶段之间的第八阶段，所述方法还包括：
在所述第八阶段和所述第四阶段之间的时间段内，保持所述第一发光控制端、所述第二发光控制端、所述第一扫描控制端以及所述第二扫描控制端所加载的信号为稳压状态，且保持所述驱动晶体管的栅极的电位和与所述第二复位晶体管耦接的第二初始化信号端所提供的控制信号相同。
在一种可能的实现方式中，所述像素电路还包括耦接于所述第二电源端和所述驱动晶体管的第二极之间的第二电容，所述方法还包括：
在所述第四阶段，将所述数据信号加载至所述驱动晶体管的第二极，并存储至所述第二电容；
通过所述第二电容继续对所述驱动晶体管的第二极进行充电。
附图说明
图1为相关技术中采用的其中一种像素电路的结构示意图；
图2为图1所示的像素电路所采用的其中一种时序图；
图3为相关技术中采用的其中一种像素电路的结构示意图；
图4为图3所示的像素电路所采用的其中一种时序图；
图5为本公开实施例提供的一种像素电路的其中一种结构示意图；
图6为本公开实施例提供的一种像素电路的其中一种结构示意图；
图7为本公开实施例提供的一种像素电路的其中一种结构示意图；
图8为本公开实施例提供的一种像素电路的其中一种结构示意图；
图9为图5所示的像素电路对应的写入帧的其中一种时序图；
图10为图5所示的像素电路对应的保持帧的其中一种时序图；
图11为图5所示的像素电路对应的写入帧的其中一种时序图；
图12为图5所示的像素电路对应的写入帧的其中一种时序图；
图13为图6所示的像素电路对应的写入帧的其中一种时序图；
图14为本公开实施例提供的一种像素电路的驱动方法的方法流程图；
图15为本公开实施例提供的一种像素电路的驱动方法的方法流程图；
图16为本公开实施例提供的一种像素电路的驱动方法的方法流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是 示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
在相关技术中，常采用如图1所示的像素电路，以及图2所示的时序图，其中，M3表示DTFT，L表示发光器件，n01、n02和n03分别表示各个晶体管与DTFT的各个极相应耦接的节点，M1和M2为N型晶体管，M3、M4、M5、M6和M7为P型晶体管，M1和M2为金属氧化物晶体管，M3至M7为低温多晶硅晶体管。对DTFT的阈值电压进行补偿，保证DTFT阈值电压的均一性，并改善低频闪烁的问题。仍结合图1和图2所示，在01阶段，对n01节点进行复位；在02阶段，数据信号写入，对DTFT的阈值电压进行补偿；在03阶段，对发光器件L的阳极(对应图1中的n04节点)进行复位；在04阶段，发光器件L发光。对于图1所示的像素电路的具体工作过程可参照相关技术中的具体实现，在此不做详述。
在图1所示的像素电路中，NR和NG采用同组栅极驱动电路(Gate on Array，GOA)驱动，PG和PR采用同组GOA驱动，V1和V2可以采用相同信号或者不同信号。这样的话，该像素电路共需要三组GOA，一个或两个复位信号。通过该像素电路可以实现对DTFT的阈值电压进行补偿。由于M1和M2为金属氧化物晶体管，可以在保持帧进行阳极重置，从而避免了低频闪烁。但是仍存在一定程度上的不同驱动频率切换时，低灰阶闪烁(即切频闪烁)，以及DTFT磁滞所带来的问题。
为此，在相关技术中，可以采用图3所示的像素电路，结合图4所示的时序图，来改善上述问题。其中，该像素电路包括m1、m2、m3、m4、m5、m6、m7和m8在内的八个晶体管，m3表示DTFT，n1、n2和n3分别表示各个晶体管与DTFT的各个极相应耦接的节点，m1和m2为金属氧化物晶体管，m3至m8为低温多晶硅晶体管。在①阶段，n1、n2、n3高电平复位，发光；在②阶段，n1低电平复位，DTFT具有较大的Vgs；在③阶段，n1、n2和n3低电平复位；在④阶段，DATA写入，DTFT阈值电压补偿；在⑤阶段，阳极(对应图3中的n4节点)低电平复位，n3高电平复位；在⑥阶段，发光控制 信号em的脉冲调制技术(Pulse Width Modulation，PWM)调节；在⑦阶段，阳极重置(Anode Reset)，n3高电平复位，此时与⑤阶段中n3低电平复位同时使用可以改善切频闪烁。由于在采用图4所示的时序图控制图3所示的像素电路的过程中，可以对n1、n2和n3节点均进行复位，还可以使用高低电平交替复位n1、n2和n3节点，以及增大DTFT的Vgs电压等，从而进一步地改善了DTFT的磁滞问题，保证了显示效果。
然而，在图3和图4中，该像素电路本质上为8T1C结构，需要五组GOA，以及三种重置信号，这样的话，该像素电路相较于图1所示的像素电路需要更多的晶体管且需要更多的GOA和重置信号，这对于增加像素密度(Pixels Per Inch，PPI)，减窄边框以及降低GOA功耗有所不利。
鉴于此，本公开实施例提供了一种像素电路、其驱动方法及显示装置，用于提高显示装置的显示效果。
如图5所示，本公开实施例提供了一种像素电路，该像素电路包括：
第一复位晶体管T1、补偿晶体管T2、驱动晶体管T3、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6、发光器件10和第一电容C1；其中：
所述第一复位晶体管T1耦接于所述发光器件10的第一极与第一初始化信号端Vinit1之间，且栅极与第一发光控制端EM(n+x)耦接；
所述发光器件10的第二极与第一电源端VSS耦接；
所述补偿晶体管T2耦接于所述驱动晶体管T3的栅极和第一极之间，且栅极与第一扫描控制端N_Gate耦接；
所述数据写入晶体管T4耦接于所述驱动晶体管T3的第二极和数据信号端Data之间，且栅极与第二扫描控制端P_Gate耦接；
所述第一发光控制晶体管T5耦接于第二电源端VDD和所述驱动晶体管T3的第二极之间，且栅极与所述第一发光控制端EM(n+x)耦接；
所述第二发光控制晶体管T6耦接于所述驱动晶体管T3的第一极和所述发光器件10的第一极之间，且栅极与第二发光控制端EM(n)耦接；
所述第一电容C1耦接于所述第二电源端VDD和所述驱动晶体管T3的栅极之间；
其中，所述第一发光控制晶体管T5和所述第二发光控制晶体管T6的类型相同，且和所述第一复位晶体管T1的类型相反；所述第一发光控制端EM(n+x)用于接收第一发光控制信号，所述第二发光控制端EM(n)用于接收第二发光控制信号，所述第一发光控制信号和所述第二发光控制信号由同一发光驱动单元的不同级输出端提供，且所述第二发光控制信号早于所述第一发光控制信号。
仍结合图5所示，本公开实施例提供的像素电路可以包括，第一复位晶体管T1、补偿晶体管T2、驱动晶体管T3、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6在内的六个晶体管，相较于图1和图3所示的像素电路来说，减少了像素电路中的晶体管个数，有利于窄边框设计。其中，第一复位晶体管T1耦接于发光器件10的第一极与第一初始化信号端Vinit1之间，且栅极与第一发光控制端EM(n+x)耦接，这样的话，在第一复位晶体管T1导通时，可以通过第一初始化信号端Vinit1对发光器件10的第一极(即图5中的N4节点)进行重置，在发光器件10的第一极为阳极时，实现了阳极重置，从而改善了切频闪烁。发光器件10的第二极与第一电源端VSS耦接，第一电源端VSS可以为低电位电源端，可以提供恒定的低电位信号。补偿晶体管T2耦接于驱动晶体管T3的栅极和第一极之间，且栅极与第一扫描控制端N_Gate耦接。数据写入晶体管T4耦接于驱动晶体管T3的第二极和数据信号端Data之间，且栅极与第二扫描控制端P_Gate耦接。在补偿晶体管T2、驱动晶体管T3和数据写入晶体管T4均导通时，可以将驱动晶体管T3的阈值电压以及数据信号端Data所提供的数据信号写入第一电容C1，从而实现了对驱动晶体管T3的阈值电压的补偿。
仍结合图5所示，第一发光控制晶体管T5耦接于第二电源端VDD和驱动晶体管T3的第二极之间，且栅极与第一发光控制端EM(n+x)EM(n+x)耦接。第二电源端VDD可以为高电位电源端，可以提供恒定的高电位信号。 第二发光控制晶体管T6耦接于驱动晶体管T3的第一极和发光器件10的第一极之间，且栅极与第二发光控制端EM(n)耦接。第一电容C1耦接于第二电源端VDD和驱动晶体管T3的栅极之间。其中，第一发光控制晶体管T5和第二发光控制晶体管T6的类型相同，且与第一复位晶体管T1的类型相反。在其中一种示例性实施例中，第一发光控制晶体管T5和第二发光控制晶体管T6均为P型晶体管，第一复位晶体管T1为N型管。第一发光控制端EM(n+x)用于接收第一发光控制信号，第二发光控制端EM(n)用于接收第二发光控制信号，第一发光控制信号和第二发光控制信号由同一发光驱动单元的不同级输出端提供，且第二发光控制信号早于第一发光控制信号。如此一来，整个像素电路需要两个发光驱动单元，以及分别与第一扫描控制端N_Gate和第二扫描控制端P_Gate耦接的两个栅极驱动单元，且仅需要第一初始化信号端Vinit1所提供的一种复位信号。
在具体实施过程中，采用图5所示的像素电路不仅可以实现对驱动晶体管T3的阈值电压进行补偿，还可以实现对驱动晶体管T3各个极的同时复位，以及交替复位，从而在简化了像素电路的结构，减少了晶体管的设置个数，保证了窄边框设计的同时，改善了驱动晶体管T3的磁滞问题，避免了残像、首帧亮度异常，以及不同驱动频率切换时，出现低灰阶闪烁等问题，改善了显示装置的显示效果。
在其中一种示例性实施例中，如图6所示，像素电路还包括第二复位晶体管T7，所述第二复位晶体管T7耦接于所述驱动晶体管T3的第一极与第二初始化信号端之间，且栅极与初始化控制端P_Gate(n-y)耦接。
仍结合图6所示，像素电路还包括第二复位晶体管T7，第二复位晶体管T7耦接于驱动晶体管T3的第一极与第二初始化信号端Vinit2之间，且栅极与初始化控制端P_Gate(n-y)。这样的话，在第二复位晶体管T7导通时，可以通过第二初始化信号端Vinit2对驱动晶体管T3的第一极进行重置，改善了驱动晶体管T3的磁滞问题。
在本公开实施例中，所述第二复位晶体管T7和所述数据写入晶体管T4 的类型相同；所述第二扫描控制端P_Gate用于接收第一扫描控制信号，所述初始化控制端P_Gate(n-y)用于接收第二扫描控制信号，所述第一扫描控制信号和所述第二扫描控制信号由同一栅极驱动单元的不同级输出端提供，且所述第二扫描控制信号早于所述第一扫描控制信号。
在具体实施过程中，第二复位晶体管T7和数据写入晶体管T4的类型相同。在其中一种示例性实施例中，仍结合图6所示，第二复位晶体管T7和数据写入晶体管T4可以是均为P型晶体管。第二扫描控制端P_Gate用于接收第一扫描控制信号，初始化控制端P_Gate(n-y)用于接收第二扫描控制信号，第一扫描控制信号和第二扫描控制信号由同一栅极驱动单元的不同级输出端提供，且第二扫描控制信号早于第一扫描控制信号。其中，所述第一初始化信号端Vinit1和所述第二初始化信号端为同一信号端或不同信号端。这样的话，整个像素电路需要两个发光驱动单元以及两个栅极驱动单元，且最多需要第一初始化信号端Vinit1和第二初始化信号端提供的两种复位信号。如此一来，采用图6所示的像素电路不仅可以实现对驱动晶体管T3的阈值电压进行补偿，还可以实现对驱动晶体管T3各个极的同时复位，以及交替复位，从而在简化了像素电路的结构，减少了晶体管的设置个数，保证了窄边框设计的同时，改善了驱动晶体管T3的磁滞问题，避免了残像、首帧亮度异常，以及不同驱动频率切换时，出现低灰阶闪烁等问题，改善了显示装置的显示效果。
在本公开实施例中，还包括：耦接于所述第二电源端VDD和所述驱动晶体管T3的第二极之间的第二电容C2。
在其中一种示例性实施例中，如图7所示，像素电路还包括耦接于第二电源端VDD和驱动晶体管T3的第二极之间的第二电容C2，第二电容C2的电容值小于第一电容C1的电容值。
在其中一种示例性实施例中，如图8所示，像素电路还包括耦接于第二电源端VDD和驱动晶体管T3的第二极之间的第二电容C2，第二电容C2的电容值小于第一电容C1的电容值。
需要说明的是，在图7和图8对应的示例性实施例中，第二电容C2的电容值大于10fF，这样的话，第二电容C2可以通过数据写入晶体管T4对N2节点进行充电，从而保证了像素电路的使用性能。可以将第二电容C2的电容值设置为小于第一电容C1的电容值，从而保证了像素电路的布局空间。
仍结合图7和图8，在高频情况下，数据写入晶体管T4、驱动晶体管T3和补偿晶体管T2均导通时，可以通过数据信号端Data对N2节点进行充电，并将其存储至第二电容C2，后续在数据写入晶体管T4截止，且补偿晶体管T2仍导通时，可以通过第二电容C2和N2节点继续对N1节点进行阈值电压补偿。
在本公开实施例中，所述第一发光控制晶体管T5、所述第二发光控制晶体管T6、所述驱动晶体管T3和所述数据写入晶体管T4均为P型晶体管；所述补偿晶体管T2和所述第一复位晶体管T1均为N型晶体管。
在具体实施过程中，仍结合图5至图8所示，第一发光控制晶体管T5、第二发光控制晶体管T6、驱动晶体管T3和数据写入晶体管T4均为P型晶体管，且补偿晶体管T2和第一复位晶体管T1均为N型晶体管。这样的话，只有在第一发光控制端EM(n+x)提供的第一发光控制信号为低电平时，第一发光控制晶体管T5才会导通；只有在第二发光控制端EM(n)提供的第二发光控制信号为低电平时，第二发光控制晶体管T6才会导通；只有在第二扫描控制端P_Gate提供的第一扫描控制信号为低电平时，数据写入晶体管T4才会导通；只有在第一扫描控制端N_Gate提供的第二扫描控制信号为高电平时，补偿晶体管T2才会导通；只有在初始化控制端P_Gate(n-y)提供的第二扫描控制信号为高电平时，第一复位晶体管T1才会导通。在实际应用中，可以对第一发光控制端EM(n+x)、第二发光控制端EM(n)、第一扫描控制端N_Gate、第二扫描控制端P_Gate和初始化控制端P_Gate(n-y)分别加载相应的信号，以此来控制相应晶体管的导通与截止，从而提高了像素电路的控制效果。
在本公开实施例中，所述补偿晶体管T2和所述第一复位晶体管T1的有 源层为金属氧化物半导体材料，所述驱动晶体管T3、所述数据写入晶体管T4、所述第一发光控制晶体管T5和所述第二发光控制晶体管T6的有源层为低温多晶硅材料。
在具体实施过程中，仍结合图5至图8所示，补偿晶体管T2和第一复位晶体管T1的有源层为金属氧化物半导体材料，驱动晶体管T3、数据写入晶体管T4、第一发光控制晶体管T5和第二发光控制晶体管T6的有源层为低温多晶硅材料。相应地，补偿晶体管T2和第一复位晶体管T1可以是用金属氧化物半导体材料作为有源层的N型晶体管，使得补偿晶体管T2和第一复位晶体管T1具有较小的漏电流。驱动晶体管T3、数据写入晶体管T4、第一发光控制晶体管T5和第二发光控制晶体管T6可以是用低温多晶硅材料作为有源层的P型晶体管(即LTPS型晶体管)，使得驱动晶体管T3、数据写入晶体管T4、第一发光控制晶体管T5和第二发光控制晶体管T6具有较高的迁移率，而且可以做的更薄更小、功耗更低等。这样的话，本公开实施例所提供的像素电路，实质上为将LTPS型晶体管与氧化物晶体管这两种制备晶体管的工艺进行结合制备低温多晶硅氧化物的低温多晶硅+氧化物(Low Temperature Poly-silicon+Oxide，LTPO)像素电路，从而保证了驱动晶体管T3的栅极的漏电流较小，功耗较低。
需要说明的是，本公开实施例中的发光器件10可以设置为电致发光二极管，例如有机发光二极管(Organic Light Emitting Diode，OLED)、量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)、微型无机发光二极管(micro Light Emitting Diode/Mini Light Emitting Diode)中的至少一种，在此不做限定。其中，所述发光器件10可以包括层叠设置的阳极、发光层、阴极。进一步地，发光层还可以包括空穴注入层、空穴传输层、电子传输层、电子注入层等膜层。当然，在实际应用中，可以根据实际应用环境的需求对发光器件10进行设计，在此不做限定。
上述提及的各个晶体管的第一极和第二极可以根据相应的类型以及信号端的信号的不同，其功能可以互换。比如，可以是第一极为源极，相应地第 二极为漏极，再比如，可以是第一极为漏极，相应地第二极为源极，在此不做限定。各个晶体管可以是薄膜晶体管(TFT，Thin Film Transistor)，也可以是金属氧化物半导体场效应管(MOS，Metal Oxide Semiconductor)，在此不作限定。当然，还可以根据实际应用需要来设置各个晶体管的具体类型，在此不做限定。
以上仅是举例说明本公开实施例提供的像素电路的具体结构，在具体实施时，上述像素电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，这些均在本发明的保护范围之内，具体在此不作限定。
下面以图5所示的像素电路结构以及图9和图10所示的时序图，其中，图9为图5所示的像素电路对应的写入帧的其中一种时序图，图10为图5所示的像素电路对应的保持帧的其中一种时序图，对本公开实施例提供的像素电路的工作过程进行说明。其中，第一电源端VSS提供的电位信号为低电平，第二电源端VDD提供的电位信号为高电平。此外，可以根据显示装置的当前刷新频率与基准刷新频率，将显示装置的当前显示帧划分为一个写入帧和N个保持帧，其中，N为大于1的整数。比如，当前刷新频率为40Hz，基准刷新频率为120Hz，基准刷新频率为当前刷新频率的三倍，可以将当前显示帧依次划分为一个写入帧和两个保持帧。再比如，当前刷新频率为60Hz，基准刷新频率为120Hz，基准刷新频率为当前刷新频率的两倍，可以将当前显示帧依次划分为一个写入帧和一个保持帧。当然，还可以根据实际应用需要来对当前显示帧进行划分，在此不做限定。一个写入帧包括依次设置的第一阶段t1、第二阶段t2、第三阶段t3、第四阶段t4和第五阶段t5。需要说明的是，本公开实施例是为了更好的解释本公开所提供的像素电路，并不限制本公开的具体实现，其中，“0”表示低电平，“1”表示高电平。
在第一阶段t1，EM(n+x)＝0，EM(n)＝1，N_Gate＝1，P_Gate＝1；
在第一阶段t1，第一发光控制晶体管T5在第一发光控制端EM(n+x)提供的第一发光控制信号的低电平的控制下导通，补偿晶体管T2在第一扫描 控制端N_Gate提供的高电平的控制下导通，且在驱动晶体管T3导通时，N1、N2和N3被第二电源端VDD重置为高电平，该第一阶段t1的实现过程和前述①阶段大致相同。此外，第二发光控制晶体管T6在第二发光控制端EM(n)提供的第二发光控制信号的高电平的控制下截止，发光器件10不发光。
在第二阶段t2，EM(n+x)＝1，EM(n)＝0，N_Gate＝1，P_Gate＝1；
在第二阶段t2，第一复位晶体管T1在第一发光控制端EM(n+x)提供的第一发光控制信号的高电平的控制下导通，补偿晶体管T2在第一扫描控制端N_Gate提供的高电平的控制下导通，第二发光控制晶体管T6在第二发光控制端EM(n)提供的第二发光控制信号的低电平的控制下导通。第一发光控制晶体管T5在第一发光控制端EM(n+x)提供的第一发光控制信号的高电平控制下截止。在该第二阶段t2，N4被重置为第一初始化信号端Vinit1所提供的信号的电位，发光器件10不发光，N1、N2和N3被重置为低电平，该第二阶段t2的实现过程和前述③阶段大致相同。
在第三阶段t3，EM(n+x)＝0，EM(n)＝1，N_Gate＝0，P_Gate＝1；
在第三阶段t3，第一发光控制晶体管T5在第一发光控制端EM(n+x)提供的第一发光控制信号的低电平的控制下导通，驱动晶体管T3在N1的低电平的控制下导通，N2和N3被重置为高电平，补偿晶体管T2在第一扫描控制端N_Gate提供的低电平的控制下截止，N1仍保持低电平，此时，驱动晶体管T3具有较大的Vgs，从而改善了驱动晶体管T3的磁滞问题。此外，第二发光控制晶体管T6在第二发光控制端EM(n)提供的第二发光控制信号的高电平的控制下截止，发光器件10不发光。该第三阶段t3的实现过程和前述②阶段大致相同。
在第四阶段t4，EM(n+x)＝1，EM(n)＝1，N_Gate＝1，P_Gate＝0；
在第四阶段t4，第一发光控制晶体管T5在第一发光控制端EM(n+x)提供的第一发光控制信号的高电平的控制下截止，第二发光控制晶体管T6在第二发光控制端EM(n)提供的第二发光控制信号的高电平的控制下截止，发光器件10不发光。第一复位晶体管T1在第一发光控制端EM(n+x)提供 的第一发光控制信号的高电平的控制下导通，发光器件10的第一极(即N4)被重置为第一初始化信号端Vinit1所提供的信号的电位。补偿晶体管T2在第一扫描控制端N_Gate提供的高电平的控制下导通，数据写入晶体管T4在第二扫描控制端P_Gate的低电平的控制下导通，驱动晶体管T3在N1的低电平的控制下导通，将数据信号端Data提供的数据信号加载至驱动晶体管T3的第二极(即N2)，且通过补偿晶体管T2将驱动晶体管T3的阈值电压以及数据信号写入驱动晶体管T3的栅极(即N1)，并存储至第一电容C1，从而实现了对驱动晶体管T3的阈值电压的补偿，改善了均一性。该第四阶段t4的实现过程和前述④阶段大致相同。
在第五阶段t5，EM(n+x)＝1，EM(n)＝0，N_Gate＝0，P_Gate＝1。
在第五阶段t5，第一复位晶体管T1在第一发光控制端EM(n+x)提供的第一发光控制信号的高电平的控制下导通，第二发光控制晶体管T6在第二发光控制端EM(n)提供的低电平的控制下导通，第一发光控制晶体管T5在第一发光控制端EM(n+x)提供的第一发光控制信号的高电平的控制下截止，驱动晶体管T3的第一极(即N3)被重置为第一初始化信号端Vinit1所提供的信号的电位，相应地，N3被重置为低电平，发光器件10不发光。该第五阶段t5的实现过程和前述⑤阶段大致相同。而且，整个重置过程未经过驱动晶体管T3，因此，无论写入哪种画面，N3均可被复位为低电平，从而保证了像素电路的使用性能。
此外，保持帧包括依次设置的第六阶段和第七阶段；
在第六阶段t6，EM(n)及EM(n+x)先后置高，N_Gate＝0，P_Gate＝1；
在第六阶段t6，EM(n)及EM(n+x)先后置高，相应地，第二发光控制晶体管T6在第二发光控制端EM(n)提供的第二发光控制信号的控制下，第一发光控制晶体管T5在第一发光控制端EM(n+x)提供的第一发光控制信号的控制下，先后截止。而且，第一复位晶体管T1在第一发光控制端EM(n+x)提供的第一发光控制信号的高电平的控制下导通，相应地，发光器件10的第一极(即N4)被重置为第一初始化信号端Vinit1所提供的信号的电位， 完成对阳极复位(Anode Reset)，发光器件10不发光，此时，可以通过控制发光控制信号置高时长来控制发光阶段的占空比，从而实现对保持帧发光亮度的灵活调整。而且，第六阶段t6的实现过程和前述⑥阶段大致相同。
在第七阶段t7，EM(n+x)＝1，EM(n)＝0，N_Gate＝0，P_Gate＝1；
在第七阶段，第二发光控制晶体管T6在第二发光控制端EM(n)提供的第二发光控制信号的低电平控制下导通，第一发光控制晶体管T5在第一发光控制端EM(n+x)提供的第一发光控制信号的高电平的控制下截止，发光器件10不发光。第一复位晶体管T1在第一发光控制端EM(n+x)提供的第一发光控制信号的高电平的控制下导通，发光器件10的第一极(即N4)被重置为第一初始化信号端Vinit1所提供的信号的电位，驱动晶体管T3的第一极(即N3)被复位为低电平。而且，第t7阶段的实现过程和前述⑦阶段大致相同。
需要说明的是，在第六阶段t6和第七阶段t7，除发光控制信号需进行信号输出外，第一扫描控制端N_Gate和第二扫描控制端P_Gate所提供的控制信号均保持稳压状态，第一扫描控制端N_Gate所提供的控制信号为恒定的低电位信号，第二扫描控制端P_Gate所提供的第一扫描控制信号为恒定的高电位信号。在其中一种示例性实施例中，对于图5所示的像素电路，若与像素电路耦接的显示驱动芯片不能实现写入帧和保持帧不同的输出实现，可以仅保持发光控制端的信号输出与写入帧相同，第一扫描控制端N_Gate和第二扫描控制端P_Gate仍分别保持低电平和高电平，仍可以满足第六阶段t6和第七阶段t7的功能，在此不做详述。
在其中一种示例性实施例中，可以对驱动晶体管T3的各极进行重复多次刷新。以图11所示的时序图为例，可以多次对N1、N2和N3反复进行高电平刷新以及低电平刷新，图11中示意出了，以第一阶段t1和第二阶段t2为一个重复单元，写入帧包括依次设置的两个重复单元的情况。当然，还可以根据实际应用需要继续设置多个重复单元，还可以对其它阶段进行重复，在此不做详述。如此一来，改善了残像的问题。
在本公开实施例中，可以通过调整发光控制信号高电平的宽度来改变发光阶段的占空比，从而实现像素电路对亮度的调整。在其中一种示例性实施例中，可以通过将发光控制信号的上升沿前移的方式进行调整。以图12所示的时序图为例，写入帧包括依次设置的第一重复单元和第二重复单元在内的两个重复单元，第二发光控制信号在第一重复单元中的占用时长，大于在第二重复单元中的占用时长；第一发光控制信号在第一重复单元中的占用时长，大于在第二重复单元中的占用时长。如此一来，实现了对发光阶段的占空比的调整。
在其中一种示例性实施例中，图6所示的像素电路还可以采用图13所示的时序图，其中，写入帧还包括位于第三阶段t3和第四阶段t4之间的第八阶段t8。在第八阶段t8和第四阶段t4之间的时间段内，保持第一发光控制端EM(n+x)、第二发光控制端EM(n)、第一扫描控制端N_Gate以及第二扫描控制端P_Gate所加载的信号为稳压状态，且保持驱动晶体管T3的栅极的电位和与第二复位晶体管T7耦接的第二初始化信号端所提供的控制信号相同。这样的话，在第八阶段t8和第四阶段t4之间的时间段内不存在信号跳变，N1节点的电位保持为Vinit1。而且，将复位N1节点的电压与复位阳极的电压分开，提高了像素电路的控制能力。
在本公开实施例中，所述第一发光控制晶体管T5、所述第二发光控制晶体管T6、所述驱动晶体管T3和所述数据写入晶体管T4均为P型晶体管；所述补偿晶体管T2和所述第一复位晶体管T1均为N型晶体管。
在本公开实施例中，所述补偿晶体管T2和所述第一复位晶体管T1的有源层为金属氧化物半导体材料，所述驱动晶体管T3、所述数据写入晶体管T4、所述第一发光控制晶体管T5和所述第二发光控制晶体管T6的有源层为低温多晶硅材料。其中，有源层为金属氧化物半导体材料的晶体管具有更低的漏电流，有源层为低温多晶硅材料的晶体管的迁移率高，可以加快充电速度。这样的话，本公开实施例所提供的像素电路可以将这两种晶体管的优势结合起来，有助于高分辨率、低功耗、高画质的显示产品的开发。
基于同一公开构思，本公开实施例还提供了一种显示装置，该显示装置包括上述任一种像素电路。
由于该显示装置解决问题的原理与前述像素电路相似。因此，该显示装置的实施可以参见前述像素电路的实施，重复之处不再赘述。
在具体实施过程中，本公开实施例所提供的显示装置可以是手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
基于同一公开构思，如图14所示，本公开实施例还提供了上述像素电路的驱动方法，该驱动方法包括：
S101：根据显示装置的当前刷新频率与基准刷新频率，将所述显示装置的当前显示帧划分为一个写入帧和N个保持帧，其中，N为大于1的整数；其中，所述写入帧包括依次设置的第一阶段、第二阶段、第三阶段、第四阶段和第五阶段；
S102：在所述第一阶段，控制所述第一发光控制晶体管、所述驱动晶体管和所述补偿晶体管导通，通过所述第二电源端重置所述驱动晶体管的第一极、栅极和第二极的电位；
S103：在所述第二阶段，控制所述第一复位晶体管、所述补偿晶体管和所述第二发光控制晶体管导通，重置所述驱动晶体管的第一极、栅极和第二极的电位，且通过所述第一初始化信号端重置所述发光器件的第一极的电位；
S104：在所述第三阶段，控制所述第一发光控制晶体管和所述驱动晶体管导通，重置所述驱动晶体管的第一极和第二极的电位；
S105：在所述第四阶段，控制所述第一复位晶体管、所述补偿晶体管、所述驱动晶体管和所述数据写入晶体管导通，重置所述发光器件的第一极的电位，并将所述数据信号端提供的数据信号加载至所述驱动晶体管的第二极，且通过所述补偿晶体管将所述驱动晶体管的阈值电压以及所述数据信号写入所述驱动晶体管的栅极，以及存储至所述第一电容；
S106：在所述第五阶段，控制所述第一复位晶体管和所述第二发光控制晶体管导通，通过所述第一初始化信号端重置所述驱动晶体管的第一极的电位。
在其中一种示例性实施例中，对于步骤S101至步骤S106的具体实现过程，可以参照前述采用图5所示的像素电路以及图9所示的时序图相应部分的描述，在此不做赘述。
在本公开实施例中，如图15所示，所述保持帧包括依次设置的第六阶段和第七阶段，所述方法还包括：
S201：在所述第六阶段，控制所述第二发光控制晶体管和所述第一发光控制晶体管先后截止，以及所述第一复位晶体管导通，通过所述第一初始化信号端重置所述发光器件的第一极的电位；
S202：在所述第七阶段，控制所述第一复位晶体管和所述第二发光控制晶体管导通，通过所述第一电源端重置所述驱动晶体管的第二极的电位。
在其中一种示例性实施例中，对于步骤S201至步骤S202的具体实现过程，可以参照前述采用图5所示的像素电路以及图10所示的时序图相应部分的描述，在此不做赘述。
在本公开实施例中，以所述第一阶段和所述第二阶段为一个重复单元，所述写入帧包括依次设置的M个所述重复单元，M为大于1的正整数。
在本公开实施例中，所述M个重复单元包括第一重复单元和第二重复单元在内的两个重复单元，所述第二发光控制信号在所述第一重复单元中的占用时长，大于在所述第二重复单元中的占用时长。对于该部分的具体实现过程，可以参照前述采用图5所示的像素电路以及图12所示的时序图相应部分的描述，在此不做赘述。
在本公开实施例中，所述像素电路还包括第二复位晶体管，所述写入帧还包括位于所述第三阶段和所述第四阶段之间的第八阶段，所述方法还包括：
在所述第八阶段和所述第四阶段之间的时间段内，保持所述第一发光控制端、所述第二发光控制端、所述第一扫描控制端以及所述第二扫描控制端 所加载的信号为稳压状态，且保持所述驱动晶体管的栅极的电位和与所述第二复位晶体管耦接的第二初始化信号端所提供的控制信号相同。对于该部分的具体实现过程，可以参照前述采用图6所示的像素电路还可以采用图13所示的时序图相应部分的描述，在此不做赘述。
在本公开实施例中，如图16所示，所述像素电路还包括耦接于所述第二电源端和所述驱动晶体管的第二极之间的第二电容，所述方法还包括：
S301：在所述第四阶段，将所述数据信号加载至所述驱动晶体管的第二极，并存储至所述第二电容；
S302：通过所述第二电容继续对所述驱动晶体管的第二极进行充电。
对于步骤S301至步骤S302的具体实现过程，可以参照前述像素电路中相关部分的描述，在此不做赘述。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本申请的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (15)

  1. 一种像素电路，其中，包括：第一复位晶体管、补偿晶体管、驱动晶体管、数据写入晶体管、第一发光控制晶体管、第二发光控制晶体管、发光器件和第一电容；其中：
    所述第一复位晶体管耦接于所述发光器件的第一极与第一初始化信号端之间，且栅极与第一发光控制端耦接；
    所述发光器件的第二极与第一电源端耦接；
    所述补偿晶体管耦接于所述驱动晶体管的栅极和第一极之间，且栅极与第一扫描控制端耦接；
    所述数据写入晶体管耦接于所述驱动晶体管的第二极和数据信号端之间，且栅极与第二扫描控制端耦接；
    所述第一发光控制晶体管耦接于第二电源端和所述驱动晶体管的第二极之间，且栅极与所述第一发光控制端耦接；
    所述第二发光控制晶体管耦接于所述驱动晶体管的第一极和所述发光器件的第一极之间，且栅极与第二发光控制端耦接；
    所述第一电容耦接于所述第二电源端和所述驱动晶体管的栅极之间；
    其中，所述第一发光控制晶体管和所述第二发光控制晶体管的类型相同，且和所述第一复位晶体管的类型相反；所述第一发光控制端用于接收第一发光控制信号，所述第二发光控制端用于接收第二发光控制信号，所述第一发光控制信号和所述第二发光控制信号由同一发光驱动单元的不同级输出端提供，且所述第二发光控制信号早于所述第一发光控制信号。
  2. 如权利要求1所述的像素电路，其中，还包括第二复位晶体管，所述第二复位晶体管耦接于所述驱动晶体管的第一极与第二初始化信号端之间，且栅极与初始化控制端耦接。
  3. 如权利要求2所述的像素电路，其中，所述第二复位晶体管和所述数据写入晶体管的类型相同；所述第二扫描控制端用于接收第一扫描控制信号， 所述初始化控制端用于接收第二扫描控制信号，所述第一扫描控制信号和所述第二扫描控制信号由同一栅极驱动单元的不同级输出端提供，且所述第二扫描控制信号早于所述第一扫描控制信号。
  4. 如权利要求3所述的像素电路，其中，所述第一初始化信号端和所述第二初始化信号端为同一信号端或不同信号端。
  5. 如权利要求1-4任一项所述的像素电路，其中，还包括：耦接于所述第二电源端和所述驱动晶体管的第二极之间的第二电容。
  6. 如权利要求5所述的像素电路，其中，所述第二电容的电容值小于所述第一电容的电容值。
  7. 如权利要求1-4任一项所述的像素电路，其中，所述第一发光控制晶体管、所述第二发光控制晶体管、所述驱动晶体管和所述数据写入晶体管均为P型晶体管；所述补偿晶体管和所述第一复位晶体管均为N型晶体管。
  8. 如权利要求7所述的像素电路，其中，所述补偿晶体管和所述第一复位晶体管的有源层为金属氧化物半导体材料，所述驱动晶体管、所述数据写入晶体管、所述第一发光控制晶体管和所述第二发光控制晶体管的有源层为低温多晶硅材料。
  9. 一种显示装置，其中，包括如权利要求1-8任一项所述的像素电路。
  10. 一种如权利要求1-8任一项所述的像素电路的驱动方法，其中，包括：
    根据显示装置的当前刷新频率与基准刷新频率，将所述显示装置的当前显示帧划分为一个写入帧和N个保持帧，其中，N为大于1的整数；其中，所述写入帧包括依次设置的第一阶段、第二阶段、第三阶段、第四阶段和第五阶段；
    在所述第一阶段，控制所述第一发光控制晶体管、所述驱动晶体管和所述补偿晶体管导通，通过所述第二电源端重置所述驱动晶体管的第一极、栅极和第二极的电位；
    在所述第二阶段，控制所述第一复位晶体管、所述补偿晶体管和所述第二发光控制晶体管导通，重置所述驱动晶体管的第一极、栅极和第二极的电 位，且通过所述第一初始化信号端重置所述发光器件的第一极的电位；
    在所述第三阶段，控制所述第一发光控制晶体管和所述驱动晶体管导通，重置所述驱动晶体管的第一极和第二极的电位；
    在所述第四阶段，控制所述第一复位晶体管、所述补偿晶体管、所述驱动晶体管和所述数据写入晶体管导通，重置所述发光器件的第一极的电位，并将所述数据信号端提供的数据信号加载至所述驱动晶体管的第二极，且通过所述补偿晶体管将所述驱动晶体管的阈值电压以及所述数据信号写入所述驱动晶体管的栅极，以及存储至所述第一电容；
    在所述第五阶段，控制所述第一复位晶体管和所述第二发光控制晶体管导通，通过所述第一初始化信号端重置所述驱动晶体管的第一极的电位。
  11. 如权利要求10所述的方法，其中，所述保持帧包括依次设置的第六阶段和第七阶段，所述方法还包括：
    在所述第六阶段，控制所述第二发光控制晶体管和所述第一发光控制晶体管先后截止，以及所述第一复位晶体管导通，通过所述第一初始化信号端重置所述发光器件的第一极的电位；
    在所述第七阶段，控制所述第一复位晶体管和所述第二发光控制晶体管导通，通过所述第一电源端重置所述驱动晶体管的第二极的电位。
  12. 如权利要求10所述的方法，其中，以所述第一阶段和所述第二阶段为一个重复单元，所述写入帧包括依次设置的M个所述重复单元，M为大于1的正整数。
  13. 如权利要求12所述的方法，其中，所述M个重复单元包括第一重复单元和第二重复单元在内的两个重复单元，所述第二发光控制信号在所述第一重复单元中的占用时长，大于在所述第二重复单元中的占用时长。
  14. 如权利要求10-13任一项所述的方法，其中，所述像素电路还包括第二复位晶体管，所述写入帧还包括位于所述第三阶段和所述第四阶段之间的第八阶段，所述方法还包括：
    在所述第八阶段和所述第四阶段之间的时间段内，保持所述第一发光控 制端、所述第二发光控制端、所述第一扫描控制端以及所述第二扫描控制端所加载的信号为稳压状态，且保持所述驱动晶体管的栅极的电位和与所述第二复位晶体管耦接的第二初始化信号端所提供的控制信号相同。
  15. 如权利要求14所述的方法，其中，所述像素电路还包括耦接于所述第二电源端和所述驱动晶体管的第二极之间的第二电容，所述方法还包括：
    在所述第四阶段，将所述数据信号加载至所述驱动晶体管的第二极，并存储至所述第二电容；
    通过所述第二电容继续对所述驱动晶体管的第二极进行充电。
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