WO2023221369A1 - 一种异质结电池及其制备方法 - Google Patents

一种异质结电池及其制备方法 Download PDF

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WO2023221369A1
WO2023221369A1 PCT/CN2022/123404 CN2022123404W WO2023221369A1 WO 2023221369 A1 WO2023221369 A1 WO 2023221369A1 CN 2022123404 W CN2022123404 W CN 2022123404W WO 2023221369 A1 WO2023221369 A1 WO 2023221369A1
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layer
transparent conductive
amorphous silicon
conductive layer
type doped
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PCT/CN2022/123404
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French (fr)
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毛卫平
刘霖
赵锋
徐锐
任明冲
张杜超
蔡涔
杨伯川
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东方日升新能源股份有限公司
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Publication of WO2023221369A1 publication Critical patent/WO2023221369A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table

Definitions

  • the present application relates to the field of heterojunction batteries, and specifically to a heterojunction battery and a preparation method thereof.
  • Monocrystalline silicon heterojunction solar cells have high conversion efficiency and are recognized by the photovoltaic industry as one of the key technologies for the next generation of large-scale industrialization.
  • Silicon-based heterojunction solar cells are generally made of N-type monocrystalline silicon wafers with a double-sided pyramid texture structure.
  • An intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer are deposited on the front side of the silicon wafer, and an N-type doped amorphous silicon layer is deposited on the back side of the silicon wafer.
  • An intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer are deposited, and then transparent conductive films and metal electrodes are formed on both sides of the silicon wafer.
  • the transparent conductive layer is easily affected by the adsorption of water vapor, oxygen, and organic matter in the air, resulting in poor contact performance between the transparent conductive layer and the low-temperature slurry, and increased contact resistance, ultimately resulting in low battery efficiency.
  • a heterojunction battery including a crystalline silicon layer.
  • a first intrinsic amorphous silicon layer, an N-type doped amorphous silicon layer, and a third intrinsic amorphous silicon layer are arranged on the front side of the crystalline silicon layer from the inside out.
  • a transparent conductive layer, a first metal electrode, a second intrinsic amorphous silicon layer, a P-type doped amorphous silicon layer, a second transparent conductive layer, and a second metal electrode are arranged on the back of the crystalline silicon layer from the inside to the outside.
  • a local reduction layer is formed on the surface of the first transparent conductive layer below the first metal electrode and/or on the surface of the second transparent conductive layer below the second metal electrode. The local reduction layer The carrier concentration is higher than the first transparent conductive layer and/or the second transparent conductive layer.
  • the contact resistance between the transparent conductive layer and the metal electrode is improved, and the battery fill factor and photoelectric conversion efficiency are improved.
  • the width of the local reduction layer is 5 ⁇ m-50 ⁇ m.
  • the crystalline silicon layer is N-type doped monocrystalline silicon, N-type doped quasi-monocrystalline silicon, P-type doped quasi-monocrystalline silicon, or P-type doped quasi-monocrystalline silicon.
  • the thickness of the layer ranges from 50 ⁇ m to 250 ⁇ m.
  • the first intrinsic amorphous silicon layer is a composite thin film layer laminated with undoped amorphous silicon, amorphous silicon oxide, amorphous silicon carbide semiconductor films or combinations thereof.
  • the thickness of the amorphous silicon layer is 2nm-8nm.
  • the N-type doped amorphous silicon layer is N-type doped amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon, microcrystalline silicon oxide, microcrystalline silicon carbide semiconductor
  • the thickness of the N-type doped amorphous silicon layer is 4nm-30nm.
  • the P-type doped amorphous silicon layer is P-type doped amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon, microcrystalline silicon oxide, microcrystalline silicon carbide Semiconductor film or composite film layer laminated by a combination thereof, the thickness of the P-type doped amorphous silicon layer is 4nm-30nm.
  • the first transparent conductive layer is a composite thin film layer laminated with doped indium oxide, zinc oxide or tin oxide or a combination thereof, and the thickness of the first transparent conductive layer is 70nm-120nm; the first transparent conductive layer
  • the second transparent conductive layer is a composite thin film layer laminated with doped indium oxide, zinc oxide or tin oxide or a combination thereof. The thickness of the second transparent conductive layer is 70nm-120nm.
  • the first transparent conductive layer and the second transparent conductive layer are both ITO transparent conductive films, wherein the mass percentage of indium in the first transparent conductive layer and the second transparent conductive layer is 90%, The mass percentage of tin element in the first transparent conductive layer and the second transparent conductive layer is 10%.
  • the first metal electrode is a low-temperature metal slurry electrode composed of Ag, Cu, Al, Ni or a combination thereof.
  • the first metal electrode has a thickness of 10 ⁇ m-50 ⁇ m and a width of 5 ⁇ m-50 ⁇ m.
  • the second metal electrode is a low-temperature metal slurry electrode composed of Ag, Cu, Al, Ni or a combination thereof.
  • the second metal electrode has a thickness of 10 ⁇ m-50 ⁇ m and a width of 5 ⁇ m-50 ⁇ m.
  • This application also provides a method for preparing the above-mentioned heterojunction battery, including the following steps:
  • Step 1 Provide a crystalline silicon layer
  • Step 2 Texturing the surface of the crystalline silicon layer and cleaning the surface of the crystalline silicon layer;
  • Step 3 deposit a first intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer on the front side of the crystalline silicon layer obtained in step 2, and deposit a second intrinsic amorphous silicon layer on the back side of the crystalline silicon layer obtained in step 2.
  • Step 4 Deposit a first transparent conductive layer on the N-type doped amorphous silicon layer obtained in Step 3, and deposit a second transparent conductive layer on the P-type doped amorphous silicon layer obtained in Step 3;
  • Step 5 Place a mask on the surface of the first transparent conductive layer and/or the second transparent conductive layer, and use hydrogen plasma treatment to locally clean and reduce the transparent conductive layer to obtain a local reduction area with a relatively increased local carrier concentration.
  • the width of the partial reduction zone is 5 ⁇ m-50 ⁇ m, optionally 30 ⁇ m-50 ⁇ m;
  • Step 6 Use screen printing to form a first metal electrode on the first transparent conductive layer; use screen printing to form a second metal electrode on the second transparent conductive layer; and the metal electrodes of the first metal electrode and the second metal electrode The pattern is consistent with the mask opening pattern, and the first metal electrode and/or the second metal electrode are located directly above the local reduction zone.
  • a relative local carrier concentration can be obtained. Increased local reduction layer.
  • Figure 1 is a structural diagram of a battery layer in an embodiment of the present application.
  • Figure 2 is a flow chart of a heterojunction battery preparation process in one embodiment of the present application.
  • Crystalline silicon layer 2. First intrinsic amorphous silicon layer; 3. N-type doped amorphous silicon layer; 4. First transparent conductive layer; 5. First metal electrode; 6. Second Intrinsic amorphous silicon layer; 7. P-type doped amorphous silicon layer; 8. Second transparent conductive layer; 9. Second metal electrode; 10. Local reduction layer.
  • a heterojunction cell includes a crystalline silicon layer 1, and a first intrinsic amorphous silicon layer 2, an N-type doped amorphous silicon layer 2, and an N-type doped non-crystalline silicon layer are arranged on the front side of the crystalline silicon layer 1 from the inside out.
  • the contact resistance between the transparent conductive layer and the metal electrode is improved, and the battery filling factor and photoelectric conversion efficiency are improved.
  • the width of the local reduction layer 10 is 5 ⁇ m-50 ⁇ m.
  • the crystalline silicon layer 1 is N-type doped monocrystalline silicon, N-type doped quasi-monocrystalline silicon, P-type doped quasi-monocrystalline silicon, or P-type doped quasi-monocrystalline silicon, and its thickness is 50 ⁇ m - 250 ⁇ m.
  • the first intrinsic amorphous silicon layer is a composite film layer of undoped amorphous silicon, amorphous silicon oxide, amorphous silicon carbide semiconductor film or a combination thereof, and its thickness is 2 nm. -8nm.
  • the N-type doped amorphous silicon layer is N-type doped amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon, microcrystalline silicon oxide, microcrystalline silicon carbide semiconductor
  • the thickness of the film or composite film layer laminated by the film or combination thereof is 4nm-30nm.
  • the P-type doped amorphous silicon layer is P-type doped amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon, microcrystalline silicon oxide, microcrystalline silicon carbide Semiconductor film or composite film layer laminated by a combination thereof, the thickness of the P-type doped amorphous silicon layer is 4nm-30nm.
  • the first transparent conductive layer is a composite thin film layer laminated with doped indium oxide, zinc oxide or tin oxide or a combination thereof, with a thickness of 70nm-120nm;
  • the second transparent conductive layer is The thickness of the composite thin film layer laminated by doped indium oxide, zinc oxide or tin oxide or their combination is 70nm-120nm.
  • the first transparent conductive layer and the second transparent conductive layer are both ITO (indium tin oxide) transparent conductive films, and the mass percentage of indium element is 90%, and the mass percentage of tin element is 90%. 10%.
  • the first metal electrode is a low-temperature metal slurry electrode composed of Ag, Cu, Al, Ni or a combination thereof, with a thickness of 10 ⁇ m-50 ⁇ m and a width of 5 ⁇ m-50 ⁇ m;
  • the second metal electrode is a low-temperature metal slurry electrode composed of Ag, Cu, Al, Ni or a combination thereof.
  • the metal electrode is a low-temperature metal slurry electrode composed of Ag, Cu, Al, Ni or a combination thereof, with a thickness of 10 ⁇ m-50 ⁇ m and a width of 5 ⁇ m-50 ⁇ m.
  • This embodiment also provides a method for preparing the above-mentioned heterojunction battery, including the following steps.
  • Step S101 Provide a crystalline silicon layer, including an N-type Czochralski single crystal silicon wafer, with a thickness of 50 ⁇ m-250 ⁇ m, a resistivity of 3 ⁇ cm, and a minority carrier lifetime of 2000 ⁇ s.
  • Step S102 Texturing and cleaning the surface of the crystalline silicon layer, including using a mixed solution of NaOH and texturing additives with a mass percentage of 2% for silicon wafer texturing. Then use RCA standard cleaning methods to clean the surface of the silicon wafer to remove surface contamination and impurities. Next, use a 2% mass percent hydrofluoric acid solution to remove the surface oxide layer.
  • Step S103 Use the PECVD (Plasma Enhanced Chemical Vapor Deposition, Chinese full name: plasma enhanced chemical vapor deposition method) process to deposit the first intrinsic amorphous silicon with a thickness of 2nm-8nm on the front side of the crystalline silicon layer, in which the reaction gas is SiH 4 and H 2 , where the flow ratio of H 2 to SiH 4 is 5:1, the power density of the PECVD equipment is 20mW/cm 2 , the pressure is 70Pa, and the substrate temperature is 200°C; then in the first intrinsic amorphous An N-type doped amorphous silicon layer with a thickness of 4nm-30nm is deposited on silicon, in which the reaction gases are SiH 4 , H 2 and PH 3 , the flow ratio of H 2 to SiH 4 is 5:1, and the flow ratio of PH 3 to SiH 4 The flow ratio is 0.02, the power density of the PECVD equipment is 15mW/cm 2 , the pressure is 80Pa, and the substrate temperature is
  • the PECVD process is used to deposit the second intrinsic amorphous silicon with a thickness of 2nm-8nm on the front side of the crystalline silicon layer.
  • the reaction gases are SiH 4 and H 2 , where the flow ratio of H 2 to SiH 4 is 5.
  • the power density of the PECVD equipment is 20mW/cm 2 , the pressure is 70Pa, and the substrate temperature is 200°C; then a P-type doped amorphous silicon layer with a thickness of 4nm-30nm is deposited on the second intrinsic amorphous silicon, and the reaction gases are SiH 4 and B 2 H 6 and H 2 , where the flow ratio of H 2 to SiH 4 is 4, the flow ratio of B 2 H 6 to SiH 4 is 0.04, the power density of the PECVD equipment is 15mW/cm 2 , the pressure is 60Pa, and the substrate temperature is 200°C.
  • Step S104 Use the PVD (Physical Vapor Deposition) method to deposit a first transparent conductive layer with a thickness of 70nm-120nm on the N-type doped amorphous silicon layer, and deposit a thickness of 70nm-120nm on the P-type doped amorphous silicon layer.
  • the second transparent conductive layer wherein the first transparent conductive layer and the second transparent conductive layer are both ITO transparent conductive films, the mass percentage of indium element in ITO is 90%, and the mass percentage of tin element is 10%.
  • the PVD equipment is filled with Ar and O 2 , the flow ratio of O 2 to Ar is 0.025, the pressure is 0.5 Pa, and the substrate temperature is room temperature.
  • Step S105 Place a mask on the surface of the first transparent conductive layer and/or the second transparent conductive layer.
  • the mask opening pattern is consistent with the metal electrode pattern.
  • Hydrogen plasma treatment is used to partially clean and restore the transparent conductive layer.
  • Step S106 Use screen printing to form a first metal electrode on the first transparent conductive layer; use screen printing to form a second metal electrode on the second transparent conductive layer; and the metal electrodes of the first metal electrode and the second metal electrode The pattern is consistent with the mask opening pattern, and the first metal electrode and/or the metal electrode is located directly above the local reduction zone.
  • a mask is placed on the surface of the transparent conductive layer.
  • the opening pattern of the mask is consistent with the metal electrode pattern, and then hydrogen plasma treatment is used to locally clean and restore the transparent conductive layer to obtain a local carrier.
  • the surface of the crystalline silicon layer is the front surface of the crystalline silicon layer, the back surface of the crystalline silicon layer, or a combination thereof.
  • the texturing additive is a texturing additive commonly used in the art.
  • the texturing additive includes an alkaline mixture, including alkali, surfactant, weak acid salt, water and other ingredients.
  • the mask plate is selected from common mask plates in the art. In some embodiments of the present application, the mask plate is selected from a mask plate of a resin substrate or a mask plate of a glass substrate.
  • the textured crystalline silicon layer is cleaned using RCA standard cleaning methods.
  • the RCA standard cleaning method includes the following steps.
  • Pre-cleaning Mix hydrogen peroxide, ammonia and deionized water to remove residual organic matter on the surface of the silicon wafer.
  • Alkali polishing Mix potassium hydroxide and deionized water, and use potassium hydroxide to dissolve the surface layer on both sides of the silicon wafer, totaling 5 ⁇ m-25 ⁇ m.
  • Texturing Mix potassium hydroxide, texturing additives and deionized water to form a surface covered with pyramids.
  • Post-cleaning Mix hydrogen peroxide, hydrochloric acid and deionized water to remove residual metal impurities on the surface of the silicon wafer.
  • Hydrophobicity Mix hydrofluoric acid and deionized water, and use hydrofluoric acid to remove silicon oxide on the surface of the silicon wafer to form a hydrophobic layer on the surface of the silicon wafer.
  • step 6 use hot air to dry the silicon wafer.
  • a method for preparing a heterojunction battery includes the following steps.
  • Step 1 Provide a crystalline silicon layer; use an N-type Czochralski monocrystalline silicon wafer with a thickness of 150 ⁇ m, a resistivity of 3 ⁇ cm, and a minority carrier lifetime of 2000 ⁇ s.
  • Step 2 Texture the surface of the crystalline silicon layer and clean the surface of the crystalline silicon layer; use a mixed solution of NaOH and texturing additives to texturize the silicon wafer. Then use RCA standard cleaning methods to clean the surface of the silicon wafer to remove surface contamination and impurities. Next, use hydrofluoric acid solution to remove the surface oxide layer.
  • Step 3 Use the PECVD process to deposit the first intrinsic amorphous silicon with a thickness of 6 nm on the front side of the crystalline silicon layer.
  • the reaction gases are SiH 4 and H 2 , where the flow ratio of H 2 to SiH 4 is 5.
  • the power density of the PECVD equipment is 20mW/cm 2 , the pressure is 70Pa, and the substrate temperature is 200°C; then an N-type doped amorphous silicon layer with a thickness of 6nm is deposited on the first intrinsic amorphous silicon; the reaction gas is SiH 4. H 2 and PH 3.
  • the flow ratio of H 2 to SiH 4 is 5, and the flow ratio of PH 3 to SiH 4 is 0.02.
  • the power density of the PECVD equipment is 15mW/cm 2 , the pressure is 80Pa, and the substrate temperature is 200°C.
  • the PECVD process is used to deposit the second intrinsic amorphous silicon with a thickness of 7 nm on the front side of the crystalline silicon layer.
  • the reaction gases are SiH 4 and H 2 , where the flow ratio of H 2 to SiH 4 is 5.
  • the power density of the PECVD equipment is 20mW/cm 2 , the pressure is 70Pa, and the substrate temperature is 200°C; then a P-type doped amorphous silicon layer with a thickness of 10nm is deposited on the second intrinsic amorphous silicon, and the reaction gas is SiH 4.
  • B 2 H 6 and H 2 where the flow ratio of H 2 to SiH 4 is 4, and the flow ratio of B 2 H 6 to SiH 4 is 0.04.
  • the power density of the PECVD equipment is 15mW/cm 2 , the pressure is 60Pa, and the substrate temperature is 200°C.
  • Step 4 Use the PVD method to deposit a first transparent conductive layer with a thickness of 75 nm on the N-type doped amorphous silicon layer, and deposit a second transparent conductive layer with a thickness of 75 nm on the P-type doped amorphous silicon layer; wherein the The first transparent conductive layer and the second transparent conductive layer are both ITO transparent conductive films.
  • the mass percentage of indium element in ITO is 90%, and the mass percentage of tin element is 10%.
  • the PVD equipment is filled with Ar and O 2 , the flow ratio of O 2 to Ar is 0.025, the pressure is 0.5 Pa, and the substrate temperature is room temperature.
  • Step 5 Place a mask on the surface of the first transparent conductive layer and the second transparent conductive layer respectively.
  • the mask opening pattern is consistent with the metal electrode pattern.
  • Step 6 Use screen printing to form a first metal electrode on the first transparent conductive layer; use screen printing to form a second metal electrode on the second transparent conductive layer; and the metal electrodes of the first metal electrode and the second metal electrode The pattern is consistent with the mask opening pattern, and the first metal electrode and the second metal electrode are located directly above the local reduction zone.
  • a method for preparing a heterojunction battery includes the following steps.
  • Step 1 Provide a crystalline silicon layer; use an N-type Czochralski monocrystalline silicon wafer with a thickness of 100 ⁇ m, a resistivity of 3 ⁇ cm, and a minority carrier lifetime of 2000 ⁇ s.
  • Step 2 Texture the surface of the crystalline silicon layer and clean the surface of the crystalline silicon layer; use a mixed solution of NaOH and texturing additives to texturize the silicon wafer. Then use RCA standard cleaning methods to clean the surface of the silicon wafer to remove surface contamination and impurities. Next, use hydrofluoric acid solution to remove the surface oxide layer.
  • Step 3 Use the PECVD process to deposit the first intrinsic amorphous silicon with a thickness of 5 nm on the front side of the crystalline silicon layer.
  • the reaction gases are SiH 4 and H 2 , where the flow ratio of H 2 to SiH 4 is 5.
  • the power density of the PECVD equipment is 20mW/cm 2 , the pressure is 70Pa, and the substrate temperature is 200°C; then an N-type doped amorphous silicon layer with a thickness of 8nm is deposited on the first intrinsic amorphous silicon; the reaction gas is SiH 4. H 2 and PH 3.
  • the flow ratio of H 2 to SiH 4 is 5, and the flow ratio of PH 3 to SiH 4 is 0.02.
  • the power density of the PECVD equipment is 15mW/cm 2 , the pressure is 80Pa, and the substrate temperature is 200°C.
  • the PECVD process is used to deposit the second intrinsic amorphous silicon with a thickness of 7 nm on the front side of the crystalline silicon layer.
  • the reaction gases are SiH 4 and H 2 , where the flow ratio of H 2 to SiH 4 is 5.
  • the power density of the PECVD equipment is 20mW/cm 2 , the pressure is 70Pa, and the substrate temperature is 200°C; then a P-type doped amorphous silicon layer with a thickness of 10nm is deposited on the second intrinsic amorphous silicon, and the reaction gas is SiH 4.
  • B 2 H 6 and H 2 where the flow ratio of H 2 to SiH 4 is 4, and the flow ratio of B 2 H 6 to SiH 4 is 0.04.
  • the power density of the PECVD equipment is 15mW/cm 2 , the pressure is 60Pa, and the substrate temperature is 200°C.
  • Step 4 Use the PVD method to deposit a first transparent conductive layer with a thickness of 100 nm on the N-type doped amorphous silicon layer, and deposit a second transparent conductive layer with a thickness of 100 nm on the P-type doped amorphous silicon layer; wherein the The first transparent conductive layer and the second transparent conductive layer are both ITO transparent conductive films.
  • the mass percentage of indium element in ITO is 90%, and the mass percentage of tin element is 10%.
  • the PVD equipment is filled with Ar and O 2 , the flow ratio of O 2 to Ar is 0.025, the pressure is 0.5 Pa, and the substrate temperature is room temperature.
  • Step 5 Place a mask on the surface of the first transparent conductive layer.
  • the mask opening pattern is consistent with the metal electrode pattern.
  • Hydrogen plasma treatment is used to locally clean and restore the transparent conductive layer to obtain a relative increase in local carrier concentration.
  • a large local reduction zone, the width of the local reduction zone is 30 ⁇ m; the carrier concentration of the local reduction layer is higher than that of the first transparent conductive layer.
  • Step 6 Use screen printing to form a first metal electrode on the first transparent conductive layer; use screen printing to form a second metal electrode on the second transparent conductive layer; and the metal electrode pattern of the first metal electrode is consistent with the above
  • the opening pattern of the mask plate is consistent with that of the first metal electrode, and the first metal electrode is located directly above the local reduction area.
  • a method for preparing a heterojunction battery includes the following steps.
  • Step 1 Provide a crystalline silicon layer; use a P-type Czochralski monocrystalline silicon wafer with a thickness of 150 ⁇ m, a resistivity of 3 ⁇ cm, and a minority carrier lifetime of 2000 ⁇ s.
  • Step 2 Texture the surface of the crystalline silicon layer and clean the surface of the crystalline silicon layer; use a mixed solution of NaOH and texturing additives to texturize the silicon wafer. Then use RCA standard cleaning methods to clean the surface of the silicon wafer to remove surface contamination and impurities. Next, use hydrofluoric acid solution to remove the surface oxide layer.
  • Step 3 Use the PECVD process to deposit the first intrinsic amorphous silicon with a thickness of 5 nm on the front side of the crystalline silicon layer.
  • the reaction gases are SiH 4 and H 2 , where the flow ratio of H 2 to SiH 4 is 5.
  • the power density of the PECVD equipment is 20mW/cm 2 , the pressure is 70Pa, and the substrate temperature is 200°C; then an N-type doped amorphous silicon layer with a thickness of 8nm is deposited on the first intrinsic amorphous silicon; the reaction gas is SiH 4. H 2 and PH 3.
  • the flow ratio of H 2 to SiH 4 is 5, and the flow ratio of PH 3 to SiH 4 is 0.02.
  • the power density of the PECVD equipment is 15mW/cm 2 , the pressure is 80Pa, and the substrate temperature is 200°C.
  • the PECVD process is used to deposit the second intrinsic amorphous silicon with a thickness of 7 nm on the front side of the crystalline silicon layer.
  • the reaction gases are SiH 4 and H 2 , where the flow ratio of H 2 to SiH 4 is 5.
  • the power density of the PECVD equipment is 20mW/cm 2 , the pressure is 70Pa, and the substrate temperature is 200°C; then a P-type doped amorphous silicon layer with a thickness of 10nm is deposited on the second intrinsic amorphous silicon, and the reaction gas is SiH 4.
  • B 2 H 6 and H 2 where the flow ratio of H 2 to SiH 4 is 4, and the flow ratio of B 2 H 6 to SiH 4 is 0.04.
  • the power density of the PECVD equipment is 15mW/cm 2 , the pressure is 60Pa, and the substrate temperature is 200°C.
  • Step 4 Use the PVD method to deposit a first transparent conductive layer with a thickness of 100 nm on the N-type doped amorphous silicon layer, and deposit a second transparent conductive layer with a thickness of 100 nm on the P-type doped amorphous silicon layer; wherein the The first transparent conductive layer and the second transparent conductive layer are both ITO transparent conductive films.
  • the mass percentage of indium element in ITO is 90%, and the mass percentage of tin element is 10%.
  • the PVD equipment is filled with Ar and O 2 , the flow ratio of O 2 to Ar is 0.025, the pressure is 0.5 Pa, and the substrate temperature is room temperature.
  • Step 5 Place a mask on the surface of the second transparent conductive layer.
  • the mask opening pattern is consistent with the metal electrode pattern.
  • Hydrogen plasma treatment is used to locally clean and restore the transparent conductive layer to obtain a relative increase in local carrier concentration.
  • a large local reduction zone, the width of the local reduction zone is 30 ⁇ m; the carrier concentration of the local reduction layer is higher than that of the second transparent conductive layer.
  • Step 6 Use screen printing to form a first metal electrode on the first transparent conductive layer; use screen printing to form a second metal electrode on the second transparent conductive layer; and the metal electrode pattern of the second metal electrode is consistent with the above
  • the opening pattern of the mask plate is consistent with that of the second metal electrode, and the second metal electrode is located directly above the local reduction area.
  • the mask opening pattern is consistent with the metal electrode pattern, and then using hydrogen plasma treatment to locally clean and restore the transparent conductive layer to obtain a relative increase in local carrier concentration. Large local reduction layer.

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Abstract

一种异质结电池及其制备方法。异质结电池包括晶体硅层(1)，晶体硅层(1)正面从内向外依次设置第一本征非晶硅层(2)、N型掺杂非晶硅层(3)、第一透明导电层(4)和第一金属电极(5)，背面从内向外依次设置第二本征非晶硅层(6)、P型掺杂非晶硅层(7)、第二透明导电层(8)和第二金属电极(9)，第一透明导电层(4)表面位于第一金属电极(5)下位置处和/或第二透明导电层(8)表面位于第二金属电极(9)下位置处形成有局部还原层(10)。

Description

一种异质结电池及其制备方法
相关申请
本申请要求2022年5月16日申请的，申请号为202210530719.0，发明名称为“一种异质结电池及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及异质结电池领域，具体而言，涉及一种异质结电池及其制备方法。
背景技术
单晶硅异质结太阳电池转换效率高，被光伏行业公认为下一代大规模产业化关键技术之一。
硅基异质结太阳能电池一般采用双面金字塔绒面结构的N型单晶硅片制作形成，在硅片正面沉积本征非晶硅层和N型掺杂非晶硅层，在硅片背面沉积本征非晶硅层与P型掺杂非晶硅层，之后在硅片两面分别形成透明导电膜及金属电极。
在相关技术中，透明导电层易受空气中水汽、氧气、有机物吸附等影响，导致透明导电层与低温浆料之间接触性能变差，接触电阻增大，最终导致电池效率偏低。
发明内容
根据本申请的各种实施例，提供一种异质结电池，包括晶体硅层，晶体 硅层正面从内向外依次设置第一本征非晶硅层、N型掺杂非晶硅层、第一透明导电层、第一金属电极，晶体硅层背面从内向外依次设置第二本征非晶硅层、P型掺杂非晶硅层、第二透明导电层、第二金属电极。所述第一透明导电层表面位于所述第一金属电极下位置处和/或所述第二透明导电层表面位于所述第二金属电极下位置处形成有局部还原层，所述局部还原层载流子浓度高于第一透明导电层和/或第二透明导电层。
通过在金属电极下方的透明导电层表面设置局部还原层，从而改善透明导电层与金属电极之间的接触电阻，并且提高了电池填充因子和光电转换效率。
在一些实施例中，所述局部还原层宽度为5μm-50μm。
在一些实施例中，所述晶体硅层为N型掺杂单晶硅、N型掺杂类单晶硅、P型掺杂单晶硅或P型掺杂类单晶硅，所述晶体硅层的厚度为50μm-250μm。
在一些实施例中，所述第一本征非晶硅层为未掺杂的非晶硅、非晶氧化硅、非晶碳化硅半导体薄膜或其组合叠合的复合薄膜层，第一本征非晶硅层的厚度为2nm-8nm。
在一些实施例中，所述N型掺杂非晶硅层为N型掺杂的非晶硅、非晶氧化硅、非晶碳化硅、微晶硅、微晶氧化硅、微晶碳化硅半导体薄膜或其组合叠合的复合薄膜层，N型掺杂非晶硅层的厚度为4nm-30nm。
在一些实施例中，所述P型掺杂非晶硅层，为P型掺杂的非晶硅、非晶氧化硅、非晶碳化硅、微晶硅、微晶氧化硅、微晶碳化硅半导体薄膜或其组合叠合的复合薄膜层，P型掺杂非晶硅层的厚度为4nm-30nm。
在一些实施例中，所述第一透明导电层为掺杂的氧化铟、氧化锌或氧化锡或其组合叠合的复合薄膜层，第一透明导电层的厚度为70nm-120nm；所 述第二透明导电层为掺杂的氧化铟、氧化锌或氧化锡或其组合叠合的复合薄膜层，第二透明导电层的厚度为70nm-120nm。
在一些实施例中，所述第一透明导电层和所述第二透明导电层均为ITO透明导电薄膜，其中第一透明导电层和第二透明导电层的铟元素的质量百分比为90％，第一透明导电层和第二透明导电层的锡元素的质量百分比为10％。
在一些实施例中，所述第一金属电极为含Ag、Cu、Al、Ni或其组合复合构成的低温金属浆料电极，第一金属电极的厚度为10μm-50μm，宽度为5μm-50μm。所述第二金属电极为含Ag、Cu、Al、Ni或其组合复合构成的低温金属浆料电极，第二金属电极的厚度为10μm-50μm，宽度为5μm-50μm。
本申请还提供了一种上述异质结电池的制备方法，包括如下步骤：
步骤一，提供晶体硅层；
步骤二，在晶体硅层的表面制绒以及清洗晶体硅层的表面；
步骤三，在步骤二中得到的晶体硅层正面依次沉积第一本征非晶硅和N型掺杂非晶硅层，以及在在步骤二中得到的晶体硅层背面依次沉积第二本征非晶硅和P型掺杂非晶硅层；
步骤四，在步骤三中获得的N型掺杂非晶硅层上沉积第一透明导电层，以及在步骤三中获得的P型掺杂非晶硅层上沉积第二透明导电层；
步骤五，在第一透明导电层和/或第二透明导电层表面放置掩膜板，采用氢等离子处理对透明导电层进行局部清洁与还原，获得局部载流子浓度相对增大的局部还原区，所述局部还原区宽度在5μm-50μm，可选为30μm-50μm；
步骤六，在第一透明导电层上利用丝网印刷形成第一金属电极；在第二透明导电层上利用丝网印刷形成第二金属电极；且第一金属电极和第二金属电极的金属电极图型与所述掩膜板开口图型与一致，所述第一金属电极和/或 所述第二金属电极位于所述局部还原区正上方位置。
在一些实施例中，通过在透明导电层表面放置开口图型与金属电极图型一致的掩膜板，然后采用氢等离子处理对透明导电层进行局部清洁与还原，可以获得局部载流子浓度相对增大的局部还原层。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施方式的技术方案，下面将对实施方式中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本申请的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1是本申请一个实施例中的电池层结构图。
图2是本申请一个实施例中的异质结电池制备工艺流程图。
图中，1、晶体硅层；2、第一本征非晶硅层；3、N型掺杂非晶硅层；4、第一透明导电层；5、第一金属电极；6、第二本征非晶硅层；7、P型掺杂非晶硅层；8、第二透明导电层；9、第二金属电极；10、局部还原层。
具体实施方式
为使本申请实施方式的目的、技术方案和优点更加清楚，下面将结合本申请实施方式中的附图，对本申请实施方式中的技术方案进行清楚、完整地描述，显然，所描述的实施方式是本申请一部分实施方式，而不是全部的实施方式。基于本申请中的实施方式，本领域普通技术人员在没有做出创造性 劳动前提下所获得的所有其他实施方式，都属于本申请保护的范围。因此，以下对在附图中提供的本申请的实施方式的详细描述并非旨在限制要求保护的本申请的范围，而是仅仅表示本申请的选定实施方式。基于本申请中的实施方式，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施方式，都属于本申请保护的范围。
本实施方式通过在低温金属浆料电极下方透明导电层表面形成局部还原区，增加透明导电层局部载流子浓度，降低与低温金属浆料电极之间的界面势垒高度，得到较低的接触电阻；另外，经过局部处理的表面更加清洁，不会受到水汽、氧气、有机物吸附的影响。如图1所示，在本申请的一些实施例中，异质结电池包括晶体硅层1，晶体硅层1正面从内向外依次设置第一本征非晶硅层2、N型掺杂非晶硅层3、第一透明导电层4、第一金属电极5，晶体硅层1背面从内向外依次设置第二本征非晶硅层6、P型掺杂非晶硅层7、第二透明导电层8、第二金属电极9，其中：所述第一透明导电层4表面位于所述第一金属电极5下位置处和/或所述第二透明导电层8表面位于所述第二金属电极9下位置处形成有局部还原层10，所述局部还原层10载流子浓度高于第一透明导电层和/或第二透明导电层。
通过在金属电极下方的透明导电层表面设置局部还原层，改善透明导电层与金属电极之间的接触电阻，提高了电池填充因子和光电转换效率。
在一些实施例中，局部还原层10宽度为5μm-50μm。
在一些实施例中，晶体硅层1为N型掺杂单晶硅、N型掺杂类单晶硅、P型掺杂单晶硅或P型掺杂类单晶硅，其厚度为50μm-250μm。
在一些实施例中，所述第一本征非晶硅层为未掺杂的非晶硅、非晶氧化硅、非晶碳化硅半导体薄膜或其组合叠合的复合薄膜层，其厚度为2nm-8nm。
在一些实施例中，所述N型掺杂非晶硅层为N型掺杂的非晶硅、非晶氧化硅、非晶碳化硅、微晶硅、微晶氧化硅、微晶碳化硅半导体薄膜或其组合叠合的复合薄膜层，其厚度为4nm-30nm。
在一些实施例中，所述P型掺杂非晶硅层，为P型掺杂的非晶硅、非晶氧化硅、非晶碳化硅、微晶硅、微晶氧化硅、微晶碳化硅半导体薄膜或其组合叠合的复合薄膜层，P型掺杂非晶硅层的厚度为4nm-30nm。
在一些实施例中，所述第一透明导电层为掺杂的氧化铟、氧化锌或氧化锡或其组合叠合的复合薄膜层，其厚度为70nm-120nm；所述第二透明导电层为掺杂的氧化铟、氧化锌或氧化锡或其组合叠合的复合薄膜层，其厚度为70nm-120nm。
在一些实施例中，所述第一透明导电层和所述第二透明导电层均为ITO(氧化铟锡)透明导电薄膜，且其中铟元素的质量百分比为90％，锡元素的质量百分比为10％。
在一些实施例中，所述第一金属电极为含Ag、Cu、Al、Ni或其组合复合构成的低温金属浆料电极，其厚度为10μm-50μm，宽度为5μm-50μm；所述第二金属电极为含Ag、Cu、Al、Ni或其组合复合构成的低温金属浆料电极，其厚度为10μm-50μm，宽度为5μm-50μm。
本实施方式还提供了一种上述异质结电池的制备方法，包括如下步骤。
步骤S101：提供晶体硅层，包括采用N型直拉单晶硅片，其厚度为50μm-250μm，电阻率为3Ω·cm，少数载流子寿命2000μs。
步骤S102：在所述晶体硅层的表面制绒和清洗所述晶体硅层的表面，包括使用质量百分比为2％的NaOH和制绒添加剂混合溶液进行硅片制绒。然后采用RCA标准清洗方法对硅片进行表面清洗，清除表面污染杂质。接下来， 用质量百分比为2％的氢氟酸溶液去除表面氧化层。
步骤S103：采用PECVD(Plasma Enhanced Chemical Vapor Deposition，中文全称：等离子体增强的化学气相沉积法)工艺在晶体硅层正面沉积厚度为2nm-8nm的第一本征非晶硅，其中反应气体为SiH 4和H 2，其中H 2与SiH 4的流量比值为5:1，PECVD设备的电源功率密度为20mW/cm 2，压力为70Pa，衬底温度为200℃；然后在第一本征非晶硅上沉积厚度为4nm-30nm的N型掺杂非晶硅层，其中反应气体为SiH 4、H 2和PH 3，H 2与SiH 4的流量比值为5:1，PH 3与SiH 4的流量比值为0.02，PECVD设备的电源功率密度为15mW/cm 2，压力为80Pa，衬底温度为200℃。采用PECVD工艺在晶体硅层正面沉积厚度为2nm-8nm的第二本征非晶硅，反应气体为SiH 4和H 2，其中H 2与SiH 4的流量比值为5，PECVD设备的电源功率密度为20mW/cm 2，压力为70Pa，衬底温度为200℃；然后在第二本征非晶硅沉积厚度为4nm-30nm的P型掺杂非晶硅层，反应气体为SiH 4、B 2H 6和H 2，其中H 2与SiH 4的流量比值为4，B 2H 6与SiH 4的流量比值为0.04，PECVD设备的电源功率密度为15mW/cm 2，压力为60Pa，衬底温度为200℃。
步骤S104：采用PVD(Physical Vapor Deposition)方法在N型掺杂非晶硅层上沉积厚度为70nm-120nm的第一透明导电层，在P型掺杂非晶硅层上沉积厚度为70nm-120nm的第二透明导电层；其中第一透明导电层和第二透明导电层均为ITO透明导电薄膜，ITO中的铟元素的质量百分比为90％，锡元素的质量百分比为10％。PVD设备中充入有Ar和O 2，O 2与Ar流量比值0.025，压力0.5Pa，衬底温度为室温。
步骤S105：在第一透明导电层和/或第二透明导电层表面放置掩膜板，掩膜板开口图型与金属电极图型一致，采用氢等离子处理对透明导电层进行局 部清洁与还原，获得局部载流子浓度相对增大的局部还原区，所述局部还原区宽度在5μm-50μm，可选为30μm-50μm；所述局部还原层载流子浓度高于第一透明导电层和/或第二透明导电层。
步骤S106：在第一透明导电层上利用丝网印刷形成第一金属电极；在第二透明导电层上利用丝网印刷形成第二金属电极；且第一金属电极和第二金属电极的金属电极图型与所述掩膜板开口图型与一致，所述第一金属电极和/或所述金属电极位于所述局部还原区正上方位置。
本申请的一些实施例中，通过在透明导电层表面放置掩膜板，掩膜板开口图型与金属电极图型一致，然后采用氢等离子处理对透明导电层进行局部清洁与还原，获得局部载流子浓度相对增大的局部还原层。
本申请中，所述晶体硅层的表面为所述晶体硅层的正面、所述晶体硅层的反面或其组合。
本申请的一些实施例中，制绒添加剂为本领域常用的制绒添加剂。本申请的一些实施例中，制绒添包括碱性混合物，包括碱、表面活性剂、弱酸盐、水等成分。
本申请的一些实施例中，掩膜板选自本领域常见的掩膜板。本申请的一些实施例中，掩膜板选自树脂基板的掩膜板或玻璃基板的掩膜板。
本申请的一些实施例中，采用RCA标准清洗方法清洗制绒后的晶体硅层。RCA标准清洗方法包括以下步骤。
(1)前清洗：将双氧水、氨水和去离子水混合，用于清除硅片表面残留的有机物。
(2)碱抛：将氢氧化钾与去离子水混合，用氢氧化钾溶解硅片双面表层共5μm-25μm。
(3)制绒：将氢氧化钾、制绒添加剂与去离子水混合，形成布满金字塔的表面。
(4)圆化：将氢氟酸、臭氧与去离子水混合，削去金字塔尖峰和谷底，使其圆化。
(5)后清洗：将双氧水、盐酸和去离子水混合，用于清除硅片表面残留的金属杂质。
(6)疏水：将氢氟酸和去离子水混合，利用氢氟酸去除硅片表面氧化硅，使硅片表面形成疏水层。
(7)泡洗：在步骤1-6之后都要用去离子水进行浸泡和冲洗。
(8)烘干：在第6步之后，使用热风将硅片烘干。
实施例一：
一种异质结电池的制备方法，包括如下步骤。
步骤一，提供晶体硅层；采用N型直拉单晶硅片，其厚度为150μm，电阻率为3Ω·cm，少数载流子寿命2000μs。
步骤二，在晶体硅层表面制绒，并清洗晶体硅层表面；使用NaOH和制绒添加剂混合溶液进行硅片制绒。然后采用RCA标准清洗方法对硅片进行表面清洗，清除表面污染杂质。接下来，用氢氟酸溶液去除表面氧化层。
步骤三，采用PECVD工艺在晶体硅层正面沉积厚度为6nm的第一本征非晶硅，反应气体为SiH 4和H 2，其中H 2与SiH 4的流量比值为5。PECVD设备的电源功率密度为20mW/cm 2，压力为70Pa，衬底温度为200℃；然后在第一本征非晶硅沉积厚度为6nm的N型掺杂非晶硅层；反应气体为SiH 4、H 2和PH 3，H 2与SiH 4的流量比值为5，PH 3与SiH 4的流量比值为0.02。PECVD设备的电源功率密度为15mW/cm 2，压力为80Pa，衬底温度为200℃。
采用PECVD工艺在晶体硅层正面沉积厚度为7nm的第二本征非晶硅，反应气体为SiH 4和H 2，其中H 2与SiH 4的流量比值为5。PECVD设备的电源功率密度为20mW/cm 2，压力为70Pa，衬底温度为200℃；然后在第二本征非晶硅沉积厚度为10nm的P型掺杂非晶硅层，反应气体为SiH 4、B 2H 6和H 2，其中H 2与SiH 4的流量比值为4，B 2H 6与SiH 4的流量比值为0.04。PECVD设备的电源功率密度为15mW/cm 2，压力为60Pa，衬底温度为200℃。
步骤四，采用PVD方法在N型掺杂非晶硅层上沉积厚度为75nm的第一透明导电层，在P型掺杂非晶硅层上沉积厚度为75nm的第二透明导电层；其中第一透明导电层和第二透明导电层均为ITO透明导电薄膜，ITO中的铟元素的质量百分比为90％，锡元素的质量百分比为10％。PVD设备中充入有Ar和O 2，O 2与Ar流量比值0.025，压力0.5Pa，衬底温度为室温。
步骤五，在第一透明导电层和第二透明导电层表面分别放置掩膜板，掩膜板开口图型与金属电极图型一致，采用氢等离子处理对透明导电层进行局部清洁与还原，获得局部载流子浓度相对增大的局部还原区，所述局部还原区宽度在30μm；所述局部还原层载流子浓度高于第一透明导电层和第二透明导电层。
步骤六，在第一透明导电层上利用丝网印刷形成第一金属电极；在第二透明导电层上利用丝网印刷形成第二金属电极；且第一金属电极和第二金属电极的金属电极图型与所述掩膜板开口图型与一致，所述第一金属电极和所述第二金属电极位于所述局部还原区正上方位置。
实施例二：
一种异质结电池的制备方法，包括如下步骤。
步骤一，提供晶体硅层；采用N型直拉类单晶硅片，其厚度为100μm， 电阻率为3Ω·cm，少数载流子寿命2000μs。
步骤二，在晶体硅层表面制绒并清洗晶体硅层表面；使用NaOH和制绒添加剂混合溶液进行硅片制绒。然后采用RCA标准清洗方法对硅片进行表面清洗，清除表面污染杂质。接下来，用氢氟酸溶液去除表面氧化层。
步骤三，采用PECVD工艺在晶体硅层正面沉积厚度为5nm的第一本征非晶硅，反应气体为SiH 4和H 2，其中H 2与SiH 4的流量比值为5。PECVD设备的电源功率密度为20mW/cm 2，压力为70Pa，衬底温度为200℃；然后在第一本征非晶硅沉积厚度为8nm的N型掺杂非晶硅层；反应气体为SiH 4、H 2和PH 3，H 2与SiH 4的流量比值为5，PH 3与SiH 4的流量比值为0.02。PECVD设备的电源功率密度为15mW/cm 2，压力为80Pa，衬底温度为200℃。
采用PECVD工艺在晶体硅层正面沉积厚度为7nm的第二本征非晶硅，反应气体为SiH 4和H 2，其中H 2与SiH 4的流量比值为5。PECVD设备的电源功率密度为20mW/cm 2，压力为70Pa，衬底温度为200℃；然后在第二本征非晶硅沉积厚度为10nm的P型掺杂非晶硅层，反应气体为SiH 4、B 2H 6和H 2，其中H 2与SiH 4的流量比值为4，B 2H 6与SiH 4的流量比值为0.04。PECVD设备的电源功率密度为15mW/cm 2，压力为60Pa，衬底温度为200℃。
步骤四，采用PVD方法在N型掺杂非晶硅层上沉积厚度为100nm的第一透明导电层，在P型掺杂非晶硅层上沉积厚度为100nm的第二透明导电层；其中第一透明导电层和第二透明导电层均为ITO透明导电薄膜，ITO中的铟元素的质量百分比为90％，锡元素的质量百分比为10％。PVD设备中充入有Ar和O 2，O 2与Ar流量比值0.025，压力0.5Pa，衬底温度为室温。
步骤五，在第一透明导电层表面放置掩膜板，掩膜板开口图型与金属电极图型一致，采用氢等离子处理对透明导电层进行局部清洁与还原，获得局 部载流子浓度相对增大的局部还原区，所述局部还原区宽度在30μm；所述局部还原层载流子浓度高于第一透明导电层。
步骤六，在第一透明导电层上利用丝网印刷形成第一金属电极；在第二透明导电层上利用丝网印刷形成第二金属电极；且第一金属电极的金属电极图型与所述掩膜板开口图型与一致，所述第一金属电极位于所述局部还原区正上方位置。
实施例三：
一种异质结电池的制备方法，包括如下步骤。
步骤一，提供晶体硅层；采用P型直拉单晶硅片，其厚度为150μm，电阻率为3Ω·cm，少数载流子寿命2000μs。
步骤二，在晶体硅层表面制绒，并清洗晶体硅层表面；使用NaOH和制绒添加剂混合溶液进行硅片制绒。然后采用RCA标准清洗方法对硅片进行表面清洗，清除表面污染杂质。接下来，用氢氟酸溶液去除表面氧化层。
步骤三，采用PECVD工艺在晶体硅层正面沉积厚度为5nm的第一本征非晶硅，反应气体为SiH 4和H 2，其中H 2与SiH 4的流量比值为5。PECVD设备的电源功率密度为20mW/cm 2，压力为70Pa，衬底温度为200℃；然后在第一本征非晶硅沉积厚度为8nm的N型掺杂非晶硅层；反应气体为SiH 4、H 2和PH 3，H 2与SiH 4的流量比值为5，PH 3与SiH 4的流量比值为0.02。PECVD设备的电源功率密度为15mW/cm 2，压力为80Pa，衬底温度为200℃。
采用PECVD工艺在晶体硅层正面沉积厚度为7nm的第二本征非晶硅，反应气体为SiH 4和H 2，其中H 2与SiH 4的流量比值为5。PECVD设备的电源功率密度为20mW/cm 2，压力为70Pa，衬底温度为200℃；然后在第二本征非晶硅沉积厚度为10nm的P型掺杂非晶硅层，反应气体为SiH 4、B 2H 6和H 2， 其中H 2与SiH 4的流量比值为4，B 2H 6与SiH 4的流量比值为0.04。PECVD设备的电源功率密度为15mW/cm 2，压力为60Pa，衬底温度为200℃。
步骤四，采用PVD方法在N型掺杂非晶硅层上沉积厚度为100nm的第一透明导电层，在P型掺杂非晶硅层上沉积厚度为100nm的第二透明导电层；其中第一透明导电层和第二透明导电层均为ITO透明导电薄膜，ITO中的铟元素的质量百分比为90％，锡元素的质量百分比为10％。PVD设备中充入有Ar和O 2，O 2与Ar流量比值0.025，压力0.5Pa，衬底温度为室温。
步骤五，在第二透明导电层表面放置掩膜板，掩膜板开口图型与金属电极图型一致，采用氢等离子处理对透明导电层进行局部清洁与还原，获得局部载流子浓度相对增大的局部还原区，所述局部还原区宽度在30μm；所述局部还原层载流子浓度高于第二透明导电层。
步骤六，在第一透明导电层上利用丝网印刷形成第一金属电极；在第二透明导电层上利用丝网印刷形成第二金属电极；且第二金属电极的金属电极图型与所述掩膜板开口图型与一致，所述第二金属电极位于所述局部还原区正上方位置。
采用本申请具有以下有益效果。
(1)通过在低温金属浆料电极下方透明导电层表面形成局部还原区，增加透明导电层局部载流子浓度，降低与低温金属浆料电极之间的界面势垒高度，得到较低的接触电阻；另外，经过局部处理的表面更加清洁，不会受到水汽、氧气、有机物吸附的影响。
(2)通过在透明导电层表面放置掩膜板，掩膜板开口图型与金属电极图型一致，然后采用氢等离子处理对透明导电层进行局部清洁与还原，获得局部载流子浓度相对增大的局部还原层。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种异质结电池，其特征在于，包括晶体硅层，
    所述晶体硅层正面从内向外依次设置第一本征非晶硅层、N型掺杂非晶硅层、第一透明导电层和第一金属电极，和，
    所述晶体硅层背面从内向外依次设置第二本征非晶硅层、P型掺杂非晶硅层、第二透明导电层和第二金属电极，其中：
    所述第一透明导电层表面位于所述第一金属电极下位置处和/或所述第二透明导电层表面位于所述第二金属电极下位置处形成有局部还原层，及，
    所述局部还原层载流子浓度高于所述第一透明导电层和/或所述第二透明导电层。
  2. 根据权利要求1所述的一种异质结电池，其中，所述局部还原层的宽度为5μm-50μm。
  3. 根据权利要求1所述的一种异质结电池，其中，所述晶体硅层选自N型掺杂单晶硅、N型掺杂类单晶硅、P型掺杂单晶硅或P型掺杂类单晶硅，所述晶体硅层的厚度为50μm-250μm。
  4. 根据权利要求1所述的一种异质结电池，其中，所述第一本征非晶硅层为未掺杂的非晶硅半导体薄膜、非晶氧化硅半导体薄膜、非晶碳化硅半导体薄膜或其组合叠加形成的复合薄膜层，所述第一本征非晶硅层的厚度为2nm-8nm。
  5. 根据权利要求1所述的一种异质结电池，其中，所述N型掺杂非晶硅层为N型掺杂的非晶硅、非晶氧化硅、非晶碳化硅、微晶硅、微晶氧化硅、微晶碳化硅半导体薄膜或其组合叠合的复合薄膜层，所述N型掺杂非晶硅层的厚度为4nm-30nm。
  6. 根据权利要求1所述的一种异质结电池，其中，所述P型掺杂非晶硅层为P型掺杂的非晶硅半导体薄膜、非晶氧化硅半导体薄膜、非晶碳化硅半导体薄膜、微晶硅半导体薄膜、微晶氧化硅半导体薄膜、微晶碳化硅半导体薄膜中或其组合叠合的复合薄膜层，所述P型掺杂非晶硅层的厚度为4nm-30nm。
  7. 根据权利要求1所述的一种异质结电池，其中，所述第一透明导电层为掺杂的氧化铟、氧化锌或氧化锡或其组合叠合的复合薄膜层，所述第一透明导电层的厚度为70nm-120nm。
  8. 根据权利要求1所述的一种异质结电池，其中，所述第二透明导电层为掺杂的氧化铟、氧化锌或氧化锡或其组合叠合的复合薄膜层，所述第二透明导电层的厚度为70nm-120nm。
  9. 根据权利要求7所述的一种异质结电池，其中，所述第一透明导电层和所述第二透明导电层均为ITO透明导电薄膜，所述第一透明导电层和所述第二透明导电层中铟元素的质量百分比为90％，所述第一透明导电层和所述第二透明导电层中锡元素的质量百分比为10％。
  10. 根据权利要求1所述的一种异质结电池，其中，所述第一金属电极为含Ag、Cu、Al、Ni或其组合复合构成的低温金属浆料电极，所述第一金属电极的厚度为10μm-50μm，所述第一金属电极的宽度为5μm-50μm。
  11. 根据权利要求1所述的一种异质结电池，其中，所述第二金属电极为含Ag、Cu、Al、Ni或其组合复合构成的低温金属浆料电极，所述第二金属电极的厚度为10μm-50μm，所述第二金属电极的宽度为5μm-50μm。
  12. 一种异质结电池的制备方法，其特征在于，包括如下步骤：
    步骤一，提供晶体硅层；
    步骤二，在所述晶体硅层的表面制绒，并清洗所述晶体硅层的表面；
    步骤三，在步骤二中得到的所述晶体硅层正面依次沉积第一本征非晶硅和N型掺杂非晶硅层，以及在在步骤二中得到的所述晶体硅层背面依次沉积第二本征非晶硅和P型掺杂非晶硅层；
    步骤四，在步骤三中得到的所述N型掺杂非晶硅层上沉积第一透明导电层，以及在步骤三中得到的所述P型掺杂非晶硅层上沉积第二透明导电层；
    步骤五，在所述第一透明导电层和/或所述第二透明导电层表面放置掩膜板，采用氢等离子处理对透明导电层进行局部清洁与还原，获得局部载流子浓度相对增大的局部还原区，所述局部还原区宽度在5μm-50μm的范围内；以及，
    步骤六，在所述第一透明导电层上利用丝网印刷形成第一金属电极，在所述第二透明导电层上利用丝网印刷形成第二金属电极；其中所述第一金属电极和所述第二金属电极的金属电极图型与所述掩膜板开口图型与一致，所述第一金属电极和/或所述第二金属电极位于所述局部还原区正上方位置。
  13. 根据权利要求12所述的异质结电池的制备方法，其中，所述局部还原区宽度在30μm-50μm的范围内。
  14. 根据权利要求12所述的异质结电池的制备方法，其中，采用PECVD方法在步骤二中得到的所述晶体硅层正面依次沉积所述第一本征非晶硅和所述N型掺杂非晶硅层，以及在在步骤二中得到的所述晶体硅层背面依次沉积第二本征非晶硅和P型掺杂非晶硅层；以及，
    采用PVD方法在步骤三中得到的所述N型掺杂非晶硅层上沉积第一透明导电层，以及在步骤三中得到的所述P型掺杂非晶硅层上沉积第二透明导电层。
  15. 一种光伏组件，其特征在于，包括如权利要求1-11任一项所述的异质结电池。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7056381B1 (en) * 1996-01-26 2006-06-06 Semiconductor Energy Laboratory Co., Ltd. Fabrication method of semiconductor device
CN109148616A (zh) * 2017-06-16 2019-01-04 国家电投集团科学技术研究院有限公司 硅异质结太阳电池及其制备方法
CN110137278A (zh) * 2019-04-11 2019-08-16 西南石油大学 原位还原制备电镀种子层的异质结太阳电池及其制备方法
CN114823935A (zh) * 2022-05-16 2022-07-29 东方日升新能源股份有限公司 一种异质结电池及其制备方法

Family Cites Families (22)

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Publication number Priority date Publication date Assignee Title
JPWO2012020682A1 (ja) * 2010-08-09 2013-10-28 株式会社カネカ 結晶シリコン系太陽電池
JP5675476B2 (ja) * 2011-04-18 2015-02-25 株式会社カネカ 結晶シリコン系太陽電池
JP5762552B2 (ja) * 2011-10-27 2015-08-12 三菱電機株式会社 光電変換装置とその製造方法
JPWO2013069324A1 (ja) * 2011-11-10 2015-04-02 三菱電機株式会社 太陽電池およびその製造方法、太陽電池モジュール
JP2013161822A (ja) * 2012-02-01 2013-08-19 Mitsubishi Electric Corp 太陽電池およびその製造方法、太陽電池モジュール
KR20140022507A (ko) * 2012-08-13 2014-02-25 현대중공업 주식회사 후면전극형 이종접합 태양전지 및 그 제조방법
FR3007200B1 (fr) * 2013-06-17 2015-07-10 Commissariat Energie Atomique Cellule solaire a heterojonction de silicium
TW201703267A (zh) * 2015-07-07 2017-01-16 國立中央大學 紫外光臭氧調製透明導電薄膜之太陽能電池製造方法
CN106449850B (zh) * 2015-08-05 2018-07-13 钧石(中国)能源有限公司 一种高效硅基异质结双面电池及其制备方法
CN106601855A (zh) * 2015-10-14 2017-04-26 钧石(中国)能源有限公司 一种双面发电异质结太阳能电池的制备方法
TW201822371A (zh) * 2016-12-07 2018-06-16 財團法人金屬工業研究發展中心 異質接面太陽能電池及其製造方法
CA3013818A1 (en) * 2017-11-15 2019-05-15 Beijing Juntaiinnovation Technology Co., Ltd. Heterojunction solar cell and preparation method thereof
CN108321239A (zh) * 2017-12-21 2018-07-24 君泰创新（北京）科技有限公司 一种太阳能异质结电池及其制备方法
KR20200058735A (ko) * 2018-11-20 2020-05-28 성균관대학교산학협력단 광 특성이 조절 가능한 후면 에미터 결정질 실리콘 태양전지의 제조 방법
CN114078986A (zh) * 2020-08-18 2022-02-22 福建金石能源有限公司 一种异质结太阳能电池的制作方法
CN114361281A (zh) * 2020-09-29 2022-04-15 嘉兴阿特斯技术研究院有限公司 双面异质结太阳能电池及光伏组件
CN112736151B (zh) * 2021-01-08 2022-11-15 上海交通大学 基于宽带隙窗口层的背结硅异质结太阳电池
CN113437184A (zh) * 2021-01-14 2021-09-24 宣城睿晖宣晟企业管理中心合伙企业(有限合伙) 一种异质结太阳能电池的制备方法及异质结太阳能电池
CN113113502A (zh) * 2021-05-11 2021-07-13 通威太阳能（安徽）有限公司 一种异质结太阳能电池及制备方法
CN113410328A (zh) * 2021-05-12 2021-09-17 北京工业大学 一种晶硅异质结太阳能电池
CN113782631A (zh) * 2021-10-09 2021-12-10 中建材光电装备（太仓）有限公司 具有缓冲保护膜的异质结太阳能电池及其制备方法
CN114447135B (zh) * 2022-01-28 2024-09-06 西安隆基乐叶光伏科技有限公司 一种太阳能电池及其制备方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7056381B1 (en) * 1996-01-26 2006-06-06 Semiconductor Energy Laboratory Co., Ltd. Fabrication method of semiconductor device
CN109148616A (zh) * 2017-06-16 2019-01-04 国家电投集团科学技术研究院有限公司 硅异质结太阳电池及其制备方法
CN110137278A (zh) * 2019-04-11 2019-08-16 西南石油大学 原位还原制备电镀种子层的异质结太阳电池及其制备方法
CN114823935A (zh) * 2022-05-16 2022-07-29 东方日升新能源股份有限公司 一种异质结电池及其制备方法

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