WO2023221215A1 - 芯片结构、芯片结构的封装方法及电路板模组 - Google Patents

芯片结构、芯片结构的封装方法及电路板模组 Download PDF

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Publication number
WO2023221215A1
WO2023221215A1 PCT/CN2022/098896 CN2022098896W WO2023221215A1 WO 2023221215 A1 WO2023221215 A1 WO 2023221215A1 CN 2022098896 W CN2022098896 W CN 2022098896W WO 2023221215 A1 WO2023221215 A1 WO 2023221215A1
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WIPO (PCT)
Prior art keywords
conductive layer
chip structure
insulating layer
conductive
layer
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PCT/CN2022/098896
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English (en)
French (fr)
Inventor
叶永超
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上海闻泰电子科技有限公司
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Publication of WO2023221215A1 publication Critical patent/WO2023221215A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements

Definitions

  • the present disclosure relates to a chip structure, a packaging method of the chip structure, and a circuit board module.
  • system-level packaging that is, 3D stacked packaging
  • 3D stacked packaging is usually used.
  • the use of 3D stacked packaging will cause The overall thickness of the chip structure becomes higher, which is not conducive to miniaturization of the chip structure.
  • a chip structure a packaging method of the chip structure, and a circuit board module are provided.
  • a chip structure including:
  • Crystal grains the crystal grains have a first surface, and a first electrical connection portion is provided on the first surface;
  • the insulating layer is provided on the first surface, the insulating layer is provided with a first through hole and a mounting hole, the first through hole corresponds to the position of the first power connection portion to expose at least part of In the first power connection part, the mounting hole is spaced apart from the first through hole;
  • the conductive layer is provided on a side of the insulating layer away from the first surface, the conductive layer is electrically connected to the first power connection part, the conductive layer has a hollow part, the hollow part The part corresponds to and is connected to the mounting hole;
  • the implanted component is at least partially installed in the hollow portion and the mounting hole in the direction from the die to the conductive layer, and the implanted component is electrically connected to the conductive layer.
  • the chip structure further includes: the first surface is further provided with a second power connection portion, the second power connection portion is located in the mounting hole, and the The second power connection part is electrically connected to the conductive layer and the implanted component.
  • the chip structure further includes: the conductive layer includes multiple layers, and multiple layers of the conductive layers are stacked, and there is a conductive layer between two adjacent conductive layers.
  • the insulating layer is also provided with a second through hole on the insulating layer between two adjacent layers of the conductive layer, and the second through hole is configured to provide space for the two adjacent layers of the conductive layer. Connect to achieve electrical conduction.
  • the chip structure further includes: multiple layers of conductive layers including at least a first conductive layer and a second conductive layer that are adjacently arranged.
  • the second conductive layer is located on a side of the first conductive layer away from the crystal grains, both the second conductive layer and the first conductive layer have the hollow portion, and The hollow portion on the second conductive layer corresponds to and is connected with the hollow portion on the first conductive layer;
  • the insulating layer located between the first conductive layer and the second conductive layer is also provided with a second power connection portion, the second power connection portion is located in the mounting hole, and the second power connection portion electrically connected to the first conductive layer and/or the second conductive layer;
  • the implanted component is also electrically connected to the second power connection part.
  • the chip structure further includes: the insulating layer is multiple layers, and the multiple insulating layers include at least a first insulating layer provided on the first surface and an insulating layer provided on the first surface. In the second insulating layer between two adjacent conductive layers, the mounting hole and the second through hole are provided in the second insulating layer.
  • the chip structure further includes: the chip structure further includes a metal ball, the metal ball is provided on a side of the conductive layer away from the insulating layer, so The metal ball is electrically connected to the conductive layer.
  • the chip structure further includes: the chip structure further includes a support portion, the support portion is electrically connected to the conductive layer, the support portion includes an end surface and a A first protruding part and a second protruding part are arranged oppositely on the end face. The first protruding part and the second protruding part extend from the end face away from the conductive layer. The metal ball clamps and Electrically connected between the first protruding part, the second protruding part and the end surface.
  • the chip structure further includes: the mutually facing surfaces of the first protrusion part and the second protrusion part are inclined surfaces.
  • the chip structure further includes: the die further has a second surface and an outer peripheral surface, the second surface is arranged opposite to the first surface, and the The outer peripheral surface is connected to the first surface and the second surface;
  • the chip structure further includes a plastic sealing layer covering the outer peripheral surface and the second surface.
  • a packaging method of a chip structure is configured as a method of manufacturing a chip structure, the packaging method includes:
  • first conductive layer on a side of the first electrical connection part away from the die, so that the first conductive layer covers the first insulating layer and the first electrical connection part, and the first conductive layer
  • the conductive layer is electrically connected to the first power connection part
  • a hollow portion is provided on the first conductive layer, the hollow portion corresponds to the position where a portion of the first insulating layer is removed;
  • An implanted element is implanted into the hollow part, and the implanted element is electrically connected to the first conductive layer.
  • the chip structure further includes a second insulating layer and a second conductive layer
  • the packaging method further includes:
  • the second insulating layer is provided on the side of the first conductive layer facing away from the first insulating layer, so that the second insulating layer covers the first conductive layer and the hollow portion;
  • the second conductive layer is disposed on a side of the second insulating layer facing away from the first conductive layer, so that the second conductive layer is electrically connected to the exposed first conductive layer;
  • the packaging method further includes:
  • a support portion is provided on a side of the second conductive layer facing away from the second insulating layer.
  • the support portion is electrically connected to the second conductive layer, and is located on a side of the support portion facing away from the second conductive layer.
  • a metal ball is provided on one side of the metal ball, and the metal ball is electrically connected to the second conductive layer through the support part.
  • the packaging method further includes:
  • Molding is performed on the second surface of the die that is opposite to the first surface and the outer peripheral surface connected to the first surface and the second surface.
  • the method of removing part of the first insulating layer to expose at least part of the first electrical connection part is:
  • Laser etching or chemical etching is used to remove part of the first insulating layer to expose at least part of the first electrical connection part.
  • a circuit board module including a circuit board and the chip structure as described in the first aspect, the circuit board is provided on the side of the conductive layer away from the crystal grain, and the circuit board is electrically connected to the The conductive layer.
  • the circuit board module further includes: the chip structure includes a metal ball, and in the direction of the crystal grain toward the conductive layer, the implanted When the component protrudes from the metal ball, a side of the circuit board facing the conductive layer is provided with an avoidance structure corresponding to the implanted component, and the avoidance structure is configured to avoid the implanted component.
  • Figure 1 is a schematic structural diagram of a chip structure (having a conductive layer) provided by one or more embodiments of the present disclosure
  • Figure 2 is a schematic structural diagram of a chip structure (having multiple conductive layers) provided by one or more embodiments of the present disclosure
  • Figure 3 is a schematic diagram of a package of a chip structure with multiple conductive layers provided by one or more embodiments of the present disclosure
  • Figure 4 is a flow chart of a packaging method provided by one or more embodiments of the present disclosure.
  • Figure 5 is another flow chart of a packaging method provided by one or more embodiments of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a circuit board module provided by one or more embodiments of the present disclosure.
  • first, second, etc. in the description and claims of the present disclosure are used to distinguish different objects, rather than to describe a specific order of objects.
  • first camera and the second camera are used to distinguish different cameras, rather than to describe a specific order of the cameras.
  • words such as “exemplary” or “for example” mean examples, illustrations or explanations. Any embodiment or design described as “exemplary” or “such as” in the present disclosure is not intended to be construed as preferred or advantageous over other embodiments or designs. To be precise, the use of words such as “exemplary” or “such as” is intended to present relevant concepts in a specific manner. In addition, in the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "plurality" refers to both one or more than two.
  • Figure 1 is a schematic structural diagram of a chip structure (having one conductive layer) provided by one or more embodiments of the present disclosure
  • Figure 2 is a structural diagram of a chip structure (having multiple conductive layers) provided by one or more embodiments of the present disclosure.
  • the schematic diagram that is, FIG. 2 is a description of another implementable manner of the present disclosure based on the embodiment shown in FIG. 1 , wherein (a) in FIG. 2 shows a chip structure with two conductive layers.
  • Structural schematic diagram, (b) in Figure 2 shows a schematic structural diagram of a chip structure with three conductive layers
  • Figure 3 is a package schematic diagram of a chip structure with multiple conductive layers provided by one or more embodiments of the present disclosure.
  • (a) to (f) in FIG. 3 provide the structural change process of a chip structure with multiple conductive layers in one or more embodiments during the packaging process.
  • the chip structure 100 includes a die 1 , an insulating layer 2 , a conductive layer 3 and an implanted component 4 .
  • the die 1 has a first surface 11, and a first power connection portion 5 is provided on the first surface 11; an insulating layer 2 is provided on the first surface 11, and the insulating layer 2 is provided with a first through hole 2a and a mounting hole 2b.
  • the through hole 2a corresponds to the position of the first power connection part 5 so as to expose at least part of the first power connection part 5.
  • the mounting hole 2b is spaced apart from the first through hole 2a.
  • the conductive layer 3 is provided on the side of the insulating layer 2 away from the first surface 11.
  • the conductive layer 3 is electrically connected to the first power connection part 5.
  • the conductive layer 3 has a hollow part 3a.
  • the hollow part 3a corresponds to and is connected to the mounting hole 2b. .
  • the implanted component 4 is at least partially located in the mounting hole 2 b and the hollow portion 3 a , and the implanted component 4 is electrically connected to the conductive layer 3 .
  • the design of the conductive circuits on the chip structure 100 will be relatively complicated.
  • the present disclosure realizes that the first power connection part 5 and the conductive layer 3 are kept insulated at positions that do not require electrical connection by arranging the insulating layer 2; at the same time, by arranging the first through hole 2a on the insulating layer 2, so that The first power connection part 5 and the conductive layer 3 are electrically connected at required positions, so that the arrangement of the conductive lines between the first power connection part 5 and the conductive layer 3 can meet the design requirements.
  • the first electrical connection portion 5, the insulating layer 2 and the conductive layer 3 in the thickness direction of the die 1 can reduce the surface area of the chip structure 100, it will make the chip The overall thickness of structure 100 is increased.
  • some implanted elements 4 need to be provided in the chip structure 100 to realize some functions of the chip structure 100, and the thickness of the implanted elements 4 is significantly thicker than the insulating layer 2 and the conductive layer 3, when the implanted elements 4 are to be implanted, When the component 4 is electrically connected to the conductive layer 3, the thickness of the chip structure 100 will be significantly increased.
  • the present disclosure further provides a hollow portion 3a on the conductive layer 3, and a mounting hole 2b corresponding to and connected to the hollow portion 3a on the insulating layer 2, so that the implanted component 4 is installed in the mounting hole 2b. , so that at least part of the implanted element 4 in the direction from the die 1 to the conductive layer 3 is located in the mounting hole 2b and the hollow portion 3a. At this time, the implanted element 4 protrudes beyond the thickness of the conductive layer 3 become smaller, thereby effectively reducing the impact of the implanted component 4 on the overall size of the chip structure 100, thereby further realizing a miniaturized design of the chip structure 100.
  • each structure mentioned above refers to the upper dimensions of the die 1, the insulating layer 2, the conductive layer 3 and the implanted element 4 in the direction from the die 1 to the conductive layer 3 (as shown in Figure 1 X direction).
  • the first power connection part 5 may be a solder joint, a solder pad, a pin, etc.
  • the implanted component 4 may include, but is not limited to, a capacitor, an inductor, a resistor, or a device that needs to be electrically connected to the chip structure 100 to achieve the functional requirements of the chip structure 100.
  • the first power connection part 5, The type of implanted component 4 is not limited.
  • the number of the first power connection portion 5 , the first through hole 2 a , the hollow portion 3 a , the mounting hole 2 b and the implanted component 4 can be multiple, and the hollow portion 3 a and the mounting hole 2 b can be located at Central position, can also be located at the edge.
  • the number of hollow portions 3 a and mounting holes 2 b can be set in accordance with the number of implanted components 4 , that is, one implanted component is provided in each hollow portion 3 a and mounting hole 2 b at the same time.
  • multiple implanted components 4 may be provided in one hollow portion 3a and the mounting hole 2b.
  • the first through hole 2a realizes the electrical connection between the first power connection part 5 and the conductive layer 3, which may include but is not limited to: the conductive layer 3 extends into the first through hole 2a and connects with the first through hole 2a.
  • the power connection part 5 is in direct contact to achieve electrical connection, or a conductive part (such as a metal pillar, a flexible circuit board, a conductive wire, etc.) is provided in the first through hole 2a, and one end of the conductive part is connected to the conductive layer 3, The other end is connected to the first power connection part 5 to achieve electrical connection between the conductive layer 3 and the first power connection part 5 .
  • a conductive part such as a metal pillar, a flexible circuit board, a conductive wire, etc.
  • the conductive layer 3 extends into the first through hole 2 a and directly contacts the first power connection portion 5 to achieve electrical connection.
  • the A through hole 2a has an inclined wall surface, so that the aperture of the first through hole 2a gradually increases along the direction from the die 1 to the conductive layer 3 (the X direction in Figure 1), so that the first through hole 2a is provided
  • the conductive layer 3 can play a guiding role to facilitate the electrical connection between the conductive layer 3 and the first power connection portion 5 . It can be understood that the number and location of the first through holes 2a can be adjusted according to the conductive circuit requirements of the chip structure 100, and are not specifically limited in this embodiment.
  • the first through hole 2a may be formed by laser etching, chemical etching or other methods by removing the material of the insulating layer 2.
  • the specific implementation of the first through hole 2a is not limited.
  • the hollow portion 3a on the conductive layer 3 can be formed together with the formation of the conductive lines or conductive patterns of the conductive layer 3. That is, after the conductive layer 3 is formed, the hollow portion 3a can be formed simultaneously.
  • the hollow portion 3a can also be formed by removing part of the material of the conductive layer 3 after the conductive layer 3 is formed.
  • the mounting hole 2b has an inclined wall, so that the opening of the mounting hole 2b extends along the die 1 to the conductive layer 3
  • the direction (X direction in Figure 1) gradually increases, thereby facilitating the installation of the implanted component 4.
  • the mounting hole 2b may be formed by laser etching or chemical etching or other materials by removing the insulating layer.
  • the specific implementation of the mounting hole 2b is not limited.
  • the conductive layer 3 can be configured as one layer or multiple layers according to actual functional requirements.
  • the conductive layer 3 is multiple layers, it is possible to increase the circuits of the chip structure 100 when the surface area of the chip structure 100 is limited. The area is arranged to meet the functional requirements of the chip structure 100 .
  • the electrical connection between 4 and the conductive layer 3 can be provided with a second power connection part 6 on the first surface 11, the second power connection part 6 is located in the mounting hole 2b, and the second power connection part 6 is electrically connected to the conductive layer 3 and the implanted component 4.
  • the electrical connection between the implanted element 4 and the conductive layer 3 can be facilitated.
  • connection structures at the electrical connection locations need to correspond to each other to achieve electrical connection between the two. That is, if the electrical connection structure electrically connected to the implanted component 4 on the chip structure 100 is fixed, then the types of implanted components 4 that the chip structure 100 can be connected to will be limited. Therefore, the present disclosure also provides a second power connection part 6 on the first surface 11.
  • the type and position of the second power connection part 6 can be designed corresponding to the power connection structure of the implanted component 4 that requires electrical connection, that is, The type and position of the second power connection part 6 can be flexibly adjusted to adapt to different implanted components 4, so that the chip structure 100 can connect to various implanted components 4, thereby facilitating the expansion of the chip structure 100. Implementation of different functions.
  • the second power-connecting part 6 may be a solder point, or other power-connecting component such as a pad that can realize the electrical connection between the implanted component 4 and the conductive layer 3.
  • the second power-connecting part 6 is The specific structure of the second power connection part 6 is not limited.
  • the electrical connection position of the implanted element 4 is located on its own outer peripheral surface, then the part of the outer peripheral surface of the implanted element 4 disposed in the hollow portion 3a is directly in contact with the conductive layer 3 to achieve electrical connection, then There is no need to provide an additional second power connection portion 6 , which can simplify the design of the conductive circuits of the chip structure 100 .
  • the conductive layer 3 includes multiple layers (as shown in Figures 2 and 3), and when the multiple conductive layers 3 are stacked, the insulating layer is provided between two adjacent conductive layers 3. 2, to achieve insulating connection between two adjacent conductive layers 3 at locations where electrical conduction is not required through the insulating layer 2 .
  • a second through hole 2c is provided on the insulating layer 2 to achieve electrical conduction at a required location between two adjacent conductive layers 3 through the second through hole 2c.
  • the method for achieving electrical connection and conduction between the two adjacent conductive layers 3 through the second through hole 2c may include but is not limited to: among the two adjacent conductive layers 3, one of them is conductive.
  • Layer 3 extends into the second through hole 2c and directly contacts another conductive layer 3 to achieve electrical connection, or conductive parts (such as metal pillars, flexible circuit boards, conductive wires, etc.) are provided in the second through hole 2c. ), one end of the conductive element is connected to one of the conductive layers 3, and the other end is connected to the other conductive layer 3 to achieve electrical connection between the two adjacent conductive layers 3.
  • the second through hole 2c since the second through hole 2c needs to realize the electrical connection between two adjacent conductive layers 3, in order to facilitate the arrangement of the conductive layer 3, the second through hole 2c has an inclined wall surface, so that the second through hole 2c The opening 2c gradually increases along the direction from the die 1 to the conductive layer 3 (the X direction in Figure 1), so that it can play a guiding role when the conductive layer 3 is set in the second through hole 2c, so as to facilitate the realization of two adjacent layers. Electrical connection between conductive layers 3. It can be understood that the number and location of the second through holes 2c can be adjusted according to the conductive circuit requirements of the chip structure 100, and are not specifically limited in this embodiment.
  • the conductive layer 3 When the conductive layer 3 has multiple layers, in one example, taking the conductive layer 3 as two layers (as shown in (a) in FIG. 2 ), the conductive layer 3 includes an adjacent first conductive layer 31 and a The second conductive layer 32 is along the direction of the die 1 to the conductive layer 3. The second conductive layer 32 is located on the side of the first conductive layer 31 away from the die 1. The second conductive layer 32 and the first conductive layer 31 are both There is a hollow portion 3 a (see (c) in FIG. 3 ), and the hollow portion 3 a on the second conductive layer 32 corresponds to and is connected with the hollow portion 3 a on the first conductive layer 31 . At this time, the insulating layer 2 also has two layers.
  • the insulating layer 2 includes a first insulating layer 21 located on the first surface 11 and a second insulating layer 22 located between the first conductive layer 31 and the second conductive layer 32 .
  • the mounting hole 2b on the second insulating layer 22 corresponds to and is connected with the hollow portion 3a of the first conductive layer 31 and the second conductive layer 32.
  • the second electrical connection portion 6 can be provided on the side of the first insulating layer 21 away from the first surface 11 and located at In the mounting hole 2 b of the insulating layer 2 between the first conductive layer 31 and the second conductive layer 32 , the second power connection portion 6 can be electrically connected to the second power connection portion 6 by the implanted component 4 .
  • the second power connection part 6 can be electrically connected to the first conductive layer 31 to realize the electrical connection between the implanted element 4 and the first conductive layer 31; or, the second power connection part 6 can be Electrically connected to the second conductive layer 32 to achieve electrical connection between the implanted element 4 and the second conductive layer 32; alternatively, the second power connection part 6 can be electrically connected to the first conductive layer 31 and the second conductive layer 32 at the same time , to achieve electrical connection between the implanted element 4 and the first conductive layer 31 and the second conductive layer 32 at the same time. It can be understood that the electrical connection method between the second power connection part 6 and the first conductive layer 31 and the second conductive layer 32 can be selected according to the needs of the conductive circuit, and is not specifically limited in this embodiment.
  • the conductive layer 3 when the conductive layer 3 has three layers (as shown in (b) in FIG. 2 ), the conductive layer 3 includes a first conductive layer 31 , a second conductive layer 32 and a third conductive layer 33 .
  • the die 1 is directed toward the conductive layer 3, the second conductive layer 32 is located on the side of the first conductive layer 31 facing away from the die 1, and the third conductive layer 33 is located on the side of the second conductive layer 32 facing away from the first conductive layer.
  • the insulating layer 2 also has three layers.
  • the insulating layer 2 includes a first insulating layer 21 located on the first surface 11, a second conductive layer 32 located between the first conductive layer 31 and the second conductive layer 32, and a second conductive layer 32 located between the first conductive layer 31 and the second conductive layer 32.
  • the third insulating layer 23 is between the conductive layer 32 and the third conductive layer 33 .
  • the mounting hole 2b on the second insulating layer 22 corresponds to and is connected with the mounting hole 2b on the third insulating layer 23, and is connected with the hollow holes on the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33.
  • Part 3a (see (c) in Figure 3) is provided correspondingly and connected.
  • the second power connection part 6 is located in the mounting hole 2b of the second insulating layer 22 and is located on the side of the first insulating layer 21 away from the first surface 11.
  • the implanted component 4 is located in the mounting hole 2b and is electrically connected to the second
  • the power connection part 6, and the second power connection part 6 can be electrically connected to any one conductive layer 3 or two conductive layers 3 according to the needs of the conductive circuit, or even to three conductive layers 3 at the same time. In this embodiment Not limited.
  • the placement position of the implanted component 4 is just an example. That is, when the conductive layer 3 is multi-layered, the implanted element 4 can be installed in one layer of conductive layer 3 and insulating layer 2 , or the implanted element 4 can also be installed in multiple layers of conductive layer 3 and insulating layer 2 In this case, the influence of the thickness of the implanted component 4 on the overall thickness of the chip structure 100 can be avoided to a greater extent. It can be understood that when the conductive layer 3 has more layers, the position of the implanted element 4 can be adjusted according to actual needs, which is not limited in this embodiment.
  • the chip structure 100 in order to achieve electrical connection between the chip structure 100 and other devices, also includes a metal ball 7 .
  • the metal ball 7 can be disposed on the conductive layer using a ball planting process. On the side of 3 facing away from the insulating layer 2, the metal ball 7 is electrically connected to the conductive layer 3.
  • the electrical connection method of the metal ball 7 between the two devices makes it easier to realize the miniaturization design of the overall structure after combining different devices.
  • the metal ball 7 can be a conductive tin ball, a copper ball, a silver ball or other metal materials.
  • the specific material of the metal ball 7 is not limited.
  • the chip structure 100 further includes a support portion 8 located between the metal ball 7 and the conductive layer 3, so that the metal ball 7 is electrically connected to the conductive layer 3 through the support portion 8 .
  • the connection area between the conductive layer 3 and the metal ball 7 may be relatively small, and the shape of the metal ball 7 may make the electrical connection between the metal ball 7 and the conductive layer 3 unstable. , therefore by adding the support portion 8 between the metal ball 7 and the conductive layer 3 , the electrical connection stability between the metal ball 7 and the conductive layer 3 can be improved.
  • the support part 8 may be made of the same metal material as the metal ball 7 , or may be a metal material different from the material of the metal ball 7 , or may be conductive ceramics with conductive function, etc. In this embodiment, The support part 8 is not specifically limited.
  • the support part 8 includes an end surface 81 and a first protruding part 82 and a second protruding part 83 provided on the end surface 81 and arranged oppositely.
  • the first protruding part 82 and the second protruding part 83 are formed from the end surface.
  • 81 extends away from the conductive layer 3 to clamp the metal ball 7 , thereby improving the connection stability of the metal ball 7 on the end surface 81 of the support part 8 and preventing the metal ball 7 from falling off the support part 8 .
  • the metal ball 7 is electrically connected between the first protruding part 82 , the second protruding part 83 and the end surface 81 , so as to achieve joint contact with the metal ball 7 through the end surface 81 , the first protruding part 82 and the second protruding part 83 . electrical connection, thereby improving the stability of the electrical connection between the support part 8 and the metal ball 7, and further improving the stability of the electrical connection between the metal ball 7 and the conductive layer 3.
  • first protruding part 82 and the second protruding part 83 may be spaced apart from each other. In this case, the force of the metal ball 7 can be more balanced, so as to improve the contact between the metal ball 7 and the first protruding part 82.
  • the connection stability of the second protrusion 83 It can be understood that the first protruding portion 82 and the second protruding portion 83 can be one pair spaced apart and oppositely arranged, or two pairs, three pairs or more pairs arranged mutually apart from each other.
  • first protruding part 82 and the second protruding part 83 may also be connected to each other and disposed oppositely.
  • first protruding part 82 and the second protruding part 83 may be enclosed with the end surface 81 Forming a groove for accommodating the metal ball 7 so that the metal ball 7 can be disposed in the groove can effectively improve the connection stability and electrical connection stability between the metal ball 7 and the support portion 8 .
  • the mutually facing surfaces of the first protruding portion 82 and the second protruding portion 83 can be inclined surfaces to guide the metal ball 7 when the metal ball 7 is set, to further improve the contact between the metal ball 7 and the metal ball 7 .
  • the die 1 since the conductive circuits required for the chip structure 100 are too complex, in order to accommodate more conductive circuits, the die 1 has a second surface 12 opposite to the first surface 11 and is connected to the first surface 11 and The outer peripheral surface 13 of the second surface 12 . And the chip structure 100 also includes a plastic sealing layer 9 covering the second surface 12 and the outer peripheral surface 13. The plastic sealing layer 9 provided on the outer periphery of the outer peripheral surface 13 can also be used to carry some conductive circuits, that is, the die 1 can be fan-out.
  • the plastic encapsulation layer 9 can also expand the area of the die 1 that can be used to carry conductive circuits, such as the first power connection part 5 , which helps provide more space for the design of conductive lines.
  • the material of the plastic sealing layer 9 can be a polymer resin material, such as Ajinomoto Build-up Film-ABF, benzocyclobutene (BCB), bismaleimide triazine (BT) ), epoxy, polyester, polyimide and/or PTFE.
  • the material of the plastic sealing layer 9 may also be a reinforcing material for polymeric resin materials, such as glass fiber reinforcing material.
  • the chip structure 100 provided in this embodiment realizes miniaturization and packaging of the chip structure 100 by stacking the conductive layer 3 and the insulating layer 2 along the thickness direction of the die 1 .
  • the implanted component 4 can be disposed in the mounting hole 2b to reduce the impact of the implanted component 4 on the chip structure. 100 to further realize the miniaturization design of the chip structure 100 .
  • embodiments of the present disclosure also provide a packaging method for encapsulating the above chip structure 100.
  • FIG. 4 is a flow chart of a packaging method provided by one or more embodiments of the present disclosure
  • FIG. 5 is another flow chart of a packaging method provided by one or more embodiments of the present disclosure. Please combine Figure 3, Figure 4 and Figure 5.
  • the packaging method of the chip structure 100 includes:
  • the purpose of this step is to provide the first electrical connection portion 5 on the first surface 11 of the die 1 as a basis for subsequent electrical connection with the first conductive layer 31 .
  • the provision of the first insulating layer 21 can realize the insulating arrangement between the first power connection part 5 and the first conductive layer 31 , thereby avoiding the installation of the first power connection part 5 on the first conductive layer 31 .
  • the first power connection part 5 can be made of metal or metal alloy, which may include but is not limited to solder joints, pads, pins, etc.
  • the first power connection part 5 is provided on the first surface 11 At this time, it can be in contact with the circuit on the first surface 11 to achieve electrical conduction.
  • the first insulating layer 21 may be a polymeric resin material, such as Ajinomoto Build-up Film-ABF, benzocyclobutene (BCB), or bismaleimide triazine (BT). , epoxy, polyester, polyimide and/or PTFE.
  • the material of the first insulating layer 21 may also be a reinforcing material for polymeric resin materials, such as glass fiber reinforcing material.
  • the purpose of this step is to form a first through hole 2 a for exposing at least part of the first power connection portion 5 and a mounting hole 2 b for mounting the implanted component 4 on the first insulating layer 21 .
  • the first conductive layer 31 is electrically Connected to the first power connection part 5;
  • the purpose of this step is to realize the electrical connection between the first conductive layer 31 and the first power connection part 5 , that is, the first conductive layer 31 realizes the electrical connection with the first power connection part through the first through hole 2 a on the first insulating layer 21 5 electrical connections between.
  • the first conductive layer 31 may be made of a single metal material or a metal alloy material, such as copper, gold, silver, copper alloy, etc.
  • the first through hole 2a realizes the electrical connection between the first power connection part 5 and the first conductive layer 31, which may include but is not limited to: the first conductive layer 31 extends into the first through hole 2a and connects with the first through hole 2a.
  • the first power connection part 5 is in direct contact to achieve electrical connection, or a conductive part (such as a metal pillar, a flexible circuit board, a conductive wire, etc.) is provided in the first through hole 2a, and one end of the conductive part 5 is connected to the first through hole 2a.
  • the other end of the conductive layer 31 is connected to the first power connection part 5 to achieve electrical connection between the first conductive layer 31 and the first power connection part 5 .
  • the hollow portion 3a formed in this step is to provide a setting location for the implanted component 4, and the hollow portion 3a corresponds to the mounting hole 2b.
  • the implanted element 4 is electrically connected to the first conductive layer 31.
  • the implanted component 4 when the implanted component 4 is installed in the mounting hole 2b, the implanted component 4 can be directly electrically connected to the first conductive layer 31 at the position of the hollow portion 3a, or it can be installed during installation.
  • a second power connection portion 6 is provided in the hole 2 b, and the implanted element 4 is electrically connected to the first conductive layer 31 through the second power connection portion 6 .
  • the chip structure 100 when the functions required to be implemented by the chip structure 100 are different, the chip structure 100 is usually provided with multiple layers of insulating layers 2 and conductive layers 3. When the chip structure 100 has multiple layers of insulating layers 2 and conductive layers 3, The above packaging methods also include:
  • this step is to realize the functional diversity of the chip structure 100, that is, when multiple conductive layers need to be provided, the second insulating layer 22 can realize the insulation arrangement between the first conductive layer 31 and the second conductive layer 32, so that The arrangement of the second conductive layer 32 is not affected.
  • the material and arrangement of the second insulating layer 22 may refer to the material and arrangement of the first insulating layer 21 , which will not be described again here.
  • This step is to form the second through hole 2c in the second insulating layer 22 so as to achieve electrical connection between the second conductive layer 32 and the first conductive layer 31 through the second through hole 2c.
  • This step is to achieve electrical connection between the second conductive layer 32 and the first conductive layer 31 .
  • this step is that when the insulating layer 2 and the conductive layer 3 have multiple layers, the mounting holes 2b corresponding to the hollow portion 3a can be formed on the second insulating layer 22, so that the mounting holes 2b of the first insulating layer 21 are connected to the second insulating layer 21.
  • the mounting holes 2b of the two insulating layers correspond to each other, so that the implanted component 4 can be installed in the mounting holes 2b of the multi-layer insulating layer 2 and the hollow portion 3a of the conductive layer 3.
  • the implanted element 4 can be embedded in the multi-layer conductive layer 3 and the multi-layer insulating layer 2 at the same time, thereby avoiding the impact of the arrangement of the implanted element 4 on the overall size of the chip structure 100 , especially along the die 1 to the conductive layer 3 size in the direction.
  • the implanted element 4 can be electrically connected to the first conductive layer 31 or the second conductive layer 32, or can be electrically connected to the first conductive layer 31 and the second conductive layer 32 at the same time.
  • the specific connection method can be based on Actual selection is required and is not specifically limited in this embodiment.
  • steps 306 to 309 of the above-mentioned packaging method can be performed after step 304 (providing the hollow portion 3a on the first conductive layer 31).
  • the packaging method in order to facilitate the electrical connection between the chip structure 100 and other structures while miniaturizing the overall structure, the packaging method also includes:
  • a support portion 8 is provided on the side of the second conductive layer 32 that is away from the second insulating layer 22.
  • the support portion 8 is electrically connected to the second conductive layer 32, and is located on the side of the support portion 8 that is away from the second conductive layer 32.
  • a metal ball 7 is provided, and the metal ball 7 is electrically connected to the second conductive layer 32 through the support portion 8 .
  • this step may be performed after step 308 (disposing the second conductive layer 32 on the side of the second insulating layer 22 away from the first conductive layer 31).
  • the purpose of this step is to improve the electrical connection stability between the metal ball 7 and the second conductive layer 32 through the arrangement of the support part 8.
  • the purpose of the metal ball 7 in this step is to connect the chip structure 100 with other circuit board structures. Provides the basis for electrical connections.
  • the metal ball 7 can be connected to the support portion 8 using a ball planting process, and the arrangement of the metal ball 7 is beneficial to miniaturization when the chip structure 100 is connected to other circuit board structures.
  • the support part 8 and the metal ball 7 can be made of the same conductive material.
  • the support part 8 and the metal ball 7 can be made of copper. They can also be made of different conductive materials.
  • the support part 8 can be made of gold, and the metal ball 7 can be made of gold.
  • the material can be copper.
  • the above steps of arranging the support part 8 and the metal ball 7 may be performed after step 308, before step 309, or after step 309, but should not be performed after the installation hole 2b is formed and between the installation of the implanted component 4. Planting the metal ball 7 operations. If the metal ball 7 is implanted first after the mounting hole 2b is formed, impurities will fall into the mounting hole 2b during the metal ball 7 implanting process, thereby causing the subsequent installation of the implanted component 4 in the mounting hole 2b to be blocked or Situations such as electrical connection failure will affect the production efficiency and production quality of the chip structure 100 .
  • the manufacturing method of the chip structure 100 can be as shown in FIG. 4, in which the support part 8 and the metal ball 7 can be provided after step 305. ;
  • the manufacturing method of the chip structure 100 can be as shown in Figure 5, in which the support part 8 and the metal The ball 7 can be set after step 309; when the structure of the chip structure 100 is more complex, the above steps of setting the first insulating layer 21, the first conductive layer 31, the second insulating layer 22, and the second conductive layer 32 can be repeated.
  • a multi-layer structure of the chip structure 100 is formed to meet the functional requirements of the chip structure 100 .
  • the support portion 8 and the metal ball 7 can be disposed on the conductive layer farthest from the die 1 3, thereby facilitating the electrical connection between the chip structure 100 and other structures.
  • the supporting portion 8 and the metal ball 7 can also be arranged in the same manner as the implanted component 4 , that is, through embedded design, thereby further realizing a miniaturized design of the chip structure 100 .
  • the packaging method further includes:
  • the crystal grain 1 has a second surface 12 and an outer peripheral surface 13.
  • the second surface 12 is arranged opposite to the first surface 11.
  • the outer peripheral surface 13 is connected to the first surface 11 and the second surface 12. Between the second surface 12 and the outer peripheral surface The surface 13 is provided with a plastic sealing layer 9;
  • this step can be performed before step 301 (setting the first electrical connection portion 5 on the first surface 11 of the die 1 and covering the first surface 11 with the first insulating layer 21).
  • the purpose of this step is to wrap and protect the die 1 through the plastic sealing layer 9 .
  • the plastic sealing layer 9 has a surface flush with the first surface 11 of the die 1 , when the first surface 11 of the die 1 is provided with a first If there is insufficient space on the first surface 11 of the die 1 for the power connection portion 5 , the first power connection portion 5 can be provided on both the die 1 and the plastic encapsulation layer 9 , thereby increasing the wiring space for the conductive lines of the chip structure 100 .
  • the material of the above-mentioned plastic sealing layer 9 can be a polymeric resin material, such as Ajinomoto Build-up Film-ABF, benzocyclobutene (BCB), bismaleimide triazine (BT), epoxy, polyester, polyimide and/or PTFE.
  • the material of the plastic sealing layer 9 may also be a reinforcing material for polymeric resin materials, such as glass fiber reinforcing material.
  • the above-mentioned removal of part of the first insulating layer 21 to expose at least part of the first power connection part 5 is as follows:
  • Laser etching or chemical etching is used to remove part of the material of the first insulating layer 21 corresponding to the first electrical connection portion 5 to form the first through hole 2a and the mounting hole 2b.
  • laser etching can improve processing accuracy and improve processing efficiency.
  • the first conductive layer 31 can be protected by chemical etching, thereby avoiding damage to the first conductive layer 31 .
  • the method of removing part of the second insulating layer 22 and exposing at least part of the first conductive layer 31 may also be implemented by, for example, chemical etching, laser etching, or other methods of removing the part of the material, so that the second insulating layer 22 is formed.
  • the hollow portion 3a can be formed together with the formation of the conductive lines or conductive patterns of the first conductive layer 31, that is, after the first conductive layer 31 is formed, the hollow portion 3a can be formed simultaneously.
  • the hollow portion 3a can also be formed by removing part of the material of the first conductive layer 31 after the first conductive layer 31 is formed.
  • an embodiment of the present disclosure also provides a circuit board module 200.
  • FIG 6 is a schematic structural diagram of a circuit board module provided by one or more embodiments of the present disclosure.
  • the circuit board module 200 provided by an embodiment of the present disclosure includes a circuit board 210 and the above-mentioned chip structure 100.
  • the circuit board 210 is located on a side of the conductive layer 3 away from the die 1 , and the circuit board 210 is electrically connected to the conductive layer 3 .
  • the circuit board module 200 having the above-mentioned chip structure 100 can realize the miniaturization design of the circuit board module 200 while achieving functional diversity.
  • the chip structure 100 includes a metal ball 7 and the implanted component 4 protrudes from the metal ball 7 along the direction of the die 1 toward the conductive layer 3
  • An avoidance structure 211 is provided on the side corresponding to the implanted component 4 to avoid the implanted component 4 .
  • the overall thickness of the circuit board module 200 along the thickness direction of the circuit board 210 makes the overall structure of the circuit board module 200 more compact.
  • the avoidance structure 211 can be a groove provided on the circuit board 210, a through hole, or a depression formed on the surface of the circuit board 210.
  • the specific form can be selected according to the actual situation. In this article There are no limitations in the examples.
  • the chip structure 100 and the circuit board 210 can also be electrically connected through conductive lines, such as gold wires, etc.; they can also be electrically connected through a flexible circuit board.
  • the specific connection method between the chip structure 100 and the circuit board 210 is not limited.
  • a support portion 8 can also be provided between the conductive layer 3 and the metal balls 7 .
  • the arrangement of the supporting part 8 may refer to the structure of the supporting part 8 described in the first aspect, and will not be described again here.
  • the circuit board module 200 provided by the embodiment of the present disclosure can realize functional diversity while also achieving miniaturization design.
  • the chip structure, chip structure packaging method and circuit board module provided by the present disclosure stack conductive layers along one side in the thickness direction of the crystal grain, and use the insulating layer to achieve insulating connections between the conductive structures, thereby making the chip structure Achieve miniaturization while meeting line layout requirements.
  • the implanted component is at least partially disposed in the hollow part and the mounting hole, the protruding height of the implanted component on the conductive layer can be reduced at this time, that is, the overall thickness of the chip structure can be reduced, and the chip can be further realized.
  • the miniaturized design of the structure has strong industrial practicality.

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Abstract

本公开实施例提供了一种芯片结构(100)、芯片结构的封装方法及电路板模组(100)，芯片结构(100)包括晶粒(1)、绝缘层(2)、导电层(3)及被植入元件(4)。晶粒(1)具有第一表面(11)，第一表面(11)上设有第一接电部(5)，绝缘层(2)设于第一表面(11)，绝缘层(2)设有第一通孔(2a)以及安装孔(2b)，第一通孔(2a)对应第一接电部(5)的位置，以暴露至少部分第一接电部(5)，安装孔(2b)与第一通孔(2a)间隔设置。导电层(3)设于绝缘层(2)的背离第一表面(11)的一侧面，导电层(3)电连接于第一接电部(5)，导电层(3)具有镂空部(3a)，镂空部(3a)对应且连通于安装孔(2b)。沿晶粒(1)至导电层(3)的方向上，被植入元件(4)至少部分安装于镂空部(3a)和安装孔(2b)中，被植入元件(4)电连接于导电层(3)。本公开公开的芯片结构、芯片结构的封装方法及电路板模组，在实现芯片结构功能需求的同时，实现芯片结构的小型化设计。

Description

芯片结构、芯片结构的封装方法及电路板模组
相关交叉引用
本公开要求于2022年5月16日提交中国专利局、申请号为202210527501X、发明名称为“芯片结构、芯片结构的封装方法以及电路板模组”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及芯片结构、芯片结构的封装方法以及电路板模组。
背景技术
随着技术的发展，由于各种电子设备的功能需求越来越多，用于支撑电子设备实现不同功能的芯片结构的功能集成度也越来越高。但是，芯片结构集成的功能越多，可能会导致芯片结构的尺寸也会相应增大。目前，为了实现芯片结构的多功能和小型化设计，通常会采用系统级封装，即3D堆叠封装，但是芯片结构在厚度上也会受到限制。
发明内容
(一)要解决的技术问题
在现有技术中，为了实现芯片结构的多功能和小型化设计，通常会采用系统级封装，即3D堆叠封装，但是随着对芯片功能要求越来越多，采用3D堆叠封装时，会使得芯片结构的整体厚度变高，不利于实现芯片结构的小型化设计。
(二)技术方案
根据本公开公开的各种实施例，提供一种芯片结构、芯片结构的封装方法及电路板模组。
一种芯片结构，包括：
晶粒，所述晶粒具有第一表面，所述第一表面上设有第一接电部；
绝缘层，所述绝缘层设于所述第一表面，所述绝缘层设有第一通孔以及安装孔，所述第一通孔对应所述第一接电部的位置，以暴露至少部分所述第一接电部，所述安装孔与所述第一通孔间隔设置；
导电层，所述导电层设于所述绝缘层的背离所述第一表面的一侧面，所述导电层电连接于所述第一接电部，所述导电层具有镂空部，所述镂空部对应且连通于所述安装孔；以及
被植入元件，沿所述晶粒至所述导电层的方向上，所述被植入元件至少部分安装于所述镂空部和所述安装孔中，且所述被植入元件电连接于所述导电层。
作为本公开实施例一种可选的实施方式，所述芯片结构还包括：所述第一表面还设有第二接电部，所述第二接电部位于所述安装孔中，所述第二接电部电连接于所述导电层以及所述被植入元件。
作为本公开实施例一种可选的实施方式，所述芯片结构还包括：所述导电层包括多层，多层所述导电层层叠设置，相邻的两层所述导电层之间设有所述绝缘层，位于相邻的两层所述导电层之间的所述绝缘层上还设有第二通孔，将所述第二通孔配置成供相邻的两层所述导电层连接以实现电导通。
作为本公开实施例一种可选的实施方式，所述芯片结构还包括：多层所述导电层至少包括相邻设置的第一导电层和第二导电层，沿所述晶粒向所述导电层的方向上，所述第二导电层位于所述第一导电层的背离所述晶粒的一侧，所述第二导电层、所述第一导电层均具有所述镂空部，且所述第二导电层上的所述镂空部与所述第一导电层上的所述镂空部对应且连通；
位于所述第一导电层和所述第二导电层之间的所述绝缘层还设有第二接电部，所述第二接电部位于所述安装孔中，所述第二接电部电连接于所述第一导电层和/或所述第二导电层；
所述被植入元件还电连接于所述第二接电部。
作为本公开实施例一种可选的实施方式，所述芯片结构还包括：所述绝缘层为多层，多层所述绝缘层至少包括设于所述第一表面的第一绝缘层以及设于相邻的两层所述导电层之间的第二绝缘层，所述安装孔、所述第二通孔设于所述第二绝缘层。
作为本公开实施例一种可选的实施方式，所述芯片结构还包括：所述芯片结构还包括金属球，所述金属球设于所述导电层的背离所述绝缘层的一侧，所述金属球电连接于所述导电层。
作为本公开实施例一种可选的实施方式，所述芯片结构还包括：所述芯片结构还包括支撑部，所述支撑部电连接于所述导电层，所述支撑部包括端面和设于端面且相对设置的第一凸起部和第二凸起部，所述第一凸起部、所述第二凸起部自所述端面背离所述导电层延伸，所述金属球夹持并电连接于所述第一凸起部、所述第二凸起部以及所述端面之间。
作为本公开实施例一种可选的实施方式，所述芯片结构还包括：所述第一凸起部、所述第二凸起部的相互朝向的表面为倾斜表面。
作为本公开实施例一种可选的实施方式，所述芯片结构还包括：所述晶粒还具有第二表面以及外周面，所述第二表面与所述第一表面相背设置，所述外周面连接于所述第一表面和所述第二表面；
所述芯片结构还包括塑封层，所述塑封层包覆于所述外周面和所述第二表面。
一种芯片结构的封装方法，将所述封装方法配置成制作芯片结构的方法，所述封装方法包括：
在晶粒的第一表面设置第一接电部，并在所述第一表面覆盖第一绝缘层；
去除部分所述第一绝缘层，暴露至少部分所述第一接电部；
在所述第一接电部的背离所述晶粒的一侧面覆盖第一导电层，使所述第一导电层覆盖所述第一绝缘层和所述第一接电部，所述第一导电层电连接于所述第一接电部；
在所述第一导电层上设置镂空部，所述镂空部对应于去除部分所述第一绝缘层的位置；
将被植入元件植入所述镂空部，所述被植入元件电连接于所述第一导电层。
作为本公开实施例一种可选的实施方式，所述芯片结构还包括第二绝缘层和第二导电层，所述封装方法还包括：
在所述第一导电层背离所述第一绝缘层的一侧设置所述第二绝缘层，使所述第二绝缘层覆盖所述第一导电层以及所述镂空部；
去除部分所述第二绝缘层，暴露至少部分所述第一导电层；
在所述第二绝缘层的背离所述第一导电层的一侧设置所述第二导电层，使所述第二导电层与暴露的所述第一导电层电连接；
去除所述镂空部处的所述第二绝缘层，将被植入元件植入所述镂空部，并使所述被植入元件电连接于所述第一导电层和/或所述第二导电层。
作为本公开实施例一种可选的实施方式，所述封装方法还包括：
在所述第二导电层的背离所述第二绝缘层的一侧设置支撑部，所述支撑部电连接于所述第二导电层，并在所述支撑部的背离所述第二导电层的一侧设置金属球，所述金属球通过所述支撑部电连接于所述第二导电层。
作为本公开实施例一种可选的实施方式，所述封装方法还包括：
在所述晶粒的与所述第一表面相背的第二表面以及连接于所述第一表面和所述第二表面的外周面进行塑封。
作为本公开实施例一种可选的实施方式，所述去除部分所述第一绝缘层，以暴露至少部分所述第一接电部的方式为：
采用激光蚀刻或化学蚀刻去除部分所述第一绝缘层，以暴露至少部分所述第一接电部。
一种电路板模组，包括电路板和如上述第一方面所述的芯片结构，所述电路板设于所述导电层的背离所述晶粒的一侧，所述电路板电连接于所述导电层。
作为本公开实施例一种可选的实施方式，所述电路板模组还包括：所述芯片结构包括金属球，且沿所述晶粒向所述导电层的方向上，所述被植入元件突出于所述金属球时，所述电路板的朝向所述导电层的一侧对应所述被植入元件设有避让结构，将所述避让结构配置成避让所述被植入元件。
本公开的其他特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本公开而了解。本公开的目的和其他优点在说明书、权利要求书以及附图中所特别指出的结构来实现和获得，本公开的一个或多个实施例的细节在下面的附图和描述中提出。
为使本公开的上述目的、特征和优点能更明显易懂，下文特举可选实施例，并配合所附附图，作详细说明如下。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用来解释本公开的原理。
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，对于本领域普通技术人员而言，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一个或多个实施例提供的芯片结构(具有一层导电层)的结构示意图；
图2为本公开一个或多个实施例提供的芯片结构(具有多层导电层)的结构示意图；
图3为本公开一个或多个实施例提供的具有多层导电层的芯片结构的封装示意图；
图4为本公开一个或多个实施例提供的封装方法的一种流程图；
图5为本公开一个或多个实施例提供的封装方法的另一种流程图；
图6为本公开一个或多个实施例提供的电路板模组的结构示意图。
具体实施方式
为了能够更清楚地理解本公开的上述目的、特征和优点，下面将对本公开的 方案进行进一步描述。需要说明的是，在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合。
在下面的描述中阐述了很多具体细节以便于充分理解本公开，但本公开还可以采用其他不同于在此描述的方式来实施；显然，说明书中的实施例只是本公开的一部分实施例，而不是全部的实施例。
本公开的说明书和权利要求书中的术语“第一”和“第二”等是用来区别不同的对象，而不是用来描述对象的特定顺序。例如，第一摄像头和第二摄像头是为了区别不同的摄像头，而不是为了描述摄像头的特定顺序。
在本公开实施例中，“示例性的”或者“例如”等词来表示作例子、例证或说明。本公开实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念，此外，在本公开实施例的描述中，除非另有说明，“多个”的含义是指两个或两个以上。
图1为本公开一个或多个实施例提供的芯片结构(具有一层导电层)的结构示意图；图2为本公开一个或多个实施例提供的芯片结构(具有多层导电层)的结构示意图，即图2是在图1所示的实施例的基础上，对本公开的另一种可实现方式的描述，其中图2中的(a)示出了具有两层导电层的芯片结构的结构示意图，图2中的(b)示出了具有三层导电层的芯片结构的结构示意图；图3为本公开一个或多个实施例提供的具有多层导电层的芯片结构的封装示意图，其中图3中的(a)至(f)提供了一个或多个实施例中具有多层导电层的芯片结构在封装过程中的结构变化过程。
请结合图1至图3，本公开实施例提供了一种芯片结构100，该芯片结构100包括晶粒1、绝缘层2、导电层3以及被植入元件4。晶粒1具有第一表面11，第一表面11上设有第一接电部5；绝缘层2设于第一表面11，绝缘层2设有第一通孔2a以及安装孔2b，第一通孔2a对应第一接电部5的位置，以暴露至少部分第一接电部5，安装孔2b与第一通孔2a为间隔设置。导电层3设于绝缘层2的背离第一表面11的一侧面，导电层3电连接于第一接电部5，同时导电层3具有镂空部3a，镂空部3a对应且连通于安装孔2b。在沿晶粒1至导电层3的方向上，被植入元件4至少部分位于安装孔2b和镂空部3a中，且被植入元件4电连接于导电层3。
考虑到芯片结构100在进行设计的过程中，在芯片功能多样性的要求下，会导致芯片结构100上的导电线路的设计较为复杂。同时，为了实现芯片结构100的小型化，可以考虑将芯片结构100的导电线路沿晶粒1的厚度方向层叠设置，从而可以有效减小芯片结构100的表面积。基于此，本公开通过设置绝缘层2以实现第一接电部5以及导电层3在不需要电连接的位置保持绝缘；与此同时，通过在绝缘层2上设置第一通孔2a，使得第一接电部5与导电层3在需要的位置进行电连接，从而使得第一接电部5与导电层3的导电线路的布置能够满足设计要求。
在一个实施例中，考虑到晶粒1、第一接电部5、绝缘层2以及导电层3在晶粒1的厚度方向的层叠设置虽然可以减小芯片结构100的表面积，但是会使得芯片结构100的整体厚度有所增加。同时，由于芯片结构100中还需要设置一些被植入元件4来实现芯片结构100的一些功能，而被植入元件4的自身厚度要明显厚于绝缘层2和导电层3，当将被植入元件4电连接于导电层3时，会使得芯片结构100的厚度明显增加。
基于此，本公开还进一步通过在导电层3上设置镂空部3a，并在绝缘层2上设置与镂空部3a对应且连通的安装孔2b，以将被植入元件4安装于该安装孔2b，从而使得被植入元件4在沿晶粒1至导电层3的方向上的至少部分位于安装孔2b和镂空部3a中，此时被植入元件4凸出于导电层3的部分的厚度变小，从而可以有效减小被植入元件4对芯片结构100的整体尺寸的影响，以进一步实现芯片结构100的小型化设计。
可以理解的是，上述的各个结构的厚度是指晶粒1、绝缘层2、导电层3以及被植入元件4在沿晶粒1至导电层3的方向的上尺寸(如图1中的X方向)。
其中，第一接电部5可以是焊点、焊盘、引脚等。被植入元件4可以包括但不局限于电容、电感、电阻或是需要电连接于芯片结构100以实现芯片结构100的功能需求的器件等，在本实施例中对第一接电部5、被植入元件4的种类不作限定。
在一个实施例中，上述第一接电部5、第一通孔2a、镂空部3a、安装孔2b以及被植入元件4的数量可以为多个，且镂空部3a以及安装孔2b可以位于中部位置，也可以位于边缘位置。同时，当被植入元件4为多个时，镂空部3a以及安装孔2b的数量可以配合被植入元件4的数量设置，即，每一个镂空部3a和安装孔2b中同时设置一个被植入元件4，或者，也可以是在一个镂空部3a和安装孔2b中设置多个被植入元件4。
可以理解的是，第一通孔2a实现第一接电部5与导电层3之间的电连接方式可包括但不局限于：该导电层3延伸至第一通孔2a中并与第一接电部5直接接触以实现电连接，或者，在该第一通孔2a中设置导电件(例如金属柱、柔性线路板、导电线等)，利用该导电件的一端连接于导电层3，另一端连接于第一接电部5以实现该导电层3与第一接电部5的电连接。
本实施例以该导电层3延伸至第一通孔2a中并与第一接电部5直接接触以实现电连接为例进行说明。
考虑到由于第一通孔2a需要实现第一接电部5与导电层3之间的电连接，基于此，为了便于导电层3延伸至该第一通孔2a中，一些实施例中，第一通孔2a具有倾斜设置的壁面，以使得第一通孔2a的孔径沿晶粒1至导电层3的方向(如图1中的X方向)逐渐增大，从而在第一通孔2a设置导电层3时能够起到导向作用，以便于导电层3与第一接电部5之间的电连接。可以理解的是，第一通孔2a的数量和设置位置可以根据芯片结构100的导电线路要求进行调整，在本实施例中不作具体限定。
可选地，第一通孔2a可以采用激光蚀刻、化学蚀刻或其他通过去除绝缘层2的材料的方式形成，在本实施例中对第一通孔2a的具体实施方式不作限定。
可选地，该导电层3上的镂空部3a可由在形成该导电层3的导电线路或导电图案时一并形成，即，该导电层3形成后，该镂空部3a同步形成。当然，可以理解的是，在其他实施例中，该镂空部3a也可在该导电层3形成后，再去除该导电层3的部分材料形成。
可选地，由于被植入元件4安装于安装孔2b，为了方便被植入元件4的安装，安装孔2b具有倾斜设置的壁面，以使得安装孔2b的开口沿晶粒1至导电层3的方向(如图1中的X方向)逐渐增大，从而便于被植入元件4的安装。
可选地，安装孔2b可以由激光蚀刻或化学蚀刻或其他通过去除绝缘层的材料形成，在本实施例中对安装孔2b的具体实施方式不作限定。
可选地，该导电层3可根据实际功能需求设置为一层或者是多层，当导电层3 为多层时，可以实现在芯片结构100的表面积有限的情况下，增加芯片结构100的线路布置面积，以满足芯片结构100的功能需求。
在一个实施例中，当该导电层3为一层(如图1所示)，且该被植入元件4的电连接位置在朝向第一表面11的一侧时，为了便于被植入元件4与导电层3之间的电连接，可在第一表面11上设有第二接电部6，第二接电部6位于安装孔2b中，第二接电部6电连接于导电层3以及被植入元件4。这样，通过在第一表面11上设置第二接电部6，并通过第二接电部6电连接于导电层3，能够便于实现被植入元件4与导电层3之间的电连接。
此外，考虑到由于两个需要进行电连接的结构，其进行电连接位置的连接结构需要相互对应才能够实现二者之间的电连接。即若芯片结构100上与被植入元件4进行电连接的接电结构是固定的，那么芯片结构100能够连接的被植入元件4的种类就会受限。因此，本公开通过在第一表面11上还设置第二接电部6，第二接电部6的类型和位置可对应需要电连接的被植入元件4的接电结构进行设计，即，第二接电部6的类型、位置都可以灵活调整，这样适配于不同的被植入元件4，以使得芯片结构100能够连接各种被植入元件4，从而有利于拓展芯片结构100的不同功能的实现。
可选地，第二接电部6可以是焊点，也可以是焊盘等其他可以实现被植入元件4与导电层3之间的电连接的接电部件，在本实施例中对第二接电部6的具体结构不作限定。
当然，若被植入元件4的电连接位置位于其自身的外周面时，此时将被植入元件4设置在镂空部3a内的部分外周面直接与导电层3接触以实现电连接，则无需额外设置第二接电部6，这样能够简化芯片结构100的导电线路的设计。
在一个实施例中，导电层3包括多层(如图2、图3所示)，且多层导电层3之间层叠设置时，相邻的两层导电层3之间设有该绝缘层2，以通过绝缘层2实现相邻两层导电层3之间不需要进行电导通的位置的绝缘连接。相应的，在绝缘层2上设有第二通孔2c，以通过第二通孔2c实现相邻的两层导电层3之间需要的位置的电导通。
可以理解的是，该相邻的两层导电层3之间通过第二通孔2c实现电连接导通的方式可包括但不局限于：相邻的两层导电层3中，其中一层导电层3延伸至第二通孔2c中并与另一层导电层3直接接触以实现电连接，或者，在该第二通孔2c中设置导电件(例如金属柱、柔性线路板、导电线等)，利用该导电件的一端连接于其中一层导电层3，另一端连接于另一层导电层3以实现该相邻的两层导电层3的电连接。
可选地，由于第二通孔2c需要实现相邻两层导电层3之间的电连接，为了便于导电层3的布置，第二通孔2c具有倾斜设置的壁面，以使得第二通孔2c开口沿晶粒1至导电层3的方向(如图1中的X方向)逐渐增大，从而在第二通孔2c设置导电层3时能够起到导向作用，以便于实现相邻两层导电层3之间的电连接。可以理解的是，第二通孔2c的数量和设置位置可以根据芯片结构100的导电线路要求进行调整，在本实施例中不作具体限定。
当导电层3具有多层时，一种示例中，以导电层3为两层为例(如图2中的(a)所示)，导电层3包括相邻设置的第一导电层31和第二导电层32，沿晶粒1向导电层3的方向上，第二导电层32位于第一导电层31的背离晶粒1的一侧，第二导电层32、第一导电层31均具有镂空部3a(参见图3中的(c))，且第二导电层32上的镂空部3a与第一导电层31上的镂空部3a对应且连通。此时绝缘层2 也有两层，绝缘层2包括位于第一表面11的第一绝缘层21和位于第一导电层31、第二导电层32之间的第二绝缘层22。第二绝缘层22上的安装孔2b与第一导电层31和第二导电层32的镂空部3a对应且连通。当被植入元件4通过第二接电部6与导电层3电连接时，此时，第二接电部6可设于第一绝缘层21的背离第一表面11的一侧，且位于第一导电层31和第二导电层32之间的绝缘层2的安装孔2b中，该第二接电部6可即被植入元件4电连接于第二接电部6。
可以理解的是，此时，第二接电部6可以电连接于第一导电层31，以实现被植入元件4与第一导电层31的电连接；或者，第二接电部6可以电连接于第二导电层32，以实现被植入元件4与第二导电层32的电连接；或者，第二接电部6可以同时电连接于第一导电层31和第二导电层32，以实现被植入元件4同时与第一导电层31和第二导电层32的电连接。可以理解的是，第二接电部6与第一导电层31和第二导电层32的电连接方式可以根据导电线路的需要进行选择，在本实施例中不作具体限定。
另一种示例中，当导电层3为三层时(如图2中的(b)所示)，导电层3包括第一导电层31、第二导电层32和第三导电层33，沿晶粒1向导电层3的方向上，第二导电层32位于第一导电层31的背离晶粒1的一侧，第三导电层33位于第二导电层32背离第一导线层的一侧。此时，绝缘层2也有三层，绝缘层2包括位于第一表面11的第一绝缘层21，位于第一导电层31、第二导电层32之间的第二导电层32，位于第二导电层32与第三导电层33之间的第三绝缘层23。同时，第二绝缘层22上的安装孔2b与第三绝缘层23上的安装孔2b对应且连通设置，并与第一导电层31、第二导电层32、第三导电层33上的镂空部3a(参见图3中的(c))对应且连通设置。第二接电部6位于第二绝缘层22的安装孔2b中并位于第一绝缘层21的背离第一表面11的一侧，被植入元件4位于安装孔2b中并电连接于第二接电部6，且第二接电部6可以根据导电线路的需要电连接于任意一层导电层3或两层导电层3，甚至同时电连接于三层导电层3，在本实施例中不作限定。
上述的导电层3为两层和三层时，被植入元件4的设置位置只是一种示例。即，当导电层3为多层时，被植入元件4可以安装到一层导电层3和绝缘层2中，或者，被植入元件4也可以安装到多层导电层3和绝缘层2中，此时能够更大程度地避免被植入元件4的厚度对芯片结构100的整体厚度的影响。可以理解的是，当导电层3具有更多层时，被植入元件4的位置可以根据实际需要进行调整，在本实施例中不作限定。
请再次一并参阅图1至图3，在一个实施例中，为了实现芯片结构100与其他器件的电连接，芯片结构100还包括金属球7，金属球7可采用植球工艺设于导电层3的背离绝缘层2的一侧，金属球7电连接于导电层3。在两个器件之间，金属球7的电连接方式更容易实现不同器件组合之后的整体结构的小型化设计。
示例性的，金属球7可以为具有导电性能的锡球、铜球、银球或其他金属材料，在本实施例中对金属球7的具体材料不作限定。
在一个实施例中，为了提高金属球7与导电层3的电连接的稳定性，芯片结构100还包括支撑部8，该支撑部8位于金属球7与导电层3之间，以使得金属球7通过支撑部8电连接于导电层3。受芯片结构100的功能需求的影响，导电层3与金属球7之间的连接面积可能会比较小，而由于金属球7的形状会使得金属球7与导电层3之间的电连接不稳定，因此通过在金属球7与导电层3之间增加支撑部8，能够提高金属球7与导电层3之间的电连接稳定性。
可选地，支撑部8可以是与金属球7材料相同的金属材料，也可以是与金属球7的材料不同的金属材料，也可以是具有导电功能的导电陶瓷等，在本实施例中对支撑部8不作具体限定。
在一个实施例中，支撑部8包括端面81和设于端面81且相对设置的第一凸起部82和第二凸起部83，第一凸起部82和第二凸起部83自端面81背离导电层3延伸以夹持金属球7，从而提高金属球7在支撑部8的端面81的连接稳定性，防止金属球7脱落于支撑部8。同时金属球7电连接于第一凸起部82、第二凸起部83以及端面81之间，以通过端面81、第一凸起部82以及第二凸起部83共同实现与金属球7的电连接，从而提高支撑部8与金属球7之间的电连接稳定性，进而提高金属球7与导电层3之间的电连接稳定性。
一种示例中，第一凸起部82与第二凸起部83可以是间隔相对设置，此时能够使得金属球7的受力更加均衡，以提高金属球7与第一凸起部82、第二凸起部83的连接稳定性。可以理解的是，第一凸起部82、第二凸起部83可以为一对间隔且相对设置，也可以是两对、三对或者更多对的间隔相对设置。
另一种示例中，该第一凸起部82与第二凸起部83也可以是相互连接且相对设置，此时第一凸起部82和第二凸起部83可以与端面81围合形成一个用于容纳金属球7的凹槽，以使得金属球7可以设置于该凹槽中，能够有效提高金属球7与支撑部8的连接稳定性以及电连接稳定性。
可选地，第一凸起部82、第二凸起部83的相互朝向的表面可以为倾斜表面，以在设置金属球7时实现对金属球7的导向作用，以进一步提高金属球7与支撑部8之间的连接稳定性。
在一个实施例中，由于芯片结构100所需的导电线路过于复杂，为了能够容纳更多的导电线路，晶粒1具有与第一表面11相对的第二表面12以及连接于第一表面11和第二表面12的外周面13。且芯片结构100还包括包覆于第二表面12和外周面13的塑封层9，设置于外周面13外周的塑封层9还可以用于承载部分导电线路，即晶粒1可以采用扇出式的封装工艺，从而在保持塑封可靠性以及实现塑封层9对晶粒实现有效保护的前提下，塑封层9还能够扩大晶粒1的可用于承载导电线路的面积，如第一接电部5，有利于为导电线路的设计提供更多的空间。
示例性的，塑封层9的材料可以是聚合树脂材料，如味之素内置膜(Ajinomoto Build-up Film-ABF)、苯并环丁烯(BCB)、双马来酰亚胺三嗪(BT)、环氧树脂、聚酯、聚酰亚胺和/或聚四氟乙烯。或者塑封层9的材料还可以是用于聚合树脂材料的加固材料，例如玻璃纤维加固材料。
本实施例提供的芯片结构100通过将导电层3、绝缘层2沿晶粒1的厚度方向层叠设置，从而实现芯片结构100的小型化封装。此外，由于在绝缘层2的导电层3上设有连通的安装孔2b和镂空部3a，从而可以使得被植入元件4设于安装孔2b中，以减小被植入元件4对芯片结构100的整体尺寸的影响，以进一步实现芯片结构100的小型化设计。
基于同一发明构思，作为对上述方法的实现，本公开实施例还提供了一种封装得到上述的芯片结构100的封装方法。
图4为本公开一个或多个实施例提供的封装方法的一种流程图，图5为本公开一个或多个实施例提供的封装方法的另一种流程图。请结合图3、图4和图5，芯片结构100的封装方法包括：
301、在晶粒1的第一表面11设置第一接电部5，并在第一表面11覆盖第一绝缘层21；
该步骤的目的是为了在晶粒1的第一表面11上设置该第一接电部5，以作为后续与第一导电层31的接电导通的基础。同时第一绝缘层21的设置能够实现第一接电部5与第一导电层31绝缘设置，从而避免第一接电部5对第一导电层31的设置。
可选地，该第一接电部5可以是金属或金属合金制成得到可包括但不局限于焊点、焊盘、引脚等，该第一接电部5设于第一表面11上时，可与第一表面11上的线路接触以实现电导通。
此外，该第一绝缘层21可以是聚合树脂材料，如味之素内置膜(Ajinomoto Build-up Film-ABF)、苯并环丁烯(BCB)、双马来酰亚胺三嗪(BT)、环氧树脂、聚酯、聚酰亚胺和/或聚四氟乙烯。或者该第一绝缘层21的材料还可以是用于聚合树脂材料的加固材料，例如玻璃纤维加固材料。
302、去除部分第一绝缘层21，暴露至少部分第一接电部5；
该步骤的目的是为了在第一绝缘层21上形成用于暴露至少部分第一接电部5的第一通孔2a和用于安装被植入元件4的安装孔2b。
303、在第一接电部5的背离晶粒1的一侧面覆盖第一导电层31，使第一导电层31覆盖第一绝缘层21和第一接电部5，第一导电层31电连接于第一接电部5；
该步骤的目的是实现第一导电层31与第一接电部5之间的电连接，即第一导电层31通过第一绝缘层21上的第一通孔2a实现与第一接电部5之间的电连接。
可选地，第一导电层31可以是单一金属材料或金属合金材料制成的，如铜、金、银以及铜合金等。
进一步地，第一通孔2a实现第一接电部5与第一导电层31之间的电连接方式可包括但不局限于：该第一导电层31延伸至第一通孔2a中并与第一接电部5直接接触以实现电连接，或者，在该第一通孔2a中设置导电件(例如金属柱、柔性线路板、导电线等)，利用该导电件的一端连接于第一导电层31，另一端连接于第一接电部5以实现该第一导电层31与第一接电部5的电连接。
304、在第一导电层31上设置镂空部3a，镂空部3a对应于去除部分第一绝缘层21的位置；
该步骤中形成的镂空部3a是为被植入元件4的设置提供设置位置，且镂空部3a对应于安装孔2b。
305、将被植入元件4植入镂空部3a以及去除部分第一绝缘层21的位置，被植入元件4电连接于第一导电层31。
由于镂空部3a对应于安装孔2b，当将被植入元件4安装于安装孔2b中时，被植入元件4可以直接与镂空部3a位置的第一导电层31电连接，或者可以在安装孔2b中设置第二接电部6，被植入元件4通过第二接电部6实现与第一导电层31的电连接。
在一个实施例中，当芯片结构100所需实现的功能不同时，芯片结构100通常会设置多层绝缘层2以及导电层3，当芯片结构100具有多层绝缘层2和导电层3时，上述封装方法还包括：
306、在第一导电层31背离第一绝缘层21的一侧设置第二绝缘层22，使第二绝缘层22覆盖第一导电层31以及镂空部3a；
该步骤的目的是为了实现芯片结构100的功能的多样性，即需要设置多层导电层时，第二绝缘层22可以实现第一导电层31与第二导电层32之间的绝缘设置，从而不影响第二导电层32的设置。
可以理解的是，第二绝缘层22的材料以及设置方式可以参照第一绝缘层21 的材料和设置方式，此处不再赘述。
307、去除部分第二绝缘层22，暴露至少部分第一导电层31；
该步骤的目的是为了在第二绝缘层22形成第二通孔2c，以通过第二通孔2c实现第二导电层32与第一导电层31的电连接。
308、在第二绝缘层22的背离第一导电层31的一侧设置第二导电层32，使第二导电层32与暴露的第一导电层31电连接；
该步骤的目的是为了实现第二导电层32与第一导电层31的电连接。
309、去除镂空部3a处的第二绝缘层22，将被植入元件4植入镂空部3a，并使被植入元件4电连接于第一导电层31或第二导电层32，或同时电连接于第一导电层31和第二导电层32。
该步骤的目的是当绝缘层2和导电层3具有多层时，可以使得第二绝缘层22上形成对应于镂空部3a的安装孔2b，从而使得第一绝缘层21的安装孔2b与第二绝缘层的安装孔2b对应，以便于被植入元件4安装于多层绝缘层2的安装孔2b和导电层3的镂空部3a中。进而可以使得被植入元件4同时嵌入多层导电层3和多层绝缘层2中，从而避免被植入元件4的设置对芯片结构100的整体尺寸，尤其是沿晶粒1至导电层3的方向的尺寸。
被植入元件4可以电连接于第一导电层31，也可以电连接于第二导电层32，还可以同时电连接于第一导电层31和第二导电层32，其具体连接方式可以根据实际需要进行选择，在本实施例中不作具体限定。
其中，上述封装方法的步骤306至步骤309可以在步骤304(在第一导电层31上设置镂空部3a)之后进行。
在一个实施例中，为了便于芯片结构100与其他结构进行电连接，同时实现整体结构的小型化，该封装方法还包括：
310、在第二导电层32的背离第二绝缘层22的一侧设置支撑部8，支撑部8电连接于第二导电层32，并在支撑部8的背离第二导电层32的一侧设置金属球7，金属球7通过支撑部8电连接于第二导电层32。
其中，该步骤可以在步骤308(第二绝缘层22的背离所述第一导电层31一侧设置第二导电层32)之后进行。
该步骤的目的是通过支撑部8的设置以提高金属球7与第二导电层32的电连接稳定性，此外该步骤中的金属球7的设置目的是为芯片结构100与其他电路板结构连接时提供电连接基础。
可选地，金属球7可以采用植球工艺连接于支撑部8，且金属球7的设置有利于实现芯片结构100与其他电路板结构连接时的小型化设置。支撑部8与金属球7可以采用相同的导电材料，如支撑部8与金属球7的材料均为铜；也可以采用不同的导电材料，如支撑部8的材料可以为金，金属球7的材料可以为铜。
示例性的，上述设置支撑部8和金属球7的步骤可以在步骤308之后、步骤309之前，或者在步骤309之后，但是不应在安装孔2b形成之后、被植入元件4安装之间进行植金属球7操作。若在安装孔2b形成后，先进行植金属球7操作，会在植金属球7过程中导致安装孔2b中掉落杂质，从而导致后续被植入元件4在安装孔2b内的安装受阻或电连接失效等情况，会影响芯片结构100的生产效率和生产质量。
可选地，当芯片结构100只有第一绝缘层21和第一导电层31时，芯片结构100的制作方法可以如图4所示，其中支撑部8和金属球7可以设置可以在步骤305之后；当芯片结构100具有第一绝缘层21、第一导电层31、第二绝缘层22、 第二导电层32时，芯片结构100的制作方法可以如图5所示，其中支撑部8和金属球7可以设置可以在步骤309之后；当芯片结构100的结构更复杂时，可以重复上述第一绝缘层21、第一导电层31、第二绝缘层22、第二导电层32的设置步骤，从而形成芯片结构100的多层结构，以满足芯片结构100的功能需求。且当第一绝缘层21、第一导电层31、第二绝缘层22、第二导电层32具有多层时，支撑部8和金属球7可以设置在最远离晶粒1的一层导电层3上，从而便于实现芯片结构100与其他结构的电连接。当然，在结构设计需要的情况下，支撑部8与金属球7的设置形式也可以如被植入元件4的设置形式，即通过嵌入式设计，从而进一步实现芯片结构100的小型化设计。
在一个实施例中，该封装方法还包括：
311、晶粒1具有第二表面12以及外周面13，第二表面12与第一表面11相背设置，外周面13连接于第一表面11和第二表面12，在第二表面12和外周面13设置有塑封层9；
其中，该步骤可以在步骤301(在晶粒1的第一表面11设置第一接电部5，并在第一表面11覆盖第一绝缘层21)之前进行。
该步骤的目的是通过塑封层9对晶粒1实现包裹保护，同时由于塑封层9具有与晶粒1的第一表面11齐平的表面，当在晶粒1的第一表面11设置第一接电部5时，若晶粒1的第一表面11空间不足，可以将第一接电部5同时设于晶粒1和塑封层9上，从而可以提高芯片结构100的导电线路的布线空间。
可选地，上述塑封层9的材料可以是聚合树脂材料，如味之素内置膜(Ajinomoto Build-up Film-ABF)、苯并环丁烯(BCB)、双马来酰亚胺三嗪(BT)、环氧树脂、聚酯、聚酰亚胺和/或聚四氟乙烯。或者塑封层9的材料还可以是用于聚合树脂材料的加固材料，例如玻璃纤维加固材料。
在一个实施例中，上述去除部分第一绝缘层21，以暴露至少部分第一接电部5的方式为：
采用激光蚀刻或化学蚀刻去除第一绝缘层21对应第一接电部5的部分材料，以形成第一通孔2a和安装孔2b。其中，通过激光蚀刻的方法能够提高加工精度，还能够提高加工效率。采用化学蚀刻的方法能够实现对第一导电层31的保护，从而避免对第一导电层31造成损坏。
进一步地，去除部分第二绝缘层22，暴露至少部分第一导电层31的方法也可采用例如化学蚀刻、激光蚀刻或者是其他去除该部分材料的方式实现，从而使得该第二绝缘层22形成第二通孔2c和安装孔2b。镂空部3a可由在形成该第一导电层31的导电线路或导电图案时一并形成，即，该第一导电层31形成后，该镂空部3a同步形成。当然，可以理解的是，在其他实施例中，该镂空部3a也可在该第一导电层31形成后，再去除该第一导电层31的部分材料形成。
基于同一发明构思，作为对上述方法的实现，本公开实施例还提供了一种电路板模组200。
图6为本公开一个或多个实施例提供的电路板模组的结构示意图，请参阅图6，本公开实施例提供的电路板模组200包括电路板210和上述所述的芯片结构100，电路板210位于导电层3的背离晶粒1的一侧，且电路板210电连接于导电层3。具有上述芯片结构100的电路板模组200，在实现功能多样性的同时能够实现电路板模组200的小型化设计。
在一个实施例中，当芯片结构100包括金属球7，且沿晶粒1向导电层3的方向上，被植入元件4突出于金属球7时，电路板210的朝向导电层3的一侧对应 被植入元件4设有避让结构211，以避让被植入元件4。这样，在电路板210跟被植入元件4的安装连接时，能够避免二者出现干涉的情况，有效确保电路板210与被植入元件4的安装可靠性，同时避让结构211的设置能够减少电路板模组200沿电路板210厚度方向上的整体厚度，使得电路板模组200整体结构更加紧凑。
可选地，该避让结构211可以为设于电路板210上的凹槽，也可以是通孔，或者是电路板210的表面上形成的凹陷等，其具体形式可以根据实际情况选择，在本实施例中不作限定。
可以理解的是，芯片结构100上未设置金属球7时，芯片结构100与电路板210也可以通过导电线路进行电连接，如打金线等；还可以通过柔性电路板进行电连接，在本实施例中对芯片结构100与电路板210的具体连接方式不作限定。
在一个实施例中，当芯片结构100包括金属球7时，为了提高金属球7与导电层3的电连接稳定性，还可以在导电层3与金属球7之间设置支撑部8。具体地，支撑部8的设置方式可以参照上述第一方面所述的支撑部8的结构，此处不再赘述。
本公开实施例提供的电路板模组200，在实现功能多样性的同时还能够实现小型化设计
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上实施例仅表达了本公开的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本公开构思的前提下，还可以做出若干变形和改进，这些都属于本公开的保护范围。因此，本公开专利的保护范围应以所附权利要求为准。
工业实用性
本公开提供的芯片结构、芯片结构的封装方法及电路板模组，通过沿晶粒的厚度方向上的一侧堆叠导电层，并利用绝缘层实现导电结构之间的绝缘连接，从而使得芯片结构在满足线路布置需求的同时实现小型化。同时，由于被植入元件至少部分设于镂空部和安装孔中，此时可以减小被植入元件在导电层上的凸出高度，即可以减小芯片结构的整体厚度，能够进一步实现芯片结构的小型化设计，具有很强的工业实用性。

Claims (16)

  1. 一种芯片结构，包括：
    晶粒，所述晶粒具有第一表面，所述第一表面上设有第一接电部；
    绝缘层，所述绝缘层设于所述第一表面，所述绝缘层设有第一通孔以及安装孔，所述第一通孔对应所述第一接电部的位置，以暴露至少部分所述第一接电部，所述安装孔与所述第一通孔间隔设置；
    导电层，所述导电层设于所述绝缘层的背离所述第一表面的一侧面，所述导电层电连接于所述第一接电部，所述导电层具有镂空部，所述镂空部对应且连通于所述安装孔；以及
    被植入元件，沿所述晶粒至所述导电层的方向上，所述被植入元件至少部分安装于所述镂空部和所述安装孔中，且所述被植入元件电连接于所述导电层。
  2. 根据权利要求1所述的芯片结构，其中，所述第一表面还设有第二接电部，所述第二接电部位于所述安装孔中，所述第二接电部电连接于所述导电层以及所述被植入元件。
  3. 根据权利要求1所述的芯片结构，其中，所述导电层包括多层，多层所述导电层层叠设置，相邻的两层所述导电层之间设有所述绝缘层，位于相邻的两层所述导电层之间的所述绝缘层上还设有第二通孔，将所述第二通孔配置成供相邻的两层所述导电层连接以实现电导通。
  4. 根据权利要求3所述的芯片结构，其中，多层所述导电层至少包括相邻设置的第一导电层和第二导电层，沿所述晶粒向所述导电层的方向上，所述第二导电层位于所述第一导电层的背离所述晶粒的一侧，所述第二导电层、所述第一导电层均具有所述镂空部，且所述第二导电层上的所述镂空部与所述第一导电层上的所述镂空部对应且连通；
    位于所述第一导电层和所述第二导电层之间的所述绝缘层还设有第二接电部，所述第二接电部位于所述安装孔中，所述第二接电部电连接于所述第一导电层和/或所述第二导电层；
    所述被植入元件还电连接于所述第二接电部。
  5. 根据权利要求3所述的芯片结构，其中，所述绝缘层为多层，多层所述绝缘层至少包括设于所述第一表面的第一绝缘层以及设于相邻的两层所述导电层之间的第二绝缘层，所述安装孔、所述第二通孔设于所述第二绝缘层。
  6. 根据权利要求1-5任一项所述的芯片结构，其中，所述芯片结构还包括金属球，所述金属球设于所述导电层的背离所述绝缘层的一侧，所述金属球电连接于所述导电层。
  7. 根据权利要求6所述的芯片结构，其中，所述芯片结构还包括支撑部，所述支撑部电连接于所述导电层，所述支撑部包括端面和设于端面且相对设置的第一凸起部和第二凸起部，所述第一凸起部、所述第二凸起部自所述端面背离所述导电层延伸，所述金属球夹持并电连接于所述第一凸起部、所述第二凸起部以及所述端面之间。
  8. 根据权利要求7所述的芯片结构，其中，所述第一凸起部、所述第二凸起部的相互朝向的表面为倾斜表面。
  9. 根据权利要求1-5任一项所述的芯片结构，其中，所述晶粒还具有第二表面以及外周面，所述第二表面与所述第一表面相背设置，所述外周面连接于所述第一表面和所述第二表面；
    所述芯片结构还包括塑封层，所述塑封层包覆于所述外周面和所述第二表面。
  10. 一种芯片结构的封装方法，将所述封装方法配置成制作芯片结构的方法，所述封装方法包括：
    在晶粒的第一表面设置第一接电部，并在所述第一表面覆盖第一绝缘层；
    去除部分所述第一绝缘层，暴露至少部分所述第一接电部；
    在所述第一接电部的背离所述晶粒的一侧面覆盖第一导电层，使所述第一导电层覆盖所述第一绝缘层和所述第一接电部，所述第一导电层电连接于所述第一接电部；
    在所述第一导电层上设置镂空部，所述镂空部对应于去除部分所述第一绝缘层的位置；
    将被植入元件植入所述镂空部，使所述被植入元件电连接于所述第一导电层。
  11. 根据权利要求10所述的封装方法，其中，所述芯片结构还包括第二绝缘层和第二导电层，所述封装方法还包括：
    在所述第一导电层背离所述第一绝缘层的一侧设置所述第二绝缘层，使所述第二绝缘层覆盖所述第一导电层以及所述镂空部；
    去除部分所述第二绝缘层，暴露至少部分所述第一导电层；
    在所述第二绝缘层的背离所述第一导电层的一侧设置所述第二导电层，使所述第二导电层与暴露的所述第一导电层电连接；
    去除所述镂空部处的所述第二绝缘层，将被植入元件植入所述镂空部，并使所述被植入元件电连接于所述第一导电层和/或所述第二导电层。
  12. 根据权利要求11所述的封装方法，其中，所述封装方法还包括：
    在所述第二导电层的背离所述第二绝缘层的一侧设置支撑部，所述支撑部电连接于所述第二导电层，并在所述支撑部的背离所述第二导电层的一侧设置金属球，所述金属球通过所述支撑部电连接于所述第二导电层。
  13. 根据权利要求10-12任一项所述的封装方法，其中，所述封装方法还包括：
    在所述晶粒的与所述第一表面相背的第二表面以及连接于所述第一表面和所述第二表面的外周面进行塑封。
  14. 根据权利要求10-12任一项所述的封装方法，其中，所述去除部分所述第一绝缘层，以暴露至少部分所述第一接电部的方式为：
    采用激光蚀刻或化学蚀刻去除部分所述第一绝缘层，以暴露至少部分所述第一接电部。
  15. 一种电路板模组，其中，包括电路板和如权利要求1-9任一项所述的芯片结构，所述电路板电连接于所述导电层。
  16. 根据权利要求15所述的电路板模组，其中，所述电路板对应所述被植入元件处设有避让结构，将所述避让结构配置成避让所述被植入元件。
PCT/CN2022/098896 2022-05-16 2022-06-15 芯片结构、芯片结构的封装方法及电路板模组 WO2023221215A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130181341A1 (en) * 2012-01-14 2013-07-18 Wan-Ling Yu Semiconductor package structure and method for manufacturing the same
CN105097492A (zh) * 2014-05-16 2015-11-25 中芯国际集成电路制造(上海)有限公司 芯片制造工艺和芯片
CN109640521A (zh) * 2018-11-20 2019-04-16 奥特斯科技(重庆)有限公司 制造具有嵌入式集群的部件承载件的方法以及部件承载件
CN113707566A (zh) * 2021-08-16 2021-11-26 矽磐微电子(重庆)有限公司 半导体结构的制造方法及半导体结构

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008160158A (ja) * 2008-03-21 2008-07-10 Fujitsu Ltd 半導体装置
US20170098628A1 (en) * 2015-10-05 2017-04-06 Mediatek Inc. Semiconductor package structure and method for forming the same
CN206312887U (zh) * 2016-12-06 2017-07-07 苏州源戍微电子科技有限公司 带有封闭空腔的芯片嵌入式封装结构
CN106876290A (zh) * 2017-03-10 2017-06-20 三星半导体(中国)研究开发有限公司 晶圆级扇出型封装件及其制造方法
KR20210105255A (ko) * 2020-02-18 2021-08-26 삼성전자주식회사 반도체 패키지, 및 이를 가지는 패키지 온 패키지

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130181341A1 (en) * 2012-01-14 2013-07-18 Wan-Ling Yu Semiconductor package structure and method for manufacturing the same
CN105097492A (zh) * 2014-05-16 2015-11-25 中芯国际集成电路制造(上海)有限公司 芯片制造工艺和芯片
CN109640521A (zh) * 2018-11-20 2019-04-16 奥特斯科技(重庆)有限公司 制造具有嵌入式集群的部件承载件的方法以及部件承载件
CN113707566A (zh) * 2021-08-16 2021-11-26 矽磐微电子(重庆)有限公司 半导体结构的制造方法及半导体结构

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