WO2023216693A1 - 一种三维集成电路及其制造方法 - Google Patents

一种三维集成电路及其制造方法 Download PDF

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Publication number
WO2023216693A1
WO2023216693A1 PCT/CN2023/079911 CN2023079911W WO2023216693A1 WO 2023216693 A1 WO2023216693 A1 WO 2023216693A1 CN 2023079911 W CN2023079911 W CN 2023079911W WO 2023216693 A1 WO2023216693 A1 WO 2023216693A1
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WIPO (PCT)
Prior art keywords
circuit
layer
power gating
power
metal interconnection
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PCT/CN2023/079911
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English (en)
French (fr)
Inventor
李泠
杨冠华
卢文栋
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中国科学院微电子研究所
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Publication of WO2023216693A1 publication Critical patent/WO2023216693A1/zh

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    • H01L27/0688—
    • H01L21/8256—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a three-dimensional integrated circuit and a manufacturing method thereof.
  • Power gating technology uses a switching transistor to turn off the connection between the internal circuit and the power supply or the connection between the internal circuit and the ground when the circuit is in a standby state to achieve a static state of turning off the power supply to the internal circuit.
  • Low power consumption technology uses a switching transistor to turn off the connection between the internal circuit and the power supply or the connection between the internal circuit and the ground when the circuit is in a standby state to achieve a static state of turning off the power supply to the internal circuit.
  • the object of the present invention is to provide a three-dimensional integrated circuit and a manufacturing method thereof, which are used to improve the performance of the integrated circuit on the premise that the integrated circuit includes a power gating circuit.
  • the present invention provides a three-dimensional integrated circuit, which includes: a substrate, a front-end circuit formed on the substrate, a back-end metal interconnection layer, and a back-end power gating circuit.
  • the back-end metal interconnect layer is formed on the front-end circuit.
  • the back-end power gating circuit is located in the back-end metal interconnect layer.
  • the front-end circuit is electrically connected to the power supply or ground wire through the back-end metal interconnection layer and the back-end power gating circuit.
  • the back-end metal interconnection layer is located on the front-end circuit.
  • the back-end power gating circuit is located in the back-end metal interconnection layer.
  • the back-end power gating circuit and the front-end circuit are vertically distributed on different layers, realizing monolithic three-dimensional integration of the power gating circuit and the circuit. Based on this, compared with existing integrated circuits that include front-end circuits and power gating circuits that are laterally distributed on the same layer, although the three-dimensional integrated circuit provided by the present invention introduces a power gating circuit, it does not increase the number of three-dimensional integrated circuits.
  • the additional area overhead can not only reduce the static power consumption of the three-dimensional integrated circuit, but also help increase the integration density of the three-dimensional integrated circuit.
  • the rear-stage power gating circuit is located on the front-stage circuit, which can realize that the current transmission path between the power supply (or ground wire), the rear-stage power gating circuit and the front-stage circuit extends along a single direction, thereby helping to solve the problems in existing integrated circuits.
  • the front-end circuit and the power gating circuit are horizontally distributed on the same layer, so the current transmission path must be extended from top to bottom and then from bottom to top to complete the corresponding signal transmission, resulting in problems such as too long transmission paths and complex circuit layout and wiring.
  • the above-mentioned front-end circuit, back-end metal interconnection layer and back-end power gating circuit are formed on the same substrate, which reduces the distance between the front-end circuit and the back-end power gating circuit, further shortening and simplifying the power transmission path. It is more conducive to reducing the voltage drop of three-dimensional integrated circuits and improving the performance of three-dimensional integrated circuits.
  • the invention also provides a method for manufacturing a three-dimensional integrated circuit.
  • the manufacturing method of the three-dimensional integrated circuit includes:
  • a substrate is provided.
  • a front-end circuit is formed on the substrate.
  • a back-end metal interconnection layer is formed on the front-end circuit, and a back-end power gating circuit located in the back-end metal interconnection layer.
  • the front-end circuit is electrically connected to the power supply or ground wire through the back-end metal interconnection layer and the back-end power gating circuit.
  • Figure 1 is a schematic block diagram of an integrated circuit using a front-end process to manufacture a power gate control circuit in the prior art
  • Figure 2 is a schematic diagram of an integrated circuit using a front-end process to manufacture a power gate control circuit in the prior art
  • Figure 3 is a functional block diagram of a three-dimensional integrated circuit provided by an embodiment of the present invention.
  • Figure 4 is a schematic diagram of a three-dimensional integrated circuit provided by an embodiment of the present invention.
  • Figure 5 is an exploded schematic diagram of a three-dimensional integrated circuit structure provided by an embodiment of the present invention.
  • FIG. 6 is a flow chart of a manufacturing method of a three-dimensional integrated circuit according to an embodiment of the present invention.
  • Reference signs: 11 is the substrate, 12 is the front-end circuit, 121 is the logic/analog transistor, 13 is the interlayer isolation layer, 14 is the back-end metal interconnection layer, 15 is the back-end power gating circuit, 151 is the power gate control transistor, 1511 is the gate, 1512 is the gate dielectric layer, 15121 is the first dielectric layer, 15122 is the second dielectric layer, 1513 is the channel, 1514 is the source region, 1515 is the drain region, 1516 is the source, 1517 is drain.
  • a layer/element when referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present between them. element. Additionally, if one layer/element is "on” another layer/element in one orientation, then the layer/element can be "under” the other layer/element when the orientation is reversed.
  • the present invention will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention and are not intended to limit the present invention.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • plurality means two or more than two, unless otherwise explicitly and specifically limited.
  • Several means one or more than one, unless otherwise expressly and specifically limited.
  • connection should be understood in a broad sense.
  • connection can be a fixed connection or a detachable connection.
  • Connection, or integral connection can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be an internal connection between two elements or an interaction between two elements.
  • connection or integral connection
  • connection, or integral connection can be a mechanical connection or an electrical connection
  • it can be a direct connection or an indirect connection through an intermediate medium
  • it can be an internal connection between two elements or an interaction between two elements.
  • CMOS complementary metal oxide semiconductor
  • a gate dielectric layer with a high dielectric constant value can be used to reduce the leakage current of the device, thereby reducing the leakage power consumption of the circuit.
  • the sub-threshold leakage of the device is the main factor of leakage. Therefore, how to reduce static power consumption should first be considered how to reduce the sub-threshold leakage current of the device.
  • the method of reducing circuit power consumption at the circuit level is the most achievable, reducing sub-threshold leakage is mostly considered at the circuit level. Among them, the most effective method is power gating technology.
  • This power gating technology uses a switching transistor to turn off the connection between the internal circuit and the power supply or the connection between the internal circuit and the ground when the circuit is in a standby state, so as to turn off the power supply to the internal circuit.
  • Static low-power technology uses a switching transistor to turn off the connection between the internal circuit and the power supply or the connection between the internal circuit and the ground when the circuit is in a standby state, so as to turn off the power supply to the internal circuit.
  • the power gate control circuits in current mainstream silicon-based integrated circuits are manufactured using the Front End Of Line (FEOL) process, which makes the integrated circuits face at least the following challenges:
  • FEOL Front End Of Line
  • the current transmission path between the power supply (or ground wire) and the integrated circuit is long.
  • the logic/analog circuit of the segment is connected to the power supply through the power gate control circuit and the metal interconnection layer.
  • the transmission line resistance R v1 between the power supply and the power gate control circuit, the power gate control circuit and the logic/analog circuit The transmission line resistance R v2 , R HORI and R v3 between them, and the transmission line resistance R v4 between the logic/analog circuit and the ground wire.
  • the total resistance of the above three types of transmission line resistance increases with the increase of the current transmission path, so Integrated circuit performance degradation due to the introduction of additional IR drop (voltage loss).
  • the introduction of the power gate control circuit occupies a larger chip area, which is not conducive to integrated circuits.
  • the introduction of power gating circuits also makes integrated circuit layout and wiring more complex.
  • embodiments of the present invention provide a three-dimensional integrated circuit and a manufacturing method thereof.
  • the back-end metal interconnection layer is formed on the front-end circuit.
  • the back-end power gating circuit is located in the back-end metal interconnection layer, which not only reduces the static power consumption of the three-dimensional integrated circuit, but also helps improve the integration density of the three-dimensional integrated circuit.
  • the above-mentioned front-end circuit, back-end metal interconnection layer and back-end power gating circuit are formed on the same substrate, which reduces the distance between the front-end circuit and the back-end power gating circuit, further shortens the power transmission path, and further shortens the distance between the front-end circuit and the back-end power gating circuit. It is beneficial to reduce the voltage drop of three-dimensional integrated circuits and improve the performance of three-dimensional integrated circuits.
  • Embodiments of the present invention provide a three-dimensional integrated circuit.
  • the three-dimensional integrated circuit includes: a substrate 11 , a front-end circuit 12 formed on the substrate 11 , a back-end metal interconnection layer 14 and a back-end power gating circuit 15 .
  • the back-end metal interconnect layer 14 is formed on the front-end circuit 12 .
  • the back-end power gating circuit 15 is located in the back-end metal interconnection layer 14 .
  • the front-end circuit 12 is electrically connected to the power supply or ground through the back-end metal interconnection layer 14 and the back-end power gating circuit 15 .
  • the above-mentioned substrate can be any substrate such as a silicon oxide wafer substrate, as long as it can be applied to the three-dimensional integrated circuit provided by the embodiment of the present invention.
  • the above-mentioned front-end circuit may be a front-end logic circuit or a front-end analog circuit. It is understandable that depending on the application scenarios of three-dimensional integrated circuits, the specific structures, materials, specifications and other information of the above-mentioned front-end circuits, back-end metal interconnection layers, and back-end power gating circuits are not completely the same or different.
  • Information such as the specific structure of the front-end circuit, the back-end metal interconnection layer, and the back-end power gating circuit can be set according to the actual application scenario, and there are no specific limitations here. Furthermore, as shown in parts (1) and (2) in Figure 3, the previous section Whether the circuit is electrically connected to the power supply or the ground wire through the back-end metal interconnection layer and the back-end power gating circuit can be set according to actual needs and the specific structure of the power gating circuit. For example: in the case where the power gating circuit includes at least one power gating transistor, and the power gating transistor is a PMOS transistor, the front-end circuit can be electrically connected to the power supply through the back-end metal interconnection layer and the back-end power gating circuit.
  • the front-end circuit is connected to the drain of the power gate transistor, and the power source is connected to the source of the power gate transistor.
  • the power gating circuit includes at least one power gating transistor, and the power gating transistor is an NMOS transistor
  • the front-end circuit can be electrically connected to the ground through the back-end metal interconnection layer and the back-end power gating circuit. connect.
  • the front circuit is connected to the drain of the power gate transistor, and the ground wire is connected to the source of the power gate transistor.
  • the position of the back-end power gating circuit in the back-end metal interconnection layer affects the relative positional relationship between the back-end power gating circuit and the front-end circuit, which in turn affects the power supply (or ground wire), the back-end power gating circuit and the
  • the distribution and length of the current transmission path between the front-end circuits, so the relative position of the back-end power gating circuit and the front-end circuit can be designed according to the requirements for the current transmission path.
  • the back-end power gating circuit along the thickness direction of the substrate, can be located obliquely above the front-end circuit, and their positions in the vertical direction partially overlap.
  • R v1 in Figure 4 is the transmission line resistance between the power supply and the back-end power gating circuit.
  • R v2 , R HORI and R v3 are the transmission line resistance between the back-end power gating circuit and the front-end circuit, and
  • R v4 is the transmission line resistance between the front-end circuit and the ground wire.
  • the front-end circuit 12 and the back-end power gating circuit 15 are vertically stacked and distributed.
  • the back-end power gating circuit 15 is located directly above the front-end circuit 12, which is conducive to realizing that the current transmission path extends along a single direction perpendicular to the surface of the substrate 11, minimizing the current transmission path and reducing the voltage of the three-dimensional integrated circuit. While reducing losses, it can also simplify circuit routing and reduce the difficulty of designing and manufacturing three-dimensional integrated circuits.
  • the above-mentioned three-dimensional integrated circuit may also include an interlayer isolation layer 13 between the front-end circuit 12 and the back-end metal interconnection layer 14 to be effective when the three-dimensional integrated circuit is in operation. Prevent the influence of the electric field generated by the back-end metal interconnection layer 14 and the back-end power gating circuit 15 on the front-end circuit 12, ensure the electrical insulation of the non-contact area between the front-end circuit 12 and the back-end metal interconnection layer 14, and suppress current leakage.
  • the material of the interlayer isolation layer 13 can be silicon dioxide or other insulators. edge material.
  • the thickness of the interlayer isolation layer 13 can be set according to actual requirements. For example, the thickness of the interlayer isolation layer 13 may be 100 nm to 400 nm.
  • the back-end metal interconnection layer is located on the front-end circuit.
  • the back-end power gating circuit is located in the back-end metal interconnection layer.
  • the back-end power gating circuit and the front-end circuit are vertically distributed on different layers.
  • the three-dimensional integrated circuit provided by the embodiment of the present invention introduces a power gate control circuit, but does not increase the additional area overhead of the three-dimensional integrated circuit, that is, it can reduce the static power consumption of the three-dimensional integrated circuit and at the same time help increase the integration density of the three-dimensional integrated circuit.
  • the rear-stage power gating circuit 15 is located on the front-stage circuit 12, which can realize that the current transmission path between the power supply (or ground wire), the rear-stage power gating circuit 15 and the front-stage circuit 12 extends in a single direction, thereby facilitating the solution
  • the front-end logic/analog circuits and power gating circuits are laterally distributed on the same layer, so the current transmission path must be extended from top to bottom and then from bottom to top to complete the corresponding signal transmission, resulting in the current transmission path being too long. , and the problem of complex circuit layout and wiring.
  • the above-mentioned front-end circuit 12, back-end metal interconnection layer 14 and back-end power gating circuit 15 are formed on the same substrate 11, so that the distance between the front-end circuit 12 and the back-end power gating circuit 15 is reduced and further shortened. And simplifying the power transmission path is more conducive to reducing the voltage drop of the three-dimensional integrated circuit and improving the performance of the three-dimensional integrated circuit.
  • the above-mentioned rear-stage power gating circuit 15 includes at least one power gating transistor 151 .
  • the channel 1513 included in at least one power gate transistor 151 may be made of amorphous indium gallium zinc oxide.
  • the amorphous indium gallium zinc oxide material has characteristics such as a large on-off (I ON /I OFF ) ratio, low-temperature process, low sub-threshold swing (SS) and high mobility, it is
  • the channel 1513 of the power gate transistor 151 included in the back-stage power gate control circuit 15 is made of amorphous indium gallium zinc oxide, the power gate transistor 151 has a lower off-state current, which is beneficial to improving the leakage phenomenon. .
  • the structure type of the above-mentioned power gate transistor can be set according to actual needs.
  • the power gate transistor may be a planar transistor, a fin field effect transistor, a gate-all-around transistor, or the like.
  • the power gating transistor 151 may include a source region 1514 , a drain region 1515 , a channel 1513 , and a gate stack. , source 1516 and drain 1517. Specifically, the channel 1513 is located between the source region 1514 and the drain region 1515. The source electrode 1516 is electrically connected to the source region 1514, and the drain electrode 1517 is electrically connected to the drain region 1515. The relative positional relationship between the gate stack and the channel 1513 varies with different structural types of the power gate transistor 151 .
  • the gate stack is formed on the surface of the channel 1513 facing away from the substrate 11 .
  • the gate stack surrounds the outer periphery of the channel.
  • the above gate stack includes a gate dielectric layer 1512 and a gate electrode 1511 formed on the gate dielectric layer 1512.
  • the source and drain regions of the power gate transistor can also be made of semiconductor materials such as amorphous indium gallium zinc oxide.
  • the source, drain and gate of the power gate transistor may be made of conductive materials such as titanium and/or gold. It should be understood that in actual application processes, titanium and gold materials can be patterned through non-dry etching methods such as lift-off. And when manufacturing upper-layer devices, if a dry etching process is used to pattern the source, drain, gate and other metal materials included in the upper-layer devices, the top interface may be uneven due to excessive etching. problems, which in turn affects the yield of upper-layer devices and affects the formation of subsequent structures because it is difficult to pattern the subsequent structures on the uneven interface.
  • the source, drain and gate of the power gate transistor when they are made of titanium and/or gold, they can be formed by non-dry etching such as stripping, which is beneficial to the flat top interface of the power gate transistor. ization, which is beneficial to the formation of back-end metal interconnection layers and other structures located on the power gate transistor, thereby improving the yield of three-dimensional integrated circuits.
  • the materials of the source, drain and gate of the power gate transistor can also be other conductive materials patterned by non-dry etching such as stripping.
  • the gate dielectric layer included in the power gate transistor may have a single-layer structure or a stacked structure composed of at least two dielectric layers.
  • the material of the gate dielectric layer included in the power gate control transistor can be a dielectric material such as silicon oxide or silicon nitride.
  • the insulating material with a lower dielectric constant may also be an insulating material with a higher dielectric constant such as HfO 2 , ZrO 2 , TiO 2 or Al 2 O 3 .
  • the gate dielectric layer 1512 of the power gate control transistor 151 may include a first dielectric layer 15121 and a A second dielectric layer 15122 on the dielectric layer 15121.
  • the material of the first dielectric layer 15121 may be aluminum oxide
  • the material of the second dielectric layer 15122 may be silicon dioxide.
  • the gate dielectric layer included in the power gate transistor 151 is a stack of a second aluminum oxide layer and a second silicon dioxide layer. The second oxide layer is located between the second aluminum oxide layer and the channel 1513 included in the power gate transistor 151 .
  • the material of the gate dielectric layer 1512 included in the power gate control transistor 151 contains a dielectric material with a high dielectric constant, and the material of the gate electrode 1511 included in the power gate control transistor 151 contains a metal material, it is beneficial to solve the problem of the power gate control transistor 151 151 has leakage problems in its gate dielectric layer 1512 after shrinkage.
  • the material of the channel 1513 included in the power gate transistor 151 is amorphous indium gallium zinc oxide
  • the second aluminum oxide layer with a smaller thickness can be formed using an atomic layer deposition process, and the second aluminum oxide layer can be formed using an atomic layer deposition process.
  • Both the silicon layer and the channel 1513 included in the power gate transistor 151 can be formed using a magnetron sputtering process. Based on this, in the actual application process, although the second aluminum oxide layer is formed in equipment that can support the atomic layer deposition process, and the formed structure is transferred to the equipment that can support the magnetron sputtering process, the second oxidation layer is The interface of the aluminum layer close to the channel 1513 is less clean. At this time, a magnetron sputtering process can be used to first form a second silicon dioxide layer on the second aluminum oxide layer, so that the interface forming the channel 1513 included in the power gate control transistor 151 is cleaner, which is beneficial to improving the power supply. Performance consistency of gate transistor 151.
  • the front-end circuit 12 includes at least one logic/analog transistor 121 .
  • the specific structure of the logic/analog transistor 121 may refer to the structure of the power gate transistor 151 described above, and will not be described again here.
  • At least one logic/analog transistor includes a source electrode and a drain electrode made of conductive materials such as titanium and/or gold.
  • the gate electrode included in the logic/analog transistor may be made of conductive material such as molybdenum.
  • Logic/analog transistors include source regions, drain regions, and channels made of semiconductor materials such as silicon, silicon germanium, germanium, or amorphous indium gallium zinc oxide.
  • the gate dielectric layer included in the logic/analog transistor can be a single-layer structure or a stacked structure. Specifically, when the gate dielectric layer included in the logic/analog transistor is a single layer When constructing the structure, reference can be made to the material of the gate dielectric layer included in the power gate transistor mentioned above.
  • the gate dielectric layer included in the logic/analog transistor may be a stack of a first aluminum oxide layer and a first silicon dioxide layer.
  • the first silicon dioxide layer is located between the channel included in the logic/analog transistor and the first aluminum oxide layer.
  • an embodiment of the present invention provides a method for manufacturing a three-dimensional integrated circuit.
  • the manufacturing method of the three-dimensional integrated circuit includes: providing a substrate. Then a front-end circuit is formed on the substrate. As shown in FIGS. 3 to 5 , the back-end metal interconnection layer 14 and the back-end power gating circuit 15 located in the back-end metal interconnection layer 14 are finally formed on the front-end circuit 12 .
  • the front-end circuit 12 is electrically connected to the power supply or ground through the back-end metal interconnection layer 14 and the back-end power gating circuit 15 .
  • the material of the substrate as well as the specific structure, material and specifications of the front-end circuit, back-end metal interconnection layer and back-end power gating circuit can be referred to the previous article.
  • the front-end process is used to form the front-end circuit on the substrate.
  • the gate material can be sputtered on a silicon/silicon oxide substrate through a magnetron sputtering process. And a dry etching process is used to pattern the gate material to obtain the gate including the logic/analog transistor of the front-end circuit.
  • a process such as atomic layer deposition can be used to form a first dielectric material layer on the substrate and the gate electrode included in the logic/analog transistor, and the first dielectric material layer can be patterned, leaving only the first dielectric material layer on the logic/analog transistor.
  • the first dielectric layer may be made of aluminum oxide, etc.
  • processes such as magnetron sputtering are used to sequentially cover the second dielectric material layer and the semiconductor material layer on the formed structure, and the above two film layers are patterned so that the remaining second dielectric material layer forms the second medium layer (the material of the second dielectric layer may be silicon dioxide, etc.) and the remaining semiconductor material layers form the source region, drain region and channel included in the logic/analog transistor.
  • the first dielectric layer and the second dielectric layer constitute a gate dielectric layer included in the logic/analog transistor.
  • a mask layer for exposing the source and drain regions included in the logic/analog transistor is manufactured on the formed structure through processes such as patterning. Then, under the cover of the mask layer, the source and drain electrodes in contact with the source and drain regions respectively are formed through processes such as sputtering and stripping, to obtain a logic/analog transistor.
  • interlayer isolation layer on the front-end circuit to achieve electrical insulation in the non-contact area between the back-end metal interconnect layer and the front-end circuit.
  • the material of the above-mentioned interlayer isolation layer can be silicon dioxide, so as to reduce the difficulty and cost of manufacturing the interlayer isolation layer on the front-end circuit and at the same time be compatible with the very large scale integrated circuit process.
  • the interlayer isolation layer may have a thickness of 100 nm to 400 nm.
  • the material and thickness of the interlayer isolation layer can also be other materials and thicknesses that meet working requirements.
  • the back-end process is finally used to manufacture the back-end metal interconnection layer 14 and the back-end power gating circuit 15 on the interlayer isolation layer 13 .
  • the process of manufacturing the power gating transistor 151 included in the back-end power gating circuit 15 can refer to the manufacturing process of the logic/analog transistor 121 described above, and will not be described again here.
  • the channel included in the at least one power gating transistor may be formed of amorphous indium gallium zinc oxide.
  • the processing temperature of the above-mentioned low-temperature process can be greater than 0 and less than or equal to 350°C.
  • the beneficial effects of the three-dimensional integrated circuit manufacturing method provided by the embodiments of the present invention are the same as those of the three-dimensional integrated circuit provided by the embodiments of the present invention, and will not be described again here.
  • front-end circuit and back-end metal interconnection layer can be formed in various ways. How to form the above structure is not the main feature of the present invention, so in this specification, it is only briefly introduced so that those of ordinary skill in the art can easily implement the present invention. Those of ordinary skill in the art can completely imagine other ways to make the above structure.

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Abstract

本发明公开了一种三维集成电路及其制造方法，涉及半导体技术领域，用于在集成电路包括电源门控电路的前提下，提高该集成电路的性能。所述三维集成电路包括：衬底、形成在衬底上的前段电路、后段金属互连层和后段电源门控电路。后段金属互连层形成在前段电路上。后段电源门控电路位于后段金属互连层内。前段电路通过后段金属互连层和后段电源门控电路与电源或地线电连接。

Description

一种三维集成电路及其制造方法
本申请要求于2022年5月11日提交中国专利局、申请号为202210515402.X、申请名称为“一种三维集成电路及其制造方法”的中国专利优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体技术领域，尤其涉及一种三维集成电路及其制造方法。
背景技术
电源门控技术是一种当电路处于待机状态时，使用开关晶体管关断内部电路与电源之间的连接，或者关断内部电路与地线之间的连接，以达到关断内部电路供电的静态低功耗技术。
但是，应用上述电源门控技术的现有集成电路的性能不佳。
发明内容
本发明的目的在于提供一种三维集成电路及其制造方法，用于在集成电路包括电源门控电路的前提下，提高该集成电路的性能。
为了实现上述目的，本发明提供了一种三维集成电路，该三维集成电路包括：衬底、形成在衬底上的前段电路、后段金属互连层和后段电源门控电路。后段金属互连层形成在前段电路上。后段电源门控电路位于后段金属互连层内。前段电路通过后段金属互连层和后段电源门控电路与电源或地线电连接。
与现有技术相比，本发明提供的三维集成电路中，后段金属互连层位于前段电路上。并且，后段电源门控电路位于后段金属互连层内。换句话说，后段电源门控电路与前段电路是竖向分布在不同层，实现了电源门控电路与电路的单片三维集成。基于此，与现有的集成电路包括的前段电路和电源门控电路是横向分布在同一层相比，本发明提供的三维集成电路虽然引入了电源门控电路，但是并未增加三维集成电路的额外面积开销，即可以在降低三维集成电路的静态功耗的同时，利于提高三维集成电路的集成密度。并且， 后段电源门控电路位于前段电路上，可以实现电源(或地线)、后段电源门控电路与前段电路之间的电流传输路径沿着单一方向延伸，从而利于解决现有集成电路中因前段电路和电源门控电路横向分布在同一层使得电流传输路径必须由上至下延伸后再由下至上延伸才能完成相应信号传输而导致传输路径过长、以及电路布局布线复杂的问题。此外，上述前段电路、后段金属互连层和后段电源门控电路是形成在同一衬底上，使得前段电路与后段电源门控电路的间距减小，进一步缩短和简化电源传输路径，更有利于降低三维集成电路的电压降，提高三维集成电路的性能。
本发明还提供了一种三维集成电路的制造方法，该三维集成电路的制造方法包括：
提供一衬底。
在衬底上形成前段电路。
在前段电路上形成后段金属互连层、以及位于后段金属互连层内的后段电源门控电路。前段电路通过后段金属互连层和后段电源门控电路与电源或地线电连接。
本发明提供的三维集成电路的制造方法具有的有益效果与本发明提供的三维集成电路具有的有益效果相同，此处不再赘述。
附图说明
此处所说明的附图用来提供对本发明的进一步理解，构成本发明的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1为现有技术中采用前段工艺制造电源门控电路的集成电路原理框图；
图2为现有技术中采用前段工艺制造电源门控电路的集成电路原理图；
图3为本发明实施例提供的三维集成电路原理框图；
图4为本发明实施例提供的三维集成电路原理图；
图5为本发明实施例提供的三维集成电路结构爆炸示意图；
图6为本发明实施例提供的三维集成电路的制造方法流程图。
附图标记：11为衬底，12为前段电路，121为逻辑/模拟晶体管，13为层间隔离层，14为后段金属互连层，15为后段电源门控电路，151为电源门控晶体管，1511为栅极，1512为栅介质层，15121为第一介质层，15122为第二介质层，1513为沟道，1514为源区，1515为漏区，1516为源极，1517为漏极。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。为了使本发明所要解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。“若干”的含义是一个或一个以上，除非另有明确具体的限定。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
随着半导体工艺技术的进步使电子设备(例如：笔记本电脑和移动电话等)能够执行越来越复杂的功能，但是，电子设备的储能元件(例如：电池)的能量存储能力却没有以同样的速度增长。基于此，功耗问题成了集成电路设计中的主要制约因素。具体的，从电路总功耗的构成考虑，降低电路功耗的方法可以分为动态低功耗方法和静态低功耗方法。并且，随着硅基互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，可缩写为CMOS)技术持续微缩至5nm以下的技术节点，静态功耗所带来的功率耗散问题日益凸显，甚至已经成为芯片总功耗的决定因素。
针对如何降低上述静态功耗，本领域技术人员已研究出很多方法。例如：从工艺层次上来考虑，可使用高介电常数值的栅介质层，以减少器件的漏电流，进而减少电路的漏功耗。此外，就目前主流工艺而言，器件的亚阈值漏电为漏电的主要因素，因此，如何降低静态功耗，首要考虑如何减少器件的亚阈值漏电流。并且，因由于电路级降低电路功耗方法最具可实现性，故减少亚阈值漏电多从电路层次上考虑。其中，最为有效的方法为电源门控技术。该电源门控技术是一种当电路处于待机状态时，使用开关晶体管关断内部电路与电源之间的连接，或者关断内部电路与地线之间的连接，以达到关断内部电路供电的静态低功耗技术。
但是，如图1和图2所示，当前的主流硅基集成电路中电源门控电路采用的是前段工艺(Front End Of Line，可缩写为FEOL)制造形成，这使得集成电路至少面临着如下技术问题：如图1中的(1)和(2)部分、以及图2所示，电源(或地线)到集成电路之间的电流传输路径较长。相应的，以前 段的逻辑/模拟电路通过电源门控电路和金属互连层与电源相连接为例，图2中电源至电源门控电路之间的传输线阻Rv1、电源门控电路与逻辑/模拟电路之间的传输线阻Rv2、RHORI和Rv3、以及逻辑/模拟电路与地线之间的传输线阻Rv4，上述三类传输线阻的总阻值随着电流传输路径的增加而变大，从而因引入了额外的IR drop(电压损耗)而导致集成电路的性能退化。如图1和图2所示，因采用前段工艺制造形成的电源门控电路与前段的逻辑/模拟电路横向排布，故电源门控电路的引入占用了较大的芯片面积，不利于集成电路的小型化的同时电源门控电路的引入还使得集成电路布局布线更为复杂。
为了解决上述技术问题，本发明实施例提供了一种三维集成电路及其制造方法。其中，在本发明实施例提供的三维集成电路中，后段金属互连层形成在前段电路上。并且，后段电源门控电路位于后段金属互连层内，以降低三维集成电路的静态功耗的同时，利于提高三维集成电路的集成密度。此外，上述前段电路、后段金属互连层和后段电源门控电路是形成在同一衬底上，使得前段电路与后段电源门控电路的间距减小，进一步缩短电源传输路径，更有利于降低三维集成电路的电压降，提高三维集成电路的性能。
本发明实施例提供了一种三维集成电路。如图3至图5所示，该三维集成电路包括：衬底11、形成在衬底11上的前段电路12、后段金属互连层14和后段电源门控电路15。后段金属互连层14形成在前段电路12上。后段电源门控电路15位于后段金属互连层14内。前段电路12通过后段金属互连层14和后段电源门控电路15与电源或地线电连接。
具体来说，上述衬底可以为氧化硅片衬底等任一衬底，只要能够应用至本发明实施例提供的三维集成电路中即可。此外，上述前段电路可以为前段逻辑电路，也可以为前段模拟电路。可以理解的是，根据三维集成电路的应用场景的不同，上述前段电路、后段金属互连层和后段电源门控电路的具体结构、材质和规格等信息也不完成相同或不相同，因此可以根据实际应用场景对前段电路、后段金属互连层和后段电源门控电路的具体结构等信息进行设置，此处不做具体限定。此外，如图3中的(1)和(2)部分所示，前段 电路通过后段金属互连层和后段电源门控电路具体是与电源电连接，还是与地线电连接，可以根据实际需求以及电源门控电路的具体结构进行设置。例如：在电源门控电路包括至少一个电源门控晶体管，并且该电源门控晶体管为PMOS晶体管的情况下，前段电路可以通过后段金属互连层和后段电源门控电路与电源电连接。其中，前段电路连接电源门控晶体管的漏极，电源连接电源门控晶体管的源极。又例如：在电源门控电路包括至少一个电源门控晶体管，并且该电源门控晶体管为NMOS晶体管的情况下，前段电路可以通过后段金属互连层和后段电源门控电路与地线电连接。其中，前段电路连接电源门控晶体管的漏极，地线连接电源门控晶体管的源极。
再者，后段电源门控电路在后段金属互连层内的位置影响后段电源门控电路与前段电路的相对位置关系，进而影响电源(或地线)、后段电源门控电路与前段电路之间电流传输路径的分布和长短，因此可以根据对电流传输路径的要求来设计后段电源门控电路与前段电路的相对位置。例如：如图4所示，沿着衬底的厚度方向，后段电源门控电路可以位于前段电路的斜上方，并且二者在竖直方向上的位置有部分重叠。其中，图4中Rv1为电源至后段电源门控电路之间的传输线阻。Rv2、RHORI和Rv3为后段电源门控电路与前段电路之间的传输线阻、Rv4为前段电路与地线之间的传输线阻。又例如：如图3和图5所示，沿着衬底11的厚度方向，前段电路12与后段电源门控电路15垂直堆叠分布。此时，后段电源门控电路15位于前段电路12的正上方，利于实现电流传输路径沿着垂直于衬底11表面的单一方向延伸，最大程度上缩短电流传输路径、降低三维集成电路的电压损耗的同时，还可以简化电路走线、降低三维集成电路的设计难度和制造难度。
在一些情况下，如图5所示，上述三维集成电路还可以包括位于前段电路12与后段金属互连层14之间的层间隔离层13，以在三维集成电路处于工作状态时有效的防止后段金属互连层14和后段电源门控电路15产生的电场对前段电路12的影响，确保前段电路12与后段金属互连层14之间的非接触区域电绝缘，抑制漏电。具体的，层间隔离层13的材质可以为二氧化硅等绝 缘材料。层间隔离层13的厚度可以根据实际需求进行设置。例如：层间隔离层13的厚度可以为100nm至400nm。
由上述内容可知，本发明实施例提供的三维集成电路中，后段金属互连层位于前段电路上。并且，后段电源门控电路位于后段金属互连层内。换句话说，后段电源门控电路与前段电路是竖向分布在不同层。基于此，如图3至图5所示，与现有的集成电路包括的前段电路和电源门控电路是横向分布在同一层相比，本发明实施例提供的三维集成电路虽然引入了电源门控电路，但是并未增加三维集成电路的额外面积开销，即可以在降低三维集成电路的静态功耗的同时，利于提高三维集成电路的集成密度。并且，后段电源门控电路15位于前段电路12上，可以实现电源(或地线)、后段电源门控电路15与前段电路12之间的电流传输路径沿着单一方向延伸，从而利于解决现有集成电路中因前段的逻辑/模拟电路和电源门控电路横向分布在同一层使得电流传输路径必须由上至下延伸后再由下至上延伸才能完成相应信号传输而导致电流传输路径过长、以及电路布局布线复杂的问题。此外，上述前段电路12、后段金属互连层14和后段电源门控电路15是形成在同一衬底11上，使得前段电路12与后段电源门控电路15的间距减小，进一步缩短和简化电源传输路径，更有利于降低三维集成电路的电压降，提高三维集成电路的性能。
在一种示例中，如图5所示，上述后段电源门控电路15包括至少一个电源门控晶体管151。至少一个电源门控晶体管151包括的沟道1513的材质可以为非晶铟镓锌氧化物。应理解，因非晶铟镓锌氧化物材料具有较大的开关(ION/IOFF)比、低温工艺、较低的亚阈值摆幅(SS)和较高的迁移率等特性，故在后段电源门控电路15所包括的电源门控晶体管151的沟道1513的材质为非晶铟镓锌氧化物的情况下，电源门控晶体管151具有较低的关态电流，利于改善漏电现象。并且利于采用低温工艺在前段电路12上制造上述后段电源门控电路15，防止前段电路12在形成电源门控晶体管151的过程中受到高温工艺的影响而导致前段电路12的工作性能降低。
具体的，上述电源门控晶体管的结构类型可以根据实际需求进行设置。 示例性的，电源门控晶体管可以为平面晶体管、鳍式场效应晶体管或环栅晶体管等。
其中，如图5所示，在后段电源门控电路15包括至少一个电源门控晶体管151的情况下，该电源门控晶体管151可以包括源区1514、漏区1515、沟道1513、栅堆叠、源极1516和漏极1517。具体的，上述沟道1513位于源区1514和漏区1515之间。源极1516与源区1514电连接，漏极1517与漏区1515电连接。上述栅堆叠与沟道1513的相对位置关系随着电源门控晶体管151的结构类型的不同而不同。例如：在电源门控晶体管151为平面晶体管的情况下，栅堆叠形成在沟道1513背离衬底11的表面。又例如：在电源门控晶体管为环栅晶体管的情况下，栅堆叠环绕在沟道的外周。上述栅堆叠包括栅介质层1512、以及形成在栅介质层1512上的栅极1511。
至于电源门控晶体管包括的源区和漏区的材质也可以为非晶铟镓锌氧化物等半导体材料。电源门控晶体管包括的源极、漏极和栅极的材质可以为钛和/或金等导电材料。应理解，在实际的应用过程中，钛和金材料可以通过剥离等非干法刻蚀方式实现图案化。并且在制造上层器件时，若采用干法刻蚀工艺对上层器件所包括的源极、漏极和栅极等金属材料进行图案化处理可能会出现因过度刻蚀而导致其顶部界面不平坦等问题，进而影响上层器件的良率、以及因难以在不平坦的界面上实现后续结构的图案化处理而影响后续结构的形成。基于此，在电源门控晶体管的源极、漏极和栅极的材质为钛和/或金的情况下，可以通过剥离等非干法刻蚀方式形成，利于电源门控晶体管的顶部界面平坦化，进而有利于后段金属互连层等其它结构位于电源门控晶体管上的部分的形成，提高三维集成电路的良率。当然，电源门控晶体管包括的源极、漏极和栅极的材质还可以为通过剥离等非干法刻蚀方式实现图案化的其它导电材料。
此外，电源门控晶体管包括的栅介质层可以为单层结构，也可以是由至少两层介质层组成的叠层结构。例如：在电源门控晶体管包括的栅介质层为单层结构时，电源门控晶体管包括的栅介质层的材质可以为氧化硅或氮化硅等介电常 数较低的绝缘材料，也可以为HfO2、ZrO2、TiO2或Al2O3等介电常数较高的绝缘材料。又例如：如图5所示，当电源门控晶体管包括151的栅介质层1512为叠层结构时，电源门控晶体管包括151的栅介质层1512可以包括第一介质层15121、以及位于第一介质层15121上的第二介质层15122。其中，第一介质层15121的材质可以为氧化铝，第二介质层15122的材质可以为二氧化硅。此时，电源门控晶体管151包括的栅介质层为第二氧化铝层和第二二氧化硅层的叠层。该第二二氧化层位于第二氧化铝层和电源门控晶体管151包括的沟道1513之间。应理解，当电源门控晶体管151包括的栅介质层1512的材质含有高介电常数的介质材料、以及电源门控晶体管151包括的栅极1511的材质含有金属材料时，利于解决电源门控晶体管151在微缩后其栅介质层1512的漏电问题。并且，在电源门控晶体管151包括的沟道1513的材质为非晶铟镓锌氧化物的情况下，因厚度较小的第二氧化铝层可以采用原子层沉积工艺形成、以及第二二氧化硅层和电源门控晶体管151包括的沟道1513均可以采用磁控溅射工艺形成。基于此，在实际的应用过程中，虽然采用能够支持原子层沉积工艺的设备内形成第二氧化铝层、并将已形成的结构转移至能够支持磁控溅射工艺的设备后，第二氧化铝层靠近沟道1513的界面的洁净程度较低。此时，可以采用磁控溅射工艺先在第二氧化铝层上形成一层第二二氧化硅层，以使得形成电源门控晶体管151包括的沟道1513的界面更为洁净，利于提高电源门控晶体管151的性能一致性。
在一种示例中，如图5所示，上述前段电路12包括至少一个逻辑/模拟晶体管121。具体的，逻辑/模拟晶体管121的具体结构可以参考前文所述的电源门控晶体管151的结构，此处不再赘述。
其中，至少一个逻辑/模拟晶体管包括的源极和漏极的材质可以为钛和/或金等导电材料。逻辑/模拟晶体管包括的栅极的材质可以为钼等导电材料。逻辑/模拟晶体管包括的源区、漏区和沟道的材质可以为硅、锗硅、锗或非晶铟镓锌氧化物等半导体材料。逻辑/模拟晶体管包括的栅介质层可以为单层结构，也可以为叠层结构。具体的，当逻辑/模拟晶体管包括的栅介质层为单层 结构时，可以参考前文所述的电源门控晶体管包括的栅介质层的材质。当逻辑/模拟晶体管包括的栅介质层为叠层结构时，逻辑/模拟晶体管包括的栅介质层可以为第一氧化铝层与第一二氧化硅层的叠层。其中，第一二氧化硅层位于逻辑/模拟晶体管包括的沟道与第一氧化铝层之间。该情况下具有的有益效果可以参考前文所述的电源门控晶体管包括的栅介质层为第二氧化铝层和第二二氧化硅层的叠层具有的有益效果，此处不再赘述。
如图6所示，本发明实施例提供了一种三维集成电路的制造方法。具体的，该三维集成电路的制造方法包括：提供一衬底。接着在衬底上形成前段电路。如图3至图5所示，最后在前段电路12上形成后段金属互连层14、以及位于后段金属互连层14内的后段电源门控电路15。前段电路12通过后段金属互连层14和后段电源门控电路15与电源或地线电连接。
具体的，衬底的材质，以及前段电路、后段金属互连层和后段电源门控电路的具体结构、材质和规格等信息可以参考前文。
在实际的应用过程中，采用前段工艺在衬底上形成前段电路。示例性的，可以通过磁控溅射工艺在硅/氧化硅衬底上溅射栅极材料。并采用干法刻蚀工艺对栅极材料进行图案化处理得到前段电路具有的逻辑/模拟晶体管包括的栅极。接着可以采用原子层沉积等工艺在衬底和逻辑/模拟晶体管包括的栅极上形成第一介质材料层，并对第一介质材料层进行图案化处理，仅保留第一介质材料层位于逻辑/模拟晶体管包括的栅极上的部分，获得第一介质层(该第一介质层的材质可以为氧化铝等)。然后采用磁控溅射等工艺在已形成的结构上依次覆盖第二介质材料层和半导体材料层，并对上述两个膜层进行图案化处理，使得剩余的第二介质材料层形成第二介质层(该第二介质层的材质可以为二氧化硅等)、以及剩余的半导体材料层形成逻辑/模拟晶体管包括的源区、漏区和沟道。上述第一介质层和第二介质层构成逻辑/模拟晶体管包括的栅介质层。最后，通过图案化等工艺在已形成的结构上制造用于暴露逻辑/模拟晶体管包括的源区和漏区的掩膜层。接着在掩膜层覆盖下，通过溅射和剥离等工艺形成分别与源区和漏区接触的源极和漏极，获得逻辑/模拟晶体管。
然后，可以采用等离子体化学气相沉积等工艺在前段电路上形成层间隔离层，以实现后段金属互连层与前段电路之间的非接触区域电绝缘。其中，上述层间隔离层的材质可以为二氧化硅，以降低在前段电路上制造层间隔离层的难度和成本的同时，与超大规模集成电路工艺所兼容。该层间隔离层的厚度可以为100nm至400nm。当然，层间隔离层的材质和厚度还可以为满足工作要求的其它材料和厚度。
如图3至图5所示，最后采用后段工艺在层间隔离层13上制造后段金属互连层14和后段电源门控电路15。具体的，制造后段电源门控电路15所包括的电源门控晶体管151的过程可以参考前文所述的逻辑/模拟晶体管121的制造过程，此处不再赘述。
其中，如前文所述，上述后段电源门控电路包括至少一个电源门控晶体管的情况下，至少一个电源门控晶体管包括的沟道可以由非晶铟镓锌氧化物形成。此时，利于采用低温工艺在前段电路的上方形成后段金属互连层和后段电源门控电路，防止前段电路因高温工艺受到损伤。具体的，上述低温工艺的处理温度可以大于0、且小于等于350℃。
与现有技术相比，本发明实施例提供的三维集成电路的制造方法具有的有益效果与本发明实施例提供的三维集成电路具有的有益效果相同，此处不再赘述。
需要说明的是，可以通过多种方式来形成上述前段电路和后段金属互连层。如何形成上述结构并非本发明的主要特征所在，因此在本说明书中，只对其进行简要地介绍，以便本领域普通技术人员能够容易地实施本发明。本领域普通技术人员完全可以设想别的方式来制作上述结构。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (10)

  1. 一种三维集成电路，其特征在于，包括：衬底、形成在所述衬底上的前段电路、后段金属互连层和后段电源门控电路；所述后段金属互连层形成在所述前段电路上；所述后段电源门控电路位于所述后段金属互连层内；所述前段电路通过所述后段金属互连层和所述后段电源门控电路与电源或地线电连接。
  2. 根据权利要求1所述的三维集成电路，其特征在于，沿着所述衬底的厚度方向，所述前段电路与所述后段电源门控电路垂直堆叠分布。
  3. 根据权利要求1所述的三维集成电路，其特征在于，所述后段电源门控电路包括至少一个电源门控晶体管；至少一个所述电源门控晶体管包括的沟道的材质为非晶铟镓锌氧化物。
  4. 根据权利要求1所述的三维集成电路，其特征在于，所述三维集成电路还包括位于所述前段电路与所述后段金属互连层之间的层间隔离层；
    所述层间隔离层的材质为二氧化硅，和/或，所述层间隔离层的厚度为100nm至400nm。
  5. 根据权利要求1所述的三维集成电路，其特征在于，所述前段电路包括至少一个逻辑/模拟晶体管；
    至少一个所述逻辑/模拟晶体管包括的源极和漏极的材质为钛和/或金；和/或，至少一个所述逻辑/模拟晶体管包括的栅极的材质为钼；和/或，至少一个所述逻辑/模拟晶体管包括的栅介质层为第一氧化铝层与第一二氧化硅层的叠层，所述第一二氧化硅层位于所述逻辑/模拟晶体管包括的沟道与所述第一氧化铝层之间。
  6. 根据权利要求1～5任一项所述的三维集成电路，其特征在于，所述后段电源门控电路包括至少一个电源门控晶体管；
    至少一个所述电源门控晶体管包括的源极和漏极的材质为钛和/或金；和/或，至少一个所述电源门控晶体管包括的栅极的材质为钛和/或金；和/或，至少一个所述电源门控晶体管包括的栅介质层为第二氧化铝层与第二二氧化硅 层的叠层，所述第二二氧化硅层位于所述电源门控晶体管包括的沟道与所述第二氧化铝层之间。
  7. 一种三维集成电路的制造方法，其特征在于，包括：
    提供一衬底；
    在所述衬底上形成前段电路；
    在所述前段电路上形成后段金属互连层、以及位于所述后段金属互连层内的后段电源门控电路；所述前段电路通过所述后段金属互连层和所述后段电源门控电路与电源或地线电连接。
  8. 根据权利要求7所述的三维集成电路的制造方法，其特征在于，所述在所述衬底上形成前段电路后，所述在所述前段电路上形成后段金属互连层、以及位于所述后段金属互连层内的后段电源门控电路前，所述三维集成电路的制造方法还包括：
    在所述前段电路上形成层间隔离层；所述层间隔离层的材质为二氧化硅，和/或，所述层间隔离层的厚度为100nm至400nm。
  9. 根据权利要求7所述的三维集成电路的制造方法，其特征在于，所述后段电源门控电路包括至少一个电源门控晶体管；至少一个所述电源门控晶体管包括的沟道由非晶铟镓锌氧化物形成。
  10. 根据权利要求7～9任一项所述的三维集成电路的制造方法，其特征在于，采用低温工艺形成所述后段金属互连层和所述后段电源门控电路；所述低温工艺的处理温度大于0、且小于等于350℃。
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