WO2023213001A1 - 半导体结构及半导体结构的制作方法 - Google Patents

半导体结构及半导体结构的制作方法 Download PDF

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Publication number
WO2023213001A1
WO2023213001A1 PCT/CN2022/103650 CN2022103650W WO2023213001A1 WO 2023213001 A1 WO2023213001 A1 WO 2023213001A1 CN 2022103650 W CN2022103650 W CN 2022103650W WO 2023213001 A1 WO2023213001 A1 WO 2023213001A1
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Prior art keywords
doped region
substrate
conductive layer
layer
gate conductive
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French (fr)
Inventor
刘翔
杨彬
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Changxin Memory Technologies Inc
Changxin Jidian Beijing Memory Technologies Co Ltd
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Changxin Memory Technologies Inc
Changxin Jidian Beijing Memory Technologies Co Ltd
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Priority to US18/149,188 priority Critical patent/US12532452B2/en
Publication of WO2023213001A1 publication Critical patent/WO2023213001A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6212—Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies having non-rectangular cross-sections
    • H10D30/6213—Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies having non-rectangular cross-sections having rounded corners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326—Aspects related to lithography, isolation or planarisation of the conductor
    • H10D64/0133—Aspects related to lithography, isolation or planarisation of the conductor at least part of the entire electrode being a sidewall spacer, being formed by transformation under a mask or being formed by plating at a sidewall
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6219—Fin field-effect transistors [FinFET] characterised by the source or drain electrodes

Definitions

  • the present disclosure relates to, but is not limited to, a semiconductor structure and a method of manufacturing the semiconductor structure.
  • DRAM Dynamic Random Access Memory
  • DRAM usually includes an array area and a core area located outside the array area.
  • the array area has transistors arranged in an array.
  • the characteristic size of transistors is reduced, and the channel length of the transistor is also reduced, which may cause a short channel effect in the transistor.
  • the short channel effect may cause leakage in the transistor, seriously affecting the performance of the transistor. electrical properties.
  • the gate's ability to control the channel will decrease, affecting the sensitivity of the transistor and reducing the yield of the semiconductor structure.
  • the present disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure.
  • a first aspect of the present disclosure provides a semiconductor structure, the semiconductor structure comprising:
  • the doped region located between the stacked structure and the substrate.
  • the doped region includes a top doped region, a bottom doped region and a top doped region connected to the substrate. and an intermediate doped region of the bottom doped region.
  • the top doped region has a first width
  • the bottom doped region has a second width
  • the middle doped region has a first width.
  • the doped region has a gradually varying third width, wherein the first width is greater than the second width, and the third width gradually decreases in a direction away from the substrate.
  • the stack structure includes a gate stack structure
  • the gate stack structure includes a gate dielectric layer in contact with the doped region and a first gate conductive layer and a second gate conductive layer located on the gate dielectric layer. , in a cross section perpendicular to the substrate, the thickness of the first gate conductive layer is smaller than the thickness of the second gate conductive layer.
  • the second gate conductive layer has a first thickness
  • the first thickness gradually increases from the bottom doped region to the top doped region.
  • the semiconductor structure further includes a first dielectric layer, the first dielectric layer is located between the stacked structure and the top doped region, and the gate dielectric layer is connected to the first dielectric layer. , the gate dielectric layer is in contact with the first gate conductive layer, and the first dielectric layer is in contact with the second gate conductive layer;
  • the gate dielectric layer and the first dielectric layer have the same or different thicknesses.
  • the stacked structure further includes a dielectric stacked structure located on the top doped region, and the gate stacked structure is located on the middle doped region and the bottom doped region, wherein the dielectric The top surface of the stack structure is higher than the top surface of the gate stack structure.
  • the dielectric stack structure includes a second dielectric layer and a third dielectric layer, and in a cross-section perpendicular to the substrate, a top surface of the second dielectric layer is higher than the first gate conductive layer.
  • the top surface of the second dielectric layer is lower than the top surface of the second gate conductive layer, and the top surface of the third dielectric layer is higher than the top surface of the second gate conductive layer.
  • the semiconductor structure further includes a first plug, which penetrates the dielectric stack structure and is in contact with the top doped region.
  • the first gate conductive layer includes a work function adjustment material
  • the second gate conductive layer includes a metal conductive material
  • the doping types of the bottom doped region and the middle doped region are the same, and the doping types of the top doped region and the middle doped region are the same or different.
  • the semiconductor structure further includes an isolation structure covering the stacked structure.
  • the semiconductor structure further includes a source region and a drain region disposed in the substrate, and the source region and the drain region are located on both sides of the stacked structure.
  • the semiconductor structure also includes:
  • the second plug is arranged perpendicular to the substrate, and the second plug is in contact connection with the source region;
  • a third plug is arranged perpendicularly to the substrate, and the third plug is in contact connection with the drain region.
  • a second aspect of the present disclosure provides a method for manufacturing a semiconductor structure.
  • the manufacturing method includes:
  • auxiliary layer covering a portion of the substrate surface outside the dielectric structure, the auxiliary layer having a horizontal width that gradually decreases in a direction away from the substrate;
  • the substrate is patterned based on the auxiliary layer and the dielectric structure, and the pattern of the auxiliary layer is transferred into the substrate to form a pattern in the substrate away from the substrate.
  • the middle doped region has a gradually decreasing horizontal width in the direction, the substrate below the dielectric structure is not etched, and the substrate below the dielectric structure forms a top with a first width Doped region, the substrate not covered by the auxiliary layer and the dielectric structure is partially etched away to form an initial bottom doped region, the middle doped region connects the initial bottom doped region and all The top doped region;
  • a stacked structure covering at least the middle doped region and part of the initial bottom doped region is formed, and the part of the initial bottom doped region covered by the stacked structure forms a bottom doped region, and the bottom doped region has and a second width, the first width being greater than the second width.
  • a first dielectric layer is also formed between the dielectric structure and the substrate to form a stack structure that at least covers the middle doped region and part of the initial bottom doped region, including:
  • the thickness of the gate dielectric layer is equal to that of the first dielectric layer. The thickness is the same or different;
  • a first gate conductive layer and a second gate conductive layer covering the gate dielectric layer are formed.
  • the thickness of the first gate conductive layer is smaller than that of the second gate conductive layer. thickness.
  • forming the first gate conductive layer and the second gate conductive layer covering the gate dielectric layer includes:
  • first initial gate conductive layer covering the gate dielectric layer, perform a first etching on the first initial gate conductive layer, control the etching conditions of the first etching, and form a first initial gate conductive layer conformable to the gate dielectric layer.
  • the second gate conductive layer has a first thickness in the cross-section, and the first thickness gradually increases from the bottom doped region to the top doped region in a direction parallel to the substrate.
  • the method further includes:
  • the second initial gate conductive layer is formed on the first gate conductive layer and on the exposed first dielectric layer.
  • substrates including:
  • a second doping region is formed on the first doping region, wherein the doping ion types of the first doping region and the second doping region are the same or different.
  • patterning the substrate based on the auxiliary layer and the dielectric structure, and transferring the pattern of the auxiliary layer to the substrate includes:
  • etching ratio of the auxiliary layer and the substrate Control the etching ratio of the auxiliary layer and the substrate, synchronously etch the auxiliary layer and the substrate, and remove the second doped region and the second doped region that are not covered by the auxiliary layer and the dielectric structure. A portion of the first doping region below the second doping region is removed, and at least a portion of the first doping region and a portion of the second doping region below the auxiliary layer are removed.
  • the manufacturing method of the semiconductor structure also includes:
  • a first plug is formed. In a direction perpendicular to the substrate, the first plug penetrates the dielectric structure and the first dielectric layer and is in contact with the top doped region.
  • the manufacturing method of the semiconductor structure also includes:
  • the isolation structure at least covering the stacked structure
  • isolation structure Using the isolation structure as a mask, perform a source and drain doping process on the substrate to form a source region and a drain region in the substrate;
  • a third plug is formed perpendicular to the top surface of the substrate, and the third plug is contact-connected with the drain region.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment.
  • FIG. 2 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment.
  • FIG. 3 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment.
  • FIG. 4 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment.
  • FIG. 5 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment.
  • FIG. 6 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment.
  • Figure 7 is a schematic diagram of a substrate according to an exemplary embodiment.
  • FIG. 8 is a schematic diagram of forming a dielectric material layer according to an exemplary embodiment.
  • FIG. 9 is a schematic diagram of forming a dielectric structure according to an exemplary embodiment.
  • FIG. 10 is a schematic diagram illustrating the formation of an initial auxiliary layer according to an exemplary embodiment.
  • FIG. 11 is a schematic diagram of forming an auxiliary layer according to an exemplary embodiment.
  • FIG. 12 is a schematic diagram of etching a substrate according to an auxiliary layer and a dielectric structure according to an exemplary embodiment.
  • FIG. 13 is a schematic diagram of forming a first oxide layer according to an exemplary embodiment.
  • FIG. 14 is a schematic diagram of forming a gate dielectric layer according to an exemplary embodiment.
  • FIG. 15 is a schematic diagram illustrating the formation of a first initial gate conductive layer according to an exemplary embodiment.
  • FIG. 16 is a schematic diagram of forming a first gate conductive layer according to an exemplary embodiment.
  • FIG. 17 is a schematic diagram illustrating the formation of a second initial gate conductive layer according to an exemplary embodiment.
  • FIG. 18 is a schematic diagram illustrating formation of a first lightly doped region and a second lightly doped region according to an exemplary embodiment.
  • FIG. 19 is a schematic diagram showing the formation of source and drain regions according to an exemplary embodiment.
  • FIG. 20 is a schematic diagram of forming a dielectric layer according to an exemplary embodiment.
  • FIG. 21 is a schematic diagram illustrating forming a first trench, a second trench, and a third trench in a dielectric layer according to an exemplary embodiment.
  • FIG. 22 is a schematic diagram illustrating forming first plugs, second plugs and third plugs in a dielectric layer according to an exemplary embodiment.
  • FIG. 23 is a schematic diagram illustrating removal of dielectric structures according to an exemplary embodiment.
  • FIG. 24 is a schematic diagram illustrating the formation of a second initial gate conductive layer according to an exemplary embodiment.
  • FIG. 25 is a schematic diagram illustrating formation of second plugs, third plugs and fourth plugs in a dielectric layer according to an exemplary embodiment.
  • FIG. 26 is a flowchart of a method of fabricating a semiconductor structure according to an exemplary embodiment.
  • Figure 27 is a flowchart illustrating forming a stacked structure according to an exemplary embodiment.
  • FIG. 28 is a flowchart of a method of fabricating a semiconductor structure according to an exemplary embodiment.
  • Substrate 101. First oxide layer; 102. First initial gate conductive layer; 103. Second initial gate conductive layer; 110. Doping region; 111. Top doping region; 112. Bottom doping region; 113. Middle doping region; 114. Initial bottom doping region; 150. Initial substrate; 151. First doping region; 152. Second doping region; 153. First initial dielectric layer; 160.
  • L1 first width
  • L2, second width L3, third width
  • D1 first thickness
  • Exemplary embodiments of the present disclosure provide a semiconductor structure and a manufacturing method of the semiconductor structure.
  • the stacked structure of the semiconductor structure covers a doping region.
  • the doping region includes a middle doping region.
  • the middle doping region On a cross-section perpendicular to the substrate direction, the middle doping region The horizontal width of the doped region gradually decreases in the direction away from the substrate, so that the doped region forms a fin-shaped structure that protrudes outward relative to the substrate, thereby increasing the contact area between the stacked structure and the doped region.
  • the semiconductor structure includes a substrate 100 and a stack structure 200 located on the substrate 100 .
  • the semiconductor structure also includes a doped region 110 located between the stacked structure 200 and the substrate 100.
  • the doped region 110 includes a top doped region 111, The bottom doped region 112 and the middle doped region 113 connecting the top doped region 111 and the bottom doped region 112.
  • the top doped region 111 has a first width L1
  • the bottom doped region 111 has a first width L1.
  • the middle doped region 113 has a gradually changing third width L3, wherein the first width L1 is larger than the second width L2, and the third width L3 gradually decreases in the direction away from the substrate 100 , that is, based on the orientation shown in FIG. 1 , along the direction from bottom to top, the size of the third width L3 gradually decreases.
  • the top surface of the middle doped region 113 is higher than the top surface of the bottom doped region 112.
  • the maximum width of the middle doped region 113 is L3 MAX , and L3 MAX is greater than the second width L2.
  • the first width L1 ranges from 5 nm to 50 nm
  • the second width L2 ranges from 1 nm to 20 nm
  • the third width L3 MAX ranges from 1 nm to 100 nm
  • the third width L3 varies from 0 to L3MAX .
  • the first width L1 may be 5nm, 8nm, 12nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm or 50nm.
  • the second width L2 may be 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm or 10 nm.
  • the variation range of the third width L3 may be 0nm-1nm, 0nm-10nm, 0nm-20nm, 0nm-30nm, 0nm-35nm, 0nm-50nm, 0nm-60nm, 0nm-70nm, 40nm-80nm, 50nm-90nm or 60nm -100nm.
  • the first width L1 may be 5 nm
  • the second width L2 may be 1 nm
  • the third width L3 MAX may be 5 nm
  • the variation range of the third width L3 is 0 nm-5 nm.
  • the first width L1 may be 15 nm
  • the second width L2 may be 4 nm
  • the third width L3 MAX may be 10 nm
  • the variation range of the third width L3 is 0 nm-10 nm.
  • the first width L1 may be 25 nm
  • the second width L2 may be 7 nm
  • the third width L3 MAX may be 20 nm
  • the third width L3 may vary from 0 nm to 20 nm.
  • L3 MAX is greater than the first width L1.
  • the first width L1 may be 30 nm
  • the second width L2 may be 6 nm
  • the third width L3 MAX may be 40 nm
  • the third width L3 may vary from 0 nm to 40 nm.
  • the first width L1 may be 15 nm
  • the second width L2 may be 8 nm
  • the third width L3 MAX may be 80 nm
  • the third width L3 may vary from 0 nm to 80 nm.
  • the first width L1 may be 50 nm
  • the second width L2 may be 10 nm
  • the third width L3 MAX may be 100 nm
  • the third width L3 may vary from 0 nm to 100 nm.
  • the bottom doped region 112 and the middle doped region 113 have the same doping type, and the top doped region 111 and the middle doped region 113 have the same or different doping types.
  • the stack structure 200 includes a gate stack structure 210 .
  • the gate stack structure 210 includes a gate dielectric layer 211 in contact with the doped region 110 and a gate dielectric layer 211 located on the gate dielectric layer 211 .
  • the thickness of the first gate conductive layer 212 and the second gate conductive layer 213 is smaller than the thickness of the second gate conductive layer 213 in a cross section perpendicular to the substrate 100 .
  • the gate stack structure 210 covers at least the bottom doped region 112 and the middle doped region 113 of the doped region 110 .
  • the gate stack structure 210 may also cover the top doped region 111 .
  • the thickness of the first gate conductive layer 212 is 1 nm-40 nm.
  • the thickness of the first gate conductive layer 212 may be 1 nm-5 nm, 5 nm-10 nm, 10nm-15nm, 15nm-20nm, 20nm-25nm, 25nm-30nm, 30nm-35nm or 35nm-40nm.
  • the second gate conductive layer 213 has a first thickness D1 in a cross-section perpendicular to the substrate 100 , and is doped from the bottom in a direction parallel to the substrate 100 From the region 112 to the top doped region 113, the first thickness D1 gradually increases.
  • the variation range of the first thickness D1 is 0nm-50nm.
  • the variation range of the first thickness D1 may be 0nm-1nm, 0nm-5nm, 0nm-10nm, 0nm-15nm, 0nm-20nm, 0nm-25nm, 0nm-35nm, 0nm-45nm or 0nm-50nm.
  • the outer surface of the doping region 110 covered by the gate stack structure 210 is the channel of the transistor.
  • the third width L3 of the middle doping region 113 gradually decreases in the direction away from the substrate 100 , and the middle doping region 113 forms the doping region 110 into a fin disposed in the direction away from the substrate 100 type structure, the doped region 110 is raised relative to the substrate 100, which increases the contact area between the doped region 110 and the stack structure 200, thereby increasing the contact area between the gate stack structure 210 and the channel, increasing the channel length, which can avoid Or reduce the short channel effect; and, the gate stack structure 210 of this embodiment covers the channel, when the semiconductor structure is in the energized state, at least the gate stack structure 210 and the middle doped region 113 are in different positions of the contact surface.
  • control electric field generated by the gate stack structure 210 converges at the center of the doped region 110, which can increase the intensity of the control electric field, thereby improving the effect of the gate stack structure 210 on the channel.
  • the control capability; the semiconductor structure of this embodiment can further reduce the characteristic size of the device and improve the integration level of the semiconductor device.
  • the first gate conductive layer 212 includes a work function adjusting material
  • the second gate conductive layer 213 includes a metal conductive material.
  • the first gate conductive layer 212 is disposed between the doped region 110 and the second gate conductive layer 213.
  • the first gate conductive layer 212 is used to adjust the work function of the second gate conductive layer 213, which is beneficial to reducing the threshold voltage of the semiconductor structure.
  • the first gate conductive layer 212 includes N-type or P-type work function adjustment material.
  • the material of the first gate conductive layer 212 may include polysilicon, and the work function of the polysilicon may be changed by adjusting the type of doping ions and the doping concentration, thereby adjusting the relationship between the first gate conductive layer 212 and the second gate.
  • the work function of the gate structure composed of the conductive layer 213 can achieve the effect of reducing the threshold voltage.
  • the thickness of the first gate conductive layer 212 is close to the gate thickness of the planar transistor. Since the thickness of the first gate conductive layer 212 is small enough and uniform, when the material of the first gate conductive layer 212 includes polysilicon, the thickness of the polysilicon is The crystal orientation is the same and the crystal lattice is uniform. The first gate conductive layer 212 has good conductivity, which is beneficial to shrinking the device size.
  • the semiconductor structure further includes a first dielectric layer 230.
  • the first dielectric layer 230 is located between the stacked structure 200 and the top doped region 111.
  • the gate dielectric layer 211 is connected to the first dielectric layer 230, wherein , in a cross-section perpendicular to the direction of the substrate 100 , the gate dielectric layer 211 and the first dielectric layer 230 have the same or different thicknesses.
  • the bottom doped region 112 , the middle doped region 113 and the top doped region 111 of the doped region 110 have the same conductivity type. That is, the bottom doped region 112, the middle doped region 113, and the top doped region 111 may each have a P-type conductivity type or an N-type conductivity type.
  • the semiconductor structure and stack structure 200 of this example only include a gate stack structure 210 .
  • the gate dielectric layer 211 includes a connected gate dielectric layer 201 and a first dielectric layer 230.
  • the gate dielectric layer 201 is located between the gate stack structure 210 and the bottom doped region 112 and the middle doped region 113.
  • the first dielectric layer 230 is located between the stacked structure 200 and the top doped region 111 .
  • the gate dielectric layer 201 and the first dielectric layer 230 have the same or different thicknesses.
  • the gate dielectric layer 201 may have the same thickness as the first dielectric layer 230; or, the gate dielectric layer 201 may have a thickness greater than or less than the thickness of the first dielectric layer 230.
  • the first gate conductive layer 212 is located on the bottom doped region 112 and the middle doped region 113 , and the first gate conductive layer 212 is in contact with the gate dielectric layer 201 .
  • the second gate conductive layer 213 is located on the bottom doped region 112, the middle doped region 113 and the top doped region 111. Part of the structure of the second gate conductive layer 213 is in contact with the first gate conductive layer 212.
  • the second gate conductive layer Another part of the structure 213 is in contact with the first dielectric layer 230 .
  • the gate stack structure 210 covers the entire doped region 110, and the contact surface between the gate stack structure 210 and the doped region 110 is the channel of the transistor.
  • the channel length of the transistor is longer; and, Different positions of the contact surfaces between the gate stack structure 210 and the top doped region 111 and the middle doped region 113 generate a control electric field toward the center of the middle doped region 113, and the control electric field converges at the center of the doped region 110.
  • the greater strength further increases the channel control capability of the gate stack structure 210 .
  • the second gate conductive layer 213 not only covers the first gate conductive layer 212, but also covers the first dielectric layer 230 on the top doped region 111, adding a second gate conductive layer in the gate stack structure 210.
  • the ratio of 213 can improve the storage capacity and control capabilities of transistors.
  • the bottom doped region 112 and the middle doped region 113 of the doped region 110 have the same conductivity type.
  • the top doped region 111 and the middle doped region 113 have different doping types. That is, in this embodiment, the bottom doped region 112 and the middle doped region 113 both have N-type conductivity type, and the top doped region 111 has a P-type conductivity type; alternatively, the bottom doped region 112 and the middle doped region 113 have N-type conductivity type.
  • the regions 113 all have a P-type conductivity type, and the top doped region 111 has an N-type conductivity type.
  • the stack structure 200 includes a gate stack structure 210 located on the bottom doped region 112 and the middle doped region 113, and a gate stack structure 210 located on the top doped region 111.
  • the first dielectric layer 230 is disposed between the dielectric stack structure 220 and the top doped region 111 .
  • the gate stack structure 210 in the direction perpendicular to the substrate 100 , includes a gate dielectric layer 211 , a third gate dielectric layer 211 , and a third gate dielectric layer 211 sequentially disposed on the bottom doped region 112 and the middle doped region 113 in a direction perpendicular to the substrate 100 .
  • the gate dielectric layer 211 and the first dielectric layer 230 have the same or different thicknesses.
  • the gate dielectric layer 211 may have the same thickness as the first dielectric layer 230 , or the thickness of the gate dielectric layer 211 may be greater than or less than the thickness of the first dielectric layer 230 .
  • the dielectric stack structure 220 includes a second dielectric layer 221 and a third dielectric layer 222.
  • the top of the second dielectric layer 221 The surface is higher than the top surface of the first gate conductive layer 212, the top surface of the second dielectric layer 221 is lower than the top surface of the second gate conductive layer 213, and the top surface of the third dielectric layer 222 is higher than the second gate conductive layer. 213 top surface.
  • the second gate conductive layer 213 is only disposed above the first gate conductive layer 212.
  • the second gate conductive layer 213 is in contact with the first gate conductive layer 212 and the doped region 110, and is perpendicular to the substrate. In the direction of the bottom 100, there is no direct overlapping area between the second gate conductive layer 213 and the doped region 110.
  • the work function of the gate stack structure 210 is uniform, preventing the metal conductive material in the second gate conductive layer 213 from affecting the threshold of the transistor. voltage to ensure that the semiconductor structure has good electrical properties.
  • the semiconductor structure further includes an isolation structure 300 covering the stacked structure 200 .
  • the semiconductor structure further includes a source region 410 and a drain region 420 disposed in the substrate 100 .
  • the source region 410 and the drain region 420 are located at both sides of the stacked structure 200 .
  • the semiconductor structure further includes a first lightly doped region 510 and a second lightly doped region 520 disposed in the substrate 100, parallel to the substrate. In the direction of the bottom 100 , the first lightly doped region 510 and the second lightly doped region 520 are located on both sides of the stacked structure 200 .
  • the doping depth of the first lightly doped region 510 is less than the doping depth of the source region 410
  • the doping depth of the second lightly doped region 520 is less than the doping depth of the drain region 420 .
  • the first lightly doped region 510 is connected to the bottom doped region 112
  • the second lightly doped region 520 is connected to the bottom doped region 112 .
  • the first lightly doped region 510 and the source region 410 are arranged on the same side, and part of the first lightly doped region 510 is located between the source region 410 and the bottom doped region 112 to prevent the source region 410 from diffusing toward the bottom doped region 112 .
  • the second lightly doped region 520 and the drain region 420 are arranged on the same side, and part of the second lightly doped region 520 is located between the drain region 420 and the bottom doped region 112 to prevent the drain region 420 from diffusing toward the bottom doped region 112 .
  • the first lightly doped region 510 and the second lightly doped region 520 reduce the overlapping range of the source region 410, the drain region 420 and the gate stack structure 210, which can reduce or avoid gate-induced drain leakage of the semiconductor structure. current to make the electrical properties of the semiconductor structure more stable and improve the service life of the semiconductor structure.
  • the semiconductor structure further includes a second plug 620 and a third plug 630 , the second plug 620 is disposed perpendicularly to the substrate 100 , and the second plug 620 is connected to the substrate 100 .
  • the source region 410 is in contact connection
  • the third plug 630 is disposed perpendicularly to the substrate 100
  • the third plug 630 is in contact connection with the drain region 420 .
  • the stack structure 200 of semiconductor structures includes a gate stack structure 210 and a dielectric stack structure 220 .
  • the semiconductor structure also includes a first plug 610 that penetrates the dielectric stack structure 220 and is in contact with the top doped region 111 .
  • the stack structure 200 of semiconductor structures only includes a gate stack structure 210 .
  • the semiconductor structure also includes a fourth plug 640 , the fourth plug 640 is vertically disposed on the gate stack structure 210 , and the fourth plug 640 is in contact with the second gate conductive layer 213 .
  • Exemplary embodiments of the present disclosure provide a method for manufacturing a semiconductor structure. This embodiment does not limit the semiconductor structure.
  • the semiconductor structure is a dynamic random access memory (Dynamic Random Access Memory, DRAM) as an example for introduction below.
  • DRAM Dynamic Random Access Memory
  • FIG. 26 shows a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • FIGS. 7 to 25 are schematic diagrams of various stages of the method for manufacturing a semiconductor structure according to this embodiment. The following is combined with 7 to 25 and with reference to FIGS. 1 to 6, the manufacturing method of the semiconductor structure of this embodiment is introduced. As shown in Figure 26, the manufacturing method of the semiconductor structure in this embodiment includes the following steps:
  • Step S110 Provide a substrate.
  • a substrate 100 including:
  • an initial substrate 150 is provided, and a first doped region 151 is formed in the initial substrate 150 .
  • the material of the initial substrate 150 includes a semiconductor material, which may be silicon (Si), germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC); the semiconductor material may also be silicon on insulator (SOI), insulator Germanium (GOI); or it can also be other materials, such as gallium arsenide and other Group III-V compounds.
  • Doping ions are injected into the initial substrate 150 to form a first doping region 151.
  • the first doping region 151 has a first conductivity type, where the first conductivity type may be a P-type conductivity type or an N-type conductivity type.
  • a second doping region 152 is formed in the first doping region 151 , wherein the doping ion types of the first doping region 151 and the second doping region 152 are the same or different.
  • the conductivity type of the second doped region 152 is the same as that of the first doped region 151; in other embodiments, the conductivity type of the second doped region 152 is the same as that of the first doped region 151. The conductivity type is opposite.
  • a first initial dielectric layer 153 is formed, and the first initial dielectric layer 153 at least covers the second doped region 152 .
  • the first initial dielectric layer 153 may be formed through a deposition process or a thermal oxidation process, and the first initial dielectric layer 153 covers the outer surface of the initial substrate 150 .
  • the material of the first initial dielectric layer 153 may include oxide or nitride.
  • the material of the first initial dielectric layer 153 may include one of silicon oxide or silicon nitride.
  • Step S120 Form a dielectric structure on the substrate, and the dielectric structure covers part of the surface of the substrate.
  • the following methods may be used:
  • a dielectric material layer 160 is formed on the top surface of the substrate 100 , and the dielectric material layer 160 covers the first initial dielectric layer 153 .
  • the dielectric material layer 160 may include a single layer or a multi-layer structure.
  • the dielectric material layer 160 includes a multi-layer structure, along the direction away from the top surface of the substrate 100, that is, as shown in FIG. 8 from below. In the upward direction, the dielectric material layer 160 includes a second initial dielectric layer 161, a third initial dielectric layer 162, and a fourth initial dielectric layer 163 stacked in sequence.
  • the material of the dielectric material layer 160 includes an insulating material, such as at least one of silicon oxide, silicon nitride, or silicon oxynitride.
  • the materials of the second initial dielectric layer 161, the third initial dielectric layer 162, and the fourth initial dielectric layer 163 may be the same or different.
  • a mask layer 170 is formed on the top surface of the dielectric material layer 160 , and the mask layer 170 covers part of the top surface of the dielectric material layer 160 .
  • the dielectric material layer 160 is etched according to the mask layer 170 , and the retained dielectric material layer 160 forms a dielectric structure 225 .
  • the dielectric structure 225 formed in this embodiment includes a second dielectric layer 221, a third dielectric layer 222, and a fourth dielectric layer 223 sequentially disposed on the substrate 100.
  • Step S130 Form an auxiliary layer covering part of the substrate surface outside the dielectric structure, and the auxiliary layer has a gradually decreasing horizontal width in a direction away from the substrate.
  • the auxiliary layer 181 covering part of the surface of the substrate 100 is formed outside the dielectric structure 225.
  • the following methods can be used:
  • an initial auxiliary layer 180 is formed.
  • the initial auxiliary layer 180 covers the top surface of the substrate 100 and the outer surface of the dielectric structure 225 .
  • the initial auxiliary layer 180 On a cross-section perpendicular to the substrate 100 , the initial auxiliary layer 180 Have a predetermined thickness.
  • the material of the initial auxiliary layer 180 includes polysilicon.
  • the initial auxiliary layer 180 is etched at a speed equal to the speed of etching the initial auxiliary layer 180 in the horizontal direction and the speed of etching the initial auxiliary layer 180 in the vertical direction, and the top of the covering substrate 100 is removed.
  • the initial auxiliary layer 180 on the surface and the initial auxiliary layer 180 covering the outer surface of the dielectric structure 225 , and a portion of the initial auxiliary layer 180 located at the connection corner between the dielectric structure 225 and the substrate 100 is retained to form the auxiliary layer 181 .
  • the auxiliary layer 181 has a horizontal width that gradually decreases in a direction away from the substrate 100 .
  • Step S140 Pattern the substrate based on the auxiliary layer and the dielectric structure, and transfer the pattern of the auxiliary layer to the substrate.
  • the pattern of the auxiliary layer 181 is transferred into the substrate 100 , and an intermediate doped region 113 having a gradually decreasing horizontal width in the direction away from the substrate 100 is formed, and the dielectric structure 225
  • the substrate 100 below is not etched, the substrate 100 below the dielectric structure 225 forms a top doped region 111 with a first width, and the substrate 100 not covered by the auxiliary layer 181 and the dielectric structure 225 is partially etched and removed.
  • forming an initial bottom doped region 114, and the middle doped region 113 connects the initial bottom doped region 114 and the top doped region 111.
  • the etching ratio of the auxiliary layer 181 and the substrate 100 is controlled, the auxiliary layer 181 and the substrate 100 are simultaneously etched, and the second doped region not covered by the auxiliary layer 181 and the dielectric structure 225 is removed. 152 and part of the first doped region 151 below the second doped region 152, while removing at least part of the first doped region 151 and part of the second doped region 152 below the auxiliary layer 181.
  • the etching ratio between the etching auxiliary layer 181 and the etching substrate 100 can be controlled at 1:1-1:2.
  • the etching ratio between the etching auxiliary layer 181 and the etching substrate 100 can be 1:1, 1 :1.1, 1:1.2, 1:1.4, 1:1.5, 1:1.7, 1:1.9 or 1:2.
  • the second doped region 152 below the dielectric structure 225 is not etched, forming a top doped region 111 , and the top doped region 111 has a first width L1 .
  • the topography of the auxiliary layer 181 is transferred to the retained portion of the first doped region 151 to form an intermediate doped region 113.
  • the intermediate doped region 113 has a gradually changing third width L3.
  • the third width L3 changes along the distance away from the initial state. gradually decreases in the direction of the substrate 150 .
  • the remaining portion of the first doped region 151 below the bottom surface of the middle doped region 113 forms an initial bottom doped region 114 .
  • Step S150 Form a stacked structure that covers at least the middle doped region and part of the initial bottom doped region.
  • the part of the initial bottom doped region covered by the stacked structure forms a bottom doped region, and the bottom doped region has a second width and a first width. Greater than the second width.
  • forming the stacked structure 200 at least includes the following steps: forming a gate dielectric layer 201 covering the surface of the middle doped region 113 and the bottom doped region 112, wherein, in a cross-section perpendicular to the substrate 100, the gate The thickness of the dielectric layer 201 is the same as or different from the thickness of the first dielectric layer 230 .
  • a first gate conductive layer 212 and a second gate conductive layer 213 are formed to cover the gate dielectric layer 201. In a cross section perpendicular to the substrate 100, the thickness of the first gate conductive layer 212 is smaller than the thickness of the second gate conductive layer 213.
  • the stacked structure 200 In a direction parallel to the substrate 100, the stacked structure 200 has a varying or fixed width. Therefore, while the stacked structure 200 covers the middle doped region 113, it also covers the initial bottom doped region adjacent to the middle doped region 113. On part of the top surface of 114, the initial bottom doped region 114 covered by the stacked structure 200 forms the bottom doped region 112, and the top doped region 111, the middle doped region 113 and the bottom doped region 112 together form the doped region 110.
  • the auxiliary layer and the dielectric structure are used as masks to etch the substrate to form a doped region.
  • the morphology of the auxiliary layer is transferred to the substrate to form an intermediate doped region.
  • the intermediate doped region forms the doped region.
  • the fin-shaped structure is arranged in a direction away from the substrate, the doped region is raised relative to the substrate, and the stacked structure covers the doped region, which increases the contact area between the stacked structure and the doped region.
  • this embodiment is a further explanation of a possible implementation of step S150 of the above embodiment.
  • the bottom doped region 112, the middle doped region 113 and the top doped region 111 of the doped region 110 have the same conductivity type. That is, the bottom doped region 112, the middle doped region 113, and the top doped region 111 may each have an N-type conductivity type or a P-type conductivity type.
  • forming a stacked structure that at least covers the middle doped region and part of the initial bottom doped region includes the following steps:
  • Step S151a Form a gate dielectric layer covering the surface of the middle doped region and the surface of the bottom doped region. In a cross-section perpendicular to the substrate, the thickness of the gate dielectric layer is the same as or different from the thickness of the first dielectric layer.
  • the gate dielectric layer 201 can be formed by the following method: as shown in FIG. 13 , with reference to FIG. 12 , the substrate 100 is processed through a thermal oxidation process to form the first oxide layer 101 on the outer surface of the substrate 100 .
  • part of the first oxide layer 101 is removed, leaving part of the first oxide layer 101 covering the middle doped region 113 to form a gate dielectric layer 201 .
  • Step S152a Form a first initial gate conductive layer covering the gate dielectric layer, perform a first etching on the first initial gate conductive layer, control the etching conditions of the first etching, and form a first gate conductive layer conformable to the gate dielectric layer. layer.
  • a first initial gate conductive layer 102 is deposited through an atomic layer deposition process (Atomic Layer Deposition, ALD) or a chemical vapor deposition process (Chemical Vapor Deposition, CVD).
  • the first initial gate conductive layer 102 covers the top surface of the substrate 100, the gate dielectric layer 201 and the outer surface of the dielectric structure 225, is affected by the morphology of the outer surface of the middle doped region 113, and is located in the middle on a cross-section perpendicular to the substrate 100.
  • the thickness of the first initial gate conductive layer 102 on the doped region 113 is greater than the thickness of the first initial gate conductive layer 102 on the top surface of the substrate 100 .
  • a first etching is performed on the first initial gate conductive layer 102 , and the etching conditions of the first etching are controlled so that the speed of etching the first initial gate conductive layer 102 in the horizontal direction is equal to the
  • the first initial gate conductive layer 102 is etched at the same speed in the vertical direction, part of the first initial gate conductive layer 102 is removed, part of the sidewall of the second dielectric layer 221 is exposed, and the retained first initial gate conductive layer 102 is formed.
  • the first gate conductive layer 212 covers the middle doped region 113 and part of the initial bottom doped region 114 connected to the middle doped region 113.
  • the part of the initial bottom doped region covered by the first gate conductive layer 212 Region 114 forms bottom doped region 112 .
  • the material of the first gate conductive layer 212 includes polysilicon. During the process of depositing the polysilicon, some doping ions can be doped into the polysilicon to modulate the work function of the first gate conductive layer 212 .
  • the thickness of the first gate conductive layer 212 is approximately 20 nm to 35 nm, which is approximately the same as the thickness of the gate electrode in the planar transistor. The thickness of the first gate conductive layer 212 is thin enough to ensure the first The polysilicon in the gate conductive layer 212 has the same crystal orientation, and the first gate conductive layer 212 has good conductivity.
  • the first gate conductive layer 212 formed in this embodiment has the same morphology as the gate dielectric layer 201 , and the thickness of the first gate conductive layer 212 is equal in the direction parallel to the substrate 100 .
  • Step S153a Form a second initial gate conductive layer covering the first gate conductive layer, perform a second etching on the second initial gate conductive layer, control the etching conditions of the second etching, and form a first gate conductive layer on a cross section perpendicular to the substrate.
  • the first thickness of the second gate conductive layer gradually increases from the bottom doped region to the top doped region in a direction parallel to the substrate.
  • a metal conductive material is deposited through an atomic layer deposition process or a chemical vapor deposition process to form a second initial gate conductive layer 103 , and the second initial gate conductive layer 103 covers the top surface of the substrate 100 , the first gate conductive layer 212 and the outer surface of the dielectric structure 225 .
  • the metal conductive material may include metal titanium (Titanium), metal tantalum (Tantalum), metal tungsten (Tungsten) or one of its alloys.
  • the second gate conductive layer 213 formed in this embodiment has a first thickness D1.
  • the first thickness D1 is formed. The thickness D1 gradually increases.
  • the dielectric structure 225 is etched simultaneously, and the second initial gate conductive layer 103 and the second initial gate conductive layer 103 are etched in the vertical direction.
  • the speed of the dielectric structure 225 is the same, and the retained dielectric structure 225 forms a dielectric stack structure 220 , and the top surface of the dielectric stack structure 220 is higher than the top surface of the second gate conductive layer 213 .
  • the semiconductor structure formed in this embodiment uses the gate dielectric layer 201 as the gate dielectric layer 211 .
  • the second gate dielectric layer is entirely located above the first gate conductive layer. There is no direct overlap between the second gate dielectric layer and the substrate.
  • the second gate dielectric layer passes through the first gate conductive layer and the substrate.
  • the substrate contacts; and, on a cross section parallel to the substrate, the thickness of the first gate conductive layer is relatively uniform, and the first gate conductive layer has a good work function adjustment effect and avoids the metal conductive material in the second gate conductive layer. Affects the threshold voltage of the transistor to ensure that the transistor with the stacked structure and doped region of this embodiment has good sensitivity.
  • the transistor with the stacked structure and the doped region of this embodiment uses part of the doped region covered by the gate stack structure as the channel.
  • the gate stack structure surrounds the channel, increasing the contact area between the gate stack structure and the channel. , increasing the gate's ability to control the channel of the transistor.
  • this embodiment is a further explanation of a possible implementation of step S150 of the above embodiment.
  • the bottom doped region 112 and the middle doped region 113 of the doped region 110 have the same conductivity type.
  • the top doped region 111 and the middle doped region 113 have different doping types. That is, in this embodiment, the bottom doped region 112 and the middle doped region 113 can both have N-type conductivity types.
  • the top doped region 111 has a P-type conductivity type; alternatively, the bottom doped region 112 and the middle doped region 113 can both have a P-type conductivity type, and the top doped region 111 has an N-type conductivity type.
  • forming a stacked structure that at least covers the middle doped region and part of the initial bottom doped region includes the following steps:
  • Step S151b Form a gate dielectric layer covering the surface of the middle doped region and the surface of the bottom doped region.
  • the thickness of the gate dielectric layer is the same as or different from the thickness of the first dielectric layer.
  • the implementation method of forming the gate dielectric layer 201 is the same as the implementation method of the gate dielectric layer 201 in step S151a in the above embodiment, and will not be described again.
  • Step S152b Form a first initial gate conductive layer covering the gate dielectric layer, perform a first etching on the first initial gate conductive layer, control the etching conditions of the first etching, and form a first gate conductive layer conformable to the gate dielectric layer. layer.
  • the implementation method of forming the first gate conductive layer 212 is the same as the implementation method of the first gate conductive layer 212 in step S152a in the above embodiment, and will not be described again.
  • Step S153b Remove the dielectric structure to expose the first dielectric layer on the top doped region.
  • all the dielectric structures 225 may be removed by dry etching or wet etching to expose the first dielectric layer 230 .
  • the first dielectric layer 230 and the first gate conductive layer 212 form a groove 205 above the top doped region 111 .
  • Step S154b Form a second initial gate conductive layer.
  • the second initial gate conductive layer covers the first gate conductive layer and the exposed first dielectric layer. Perform a second etching on the second initial gate conductive layer to form a second gate conductive layer.
  • a metal conductive material is deposited through an atomic layer deposition process or a chemical vapor deposition process to form a second initial gate conductive layer 103 .
  • the second initial gate conductive layer 103 covers the top surface of the substrate 100 and the second initial gate conductive layer 103 .
  • a gate conductive layer 212 fills the groove 205.
  • the metal conductive material is the same as the material of the second initial gate conductive layer 103 in the above embodiment.
  • a second etching is performed on the second initial gate conductive layer 103 , and the etching conditions of the second etching are controlled so that the speed of etching the second initial gate conductive layer 103 in the vertical direction is is greater than the speed of etching the second initial gate conductive layer 103 in the horizontal direction.
  • the entire second initial gate conductive layer 103 on the top surface of the substrate 100 is removed and part of the sidewall of the first gate conductive layer 212 connected to the substrate 100 is exposed.
  • the retained second initial gate conductive layer 103 forms a second gate.
  • the first dielectric layer 230 and the gate dielectric layer 201 together form the gate dielectric layer 211 .
  • the first gate conductive layer 212 contacts the bottom doped region 112 and the middle doped region 113 through the gate dielectric layer 201 .
  • Part of the second gate conductive layer 213 is located on the first gate conductive layer 212 , and the other part of the second gate conductive layer 213 Contact is made through the first dielectric layer 230 and the top doped region 111 .
  • the stacked structure formed in this embodiment only includes a gate stack structure.
  • the second gate conductive layer not only covers part of the second gate conductive layer, but also fills the groove surrounded by the first gate conductive layer and the first dielectric layer, increasing the number of gate electrodes.
  • the proportion of the second gate conductive layer in the electrode stack structure is increased, thereby improving the electrical performance of the semiconductor structure.
  • this embodiment is a further explanation of the above-mentioned embodiment. Compared with the above embodiment, this embodiment adds the following steps after step S150 of the embodiment:
  • Step S160 Perform a doping process on the substrates on both sides of the stacked structure to form a first lightly doped region and a second lightly doped region in the substrate.
  • the sidewalls of the stack structure 200 are used as masks to inject doping ions into the substrate 100.
  • a first lightly doped region 510 and a second lightly doped region 520 are formed in the substrate 100 on both sides of the structure 200 .
  • the first lightly doped region 510 is connected to the bottom doped region 112
  • the second lightly doped region 520 is connected to the bottom doped region 112 .
  • Step S170 Form an isolation structure, which at least covers the stacked structure.
  • the isolation structure 300 can be formed by the following method: depositing an isolation material, and the isolation material covers the outer surface of the stacked structure 200 And covering the top surface of the substrate 100, and then etching to remove part of the isolation material to expose the top surface of the substrate 100.
  • the retained isolation material forms an isolation structure 300, and the isolation structure 300 covers the stacked structure 200.
  • Step S180 Using the isolation structure as a mask, perform a source and drain doping process on the substrate to form a source region and a drain region in the substrate.
  • doping ions are respectively implanted into the substrate 100 outside the isolation structure 300 through an ion implantation process or a diffusion process, and are distributed on both sides of the stacked structure 200 to form Source region 410 and drain region 420.
  • the first lightly doped region 510 is located between the source region 410 and the bottom doped region 112 to block the source.
  • the first doped ions in region 410 diffuse toward the bottom doped region 112 .
  • the second lightly doped region 520 blocks the first doped ions in the drain region 420 from diffusing toward the bottom doped region 112 .
  • Step S190 Form a second plug perpendicular to the top surface of the substrate, the second plug is in contact with the source region, and form a third plug perpendicular to the top surface of the substrate, and the third plug is in contact with the drain region .
  • the stack structure 200 includes a gate stack structure 210 and a dielectric stack structure 220 for description.
  • a dielectric material is deposited to cover the substrate 100 and the stacked structure 200 .
  • the top surface of the dielectric material is higher than the top surface of the stacked structure 200 .
  • the dielectric material is etched back to expose the isolation structure 300 .
  • a dielectric layer 600 is formed on the top surface.
  • part of the dielectric layer 600, part of the dielectric stack structure 220 and part of the substrate 100 are removed to form a second trench 602 and a third trench 603 respectively.
  • the second trench 602 extends to the substrate.
  • the third trench 603 extends into the substrate 100 and exposes a portion of the source region 410 .
  • the third trench 603 extends into the substrate 100 and exposes a portion of the drain region 420 .
  • a barrier material (not shown in the figure) is deposited, and the barrier material covers the inner wall of the second trench 602 and the inner wall of the third trench 603 .
  • the material of the barrier material may comprise titanium or a titanium compound, or the material of the barrier material may comprise tantalum or a tantalide compound.
  • metal material is filled in the second trench 602 and the third trench 603 respectively.
  • the metal material in the second trench 602 forms The second plug 620 is perpendicular to the top surface of the substrate 100 and is in contact with the source region 410 .
  • the metal material in the third trench 603 forms a third plug 630 perpendicular to the top surface of the substrate 100 , and the third plug 630 is in contact with the drain region 420 .
  • the metal material may include tungsten or tungsten compound.
  • part of the metal material forms the metal layer 650.
  • the metal layer 650 covers the top surface of the dielectric layer 600 and covers the stacked structure 200.
  • the second plug 620 and the third plug 630 are both in contact with the metal layer 650.
  • the second plug 620 and the third plug 630 can connect the source region 410 and the drain region 420 to other semiconductor structures or devices through the metal layer 650 .
  • multiple insulating structures 651 are formed in the metal layer 650.
  • the multiple insulating structures 651 divide the metal layer 650 into multiple independently arranged parts.
  • the second plug The second plug 620 and the third plug 630 are respectively connected to different parts of the metal layer 650.
  • the second plug 620 and the third plug 630 can be connected to the same or different devices through different parts of the metal layer 650.
  • the isolation structure 300 may include a single-layer structure or a multi-layer structure.
  • the isolation structure 300 is a multi-layer structure, and the isolation structure 300 includes a first isolation layer 310, a middle isolation layer 320 and an outer isolation layer 330.
  • the stack structure 200 includes a gate stack structure 210 and a dielectric stack structure 220 for description.
  • forming the isolation structure 300 includes the following steps:
  • a first isolation layer 310 is formed.
  • the first isolation layer 310 covers at least part of the outer surface of the stacked structure 200 and part of the top surface of the substrate 100 adjacent to the stacked structure 200 .
  • an intermediate isolation layer 320 is formed.
  • the intermediate isolation layer 320 covers at least the first isolation layer 310 and a portion of the top surface of the substrate 100 adjacent to the first isolation layer 310 .
  • an outer isolation layer 330 is formed, covering the middle isolation layer 320 and the uncovered outer surface of the stacked structure 200.
  • this embodiment is a further explanation of a possible implementation of the above embodiment.
  • this embodiment adds the following steps: forming a first plug, which penetrates the dielectric structure and the first dielectric layer in a direction perpendicular to the substrate, and connects with the top doped region Contact connection.
  • the stacked structure 200 of the semiconductor structure of this embodiment includes a gate stacked structure 210 and a dielectric stacked structure 220 .
  • part of the dielectric stack structure 220 is removed to form the first trench 601 .
  • the first trench 601 extends to the substrate.
  • the top doped region 111 is exposed in the bottom 100 .
  • the first trench 601 is filled with metal material to form a first plug 610 .
  • the first plug 610 is used to connect the gate stack structure 210 to the metal layer 650 and connect the gate electrode through the metal layer 650 .
  • Stacked structure 210 is connected to other semiconductor structures or devices.
  • the first plug 610 , the second plug 620 and the third plug 630 are respectively connected to different parts of the metal layer 650 .
  • the three plugs 630 may be connected to the same or different devices through different portions of the metal layer 650 .
  • the stack structure 200 in the semiconductor structure of this embodiment only includes a gate stack structure 210.
  • this embodiment adds the following steps: forming a fourth plug, perpendicular to the substrate. In the direction of the bottom, the fourth plug is in contact with the top doped region.
  • a fourth trench (not shown in the figure) is formed at the same time, and the fourth trench exposes part of the top doped In the impurity region 111, a barrier material is then deposited, and the barrier material covers the trench wall of the fourth trench.
  • the fourth trench is filled with metal material.
  • the metal material in the fourth trench forms a fourth plug 640.
  • the fourth plug 640 contacts the metal layer 650.
  • the fourth plug 640 can connect the gate through the metal layer 650.
  • the pole stack structure 210 is connected to other semiconductor structures or devices.
  • the fourth plug 640 , the second plug 620 and the third plug 630 are respectively connected to different parts of the metal layer 650 .
  • the three plugs 630 may be connected to the same or different devices through different portions of the metal layer 650 .
  • the stacked structure of the semiconductor structure covers the doping region, and the doping region includes a middle doping region.
  • the middle doping region In a direction parallel to the substrate, the middle doping region The width gradually decreases in the direction away from the substrate, so that the doped region forms a fin-shaped structure that protrudes outward relative to the substrate, thereby increasing the contact area between the stacked structure and the doped region.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本公开提供一种半导体结构及半导体结构的制作方法，涉及半导体技术领域，半导体结构包括衬底和位于衬底上的堆叠结构；位于堆叠结构与衬底之间的掺杂区，在垂直于衬底的截面上，掺杂区包括顶部掺杂区、底部掺杂区以及连接顶部掺杂区和底部掺杂区的中间掺杂区，在平行于衬底的方向上，顶部掺杂区具有第一宽度，底部掺杂区具有第二宽度，中间掺杂区具有逐渐变化的第三宽度，其中，第一宽度大于第二宽度，第三宽度在沿着远离衬底的方向上逐渐减小。

Description

半导体结构及半导体结构的制作方法
本公开基于申请号为202210484142.4、申请日为2022年05月06日、申请名称为“半导体结构及半导体结构的制作方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种半导体结构及半导体结构的制作方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)通常包括阵列(Array)区域和位于阵列区域外部的核心(Core)区域。阵列区域具有呈阵列排布的晶体管。
随着芯片集成度不断提高，晶体管的特征尺寸减小，晶体管的沟道长度也随之减小，可能导致晶体管出现短沟道效应，短沟道效应可能会引发晶体管产生漏电，严重影响晶体管的电性能。并且，晶体管的特征尺寸减小，栅极的尺寸减小，栅极对沟道的控制能力会降低，影响晶体管的灵敏度，降低半导体结构的良率。
因此，如何降低半导体结构中晶体管的短沟道效应，提高栅极对沟道的控制能力、提高半导体结构的良率，是当前亟待解决的技术问题。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种半导体结构及半导体结构的制作方法。
本公开的第一方面提供了一种半导体结构，所述半导体结构包括：
衬底和位于所述衬底上的堆叠结构；
位于所述堆叠结构与所述衬底之间的掺杂区，在垂直于所述衬底的截面上，所述掺杂区包括顶部掺杂区、底部掺杂区以及连接所述顶部掺杂区和所述底部掺杂区的中间掺杂区，在平行于所述衬底的方向上，所述顶部掺杂区具有第一宽度，所述底部掺杂区具有第二宽度，所述中间掺杂区具有逐渐变化的第三宽度，其中，所述第一宽度大于所述第二宽度，所述第三宽度在沿着远离所述衬底的方向上逐渐减小。
其中，所述堆叠结构包括栅极堆叠结构，所述栅极堆叠结构包括与所述掺杂区接触的栅介质层和位于所述栅介质层上的第一栅导电层和第二栅导电层，在垂直于所述衬底的截面上，所述第一栅导电层的厚度小于所述第二栅导电层的厚度。
其中，在垂直于所述衬底的截面上，所述第二栅导电层具有第一厚度；
沿平行于所述衬底的方向，由所述底部掺杂区至所述顶部掺杂区，所述第一厚度逐渐增大。
其中，所述半导体结构还包括第一介电层，所述第一介电层位于所述堆叠结构和所述顶部掺杂区之间，所述栅介质层与所述第一介电层相连，所述栅介质层与所述第一栅导电层接触，所述第一介电层与所述第二栅导电层接触；
其中，在垂直于所述衬底方向的截面上，所述栅介质层和所述第一介电层的厚度相同或不同。
其中，所述堆叠结构还包括位于所述顶部掺杂区上的介电堆叠结构，所述栅极堆叠结构位于所述中间掺杂区和所述底部掺杂区上，其中，所述介电堆叠结构的顶表面高于所述栅极堆叠结构的顶表面。
其中，所述介电堆叠结构包括第二介电层和第三介电层，在垂直于所述衬底的截面上，所述第二介电层的顶表面高于所述第一栅导电层的顶表面，所述第二介电层的顶表面低于所述第二栅导电层的顶表面，所述第三介电层的顶表面高于所述第二栅导电层的顶表面。
其中，所述半导体结构还包括第一插塞，所述第一插塞贯穿所述介电堆叠结构，并与所述顶部掺杂区接触连接。
其中，所述第一栅导电层包括功函数调节材料，所述第二栅导电层包括金属导电材料。
其中，所述底部掺杂区和所述中间掺杂区的掺杂类型相同，所述顶部掺杂区和所述中间掺杂区的掺杂类型相同或不同。
其中，所述半导体结构还包括隔离结构，所述隔离结构覆盖所述堆叠结构。
其中，所述半导体结构还包括设置于所述衬底中的源区和漏区，所述源区和所述漏区位于所述堆叠结构的两侧。
其中，所述半导体结构还包括：
第二插塞，所述第二插塞垂直于所述衬底设置，所述第二插塞与所述源区接触连接；
第三插塞，所述第三插塞垂直于所述衬底设置，所述第三插塞与所述漏区接触连接。
本公开的第二方面提供了一种半导体结构的制作方法，所述制作方法，包括：
提供衬底；
在所述衬底上形成介电结构，所述介电结构覆盖所述衬底的部分表面；
在所述介电结构的外侧形成覆盖部分所述衬底表面的辅助层，所述辅助层在远离所述衬底的方向上具有逐渐减小的水平宽度；
基于所述辅助层和所述介电结构对所述衬底进行图形化处理，将所述辅助层的图形转移到所述衬底中，以在所述衬底中形成在远离所述衬底的方向上具有逐渐减小的水平宽度的中间掺杂区，所述介电结构的下方的所述衬底未被蚀刻，所述介电结构下方的所述衬底形成具有第一宽度的顶部掺杂区，未被所述辅助层和所述介电结构覆盖的所述衬底被部分蚀刻去除，形成初始底部掺杂区，所述中间掺杂区连接所述初始底部掺杂区和所述顶部掺杂区；
形成至少覆盖所述中间掺杂区和部分所述初始底部掺杂区的堆叠结构，被所述堆叠结构覆盖的部分所述初始底部掺杂区形成底部掺杂区，所述底部掺杂区具有第二宽度，所述第一宽度大于所述第二宽度。
其中，所述介电结构和所述衬底之间还形成有第一介电层，形成至少覆盖所述中间掺杂区和部分所述初始底部掺杂区的堆叠结构，包括：
形成覆盖所述中间掺杂区表面以及所述底部掺杂区表面的栅极介质层，在垂直于所述衬底的截面上，所述栅极介质层的厚度与所述第一介电层的厚度相同或不同；
形成覆盖所述栅极介质层的第一栅导电层和第二栅导电层，在垂直于所述衬底的截面上，所述第一栅导电层的厚度小于所述第二栅导电层的厚度。
其中，形成覆盖所述栅极介质层的第一栅导电层和第二栅导电层，包括:
形成覆盖所述栅极介质层的第一初始栅导电层，对所述第一初始栅导电层进行第一蚀刻，控制所述第一蚀刻的蚀刻条件，形成与所述栅极介质层共形的所述第一栅导电层；
形成覆盖所述第一栅导电层的第二初始栅导电层，对所述第二初始栅导电层进行第二蚀刻，控制所述第二蚀刻的蚀刻条件，形成在垂直于所述衬底的截面上具有第一厚度的第二栅导电层，沿平行于所述衬底的方向，由所述底部掺杂区至所述顶部掺杂区，所述第一厚度逐渐增大。
其中，在形成所述第一栅导电层之后，在形成所述第二栅导电层之前，还包括：
去除所述介电结构，暴露出所述顶部掺杂区上的所述第一介电层；
在所述第一栅导电层上和暴露的所述第一介电层上形成所述第二初始栅导电层。
其中，提供衬底，包括：
提供初始衬底，在所述初始衬底中形成第一掺杂区；
在所述第一掺杂区上形成第二掺杂区，其中，所述第一掺杂区和所述第二掺杂区的掺杂离子类型相同或不同。
其中，基于所述辅助层和所述介电结构对所述衬底进行图形化处理，将所述辅助层的图形转移到所述衬底中，包括：
控制所述辅助层和所述衬底的蚀刻比，同步蚀刻所述辅助层和所述衬底，去除未被所述辅助层和所述介电结构覆盖的所述第二掺杂区和所述第二掺杂区下方的部分所述第一掺杂区，同时去除所述辅助层下方的至少部分第一掺杂区和部分第二掺杂区。
其中，所述半导体结构的制作方法，还包括：
形成第一插塞，在垂直于所述衬底的方向上，所述第一插塞贯穿所述介电结构和所述第一介电层，与所述顶部掺杂区接触连接。
其中，所述半导体结构的制作方法，还包括：
形成隔离结构，所述隔离结构至少覆盖所述堆叠结构；
以所述隔离结构为掩膜，对所述衬底进行源漏掺杂工艺，在所述衬底中形成源区和漏区；
形成垂直于所述衬底的顶面的第二插塞，所述第二插塞与所述源区接触连接；
形成垂直于所述衬底的顶面的第三插塞，所述第三插塞与所述漏区接触连接。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1是根据一示例性实施例示出的半导体结构的结构示意图。
图2是根据一示例性实施例示出的半导体结构的结构示意图。
图3是根据一示例性实施例示出的半导体结构的结构示意图。
图4是根据一示例性实施例示出的半导体结构的结构示意图。
图5是根据一示例性实施例示出的半导体结构的结构示意图。
图6是根据一示例性实施例示出的半导体结构的结构示意图。
图7是根据一示例性实施例示出的衬底的示意图。
图8是根据一示例性实施例示出的形成介电材料层的示意图。
图9是根据一示例性实施例示出的形成介电结构的示意图。
图10是根据一示例性实施例示出的形成初始辅助层的示意图。
图11是根据一示例性实施例示出的形成辅助层的示意图。
图12是根据一示例性实施例示出的根据辅助层和介电结构蚀刻衬底的示意图。
图13是根据一示例性实施例示出的形成第一氧化层的示意图。
图14是根据一示例性实施例示出的形成栅极介质层的示意图。
图15是根据一示例性实施例示出的形成第一初始栅导电层的示意图。
图16是根据一示例性实施例示出的形成第一栅导电层的示意图。
图17是根据一示例性实施例示出的形成第二初始栅导电层的示意图。
图18是根据一示例性实施例示出的形成第一轻掺杂区和第二轻掺杂区的示意图。
图19是根据一示例性实施例示出的形成源区和漏区的示意图。
图20是根据一示例性实施例示出的形成介质层的示意图。
图21是根据一示例性实施例示出的在介质层中形成第一沟槽、第二沟槽和第三沟槽的示意图。
图22是根据一示例性实施例示出的在介质层中形成第一插塞、第二插塞和第三插塞的示意图。
图23是根据一示例性实施例示出的去除介电结构的示意图。
图24是根据一示例性实施例示出的形成第二初始栅导电层的示意图。
图25是根据一示例性实施例示出的在介质层中形成第二插塞、第三插塞和第四插塞的示意图。
图26是根据一示例性实施例示出的半导体结构的制作方法的流程图。
图27是根据一示例性实施例示出的形成堆叠结构的流程图。
图28是根据一示例性实施例示出的半导体结构的制作方法的流程图。
附图标记：
100、衬底；101、第一氧化层；102、第一初始栅导电层；103、第二初始栅导电层；110、掺杂区；111、顶部掺杂区；112、底部掺杂区；113、中间掺杂区；114、初始底部掺杂区；150、初始衬底；151、第一掺杂区；152、第二掺杂区；153、第一初始介电层；160、介电材料层；161、第二初始介电层；162、第三初始介电层；163、第四初始介电层；170、掩膜层；180、初始辅助层；181、辅助层；200、堆叠结构；201、栅极介质层；205、凹槽；210、栅极堆叠结构；211、栅介质层；212、第一栅导电层；213、第二栅导电层；220、介电堆叠结构；225、介电结构；221、第二介电层；222、第三介电层；223、第四介电层；230、第一介电层；300、隔离结构；310、第一隔离层；320、中间隔离层；330、外部隔离层；410、源区；420、漏区；510、第一轻掺杂区；520、第二轻掺杂区；600、介质层；601、第一沟槽；602、第二沟槽；603、第三沟槽；610、第一插塞；620、第二插塞；630、第三插塞；640、第四插塞；650、金属层；651、绝缘结构；
L1、第一宽度；L2、第二宽度；L3、第三宽度；D1、第一厚度。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他 实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开示例性实施例提供了一种半导体结构及半导体结构的制作方法，半导体结构的堆叠结构覆盖掺杂区，掺杂区包括中间掺杂区，在垂直于衬底方向的截面上，中间掺杂区的水平宽度在沿着远离衬底的方向上逐渐减小，以将掺杂区形成相对于衬底向外凸起的鳍形结构，增加了堆叠结构和掺杂区的接触面积。
本公开示例性实施例提供了一种半导体结构，如图1或图4所示，半导体结构包括衬底100和位于衬底100上的堆叠结构200。半导体结构还包括位于堆叠结构200与衬底100之间的掺杂区110，在垂直于衬底100的截面上，即图1中示出的截面，掺杂区110包括顶部掺杂区111、底部掺杂区112以及连接顶部掺杂区111和底部掺杂区112的中间掺杂区113，在平行于衬底100的方向上，顶部掺杂区111具有第一宽度L1，底部掺杂区112具有第二宽度L2，中间掺杂区113具有逐渐变化的第三宽度L3，其中，第一宽度L1大于第二宽度L2，第三宽度L3在沿着远离衬底100的方向上逐渐减小，即以图1中示出的方位为准，沿由下至上的方向，第三宽度L3的尺寸逐渐减小。
其中，中间掺杂区113的顶表面高于底部掺杂区112的顶表面，中间掺杂区113的最大宽度为L3 MAX，L3 MAX大于第二宽度L2。
在一些实施例中，第一宽度L1的范围为5nm-50nm，第二宽度L2的范围为1nm-20nm，第三宽度L3 MAX的范围为1nm-100nm，第三宽度L3的变化范围为0-L3 MAX。
示例性的，第一宽度L1可以为5nm、8nm、12nm、15nm、20nm、25nm、30nm、35nm、40nm、45nm或50nm。第二宽度L2可以为1nm、2nm、3nm、4nm、5nm、6nm、7nm、8nm、9nm或10nm。第三宽度L3的变化范围可以为0nm-1nm、0nm-10nm、0nm-20nm、0nm-30nm、0nm-35nm、0nm-50nm、0nm-60nm、0nm-70nm、40nm-80nm、50nm-90nm或60nm-100nm。
例如，第一宽度L1可以为5nm，第二宽度L2可以为1nm，第三宽度L3 MAX可以为5nm，第三宽度L3的变化范围为0nm-5nm。或者，第一宽度L1可以为15nm，第二宽度L2可以为4nm，第三宽度L3 MAX可以为10nm，第三宽度L3的变化范围为0nm-10nm。再或者，第一宽度L1可以为25nm，第二宽度L2可以为7nm，第三宽度L3 MAX可以为20nm，第三宽度L3的变化范围为0nm-20nm。
在一些实施例中，L3 MAX大于第一宽度L1。例如，第一宽度L1可以为30nm，第二宽度L2可以为6nm，第三宽度L3 MAX可以为40nm，第三宽度L3的变化范围为0nm-40nm。或者，第一宽度L1可以为15nm，第二宽度L2可以为8nm，第三宽度L3 MAX可以为80nm，第三宽度L3的变化范围为0nm-80nm。再或者，第一宽度L1可以为50nm，第二宽度L2可以为10nm，第三宽度L3 MAX可以为100nm，第三宽度L3的变化范围为0nm-100nm。
其中，底部掺杂区112和中间掺杂区113的掺杂类型相同，顶部掺杂区111和中间掺杂区113的掺杂类型相同或不同。
在一些实施例中，如图1或图4所示，堆叠结构200包括栅极堆叠结构210，栅极堆叠结构210包括与掺杂区110接触的栅介质层211和位于栅介质层211上的第一栅导电层212和第二栅导电层213，在垂直于衬底100的截面上，第一栅导电层212的厚度小于第二栅导电层213的厚度。其中，栅极堆叠结构210至少覆盖掺杂区110的底部掺杂区112和中间掺杂区113。在一些实施例中，栅极堆叠结构210还可以覆盖顶部掺杂区111。
在一些实施例中，在垂直于衬底100方向的截面上，第一栅导电层212的厚度为1nm-40nm，例如，第一栅导电层212的厚度可以为1nm-5nm、5nm-10nm、10nm-15nm、15nm-20nm、20nm-25nm、25nm-30nm、30nm-35nm或35nm-40nm。
在一些实施例中，如图1或如图4所示，在垂直于衬底100的截面上第二栅导电层213具有第一厚度D1，沿平行于衬底100的方向，由底部掺杂区112至顶部掺杂区113，第一厚度D1逐渐增大。
其中，第一厚度D1的变化范围为0nm-50nm。例如，第一厚度D1的变化范围可以为0nm-1nm、0nm-5nm、0nm-10nm、0nm-15nm、0nm-20nm、0nm-25nm、0nm-35nm、0nm-45nm或0nm-50nm。
具有本实施例中的栅极堆叠结构210和掺杂区110的晶体管，栅极堆叠结构210覆盖的掺杂区110的外表面为晶体管的沟道。在本实施例中，中间掺杂区113的第三宽度L3沿着远离衬底100的方向上逐渐减小，中间掺杂区113将掺杂区110形成远离衬底100的方向上设置的鳍型结构，掺杂区110相对衬底100隆起，增加了掺杂区110和堆叠结构200的接触面积，进而增加了栅极堆叠结构210和沟道的接触面积，增加了沟道长度，能 够避免或减少短沟道效应；并且，本实施例的栅极堆叠结构210覆盖沟道，当半导体结构处于通电状态时，栅极堆叠结构210至少和中间掺杂区113的接触面的不同位置均产生向中间掺杂区113的中心方向的控制电场，栅极堆叠结构210产生的控制电场在掺杂区110的中心位置汇集，能够增加控制电场的强度，进而提高了栅极堆叠结构210对沟道的控制能力；本实施例的半导体结构，能够进一步缩小器件的特征尺寸，提高半导体器件的集成度。
在一些实施例中，如图1或图4所示，第一栅导电层212包括功函数调节材料，第二栅导电层213包括金属导电材料。第一栅导电层212设置在掺杂区110和第二栅导电层213之间，第一栅导电层212用于调节第二栅导电层213的功函数，有利于降低半导体结构的阈值电压。示例性的，第一栅导电层212包括N型或P型功函数调节材料。在本实施例中，第一栅导电层212的材料可以包括多晶硅，多晶硅的功函数可通过调节掺杂离子的种类以及调节掺杂浓度改变，从而调节由第一栅导电层212和第二栅导电层213组成的栅极结构的功函数，以达到降低阈值电压的效果。
本实施例中第一栅导电层212的厚度和平面晶体管的栅极厚度接近，由于第一栅导电层212的厚度足够小且均匀，在第一栅导电层212的材料包括多晶硅时，多晶硅的晶向相同且晶格均匀，第一栅导电层212的导电性好，有利于器件尺寸的微缩。
在一些实施例中，半导体结构还包括第一介电层230，第一介电层230位于堆叠结构200和顶部掺杂区111之间，栅介质层211与第一介电层230相连，其中，在垂直于衬底100方向的截面上，栅介质层211和第一介电层230的厚度相同或不同。
在一个示例中，本示例的半导体结构，参照图4，掺杂区110的底部掺杂区112、中间掺杂区113和顶部掺杂区111具有相同的导电类型。也即，底部掺杂区112、中间掺杂区113和顶部掺杂区111可以均具有P型导电类型或N型导电类型。如图4、图5或图6所示，本示例的半导体结构，堆叠结构200仅包括栅极堆叠结构210。
在本示例中，栅介质层211包括相连的栅极介质层201以及第一介电层230，栅极介质层201位于栅极堆叠结构210和底部掺杂区112以及中间掺杂区113之间，第一介电层230位于堆叠结构200和顶部掺杂区111之间。其中，栅极介质层201和第一介电层230的厚度相同或不同。例如，栅极介质层201可以和第一介电层230的厚度相同；或者，栅极介质层201的厚度还可以大于或小于第一介电层230的厚度。
如图4、图5或图6所示，第一栅导电层212位于底部掺杂区112和中间掺杂区113之上，第一栅导电层212和栅极介质层201接触。第二栅导电层213位于底部掺杂区112、中间掺杂区113和顶部掺杂区111之上，第二栅导电层213的部分结构和第一栅导电层212接触，第二栅导电层213的另一部分结构和第一介电层230接触。
本示例的半导体结构，栅极堆叠结构210覆盖整个掺杂区110，栅极堆叠结构210和掺杂区110的接触面为晶体管的沟道，本示例中晶体管的沟道长度更长；并且，栅极堆叠结构210和顶部掺杂区111以及中间掺杂区113的接触面的不同位置均产生向中间掺杂区113的中心方向的控制电场，在掺杂区110的中心位置汇集的控制电场强度更大，进一步增加了栅极堆叠结构210对沟道的控制能力。
在本示例中，第二栅导电层213不仅覆盖第一栅导电层212，同时还覆盖顶部掺杂区111上的第一介电层230，增加了栅极堆叠结构210中第二栅导电层213的占比，能够提高晶体管的存储能力和控制能力。
在另一个示例中，本示例的半导体结构，参照图1，掺杂区110的底部掺杂区112、中间掺杂区113具有相同的导电类型。顶部掺杂区111和中间掺杂区113的掺杂类型不同。也即，在本实施例中，底部掺杂区112、中间掺杂区113均具有N型导电类型，则顶部掺杂区111具有P型导电类型；或者，底部掺杂区112、中间掺杂区113均具有P型导电类型，则顶部掺杂区111具有N型导电类型。
如图1、图2或图3所示，本示例的半导体结构，堆叠结构200包括位于底部掺杂区112和中间掺杂区113之上的栅极堆叠结构210以及位于顶部掺杂区111上的介电堆叠结构220，第一介电层230设置在介电堆叠结构220和顶部掺杂区111之间。
如图1、图2或图3所示，在垂直于衬底100的方向上，栅极堆叠结构210包括依次设置在底部掺杂区112和中间掺杂区113上的栅介质层211、第一栅导电层212和第二栅导电层213。其中，在垂直于衬底100的截面上，栅介质层211与第一介电层230的厚度相同或不同。栅介质层211可以与第一介电层230的厚度相同，或者，栅介质层211的厚度还可以大于或小于第一介电层230的厚度。
如图1、图2或图3所示，介电堆叠结构220包括第二介电层221和第三介电层222，在垂直于衬底100的截面上，第二介电层221的顶表面高于第一栅导电层212的顶表面，第二介电层221的顶表面低于第二栅导电层213的顶表面，第三介电层222的顶表面高于第二栅导电层213的顶表面。
本实施例的半导体结构，第二栅导电层213仅设置在第一栅导电层212的上方，第二栅导电层213通过第一栅导电层212和掺杂区110接触连接，在垂直于衬底100的方向上，第二栅导电层213和掺杂区110无直接交叠的区域，栅极堆叠结构210的功函数均匀，避免第二栅导电层213中的金属导电材料影响晶体管的阈值电压，确保半导体结构具有良好的电性能。
在一些实施例中，如图2和图5所示，半导体结构还包括隔离结构300，隔离结构300覆盖堆叠结构200。
如图2所示，或如图5所示，半导体结构还包括设置于衬底100中的源区410和漏区420，在平行于衬底100的方向上，源区410和漏区420位于堆叠结构200的两侧。
在一些实施例中，如图2所示，或如图5所示，半导体结构还包括设置于衬底100中的第一轻掺杂区510和第二轻掺杂区520，在平行于衬底100的方向上，第一轻掺杂区510和第二轻掺杂区520位于堆叠结构200的两侧。其中，第一轻掺杂区510的掺杂深度小于源区410的掺杂深度，且第二轻掺杂区520的掺杂深度小于漏区420的掺杂深度。
如图2所示，或如图5所示，第一轻掺杂区510和底部掺杂区112相接，第二轻掺杂区520和底部掺杂区112相接。第一轻掺杂区510和源区410同侧设置，部分第一轻掺杂区510位于源区410和底部掺杂区112之间，以防止源区410向底部掺杂区112扩散。第二轻掺杂区520和漏区420同侧设置，且部分第二轻掺杂区520位于漏区420和底部掺杂区112之间，防止漏区420向底部掺杂区112扩散。第一轻掺杂区510和第二轻掺杂区520减小了源区410、漏区420和栅极堆叠结构210的交叠范围，能够减小或避免半导体结构的栅极诱导漏极泄漏电流，以使半导体结构的电性能更加稳定，且能够提高半导体结构的使用寿命。
在一些实施例中，如图3或如图6所示，半导体结构还包括第二插塞620和第三插塞630，第二插塞620垂直于衬底100设置，第二插塞620与源区410接触连接，第三插塞630垂直于衬底100设置，第三插塞630与漏区420接触连接。
在一些实施例中，如图3所示，参照图1，半导体结构的堆叠结构200包括栅极堆叠结构210和介电堆叠结构220。半导体结构还包括第一插塞610，第一插塞610贯穿介电堆叠结构220，并与顶部掺杂区111接触连接。
在一些实施例中，如图6所示，参照图3，半导体结构的堆叠结构200仅包括栅极堆叠结构210。半导体结构还包括第四插塞640，第四插塞640垂直设置在栅极堆叠结构210上，第四插塞640与第二栅导电层213接触连接。
本公开示例性的实施例中提供了一种半导体结构的制作方法，本实施例对半导体结构不作限制，下面将半导体结构为动态随机存储器(Dynamic Random Access Memory，DRAM)为例进行介绍。
图26示出了根据本公开一示例性的实施例提供的一种半导体结构的制作方法的流程图，图7-图25为本实施例的半导体结构的制作方法的各个阶段的示意图，下面结合图7-图25并参照图1-图6对本实施例的半导体结构的制作方法进行介绍。如图26所示，本实施例中的半导体结构的制作方法包括以下步骤：
步骤S110：提供衬底。
在本实施例中，提供衬底100，包括：
如图7所示，首先，提供初始衬底150，在初始衬底150中形成第一掺杂区151。初始衬底150的材料包括半导体材料，半导体材料可以为硅(Si)、锗(Ge)、或硅锗(GeSi)、碳化硅(SiC)；半导体材料也可以是绝缘体上硅(SOI)，绝缘体上锗(GOI)；或者还可以为其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。
向初始衬底150中注入掺杂离子形成第一掺杂区151，第一掺杂区151具有第一导电类型，其中，第一导电类型可以为P型导电类型或N型导电类型。
然后，在第一掺杂区151中形成第二掺杂区152，其中，第一掺杂区151和第二掺杂区152的掺杂离子类型相同或不同。在一些实施例中，第二掺杂区152的导电类型和第一掺杂区151的导电类型相同；在另一些实施例中，第二掺杂区152的导电类型和第一掺杂区151的导电类型相反。
接着，形成第一初始介电层153，第一初始介电层153至少覆盖第二掺杂区152。在本实施例中，可以通过沉积工艺或热氧化工艺形成第一初始介电层153，第一初始介电层153覆盖初始衬底150的外表面。其中，第一初始介电层153的材料可以包括氧化物或氮化物，例如，第一初始介电层153的材料可以包括氧化硅或氮化硅中的一种。
步骤S120：在衬底上形成介电结构，介电结构覆盖衬底的部分表面。
在本实施例中，形成介电结构225，可以采用以下方法：
如图8所示，参照图7，于衬底100的顶面形成介电材料层160，介电材料层160覆盖第一初始介电层153。介电材料层160可以包括单层或多层结构，本实施例中以介电材料层160包括多层结构进行说明，沿远离衬底100顶面的方向，即图8中示出的由下至上的方向，介电材料层160包括依次叠置的第二初始介电层161、第三初始介电层162以及第四初始介电层163。其中，介电材料层160的材料包括绝缘材料，例如可以包括氧化硅、氮化硅或氮氧化硅中的至少一种。第二初始介电层161、第三初始介电层162和第四初始介电层163的材料可以相同或不同。
如图8所示，在介电材料层160的顶面形成掩膜层170，掩膜层170覆盖介电材料层160的部分顶面。如图9所示，参照图8，根据掩膜层170蚀刻介电材料层160，被保留的介电材料层160形成介电结构225。本实施例中形成的介电结构225包括依次设置在衬底100上的第二介电层221、第三介电层222以及第四介电层223。
步骤S130：在介电结构的外侧形成覆盖部分衬底表面的辅助层，辅助层在远离衬底的方向上具有逐渐减小的水平宽度。
在介电结构225的外侧形成覆盖部分衬底100表面的辅助层181，可以采用以下方法：
如图10所示，参照图9，形成初始辅助层180，初始辅助层180覆盖衬底100的顶面以及介电结构225的外表面，在垂直于衬底100的截面上，初始辅助层180具有预定厚度。在本实施例中，初始辅助层180的材料包括多晶硅。
然后，如图11所示，参照图10，蚀刻初始辅助层180，在水平方向上蚀刻初始辅助层180的速度和在竖直方向上蚀刻初始辅助层180的速度相等，去除覆盖衬底100顶面的初始辅助层180以及覆盖介电结构225的外表面的初始辅助层180，位于介电结构225和衬底100的连接转角的部分初始辅助层180被保留，形成辅助层181。
如图11所示，在垂直于衬底100的截面上，辅助层181在远离衬底100的方向上具有逐渐减小的水平宽度。
步骤S140：基于辅助层和介电结构对衬底进行图形化处理，将辅助层的图形转移到衬底中。
如图12所示，辅助层181的图形转移到衬底100中，在衬底100中形成在远离衬底100的方向上具有逐渐减小的水平宽度的中间掺杂区113，介电结构225的下方的衬底100未被蚀刻，介电结构225下方的衬底100形成具有第一宽度的顶部掺杂区111，未被辅助层181和介电结构225覆盖的衬底100被部分蚀刻去除，形成初始底部掺杂区114，中间掺杂区113连接初始底部掺杂区114和顶部掺杂区111。
在本实施例中，将辅助层181的图形转移到衬底100中，可以采用以下方法：
如图12所示，参照图11，控制辅助层181和衬底100的蚀刻比，同步蚀刻辅助层181和衬底100，去除未被辅助层181和介电结构225覆盖的第二掺杂区152和第二掺杂区152下方的部分第一掺杂区151，同时去除辅助层181下方的至少部分第一掺杂区151和部分第二掺杂区152。在本实施例中，蚀刻辅助层181和蚀刻衬底100的蚀刻比可以控制在1:1-1:2，例如，蚀刻辅助层181和蚀刻衬底100的蚀刻比可以为1:1、1:1.1、1:1.2、1:1.4、1:1.5、1:1.7、1:1.9或1:2。
如图12所示，介电结构225下方的第二掺杂区152未被蚀刻，形成顶部掺杂区111，顶部掺杂区111具有第一宽度L1。辅助层181的形貌转移到被保留的部分第一掺杂区151中，形成中间掺杂区113，中间掺杂区113具有逐渐变化的第三宽度L3，第三宽度L3在沿着远离初始衬底150的方向上逐渐减小。中间掺杂区113底面以下被保留的部分第一掺杂区151形成初始底部掺杂区114。
步骤S150：形成至少覆盖中间掺杂区和部分初始底部掺杂区的堆叠结构，被堆叠结构覆盖的部分初始底部掺杂区形成底部掺杂区，底部掺杂区具有第二宽度，第一宽度大于第二宽度。
在本实施例中，形成堆叠结构200至少包括以下步骤：形成覆盖中间掺杂区113以及底部掺杂区112表面的栅极介质层201，其中，在垂直于衬底100的截面上，栅极介质层201的厚度与第一介电层230的厚度相同或不同。形成覆盖栅极介质层201的第一栅导电 层212和第二栅导电层213，在垂直于衬底100的截面上，第一栅导电层212的厚度小于第二栅导电层213的厚度。
在平行于衬底100的方向上，堆叠结构200具有变化或固定的宽度，因此，堆叠结构200覆盖中间掺杂区113的同时，也会覆盖和中间掺杂区113邻接的初始底部掺杂区114的部分顶面，被堆叠结构200覆盖的初始底部掺杂区114形成底部掺杂区112，顶部掺杂区111、中间掺杂区113和底部掺杂区112共同形成掺杂区110。
本实施例的制作方法，以辅助层和介电结构作为掩膜蚀刻衬底形成掺杂区，辅助层的形貌转移到衬底中形成中间掺杂区，中间掺杂区将掺杂区形成远离衬底的方向上设置的鳍型结构，掺杂区相对衬底隆起，堆叠结构覆盖掺杂区，增加了堆叠结构和掺杂区的接触面积。
根据一示例性实施例，本实施例是对上述实施例的步骤S150的一种可能的实施方式的进一步说明。在本实施例中，掺杂区110的底部掺杂区112、中间掺杂区113和顶部掺杂区111具有相同的导电类型。也即，底部掺杂区112、中间掺杂区113和顶部掺杂区111可以均具有N型导电类型或P型导电类型。如图27所示，在实施过程中，形成至少覆盖中间掺杂区和部分初始底部掺杂区的堆叠结构，包括以下步骤：
步骤S151a：形成覆盖中间掺杂区表面以及底部掺杂区表面的栅极介质层，在垂直于衬底的截面上，栅极介质层的厚度与第一介电层的厚度相同或不同。
形成栅极介质层201，可以采用以下方法：如图13所示，参照图12，通过热氧化工艺处理衬底100，在衬底100的外表面形成第一氧化层101。
然后，如图14所示，参照图13，去除部分第一氧化层101，保留覆盖中间掺杂区113的部分第一氧化层101，形成栅极介质层201。
步骤S152a：形成覆盖栅极介质层的第一初始栅导电层，对第一初始栅导电层进行第一蚀刻，控制第一蚀刻的蚀刻条件，形成与栅极介质层共形的第一栅导电层。
如图15所示，参照图14，通过原子层沉积工艺(Atomic Layer Deposition，ALD)或化学气相沉积工艺(Chemical Vapor Deposition，CVD)沉积形成第一初始栅导电层102，第一初始栅导电层102覆盖衬底100的顶面、栅极介质层201以及介电结构225的外表面，受到中间掺杂区113的外表面的形貌的影响，在垂直于衬底100的截面上，位于中间掺杂区113上的第一初始栅导电层102的厚度大于位于衬底100顶面上的第一初始栅导电层102的厚度。
然后，如图16所示，参照图15，对第一初始栅导电层102进行第一蚀刻，控制第一蚀刻的蚀刻条件，以使水平方向上蚀刻第一初始栅导电层102的速度和在竖直方向上蚀刻第一初始栅导电层102的速度相等，去除部分第一初始栅导电层102，暴露出第二介电层221的部分侧壁，被保留的第一初始栅导电层102形成第一栅导电层212，第一栅导电层212覆盖中间掺杂区113以及和中间掺杂区113相连的部分初始底部掺杂区114，被第一栅导电层212覆盖的部分初始底部掺杂区114形成底部掺杂区112。
在本实施例中，第一栅导电层212的材料包括多晶硅，在沉积多晶硅的过程中可以向多晶硅中掺杂部分掺杂离子，调制第一栅导电层212的功函数。在垂直于衬底100的方向上，第一栅导电层212的厚度约为20nm～35nm，和平面晶体管中栅极的厚度大致相同，第一栅导电层212的厚度足够薄，能够保证第一栅导电层212中的多晶硅具有相同的晶向，第一栅导电层212具有良好的导电性。并且，本实施例形成的第一栅导电层212与栅极介质层201的形貌相同，在平行于衬底100的方向上，第一栅导电层212的厚度的相等。
步骤S153a：形成覆盖第一栅导电层的第二初始栅导电层，对第二初始栅导电层进行第二蚀刻，控制第二蚀刻的蚀刻条件，形成在垂直于衬底的截面上具有第一厚度的第二栅导电层，沿平行于衬底的方向，由底部掺杂区至顶部掺杂区，第一厚度逐渐增大。
首先，如图17所示，参照图16，通过原子层沉积工艺或化学气相沉积工艺沉积金属导电材料，形成第二初始栅导电层103，第二初始栅导电层103覆盖衬底100的顶面、第一栅导电层212以及介电结构225的外表面。其中，金属导电材料可以包括金属钛(Titanium)、金属钽(Tantalum)、金属钨(Tungsten)或其合金中的一种。
然后，如图1所示，参照图17，对第二初始栅导电层103进行第二蚀刻，控制第二蚀刻的蚀刻条件，以使竖直方向上蚀刻第二初始栅导电层103的速度大于在水平方向上蚀刻第二初始栅导电层103的速度，被保留的第二初始栅导电层103形成第二栅导电层213。在垂直于衬底的截面上，本实施例形成的第二栅导电层213具有第一厚度D1，沿平行于衬底100的方向，由底部掺杂区112至顶部掺杂区111，第一厚度D1逐渐增大。
如图1所示，参照图17，在本实施例中，蚀刻第二初始栅导电层103的过程中，同 时蚀刻介电结构225，并且在竖直方向上蚀刻第二初始栅导电层103和介电结构225的速度相同，被保留的介电结构225形成介电堆叠结构220，介电堆叠结构220的顶面高于第二栅导电层213的顶面。
如图1所示，参照图17，本实施例形成的半导体结构以栅极介质层201作为栅介质层211。
本实施例形成的堆叠结构，第二栅介质层全部位于第一栅导电层的上方，第二栅介质层和衬底没有直接交叠的部分，第二栅介质层通过第一栅导电层和衬底接触；并且，在平行于衬底的截面上，第一栅导电层的厚度相对均匀，第一栅导电层起到了良好的功函数调节效果，避免第二栅导电层中的金属导电材料影响晶体管的阈值电压，确保具有本实施例的堆叠结构和掺杂区的晶体管具有良好的灵敏性。
具有本实施例的堆叠结构和掺杂区的晶体管，以被栅极堆叠结构覆盖的部分掺杂区作为沟道，栅极堆叠结构围绕沟道，增加了栅极堆叠结构和沟道的接触面积，增加了晶体管的栅极对沟道的控制能力。
根据一示例性实施例，本实施例是对上述实施例的步骤S150的一种可能的实施方式的进一步说明。本实施例中，掺杂区110的底部掺杂区112、中间掺杂区113具有相同的导电类型。顶部掺杂区111和中间掺杂区113的掺杂类型不同，也即，在本实施例中，底部掺杂区112、中间掺杂区113可以均具有N型导电类型，则顶部掺杂区111具有P型导电类型；或者，底部掺杂区112、中间掺杂区113还可以均具有P型导电类型，则顶部掺杂区111具有N型导电类型。如图28所示，在本实施例的实施过程中，形成至少覆盖中间掺杂区和部分初始底部掺杂区的堆叠结构，包括以下步骤：
步骤S151b：形成覆盖中间掺杂区表面以及底部掺杂区表面的栅极介质层，在垂直于衬底的截面上，栅极介质层的厚度与第一介电层的厚度相同或不同。
本实施例中，参照图23，形成栅极介质层201的实现方式和上述实施例中步骤S151a中栅极介质层201的实现方式相同，在此，不再赘述。
步骤S152b：形成覆盖栅极介质层的第一初始栅导电层，对第一初始栅导电层进行第一蚀刻，控制第一蚀刻的蚀刻条件，形成与栅极介质层共形的第一栅导电层。
本实施例中，参照图23，形成第一栅导电层212的实现方式和上述实施例中步骤S152a中第一栅导电层212的实现方式相同，在此，不再赘述。
步骤S153b：去除介电结构，暴露出顶部掺杂区上的第一介电层。
如图23所示，参照图16，可以通过干法蚀刻或湿法蚀刻去除全部的介电结构225，暴露出第一介电层230。第一介电层230和第一栅导电层212在顶部掺杂区111的上方围成凹槽205。
步骤S154b：形成第二初始栅导电层，第二初始栅导电覆盖第一栅导电层以及暴露的第一介电层，对第二初始栅导电层进行第二蚀刻，形成第二栅导电层。
如图24所示，参照图23，通过原子层沉积工艺或化学气相沉积工艺沉积金属导电材料，形成第二初始栅导电层103，第二初始栅导电层103覆盖衬底100的顶面、第一栅导电层212并填充凹槽205。其中，金属导电材料和上述实施例中第二初始栅导电层103的材料相同。
然后，如图4所示，参照图24，对第二初始栅导电层103进行第二蚀刻，控制第二蚀刻的蚀刻条件，以使在竖直方向上蚀刻第二初始栅导电层103的速度大于在水平方向上蚀刻第二初始栅导电层103的速度。去除位于衬底100顶面的全部第二初始栅导电层103并暴露出和衬底100连接的第一栅导电层212的部分侧壁，被保留的第二初始栅导电层103形成第二栅导电层213。
如图4所示，本实施例中，第一介电层230和栅极介质层201共同形成栅介质层211。第一栅导电层212通过栅极介质层201与底部掺杂区112和中间掺杂区113接触，部分第二栅导电层213位于第一栅导电层212上，另一部分第二栅导电层213通过第一介电层230和顶部掺杂区111接触。
本实施例形成的堆叠结构仅包括栅极堆叠结构，第二栅导电层不仅覆盖部分第二栅导电层，并填充第一栅导电层和第一介电层围成的凹槽，增加了栅极堆叠结构中第二栅导电层的占比，进而提高了半导体结构的电性能。
根据一示例性实施例，本实施例是对上述实施例的进一步说明。和上述实施例相比，本实施例在实施例步骤S150之后，增加了以下步骤：
步骤S160：对堆叠结构两侧的衬底进行掺杂工艺，在衬底中形成第一轻掺杂区和第二轻掺杂区。
如图18所示，参照图1，或如图5所示，参照图4，在本实施例中，以堆叠结构200的侧壁为掩膜，向衬底100中注入掺杂离子，在堆叠结构200两侧的衬底100中形成第一轻掺杂区510和第二轻掺杂区520。其中，第一轻掺杂区510和底部掺杂区112相接，第二轻掺杂区520和底部掺杂区112相接。
步骤S170：形成隔离结构，隔离结构至少覆盖堆叠结构。
如图2所示，参照图18，或如图5所示，参照图4，在本实施例中，形成隔离结构300，可以采用以下方法：沉积隔离材料，隔离材料覆盖堆叠结构200的外表面并覆盖衬底100的顶面，然后蚀刻去除部分隔离材料，暴露出衬底100的顶面，被保留的隔离材料形成隔离结构300，隔离结构300覆盖堆叠结构200。
步骤S180：以隔离结构为掩膜，对衬底进行源漏掺杂工艺，在衬底中形成源区和漏区。
参照图2或参照图5所示，以隔离结构300为掩膜，通过离子注入工艺或扩散工艺在隔离结构300外侧的衬底100中分别注入掺杂离子，在堆叠结构200的两侧分布形成源区410和漏区420。
如图2或如图5所示，第一轻掺杂区510和源区410存在部分重叠区域，部分第一轻掺杂区510位于源区410和底部掺杂区112之间，以阻挡源区410的第一掺杂离子向底部掺杂区112扩散。同样的，第二轻掺杂区520阻挡漏区420的第一掺杂离子向底部掺杂区112扩散。通过减小源区410、漏区420和栅极堆叠结构210的交叠区域，能够减小或避免形成的半导体结构出现栅极诱导漏极漏电流导致漏电的问题。
步骤S190：形成垂直于衬底的顶面的第二插塞，第二插塞与源区接触连接，形成垂直于衬底的顶面的第三插塞，第三插塞与漏区接触连接。
本实施例中，以堆叠结构200包括栅极堆叠结构210以及介电堆叠结构220的方案进行说明。
如图20所示，参照图2，首先，沉积介质材料覆盖衬底100以及堆叠结构200，介质材料的顶面高于堆叠结构200的顶面，然后回刻介质材料，暴露出隔离结构300的顶面，形成介质层600。
如图21所示，参照图20，去除部分介质层600、部分介电堆叠结构220以及部分衬底100，分别形成第二沟槽602和第三沟槽603，第二沟槽602延伸到衬底100中并暴露出部分源区410，第三沟槽603延伸到衬底100中并暴露出部分漏区420。
然后，参照图21，沉积阻挡材料(图中未示出)，阻挡材料覆盖第二沟槽602的内壁以及第三沟槽603的内壁。阻挡材料的材料可以包括钛或钛化物，或者阻挡材料的材料可以包括钽或钽化物。
接着，如图22所示，参照图21，分别于第二沟槽602和第三沟槽603中填充金属材料，在垂直于衬底100的截面上，第二沟槽602中的金属材料形成垂直于衬底100的顶面的第二插塞620，第二插塞620与源区410接触连接。第三沟槽603中的金属材料形成垂直于衬底100的顶面的第三插塞630，第三插塞630与漏区420接触连接。其中，金属材料可以包括钨或钨化物。
在本实施例中，部分金属材料形成金属层650，金属层650覆盖介质层600的顶面并覆盖堆叠结构200，第二插塞620和第三插塞630均和金属层650接触连接，第二插塞620和第三插塞630可以通过金属层650将源区410和漏区420和其它半导体结构或器件连接。
在一些实施例中，如图3所示，参照图22，于金属层650中形成多个绝缘结构651，多个绝缘结构651将金属层650划分成多个独立设置的部分，第二插塞620和第三插塞630分别与金属层650的不同部分连接，第二插塞620和第三插塞630可以通过金属层650的不同部分与相同或不同的器件连接。
根据一示例性实施例，本实施例是对上述实施例的一种可能的实施方式的进一步说明。其中，隔离结构300可以包括单层结构或多层结构，在本实施例中，隔离结构300为多层结构，隔离结构300包括第一隔离层310、中间隔离层320以及外部隔离层330。
本实施例中，以堆叠结构200包括栅极堆叠结构210以及介电堆叠结构220的方案进行说明。在本实施例中，形成隔离结构300，包括以下步骤：
首先，如图18所示，参照图17，形成第一隔离层310，第一隔离层310至少覆盖堆叠结构200的部分外表面以及与堆叠结构200邻接的衬底100的部分顶面。然后，如图19所示，参照图18，形成中间隔离层320，中间隔离层320至少覆盖第一隔离层310以及与第一隔离层310邻接的部分衬底100的顶面。接着，如图2所示，参照图19，形成外部隔离层330，外部隔离层330覆盖中间隔离层320以及堆叠结构200未被覆盖的外表 面。
根据一示例性实施例，本实施例是对上述实施例的一种可能的实施方式的进一步说明。和上述实施例相比，本实施例增加了以下步骤：形成第一插塞，在垂直于衬底的方向上，第一插塞贯穿介电结构和第一介电层，与顶部掺杂区接触连接。
如图2所示，本实施例的半导体结构的堆叠结构200包括栅极堆叠结构210以及介电堆叠结构220。在本实施例中，如图21所示，在形成第二沟槽602、第三沟槽603的同时，去除部分介电堆叠结构220形成第一沟槽601，第一沟槽601延伸到衬底100中并暴露出部分顶部掺杂区111。如图22所示，于第一沟槽601中填充金属材料形成第一插塞610，第一插塞610用于将栅极堆叠结构210连接至金属层650，并通过金属层650将栅极堆叠结构210与其它半导体结构或器件连接。在一些实施例中，参照图3，第一插塞610、第二插塞620和第三插塞630分别与金属层650的不同部分连接，第一插塞610、第二插塞620和第三插塞630可以通过金属层650的不同部分与相同或不同的器件连接。
根据一示例性实施例，本实施例的半导体结构中堆叠结构200仅包括栅极堆叠结构210，和上述实施例相比，本实施例增加了以下步骤：形成第四插塞，在垂直于衬底的方向上，第四插塞与顶部掺杂区接触连接。
如图25所示，参照图21，在形成第二沟槽602和第三沟槽603的过程中，同时形成第四沟槽(图中未示出)，第四沟槽暴露出部分顶部掺杂区111，然后沉积阻挡材料，阻挡材料覆盖第四沟槽的槽壁。接着，于第四沟槽中填充金属材料，第四沟槽中的金属材料形成第四插塞640，第四插塞640和金属层650接触，第四插塞640可通过金属层650将栅极堆叠结构210和其它半导体结构或器件连接。在一些实施例中，参照图6，第四插塞640、第二插塞620和第三插塞630分别与金属层650的不同部分连接，第四插塞640、第二插塞620和第三插塞630可以通过金属层650的不同部分与相同或不同的器件连接。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的半导体结构及半导体结构的制作方法中，半导体结构的堆叠结构覆盖掺杂区，掺杂区包括中间掺杂区，在平行于衬底的方向上，中间掺杂区的宽度在沿着远离衬底的方向逐渐减小，以将掺杂区形成相对于衬底向外凸起的鳍形结构，增加了堆叠结构和掺杂区的接触面积。

Claims (20)

  1. 一种半导体结构，所述半导体结构包括：
    衬底和位于所述衬底上的堆叠结构；
    位于所述堆叠结构与所述衬底之间的掺杂区，在垂直于所述衬底的截面上，所述掺杂区包括顶部掺杂区、底部掺杂区以及连接所述顶部掺杂区和所述底部掺杂区的中间掺杂区，在平行于所述衬底的方向上，所述顶部掺杂区具有第一宽度，所述底部掺杂区具有第二宽度，所述中间掺杂区具有逐渐变化的第三宽度，其中，所述第一宽度大于所述第二宽度，所述第三宽度在沿着远离所述衬底的方向上逐渐减小。
  2. 根据权利要求1所述的半导体结构，其中，所述堆叠结构包括栅极堆叠结构，所述栅极堆叠结构包括与所述掺杂区接触的栅介质层和位于所述栅介质层上的第一栅导电层和第二栅导电层，在垂直于所述衬底的截面上，所述第一栅导电层的厚度小于所述第二栅导电层的厚度。
  3. 根据权利要求2所述的半导体结构，其中，在垂直于所述衬底的截面上，所述第二栅导电层具有第一厚度；
    沿平行于所述衬底的方向，由所述底部掺杂区至所述顶部掺杂区，所述第一厚度逐渐增大。
  4. 根据权利要求2所述的半导体结构，所述半导体结构还包括第一介电层，所述第一介电层位于所述堆叠结构和所述顶部掺杂区之间，所述栅介质层与所述第一介电层相连，所述栅介质层与所述第一栅导电层接触，所述第一介电层与所述第二栅导电层接触；
    其中，在垂直于所述衬底方向的截面上，所述栅介质层和所述第一介电层的厚度相同或不同。
  5. 根据权利要求4所述的半导体结构，其中，所述堆叠结构还包括位于所述顶部掺杂区上的介电堆叠结构，所述栅极堆叠结构位于所述中间掺杂区和所述底部掺杂区上，其中，所述介电堆叠结构的顶表面高于所述栅极堆叠结构的顶表面。
  6. 根据权利要求5所述的半导体结构，其中，所述介电堆叠结构包括第二介电层和第三介电层，在垂直于所述衬底的截面上，所述第二介电层的顶表面高于所述第一栅导电层的顶表面，所述第二介电层的顶表面低于所述第二栅导电层的顶表面，所述第三介电层的顶表面高于所述第二栅导电层的顶表面。
  7. 根据权利要求5所述的半导体结构，所述半导体结构还包括第一插塞，所述第一插塞贯穿所述介电堆叠结构，并与所述顶部掺杂区接触连接。
  8. 根据权利要求2所述的半导体结构，其中，所述第一栅导电层包括功函数调节材料，所述第二栅导电层包括金属导电材料。
  9. 根据权利要求1所述的半导体结构，其中，所述底部掺杂区和所述中间掺杂区的掺杂类型相同，所述顶部掺杂区和所述中间掺杂区的掺杂类型相同或不同。
  10. 根据权利要求1所述的半导体结构，所述半导体结构还包括隔离结构，所述隔离结构覆盖所述堆叠结构。
  11. 根据权利要求10所述的半导体结构，所述半导体结构还包括设置于所述衬底中的源区和漏区，所述源区和所述漏区位于所述堆叠结构的两侧。
  12. 根据权利要求11所述的半导体结构，所述半导体结构还包括：
    第二插塞，所述第二插塞垂直于所述衬底设置，所述第二插塞与所述源区接触连接；
    第三插塞，所述第三插塞垂直于所述衬底设置，所述第三插塞与所述漏区接触连接。
  13. 一种半导体结构的制作方法，所述半导体结构的制作方法，包括：
    提供衬底；
    在所述衬底上形成介电结构，所述介电结构覆盖所述衬底的部分表面；
    在所述介电结构的外侧形成覆盖部分所述衬底表面的辅助层，所述辅助层在远离所述衬底的方向上具有逐渐减小的水平宽度；
    基于所述辅助层和所述介电结构对所述衬底进行图形化处理，将所述辅助层的图形转移到所述衬底中，以在所述衬底中形成在远离所述衬底的方向上具有逐渐减小的水平宽度的中间掺杂区，所述介电结构的下方的所述衬底未被蚀刻，所述介电结构下方的所述衬底形成具有第一宽度的顶部掺杂区，未被所述辅助层和所述介电结构覆盖的所述衬底被部分蚀刻去除，形成初始底部掺杂区，所述中间掺杂区连接所述初始底部掺杂区和所述顶部掺杂区；
    形成至少覆盖所述中间掺杂区和部分所述初始底部掺杂区的堆叠结构，被所述堆叠结构覆盖的部分所述初始底部掺杂区形成底部掺杂区，所述底部掺杂区具有第二宽度，所述第一宽度大于所述第二宽度。
  14. 根据权利要求13所述的半导体结构的制作方法，其中，所述介电结构和所述衬底之间还形成有第一介电层，形成至少覆盖所述中间掺杂区和部分所述初始底部掺杂区的堆叠结构，包括：
    形成覆盖所述中间掺杂区表面以及所述底部掺杂区表面的栅极介质层，在垂直于所述衬底的截面上，所述栅极介质层的厚度与所述第一介电层的厚度相同或不同；
    形成覆盖所述栅极介质层的第一栅导电层和第二栅导电层，在垂直于所述衬底的截面上，所述第一栅导电层的厚度小于所述第二栅导电层的厚度。
  15. 根据权利要求14所述的半导体结构的制作方法，其中，形成覆盖所述栅极介质层的第一栅导电层和第二栅导电层，包括:
    形成覆盖所述栅极介质层的第一初始栅导电层，对所述第一初始栅导电层进行第一蚀刻，控制所述第一蚀刻的蚀刻条件，形成与所述栅极介质层共形的所述第一栅导电层；
    形成覆盖所述第一栅导电层的第二初始栅导电层，对所述第二初始栅导电层进行第二蚀刻，控制所述第二蚀刻的蚀刻条件，形成在垂直于所述衬底的截面上具有第一厚度的第二栅导电层，沿平行于所述衬底的方向，由所述底部掺杂区至所述顶部掺杂区，所述第一厚度逐渐增大。
  16. 根据权利要求15所述的半导体结构的制作方法，其中，在形成所述第一栅导电层之后，在形成所述第二栅导电层之前，还包括：
    去除所述介电结构，暴露出所述顶部掺杂区上的所述第一介电层；
    在所述第一栅导电层上和暴露的所述第一介电层上形成所述第二初始栅导电层。
  17. 根据权利要求13所述的半导体结构的制作方法，其中，提供衬底，包括：
    提供初始衬底，在所述初始衬底中形成第一掺杂区；
    在所述第一掺杂区上形成第二掺杂区，其中，所述第一掺杂区和所述第二掺杂区的掺杂离子类型相同或不同。
  18. 根据权利要求17所述的半导体结构的制作方法，其中，基于所述辅助层和所述介电结构对所述衬底进行图形化处理，将所述辅助层的图形转移到所述衬底中，包括：
    控制所述辅助层和所述衬底的蚀刻比，同步蚀刻所述辅助层和所述衬底，去除未被所述辅助层和所述介电结构覆盖的所述第二掺杂区和所述第二掺杂区下方的部分所述第一掺杂区，同时去除所述辅助层下方的至少部分第一掺杂区和部分第二掺杂区。
  19. 根据权利要求14所述的半导体结构的制作方法，所述半导体结构的制作方法，还包括：
    形成第一插塞，在垂直于所述衬底的方向上，所述第一插塞贯穿所述介电结构和所述第一介电层，与所述顶部掺杂区接触连接。
  20. 根据权利要求13所述的半导体结构的制作方法，所述半导体结构的制作方法，还包括：
    形成隔离结构，所述隔离结构至少覆盖所述堆叠结构；
    以所述隔离结构为掩膜，对所述衬底进行源漏掺杂工艺，在所述衬底中形成源区和漏区；
    形成垂直于所述衬底的顶面的第二插塞，所述第二插塞与所述源区接触连接；
    形成垂直于所述衬底的顶面的第三插塞，所述第三插塞与所述漏区接触连接。
PCT/CN2022/103650 2022-05-06 2022-07-04 半导体结构及半导体结构的制作方法 Ceased WO2023213001A1 (zh)

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