WO2023211511A1 - Circuits de réseau crossbar avec des cellules rram 2t1r pour des opérations à basse tension - Google Patents

Circuits de réseau crossbar avec des cellules rram 2t1r pour des opérations à basse tension Download PDF

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Publication number
WO2023211511A1
WO2023211511A1 PCT/US2022/071987 US2022071987W WO2023211511A1 WO 2023211511 A1 WO2023211511 A1 WO 2023211511A1 US 2022071987 W US2022071987 W US 2022071987W WO 2023211511 A1 WO2023211511 A1 WO 2023211511A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
nmos
pmos
rram
implementations
Prior art date
Application number
PCT/US2022/071987
Other languages
English (en)
Inventor
Wenbo YIN
Ning GE
Original Assignee
Tetramem Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tetramem Inc. filed Critical Tetramem Inc.
Priority to PCT/US2022/071987 priority Critical patent/WO2023211511A1/fr
Publication of WO2023211511A1 publication Critical patent/WO2023211511A1/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0028—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0097—Erasing, e.g. resetting, circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/74—Array wherein each memory cell has more than one access device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/82—Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials

Definitions

  • the present disclosure relates generally to crossbar array circuits and more specifically to crossbar array circuits with a 2T1R RRAM cell that includes at least one NMOS transistor and one PMOS transistor for low voltage operations.
  • a crossbar array circuit may include horizontal metal wire rows and vertical metal wire columns (or other electrodes) intersecting with each other in a two-dimension (2D) plane, with crossbar devices formed at the intersecting points.
  • the crossbar array may be used in non-volatile solid-state memory, signal processing, control systems, high-speed image processing, neural network, machine learning, and other applications.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • MOS transistor also known as the metal-oxide-silicon transistor, MOS transistor, or simply MOS
  • FET Field-Effect Transistor
  • a MOSFET is an n-channel MOSFET (also referred to as an NMOS FET)
  • the source and drain of the MOSFET are n+ regions and the body of the MOSFET is a p region.
  • the RRAM device is connected between a first source terminal of the first NMOS transistor and the bit line, and between a second source terminal of the second PMOS transistor and the bit line; a first drain terminal of the first NMOS transistor is connected to the word line; a second drain terminal of the second PMOS transistor is connected to the word line; and a first gate terminal of the first NMOS transistor is connected to a first selector voltage source.
  • the apparatus in some implementations, further includes: an inverter, via which the second gate terminal of the second transistor is connected to the first gate terminal.
  • the inverter in some implementations, comprises an NMOS inverter, a PMOS inverter, a CMOS inverter, or a combination thereof.
  • the RRAM device is, in some implementations, connected between a first source terminal of the first NMOS transistor and the bit line, and between a second source terminal of the second PMOS transistor and the bit line.
  • An apparatus that comprises: a word line; a bit line; a first transistor; a second transistor; and an RRAM device, wherein the first transistor and the second transistor are connected in series with the RRAM device.
  • the RRAM device is connected between a first drain terminal of the first transistor and the word line, and between a second drain terminal of the second transistor and the word line.
  • a first source terminal of the first transistor is connected to the bit line; a second source terminal of the second transistor is connected to the bit line; and a first gate terminal of the first transistor is connected to a first selector voltage source.
  • the apparatus comprises an inverter, via which the second gate terminal of the second PMOS transistor is connected to the first gate terminal via the inverter.
  • the apparatus comprises: two or more NMOS transistors including the first NMOS transistor.
  • FIG. 1 A is a block diagram illustrating an example crossbar array circuit.
  • FIG. 6 is a summary chart illustrating the voltage and power consumption of two different designs.
  • the word line 201 is set to a 0V voltage
  • the bit line 202 is set to voltage VDD during the SET operation (with selector voltage source set to voltage VDD).
  • Vds VDD-Vx (1)
  • Vx cannot become greater than Vtn.
  • Vx is thus kept relatively low, due to limit imposed a transistor's Vtn.
  • the low RESET current for the RRAM device 205 is an issue and therefore a higher VDD should be applied to obtain the required RESET current.
  • FIG. 3B illustrates an example RESET operation of the 2T1R RRAM cell 303.
  • a SEL line does not dissipate DC current, it does not need to be wide. Because a 2T1R cell needs both a SEL line and a SEL b line, the 2T1R cell's Resistor-Capacitor (RC) delay will be increased. The increased RC delay, however, does not have a significant impact in small crossbar arrays, because the read speed is not dictated by RC delays on a SEL (or SEL b) line for small arrays.
  • RC Resistor-Capacitor
  • FIG. 8 is a block diagram 8000 illustrating an example 2T1R RRAM cell 803 in accordance with some implementations of the present disclosure.
  • the NMOS transistor 907 and the PMOS transistor 909 are connected in series with the RRAM device 905.
  • the RRAM device 905 is connected between a first drain terminal 9075 of the NMOS transistor 907 and the word line 901, and between a second drain terminal 9095 of the PMOS transistor 909 and the word line 901.
  • a first source terminal 9073 of the NMOS transistor 907 is connected to the bit line 902.
  • a second source terminal 9093 of the PMOS transistor 909 is connected to the bit line 902.
  • a first gate terminal 9071 of the NMOS transistor 907 is connected to a first selector voltage source.
  • a second gate terminal 9091 of the PMOS transistor 909 is connected to the first gate terminal 9071 via the inverter 911.
  • first means “first,” “second,” etc.
  • these elements should not be limited by these terms. These terms are only used to distinguish one element from another.
  • a first column could be termed a second column, and, similarly, a second column could be termed the first column, without changing the meaning of the description, so long as all occurrences of the "first column” are renamed consistently and all occurrences of the "second column” are renamed consistently.
  • the first column and the second are columns both columns, but they are not the same column.

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  • Semiconductor Memories (AREA)

Abstract

Sont divulguées des technologies se rapportant aux circuits de réseau crossbar avec une cellule RRAM 2T1R qui comprend au moins un transistor NMOS et un transistor PMOS pour des opérations à basse tension. Un appareil donné à titre d'exemple comprend une ligne de mots ; une ligne de bits ; un premier transistor NMOS ; un second transistor PMOS ; et un dispositif RRAM. Le premier transistor NMOS et le second transistor PMOS sont en parallèle sous la forme d'une paire, la paire se connectant en série avec le dispositif RRAM. L'appareil peut en outre comprendre un onduleur, par l'intermédiaire duquel la seconde borne de grille du second transistor PMOS est connectée à la première borne de grille.
PCT/US2022/071987 2022-04-28 2022-04-28 Circuits de réseau crossbar avec des cellules rram 2t1r pour des opérations à basse tension WO2023211511A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2022/071987 WO2023211511A1 (fr) 2022-04-28 2022-04-28 Circuits de réseau crossbar avec des cellules rram 2t1r pour des opérations à basse tension

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2022/071987 WO2023211511A1 (fr) 2022-04-28 2022-04-28 Circuits de réseau crossbar avec des cellules rram 2t1r pour des opérations à basse tension

Publications (1)

Publication Number Publication Date
WO2023211511A1 true WO2023211511A1 (fr) 2023-11-02

Family

ID=88519416

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2022/071987 WO2023211511A1 (fr) 2022-04-28 2022-04-28 Circuits de réseau crossbar avec des cellules rram 2t1r pour des opérations à basse tension

Country Status (1)

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WO (1) WO2023211511A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190080754A1 (en) * 2017-09-11 2019-03-14 Silicon Storage Technology, Inc. Methods For Writing To An Array Of Resistive Random Access Memory Cells
US20190325933A1 (en) * 2018-04-19 2019-10-24 Samsung Electronics Co., Ltd. Resistive memory device having memory cell array and system including the same
US20210159274A1 (en) * 2019-11-23 2021-05-27 Tetramem Inc. Crossbar array circuit with parallel grounding lines

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190080754A1 (en) * 2017-09-11 2019-03-14 Silicon Storage Technology, Inc. Methods For Writing To An Array Of Resistive Random Access Memory Cells
US20190325933A1 (en) * 2018-04-19 2019-10-24 Samsung Electronics Co., Ltd. Resistive memory device having memory cell array and system including the same
US20210159274A1 (en) * 2019-11-23 2021-05-27 Tetramem Inc. Crossbar array circuit with parallel grounding lines

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