WO2023210676A1 - 半導体発光素子、及び半導体発光素子の製造方法 - Google Patents

半導体発光素子、及び半導体発光素子の製造方法 Download PDF

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Publication number
WO2023210676A1
WO2023210676A1 PCT/JP2023/016403 JP2023016403W WO2023210676A1 WO 2023210676 A1 WO2023210676 A1 WO 2023210676A1 JP 2023016403 W JP2023016403 W JP 2023016403W WO 2023210676 A1 WO2023210676 A1 WO 2023210676A1
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Prior art keywords
ridge
layer
light emitting
semiconductor light
emitting device
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PCT/JP2023/016403
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English (en)
French (fr)
Japanese (ja)
Inventor
篤志 山田
康光 久納
洋希 永井
東吾 中谷
隆司 油本
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Nuvoton Technology Corp Japan
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Nuvoton Technology Corp Japan
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Priority to JP2024517366A priority Critical patent/JPWO2023210676A1/ja
Priority to CN202380035842.8A priority patent/CN119096437A/zh
Publication of WO2023210676A1 publication Critical patent/WO2023210676A1/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
    • H01S5/343—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser

Definitions

  • the present disclosure relates to a semiconductor light emitting device and a method for manufacturing the semiconductor light emitting device.
  • a semiconductor light emitting device such as a semiconductor laser device is used as such a laser light source.
  • Patent Document 1 As a technique for increasing the efficiency of semiconductor light emitting devices, a technique is known in which a ridge is formed and a current is confined in the ridge (for example, Patent Document 1).
  • the present disclosure aims to solve such problems, and to provide a semiconductor light emitting device and the like that can suppress the current flowing to the side surface of the ridge.
  • a semiconductor light emitting device that emits light, which includes a substrate, an N-type cladding layer disposed above the substrate, and a semiconductor light emitting device that emits light.
  • an active layer disposed above the P-type cladding layer, a P-type cladding layer disposed above the active layer, a contact layer disposed above the P-type cladding layer, and a contact layer disposed above the P-type cladding layer.
  • a ridge extending in the light propagation direction is formed in a region including the P-type cladding layer and the contact layer; the ridge extends in the direction of propagation of the light; and an upper ridge disposed on a top surface of the lower ridge and including the contact layer, and the top surface of the lower ridge is between a side surface of the lower ridge and a bottom surface of the upper ridge.
  • the upper ridge has a flat portion extending in the light propagation direction, and the width of the bottom surface of the upper ridge is smaller than the width of the top surface of the lower ridge and the width of the lower ridge at a central position in the stacking direction.
  • the insulating film continuously covers from a side surface of the lower ridge to a part of the top surface of the upper ridge.
  • another aspect of the semiconductor light emitting device is a semiconductor light emitting device that emits light, which includes a substrate, an N-type cladding layer disposed above the substrate, an active layer disposed above the N-type cladding layer; a P-type cladding layer disposed above the active layer; and a contact layer disposed above the P-type cladding layer; A ridge extending in the light propagation direction is formed in a region including the cladding layer and the contact layer, and the ridge is arranged on a lower ridge including the P-type cladding layer and on a top surface of the lower ridge.
  • the P-type cladding layer is made of Al x Ga 1-x As (0 ⁇ X ⁇ 1), and a lower cladding layer and an upper ridge above the lower cladding layer.
  • a first cladding layer disposed above the first cladding layer; a first etch stop layer disposed above the first cladding layer; a second cladding layer disposed above the first etch stop layer; a second etching stop layer disposed above the layer,
  • the lower cladding layer has an Al composition ratio X0
  • the first cladding layer has an Al composition ratio X1
  • the second cladding layer has an Al composition ratio X2.
  • one embodiment of a method for manufacturing a semiconductor light emitting device is a method for manufacturing a semiconductor light emitting device that emits light, which includes a step of forming an N-type cladding layer above a substrate. , forming an active layer above the N-type cladding layer; forming a P-type cladding layer above the active layer; forming a contact layer above the P-type cladding layer; forming a ridge in a region including the P-type cladding layer and the contact layer; and forming an insulating film on the ridge, the ridge including the lower ridge including the P-type cladding layer and the lower ridge.
  • the step of forming the ridge includes forming the upper ridge, and forming the lower ridge after the step of forming the upper ridge.
  • the top surface of the lower ridge has a flat portion located between the side surface of the lower ridge and the bottom surface of the upper ridge and extends in the propagation direction of the light;
  • the width of the bottom surface of the ridge is smaller than the width of the top surface of the lower ridge and the width at the center position of the lower ridge in the stacking direction, and the insulating film extends from the side surface of the lower ridge to one of the top surfaces of the upper ridge. Continuously cover the entire area.
  • FIG. 1 is a schematic top view showing the overall configuration of a semiconductor light emitting device according to an embodiment.
  • FIG. 2 is a first schematic cross-sectional view showing the overall configuration of the semiconductor light emitting device according to the embodiment.
  • FIG. 3 is a second schematic cross-sectional view showing the overall configuration of the semiconductor light emitting device according to the embodiment.
  • FIG. 4 is a third schematic cross-sectional view showing the overall configuration of the semiconductor light emitting device according to the embodiment.
  • FIG. 5 is a schematic cross-sectional view showing the structure of the active layer according to the embodiment.
  • FIG. 6 is a schematic cross-sectional view showing the structure of the second etching stop layer according to the embodiment.
  • FIG. 7 is an enlarged view of the ridge shown in FIG. FIG.
  • FIG. 8 is an enlarged view of the wing section shown in FIG. 2.
  • FIG. 9 is a schematic cross-sectional view showing the first step of the method for manufacturing a semiconductor light emitting device according to the embodiment.
  • FIG. 10 is a schematic cross-sectional view showing the second step of the method for manufacturing a semiconductor light emitting device according to the embodiment.
  • FIG. 11 is a schematic first cross-sectional view showing the third step of the method for manufacturing a semiconductor light emitting device according to the embodiment.
  • FIG. 12 is a second schematic cross-sectional view showing the third step of the method for manufacturing a semiconductor light emitting device according to the embodiment.
  • FIG. 13 is a schematic first cross-sectional view showing the fourth step of the method for manufacturing a semiconductor light emitting device according to the embodiment.
  • FIG. 14 is a second schematic cross-sectional view showing the fourth step of the method for manufacturing a semiconductor light emitting device according to the embodiment.
  • FIG. 15 is a first schematic cross-sectional view showing the fifth step of the method for manufacturing a semiconductor light emitting device according to the embodiment.
  • FIG. 16 is a second schematic cross-sectional view showing the fifth step of the method for manufacturing a semiconductor light emitting device according to the embodiment.
  • FIG. 17 is a schematic first cross-sectional view showing the sixth step of the method for manufacturing a semiconductor light emitting device according to the embodiment.
  • FIG. 18 is a second schematic cross-sectional view showing the sixth step of the method for manufacturing a semiconductor light emitting device according to the embodiment.
  • FIG. 19 is a schematic cross-sectional view showing the seventh step of the method for manufacturing a semiconductor light emitting device according to the embodiment.
  • FIG. 20 is a first schematic cross-sectional view showing the eighth step of the method for manufacturing a semiconductor light emitting device according to the embodiment.
  • FIG. 21 is a second schematic cross-sectional view showing the eighth step of the method for manufacturing a semiconductor light emitting device according to the embodiment.
  • FIG. 22 is a schematic cross-sectional view showing the ninth step of the method for manufacturing a semiconductor light emitting device according to the embodiment.
  • FIG. 23 is a first schematic cross-sectional view showing the tenth step of the method for manufacturing a semiconductor light emitting device according to the embodiment.
  • FIG. 24 is a second schematic cross-sectional view showing the tenth step of the method for manufacturing a semiconductor light emitting device according to the embodiment.
  • FIG. 25 is a graph showing the relationship between the output power and the injection current of the semiconductor light emitting device according to the embodiment.
  • FIG. 26 is a graph showing the relationship between the remaining thickness of the semiconductor light emitting device and the horizontal spread angle of emitted light according to the embodiment.
  • FIG. 27 is a graph showing the relationship between the horizontal spread angle of emitted light and the effective refractive index difference of the semiconductor light emitting device according to the embodiment.
  • FIG. 28 is a schematic top view showing the overall configuration of a semiconductor light emitting device according to Modification 1 of the embodiment.
  • FIG. 29 is a first schematic cross-sectional view showing the overall configuration of a semiconductor light emitting device according to Modification 1 of the embodiment.
  • FIG. 30 is a second schematic cross-sectional view showing the overall configuration of a semiconductor light emitting device according to Modification 1 of the embodiment.
  • FIG. 31 is a third schematic cross-sectional view showing the overall configuration of a semiconductor light emitting device according to Modification 1 of the embodiment.
  • FIG. 32 is a fourth schematic cross-sectional view showing the overall configuration of a semiconductor light emitting device according to Modification 1 of the embodiment.
  • FIG. 33 is a schematic top view showing the overall configuration of a semiconductor light emitting device according to Modification 2 of the embodiment.
  • FIG. 34 is a first schematic cross-sectional view showing the overall configuration of a semiconductor light emitting device according to Modification 2 of the embodiment.
  • FIG. 35 is a second schematic cross-sectional view showing the overall configuration of a semiconductor light emitting device according to Modification 2 of the embodiment.
  • FIG. 36 is a third schematic cross-sectional view showing the overall configuration of a semiconductor light emitting device according to Modification 2 of the embodiment.
  • each figure is a schematic diagram and is not necessarily strictly illustrated. Therefore, the scale etc. in each figure are not necessarily the same.
  • symbol is attached to the substantially the same structure, and the overlapping description is omitted or simplified.
  • the terms “upper” and “lower” do not refer to the upper direction (vertically upward) or the lower direction (vertically downward) in absolute spatial recognition, but are based on the stacking order in the stacked structure. Used as a term defined by the relative positional relationship. Additionally, the terms “above” and “below” are used not only when two components are spaced apart and there is another component between them; This also applies when they are placed in contact with each other.
  • FIG. 1 is a schematic top view showing the overall configuration of a semiconductor light emitting device 1 according to this embodiment.
  • 2 to 4 are schematic cross-sectional views showing the overall structure of the semiconductor light emitting device 1 according to the present embodiment.
  • 2 and 3 show cross sections of the semiconductor light emitting device 1 taken along the line II-II and the line III-III in FIG. 1, respectively.
  • FIG. 4 shows only a part of the cross section of the semiconductor light emitting device 1 taken along the line IV-IV in FIG. 1, including the end surface 1F.
  • each figure shows an X-axis, a Y-axis, and a Z-axis that are orthogonal to each other.
  • the X, Y, and Z axes are a right-handed Cartesian coordinate system.
  • the stacking direction of the semiconductor light emitting device 1 (that is, the thickness direction of each layer included in the semiconductor light emitting device 1) is parallel to the Z-axis direction, and the main propagation direction of light (laser light) is parallel to the Y-axis direction. be.
  • the semiconductor light emitting element 1 is an element that emits light when supplied with electric current.
  • the semiconductor light emitting device 1 is a semiconductor laser device that emits laser light with a wavelength in the near-infrared region (about 900 nm or more and 980 nm or less). More specifically, the semiconductor light emitting device 1 emits laser light with a wavelength of about 976 nm.
  • the semiconductor light emitting device 1 has two end faces 1F and 1R forming a resonator.
  • the end surface 1F is a front end surface that emits laser light
  • the end surface 1R is a rear end surface that has a higher reflectance than the end surface 1F.
  • the semiconductor light emitting device 1 has a waveguide formed between the end surface 1F and the end surface 1R.
  • the resonator length of the semiconductor light emitting device 1, that is, the distance between the end surfaces 1F and 1R in the laser beam propagation direction (the Y-axis direction in each figure, that is, the resonance direction) is not particularly limited, but in this embodiment , 2 mm or more. Further, the resonator length of the semiconductor light emitting device 1 may be 5 mm or more.
  • the semiconductor light emitting device 1 includes reflective films 2F and 2R arranged at the ends in the propagation direction of laser light.
  • the reflective films 2F and 2R are films for adjusting the reflectance of the end faces 1F and 1R, respectively.
  • each of the reflective films 2F and 2R is a dielectric multilayer film.
  • the reflective film 2F has a lower reflectance than the reflective film 2R.
  • the semiconductor light emitting device 1 includes a substrate 10, an N-type cladding layer 20, an active layer 30, a P-type cladding layer 40, a contact layer 50, and an insulating film 60.
  • the semiconductor light emitting device 1 includes an N-type buffer layer (not shown), an N-type buffer boundary layer (not shown), a first P-side electrode 71, a pad electrode 73, and a second It further includes a P-side electrode 72 and an N-side electrode 80.
  • the substrate 10 is a plate-like member that serves as a base for the semiconductor light emitting device 1.
  • substrate 10 is an N-type GaAs substrate.
  • the N-type buffer layer is an N-type semiconductor layer placed above the substrate 10.
  • the N-type buffer layer is an N-type GaAs layer with a thickness of 0.5 ⁇ m.
  • the N-type buffer boundary layer is an N-type semiconductor layer disposed between the N-type buffer layer and the N-type cladding layer 20.
  • the N-type buffer boundary layer is an N-type Al X22 Ga 1-X22 As layer (0.15 ⁇ X22 ⁇ 0.25) with a thickness of 0.05 ⁇ m.
  • the Al composition ratio X22 of the N-type buffer boundary layer increases as it approaches the N-type cladding layer 20.
  • the Al composition ratio X22 of the N-type buffer boundary layer is 0.15 at the interface with the N-type buffer layer, and 0.25 at the interface with the N-type cladding layer 20.
  • the N-type cladding layer 20 is an N-type semiconductor layer disposed above the substrate 10.
  • the average refractive index of the N-type cladding layer 20 is lower than the average refractive index of the active layer 30.
  • the N-type cladding layer 20 is placed on the N-type buffer boundary layer.
  • the N-type cladding layer 20 is an N-type Al 0.25 Ga 0.75 As layer with a thickness of 3.1 ⁇ m.
  • the active layer 30 is a light emitting layer disposed above the N-type cladding layer 20.
  • active layer 30 has a quantum well structure.
  • FIG. 5 is a schematic cross-sectional view showing the configuration of the active layer 30 according to this embodiment.
  • FIG. 5 shows a cross section of the active layer 30 taken along line II-II in FIG.
  • the active layer 30 includes an N-side cladding boundary layer 31, an N-side guide layer 32, an N-side barrier layer 33, a well layer 34, a P-side barrier layer 35, and a P-side guide layer 33.
  • layer 36 and a P-side cladding boundary layer 37 is a schematic cross-sectional view showing the configuration of the active layer 30 according to this embodiment.
  • FIG. 5 shows a cross section of the active layer 30 taken along line II-II in FIG.
  • the active layer 30 includes an N-side cladding boundary layer 31, an N-side guide layer 32, an N-side barrier layer 33, a well layer 34, a P-side barrier
  • the active layer 30 has a window region 30w (that is, a non-light emitting region) near the end surface 1F of the semiconductor light emitting device 1.
  • a window region 30w that is, a non-light emitting region
  • the bandgap energy is larger than the regions other than the region 30w. This suppresses light emission and absorption of light in the vicinity of the end face 1F, so that heat generation in the vicinity of the end face 1F can be suppressed. Therefore, COD (catastrophic optical damage) near the end surface 1F of the semiconductor light emitting device 1 can be suppressed.
  • the active layer 30 has a window region 30w also near the end surface 1R.
  • the window region 30w is formed over a predetermined length in the light propagation direction from the end of the active layer 30 on the end surface 1F side.
  • the length of the window region 30w in the light propagation direction may be equal to the length from the end of the upper ridge Ru on the end surface 1F side to the end of the P-type cladding layer 40 on the end surface 1F side.
  • the state where these lengths are equal is not limited to a state where these lengths are completely equal, but also includes a state where these lengths are substantially equal.
  • the state where these lengths are equal includes, for example, a state where the difference between these lengths is 10% or less of each length.
  • the N-side cladding boundary layer 31 shown in FIG. 5 is a semiconductor layer disposed above the N-type cladding layer 20 (see FIGS. 2 to 4).
  • the N-side cladding boundary layer 31 is an N-type Al X31 Ga 1-X31 As layer ( 0.25 ⁇ X31 ⁇ 0.20).
  • the Al composition ratio X31 of the N-side cladding boundary layer 31 decreases as it approaches the N-side guide layer 32.
  • the Al composition ratio X31 of the N-side cladding boundary layer 31 is 0.25 at the interface with the N-type cladding layer 20 and 0.20 at the interface with the N-side guide layer 32.
  • the N-side guide layer 32 is a semiconductor layer disposed above the N-type cladding layer 20 (see FIGS. 2 to 4).
  • the average refractive index of the N-side guide layer 32 is higher than the average refractive index of the N-type cladding layer 20.
  • the N-side guide layer 32 is arranged above the N-side cladding boundary layer 31.
  • the N-side guide layer 32 is an N-type Al 0.20 Ga 0.80 As layer with a thickness of 0.27 ⁇ m.
  • the N-side barrier layer 33 is a semiconductor layer that is placed above the N-type cladding layer 20 and functions as a barrier for the quantum well structure. In this embodiment, the N-side barrier layer 33 is arranged above the N-side guide layer 32.
  • the N-side barrier layer 33 is an undoped Al 0.16 Ga 0.84 As layer with a thickness of 0.010 ⁇ m.
  • the well layer 34 is a semiconductor layer that is disposed above the N-type cladding layer 20 and functions as a well of a quantum well structure. In this embodiment, the well layer 34 is arranged above the N-side barrier layer 33.
  • the well layer 34 is an undoped In 0.14 Ga 0.86 As layer with a thickness of 0.0090 ⁇ m.
  • the P-side barrier layer 35 is a semiconductor layer that is placed above the N-type cladding layer 20 (see FIGS. 2 to 4) and functions as a barrier for the quantum well structure. In this embodiment, the P-side barrier layer 35 is arranged above the well layer 34.
  • the P-side barrier layer 35 is an undoped Al 0.16 Ga 0.84 As layer with a thickness of 0.010 ⁇ m.
  • the P-side guide layer 36 is a semiconductor layer disposed above the N-type cladding layer 20 (see FIGS. 2 to 4).
  • the average refractive index of the P-side guide layer 36 is higher than the average refractive index of the P-type cladding layer 40 (see FIGS. 2 to 4).
  • the P-side guide layer 36 is arranged above the P-side barrier layer 35.
  • the P-side guide layer 36 is a P-type Al X36 Ga 1-X36 As layer (0.20 ⁇ X36 ⁇ 0.21) with a film thickness of 0.29 ⁇ m.
  • the Al composition ratio X36 of the P-side guide layer 36 is 0.20 in a region where the distance from the interface between the P-side guide layer 36 and the P-side barrier layer 35 is 0.010 ⁇ m or less.
  • the Al composition ratio X36 of the P-side guide layer 36 increases as it approaches the P-side cladding boundary layer 37 in a region where the distance from the interface between the P-side guide layer 36 and the P-side barrier layer 35 is greater than 0.010 ⁇ m. increase
  • the Al composition ratio X36 of the P-side guide layer 36 is 0.21 at the interface with the P-side cladding boundary layer 37.
  • the P-side cladding boundary layer 37 is a semiconductor layer disposed above the N-type cladding layer 20 (see FIGS. 2 to 4).
  • the P-side cladding boundary layer 37 is made of N-type Al having a thickness of 0.1 ⁇ m, which is disposed between the P-side guide layer 36 and the P-type cladding layer 40 (see FIGS. 2 to 4).
  • the layer is an X37 Ga 1-X37 As layer (0.21 ⁇ X37 ⁇ 0.75).
  • the Al composition ratio X37 of the P-side cladding boundary layer 37 increases as it approaches the P-type cladding layer 40.
  • the Al composition ratio X37 of the P-side cladding boundary layer 37 is 0.21 at the interface with the P-side guide layer 36 and 0.75 at the interface with the P-type cladding layer 40.
  • the P-type cladding layer 40 shown in FIGS. 2 to 4 is a P-type semiconductor layer disposed above the active layer 30.
  • the average refractive index of the P-type cladding layer 40 is lower than the average refractive index of the active layer 30.
  • the P-type cladding layer 40 is made of Al x Ga 1-X As (0 ⁇ X ⁇ 1), and includes a lower cladding layer 41, a first cladding layer 42, and a first etching stop layer. 43, a second cladding layer 44, and a second etching stop layer 45.
  • the lower cladding layer 41 is a P-type semiconductor layer disposed above the active layer 30.
  • the lower cladding layer 41 is a P-type Al 0.75 Ga 0.25 As layer with a thickness of 0.050 ⁇ m.
  • the first cladding layer 42 is a P-type semiconductor layer disposed above the active layer 30.
  • the first cladding layer 42 is a P-type Al 0.85 Ga 0.15 As layer with a thickness of 0.10 ⁇ m, which is disposed above the lower cladding layer 41 .
  • the first etching stop layer 43 is a P-type semiconductor layer disposed above the active layer 30. In this embodiment, the first etching stop layer 43 is arranged above the first cladding layer 42 .
  • the Al composition ratio of the first etching stop layer 43 is 0.7 or less.
  • the first etching stop layer 43 is a P-type Al 0.70 Ga 0.30 As layer with a thickness of 0.05 ⁇ m.
  • the second cladding layer 44 is a P-type semiconductor layer disposed above the active layer 30.
  • the second cladding layer 44 is a P-type Al 0.85 Ga 0.15 As layer with a thickness of 0.20 ⁇ m, which is disposed above the first etching stop layer 43 .
  • the second etching stop layer 45 is a P-type semiconductor layer disposed above the active layer 30.
  • the second etching stop layer 45 is a P-type Al X45 Ga 1-X45 As layer (0.70 ⁇ X45 ⁇ 0 .15).
  • the second etching stop layer 45 has two or more inclined regions where the Al composition ratio decreases as it approaches the contact layer, and one or more constant regions where the Al composition ratio is constant with respect to the position in the stacking direction. . Two or more inclined regions and one or more fixed regions are arranged alternately in the stacking direction.
  • FIG. 6 the structure of the second etching stop layer 45 according to this embodiment will be explained using FIG. 6. FIG.
  • FIG. 6 is a schematic cross-sectional view showing the structure of the second etching stop layer 45 according to this embodiment.
  • FIG. 6 shows a cross section of the second etching stop layer 45 at the ridge R along line II-II in FIG.
  • the second etching stop layer 45 has two inclined regions 45b and 45d and two constant regions 45a and 45c.
  • the constant region 45a is a P-type Al 0.70 Ga 0.30 As layer with a thickness of 0.050 ⁇ m, which is disposed above the second cladding layer 44 .
  • the inclined region 45b is a P-type Al X45 Ga 1-X45 As layer with a thickness of 0.01 ⁇ m, which is disposed above the fixed region 45a.
  • the Al composition ratio X45 of the inclined region 45b decreases as it approaches the contact layer 50.
  • the Al composition ratio X45 of the inclined region 45b is 0.70 at the interface with the constant region 45a, and 0.60 at the interface with the constant region 45c.
  • the constant region 45c is a P-type Al 0.60 Ga 0.40 As layer with a thickness of 0.030 ⁇ m, which is disposed above the inclined region 45b.
  • the inclined region 45d is a P-type Al X45 Ga 1-X45 As layer with a film thickness of 0.010 ⁇ m, which is disposed above the fixed region 45c.
  • the Al composition ratio X45 of the inclined region 45d decreases as it approaches the contact layer 50.
  • the Al composition ratio X45 of the inclined region 45d is 0.60 at the interface with the fixed region 45c, and 0.15 at the interface with the contact layer 50.
  • the contact layer 50 is a P-type semiconductor layer arranged above the P-type cladding layer 40 and in ohmic contact with the first P-side electrode 71.
  • the contact layer 50 is a P-type GaAs layer with a thickness of 0.25 ⁇ m.
  • FIGS. 1 and 2 a ridge R extending in the light propagation direction is formed in a region including the P-type cladding layer 40 and the contact layer 50.
  • a waveguide is formed along the ridge R.
  • FIG. 1 shows the outline of the upper surface of the ridge R.
  • FIG. 7 is an enlarged view of the ridge R shown in FIG.
  • the ridge R includes a lower ridge Rd including a P-type cladding layer 40, and an upper ridge Ru disposed on the top surface Rdt of the lower ridge Rd and including a contact layer 50.
  • the top surface Rdt of the lower ridge Rd has a flat portion Rdf that is located between the side surface Rds of the lower ridge Rd and the bottom surface Rub of the upper ridge Ru and extends in the light propagation direction.
  • the width Wub of the bottom surface Rub of the upper ridge Ru is smaller than the width Wdt of the top surface Rdt of the lower ridge Rd and the width Wdc of the lower ridge Rd at the center position Rdc in the stacking direction.
  • the width of the ridge R here refers to the direction perpendicular to the stacking direction (that is, the Z-axis direction) and the longitudinal direction of the ridge R (that is, the light propagation direction or the Y-axis direction) (that is, the This means the dimension of the ridge R in the axial direction).
  • the width Wut of the top surface Rut of the upper ridge Ru is smaller than the width Wub of the bottom surface Rub of the upper ridge Ru. That is, the upper ridge Ru has a forward mesa shape in a cross section perpendicular to the longitudinal direction of the ridge R.
  • the side surface Rus of the upper ridge Ru forms a mesa-shaped inclined surface.
  • the upper ridge Ru includes at least a portion of the contact layer 50.
  • the upper ridge Ru includes at least a portion of each of the second etching stop layer 45 and the contact layer 50.
  • the upper ridge Ru is not formed near the end surface 1F of the semiconductor light emitting device 1.
  • the upper surface of the end closer to the end surface 1F from which the light of the semiconductor light emitting element 1 is emitted is located on the second etching stop layer 45 . That is, the contact layer 50 is not formed at the end of the ridge R in the light propagation direction that is closer to the end face 1F from which the light of the semiconductor light emitting element 1 is emitted.
  • the semiconductor light emitting device 1 is junction-down (that is, flip-chip) mounted on a mounting board or the like, stress can be suppressed from being concentrated at the end of the ridge R. Therefore, damage near the end face 1F of the semiconductor light emitting device 1 can be suppressed.
  • the upper ridge Ru is not formed even near the end surface 1R of the semiconductor light emitting device 1.
  • the end of the upper ridge Ru that is closer to the end face 1F from which the light of the semiconductor light emitting element 1 is emitted is , has an inverted mesa shape.
  • the upper end of the upper ridge Ru is located closer to the end surface 1F than the lower end.
  • the lower ridge Rd includes at least a portion of each of the second cladding layer 44 and the second etching stop layer 45.
  • the lower ridge Rd includes at least a portion of each of the first etching stop layer 43, the second cladding layer 44, and the second etching stop layer 45.
  • the top surface Rdt of the lower ridge Rd is located on the second etching stop layer 45. Therefore, the flat portion Rdf, which is a part of the top surface Rdt of the lower ridge Rd, is also located in the second etching stop layer 45.
  • the Al composition ratio of the flat portion Rdf is 0.7 or less.
  • the width Wdt of the top surface Rdt of the lower ridge Rd may be equal to the width Wdc of the lower ridge Rd at the center position Rdc in the stacking direction.
  • the state where the width Wdt and the width Wdc are equal is not limited to a state where the widths Wdt and the width Wdc are completely equal, but also includes a state where the widths are substantially equal.
  • the state where the width Wdt and the width Wdc are equal includes, for example, a state where the difference between the width Wdt and the width Wdc is 3% or less of each width.
  • the upper surface (that is, the bottom Tb shown in FIG. 7) of the P-type cladding layer 40 at a position adjacent to the bottom surface Rdb of the lower ridge Rd in the width direction (that is, the X-axis direction) of the lower ridge Rd is the first Located in the etching stop layer 43.
  • the bottom surface Rdb of the lower ridge Rd is located at the first etching stop layer 43.
  • a wing portion G extending along the ridge R is formed in a region including the P-type cladding layer 40 and the contact layer 50.
  • the groove T is formed between the wing portion G and the ridge R.
  • FIG. 1 shows the outline of the upper surface of the wing portion G.
  • the wing portion G will be explained below using FIG. 8.
  • FIG. 8 is an enlarged view of the wing portion G shown in FIG.
  • the wing section G includes a lower wing section Gd including a P-type cladding layer 40, and an upper wing section Gu disposed on the top surface Gdt of the lower wing section Gd and including a contact layer 50.
  • the top surface Gdt of the lower wing portion Gd is located between the side surface Gds of the lower wing portion Gd and the bottom surface Gub of the upper wing portion Gu, and is a wing flat portion Gdf that is a flat area extending in the light propagation direction. has.
  • a ridge R is formed between two wing parts G. Such a wing portion G can suppress stress applied to the ridge R when the semiconductor light emitting device 1 is mounted on a mounting board or the like.
  • a recess 3 recessed in the width direction of the semiconductor light emitting element 1 is formed at the end of the semiconductor light emitting element 1 in the width direction (that is, the end in the X axis direction).
  • a recess 3 is formed on the outer side of the wing portion G in the X-axis direction.
  • the recess 3 is part of a separation groove used when dividing the semiconductor light emitting device 1 into individual pieces. As shown in FIG. 8 and the like, the portion of the side surface of the semiconductor light emitting device 1 corresponding to the recess 3 is constricted toward the inside in the X-axis direction.
  • a side surface Gds of the lower wing portion Gd on the side far from the ridge R is included in the recess 3.
  • the side surface Gds of the lower wing portion Gd on the side far from the ridge R is a constriction portion located inside in the width direction of the semiconductor light emitting device 1 from the upper end of the lower wing portion Gd (the position corresponding to the top surface Gdt of the side surface Gds). It has 3w.
  • the position of the recess 3 in the width direction of the semiconductor light emitting device 1 is located at the innermost side in the width direction (that is, closer to the ridge R) in the P-type cladding layer 40. In other words, the recess 3 is the narrowest in the P-type cladding layer 40.
  • the position of the recess 3 in the width direction of the semiconductor light emitting element 1 is shifted outward in the width direction of the semiconductor light emitting element 1 (that is, in a direction away from the ridge R) as it approaches the substrate 10 from the active layer 30 from the upper end of the lower wing part Gd. to) move.
  • the upper wing portion Gu has a forward mesa shape in a cross section perpendicular to the longitudinal direction of the wing portion G.
  • the side surface Gus of the upper wing portion Gu forms a mesa-shaped inclined surface.
  • the insulating film 60 is an electrical insulating film disposed above the P-type cladding layer 40. As shown in FIG. 7, the insulating film 60 continuously covers from the side surface Rds of the lower ridge Rd to a part of the top surface Rut of the upper ridge Ru. That is, the insulating film 60 continuously covers the side surface Rds of the lower ridge Rd, the flat portion Rdf, the side surface Rus of the upper ridge Ru, and the top surface Rut. In this embodiment, an opening 60a is formed at a position corresponding to the top surface Rut of the upper ridge Ru of the insulating film 60. A current is injected from the first P-side electrode 71 to the contact layer 50 through the opening 60a.
  • the opening 60a is a current injection window region into the contact layer 50.
  • the insulating film 60 continuously covers the entire upper surface of the semiconductor stack formed on the substrate 10 except for the opening 60a. Thereby, it is possible to suppress current from flowing to regions other than the ridge R.
  • the material of the insulating film 60 is not particularly limited as long as it is electrically insulating.
  • the insulating film 60 is a silicon nitride film with a thickness of 100 nm.
  • the first P-side electrode 71 is a conductive layer placed above the contact layer 50. As shown in FIG. 7, the first P-side electrode 71 is in contact with the contact layer 50 on the upper surface of the ridge R, that is, on the top surface Rut of the upper ridge Ru. As shown in FIGS. 7 and 8, the first P-side electrode 71 has an opening extending from the upper surface of one wing portion G (that is, the top surface Gut of the upper wing portion Gu) to the upper surface of the other wing portion G. Continuously cover except for the portion 60a.
  • the material of the first P-side electrode 71 is not particularly limited as long as it is conductive.
  • the first P-side electrode 71 includes, for example, a Ti film with a thickness of 50 nm, a Pt film with a thickness of 150 nm, and an Au film with a thickness of 50 nm, which are laminated in order from the contact layer 50 side.
  • the pad electrode 73 shown in FIGS. 2 and 4 is a pad-shaped conductive layer placed above the first P-side electrode 71.
  • the pad electrode 73 has an eave-shaped portion 73a at the end in the X-axis direction.
  • the eaves-like portion 73a is a portion that protrudes outward in the X-axis direction at the upper end of the end portion of the pad electrode 73 in the X-axis direction.
  • the configuration of pad electrode 73 is not particularly limited.
  • pad electrode 73 is an Au plating film with a thickness of 2.5 ⁇ m.
  • the second P-side electrode 72 shown in FIGS. 2 to 4 is a conductive layer placed above the pad electrode 73.
  • the second P-side electrode 72 may also be arranged in a region of the upper surface of the first P-side electrode 71 and the insulating film 60 where the pad electrode 73 is not arranged.
  • the configuration of the second P-side electrode 72 is not particularly limited.
  • the second P-side electrode 72 is a Ti film with a thickness of 50 nm, a Pt film with a thickness of 150 nm, and an Au film with a thickness of 300 nm, which are laminated in order from the pad electrode 73 side.
  • the N-side electrode 80 shown in FIGS. 2 and 4 is arranged on the lower main surface of the substrate 10 (that is, among the main surfaces of the substrate 10, the main surface on the back side of the main surface on which the semiconductor layer is laminated). It is a conductive layer.
  • the configuration of the N-side electrode 80 is not particularly limited.
  • the N-side electrode 80 includes a 90 nm thick AuGe film, a 20 nm thick Ni film, a 50 nm thick Au film, a 100 nm thick Ti film, and a 50 nm thick Ti film, which are laminated in order from the substrate 10 side. , a Ti film with a thickness of 50 nm, a Pt film with a thickness of 100 nm, and an Au film with a thickness of 500 nm.
  • FIGS. 9 to 24 are schematic cross-sectional views showing each step of the method for manufacturing the semiconductor light emitting device 1 according to this embodiment. 9, FIG. 11, FIG. 13, FIG. 15, FIG. 17, FIG. 19, FIG. 20, FIG. 22, and FIG. It is shown. 10, FIG. 12, FIG. 14, FIG. 16, FIG. 18, FIG. 21, and FIG. 24 show cross sections of the semiconductor light emitting device 1 taken along the line III--III shown in FIG.
  • each semiconductor layer is formed.
  • the process of forming each semiconductor layer includes a process of forming an N-type cladding layer 20 above the substrate 10, a process of forming an active layer 30 above the N-type cladding layer 20, and a process of forming a P-type cladding layer 30 above the active layer 30.
  • the method includes a step of forming a cladding layer 40 and a step of forming a contact layer 50 above the P-type cladding layer 40.
  • the step of forming each semiconductor layer includes a step of forming an N-type buffer layer above the substrate 10, and a step of forming an N-type buffer layer above the N-type buffer layer before the step of forming the N-type cladding layer. forming an N-type buffer boundary layer.
  • Each semiconductor layer is formed by crystal growth using, for example, MOCVD (Metalorganic Chemical Vapor Deposition).
  • a window region 30w is formed in a region of the active layer 30 corresponding to the vicinity of the end face 1F.
  • the window region 30w can be formed by diffusing an impurity such as Zn into the active layer 30.
  • a window region 30w is also formed in a region corresponding to the vicinity of the end surface 1R.
  • a ridge R is formed in a region including the P-type cladding layer 40 and the contact layer 50.
  • the step of forming the ridge R includes a step of forming an upper ridge Ru, and a step of forming a lower ridge Rd (see FIG. 2) after the step of forming the upper ridge Ru.
  • an upper ridge Ru is formed.
  • the upper wing portion Gu is also formed at the same time.
  • wet etching is used in the step of forming the upper ridge Ru.
  • the side surface Rus can be inclined so that the upper ridge Ru has a forward mesa shape. Therefore, the adhesion between the side surface Rus and the insulating film 60 can be improved.
  • a mask made of SiO 2 or the like is formed in a predetermined pattern on the contact layer 50 by photolithography. Thereafter, the portions of the contact layer 50 that are not covered with the mask are removed by wet etching.
  • the chemical solution used for etching and the configuration of each semiconductor layer are determined so that the etching rate of the second etching stop layer 45 is slower than that of the contact layer 50. This makes it easier to stop etching in the second etching stop layer 45. In other words, the controllability of the heights of the upper ridge Ru and the upper wing portion Gu can be improved.
  • contact layer 50 and a portion of second etching stop layer 45 are removed by wet etching. That is, the bottom surface Rub of the upper ridge Ru and the bottom surface Gub of the upper wing portion Gu are located in the second etching stop layer 45.
  • the second etching stop layer 45 has constant regions 45a and 45c (see FIG. 6) in which the Al composition ratio is constant with respect to the position in the stacking direction, so that the entire second etching stop layer 45 is Etching can be stopped more reliably in the second etching stop layer 45 than in the case where the second etching stop layer 45 is formed of an inclined region.
  • a solution containing tartaric acid and hydrogen peroxide solution can be used as the chemical solution used for etching.
  • the mixing ratio of tartaric acid and hydrogen peroxide solution is, for example, 2:1.
  • the upper ridge Ru and the upper wing portion Gu that have a normal mesa shape in a cross section perpendicular to the light propagation direction.
  • the upper ridge Ru is not formed near the end surface 1F (and end surface 1R) of the semiconductor light emitting device 1.
  • the end of the upper ridge Ru closer to the end surface 1F has an inverted mesa shape.
  • the lower ridge Rd and the lower wing part Gd are formed as shown in FIGS. 13 and 14.
  • wet etching is used in the step of forming the lower ridge Rd.
  • a mask made of SiO 2 or the like is formed by photolithography so as to cover the upper ridge Ru and the upper wing portion Gu.
  • the mask is also formed in regions corresponding to the flat portion Rdf and the wing flat portion Gdf.
  • the groove T is formed by etching the region of the P-type cladding layer 40 that is not covered with the mask up to the first etching stop layer 43 using a wet etching technique.
  • a lower ridge Rd having a flat portion Rdf and a lower wing portion Gd having a wing flat portion Gdf can be formed.
  • the chemical solution used for etching and the structure of each semiconductor layer are determined so that the etching rate of the first etching stop layer 43 is slower than that of the second cladding layer 44. This makes it easier to stop etching in the first etching stop layer 43. In other words, it is possible to improve the controllability of the heights of the lower ridge Rd and the lower wing portion Gd.
  • second etching stop layer 45, second cladding layer 44, and part of first etching stop layer 43 are removed by wet etching. That is, the bottom surface Rdb of the lower ridge Rd and the bottom surface Gdb of the lower wing portion Gd are located in the first etching stop layer 43.
  • a solution containing sulfuric acid, hydrogen peroxide, and water can be used as the chemical solution used for etching.
  • the mixing ratio of sulfuric acid, hydrogen peroxide, and water is, for example, 1:1:6.
  • the lower ridge Rd and the lower wing portion Gd can be formed as shown in FIGS. 13 and 14.
  • the lower ridge Rd and the lower wing portion Gd are continuously formed from the end of the P-type cladding layer 40 on the end surface 1F side to the end on the end surface 1R side.
  • the effective refractive index difference ⁇ N between the inside and outside of the ridge R of the semiconductor light emitting device 1 and the individual differences in the spread angle of the emitted light can be reduced.
  • the effective refractive index difference is the difference between the ridge R and the effective refractive index n0 for light below the ridge R, and the effective refractive index n1 on the outside of the ridge R in the width direction.
  • the outer side of the ridge R in the width direction means the outer side (in the X-axis direction) of the maximum width position of the ridge R.
  • the maximum width of the ridge R is the width Wdb of the bottom surface Rdb of the lower ridge Rd.
  • the effective refractive index is a value obtained by multiplying the distribution of light guided through the semiconductor light emitting device 1 (in this embodiment, the light distribution generated during laser oscillation) and the refractive index distribution of the semiconductor light emitting device 1.
  • the dry etching can form the lower ridge Rd and the lower wing portion Gd having the shapes described above.
  • SiCl 4 can be used as the dry etching gas.
  • the inclination angle of the side surface Rds of the lower ridge Rd changes depending on the flow rate of SiCl 4 during etching. By setting the flow rate of SiCl 4 to, for example, 10 sccm or more, the side surface Rds of the lower ridge Rd having an inclination angle close to perpendicular to the main surface of the substrate 10 can be formed.
  • a recess 3 recessed in the width direction of the semiconductor light emitting element 1 is formed at the end of the semiconductor light emitting element 1 in the width direction.
  • the recess 3 is a part of a separation groove used in dividing the semiconductor light emitting device 1 into individual pieces. That is, in a state where a plurality of semiconductor stacked bodies shown in FIGS. 13 and 14 are connected in the X-axis direction, a separation groove is formed between adjacent semiconductor stacked bodies, and along the separation groove, Separate the semiconductor stack. As a result, a recess 3 as shown in FIGS. 15 and 16 is formed.
  • an insulating film 60 is formed on the ridge R.
  • the insulating film 60 continuously covers from the side surface Rds of the lower ridge Rd to a part of the top surface Rut of the upper ridge Ru.
  • an insulating film 60 is formed over the entire upper surface of the semiconductor stack shown in FIGS. 15 and 16.
  • a silicon nitride film is formed as the insulating film 60 using a CVD method or the like.
  • an opening 60a is formed in a region of the insulating film 60 corresponding to the top surface Rut of the upper ridge Ru.
  • a mask is formed in a region of the insulating film 60 other than the region corresponding to the opening 60a.
  • the opening 60a is formed by, for example, etching a region of the insulating film 60 corresponding to the opening 60a.
  • the first P-side electrode 71 is formed.
  • the first P-side electrode 71 is formed at least in the opening 60a of the insulating film 60.
  • the first P-side electrode 71 continuously covers from the top surface Gut of one upper wing section Gu to the top surface Gut of the other upper wing section Gu.
  • the first P-side electrode 71 is formed using, for example, a photolithography technique and a vapor deposition method.
  • Pad electrode 73 is formed at least above opening 60a of insulating film 60.
  • the area on the first P-side electrode 71 from the top surface Gut of one upper wing portion Gu to the top surface Gut of the other upper wing portion Gu is continuously covered.
  • Pad electrode 73 is formed using, for example, a plating method.
  • the pad electrode 73 may have an eave-shaped portion 73a at the end in the X-axis direction.
  • the second P-side electrode 72 is formed.
  • the second P-side electrode 72 is formed in the region above the pad electrode 73 at least above the opening 60a of the insulating film 60.
  • the second P-side electrode 72 covers the entire upper surface of the pad electrode 73.
  • the second P-side electrode 72 covers at least a portion of the upper surface of the first P-side electrode 71 arranged around the periphery of the pad electrode 73 .
  • the second P-side electrode 72 does not need to cover the area below the eave-shaped portion 73a among the side surfaces of the pad electrode 73.
  • the second P-side electrode 72 is formed using, for example, a photolithography technique and a vapor deposition method.
  • an N-side electrode 80 is formed on the lower surface of the substrate 10 (the main surface on the back side of the main surface on which each semiconductor layer is laminated among the main surfaces of the substrate 10). do.
  • the N-side electrode 80 is formed at least at a position facing the opening 60a of the insulating film 60.
  • the N-side electrode 80 is formed using, for example, photolithography and vapor deposition.
  • the semiconductor light emitting device 1 according to this embodiment can be formed.
  • the semiconductor light emitting device 1 has an upper ridge Ru and a lower ridge Rd.
  • the top surface Rdt of the lower ridge Rd has a flat portion Rdf that is located between the side surface Rds of the lower ridge Rd and the bottom surface Rub of the upper ridge Ru and extends in the light propagation direction.
  • the width Wub of the bottom surface Rub of the upper ridge Ru is smaller than the width Wdt of the top surface Rdt of the lower ridge Rd and the width Wdc of the lower ridge Rd at the center position Rdc in the stacking direction.
  • the top surface of the upper ridge Ru is The current injected from the surface Rut flows into a region inside the side surface Rds of the top surface Rdt of the lower ridge Rd. Therefore, it is possible to suppress the current from flowing to the side surface Rds of the lower ridge Rd. Thereby, heat generation due to current flowing through the side surface Rds of the lower ridge Rd can be suppressed, so that the output of the semiconductor light emitting device 1 can be increased. Further, failures caused by heat generation of the semiconductor light emitting device 1 can be reduced.
  • the lower ridge Rd has the flat portion Rdf, the adhesion between the insulating film 60 and the ridge R can be improved. Therefore, the insulation between the first P-side electrode 71 and the side surfaces (side surface Rds and side surface Rus) of the ridge R can be improved.
  • FIG. 25 is a graph showing the relationship between the output power of the semiconductor light emitting device 1 according to this embodiment and the injection current.
  • a solid line shows the relationship when the temperature (Tc) of the measurement stage is 25° C.
  • the average refractive index of the P-type cladding layer 40 can be reduced. Therefore, the average refractive index difference between the active layer 30 and the P-type cladding layer 40 can be increased, so that the effect of confining light near the active layer 30 can be increased.
  • the maximum output power can be increased by about 3.5 W compared to the semiconductor light emitting device of the comparative example.
  • the Al composition ratio of the first etching stop layer 43 is 0.7 or less.
  • the Al composition ratio X1 is larger than 0.8 as in the first cladding layer 42, it is easily oxidized and easily corroded by a chemical solution used in etching or the like.
  • the first etching stop layer 43 with an Al composition ratio of 0.7 or less on the first cladding layer 42 etching can be stopped by the first etching stop layer 43, and the first cladding layer 42 Exposure can be suppressed. Therefore, oxidation and erosion of the first cladding layer 42 can be suppressed.
  • the Al composition ratio of the flat portion Rdf of the lower ridge Rd is 0.7 or less. That is, the flat portion Rdf is located in the second etching stop layer 45. Thereby, etching can be stopped at the flat portion Rdf, and exposure of the second cladding layer 44 having an Al composition ratio X2 greater than 0.8 can be reduced. Therefore, oxidation and erosion of the second cladding layer 44 can be suppressed.
  • the second etching stop layer 45 includes sloped regions 45b and 45d in which the Al composition ratio decreases as it approaches the contact layer 50. This makes it possible to suppress a sudden change in composition in the stacking direction, thereby suppressing an energy barrier caused by a sudden change in band gap. Therefore, since the electrical resistance in the second etching stop layer 45 can be suppressed, the operating voltage of the semiconductor light emitting device 1 can be suppressed.
  • the second etching stop layer 45 includes one or more constant regions 45a and 45c in which the Al composition ratio is constant with respect to the position in the stacking direction.
  • the etching stop property of the second etching stop layer 45 can be improved.
  • the two or more inclined regions 45b and 45d and the one or more fixed regions 45a and 45c are arranged alternately in the lamination direction, the electrical resistance in the second etching stop layer 45 can be suppressed while etching Stopping performance can be improved.
  • the width Wdt of the top surface Rdt of the lower ridge Rd, the width Wdc at the center position Rdc in the stacking direction of the lower ridge Rd, and the width Wdb of the bottom surface Rdb of the lower ridge Rd, Wdt>Wdc, as well as, Wdb>Wdc The relationship holds true. Thereby, the current can be constricted in the lower ridge Rd.
  • the width Wut of the top surface Rut of the upper ridge Ru is smaller than the width Wub of the bottom surface Rub of the upper ridge Ru.
  • the upper surface of the end of the ridge R in the light propagation direction that is closer to the end surface 1F from which the light of the semiconductor light emitting element 1 is emitted is located in the second etching stop layer 45. do.
  • the upper ridge Ru is not formed at the end of the ridge R closer to the end surface 1F. That is, the contact layer 50 is not formed at the end of the ridge R in the light propagation direction that is closer to the end face 1F from which the light of the semiconductor light emitting element 1 is emitted.
  • the active layer 30 includes a well layer 34 , a P-side barrier layer 35 disposed above the well layer 34 , and a P-side guide layer 36 disposed above the P-side barrier layer 35 . and a P-side cladding boundary layer 37.
  • the remaining thickness dc defined as the sum is greater than 0.5 ⁇ m.
  • the horizontal spread angle means the spread angle in the X-axis direction in each figure.
  • the horizontal spread angle of the emitted light can be suppressed.
  • a light emitting module with a lens including the semiconductor light emitting element 1 and a lens disposed near the end surface 1F of the semiconductor light emitting element 1
  • the emitted light and Coupling efficiency with the lens can be increased.
  • the effective refractive index difference ⁇ N between the ridge R and the effective refractive index n0 for light below the ridge R and the effective refractive index n1 outside the ridge R in the width direction is 4 ⁇ 10 ⁇ 4 It is as follows. The effects produced by the effective refractive index difference will be explained using FIG. 27.
  • FIG. 27 is a graph showing the relationship between the horizontal spread angle of the emitted light of the semiconductor light emitting device 1 according to the present embodiment and the effective refractive index difference ⁇ N.
  • the horizontal spread angle can be suppressed to 10.5 degrees or less. Therefore, when configuring the light emitting module with a lens as described above, by suppressing the horizontal spread angle of the emitted light, it is possible to increase the coupling efficiency between the emitted light and the lens.
  • the thickness tpc0 of the lower cladding layer 41, the thickness tpc1 of the first cladding layer 42, and the thickness ts1 of the first etching stop layer 43 are as follows. ts1 ⁇ tpc0 ⁇ tpc1 The relationship holds true. In this way, by increasing the thickness of the lower cladding layer 41 having a higher refractive index than the first cladding layer 42, the first etching stop layer 43 having a higher refractive index than the first cladding layer 42 is formed from the first cladding layer 42. Light leakage can be suppressed. Further, by reducing the thickness ts1 of the first etching stop layer 43, which has a relatively high electrical resistance, the operating voltage of the semiconductor light emitting device 1 can be suppressed.
  • the thickness tng of the N-side guide layer 32 and the thickness tpg of the P-side guide layer 36 are as follows. tng>tpg The relationship holds true. Thereby, the peak position of the light intensity distribution can be located closer to the N-side guide layer 32 with respect to the well layer 34. Therefore, since the waveguide loss in the semiconductor light emitting device 1 can be reduced, the slope efficiency can be increased.
  • the top surface Gdt of the lower wing portion Gd is located between the side surface Gds of the lower wing portion Gd and the bottom surface Gub of the upper wing portion Gu, and is a flat surface extending in the light propagation direction. It has a wing flat portion Gdf which is a wide area. Thereby, the adhesion between the wing portion G and the insulating film 60 can be improved.
  • FIG. 28 is a schematic top view showing the overall configuration of a semiconductor light emitting device 1a according to this modification.
  • 29 to 32 are schematic cross-sectional views showing the overall structure of a semiconductor light emitting device 1a according to this modification. 29, FIG. 30, and FIG.
  • FIG. 31 show cross sections of the semiconductor light emitting device 1a taken along the lines XXIX-XXIX, XXX-XXX, and XXXI-XXXI in FIG. 28, respectively. Further, FIG. 32 shows only a part of the cross section of the semiconductor light emitting device 1a taken along the line XXXII-XXXII in FIG. 28, including the end surface 1F.
  • the semiconductor light emitting device 1a according to this modification differs from the semiconductor light emitting device 1 according to the embodiment in the configuration near the end in the light propagation direction,
  • the other configurations are the same as shown in FIG. More specifically, the semiconductor light emitting device 1a according to the present modification is different from the semiconductor light emitting device according to the embodiment in the configuration between the ridge R and the end surface 1F and the configuration between the ridge R and the end surface 1R. Different from 1.
  • the region including the P-type cladding layer 40 and the contact layer 50 is located between the end surface 1F of the semiconductor light emitting device 1a in the light propagation direction and the upper ridge Ru. , and has a separate region De spaced apart from the upper ridge Ru.
  • the groove Te is formed between the upper ridge Ru and the separation region De.
  • the contact layer 50 and a portion of the P-type cladding layer 40 are removed in the trench Te.
  • the separation region De is arranged between the two wing parts G, as shown in FIGS. 28 and 31. Further, the isolated region De and the two wing portions G are connected.
  • the upper surface of the contact layer 50 at the end of the semiconductor light emitting device 1a in the light propagation direction is flat and continuous over the entire length of the contact layer 50 in the width direction (that is, the X-axis direction).
  • the contact layer 50 and the second etching stop layer 45 cover the second cladding layer 44 and the like having a high Al composition ratio at the ends of the semiconductor light emitting device 1a according to the present modification in the light propagation direction, Oxidation and erosion of the second cladding layer 44 and the like can be suppressed.
  • the adhesion between the semiconductor stack including these layers and the insulating film 60 can be improved.
  • the semiconductor light emitting device 1a when the semiconductor light emitting device 1a is diced into pieces, it is cleaved at positions corresponding to the ends in the light propagation direction. may peel off.
  • the adhesion between the insulating film 60 and the contact layer 50 at the position corresponding to the end in the light propagation direction can be improved. Peeling of the film 60 can be suppressed.
  • the distance D1 from the end of the contact layer 50 in the light propagation direction to the end of the pad electrode 73 in the light propagation direction is the distance D1 between both ends of the separation region De in the light propagation direction. It is smaller than the distance (that is, the length of the separation region De) D2 and larger than zero.
  • the distance D1 is about 10 ⁇ m
  • the distance D2 is 20 ⁇ m or more and 150 ⁇ m or less. The smaller the distance D1 is, the better, as long as it is equal to or greater than the control accuracy of the cleavage position when dividing the semiconductor light emitting device 1a into pieces.
  • FIG. 33 is a schematic top view showing the overall configuration of a semiconductor light emitting device 1b according to this modification.
  • 34 to 36 are schematic cross-sectional views showing the overall configuration of a semiconductor light emitting device 1b according to this modification.
  • 34, FIG. 35, and FIG. 36 show cross sections of the semiconductor light emitting device 1b taken along the XXXIV-XXXIV line, the XXXV-XXXV line, and the XXVI-XXXVI line in FIG. 33, respectively.
  • the semiconductor light emitting device 1b according to this modification differs from the semiconductor light emitting device 1a according to modification 1 in the configuration of the separation region De, and is different from the semiconductor light emitting device 1a according to modification 1 in the configuration of the separation region De. and so on in other configurations.
  • the separation region De and the wing portion G are not connected.
  • the contact layer 50 is not continuous between the separation region De and the wing portion G.
  • the widthwise end of the separation region De is located at a position corresponding to the widthwise end of the upper ridge Ru.
  • the position of the widthwise end of the separation region De in the X-axis direction is equal to the position of the widthwise end of the upper ridge Ru in the X-axis direction.
  • the state where these positions are equal is not limited to a state where these positions are completely equal, but also includes a state where these positions are substantially equal.
  • the state where the description that these positions are equal includes, for example, a state where the difference between these positions is 10% or less of the width of the ridge R.
  • the pad electrode 73 is not formed at the end of the semiconductor light emitting device 1b in the light propagation direction, so at least a part of the isolated region De is covered with the pad electrode 73. Not covered. Therefore, the position of the widthwise end of the separation region De can be confirmed based on the appearance of the semiconductor light emitting element 1b.
  • the position of the separation region De in the width direction corresponds to the position of the ridge R in the width direction, so the position of the waveguide, that is, is determined based on the position of the end of the separation region De in the width direction.
  • the position where light is emitted from the end face 1F (position in the X-axis direction) can be confirmed based on the appearance of the semiconductor light emitting element 1b.
  • the contact layer 50 is separated by the separation region De and the wing portion G, but the second etching stop layer 45 of the P-type cladding layer 40 and The second cladding layer 44 is not separated.
  • the upper surface of the second cladding layer 44 at the end of the semiconductor light emitting device 1b in the light propagation direction is flat and continuous over the entire length of the second cladding layer 44 in the width direction, and the second etching stop is Covered with layer 45.
  • the second etching stop layer 45 covers the second cladding layer 44 and the like having a high Al composition ratio, so that oxidation and erosion of the second cladding layer 44 and the like can be suppressed.
  • the adhesion between the semiconductor stack including these layers and the insulating film 60 can be improved. Therefore, similarly to the semiconductor light emitting device 1a according to the first modification, peeling of the insulating film 60 during cleavage can be suppressed.
  • the semiconductor light emitting device 1 is a semiconductor laser device, but the semiconductor light emitting device 1 is not limited to a semiconductor laser device.
  • the semiconductor light emitting device may be a superluminescent diode.
  • the semiconductor light emitting device 1 has two wing portions G, but the semiconductor light emitting device 1 may have only one wing portion G.
  • the active layer 30 of the semiconductor light emitting device 1 has a single quantum well structure, but it may have a multiple quantum well structure.
  • the active layer 30 of the semiconductor light emitting device 1 had the window region 30w near the end surface 1F and the end surface 1R, but the semiconductor light emitting device 1 does not have the window region 30w. Good too.
  • the inclined regions 45b and 45d of the second etching stop layer 45 are regions in which the Al composition ratio decreases as the contact layer 50 is approached; It may also be a region where the ratio increases.
  • the semiconductor light emitting device of the present disclosure can be used, for example, as a high output and highly efficient light source for laser processing.

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  • Optics & Photonics (AREA)
  • Geometry (AREA)
  • Semiconductor Lasers (AREA)
PCT/JP2023/016403 2022-04-28 2023-04-26 半導体発光素子、及び半導体発光素子の製造方法 Ceased WO2023210676A1 (ja)

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JP2006073818A (ja) * 2004-09-02 2006-03-16 Sharp Corp 半導体素子、半導体素子の製造方法、光ディスク装置および光伝送システム
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