WO2023210642A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2023210642A1
WO2023210642A1 PCT/JP2023/016309 JP2023016309W WO2023210642A1 WO 2023210642 A1 WO2023210642 A1 WO 2023210642A1 JP 2023016309 W JP2023016309 W JP 2023016309W WO 2023210642 A1 WO2023210642 A1 WO 2023210642A1
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Prior art keywords
layer
region
collector
semiconductor device
emitter
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PCT/JP2023/016309
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English (en)
French (fr)
Japanese (ja)
Inventor
将之 青池
新之助 高橋
昌俊 長谷
史生 播磨
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Priority to CN202380035902.6A priority Critical patent/CN119072788A/zh
Priority to JP2024517343A priority patent/JP7740531B2/ja
Publication of WO2023210642A1 publication Critical patent/WO2023210642A1/ja
Priority to US18/901,620 priority patent/US20250022873A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/021—Manufacture or treatment of heterojunction BJTs [HBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/051—Manufacture or treatment of vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/80—Heterojunction BJTs
    • H10D10/821—Vertical heterojunction BJTs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/231—Emitter or collector electrodes for bipolar transistors
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/50—PIN diodes 
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/05—Manufacture or treatment characterised by using material-based technologies using Group III-V technology
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/611—Combinations of BJTs and one or more of diodes, resistors or capacitors
    • H10D84/613—Combinations of vertical BJTs and one or more of diodes, resistors or capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/611—Combinations of BJTs and one or more of diodes, resistors or capacitors
    • H10D84/613—Combinations of vertical BJTs and one or more of diodes, resistors or capacitors
    • H10D84/615—Combinations of vertical BJTs and one or more of resistors or capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/611—Combinations of BJTs and one or more of diodes, resistors or capacitors
    • H10D84/613—Combinations of vertical BJTs and one or more of diodes, resistors or capacitors
    • H10D84/617—Combinations of vertical BJTs and only diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/641—Combinations of only vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/253—Semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present invention relates to a semiconductor device.
  • a semiconductor device in which a semi-insulating GaAs substrate is bonded onto a Si substrate via a bonding layer such as an Au film (Patent Document 1).
  • An n-type subcollector layer is placed on a semi-insulating GaAs substrate, and a heterojunction bipolar transistor (HBT) is placed on top of the n-type subcollector layer.
  • HBT heterojunction bipolar transistor
  • a collector electrode is arranged on the n-type subcollector layer. The collector electrode is connected to the collector layer of the HBT via the n-type sub-collector layer.
  • a collector electrode is connected to a collector layer via a sub-collector layer.
  • a semiconductor layer doped with a high concentration of n-type dopant to reduce the resistance is used, but the resistance is higher than that of metal, and the parasitic resistance generated between the collector electrode and the collector layer is high. , which impedes improvement in the operating speed of the transistor.
  • An object of the present invention is to provide a semiconductor device that can reduce parasitic resistance between a collector electrode and a collector layer and improve the operating speed of a transistor.
  • a support substrate an adhesive layer including a first metal region disposed on at least a partial region of the upper surface of the support substrate; a base layer including a sub-collector region made of a conductive semiconductor material, disposed on the adhesive layer and electrically connected to the first metal region; A collector layer disposed on the sub-collector region and electrically connected to the sub-collector region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer.
  • a first transistor a collector electrode disposed on the sub-collector region at a position outside the first transistor in plan view and overlapping with the first metal region, and electrically connected to the sub-collector region;
  • a semiconductor device is provided.
  • the first metal region is connected to the sub-collector region, parasitic resistance between the collector layer and the collector electrode of the first transistor is reduced. Thereby, it is possible to improve the operating speed of the first transistor.
  • FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment.
  • FIG. 2 is a sectional view taken along the dashed-dotted line 2-2 in FIG.
  • the drawings from FIG. 3A to FIG. 3F are schematic cross-sectional views at an intermediate stage of manufacturing the semiconductor device.
  • 4A, 4B, and 4C are schematic cross-sectional views of a semiconductor device at an intermediate stage of manufacturing, and
  • FIG. 4D is a schematic cross-sectional view of a completed semiconductor device.
  • FIG. 5 is a schematic diagram of the first transistor of the semiconductor device according to the first embodiment.
  • FIG. 6 is a cross-sectional view of a semiconductor device according to a second embodiment. 7A, FIG. 7B, and FIG.
  • FIG. 7C are cross-sectional views of the semiconductor device according to the second embodiment at an intermediate stage of manufacture.
  • FIG. 8 is a diagram schematically showing a cross-sectional structure of a semiconductor device according to a third embodiment.
  • FIG. 9 is a diagram schematically showing a cross-sectional structure of a semiconductor device according to a third embodiment.
  • FIG. 10 is a diagram schematically showing a cross-sectional structure of a semiconductor device according to a fourth example.
  • FIG. 11 is a diagram schematically showing a cross-sectional structure of a semiconductor device according to a fifth embodiment.
  • FIG. 12 is an equivalent circuit diagram of a semiconductor device according to a sixth embodiment.
  • FIG. 13 is a diagram schematically showing a cross-sectional structure of a semiconductor device according to a sixth embodiment.
  • FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment.
  • An adhesive layer 21 including a metal region 21A is arranged on a support substrate 20, which will be described later with reference to FIG.
  • a sub-collector region 40A made of a semiconductor material is arranged so as to substantially overlap the metal region 21A.
  • a plurality of first transistors 41 are arranged, for example, in a line in one direction (vertical direction in FIG. 1).
  • Each of the first transistors 41 includes a collector layer 41C, a base layer 41B, and an emitter layer 41E.
  • the collector layer 41C and the base layer 41B substantially overlap in plan view.
  • the emitter layer 41E is smaller than the base layer 41B in plan view and is included in the base layer 41B.
  • the emitter electrode 42E is arranged so as to substantially overlap the emitter layer 41E in plan view.
  • the emitter electrode 42E has a long shape in a direction perpendicular to the arrangement direction of the first transistors 41 (left-right direction in FIG. 1) in plan view.
  • the shape of the emitter electrode 42E in plan view is, for example, a rectangle.
  • a U-shaped base electrode 42B is arranged at intervals from each of the two long sides and one short side of the emitter electrode 42E.
  • the base electrodes 42B are all open toward the same direction (rightward in FIG. 1).
  • Collector electrodes 42C are arranged between the two first transistors 41 adjacent to each other and on the outside of the first transistors 41 at both ends.
  • the emitter electrode 42E, the base electrode 42B, and the collector electrode 42C are hatched with relatively dark upward hatching.
  • a first layer base wiring 43B is connected to a portion of each of the plurality of base electrodes 42B spaced apart from the short side of the emitter electrode 42E.
  • Each base wiring 43B extends to the outside of the sub-collector region 40A in a direction away from the emitter electrode 42E.
  • Each of the base wirings 43B intersects with the second-layer common base wiring 44B in plan view.
  • Input capacitors Cin are formed at intersections between each of the first-layer base wirings 43B and the second-layer base wirings 44B.
  • a high frequency signal is input from the second layer base wiring 44B to the base electrode 42B via the input capacitor Cin and the first layer base wiring 43B.
  • a first layer collector wiring 43C is connected to each of the plurality of collector electrodes 42C.
  • the collector wiring 43C extends in a direction opposite to the direction in which the base wiring 43B extends from a location where it overlaps with each of the collector electrodes 42C, and is connected to each other outside the sub-collector region 40A.
  • the base wiring 43B and the collector wiring 43C are hatched with relatively light downward slanting hatching.
  • First-layer emitter wiring 43E is arranged so as to substantially overlap each emitter electrode 42E.
  • a second layer emitter wiring 44E is arranged so as to overlap with all the emitter wirings 43E from the emitter wiring 43E at one end to the emitter wiring 43E at the other end in the arrangement direction of the first transistor 41.
  • the second layer emitter wiring 44E interconnects the plurality of first layer emitter wirings 43E. In this way, the emitters of the plurality of first transistors 41 are mutually connected, the collectors are mutually connected, and the plurality of first transistors 41 are connected in parallel.
  • a second layer collector wiring 44C is arranged so as to overlap the collector wiring 43C outside the sub-collector region 40A. In FIG. 1, the second layer emitter wiring 44E, collector wiring 44C, and base wiring 44B are represented by relatively thick outlines.
  • FIG. 2 is a sectional view taken along the dashed line 2-2 in FIG. 1.
  • An adhesive layer 21 is arranged on the support substrate 20.
  • Adhesive layer 21 includes at least one metal region 21A. In FIG. 2, a cross section of one metal region 21A of the adhesive layer 21 is shown.
  • the support substrate 20 for example, a high-resistance silicon substrate can be used.
  • an Au film can be used. Note that a metal film containing Ag, Pt, Cu, Al, W, Ti, or Ta other than Au may be used.
  • a base layer 40 made of a semiconductor material is bonded onto the adhesive layer 21.
  • the base layer 40 includes a sub-collector region 40A imparted with conductivity and an insulated element isolation region. In FIG. 2, a cross section of the sub-collector region 40A is shown, and the element isolation region is not shown.
  • a plurality of first transistors 41 are arranged on the sub-collector region 40A.
  • Each of the first transistors 41 includes a collector layer 41C, a base layer 41B, and an emitter layer 41E stacked in this order on the base layer 40.
  • the first transistor 41 is, for example, a heterojunction bipolar transistor.
  • the sub-collector region 40A and collector layer 41C of the base layer 40 are formed of n-type GaAs
  • the base layer 41B is formed of p-type GaAs.
  • the emitter layer 41E includes two layers, for example, an n-type InGaP layer and an n-type GaAs layer thereon. Note that these semiconductor layers may be formed of other compound semiconductors, such as InP, GaN, SiGe, and SiC.
  • a plurality of collector electrodes 42C are arranged on the sub-collector region 40A so as to sandwich each of the first transistors 41 therebetween. Note that one collector electrode 42C is arranged between two adjacent first transistors 41, and one collector electrode 42C is shared by the first transistors 41 on both sides.
  • the collector electrode 42C is electrically connected to the collector layer 41C via the sub-collector region 40A. Further, the sub-collector region 40A is electrically connected to the metal region 21A therebelow.
  • the state in which "the sub-collector region 40A is electrically connected to the metal region 21A" is a state in which both are in ohmic contact, and a state in which both are in Schottky contact, but the Schottky barrier is sufficiently thin and substantially This includes a state that is considered to be ohmic contact.
  • the subcollector region 40A is made of highly doped n-type GaAs and the two are in shot contact, the Schottky barrier will be sufficiently thin.
  • a first-layer collector wiring 43C is arranged on each of the collector electrodes 42C via an interlayer insulating film (not shown). The collector wiring 43C is connected to the collector electrode 42C through an opening provided in the interlayer insulating film.
  • the emitter layer 41E is arranged on a part of the base layer 41B. Note that a ledge structure may be used in which the emitter layer 41E is disposed over the entire area of the base layer 41B, and the emitter mesa is disposed over a partial region of the emitter layer 41E. In this configuration, a region overlapping with the emitter mesa in plan view substantially functions as an emitter layer.
  • a base electrode 42B is placed on the base layer 41B, and an emitter electrode 42E is placed on the emitter layer 41E.
  • the base electrode 42B is electrically connected to the base layer 41B, and the emitter electrode 42E is electrically connected to the emitter layer 41E.
  • a first layer emitter wiring 43E is arranged on each of the emitter electrodes 42E with an interlayer insulating film (not shown) interposed therebetween. Emitter wiring 43E is electrically connected to emitter electrode 42E through an opening provided in the interlayer insulating film.
  • One emitter wiring 44E of the second layer is arranged on the plurality of emitter wirings 43E of the first layer with an interlayer insulating film (not shown) interposed therebetween.
  • the emitter wiring 44E in the second layer is connected to the plurality of emitter wirings 43E in the first layer through an opening provided in the interlayer insulating film.
  • An emitter pad 82E is placed on the emitter wiring 44E, and an emitter protrusion electrode 83E is placed on top of the emitter pad 82E.
  • a Cu pillar bump is used as the emitter protrusion electrode 83E.
  • Solder 84 is placed on emitter protrusion electrode 83E.
  • FIG. 3A to FIG. 4D are schematic cross-sectional views of the semiconductor device at an intermediate stage of manufacturing
  • FIG. 4D is a schematic cross-sectional view of the completed semiconductor device.
  • a peeling layer 201 is epitaxially grown on a single crystal mother substrate 200 of a compound semiconductor such as GaAs, and an element forming layer 202 is formed on the peeling layer 201.
  • the element structure shown in FIG. 2 from the base layer 40 to the second layer emitter wiring 44E is formed in the element formation layer 202.
  • These element structures are formed by common semiconductor processes.
  • the description of the element structure formed in the element formation layer 202 is omitted.
  • element structures corresponding to a plurality of semiconductor devices are formed in the element formation layer 202, and are not separated into individual semiconductor devices.
  • the emitter pad 82E, the emitter protrusion electrode 83E, and the solder 84 (FIG. 2) are not formed.
  • the element forming layer 202 and peeling layer 201 are patterned using a resist pattern (not shown) as an etching mask. At this stage, the element formation layer 202 is separated for each semiconductor device.
  • a connecting support 204 is attached on top of the separated element forming layer 202.
  • the plurality of element formation layers 202 are interconnected via the connection support 204.
  • the resist pattern used as an etching mask in the patterning step of FIG. 3B may be left, and the resist pattern may be interposed between the element forming layer 202 and the connection support 204.
  • the release layer 201 is selectively etched with respect to the mother substrate 200 and the element forming layer 202.
  • the element formation layer 202 and the connection support 204 are peeled off from the mother substrate 200.
  • a compound semiconductor having different etching resistance from both the mother substrate 200 and the element formation layer 202 is used as the peeling layer 201.
  • an adhesive layer 21 is formed on the upper surface of the support substrate 20.
  • the adhesive layer 21 includes a plurality of metal regions 21A distributed within the plane and an insulating region 21Z arranged in a region where the metal regions 21A are not arranged.
  • the adhesive layer 21 can be formed by, for example, a damascene process.
  • the insulating region 21Z is formed of, for example, an insulating oxide or nitride, specifically silicon oxide, silicon nitride, silicon oxynitride, or the like.
  • the element forming layer 202 is bonded to the adhesive layer 21.
  • the element forming layer 202 and the adhesive layer 21 are bonded to each other by van der Waals bond or hydrogen bond.
  • the element forming layer 202 may be bonded to the adhesive layer 21 by electrostatic force, covalent bonding, eutectic alloy bonding, or the like.
  • the metal region 21A is made of Au
  • the element forming layer 202 may be brought into close contact with the Au film and pressurized to bond the two.
  • connection support 204 is peeled off from the element forming layer 202.
  • an interlayer insulating film 86 and a rewiring layer are formed on the adhesive layer 21 and the element formation layer 202.
  • the rewiring layer includes an emitter pad 82E disposed on the emitter wiring 44E (FIG. 2), an interconnection wiring 82W connecting the circuit included in the element formation layer 202 and one metal region of the adhesive layer 21, and the like. included.
  • a protective film 87 is formed on the redistribution layer including the emitter pad 82E, interconnection wiring 82W, etc., and a plurality of openings 87A are formed in the protective film 87.
  • the plurality of openings 87A are each included in the plurality of emitter pads 82E in plan view.
  • An emitter protrusion electrode 83E is formed within the opening 87A. Note that the emitter protrusion electrode 83E extends to the top of the protective film 87 around the opening 87A.
  • the emitter protrusion electrode 83E protrudes in the direction away from the support substrate 20. Further, solder 84 is placed on the top surface of the emitter protrusion electrode 83E and reflow processing is performed.
  • the support substrate 20 is diced.
  • a semiconductor device 28 is obtained which is divided into pieces, including the support substrate 20, the adhesive layer 21, the element formation layer 202, the emitter pad 82E, the emitter protrusion electrode 83E, the interconnection wiring 82W, and the like.
  • the support substrate 20 is larger than the element formation layer 202 in plan view.
  • the diced semiconductor devices are flip-chip mounted on a module substrate or the like.
  • FIG. 5 is a schematic diagram of the first transistor 41 of the semiconductor device according to the first embodiment.
  • a collector electrode 42C is in contact with one surface of the sub-collector region 40A, and a metal region 21A is in contact with the other surface.
  • a current flows from the collector electrode 42C in contact with one surface of the sub-collector region 40A to the emitter electrode 42E through the sub-collector region 40A, the collector layer 41C, the base layer 41B, and the emitter layer 41E. flows.
  • the parasitic resistance of the sub-collector region 40A is denoted as R1.
  • a resistance component R2 of the metal region 21A in contact with the other surface of the sub-collector region 40A is connected in parallel to the parasitic resistance R1 of the sub-collector region 40A. Therefore, the parasitic resistance between the collector electrode 42C and the collector layer 41C is reduced. This reduction in parasitic resistance allows the operating frequency of the first transistor 41 to be increased.
  • the adhesive layer 21 not only has the function of bonding the support substrate 20 and the element formation layer 202 (FIG. 4A etc.), but also reduces the parasitic resistance between the collector electrode 42C and the collector layer 41C of the first transistor 41. It has the function of reducing
  • electrodes connected to the second layer emitter wiring 44E, collector wiring 44C, and base wiring 44B are formed on the surface of the element formation layer 202. exposed. Therefore, before bonding the element formation layer 202 to the support substrate 20, an evaluation test of the first transistor 41 can be performed by bringing a probe into contact with these electrodes.
  • the heat generated in the first transistor 41 is conducted to the support substrate 20 via the adhesive layer 21, and the emitter wirings 43E, 44E and the emitter protrusion electrode 83E etc., to the module board on which the semiconductor device is mounted.
  • the heat generated by the first transistor 41 is conducted in two directions, up and down, so that heat dissipation from the first transistor 41 can be improved.
  • the support substrate 20 may be made of any one of the semiconductor material forming the collector layer 41C, base layer 41B, and emitter layer 41E of the first transistor 41, and the semiconductor material forming the sub-collector region 40A.
  • the thermal conductivity of Si which is the material of the support substrate 20
  • GaAs which is the material of the collector layer 41C, base layer 41B, and subcollector region 40A
  • InGaP which is the material of the emitter layer 41E. It has higher thermal conductivity. Therefore, a sufficient effect of improving heat dissipation from the first transistor 41 can be obtained.
  • FIG. 6 is a cross-sectional view of a semiconductor device according to the second embodiment.
  • the adhesive layer 21 includes at least one single-layer metal region 21A.
  • the adhesive layer 21 includes two layers: a lower adhesive layer 21L on the support substrate 20 side and an upper adhesive layer 21U on the underlayer 40 side.
  • the lower adhesive layer 21L includes at least one metal region 21LA
  • the upper adhesive layer 21U includes at least one metal region 21UA.
  • the metal region 21LA of the lower adhesive layer 21L and the metal region 21UA of the upper adhesive layer 21U overlap each other and are bonded together.
  • Au, Ag, Pt, Cu, Al, W, Ti, or Ta is used for the metal regions 21LA and 21UA.
  • the same metal or different metals may be used for the metal area 21LA and the metal area 21UA.
  • a sub-collector region 40A of the base layer 40 is electrically connected to a metal region 21UA of the upper adhesive layer 21U.
  • the structure in which the metal region 21UA of the upper adhesive layer 21U and the metal region 21LA of the lower adhesive layer 21L are bonded is a structure in which both are in contact with each other without a gap in the entire area, and a structure in which the metal region 21UA of the upper adhesive layer 21U is bonded.
  • a gap is formed between a part of the metal area 21LA of the lower adhesive layer 21L and a part of the metal area 21LA of the lower adhesive layer 21L includes a structure in which they contact each other in other areas.
  • FIGS. 7A, 7B, and 7C are cross-sectional views of the semiconductor device according to the second embodiment at an intermediate stage of manufacture.
  • the configuration shown in FIG. 7A is the same as the configuration shown in FIG. 3D of the first embodiment during the manufacturing stage.
  • the element forming layer 202 is bonded to the support substrate 20 in close contact with the metal region 21A (FIG. 3F) of the adhesive layer 21.
  • an upper adhesive layer 21U is formed on the surface of the element forming layer 202 (the lower surface of the base layer 40 in FIG. 6).
  • the upper adhesive layer 21U can be formed by depositing a metal film using, for example, a vacuum deposition method, a sputtering method, or the like, and then etching away unnecessary portions. Alternatively, a lift-off method may be used.
  • a lower adhesive layer 21L is formed on the support substrate 20.
  • the lower adhesive layer 21L can be formed by a method similar to that described with reference to FIG. 3E in the first embodiment.
  • the metal area 21LA of the lower adhesive layer 21L is brought into close contact with the metal area 21UA of the upper adhesive layer 21U to join them together.
  • the subsequent procedure is the same as the procedure described with reference to the drawings from FIG. 4A to FIG. 4D of the first embodiment.
  • the element forming layer 202 is bonded to the support substrate 20 by bringing metals into contact with each other. Therefore, the joining process is easier than when joining a metal and a semiconductor by bringing them into contact.
  • the interface between the base layer 40 (FIG. 6) and the upper adhesive layer 21U (FIG. 6) is kept clean. can be maintained in the same condition.
  • the contact resistance between the sub-collector region 40A of the base layer 40 and the metal region 21UA of the upper adhesive layer 21U can be reduced. Therefore, the resistance component R2 connected in parallel to the parasitic resistance R1 (FIG. 5) of the sub-collector region 40A further decreases. Thereby, the effect of reducing the parasitic resistance between the collector layer 41C and the collector electrode 42C can be enhanced.
  • FIGS. 8 and 9 a semiconductor device according to a third embodiment will be described with reference to FIGS. 8 and 9.
  • a description of the common components of the semiconductor device according to the first embodiment described with reference to the drawings from FIG. 1 to FIG. 5 will be omitted.
  • FIGS. 8 and 9 are diagrams schematically showing the cross-sectional structure of a semiconductor device according to a third example. Note that FIGS. 8 and 9 do not show a cross section of the semiconductor device taken along a specific plane, but schematically show the structure in the stacking direction and the in-plane direction.
  • a plurality of first transistors 41 are arranged on the base layer 40.
  • a second transistor 61 and a diode 71 are arranged on the base layer 40.
  • one first transistor 41 is shown in FIG. 8 and two first transistors 41 are shown in FIG. 9, the number of first transistors 41 may be three or more.
  • one collector electrode 42C (FIG. 2) is arranged between two first transistors 41, and one collector electrode 42C is shared by the first transistors 41 on both sides.
  • two collector electrodes 42C are arranged between two first transistors 41. That is, two collector electrodes 42C are arranged for each of the first transistors 41.
  • the adhesive layer 21 has a two-layer structure including a lower adhesive layer 21L and an upper adhesive layer 21U, similar to the second embodiment (FIG. 6).
  • the lower adhesive layer 21L includes metal regions 21LB and 21LC in addition to the metal region 21LA. Metal regions 21LA, 21LB, and 21LC are electrically isolated from each other by an insulating region 21Z.
  • the upper adhesive layer 21U includes metal regions 21UB and 21UC in addition to the metal region 21UA. Metal regions 21UA, 21UB, and 21UC are separated from each other in the in-plane direction via a cavity. Note that the plurality of metal regions 21LA, 21LB, and 21LC of the lower adhesive layer 21L may also be separated from each other via a cavity. Further, the plurality of metal regions 21UA, 21UB, and 21UC of the upper adhesive layer 21U may be electrically isolated from each other via an insulating region.
  • the base layer 40 includes, in addition to the sub-collector region 40A, a sub-collector region 40B and a conductive region 40C. Sub-collector regions 40A, 40B and conductive region 40C are separated from each other by element isolation region 40Z.
  • the element isolation region 40Z is formed, for example, by implanting ions into the base layer 40 made of n-type GaAs to increase the resistance.
  • the sub-collector region 40A and the metal regions 21UA and 21LA overlap each other in plan view and are electrically connected to each other.
  • the sub-collector region 40B and metal regions 21UB and 21LB also overlap each other in plan view and are electrically connected to each other
  • the conductive region 40C and metal regions 21UC and 21LC also overlap each other in plan view, are electrically connected to each other.
  • “the components A, B, and C overlap each other” means that at least a portion of the component A, at least a portion of the component B, and at least a portion of the component C overlap in plan view. means. In a plan view, when one component is included in another component, it can be said that the two components overlap with each other even if the outer circumferential lines of the two components coincide.
  • the second transistor 61 is arranged on the sub-collector region 40B, and like the first transistor 41, includes a collector layer 61C, a base layer 61B, and an emitter layer 61E.
  • a collector electrode 62C disposed on the sub-collector region 40B is electrically connected to the collector layer 61C via the sub-collector region 40B.
  • Base electrode 62B is connected to base layer 61B, and emitter electrode 62E is connected to emitter layer 61E.
  • the first layer collector wiring 63C is connected to the collector electrode 62C, and the first layer emitter wiring 63E is connected to the emitter electrode 62E.
  • the emitter electrode 62E of the second transistor 61 is not connected to the protruding electrode.
  • the diode 71 is placed on the conductive region 40C and includes a cathode layer 71C made of n-type GaAs and an anode layer 71A made of p-type GaAs.
  • the collector layer 41C of the first transistor 41, the collector layer 61C of the second transistor 61, and the cathode layer 71C of the diode 71 are formed by patterning a common n-type GaAs layer.
  • the base layer 41B of the first transistor 41, the base layer 61B of the second transistor 61, and the anode layer 71A of the diode 71 are formed by patterning a common p-type GaAs layer.
  • the emitter layer 41E of the first transistor 41 and the emitter layer 61E of the second transistor 61 are formed by patterning a common n-type InGaP layer or the like.
  • a cathode electrode 72C is arranged on the conductive region 40C, and the cathode electrode 72C is electrically connected to the cathode layer 71C via the conductive region 40C.
  • a first layer of cathode wiring 73C is arranged on the cathode electrode 72C.
  • An anode electrode 72A is arranged on the anode layer 71A.
  • Anode electrode 72A is electrically connected to anode layer 71A.
  • An interlayer insulating film 80 is arranged to cover the first transistor 41, the second transistor 61, the diode 71, the first layer emitter wirings 43E and 63E, the collector wirings 43C and 63C, and the cathode wiring 73C. Note that an interlayer insulating film is also arranged between the emitter electrode 42E and the first layer emitter wiring 43E, but the description of this interlayer insulating film is omitted.
  • a second layer emitter wiring 44E is arranged on the interlayer insulating film 80. The second layer emitter wiring 44E is connected to the first layer emitter wiring 43E through an opening provided in the interlayer insulating film 80.
  • the element structure from the base layer 40 to the second layer emitter wiring 44E corresponds to the element formation layer 202 (FIG. 7A).
  • An interlayer insulating film 86 is arranged on the second layer emitter wiring 44E and the interlayer insulating film 80, and an opening is provided in the interlayer insulating film 86 to expose the second layer emitter wiring 44E. As shown in FIG. 4B, the interlayer insulating film 86 extends to the top of the support substrate 20 outside the element formation layer 202 in plan view.
  • An emitter pad 82E is arranged on the second layer emitter wiring 44E in the opening provided in the interlayer insulating film 86 and on the interlayer insulating film 86 around the opening.
  • a protective film 87 is disposed on the emitter pad 82E and the interlayer insulating film 86, and an opening is provided in the protective film 87 to expose the emitter pad 82E.
  • An emitter protrusion electrode 83E is arranged on the emitter pad 82E in the opening of the protective film 87 and on the protective film 87 around the opening. Solder 84 is placed on emitter protrusion electrode 83E.
  • the plurality of metal regions 21LA, 21LB, and 21LC of the lower adhesive layer 21L are electrically separated from each other, and the plurality of metal regions 21UA, 21UB, and 21UC of the upper adhesive layer 21U are also electrically separated from each other. It is separated into For this reason, these metal regions 21UA, 21UB, 21UC, 21LA, 21LB, and 21LC of the adhesive layer 21 are used as a low-resistance layer for reducing parasitic resistance for each element arranged on the base layer 40. be able to. For example, parasitic resistance not only between the first transistor 41 but also between the collector layer 61C and the collector electrode 62C of the second transistor 61 can be reduced. Furthermore, parasitic resistance between the cathode layer 71C and the cathode electrode 72C of the diode 71 can be reduced.
  • FIG. 10 is a diagram schematically showing a cross-sectional structure of a semiconductor device according to a fourth example.
  • a capacitor 100, a resistance element 110, and an inductor 120 are arranged in addition to the first transistor 41.
  • the capacitor 100, the resistance element 110, and the inductor 120 are arranged on the element isolation region 40Z of the base layer 40.
  • the capacitor 100 has a lower electrode 100L and an upper electrode 100U placed thereon with an interlayer insulating film interposed therebetween.
  • the resistance element 110 has a high resistance portion 110R and end connection wiring 110W connected to both ends of the high resistance portion 110R.
  • the inductor 120 includes a spiral wiring having a two-layer structure including a lower layer 120L and an upper layer 120U.
  • the lower electrode 100L of the capacitor 100, the end connection wiring 110W of the resistive element 110, and the lower layer 120L of the inductor 120 are formed, for example, by patterning the same metal film as the collector electrode 42C.
  • the upper electrode 100U of the capacitor 100 and the upper layer 120U of the inductor 120 are formed by patterning the same metal film as the first layer collector wiring 43C and the like.
  • the lower adhesive layer 21L includes a plurality of metal regions 21LD and an insulating region 21LZ.
  • the insulating region 21LZ is formed, for example, by the same damascene method as the insulating region 21Z formed in the step shown in FIG. 3E of the first embodiment. Note that the insulating region 21LZ may be a natural oxide film formed on the surface of the support substrate 20 made of Si.
  • the upper adhesive layer 21U includes a plurality of metal regions 21UD and an insulating region 21UZ in addition to the metal region 21UA.
  • the metal region 21LA of the lower adhesive layer 21L and the metal region 21UD of the upper adhesive layer 21U overlap each other and are in close contact with each other.
  • Capacitor 100, resistance element 110, and inductor 120 are included in insulating region 21LZ and insulating region 21UZ in plan view.
  • the plurality of first transistors 41 constitute a high frequency amplification circuit.
  • Capacitor 100 is a DC cut capacitor that removes a DC component from a high frequency signal
  • resistance element 110 is a base ballast resistance element.
  • the capacitor 100 and the inductor 120 may constitute an impedance matching circuit.
  • the fourth embodiment by arranging various passive elements in addition to the plurality of first transistors 41 on the base layer 40, the size of the electronic circuit is reduced compared to a structure in which passive elements are arranged externally. be able to.
  • Each of the plurality of passive elements is included in the insulating regions 21UZ and 21LZ in plan view and does not overlap with the metal regions 21UD and 21LD, so that the parasitic capacitance between the passive elements and the metal regions 21UD and 21LD is reduced. Ru. Therefore, instability in operation due to high frequency coupling between the first transistor 41 and the passive element can be avoided.
  • FIG. 11 is a diagram schematically showing a cross-sectional structure of a semiconductor device according to a fifth embodiment.
  • the metal regions 21LA and 21LD of the lower adhesive layer 21L are electrically isolated from each other by the insulating region 21LZ, and the metal regions 21UA and 21UD of the upper adhesive layer 21U are insulated. They are electrically isolated from each other by a region 21UZ.
  • a cavity is formed between the metal regions 21LA and 21LD of the lower adhesive layer 21L, and a cavity is also formed between the metal regions 21UA and 21UD of the upper adhesive layer 21U.
  • a metal film is formed on the support substrate 20 and patterned, thereby forming metal regions 21LA and 21LD separated by a cavity.
  • Capacitor 100, resistance element 110, and inductor 120 are included in the hollow portion of lower adhesive layer 21L and upper adhesive layer 21U in plan view.
  • the electronic circuit is made smaller and operation instability due to high frequency coupling between the first transistor 41 and the passive element is avoided. be able to.
  • FIG. 12 is an equivalent circuit diagram of the semiconductor device according to the sixth embodiment.
  • the first transistor 41 constitutes a power stage amplifier circuit. Power supply voltage Vcc is applied to the collector of the first transistor 41 through the choke coil Lc, and the emitter of the first transistor 41 is grounded.
  • a second transistor 61 is included in the base bias circuit of the first transistor 41.
  • the emitter of the second transistor 61 is connected to the base of the first transistor 41 via a base ballast resistor Rb.
  • the battery voltage Vbatt is applied to the collector of the second transistor 61, and the bias control signal Vbias is provided to the base of the second transistor 61.
  • a base bias is supplied to the base of the first transistor 41 via the second transistor 61 and the base ballast resistor Rb.
  • a high frequency signal RFin is input to the base of the first transistor 41 through the input capacitor Cin.
  • An output signal RFout is output from the collector of the first transistor 41.
  • the collector of the first transistor 41 is grounded via a plurality of diodes 71 connected in series.
  • the plurality of diodes 71 are connected with a forward polarity from the collector of the first transistor 41 toward the ground potential, and function as clamp diodes.
  • FIG. 13 is a diagram schematically showing a cross-sectional structure of a semiconductor device according to a sixth embodiment.
  • the lower adhesive layer 21L is in direct contact with the silicon surface of the support substrate 20.
  • the support substrate 20 has a multilayer wiring layer 20A on the surface layer, and the lower adhesive layer 21L is in contact with the surface of the multilayer wiring layer 20A.
  • the base layer 40 includes a conductive region 40E, the upper adhesive layer 21U includes a metal region 21UE, and the lower adhesive layer 21L includes a metal region 21LE.
  • a connection electrode 72B is arranged on the conductive region 40E. In a plan view, the conductive region 40E and the metal regions 21UE and 21LE overlap each other and are electrically connected.
  • An anode electrode 72A of the diode 71 is connected to a connection electrode 72B via a first layer anode wiring 73A.
  • a wiring 20W included in the multilayer wiring layer 20A connects the metal region 21LA and the metal region 21LE. That is, the collector layer 41C of the first transistor 41 is electrically connected to the anode layer 71A of the diode 71 via the wiring 20W in the multilayer wiring layer 20A.
  • the collector electrode 42C and the collector wiring 43C electrically connected to the collector layer 41C of the first transistor 41 are used as electrodes to which a probe comes into contact in order to perform an evaluation test at the stage shown in FIG. 3B of the first embodiment. be done.
  • the wiring 20W in the multilayer wiring layer 20A of the support substrate 20 connects the first transistor 41 and the diode 71. Therefore, the degree of freedom in arranging the wiring on the base layer 40 can be increased. Furthermore, by using the collector wiring 43C connected to the sub-collector region 40A and the collector wiring 44C (FIG. 1) thereon as electrodes for evaluation tests, a state in which the base layer 40 is not bonded to the support substrate 20 ( An evaluation test can be performed in Figure 3B).
  • the metal region 21LA of the lower adhesive layer 21L and the metal region 21UA of the upper adhesive layer 21U have the function of reducing the parasitic resistance between the collector electrode 42C and the collector layer 41C by passing a current in the in-plane direction, and the thickness. It has a function of connecting the collector layer 41C and the wiring 20W in the support substrate 20 by passing a current in the horizontal direction.

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JP2017152550A (ja) * 2016-02-25 2017-08-31 日本電信電話株式会社 ヘテロ接合バイポーラトランジスタおよびその製造方法
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