WO2023206164A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

Info

Publication number
WO2023206164A1
WO2023206164A1 PCT/CN2022/089651 CN2022089651W WO2023206164A1 WO 2023206164 A1 WO2023206164 A1 WO 2023206164A1 CN 2022089651 W CN2022089651 W CN 2022089651W WO 2023206164 A1 WO2023206164 A1 WO 2023206164A1
Authority
WO
WIPO (PCT)
Prior art keywords
area
display
display area
layer
via holes
Prior art date
Application number
PCT/CN2022/089651
Other languages
English (en)
French (fr)
Inventor
谢涛峰
徐元杰
李双
黄耀
龙跃
蔡建畅
王彬艳
张静
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/089651 priority Critical patent/WO2023206164A1/zh
Priority to CN202280000924.4A priority patent/CN117321767A/zh
Publication of WO2023206164A1 publication Critical patent/WO2023206164A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate and a display device.
  • a display substrate has a main display area and a auxiliary display area.
  • the main display area at least partially surrounds the auxiliary display area.
  • the auxiliary display area includes an element setting area and a transition area surrounding the element setting area.
  • the display substrate includes: a substrate, a pixel circuit layer located on one side of the substrate, and a plurality of first via holes.
  • the substrate is located at least in the main display area and the secondary display area;
  • the pixel circuit layer includes an active layer and a multi-layer inorganic insulating layer disposed on a side of the active layer away from the substrate;
  • the active layer is located at least in the main display area and at least partially surrounds the auxiliary display area, and the multi-layer inorganic insulation layer is at least located in the main display area and the auxiliary display area.
  • the plurality of first via holes are at least located in the transition region; the plurality of first via holes penetrate at least one layer of the multi-layer inorganic insulation layer.
  • the secondary display area includes a first unit area area and a second unit area area, and the distance between the first unit area area and the boundary of the secondary display area is greater than the second unit area area. The distance between the area area and the boundary of the secondary display area.
  • the distribution density of the first via holes located in the first unit area area is less than or equal to the distribution density of the first via holes located in the second unit area area.
  • the distribution density of the first via holes in at least two first unit area areas that are the same as the spacing between boundaries of the secondary display areas is the same. And/or, the distribution density of the first via holes in at least two second unit area areas that are the same as the spacing between the boundaries of the secondary display areas is the same.
  • the first via holes located in the secondary display area are evenly distributed.
  • the plurality of first via holes are located in the transition region. At least some of the first via holes among the plurality of first via holes are arranged sequentially along the boundary of the component setting area and arranged in an annular shape.
  • the pixel circuit layer includes a plurality of pixel circuits.
  • a part of the plurality of first via holes is located in the transition area, and another part of the plurality of first via holes is located in a part of the component placement area that is at least close to the transition area.
  • the minimum size of the area occupied by part of the first via holes located in the component setting area is greater than or equal to the size of one pixel circuit.
  • the distribution density of part of the first via holes located in the transition area is the same as the distribution density of part of the first via holes located in the component placement area.
  • the display substrate further includes: a light-emitting device layer located on a side of the pixel circuit layer away from the substrate; the light-emitting device layer includes a plurality of secondary light-emitting devices located in the secondary display area. There is no overlap between the orthographic projection of a portion of the first via holes located in the element setting area on the substrate and the orthographic projection of the plurality of sub-light-emitting devices on the substrate.
  • the distribution density of the first via holes ranges from 1% to 14%.
  • the aperture of the first via hole, and the first via hole and the sub-display area is negatively correlated.
  • the multi-layer inorganic insulating layer includes a first gate insulating layer, a second gate insulating layer and an interlayer dielectric layer sequentially stacked in a direction away from the active layer, and at least one of the first through The hole penetrates the interlayer dielectric layer, the second gate insulating layer and the first gate insulating layer.
  • the pixel circuit layer further includes a plurality of redundant semiconductor patterns located in the secondary display area, and the plurality of redundant semiconductor patterns are arranged in the same layer as the active layer.
  • the display substrate further includes: a plurality of second via holes located in the secondary display area, and the second via holes penetrate at least one layer of the multi-layer inorganic insulation layer.
  • the orthographic projection of the plurality of second via holes on the substrate is located within the orthographic projection range of the plurality of redundant semiconductor patterns on the substrate, and is located at at least one of the transition regions.
  • the second via hole is the first via hole.
  • the plurality of second via holes penetrate the interlayer dielectric layer, the second gate insulating layer and the first gate insulating layer to the plurality of redundant semiconductor patterns away from the liner. surface on the bottom side.
  • the display substrate further includes: a light-emitting device layer located on a side of the pixel circuit layer away from the substrate; the light-emitting device layer includes a plurality of secondary light-emitting devices located in the secondary display area.
  • the orthographic projection of at least part of the plurality of second via holes on the substrate is located within the orthographic projection range of the plurality of sub-light-emitting devices on the substrate.
  • a portion of the plurality of second via holes is located in the component placement area.
  • the distribution density of the first via holes near the boundary of the component placement area is greater than or equal to the distribution density of the second via holes located in the component placement area.
  • the display substrate further includes: a plurality of third via holes located at least in the main display area.
  • the plurality of third via holes penetrates the multi-layer inorganic insulating layer to the surface of the active layer away from the substrate; the distribution density of the plurality of third via holes is less than or equal to the plurality of third via holes. The distribution density of the first via holes.
  • the pixel circuit layer includes a plurality of pixel circuits, at least a portion of the plurality of pixel circuits are located in the main display area, and at least a portion of the pixel circuits located in the main display area surround the secondary display area.
  • the pixel circuit includes driving transistors, and each driving transistor closest to the boundary of the sub-display area is the same as the minimum spacing between the sub-display areas.
  • the display substrate further includes: a light-emitting device layer located on the side of the pixel circuit layer away from the substrate, and the light-emitting device layer includes a plurality of main light-emitting devices located in the main display area. device and a plurality of secondary light-emitting devices located in the secondary display area.
  • the pixel circuit layer includes a plurality of display pixel circuits, and the plurality of display pixel circuits include a plurality of first display pixel circuits and a plurality of second display pixel circuits.
  • the plurality of first display pixel circuits are located in the main display area and are electrically connected to the plurality of main light-emitting devices respectively; and are respectively electrically connected to the plurality of secondary light-emitting devices through wires.
  • the display substrate has a display area and a frame area surrounding the display area, and the display area includes the main display area and the secondary display area.
  • the display substrate also includes: a light-emitting device layer located on the pixel circuit layer, the light-emitting device layer including a plurality of main light-emitting devices located in the main display area and a plurality of secondary light-emitting devices located in the secondary display area. .
  • the pixel circuit layer includes a plurality of display pixel circuits, the plurality of display pixel circuits include a plurality of first display pixel circuits and a plurality of second display pixel circuits; the plurality of first display pixel circuits are located on the main display area, and are electrically connected to the plurality of main light-emitting devices respectively; the plurality of second display pixel circuits are located in the main display area or the frame area, and are electrically connected to the plurality of secondary light-emitting devices through conduction. .
  • the pixel circuit layer further includes a plurality of redundant pixel circuits located in the main display area and between the plurality of pixel circuits and the secondary display area. between.
  • the display device includes: a display substrate as described in any one of the above embodiments, and an optical element.
  • the optical element is disposed on the non-light-emitting side of the display substrate, and the orthographic projection of the optical element on the display substrate at least partially overlaps with the element placement area of the display substrate.
  • Figure 1 is a structural diagram of a display device according to some embodiments of the present disclosure.
  • Figure 2 is a structural diagram of another display device according to some embodiments of the present disclosure.
  • Figure 3 is a structural diagram of a display substrate according to some embodiments of the present disclosure.
  • Figure 4 is a structural diagram of another display substrate according to some embodiments of the present disclosure.
  • Figure 5 is a structural diagram of another display substrate according to some embodiments of the present disclosure.
  • Figure 6 is an equivalent circuit diagram of a display pixel circuit according to some embodiments of the present disclosure.
  • Figure 7 is a structural diagram of another display substrate according to some embodiments of the present disclosure.
  • Figure 8 is a structural diagram of another display substrate according to some embodiments of the present disclosure.
  • Figure 9 is a top view of some film layers in a pixel circuit layer according to some embodiments of the present disclosure.
  • Figure 10 is a top view of other film layers in a pixel circuit layer according to some embodiments of the present disclosure.
  • Figure 11 is a top view of some further film layers in a pixel circuit layer according to some embodiments of the present disclosure.
  • Figure 12 is a top view of some further film layers in a pixel circuit layer according to some embodiments of the present disclosure.
  • Figure 13 is a top view of some further film layers in a pixel circuit layer according to some embodiments of the present disclosure.
  • Figure 14 is a structural diagram of further film layers in a pixel circuit layer according to some embodiments of the present disclosure.
  • Figure 15 is a structural diagram of further film layers in a pixel circuit layer according to some embodiments of the present disclosure.
  • Figure 16 is a structural diagram of further film layers in a pixel circuit layer according to some embodiments of the present disclosure.
  • Figure 17 is a schematic diagram of a dark ring appearing on a display substrate in an implementation manner
  • Figure 18 is a partially enlarged view of a display substrate according to some embodiments of the present disclosure.
  • Figure 19 is a partial enlarged view of the display substrate shown in Figure 18;
  • Figure 20 is another partial enlarged view of a display substrate according to some embodiments of the present disclosure.
  • Figure 21 is a partial enlarged view of the display substrate shown in Figure 20;
  • Figure 22 is a partially enlarged view of a display substrate according to some embodiments of the present disclosure.
  • Figure 23 is another partial enlarged view of a display substrate according to some embodiments of the present disclosure.
  • Figure 24 is another partial enlarged view of a display substrate according to some embodiments of the present disclosure.
  • Figure 25 is a structural diagram of another display substrate according to some embodiments of the present disclosure.
  • Figure 26 is another partial enlarged view of a display substrate according to some embodiments of the present disclosure.
  • Figure 27 is a structural diagram of further film layers in a pixel circuit layer according to some embodiments of the present disclosure.
  • Figure 28 is another partial enlarged view of a display substrate according to some embodiments of the present disclosure.
  • Figure 29 is another partial enlarged view of a display substrate according to some embodiments of the present disclosure.
  • Figure 30 is a structural diagram of further film layers in a pixel circuit layer according to some embodiments of the present disclosure.
  • Figure 31 is a structural diagram of further film layers in a pixel circuit layer according to some embodiments of the present disclosure.
  • Figure 32 is a structural diagram of further film layers in a pixel circuit layer according to some embodiments of the present disclosure.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally interpreted to mean “when” or “in response to” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrase “if it is determined" or “if [stated condition or event] is detected” is optionally interpreted to mean “when it is determined" or “in response to the determination" or “on detection of [stated condition or event]” or “in response to detection of [stated condition or event]”.
  • vertical and “equal” include the stated situation and situations that are approximate to the stated situation, and the range of the approximate situation is within an acceptable deviation range, where the acceptable deviation Ranges are as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (ie, the limitations of the measurement system).
  • vertical includes absolute verticality and approximate verticality, wherein the acceptable deviation range of the approximate verticality may also be a deviation within 5°, for example.
  • “Equal” includes absolute equality and approximate equality, wherein the difference between the two that may be equal within the acceptable deviation range of approximately equal is less than or equal to 5% of either one, for example.
  • Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • Some embodiments of the present disclosure provide a display substrate 100 and a display device 1000.
  • the display substrate 100 and the display device 1000 are introduced respectively below.
  • the display device 1000 may be any display device that displays text or images, whether moving (eg, video) or stationary (eg, still images). More specifically, it is contemplated that the display devices of the embodiments may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants, etc.
  • PDA handheld or portable computer
  • GPS receiver/navigator camera
  • MP4 video player video player
  • video camera game console
  • watch clock
  • calculator TV monitor
  • flat panel display computer monitor
  • automotive monitor e.g., odometer display, etc.
  • navigator cockpit controller and/or display
  • display of camera view e.g., display of rear view camera in vehicle
  • electronic photo electronic billboard or sign
  • projector construction Structure
  • packaging and aesthetic structure for example, for the display of an image of a piece of jewelry
  • the above-mentioned display device 1000 includes: a display substrate 100 .
  • the display device 1000 also includes: a frame, a display driver IC (Integrated Circuit), and other electronic accessories.
  • a display driver IC Integrated Circuit
  • the above-mentioned display substrate 100 has a display area A. As shown in FIG. 3 , the display substrate 100 also has a frame area S surrounding the display area A. As shown in FIG.
  • display area A includes a main display area A1 and a secondary display area A2.
  • the main display area A1 surrounds the auxiliary display area A2.
  • This disclosure does not limit the shapes of the display area A and the sub-display area A2, and they can be selected and set according to actual needs.
  • the shape of the display area A may be a rectangle, an approximately rectangle, a circle, an ellipse, etc.
  • the approximate rectangle is a rectangle in a non-strict sense, and its four inner corners may be rounded corners, for example, or a certain side may not be a straight line, for example.
  • the shape of the secondary display area A2 includes any one of a circle, an ellipse, and a polygon.
  • polygons may include quadrilaterals, pentagons or hexagons, etc.
  • the boundary of the sub-display area A2 is composed of smooth lines. From a microscopic perspective, the boundaries of the secondary display area A2 may include smooth lines or jagged lines.
  • the display substrate 100 includes a substrate 10 .
  • the above-mentioned substrate 10 includes a variety of structures, which can be selected and arranged according to actual needs.
  • substrate 10 may be a rigid substrate.
  • the rigid substrate may be, for example, a glass substrate or a PMMA (Polymethyl Methacrylate) substrate.
  • the above-mentioned display substrate 100 may be a rigid display substrate.
  • the substrate 10 may be a flexible substrate.
  • the flexible substrate can be, for example, a PET (Polyethylene Terephthalate, polyethylene terephthalate) substrate, a PEN (Polyethylene Naphthalate Two Formic Acid Glycol Ester, polyethylene naphthalate) substrate or a PI (Polyimide) substrate. , polyimide) substrate.
  • the above-mentioned display substrate 100 may be a flexible display substrate.
  • the display substrate 100 further includes: a pixel circuit layer 20 located on the substrate 10 .
  • the above-mentioned pixel circuit layer 20 includes a plurality of pixel circuits C.
  • the plurality of pixel circuits C may include a plurality of display pixel circuits C1.
  • the plurality of pixel circuits C may also include a plurality of redundant pixel circuits C2.
  • the plurality of redundant pixel circuits C2 please refer to the description below and will not be described again here.
  • the display pixel circuit C1 and the redundant pixel circuit C2 may have the same structure.
  • the display pixel circuit C1 is taken as an example for schematic explanation below.
  • the above-mentioned display pixel circuit C1 includes a variety of structures, which can be selected and set according to actual needs.
  • the structure of the display pixel circuit C1 may include a "2T1C”, “6T1C”, “7T1C”, “6T2C” or “7T2C” structure.
  • T represents a transistor
  • the number in front of “T” represents the number of transistors
  • C represents a storage capacitor
  • the number in front of "C” represents the number of storage capacitors.
  • FIG. 4 and FIG. 5 only illustrate one transistor, and in this disclosure, this transistor represents the display pixel circuit C1.
  • the structure of the display pixel circuit C1 is a "7T1C" structure as an example for explanation.
  • FIG. 6 illustrates an equivalent circuit diagram of the display pixel circuit C1.
  • the display pixel circuit C1 includes: a first reset transistor T1, a second reset transistor T2, a switching transistor T3, a driving transistor T4, a compensation transistor T5, a first light emission control transistor T6, and a second light emission control transistor. T7 and storage capacitor Cst.
  • the gate of the first reset transistor T1 is coupled to the first reset signal line Reset1, the first electrode of the first reset transistor T1 is coupled to the first initial signal line Vinit1, and the first reset transistor T1
  • the second pole is coupled to the fourth node N4.
  • the gate of the second reset transistor T2 is coupled to the second reset signal line Reset2, the first electrode of the second reset transistor T2 is coupled to the second initial signal line Vinit2, and the second electrode of the second reset transistor T2 is coupled to the first node. N1 coupling.
  • the gate of the switching transistor T3 is coupled to the scanning signal line Gate, the first pole of the switching transistor T3 is coupled to the data line Data, and the second pole of the switching transistor T3 is coupled to the second node N2.
  • the gate of the driving transistor T4 is coupled to the fourth node N4, the first electrode of the driving transistor T4 is coupled to the second node N2, and the second electrode of the driving transistor T4 is coupled to the third node N3.
  • the gate of the compensation transistor T5 is coupled to the scanning signal line Gate, the first electrode of the compensation transistor T5 is coupled to the third node N3, and the second electrode of the compensation transistor T5 is coupled to the fourth node N4.
  • the gate of the first light-emitting control transistor T6 is coupled to the enable signal line EM, the first electrode of the first light-emitting control transistor T6 is coupled to the first voltage signal line VDD, and the second electrode of the first light-emitting control transistor T6 is coupled to the first voltage signal line VDD.
  • Two nodes N2 are coupled.
  • the gate of the second light-emitting control transistor T7 is coupled to the enable signal line EM
  • the first electrode of the second light-emitting control transistor T7 is coupled to the third node N3
  • the second electrode of the second light-emitting control transistor T7 is coupled to the first node.
  • the first pole of the storage capacitor Cst is coupled to the fourth node N4, and the second pole of the storage capacitor Cst is coupled to the first voltage signal line VDD.
  • the working process of the display pixel circuit C1 includes a reset phase, a data writing and compensation phase, and a light emitting phase in sequence.
  • the first reset transistor T1 is turned on and transmits the first initial signal provided by the first initial signal line Vinit1 to the fourth Node N4, resets the fourth node N4.
  • the second reset transistor T2 is turned on under the control of the second reset signal provided by the second initial signal line Reset2, and transmits the second initial signal provided by the second initial signal line Vinit2. to the first node N1, and reset the first node N1.
  • the switching transistor T3 and the compensation transistor T5 are turned on under the control of the scanning signal provided by the scanning signal line Gate.
  • the switching transistor T3 transmits the data signal provided by the data line Data to the second node N2, and the driving transistor T4 is transmitted from the second node
  • the data signal of N2 is transmitted to the third node N3.
  • the compensation transistor T5 transmits the data signal from the third node N3 to the fourth node N4, and charges the driving transistor T4 until the compensation of the threshold voltage of the driving transistor T4 is completed.
  • the first light-emitting control transistor T6 and the second light-emitting control transistor T7 are turned on simultaneously under the control of the enable signal provided by the enable signal line EM.
  • the first light emission control transistor T6 transmits the first voltage signal to the second node N2.
  • the driving transistor T4 generates a driving signal (eg, a driving current) according to the first voltage signal from the second node N2 and the data signal from the fourth node N4, and transmits the data signal to the third node N3.
  • the second light emission control transistor T7 transmits the data signal from the third node N3 to the first node N1.
  • the display substrate 100 further includes: a light emitting device layer 30 located on the pixel circuit layer 20 .
  • the light-emitting device layer 30 includes a plurality of light-emitting devices 31 .
  • the above-mentioned light-emitting device 31 may be an OLED (Organic Light Emitting Diode, organic light-emitting diode).
  • the light emitting device 31 includes an anode 311 , a light emitting layer 312 and a cathode 313 .
  • the light-emitting device 31 may further include a hole injection layer and/or a hole transport layer disposed between the anode 311 and the light-emitting layer 312.
  • the light-emitting device 31 may further include an electron transport layer and/or an electron injection layer disposed between the light-emitting layer 312 and the cathode 313 .
  • the plurality of display pixel circuits C1 and the plurality of light-emitting devices 31 may be electrically connected to each other.
  • the electrical connection relationships between the plurality of display pixel circuits C1 and the plurality of light-emitting devices 31 include various types, and can be selected and set according to actual needs.
  • the plurality of display pixel circuits C1 and the plurality of light-emitting devices 31 may be electrically connected in one-to-one correspondence.
  • one display pixel circuit C1 may be coupled to multiple light-emitting devices 31 .
  • multiple display pixel circuits C1 may be coupled to one light emitting device 31.
  • the display pixel circuit C1 can generate a driving current, and each light-emitting device 31 can emit light under the driving action of the driving current generated by the corresponding display pixel circuit C1.
  • the light emitted by the plurality of light-emitting devices 31 cooperates with each other to enable the display substrate 100 to display images.
  • the present disclosure schematically explains the structure of the display substrate 100 by taking a display pixel circuit C1 and a light-emitting device 31 as an example.
  • the plurality of display pixel circuits C1 include a plurality of first display pixel circuits C11 and a plurality of second display pixel circuits C12.
  • the plurality of light-emitting devices 31 include: a plurality of main light-emitting devices 31a located in the main display area A1 and a plurality of secondary light-emitting devices 31b located in the sub-display area A2.
  • the plurality of main light-emitting devices 31a are respectively electrically connected to the plurality of first display pixel circuits C11, and the plurality of secondary light-emitting devices 31b are respectively electrically connected to the plurality of second display pixel circuits C12.
  • the first display pixel circuit C11 can drive the main light-emitting device 31a located in the main display area A1 to emit light
  • the second display pixel circuit C12 can drive the secondary light-emitting device 31b located in the sub-display area A2 to emit light.
  • the plurality of first display pixel circuits C11 are located in the main display area A1, and the plurality of second display pixel circuits C12 are located in an area outside the secondary display area A2.
  • the above-mentioned plurality of second display pixel circuits C12 can be arranged in various ways, and the arrangement can be selected according to actual needs.
  • the plurality of second display pixel circuits C12 are provided in the main display area A1.
  • the plurality of second display pixel circuits C12 are, for example, arranged in multiple rows and multiple columns. At least one column of first display pixel circuits C11 can be disposed between any two adjacent columns of second display pixel circuits C12.
  • the present disclosure may adopt a local compression method to provide the plurality of second display pixel circuits C12 mentioned above. That is, the plurality of second display pixel circuits C12 are disposed in a part of the main display area A1 adjacent to the sub-display area A2, and the first display pixel circuit C11 and the second display pixel circuit located in this part of the area The size of C12 is smaller than the size of the first display pixel circuit C11 located in other areas.
  • the present disclosure may adopt a global compression method to configure the plurality of second display pixel circuits C12 mentioned above. That is, the sizes of the plurality of first display pixel circuits C11 and the plurality of second display pixel circuits C12 included in the display substrate 100 are reduced.
  • the present disclosure does not limit the number of columns of the first display pixel circuit C1 provided between any two adjacent columns of the second display pixel circuit C12, and can be based on actual needs. Make selection settings.
  • the number of columns of the first display pixel circuits C11 provided between any two adjacent columns of the second display pixel circuits C12 may be 1 column, 2 columns, 4 columns, etc.
  • the plurality of second display pixel circuits C12 are provided in the frame area S. 8 only illustrates part of the second display pixel circuit C12 and does not limit the number of the second display pixel circuit C12 located in the frame area S.
  • the area for disposing the first display pixel circuit C11 in the main display area A1 can be increased, and more first display pixel circuits C11 can be disposed in the main display area A1 to increase the pixel density of the display substrate 100 .
  • the plurality of display pixel circuits C1 included in the display substrate 100 are located in the area outside the sub-display area A2, and the multiple light-emitting devices 31 included in the display substrate 100 are located in the display area A.
  • the material of the partial structure of the display pixel circuit C1 includes metal materials. Metal materials have low light transmittance and have a high blocking effect on light.
  • the display substrate 100 can not only achieve full-screen display, but also can When external light is incident on the part of the display substrate 100 located in the sub-display area A2, the second display pixel circuit C12 can be prevented from blocking the external light, so that the external light can pass between any two adjacent sub-light-emitting devices 31b. The light is emitted from the gap, so that the part of the display substrate 100 located in the sub-display area A2 has a higher light transmittance.
  • the display substrate 100 further includes: a transfer layer located between the pixel circuit layer 20 and the light emitting device layer 30 .
  • the transfer layer includes a plurality of wires 41, one end of each wire 41 is electrically connected to the second display pixel circuit C12, and the other end is electrically connected to the sub-light-emitting device 31b. That is, each second display pixel circuit C12 is electrically connected to the corresponding sub-light-emitting device 31b through the wire 41.
  • the material of the wire 41 includes a light-transmissive conductive material, such as ITO (Indium Tin Oxide). This can avoid affecting the light transmittance of the portion of the display substrate 100 located in the sub-display area A2.
  • a light-transmissive conductive material such as ITO (Indium Tin Oxide). This can avoid affecting the light transmittance of the portion of the display substrate 100 located in the sub-display area A2.
  • the display device 1000 further includes: an optical element 200 disposed on the non-light-emitting side of the display substrate 100 , and the optical element 200 is located in the secondary display area A2 of the display substrate 100 .
  • the light-emitting side refers to the side of the display substrate 100 that can display images.
  • the non-light emitting side refers to the side of the display substrate 100 opposite to the light emitting side.
  • the non-light emitting side refers to the side of the substrate 10 away from the light emitting device layer 30 .
  • the above-mentioned optical element 200 includes: a camera, an infrared sensor or a fingerprint sensor, etc.
  • This disclosure takes the optical element 200 as a camera as an example.
  • the display pixel circuit C1 is not provided in the part of the display substrate 100 located in the secondary display area A2, the display pixel circuit C1 can be prevented from blocking external light, and the external light can pass through the display substrate. 100 is located in the sub-display area A2. In this way, the camera can collect the light and realize the function of taking pictures.
  • the portion of the display substrate 100 located in the sub-display area A2 can also display, so that the entire display substrate 100 can display images, achieving full-screen display.
  • the sub-display area A2 of the display substrate 100 includes an element setting area A21 and a transition area A22 surrounding the element setting area A21.
  • the transition area A22 is closer to the main display area A1 than the component setting area A21.
  • the viewing angle of the optical element 200 may at least partially overlap the orthographic projection of the optical element 200 on the display substrate 100 with the element placement area A21 of the display substrate 100 . That is, the optical element 200 may be disposed within the element setting area A21, or there may be some misalignment between the optical element 200 and the element setting area A21. This is beneficial to improving the working performance of the optical element 200.
  • the pixel circuit layer 20 includes an active layer 21 and a multi-layer inorganic insulating material 22 disposed on a side of the active layer 21 away from the substrate 10 .
  • the above-mentioned multi-layer inorganic insulating material 22 includes, for example: a first gate insulating layer 221 , a second gate insulating layer 222 and an interlayer dielectric layer 223 that are sequentially stacked in a direction away from the substrate 10 .
  • the pixel circuit layer 20 further includes a first gate conductive layer 23 located between the first gate insulating layer 221 and the second gate insulating layer 222 , and a second gate layer 23 located between the second gate insulating layer 222 and the interlayer dielectric layer 223 .
  • the conductive layer 26 and the source-drain conductive layer 24 located on the side of the interlayer dielectric layer 223 away from the substrate 10 .
  • the material of the active layer 21 may be LTPS (Low Temperature Poly Silicon) or metal oxide.
  • the metal oxide may be IGZO (Indium Gallium Zinc Oxide). This disclosure takes the material of the active layer 21 as LTPS as an example for schematic explanation.
  • the present disclosure can use chemical vapor deposition (Chemical Vapor Deposition, referred to as CVD) method or plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, referred to as PECVD) method to prepare the LTPS film layer, and then undergo subsequent processes (such as etching process) to pattern the LTPS film layer to form the active layer 21.
  • CVD chemical Vapor Deposition
  • PECVD plasma enhanced chemical vapor deposition
  • the materials of the first gate insulating layer 221 and the second gate insulating layer 222 are both inorganic materials.
  • the inorganic material may be at least one of silicon nitride, silicon oxide, and silicon oxynitride. Among them, the thickness of the first gate insulating layer 221 and the second gate insulating layer 222 is relatively uniform.
  • the material of the interlayer dielectric layer 223 is an inorganic material.
  • the inorganic material may be at least one of silicon nitride, silicon oxide, and silicon oxynitride.
  • FIG. 9 illustrates a top view structure of the active layer 21
  • FIG. 10 illustrates a top view structure of the first gate conductive layer 23
  • FIG. 11 illustrates a top view structure of the second gate conductive layer 26
  • FIG. 12 illustrates a top view structure of the via hole of the interlayer dielectric layer 223
  • FIG. 13 illustrates a top view structure of the source-drain conductive layer 24 .
  • the material of the interlayer dielectric layer 223 is a light-transmissive material. Therefore, FIG. 12 only illustrates the positions of the via holes (for example, including the third via hole G3 ) in the interlayer dielectric layer 223 .
  • the orthographic projection of the active layer 21 on the substrate 10 overlaps with the orthographic projection of the first gate conductive layer 23 and the second gate conductive layer 26 on the substrate 10 .
  • the first gate conductive layer 23 and the second gate conductive layer 26 can be used as masks.
  • the source layer 21 is doped, so that the portion of the active layer 21 covered by the first gate conductive layer 23 and the second gate conductive layer 26 constitutes the active pattern of each transistor in the display pixel circuit C1, so that the active layer 21
  • the portion not covered by the first gate conductive layer 23 and the second gate conductive layer 26 constitutes a conductor.
  • the overlapping portions of the first gate conductive layer 23 or the second gate conductive layer 26 and the active layer 21 constitute the gate electrodes of each transistor in the display pixel circuit C1.
  • the portion of the second gate conductive layer 26 that overlaps the first gate conductive layer 23 is, for example, a storage capacitor in the display pixel circuit C1.
  • the display substrate 100 further includes a plurality of third via holes G3.
  • each third via hole G3 penetrates the above-mentioned multi-layer inorganic insulation layer 22 to a side surface of the active layer 21 away from the substrate 10 .
  • the plurality of third via holes G3 are located at least in the main display area A1.
  • the source-drain conductive layer 24 includes a plurality of source-drain conductive patterns.
  • the plurality of third via holes G3 can expose doped portions of the active layer 21 , so that part of the source and drain conductive patterns can pass through the third via holes G3 and the active layer 21 The doped portion forms an electrical contact, thereby constituting the source or drain of each transistor in the display pixel circuit C1.
  • the display pixel circuit C1 included in the display substrate 100 is located at least in the main display area A1, the above-mentioned active layer 21 is at least located in the main display area A1.
  • the active layer 21 is located in the main display area A1, or the active layer 21 is located in the main display area A1 and the auxiliary display area A2.
  • the area where the first gate conductive layer 23 , the second gate conductive layer 26 and the source-drain conductive layer 24 are located is basically consistent with the area where the active layer 21 is located.
  • the active layer in the process of preparing the active layer included in the pixel circuit layer, the active layer usually contains a large amount of hydrogen, and the hydrogen contained in the active layer will affect the subsequent formation of the display pixel circuit layer.
  • the device characteristics of each transistor especially the driving transistor, therefore, it is generally necessary to perform a dehydrogenation treatment on the active layer during the preparation of the pixel circuit layer to remove the hydrogen contained in the active layer.
  • the active layer may be heat treated to allow hydrogen contained in the active layer to escape.
  • the overflowing hydrogen can, for example, overflow through the third via hole corresponding to the active layer, which can slow down the overflow speed of hydrogen and avoid the accumulation of high concentration of hydrogen in a short time in the space where the active layer is located, thereby avoiding the generation of hydrogen. Explosive problem.
  • the hydrogen contained in the portion of the active layer adjacent to the sub-display area can pass through the third via hole directly opposite to it, or through the The third via hole adjacent to and away from the secondary display area overflows, and the portion of the active layer located in other areas can also overflow through the third via hole adjacent to it and close to the secondary display area.
  • the parts of the active layer adjacent to the sub-display area include fewer hydrogen overflow paths than other parts. This will cause the active layer to be different from the sub-display area.
  • the dehydrogenation amount of the adjacent part and the dehydrogenation amount of other parts, which causes the threshold voltage of the transistor in the subsequently formed part of the display pixel circuit C1 adjacent to the sub-display area to have a positive drift (referred to as positive). bias), the threshold voltage of these transistors is in the range of forward bias, for example, 0.1V to 1.2V.
  • L64 indicates that the luminous brightness of the light-emitting device is 64 gray levels
  • L128 indicates that the luminous brightness of the light-emitting device is 128 gray levels
  • L255 indicates that the luminous brightness of the light-emitting device is 255 gray levels.
  • the driving current variation ⁇ I represents the driving current transmitted by the display pixel circuit to the corresponding light-emitting device after the threshold voltage of the transistor of the display pixel circuit is forward-biased, and the driving current transmitted by the display pixel circuit when the threshold voltage of the transistor of the display pixel circuit does not drift. The difference between the driving currents to the corresponding light-emitting devices.
  • the percentage change of the driving current represents the percentage of the change of the driving current accounting for the driving current transmitted by the display pixel circuit to the corresponding light-emitting device when the threshold voltage of the transistor of the display pixel circuit does not drift. It can be used to represent the proportion of the driving current transmitted by the display pixel circuit to the corresponding light-emitting device. Differences in device drive current.
  • the human eye can detect changes in luminous brightness.
  • Table 1 at 64 gray levels, when the threshold voltage is biased forward by 0.1V, the change difference in driving current reaches 2.1% (more than 2%); at 128 gray levels, when the threshold voltage is biased forward by 0.2V Under 255 gray scale, when the threshold voltage is biased forward by 0.4V, the variation in driving current reaches 2.3% (greater than 2%).
  • the driving current transmitted to the corresponding light-emitting device from the display pixel circuit adjacent to the sub-display area will change, thereby causing the light-emitting device to change.
  • the luminous brightness of the LED and the luminous brightness of other light-emitting devices resulting in a display dark ring around the secondary display area (as shown in Figure 15), and the dark ring can be observed by the human eye, which affects the display substrate and display The display effect of the device.
  • the display substrate 100 further includes a plurality of first via holes G1 .
  • the plurality of first via holes G1 penetrate at least one layer of the above-mentioned multi-layer inorganic insulation layer 22 .
  • the film layers penetrated by each first via hole G1 may be the same or different.
  • FIG. 14 and FIG. 15 illustrate the active layer 21 in the pixel circuit layer 20 and the first gate insulating layer 221, the second gate insulating layer 222 and the interlayer dielectric layer in the above-mentioned multi-layer inorganic insulating layer 22. 223Local structure after stacking setup.
  • a part of the first via holes G1 among the plurality of first via holes G1 penetrates the interlayer dielectric layer 223 , and the depth of this part of the first via holes G1 is, for example, equal to the thickness of the interlayer dielectric layer 223 .
  • a part of the first via hole G1 penetrates the interlayer dielectric layer 223, the second gate insulating layer 222 and the first gate insulating layer 221.
  • the depth of this part of the first via hole G1 is, for example, the same as the interlayer dielectric layer 223 and the second gate insulating layer 222. is equal to the sum of the thicknesses of the first gate insulating layer 221 .
  • the plurality of first via holes G1 all penetrate the interlayer dielectric layer 223 , the second gate insulating layer 222 and the first gate insulating layer 221 .
  • each first via hole G1 and the first gate conductive layer 23 and the second gate conductive layer 26 are arranged in a staggered manner.
  • the plurality of first via holes G1 are located at least in the transition area A22.
  • the plurality of first via holes G1 mentioned above may be located in the entire transition area A22.
  • part of the plurality of first via holes G1 is located in the transition area A22, and another part is located in the component placement area A21.
  • some of the first via holes G1 may also be located in the main display area A1.
  • the present disclosure is schematically illustrated by taking the plurality of first via holes G1 located in the sub-display area A2 and at least in the transition area A22 as an example.
  • FIG. 18 is a partial enlarged view of the display substrate 100
  • FIG. 19 is a partial enlarged view of the display substrate 100 shown in FIG. 18 .
  • the plurality of first via holes G1 mentioned above may all be located in the transition area A22.
  • FIG. 20 is another partial enlarged view of the display substrate 100
  • FIG. 21 is another partial enlarged view of the display substrate 100 shown in FIG. 20 .
  • part of the plurality of first via holes G1 is located in the transition area A22, and another part of the plurality of first via holes G1 is located in the component placement area A21.
  • the via hole located in the main display area A1 (that is, the via hole G1) can be reduced.
  • the hydrogen contained in the portion of the active layer 21 adjacent to the sub-display area A2 can not only pass through the third via hole facing it G3 or the third via hole G3 adjacent to it and far away from the sub-display area A2 overflows, and can also overflow through the first via hole G1 located in the sub-display area A2.
  • the portion of the active layer 21 adjacent to the sub-display area A2 has a similar number of hydrogen overflow pathways compared to other portions, thereby increasing the dehydrogenation of the portion of the active layer 21 adjacent to the sub-display area A2.
  • the driving currents transmitted by the display pixel circuit C1 to the corresponding light-emitting devices 31 are basically equal, reducing the difference in the driving currents transmitted by the display pixel circuit C1 at different positions to the corresponding light-emitting devices 31, thereby causing the light-emitting devices 31 at different positions to emit
  • the brightness of the light is nearly consistent, which slows down or even eliminates the dark ring phenomenon appearing on the display screen of the display substrate 100 and the display device 1000 , and improves the uniformity of the display screen.
  • the active layer 2 can be During the dehydrogenation process, the hydrogen contained in the portion of the active layer 21 adjacent to the sub-display area A2 can not only pass through the third via hole G3 directly opposite it or the adjacent one and away from the sub-display area A2
  • the third via hole G3 overflows, and can also overflow through at least the first via hole G1 located in the transition area A22.
  • the present disclosure increases the overflow path of hydrogen contained in the portion of the active layer 21 adjacent to the sub-display area A2, and can increase the escape path of the hydrogen contained in the portion of the active layer 21 adjacent to the sub-display area A2.
  • the amount of hydrogen makes the dehydrogenation amount of the part adjacent to the sub-display area A2 in the active layer 21 nearly consistent with the dehydrogenation amount of other parts, thereby avoiding the subsequent formation of display pixel circuits in the area adjacent to the sub-display area A2
  • the threshold voltage of the transistor C1 is forward-biased, thereby making the brightness of the light emitted by the light-emitting devices 31 at different positions close to the same, slowing down or even eliminating the dark ring phenomenon in the display screen of the display substrate 100 and the display device 1000, and improving the display screen. of uniformity.
  • This disclosure does not limit the distribution of the first via holes G1 in the sub-display area A2, and can be selected and set according to actual needs.
  • the sub-display area A2 includes a first unit area area a and a second unit area area b.
  • the boundary between the first unit area area a and the sub-display area A2 is The distance is greater than the distance between the second unit area area b and the boundary of the sub-display area A2.
  • the shape of the boundary of the sub-display area A2 and the boundary of the component placement area A21 are basically the same.
  • at least part of the boundary of the auxiliary display area A2 may be in a polygonal or zigzag shape, and the part of the boundary in the polygonal or zigzag shape will be inconsistent with the boundary of the device setting area A21.
  • Regular areas (such as triangular-like areas shown in Figures 19 and 21 to 23).
  • the distance between the boundary of the first unit area area a and the auxiliary display area A2 can be understood as the distance between the first unit area area a and the auxiliary display area A2 passing through the center of the component setting area A21 and pointing in the direction of the auxiliary display area A2 The spacing between borders.
  • the distance between the boundary of the second unit area area b and the auxiliary display area A2 can be understood as the distance between the second unit area area b and the auxiliary display area A2 through the center of the component setting area A21 and pointing in the direction of the auxiliary display area A2 The spacing between borders.
  • This disclosure does not limit the specific positions of the first unit area area a and the second unit area area b in the sub-display area A2. As long as the distance between the boundary of the first unit area area a and the sub-display area A2 is greater than In the case of the distance between the boundary of the second unit area area b and the sub-display area A2, it can be selected and set according to actual needs.
  • both areas are 1, and the area units of both are the same.
  • the unit areas of both units can be set according to actual needs.
  • the area units of both units are square micrometers ( ⁇ m 2 ).
  • both the area of the first unit area area a and the area of the second unit area area b are smaller than the area of the secondary display area A2.
  • L represents a line passing through the center of the component setting area A21
  • the extending direction of L is a direction passing through the center of the component setting area A21 and pointing toward the boundary of the sub-display area A2
  • L passes through a first unit area area a and a second unit area area b.
  • the distance between the boundary of the first unit area area a and the boundary of the sub-display area A2 is ⁇ h1.
  • the distance between the boundary and the boundary of the sub-display area A2 is ⁇ h2, where ⁇ h1> ⁇ h2.
  • the distribution density of the first via holes G1 mentioned in this disclosure refers to the sum of the orthographic projection areas of each first via hole G1 provided in a certain area on the substrate 10, and the The ratio between the orthographic projected areas of the areas on the substrate 10.
  • the number of the first via holes G1 provided per unit area in a certain area can reflect the distribution density of the first via holes G1.
  • the smaller the number of first via holes G1 provided in the unit area area the smaller the distribution density of the first via holes G1 is, and the larger the number of first via holes G1 provided in the unit area area, the first The distribution density of via G1 is larger.
  • the distribution density of the first via holes G1 located in the first unit area area a is less than or equal to the distribution density of the first via holes G1 located in the second unit area area b. . That is, the area ratio of the first via hole G1 located in the first unit area area a is less than or equal to the area ratio of the first via hole G1 located in the second unit area area b.
  • the number of first via holes G1 located in the first unit area area a is less than or equal to the number of first via holes G1 located in the second unit area area b. quantity.
  • the portion of the first via hole G1 closest to the sub-display area A2 has the highest distribution density. As the distance from the boundary of the sub-display area A2 increases, the distribution density of the first via hole G1 gradually decreases. The distribution density of the first via hole G1 may decrease linearly or in stages. Small.
  • the drift of the threshold voltage of the transistor in the display pixel circuit C1 has a transitional nature, that is, as the distance from the boundary of the sub-display area A2 increases, the drift amount of the threshold voltage of the transistor in the display pixel circuit C1 gradually increases. decrease.
  • the distribution density of the first via holes G1 so that the distribution density of the first via holes G1 is the largest in the part closest to the secondary display area A2
  • the hydrogen contained in the active layer 21 effectively reduces the threshold voltage drift of the transistors close to the boundary of the sub-display area A2 and improves the dark ring phenomenon.
  • the distribution density of the first via holes G1 in at least two first unit area areas a is the same as the spacing between the boundaries of the sub-display area A2. And/or, the distribution density of the first via holes G1 in at least two second unit area areas b is the same as the spacing between the boundaries of the sub-display area A2.
  • the distribution density of the first via holes G1 in multiple first unit area areas a is the same as the spacing between the boundaries of the sub-display area A2. That is, the distribution density of the first via holes G1 in different first unit area areas a is the same.
  • the area ratio of one via G1 is the same.
  • the distribution density of the first via holes G1 in the plurality of second unit area areas b is the same as that between the boundaries of the sub-display area A2, that is, the first via holes G1 in different second unit area areas b are The area ratio of via G1 is the same.
  • the distribution density of the first via holes G1 in a circle area with the same spacing between the boundaries of the sub-display area A2 is the same, so that the distribution density of the first via holes G1 in the active layer 21 adjacent to the sub-display area A2 can be the same.
  • Parts have substantially the same number of hydrogen overflow paths at the same distance from the sub-display area A2.
  • the distribution density of the first via holes G1 in the plurality of first unit area areas a is the same as the spacing between the boundaries of the sub-display area A2, and is the same as the spacing between the boundaries of the sub-display area A2.
  • the distribution density of the first via holes G1 in the plurality of second unit area regions b is the same.
  • the distribution density of the first via holes G1 in any circle area with the same distance as the boundary of the sub-display area A2 is the same, and the farther the distance from the boundary of the sub-display area A2 , the smaller the distribution density of the first via hole G1 in this circle area. This allows the portion of the active layer 21 adjacent to the sub-display area A2 to have the same number of hydrogen overflow paths in any area that is the same distance from the sub-display area A2.
  • the amount of hydrogen overflowing in the part of the active layer 21 surrounding the sub-display area A2 can be basically the same, and thus the improvement effect on the threshold voltage of different transistors surrounding the sub-display area A2 can be basically the same, avoiding the occurrence of the sub-display area
  • the non-uniform dark ring phenomenon around A2 (for example, in different areas above, below, left and right of the sub-display area A2) further improves the uniformity of the display images of the display substrate 100 and the display device 1000.
  • the first via holes G1 located in the secondary display area A2 are evenly distributed.
  • the distance between any two adjacent first via holes G1 is equal.
  • the plurality of first via holes G1 are located in the transition area A22. Wherein, at least some of the first via holes G1 among the plurality of first via holes G1 are arranged sequentially along the boundary of the component setting area A21 and arranged in a ring shape.
  • the amount can also reduce the layout difficulty of the first via G1 and the preparation difficulty of the display substrate 100 .
  • some of the first via holes G1 are located in the transition area A22 , and the other part of the first via holes G1 are located in the component setting area A21 .
  • the area where the first via hole G1 is provided is not limited to the transition area A22 close to the sub-display A2.
  • part of the first via hole G1 located in the component setting area A21 is located, for example, in a partial area close to the boundary of the transition area A22.
  • the first via hole G1 By arranging the first via hole G1 in both the transition region A22 and the component setting area A21, not only the area available for arranging the first via hole G1 can be increased, but also the number of the arrangable first via hole G1 can be greatly increased. This allows the hydrogen contained in the portion of the active layer 21 adjacent to the sub-display area A2 to have more escape paths, thereby more fully removing hydrogen contained in the portion of the active layer 21 adjacent to the sub-display area A2. Hydrogen to ensure good dehydrogenation effect.
  • the minimum size of the area occupied in the area A21 is greater than or equal to the size of one pixel circuit C.
  • the size of the area occupied by the other part of the plurality of first via holes G1 in the component setting area A21 refers, for example, to the direction passing through the center of the component setting area A21 and pointing to the boundary of the transition area A22. size.
  • the size of the pixel circuit C refers to, for example, the lateral size, vertical size or average size of the pixel circuit C.
  • the size of the pixel circuit C can be selected and set according to actual needs.
  • the above minimum size may be equal to the size of one pixel circuit C, the size of two pixel circuits C, or the size of four pixel circuits C.
  • the size of one pixel circuit C is about 64 ⁇ m.
  • this part of the first via hole G1 can be positioned away from the active layer 21 and adjacent to the sub-display area A2.
  • the distance between the adjacent parts is relatively close, which is beneficial to reducing the moving distance of hydrogen during the dehydrogenation process of the active layer 21, and thus is beneficial to the sufficient removal of hydrogen.
  • the minimum size of the area occupied by another part of the plurality of first via holes G1 in the element setting area A21 greater than or equal to the size of one pixel circuit C it is possible to make the area in the active layer 21 adjacent to the sub-display area A2
  • the hydrogen contained in the part has more overflow paths, which is conducive to the sufficient removal of hydrogen, which is conducive to more fully reducing the drift amount of the threshold voltage of the transistor of the display pixel circuit C1 close to the sub-display area A2, which is conducive to further Improve the dark ring phenomenon.
  • the sizes at different positions are equal.
  • the area occupied by another part of the plurality of first via holes G1 in the component placement area A21 is annular.
  • the distribution density of the first via holes G1 located in the transition area A22 is the same as the distribution density of the first via holes G1 located in the component placement area A21. That is, the area ratio of the first via hole G1 located in the transition area A22 is the same as the area ratio of the first via hole G1 located in the component placement area A21.
  • the spacing between two adjacent first via holes G1 located in the transition area A22 which is the same as the spacing between two adjacent first via holes G1 located in the component setting area A21.
  • the plurality of first via holes G1 can be evenly distributed in the sub-display area A2, which is conducive to providing a uniform hydrogen overflow environment for the portion of the active layer 21 adjacent to the sub-display area A2, and is conducive to making the active layer Different parts of 21 have similar dehydrogenation amounts, so that the threshold voltages of the transistors of the display pixel circuit C1 at different positions are basically the same.
  • the positional relationship between the first via hole G1 and the sub-light-emitting device 31b includes a variety of positions, and can be selected and set according to actual needs.
  • the orthographic projection of part of the first via hole G1 located in the component setting area A21 on the substrate 10 does not overlap with the orthographic projection of the sub-light emitting device 31b on the substrate 10 .
  • part of the first via hole G1 located in the component setting area A21 is staggered from the sub-light-emitting device 31b. This is beneficial to improving the structural stability of the sub-light emitting device 31b.
  • the orthographic projection of part of the first via holes G1 on the substrate 10 is located within the orthographic projection range of the sub-light emitting device 31 b on the substrate 10 . That is, this part of the first via hole G1 will be located below the sub-light emitting device 31b.
  • no redundant semiconductor pattern 21 a is provided between at least one first via hole G1 and the substrate 10 .
  • the redundant semiconductor pattern 21a please refer to the description below and will not be described again here.
  • the aperture of the first via hole G1, and the first via hole G1 and the sub-display area A2 are The spacing between the boundaries of display area A2 is negatively correlated.
  • the aperture of the first via hole G1 that is closer to the boundary of the sub-display area A2 is larger, and the aperture of the first via hole G1 that is further from the boundary of the sub-display area A2 is smaller.
  • the aperture diameter of the first via hole G1 slowing shrieking.
  • the diameter of the first via hole G1 may be reduced linearly or may be reduced stepwise.
  • the area with a large hydrogen content can be made to correspond to a larger aperture, and the area with a small hydrogen content can be made to correspond to a larger aperture. Corresponding to a smaller aperture, this is conducive to sufficient overflow of hydrogen, thereby achieving a sufficient dehydrogenation effect and achieving a good improvement effect on the threshold voltage of the transistor in the display pixel circuit C1.
  • the distribution density of the first via hole G1 ranges from 1% to 14%.
  • the above-mentioned distribution density is the ratio of the sum of the orthogonal projected areas of the plurality of first via holes G1 on the substrate 10 to the area occupied by the plurality of first via holes G1.
  • the distribution density of the first via G1 may be: 1%, 3%, 5%, 8%, 11% or 14%, etc.
  • the first via holes G1 may be most densely arranged. At this time, both the dehydrogenation effect on the portion of the active layer 21 adjacent to the sub-display area A2 and the structural stability of the interlayer dielectric layer 223 can be ensured.
  • the distribution density of the first via holes G1 located in the first unit area area a is less than or equal to the distribution density of the first via holes G1 located in the second unit area area b, along with the secondary display As the spacing between the boundaries of the area A2 increases, the distribution density of the first via hole G1 can gradually decrease from 14% to 1%.
  • the distribution density of the first via hole G1 may be gradually reduced in the order of 14%, 12%, 10%, 8%, 6%, 4%, 2%, and 1%.
  • the distribution density of the first via hole G1 may be gradually reduced in the order of 14%, 12%, 10%, 10%, 6%, 6%, 2%, and 1%.
  • the distribution density of the first via G1 located in the transition area A22 is the same as the distribution density of the first via G1 located in the component setting area A21, the distribution density of the first via G1 may be: 1%, 3%, 5%, 8%, 11% or 14% etc.
  • the distribution density of the third via hole G3 located in the main display area A1 is the same as the distribution density of the first via hole G1 located in the secondary display area A2.
  • the third via hole G3 can expose the doped portion of the active layer 21 , after the source-drain conductive layer 24 is subsequently formed, the portion of the source-drain conductive layer 24 can be exposed.
  • the source-drain conductive pattern forms electrical contact with the active layer 21 through the third via hole G3 to form a transistor. Therefore, the distribution density of the third via hole G3 in the main display area A1 is mainly related to the pixel circuit C included in the display substrate 100 related to the number of transistors. The greater the number of transistors included in the display substrate 100, the greater the distribution density of the third via hole G3 in the main display area A1.
  • the portion of the active layer 21 adjacent to the secondary display area A2 can be The other parts are in a relatively uniform environment, so that the hydrogen contained in the active layer 21 located at different locations has a similar number of escape paths, thereby ensuring that the amount of hydrogen removed by the active layer 21 at different locations is relatively similar.
  • This can avoid large differences between the threshold voltages of transistors formed at different positions, so that the driving currents transmitted from the pixel circuits at different positions to the corresponding light-emitting devices are basically equal, and avoid the appearance of the display screen of the display substrate 100 Dark ring problem caused by differences in drive current.
  • the distribution density of the third via hole G3 located in the main display area A1 is smaller than the distribution density of the first via hole G1 located in the secondary display area A2.
  • the distribution density of the first via holes G1 in the transition area A22 can be arranged according to the maximum density that can be achieved in the relevant process, so as to ensure that the active layer 21 is adjacent to the boundary of the sub-display area A2.
  • Part of the hydrogen contained in the transition area A22 has a sufficient overflow path to ensure that the portion of the active layer 21 adjacent to the boundary of the sub-display area A2 has a better dehydrogenation effect, so that the active layer 21 is The amount of hydrogen removal at different positions is basically consistent.
  • the distribution density of the first via G1 in the transition area A22 is 14%.
  • a plurality of pixel circuits C (such as display pixel circuits C1) included in the display substrate 100 are arranged in multiple rows and multiple columns.
  • pixel circuits C such as display pixel circuits C1
  • each row of pixel circuits C there are two pixel circuits C located on opposite sides of the sub-display area A2, and relative to other pixel circuits C Closer to the sub-display area A2; in each column of pixel circuits C, there are two pixel circuits C located on opposite sides of the sub-display area A2, and are closer to the sub-display area A2 than other pixel circuits C.
  • the dotted circles in Figure 26 can be used to represent the pixel circuits C closest to the boundary of the sub-display area A2 among the multiple rows and columns of pixel circuits C surrounding the sub-display area A2, or they can be It is used to represent the driving transistor T4 of each pixel circuit C closest to the boundary of the sub-display area A2.
  • the minimum spacing between each driving transistor T4 closest to the boundary of the sub-display area A2 and the sub-display area A2 is the same.
  • the active pattern included in each driving transistor T4 closest to the boundary of the sub-display area A2 is the same as the minimum spacing between the sub-display area A2 and the sub-display area A2.
  • the pixel circuit C closest to the boundary of the sub-display area A2 refers to the display pixel circuit C1.
  • the pixel circuit C closest to the boundary of the sub-display area A2 refers to the display pixel circuit C1.
  • the above display pixel circuit C1 can generate a driving current through the driving transistor T4 to drive the light emitting device 31 to emit light.
  • the threshold voltage of the driving transistor T4 is related to the driving current provided to the light-emitting device 31 , and the driving current is related to the brightness of the light emitted by the light-emitting device 31 .
  • an external optical compensation (demura) method can generally be used to compensate for the brightness difference between different light-emitting devices 31 .
  • the key step in the demura method is to use the demura algorithm to process the brightness data of the light emitted by different light-emitting devices 31, thereby generating the compensation data required by the different light-emitting devices 31 to compensate for the difference in brightness of the light emitted by the different light-emitting devices 31. The difference between them improves the unevenness of the display screen.
  • the demura method can be used to compensate for the brightness of the light emitted by the light-emitting device 31 located near the boundary of the sub-display area A2, so that the light emitted by this part of the light-emitting device 31 The brightness is close to the brightness of the light emitted by other parts of the light-emitting devices 31, thereby eliminating the dark ring phenomenon.
  • the active pattern included in each driving transistor T4 can be made consistent with the sub-display area A2
  • the minimum spacing between them is basically the same. Therefore, in the process of dehydrogenating the active patterns of each driving transistor T4, the distribution of the first vias G1 faced by the active patterns of each driving transistor T4 can be made basically the same, so that the Therefore, the amount of hydrogen removal in the active patterns of each driving transistor T4 is substantially the same. In this way, even if the threshold voltage of the driving transistor T4 at different positions surrounding the sub-display area A2 drifts, the corresponding drift value is basically the same.
  • the effect of the demura algorithm on different light-emitting devices can be reduced 31
  • the difficulty of processing the brightness data of the emitted light makes it easy to accurately generate the compensation data required by different light-emitting devices 31, thereby helping to eliminate dark rings and improve the uniformity of the display screen.
  • the pixel circuit layer 20 also includes a plurality of redundant semiconductor patterns 21 a located in the secondary display area A2 , and the plurality of redundant semiconductor patterns 21 a are in the same layer as the active layer 21 set up.
  • the "same layer” mentioned in this article refers to a layer structure formed by using the same film formation process to form a film layer for forming a specific pattern, and then using the same mask to form a patterning process.
  • a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights. Or have different thicknesses.
  • the plurality of redundant semiconductor patterns 21 a and the active layer 21 can be formed simultaneously in one patterning process, which is beneficial to simplifying the preparation process of the display substrate 100 .
  • the material of the plurality of redundant semiconductor patterns 21a and the active layer 21 are the same.
  • the display substrate 100 further includes a plurality of second via holes G2 located in the secondary display area A2.
  • Each second via hole G2 penetrates at least one layer of the above-mentioned multi-layer inorganic insulation layer 22 .
  • the structure of the second via hole G2 is the same as the structure of the first via hole G1.
  • the plurality of second vias G2 penetrate through the interlayer dielectric layer 223 , the second gate insulating layer 222 and the first gate insulating layer 221 to the redundant semiconductor pattern 21 a away from the substrate.
  • the second via hole G2 exposes part of the surface of the redundant semiconductor pattern 21a.
  • the orthographic projection of the plurality of second via holes G2 on the substrate 10 is located within the orthographic projection range of the redundant semiconductor pattern 21 a on the substrate 10 .
  • each second via hole G2 and the first gate conductive layer 23 and the second gate conductive layer 26 are arranged in a staggered manner.
  • the plurality of second via holes G2 may be located in the transition area A22 or in the component placement area A21. Among them, the part of the second via hole G2 located in the transition area A22 may be called the first via hole G1.
  • the redundant semiconductor pattern 21 a on the substrate 10 The orthographic projection does not overlap with the orthographic projection of any of the first gate conductive layer 23 , the second gate conductive layer 26 , and the source-drain conductive layer 24 on the substrate 10 .
  • the redundant semiconductor pattern 21a is provided independently and does not constitute a part of the transistor.
  • the sub-light emitting device 31 b is located on a side of the redundant semiconductor pattern 21 a away from the substrate 10 , and the two are insulated from each other.
  • the orthographic projection of at least part of the redundant semiconductor pattern 21 a on the substrate 10 is located within the orthographic projection range of the sub-light emitting device 31 b on the substrate 10 .
  • the orthographic projection of all redundant semiconductor patterns 21 a on the substrate 10 is located within the orthographic projection range of the sub-light emitting device 31 b on the substrate 10 .
  • the front projection of a part of the redundant semiconductor pattern 21a on the substrate 10 is located within the front projection range of the secondary light-emitting device 31b on the substrate 10, and the front projection and secondary projection of the other part of the redundant semiconductor pattern 21a on the substrate 10 are
  • the orthographic projection of the light emitting device 31b on the substrate 10 has no overlap.
  • the second via hole G2 corresponding to the partial redundant semiconductor pattern 21a that does not overlap with the orthographic projection of the sub-light emitting device 31b on the substrate 10 can be called the first via hole G1.
  • the distribution density of a portion of the first via holes G1 close to the boundary of the component placement area A21 is greater than or equal to the distribution density of the second via holes G2 .
  • the hydrogen contained in the part of the active layer 21 adjacent to the sub-display area A2 can also overflow through the plurality of second via holes G2 during the dehydrogenation process, thereby further increasing the density of this part of the active layer 21
  • the hydrogen overflow pathway is beneficial to increase the hydrogen removal efficiency.
  • the distribution density of the first via holes G1 located in the first unit area area a is less than or equal to the distribution density of the first via holes G1 located in the second unit area area b
  • the distribution density of the first via holes G1 gradually decreases, and the distribution density of the first via holes G1 near the boundary of the component setting area A21 decreases to or approaches the second via hole G1.
  • the pixel circuit layer 20 also includes a plurality of redundant pixel circuits C2.
  • the plurality of redundant pixel circuits C2 are located in the main display area A1 and are located in the plurality of display pixel circuits C11 and the secondary display area A1. between display areas A2.
  • the plurality of redundant pixel circuits C2 are electrically insulated from signal lines (such as the above-mentioned scanning signal line Gate, data signal line Data, enable signal line EM, etc.) and the anode of the light-emitting device 31 . That is to say, none of the plurality of redundant pixel circuits C2 is coupled to a signal line (such as the scanning signal line Gate, the data signal line Data, the enable signal line EM, etc. mentioned above), and the plurality of redundant pixel circuits C2 None are coupled to the light emitting device 31 .
  • signal lines such as the above-mentioned scanning signal line Gate, data signal line Data, enable signal line EM, etc.
  • multiple redundant pixel circuits C2 can be set up to improve the display uniformity of the display pixel circuit C1 and avoid the problem of threshold voltage shift in the display pixel circuit C1, thereby solving the problem of the light-emitting device 31 being close to the secondary display.
  • the problem of abnormal display occurs in the light-emitting device 31 coupled to the display pixel circuit C1 at the boundary of the area A2.
  • the dark ring problem in the display screen is mainly caused by the part of the display pixel circuit C1 adjacent to the boundary of the sub-display area A2.
  • redundant pixel circuits C2 By arranging multiple display pixel circuits C1 and the sub-display area A2, redundant pixel circuits C2, then in the process of dehydrogenating the active layer 21, even if the dehydrogenation amount of the part of the active layer 21 corresponding to the plurality of redundant pixel circuits C2 is equal to that of the display pixel circuit C1
  • the dehydrogenation amount of some active layers 21, which can also avoid affecting the luminous brightness of the light-emitting device 31, and the distance between the boundary of the display pixel circuit C1 and the sub-display area A2 is relatively far, and the dehydrogenation amount is relatively relatively small.
  • the transistor included in the display pixel circuit C1 can be prevented from having a forward bias phenomenon in the threshold voltage, and thus the difference between the driving currents provided by the display pixel circuit C1 to the light-emitting device 31 electrically connected thereto can be small, and there is Helps avoid dark rings in the display.
  • the pixel circuit layer 20 also includes a flat layer 25 .
  • the flat layer 25 can fill the first via hole G1 and the second via hole G2 to provide a flat surface and ensure the structural stability of the sub-light emitting device 31b.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种显示基板，具有主显示区和副显示区，所述主显示区至少部分围绕所述副显示区，所述副显示区包括元件设置区和围绕所述元件设置区的过渡区。所述显示基板包括：衬底和位于所述衬底一侧的像素电路层和多个第一过孔。所述衬底至少位于所述主显示区和所述副显示区；所述像素电路层包括有源层及设置在所述有源层远离所述衬底一侧的多层无机绝缘层；所述有源层至少位于所述主显示区，且至少部分围绕所述副显示区，所述多层无机绝缘层至少位于所述主显示区和所述副显示区。所述多个第一过孔至少位于所述过渡区；所述多个第一过孔贯穿所述多层无机绝缘层中的至少一层。

Description

显示基板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及显示装置。
背景技术
随着科学技术的不断发展，用户对显示装置的屏占比(显示屏的面积与显示装置的前面板的面积的比例)有着越来越高的追求。
在显示技术领域中，出现了全面屏的概念，也即，将显示装置中的摄像头等光学器件设置在显示屏的下方，以增大显示屏的面积与显示装置的前面板的面积之间的比例，并使得该比例趋近于100％。
发明内容
一方面，提供一种显示基板。所述显示基板具有主显示区和副显示区，所述主显示区至少部分围绕所述副显示区，所述副显示区包括元件设置区和围绕所述元件设置区的过渡区。所述显示基板包括：衬底和位于所述衬底一侧的像素电路层和多个第一过孔。所述衬底至少位于所述主显示区和所述副显示区；所述像素电路层包括有源层及设置在所述有源层远离所述衬底一侧的多层无机绝缘层；所述有源层至少位于所述主显示区，且至少部分围绕所述副显示区，所述多层无机绝缘层至少位于所述主显示区和所述副显示区。所述多个第一过孔至少位于所述过渡区；所述多个第一过孔贯穿所述多层无机绝缘层中的至少一层。
在一些实施例中，所述副显示区包括第一单位面积区域和第二单位面积区域，所述第一单位面积区域与所述副显示区的边界之间的间距，大于所述第二单位面积区域与所述副显示区的边界之间的间距。位于所述第一单位面积区域的第一过孔的分布密度，小于或等于位于所述第二单位面积区域的第一过孔的分布密度。
在一些实施例中，与所述副显示区的边界之间的间距相同的至少两个第一单位面积区域内的第一过孔的分布密度，相同。和/或，与所述副显示区的边界之间的间距相同的至少两个第二单位面积区域内的第一过孔的分布密度，相同。
在一些实施例中，位于所述副显示区的第一过孔，均匀分布。
在一些实施例中，所述多个第一过孔位于所述过渡区。所述多个第一过孔中的至少部分第一过孔沿所述元件设置区的边界依次排列、呈环形设置。
在一些实施例中，所述像素电路层包括多个像素电路。所述多个第一过孔的一部分位于所述过渡区，所述多个第一过孔的另一部分位于所述元件设置区中至少靠近所述过渡区的部分区域。位于所述元件设置区中的部分第一过孔所占据的区域的最小尺寸，大于或等于一个像素电路的尺寸。
在一些实施例中，位于所述过渡区的部分第一过孔的分布密度，与位于所述元件设置区的部分第一过孔的分布密度相同。
在一些实施例中，所述显示基板还包括：位于所述像素电路层远离所述衬底一侧的发光器件层；所述发光器件层包括位于所述副显示区的多个副发光器件。位于所述元件设置区中的部分第一过孔在所述衬底上的正投影，和所述多个副发光器件在所述衬底上的正投影无交叠。
在一些实施例中，所述第一过孔的分布密度的范围为1％～14％。
在一些实施例中，沿经过所述元件设置区的中心、且与所述副显示区的边界连线的方向，第一过孔的孔径，及所述第一过孔和所述副显示区的边界之间的间距，呈负相关。
在一些实施例中，所述多层无机绝缘层包括沿远离所述有源层的方向依次层叠的第一栅绝缘层、第二栅绝缘层和层间介质层，至少一个所述第一过孔贯穿所述层间介质层、所述第二栅绝缘层和所述第一栅绝缘层。
在一些实施例中，所述像素电路层还包括位于所述副显示区的多个冗余半导体图案，所述多个冗余半导体图案与所述有源层同层设置。所述显示基板还包括：位于所述副显示区的多个第二过孔，第二过孔贯穿所述多层无机绝缘层中的至少一层。其中，所述多个第二过孔在所述衬底上的正投影，位于所述多个冗余半导体图案在所述衬底上的正投影范围内，位于所述过渡区的至少一个所述第二过孔为所述第一过孔。
在一些实施例中，所述多个第二过孔贯穿所述层间介质层、所述第二栅绝缘层和所述第一栅绝缘层至所述多个冗余半导体图案远离所述衬底一侧的表面。
在一些实施例中，所述显示基板还包括：位于所述像素电路层远离所述衬底一侧的发光器件层；所述发光器件层包括位于所述副显示区的多个副发光器件。其中，所述多个第二过孔中的至少部分在所述衬底上的正投影，位于所述多个副发光器件在所述衬底上的正投影范围内。
在一些实施例中，所述多个第二过孔的一部分位于所述元件设置区。靠近所述元件设置区的边界的部分第一过孔的分布密度，大于或等于位于所述元件设置区的第二过孔的分布密度。
在一些实施例中，所述显示基板还包括：至少位于所述主显示区的多个第三过孔。所述多个第三过孔贯穿所述多层无机绝缘层至所述有源层远离所述衬底一侧的表面；所述多个第三过孔的分布密度，小于或等于所述多个第一过孔的分布密度。
在一些实施例中，所述像素电路层包括多个像素电路，所述多个像素电路的至少一部分位于所述主显示区，位于所述主显示区的至少部分像素电路围绕所述副显示区。像素电路包括驱动晶体管，最靠近所述副显示区的边界的各驱动晶体管，与所述副显示区之间的最小间距相同。
在一些实施例中，所述的显示基板，还包括：位于所述像素电路层远离所述衬底一侧的发光器件层，所述发光器件层包括位于所述主显示区的多个主发光器件和位于所述副显示区的多个副发光器件。所述像素电路层包括多个显示像素电路，所述多个显示像素电路包括多个第一显示像素电路和多个第二显示像素电路。所述多个第一显示像素电路位于所述主显示区，且分别与所述多个主发光器件电连接；且分别通过导线与所述多个副发光器件电连接。
在一些实施例中，所述显示基板具有显示区和围绕所述显示区的边框区，所述显示区包括所述主显示区和所述副显示区。所述显示基板还包括：位于所述像素电路层上的发光器件层，所述发光器件层包括位于所述主显示区的多个主发光器件和位于所述副显示区的多个副发光器件。所述像素电路层包括多个显示像素电路，所述多个显示像素电路包括多个第一显示像素电路和多个第二显示像素电路；所述多个第一显示像素电路位于所述主显示区，且分别与所述多个主发光器件电连接；所述多个第二显示像素电路位于所述主显示区或所述边框区，且分别通过导电与所述多个副发光器件电连接。
在一些实施例中，所述像素电路层还包括多个冗余像素电路，所述多个冗余像素电路 位于所述主显示区，且位于所述多个像素电路和所述副显示区之间。
另一方面，提供一种显示装置。所述显示装置包括：如上述一些实施例中任一项所述的显示基板，及光学元件。所述光学元件设置在所述显示基板的非出光侧，所述光学元件在所述显示基板上的正投影与所述显示基板的元件设置区至少部分交叠。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸等的限制。
图1为根据本公开一些实施例中的一种显示装置的结构图；
图2为根据本公开一些实施例中的另一种显示装置的结构图；
图3为根据本公开一些实施例中的一种显示基板的结构图；
图4为根据本公开一些实施例中的另一种显示基板的结构图；
图5为根据本公开一些实施例中的又一种显示基板的结构图；
图6为根据本公开一些实施例中的一种显示像素电路的等效电路图；
图7为根据本公开一些实施例中的又一种显示基板的结构图；
图8为根据本公开一些实施例中的又一种显示基板的结构图；
图9为根据本公开一些实施例中的一种像素电路层中的一些膜层的俯视图；
图10为根据本公开一些实施例中的一种像素电路层中的另一些膜层的俯视图；
图11为根据本公开一些实施例中的一种像素电路层中的又一些膜层的俯视图；
图12为根据本公开一些实施例中的一种像素电路层中的又一些膜层的俯视图；
图13为根据本公开一些实施例中的一种像素电路层中的又一些膜层的俯视图；
图14为根据本公开一些实施例中的一种像素电路层中的又一些膜层的结构图；
图15为根据本公开一些实施例中的一种像素电路层中的又一些膜层的结构图；
图16为根据本公开一些实施例中的一种像素电路层中的又一些膜层的结构图；
图17为一种实现方式中显示基板出现的暗环的示意图；
图18为根据本公开一些实施例中的一种显示基板的一种局部放大图；
图19为图18所示显示基板的一种局部放大图；
图20为根据本公开一些实施例中的一种显示基板的另一种局部放大图；
图21为图20所示显示基板的一种局部放大图；
图22为根据本公开一些实施例中的一种显示基板的一种局部放大图；
图23为根据本公开一些实施例中的一种显示基板的另一种局部放大图；
图24为根据本公开一些实施例中的一种显示基板的另一种局部放大图；
图25为根据本公开一些实施例中的又一种显示基板的结构图；
图26为根据本公开一些实施例中的一种显示基板的又一种局部放大图；
图27为根据本公开一些实施例中的一种像素电路层中的又一些膜层的结构图；
图28为根据本公开一些实施例中的一种显示基板的又一种局部放大图；
图29为根据本公开一些实施例中的一种显示基板的又一种局部放大图；
图30为根据本公开一些实施例中的一种像素电路层中的又一些膜层的结构图；
图31为根据本公开一些实施例中的一种像素电路层中的又一些膜层的结构图；
图32为根据本公开一些实施例中的一种像素电路层中的又一些膜层的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如 由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开的一些实施例提供了一种显示基板100及显示装置1000，以下对显示基板100及显示装置1000分别进行介绍。
本公开的一些实施例提供一种显示装置1000，如图1所示。该显示装置1000可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字的还是图像的任何显示装置中。更明确地说，预期所述实施例的显示装置可实施应用在多种电子中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
在一些示例中，如图2所示，上述显示装置1000包括：显示基板100。
示例性的，显示装置1000还包括：框架、显示驱动IC(Integrated Circuit，集成电路)以及其他电子配件等。
在一些示例中，如图2和图3所示，上述显示基板100具有显示区A。如图3所示，显示基板100还具有边框区S，该边框区S围绕显示区A。
示例性的，如图2和3所示，显示区A包括主显示区A1和副显示区A2。其中，主显示区A1围绕副显示区A2。
本公开对于显示区A及副显示区A2的形状不做限定，可以根据实际需要进行选择设置。
示例性的，显示区A的形状可以为矩形、近似矩形、圆形或椭圆形等。其中，近似矩形为非严格意义上的矩形，其四个内角例如可以为圆角，或者某条边例如不是直线。
示例性的，副显示区A2的形状包括：圆形、椭圆形、多边形中的任意一种。其中，多边形可以包括四边形、五边形或六边形等。
需要说明的是，在宏观角度上，副显示区A2的边界由平滑的线条构成。在微观角度上，副显示区A2的边界可以包括平滑的线条，也可以包括呈锯齿状的线条。
在一些示例中，如图4和图5所示，显示基板100包括：衬底10。
上述衬底10的结构包括多种，可以根据实际需要选择设置。
例如，衬底10可以为刚性衬底。该刚性衬底例如可以为玻璃衬底或PMMA(Polymethyl Methacrylate，聚甲基丙烯酸甲酯)衬底。在此情况下，上述显示基板100可以为刚性显示基板。
又如，衬底10可以为柔性衬底。该柔性衬底例如可以为PET(Polyethylene Terephthalate，聚对苯二甲酸乙二醇酯)衬底、PEN(Polyethylene Naphthalate Two Formic Acid Glycol Ester，聚萘二甲酸乙二醇酯)衬底或PI(Polyimide，聚酰亚胺)衬底。在此情况下，上述显示基板100可以为柔性显示基板。
在一些示例中，如图4和图5所示，显示基板100还包括：位于衬底10上的像素电路层20。
示例性的，上述像素电路层20包括多个像素电路C。该多个像素电路C可以包括多个显示像素电路C1。
可选地，如图8所示，上述多个像素电路C还可以包括多个冗余像素电路C2，关于该多个冗余像素电路C2，可以参见下文中的说明，此处不再赘述。
可以理解的是，如图8所示，显示像素电路C1和冗余像素电路C2可以具有相同的结构，下面以显示像素电路C1为例进行示意性说明。
上述显示像素电路C1的结构包括多种，可以根据实际需要选择设置。例如，显示像素电路C1的结构可以包括“2T1C”、“6T1C”、“7T1C”、“6T2C”或“7T2C”等结构。此处，“T”表示为晶体管，位于“T”前面的数字表示为晶体管的数量，“C”表示为存储电容器，位于“C”前面的数字表示为存储电容器的数量。
需要说明的是，图4和图5仅示意出了一个晶体管，本公开以该晶体管代表显示像素电路C1。
本公开中以显示像素电路C1的结构为“7T1C”结构为例进行说明。其中，图6示意出了显示像素电路C1的等效电路图。
例如，如图6所示，显示像素电路C1包括：第一复位晶体管T1、第二复位晶体管T2、开关晶体管T3、驱动晶体管T4、补偿晶体管T5、第一发光控制晶体管T6、第二发光控制晶体管T7和存储电容器Cst。
例如，如图6所示，第一复位晶体管T1的栅极与第一复位信号线Reset1耦接，第一复位晶体管T1的第一极与第一初始信号线Vinit1耦接，第一复位晶体管T1的第二极与第四节点N4耦接。第二复位晶体管T2的栅极与第二复位信号线Reset2耦接，第二复位晶体管T2的第一极与第二初始信号线Vinit2耦接，第二复位晶体管T2的第二极与第一节点N1耦接。开关晶体管T3的栅极与扫描信号线Gate耦接，开关晶体管T3的第一极与数据线Data耦接，开关晶体管T3的第二极与第二节点N2耦接。驱动晶体管T4的栅极与第四节点N4耦接，驱动晶体管T4的第一极与第二节点N2耦接，驱动晶体管T4的第二极与第三节点N3耦接。补偿晶体管T5的栅极与扫描信号线Gate耦接，补偿晶体管T5的第一极与第三节点N3耦接，补偿晶体管T5的第二极与第四节点N4耦接。第一发光控制晶体管T6的栅极与使能信号线EM耦接，第一发光控制晶体管T6的第一极与第一电压信号线VDD耦接，第一发光控制晶体管T6的第二极与第二节点N2耦接。第二发光控制晶体管T7的栅极与使能信号线EM耦接，第二发光控制晶体管T7的第一极与第三节点N3耦接，第二发光控制晶体管T7的第二极与第一节点N1耦接。存储电容器Cst的第一 极与第四节点N4耦接，存储电容器Cst的第二极与第一电压信号线VDD耦接。
可选地，显示像素电路C1的工作过程包括依次进行的复位阶段、数据写入及补偿阶段、发光阶段。
例如，在复位阶段，在第一初始信号线Reset1所提供的第一复位信号的控制下，第一复位晶体管T1导通，将第一初始信号线Vinit1所提供的第一初始信号传输至第四节点N4，对第四节点N4进行复位。
例如，在数据写入及补偿阶段，第二复位晶体管T2在第二初始信号线Reset2所提供的第二复位信号的控制下导通，将第二初始信号线Vinit2所提供的第二初始信号传输至第一节点N1，对第一节点N1进行复位。开关晶体管T3、补偿晶体管T5在扫描信号线Gate所提供的扫描信号的控制下导通，开关晶体管T3将数据线Data所提供的数据信号传输至第二节点N2，驱动晶体管T4将来自第二节点N2的数据信号传输至第三节点N3。补偿晶体管T5将来自第三节点N3的数据信号传输至第四节点N4，对驱动晶体管T4进行充电，直至完成对驱动晶体管T4的阈值电压的补偿。
例如，在发光阶段，第一发光控制晶体管T6和第二发光控制晶体管T7在使能信号线EM所提供的使能信号的控制下同时导通。第一发光控制晶体管T6将第一电压信号传输至第二节点N2。驱动晶体管T4根据来自第二节点N2的第一电压信号和来自第四节点N4的数据信号生成驱动信号(例如驱动电流)，并将数据信号传输至第三节点N3。第二发光控制晶体管T7将来自第三节点N3的数据信号传输至第一节点N1。
在一些示例中，如图4和图5所示，显示基板100还包括：位于像素电路层20上的发光器件层30。该发光器件层30包括多个发光器件31。
示例性的，上述发光器件31可以为OLED(Organic Light Emitting Diode，有机发光二极管)。
例如，如图4和图5所示，发光器件31包括阳极311、发光层312和阴极313。
可选地，发光器件31还可以包括设置在阳极311和发光层312之间的空穴注入层和/或空穴传输层。发光器件31还可以包括设置在发光层312和阴极313之间的电子传输层和/或电子注入层。
示例性的，上述多个显示像素电路C1和上述多个发光器件31(例如发光器件31的阳极311)之间可以相互电连接。其中，该多个显示像素电路C1和该多个发光器件31之间的电连接关系包括多种，可以根据实际需要选择设置。
例如，上述多个显示像素电路C1和上述多个发光器件31可以一一对应地电连接。又如，一个显示像素电路C1可以与多个发光器件31耦接。又如，多个显示像素电路C1可以与一个发光器件31耦接。
上述显示基板100中，显示像素电路C1可以生成驱动电流，各发光器件31可以在相应的显示像素电路C1所生成的驱动电流的驱动作用下发出光。多个发光器件31所发出的光相互配合，可以使得显示基板100进行画面显示。
下面，本公开以一个显示像素电路C1与一个发光器件31耦接为例，对显示基板100的结构进行示意性说明。
示例性的，如图4、图5、图7和图8所示，上述多个显示像素电路C1包括多 个第一显示像素电路C11和多个第二显示像素电路C12。上述多个发光器件31包括：位于主显示区A1的多个主发光器件31a和位于副显示区A2的多个副发光器件31b。其中，上述多个主发光器件31a分别与该多个第一显示像素电路C11电连接，上述多个副发光器件31b分别与该多个第二显示像素电路C12电连接。
这样，第一显示像素电路C11可以驱动位于主显示区A1的主发光器件31a发光，第二显示像素电路C12可以驱动位于副显示区A2的副发光器件31b发光。
可选地，上述多个第一显示像素电路C11位于主显示区A1，上述多个第二显示像素电路C12位于副显示区A2以外的区域。
需要说明的是，上述多个第二显示像素电路C12的设置方式包括多种，可以根据实际需要选择设置。
示例性的，如图7所示，上述多个第二显示像素电路C12设置在主显示区A1。该多个第二显示像素电路C12例如排列为多行多列，任意相邻两列第二显示像素电路C12之间可以设置有至少一列第一显示像素电路C11。
例如，本公开可以采用局部压缩的方式，设置上述多个第二显示像素电路C12。也即，将该多个第二显示像素电路C12设置在主显示区A1的与副显示区A2临近的一部分区域中，且位于该部分区域中的第一显示像素电路C11和第二显示像素电路C12的尺寸，小于位于其他区域中的第一显示像素电路C11的尺寸。
又如，本公开可以采用全局压缩的方式，设置上述多个第二显示像素电路C12。也即，显示基板100所包括的多个第一显示像素电路C11和多个第二显示像素电路C12的尺寸，均被减小。
其中，不论是采用局部压缩的方式还是全局压缩的方式，本公开对于任意相邻两列第二显示像素电路C12之间设置的第一显示像素电路C1的列数不做限定，可以根据实际需要进行选择设置。
例如，任意相邻两列第二显示像素电路C12之间所设置的第一显示像素电路C11的列数可以为1列、2列或4列等。
这样，可以避免在边框区S设置显示像素电路C1，降低边框区S的宽度，进而可以提高显示基板100及显示装置1000的屏占比。
示例性的，如图8所示，上述多个第二显示像素电路C12设置在边框区S。其中，图8仅示意出了部分第二显示像素电路C12，并不对位于边框区S的第二显示像素电路C12的数量形成限定。
这样，可以增大主显示区A1中用于设置第一显示像素电路C11的面积，进而可以在主显示区A1设置更多的第一显示像素电路C11，提升显示基板100的像素密度。
由上可知，显示基板100所包括的多个显示像素电路C1，均位于副显示区A2以外的区域，显示基板100所包括的多个发光器件31，均位于显示区A。
可以理解的是，显示像素电路C1的部分结构的材料包括金属材料，金属材料的透光率较低，对光线的阻挡效果较高。本公开实施例通过将与位于副显示区A2的副发光器件31b电连接的第二显示像素电路C12设置在副显示区A2以外的区域，不仅可以使得显示基板100实现全面屏显示，还可以在外界光线入射至显示基板100位于副显示区A2的部分的情况下，可以避免第二显示像素电路C12对外界光线进行遮挡， 使得该外界光线能够穿过任意相邻两个副发光器件31b之间的间隙射出，使得显示基板100位于副显示区A2的部分具有较高的透光率。
示例性的，如图4、图7和图8所示，显示基板100还包括：位于像素电路层20和发光器件层30之间的转接层。该转接层包括多条导线41，每条导线41的一端与第二显示像素电路C12电连接，另一端连接与副发光器件31b电连接。也即，每个第二显示像素电路C12通过导线41与相应的副发光器件31b电连接。
可选地，导线41的材料包括可透光的导电材料，例如ITO(Indium Tin Oxide，氧化铟锡)。这样可以避免影响显示基板100位于副显示区A2的部分的透光率。
在一些示例中，如图2所示，显示装置1000还包括：设置在显示基板100的非出光侧的光学元件200，该光学元件200位于显示基板100的副显示区A2。
可以理解的是，出光侧指的是显示基板100能够显示画面的一侧。非出光侧指的是，显示基板100中，与出光侧相背的一侧。
示例性的，在发光器件层30的出光方向、为发光器件层30远离衬底10的一侧的情况下，上述非出光侧指的是，衬底10远离发光器件层30的一侧。
示例性的，上述光学元件200包括：摄像头、红外传感器或指纹传感器等。
本公开以光学元件200为摄像头为例。
示例性的，在摄像头进行工作的过程中，由于显示基板100位于副显示区A2的部分未设置显示像素电路C1，可以避免显示像素电路C1对外界光线形成遮挡，进而外界光线可以穿过显示基板100位于副显示区A2的部分。这样摄像头便可以采集该光线，实现拍照的功能。
示例性的，在摄像头未进行工作的情况下，显示基板100位于副显示区A2的部分也能够进行显示，使得显示基板100的整体能够显示图像，实现全面屏显示。
需要说明的是，如图3所示，显示基板100的副显示区A2包括元件设置区A21和围绕元件设置区A21的过渡区A22。
示例性的，如图3所示，过渡区A22相比元件设置区A21更靠近主显示区A1。
进一步地，本领域技术人员考虑到光学元件200的视角，可以将光学元件200在显示基板100上的正投影与显示基板100的元件设置区A21至少部分交叠。也即，光学元件200可以设置在元件设置区A21内，或者，光学元件200与元件设置区A21可以有一些错位。这样有利于提高光学元件200的工作性能。
在一些实施例中，如图4和图5所示，像素电路层20包括有源层21，设置在有源层21远离衬底10一侧的多层无机绝缘材料22。
在一些示例中，上述多层无机绝缘材料22例如包括：沿远离衬底10的方向依次层叠的第一栅绝缘层221、第二栅绝缘层222和层间介质层223。
像素电路层20例如还包括位于第一栅绝缘层221、第二栅绝缘层222之间的第一栅导电层23、位于第二栅绝缘层222和层间介质层223之间的第二栅导电层26、及位于层间介质层223远离衬底10一侧的源漏导电层24。
示例性的，有源层21的材料可以为LTPS(Low Temperature Poly Silicon，低温多晶硅)或金属氧化物等。该金属氧化物可以为IGZO(Indium Gallium Zinc Oxide，铟镓锌氧化物)。本公开以有源层21的材料为LTPS为例进行示意性说明。
例如，本公开可以采用化学气相沉积(Chemical Vapor Deposition，简称CVD)方法或 等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，简称PECVD)方法制备得到LTPS膜层，然后经后续工艺(例如刻蚀工艺)对LTPS膜层进行图案化，形成有源层21。
示例性的，第一栅绝缘层221和第二栅绝缘层222的材料均为无机材料。该无机材料可以是氮化硅、氧化硅和氮氧化硅中的至少一种。其中，第一栅绝缘层221和第二栅绝缘层222的厚度较为均匀。
示例性的，层间介质层223的材料为无机材料。例如，该无机材料可以是氮化硅、氧化硅和氮氧化硅中的至少一种。
示例性的，图9示意出了有源层21的一种俯视结构，图10示意出了第一栅导电层23的一种俯视结构，图11示意出了第二栅导电层26的一种俯视结构，图12示意出了层间介质层223的过孔俯视结构，图13示意出了源漏导电层24的一种俯视结构。可以理解的是，层间介质层223的材料为可透光的材料，因此，图12中仅示意出了层间介质层223中的过孔(例如包括第三过孔G3)的位置。
需要说明的是，有源层21在衬底10上的正投影，与第一栅导电层23、第二栅导电层26在衬底10上的正投影具有交叠。其中，在有源层21远离衬底10的一侧形成第一栅导电层23和第二栅导电层26后，可以第一栅导电层23和第二栅导电层26为掩膜，对有源层21进行掺杂处理，使得有源层21中被第一栅导电层23和第二栅导电层26覆盖的部分，构成显示像素电路C1中各晶体管的有源图案，使得有源层21中未被第一栅导电层23和第二栅导电层26覆盖的部分，构成导体。第一栅导电层23或第二栅导电层26与有源层21交叠的部分，构成显示像素电路C1中各晶体管的栅极。
示例性的，第二栅导电层26中与第一栅导电层23中重叠的部分，例如显示像素电路C1中的存储电容器。
在一些示例中，如图14和图15所示，显示基板100还包括多个第三过孔G3。该多个第三过孔G3中，每个第三过孔G3贯穿上述多层无机绝缘层22至有源层21远离衬底10的一侧表面。该多个第三过孔G3至少位于主显示区A1。
示例性的，如图13所示，源漏导电层24包括多个源漏导电图案。如图14～图16所示，上述多个第三过孔G3可以暴露有源层21中被掺杂的部分，以使得部分源漏导电图案可以通过第三过孔G3与有源层21中被掺杂的部分形成电接触，进而构成显示像素电路C1中各晶体管的源极或漏极。
由于显示基板100所包括的显示像素电路C1至少位于主显示区A1，因此，上述有源层21则至少位于主显示区A1。例如，有源层21位于主显示区A1，或者，有源层21位于主显示区A1和副显示区A2。另外，第一栅导电层23、第二栅导电层26及源漏导电层24所在区域与有源层21所在区域基本一致。
需要说明的是，在制备像素电路层所包括的有源层的过程中，通常会使得有源层中含有大量氢，而有源层中所含有的氢会影响后续形成的显示像素电路层中各晶体管(尤其是驱动晶体管)的器件特性，因此，一般需要在制备像素电路层的过程中对有源层进行脱氢处理，以去除有源层中所包含的氢。例如，在形成源漏导电层之前，可以对有源层进行热处理，以使得有源层中所包含的氢溢出。
其中，溢出的氢例如可以通过和有源层对应的第三过孔溢出，这样可以减缓氢的溢出速度，避免有源层所处的空间中短时间内聚集高浓度的氢，进而避免产生氢爆问题。
在一种实现方式中，在对有源层进行脱氢处理的过程中，有源层中与副显示区相邻的部分所包含的氢，可以通过与其正对的第三过孔、或与其临近且远离副显示区的第三过孔溢出，而有源层位于其他区域的部分还可以通过与其临近的且靠近副显示区的第三过孔溢出。
也就是说，有源层中与副显示区相邻的部分所包括的氢的溢出途径，相比其他部分所包括的氢的溢出途径较少，这样会导致有源层中与副显示区相邻的部分的去氢量和其他部分的去氢量之间存在差异，进而使得后续形成的、与副显示区相邻的部分显示像素电路C1中的晶体管的阈值电压产生正向漂移(简称正偏)，这些晶体管的阈值电压正偏的范围例如为0.1V～1.2V。
如表1所示，L64表示发光器件的发光亮度为64灰阶，L128表示发光器件的发光亮度为128灰阶，L255表示发光器件的发光亮度为255灰阶。驱动电流变化量ΔI表示显示像素电路的晶体管的阈值电压正偏后，显示像素电路传输至相应发光器件的驱动电流，与显示像素电路的晶体管的阈值电压未发生漂移的情况下，显示像素电路传输至相应发光器件的驱动电流之间的差值。驱动电流变化量百分比表示驱动电流变化量占显示像素电路的晶体管的阈值电压未发生漂移的情况下显示像素电路传输至相应发光器件的驱动电流的百分比，可以用来表示显示像素电路传输至相应发光器件的驱动电流差异。
一般来说，在传输至发光器件的驱动电流的差异超过2％的情况下，人眼可以察觉到发光亮度的变化。而由表1可知，64灰阶下，在阈值电压正偏0.1V的情况下，驱动电流的变化差异达到2.1％(大于2％)；128灰阶下，在阈值电压正偏0.2V的情况下，驱动电流的变化差异达到2.5％(大于2％)；255灰阶下，在阈值电压正偏0.4V的情况下，驱动电流的变化差异达到2.3％(大于2％)。也就是说，在显示像素电路的晶体管产生0.1～1.2V的阈值电压正偏后，会使得与副显示区相邻的显示像素电路传输至相应发光器件的驱动电流产生变化，进而使得该发光器件的发光亮度与其他发光器件的发光亮度之间产生差异，导致副显示区周围出现显示暗环(如图15所示)，并且该暗环能够被人眼观察到，这样影响了显示基板及显示装置的显示效果。
表1
Figure PCTCN2022089651-appb-000001
基于此，如图14和图15所示，显示基板100还包括多个第一过孔G1。该多个第一过孔G1贯穿上述多层无机绝缘层22中的至少一层。
在一些示例中，每个第一过孔G1所贯穿的膜层可以相同，也可以不同。
示例性的，图14和图15示意出了像素电路层20中的有源层21和上述多层无机绝缘层22中的第一栅绝缘层221、第二栅绝缘层222及层间介质层223层叠设置之后的局部结构。
如图14所示，上述多个第一过孔G1中的一部分第一过孔G1贯穿层间介质层223，该部分第一过孔G1的深度例如与层间介质层223的厚度相等；另一部分第一过孔G1贯穿层间介质层223、第二栅绝缘层222和第一栅绝缘层221，该部分第一过孔G1的深度例如与层间介质层223、第二栅绝缘层222和第一栅绝缘层221的厚度之和相等。
如图15所示，上述多个第一过孔G1均贯穿层间介质层223、第二栅绝缘层222和第一栅绝缘层221。
上述多个第一过孔G1在衬底10上的正投影和第一栅导电层23在衬底10上的正投影及第二栅导电层26在衬底10上的正投影之间无交叠，也即，各第一过孔G1和第一栅导电层23、第二栅导电层26错开设置。
在一些示例中，上述多个第一过孔G1至少位于过渡区A22。
示例性的，上述多个第一过孔G1可以位于全部过渡区A22。或者，上述多个第一过孔G1中的一部分位于过渡区A22，另一部分位于元件设置区A21。当然，部分第一过孔G1也可以位于主显示区A1。
如图18～图21所示，本公开以上述多个第一过孔G1位于副显示区A2，且至少位于过渡区A22为例进行示意性说明。
图18为显示基板100的一种局部放大图，图19为图18所示显示基板100的一种局部放大图。
示例性的，如图18和图19所示，上述多个第一过孔G1可以均位于过渡区A22内。
图20为显示基板100的另一种局部放大图，图21为图20所示显示基板100的另一种局部放大图。
示例性的，如图20和图21所示，上述多个第一过孔G1中的一部分位于过渡区A22内，该多个第一过孔G1中的另一部分位于元件设置区A21内。
至少在过渡区A22设置第一过孔G1后，也即，至少在靠近副显示区A2的边界的区域内设置第一过孔G1后，可以降低位于主显示区A1内的过孔(也即第三过孔G3)的分布密度和位于靠近副显示区A2的边界的区域内的过孔(也即第一过孔G1)的分布密度之间的差异。在对像素电路层20中的有源层21进行脱氢处理的过程中，有源层21中与副显示区A2相邻的部分所包含的氢，不仅可以通过与其正对的第三过孔G3或与其临近的且远离副显示区A2的第三过孔G3溢出，还可以通过位于副显示区A2中的第一过孔G1溢出。这样可以使得有源层21中与副显示区A2相邻的部分和其他部分相比，具有数量接近的氢溢出途径，增大有源层21中与副显示区A2相邻的部分的去氢量，从而可以降低有源层21中的各部分的去氢量的差异，避免与副显示区A2相邻的区域内的显示像素电路C1的晶体管的阈值电压产生正偏，使得不同位置处的显示像素电路C1传输至相应的发光器件31的驱动电流基本相等，降低不同位置处的显示像素电路C1传输至相应的发光器件31的驱动电流的差值，进而使得不同位置处的发光器件31发出的光的亮度接近一致，减缓甚至消除避免显示基板100及显示装置1000的显示画面出现的暗环现象，提高显示画面的均一性。
由此，本公开的一些实施例所提供的显示基板100，通过设置多个第一过孔G1，并将该多个第一过孔G1至少设置在过渡区A22，可以在对有源层2进行脱氢处理的过程中，使得有源层21中与副显示区A2相邻的部分所包含的氢，不仅能够通过与其正对的第三过孔G3或与其临近的且远离副显示区A2的第三过孔G3溢出，还可以通过至少位于过渡区 A22内的第一过孔G1溢出。
这也就意味着，本公开增加了有源层21中与副显示区A2相邻的部分所包含的氢的溢出途径，可以增加有源层21中与副显示区A2相邻的部分的去氢量，使得有源层21中与副显示区A2相邻的部分的去氢量和其他部分的去氢量接近一致，避免后续形成在与副显示区A2相邻的区域内的显示像素电路C1的晶体管的阈值电压产生正偏，进而使得不同位置处的发光器件31发出的光的亮度接近一致，减缓甚至消除避免显示基板100及显示装置1000的显示画面出现的暗环现象，提高显示画面的均一性。
本公开对于第一过孔G1在副显示区A2中的分布情况不做限定，具体可以根据实际需要进行选择设置。
在一些实施例中，如图22和图23所示，副显示区A2包括第一单位面积区域a和第二单位面积区域b，第一单位面积区域a与副显示区A2的边界之间的间距，大于第二单位面积区域b与副显示区A2的边界之间的间距。
需要说明的是，如图3所示，在宏观角度上，副显示区A2的边界与元件设置区A21边界的形状基本相同。如图18～图23所示，在微观角度上，副显示区A2的边界的至少一部分可能呈折线形或锯齿状，呈折线形或锯齿状的部分边界会与元件设置区A21的边界形成不规则区域(例如图19、图21～图23所示的类似三角形区域)。
第一单位面积区域a与副显示区A2的边界之间的间距，可以理解为，经过元件设置区A21的中心、且指向副显示区A2的方向，第一单位面积区域a与副显示区A2的边界之间的间距。第二单位面积区域b与副显示区A2的边界之间的间距，可以理解为，经过元件设置区A21的中心、且指向副显示区A2的方向，第二单位面积区域b与副显示区A2的边界之间的间距。
本公开对于第一单位面积区域a和第二单位面积区域b在副显示区A2中的具体位置不做限定，在满足第一单位面积区域a与副显示区A2的边界之间的间距，大于第二单位面积区域b与副显示区A2的边界之间的间距的情况下，可以根据实际需要进行选择设置。
可以理解的是，第一单位面积区域a和第二单位面积区域b中，两者面积均为1，且两者的面积单位相同。其中，两者的档单位面积可以根据实际需要设置，例如，两者的面积单位均为平方微米(μm 2)。
示例性的，第一单位面积区域a的面积和第二单位面积区域b的面积均小于副显示区A2的面积。其中，第一单位面积区域a的边界与副显示区A2的边界之间存在间距，第二单位面积区域b的边界可以与副显示区A2的边界部分重合或者存在间距。这样可以确保第一单位面积区域a与副显示区A2的边界之间的间距，能够大于第二单位面积区域b与副显示区A2的边界之间的间距。
例如，如图22所示，L代表经过元件设置区A21的中心的线条，L的延伸方向为经过元件设置区A21的中心、且指向副显示区A2的边界的方向。L经过一个第一单位面积区域a和一个第二单位面积区域b，此时，第一单位面积区域a的边界与副显示区A2的边界之间的间距为Δh1，第二单位面积区域b的边界与副显示区A2的边界之间的间距为Δh2，其中，Δh1＞Δh2。
需要说明的是，本公开中提及的第一过孔G1的分布密度指的是，某一区域中所设置的各第一过孔G1在衬底10上的正投影面积之和，与该区域在衬底10上的正投影面积之间的比值。
可以理解的是，在各第一过孔G1的孔径相等的情况下，某一区域中单位面积区域内所设置的第一过孔G1的数量，可以反应出第一过孔G1的分布密度。例如，单位面积区域中所设置的第一过孔G1的数量越小，第一过孔G1的分布密度则越小，单位面积区域中所设置的第一过孔G1的数量越大，第一过孔G1的分布密度则越大。
在一些示例中，如图22和图23所示，位于第一单位面积区域a的第一过孔G1的分布密度，小于或等于位于第二单位面积区域b的第一过孔G1的分布密度。也即，位于第一单位面积区域a的第一过孔G1的面积占比，小于或等于，位于第二单位面积区域b的第一过孔G1的面积占比。
示例性的，在不同第一过孔G1的孔径相等的情况下，位于第一单位面积区域a的第一过孔G1的数量，小于或等于位于第二单位面积区域b的第一过孔G1的数量。
也就是说，最靠近副显示区A2的部分第一过孔G1的分布密度最大。随着与副显示区A2的边界之间的间距的增大，第一过孔G1的分布密度逐渐减小，其中，第一过孔G1的分布密度可以呈线性减小、或呈阶段性减小。
可以理解的是，显示像素电路C1中晶体管的阈值电压的漂移具有过渡性，也即，随着与副显示区A2边界的间距的增大，显示像素电路C1中晶体管的阈值电压的漂移量逐渐减小。本公开通过对第一过孔G1的分布密度进行设置，使得最靠近副显示区A2的部分第一过孔G1的分布密度最大，可以在对有源层21进行脱氢处理的过程中，有源层21中与副显示区A2相邻的部分所包含的氢中，大部分可以从距离副显示区A2最近的、分布密度最大的第一过孔G1溢出，有利于较为充分地去除该部分有源层21所包含的氢，进而有效降低靠近副显示区A2的边界的晶体管的阈值电压漂移量，改善暗环现象。
在一些示例中，如图23所示，与副显示区A2的边界之间的间距相同的至少两个第一单位面积区域a内的第一过孔G1的分布密度，相同。和/或，与副显示区A2的边界之间的间距相同的至少两个第二单位面积区域b内的第一过孔G1的分布密度，相同。
示例性的，与副显示区A2的边界之间的间距相同的多个第一单位面积区域a内的第一过孔G1的分布密度相同，也即，不同第一单位面积区域a内的第一过孔G1的面积占比相同。或着，与副显示区A2的边界之间的间距相同的多个第二单位面积区域b内的第一过孔G1的分布密度相同，也即，不同第二单位面积区域b内的第一过孔G1的面积占比相同。这样副显示区A2中，与副显示区A2的边界之间的间距相同的一圈区域内的第一过孔G1的分布密度相同，可以使得有源层21中与副显示区A2相邻的部分，在与副显示区A2的距离相同的地方具有基本相同数量的氢溢出途径。
示例性的，与副显示区A2的边界之间的间距相同的多个第一单位面积区域a内的第一过孔G1的分布密度相同，且与副显示区A2的边界之间的间距相同的多个第二单位面积区域b内的第一过孔G1的分布密度相同。这样副显示区A2中，与副显示区A2的边界之间的间距相同的任意一圈区域内的第一过孔G1的分布密度相同，且与副显示区A2的边界之间的间距越远，这一圈区域内的第一过孔G1的分布密度越小。这样可以使得有源层21中与副显示区A2相邻的部分，在与副显示区A2的距离相同的任意一块区域具有相同数量的氢溢出途径。
这样可以使得环绕副显示区A2的部分有源层21中，溢出的氢的量基本相同，进而可以使得对环绕副显示区A2的不同晶体管的阈值电压的改善效果基本相同，避免出现副显示区A2周围(例如位于副显示区A2上方、下方、左方及右方的不同区域)暗环现象不均 一的情况，进一步提高显示基板100及显示装置1000的显示画面的均一性。
在一些实施例中，如图19和图21所示，位于副显示区A2的第一过孔G1，均匀分布。
示例性的，任意两个相邻的第一过孔G1之间的间距相等。
通过使位于副显示A2的第一过孔G1均匀分布，不仅可以使有源层21中与副显示区A2相邻的部分具有相同的氢溢出环境，以使得不同位置处的有源层21具有接近的去氢量，还可以降低第一过孔G1的排版难度，降低显示基板100的制备难度。
在一些实施例中，如图18所示，上述多个第一过孔G1位于过渡区A22。其中，该多个第一过孔G1中的至少部分第一过孔G1沿元件设置区A21的边界依次排列、呈环形设置。
这样可以提高第一过孔G1的分布均匀度，使得围绕副显示区A2的部分有源层21能够通过第一过孔G1溢出氢，以使得不同位置处的有源层21具有接近的去氢量，还可以降低第一过孔G1的排版难度，降低显示基板100的制备难度。
在一些实施例中，如图20～图23所示，上述多个第一过孔G1中，一部分第一过孔G1位于过渡区A22，另一部分第一过孔G1位于元件设置区A21。
也就是说，设置第一过孔G1的区域，并不局限于靠近副显示A2的过渡区A22。其中，位于元件设置区A21的部分第一过孔G1，例如位于靠近过渡区A22的边界的部分区域内。
通过在过渡区A22和元件设置区A21均设置第一过孔G1，不仅可以增大可用于设置第一过孔G1的区域的面积，还可以大大增加可设置的第一过孔G1的数量。这样可以使得有源层21中与副显示区A2相邻的部分所包含的氢能够具有更多的溢出途径，进而能够更加充分地去除有源层21中与副显示区A2相邻的部分的氢，确保良好的去氢效果。
在一些示例中，如图20～图23所示，在上述多个第一过孔G1的另一部分位于元件设置区A21中的情况下，该多个第一过孔G1的另一部分在元件设置区A21中占据的区域的最小尺寸，大于或等于一个像素电路C的尺寸。
上述多个第一过孔G1的另一部分在元件设置区A21中占据的区域的尺寸，例如指的是，经过元件设置区A21的中心、且指向过渡区A22的边界的方向上，上述区域的尺寸。
上述像素电路C的尺寸，例如指的是，像素电路C的横向尺寸、纵向尺寸或平均尺寸。像素电路C的尺寸可以根据实际需要选择设置。
示例性的，上述最小尺寸可以等于一个像素电路C的尺寸、两个像素电路C的尺寸或四个像素电路C的尺寸。
示例性的，一个像素电路C的尺寸约为64μm。
通过将上述多个第一过孔G1的另一部分设置在元件设置区A21中至少靠近过渡区A22的部分区域，可以使这部分第一过孔G1距离有源层21中与副显示区A2相邻的部分的距离较近，在对有源层21进行去氢处理的过程中，有利于减小氢的移动距离，进而有利于氢的充分去除。通过使多个第一过孔G1的另一部分在元件设置区A21中占据的区域的最小尺寸，大于或等于一个像素电路C的尺寸，可以使得有源层21中位于与副显示区A2相邻的部分所包含的氢具有较多的溢出途径，有利于氢的充分去除，进而有利于更加充分地减小靠近副显示区A2的显示像素电路C1的晶体管的阈值电压的漂移量，有利于进一步改善暗环现象。
示例性的，如图20所示，上述多个第一过孔G1的另一部分在元件设置区A21中占据的区域中，不同位置处的尺寸相等。该多个第一过孔G1的另一部分在元件设置区A21中占据的区域呈环形。
在一些示例中，如图21所示，位于过渡区A22的第一过孔G1的分布密度，与位于元件设置区A21的第一过孔G1的分布密度相同。也即，位于过渡区A22的第一过孔G1的面积占比与位于元件设置区A21的第一过孔G1的面积占比，相同。
在位于过渡区A22的第一过孔G1的孔径与位于元件设置区A21的第一过孔G1的孔径相同的情况下，位于过渡区A22的相邻两个第一过孔G1之间的间距，与位于元件设置区A21的相邻两个第一过孔G1之间的间距，相同。
这样可以使多个第一过孔G1在副显示区A2中实现均匀分布，有利于为有源层21中与副显示区A2相邻的部分提供均一的氢溢出环境，有利于使有源层21的不同部分具有接近的去氢量，进而使得不同位置处的显示像素电路C1的晶体管的阈值电压基本一致。
可以理解的是，第一过孔G1和副发光器件31b之间的位置关系包括多种，可以根据实际需要选择设置。
在一些实施例中，如图29所示，位于元件设置区A21中的部分第一过孔G1在衬底10上的正投影，和副发光器件31b在衬底10上的正投影无交叠。
也即，位于元件设置区A21中的部分第一过孔G1，和副发光器件31b错开设置。这样有利于提高副发光器件31b的结构稳定性。
在另一些实施例中，上述多个第一过孔G1中，部分第一过孔G1在衬底10上的正投影，位于副发光器件31b在衬底10上的正投影范围内。也即，该部分第一过孔G1会位于副发光器件31b下方。
可选地，位于副发光器件31b下方的第一过孔G1中，至少一个第一过孔G1和衬底10之间未设置冗余半导体图案21a。关于冗余半导体图案21a可以参见下文中的说明，此处不再赘述。
在一些实施例中，如图24所示，沿经过元件设置区A21的中心、且与副显示区A2的边界连线的方向，第一过孔G1的孔径，及第一过孔G1和副显示区A2的边界之间的间距，呈负相关。
也就是说，越靠近副显示区A2的边界的第一过孔G1的孔径越大，越远离副显示区A2的边界的第一过孔G1的孔径越小。沿经过元件设置区A21的中心、且与副显示区A2的边界连线的方向，随着第一过孔G1和副显示区A2的边界之间的间距增大，第一过孔G1的孔径逐渐减小。其中，第一过孔G1的孔径可以呈线性减小，也可以呈阶段性减小。
可以理解的是，在对有源层21进行去氢处理的过程中，从副显示区A2溢出的氢中，越靠近副显示区A2的边界的地方的氢含量越大，越远离副显示区A2的边界的地方的氢含量越小。
通过使第一过孔G1的孔径，与第一过孔G1和副显示区A2的边界之间的间距，呈负相关，可以使得氢含量大的区域对应较大的孔径，氢含量小的区域对应较小的孔径，这样有利于氢的充分溢出，进而实现充分的去氢效果，实现对显示像素电路C1中晶体管的阈值电压的良好改善效果。
在一些实施例中，第一过孔G1的分布密度的范围为1％～14％。
示例性的，上述分布密度为多个第一过孔G1在衬底10上的正投影面积之和，与该多 个第一过孔G1所占据的区域的面积的比值。
示例性的，第一过孔G1的分布密度可以为：1％、3％、5％、8％、11％或14％等。
此处，在第一过孔G1的分布密度为14％的情况下，第一过孔G1可以呈最密排布。此时，既可以确保对有源层21中与副显示区A2相邻的部分的去氢效果，又可以确保层间介质层223的结构稳定性。
可选地，在位于第一单位面积区域a的第一过孔G1的分布密度，小于或等于位于第二单位面积区域b的第一过孔G1的分布密度的情况下，随着与副显示区A2的边界之间的间距的增大，第一过孔G1的分布密度可以由14％逐渐降低至1％。
例如，第一过孔G1的分布密度可以按照14％、12％、10％、8％、6％、4％、2％、1％的顺序逐渐降低。
又如，第一过孔G1的分布密度可以按照14％、12％、10％、10％、6％、6％、2％、1％的顺序逐渐降低。
可选地，在位于过渡区A22的第一过孔G1的分布密度，与位于元件设置区A21的第一过孔G1的分布密度相同的情况下，第一过孔G1的分布密度可以为：1％、3％、5％、8％、11％或14％等。
在一些实施例中，如图14和图19所示，位于主显示区A1的第三过孔G3的分布密度，与位于副显示区A2的第一过孔G1的分布密度相同。
需要说明的是，如图14所示，由于第三过孔G3可以暴露有源层21中被掺杂的部分，能够在后续形成源漏导电层24后，使得源漏导电层24中的部分源漏导电图案通过第三过孔G3与有源层21形成电接触，以构成晶体管，因此，第三过孔G3在主显示区A1中的分布密度主要与显示基板100所包括的像素电路C中晶体管的数量相关。显示基板100所包括的晶体管的数量越多，第三过孔G3在主显示区A1中的分布密度也就越大。
通过使位于主显示区A1的第三过孔G3的分布密度，与位于过渡区A22的第一过孔G1的分布密度相同，可以使得有源层21中与副显示区A2相邻的部分和其他部分处于较为均一的环境中，从而使得位于不同位置的有源层21所包含的氢具有数量接近的溢出途径，进而可以保证有源层21在不同位置的去氢量较为接近。这样可以避免在不同位置处形成的晶体管的阈值电压之间产生较大的差异，从而可以使得不同位置处的像素电路传输至相应的发光器件的驱动电流基本相等，避免显示基板100的显示画面出现因驱动电流差异而导致的暗环问题。
在一些实施例中，位于主显示区A1的第三过孔G3的分布密度，小于位于副显示区A2的第一过孔G1的分布密度。
示例性的，第一过孔G1在过渡区A22中的分布密度可以按照相关工艺中所能实现的最大密度进行排布，这样可以保证有源层21中与副显示区A2的边界相邻的部分所包含的氢，在过渡区A22一侧具有足够充分的溢出途径，保证有源层21中与副显示区A2的边界相邻的部分具有较好的去氢效果，使得有源层21在不同位置的去氢量基本保持一致。避免在不同位置处形成的晶体管的阈值电压之间产生较大的差异，从而可以使得不同位置处的像素电路传输至相应的发光器件的驱动电流基本相等，避免显示基板100的显示画面出现因驱动电流差异而导致的暗环问题。
例如，第一过孔G1在过渡区A22中的分布密度为14％。
在一些实施例中，如图25所示，显示基板100所包括的多个像素电路C(例如显示像 素电路C1)呈多行多列排布。其中，环绕在副显示区A2周围的多行多列像素电路C中，每一行像素电路C中，有两个像素电路C分别位于副显示区A2的相对两侧，且相对于其他像素电路C更靠近副显示区A2；每一列像素电路C中，有两个像素电路C分别位于副显示区A2的相对两侧，且相对于其他像素电路C更靠近副显示区A2。
需要说明的是，图26中的虚线圆，可以用来表示上述环绕在副显示区A2周围的多行多列像素电路C中，最靠近副显示区A2的边界的各像素电路C，也可以用来表示最靠近副显示区A2的边界的各像素电路C的驱动晶体管T4。
在一些实施例中，如图24所示，最靠近副显示区A2的边界的各驱动晶体管T4，与副显示区A2之间的最小间距相同。
示例性的，最靠近副显示区A2的边界的各驱动晶体管T4所包括的有源图案与副显示区A2之间的最小间距相同。
需要说明的是，在上述多个像素电路C仅包括显示像素电路C1的情况下，最靠近副显示区A2边界的像素电路C则指的是显示像素电路C1。在上述多个像素电路C还包括其他电路的情况下，最靠近副显示区A2边界的像素电路C则指的是显示像素电路C1。上述显示像素电路C1可以通过驱动晶体管T4生成驱动电流，以驱动发光器件31发光。其中，驱动晶体管T4的阈值电压和提供至发光器件31的驱动电流相关，该驱动电流与发光器件31发出的光的亮度相关。
还需要说明的是，对于不同发光器件31发出的光的亮度不均一的现象，一般还可以利用外部光学补偿(demura)方法，补偿不同发光器件31之间的亮度差异。其中，demura方法中的关键一步是利用demura算法对不同发光器件31发出的光的亮度数据进行处理，从而生成不同发光器件31所需要的补偿数据，以补偿不同发光器件31发出的光的亮度之间的差异，改善显示画面不均一的现象。也即在面对上文中指出的暗环问题时，可以利用demura方法，对位于副显示区A2的边界附件的发光器件31发出的光的亮度进行补偿，使该部分发光器件31发出的光的亮度与其他部分发光器件31发出的光的亮度接近，从而消除暗环现象。
本实施例中，通过使最靠近副显示区A2的边界的各驱动晶体管T4，与副显示区A2之间的最小间距相同，可以使得各驱动晶体管T4所包括的有源图案与副显示区A2之间的最小间距基本相同。由此，在对上述各驱动晶体管T4的有源图案进行去氢处理的过程中，可以使得该各驱动晶体管T4的有源图案所面临的的第一过孔G1的分布情况基本相同，从而可以使得该各驱动晶体管T4的有源图案的去氢量基本相同。这样即使环绕副显示区A2的不同位置的驱动晶体管T4的阈值电压存在漂移，对应的漂移值也基本相同，在利用demura方法改善显示画面的暗环问题时，可以降低demura算法对不同发光器件31发出的光的亮度数据进行处理的难度，易于准确地生成不同发光器件31所需要的补偿数据，进而有助于消除暗环，提高显示画面的均一性。
在一些实施例中，如图27～图29所示，像素电路层20还包括位于副显示区A2的多个冗余半导体图案21a，该多个冗余半导体图案21a与有源层21同层设置。
需要说明的是，本文中提及的“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。
这样一来，可以在一次构图工艺中同时制作形成上述多个冗余半导体图案21a和有源层21，有利于简化显示基板100的制备工艺。
示例性的，上述多个冗余半导体图案21a的材料和有源层21的材料相同。
在一些示例中，如图28～图32所示，显示基板100还包括位于副显示区A2的多个第二过孔G2。每个第二过孔G2贯穿上述多层无机绝缘层22中的至少一层。
可选地，第二过孔G2的结构与第一过孔G1的结构相同。
在一些示例中，如图30和图31所示，上述多个第二过孔G2贯穿层间介质层223、第二栅绝缘层222和第一栅绝缘层221至冗余半导体图案21a远离衬底10一侧的表面。第二过孔G2会暴露冗余半导体图案21a的部分表面。
如图28和图29所示，上述多个第二过孔G2在衬底10上的正投影，位于冗余半导体图案21a在衬底10上的正投影范围内。
上述多个第二过孔G2在衬底10上的正投影和第一栅导电层23在衬底10上的正投影及第二栅导电层26在衬底10上的正投影之间无交叠，也即，各第二过孔G2和第一栅导电层23、第二栅导电层26错开设置。
可以理解的是，上述多个第二过孔G2可以位于过渡区A22，也可以位于元件设置区A21。其中，位于过渡区A22的部分第二过孔G2，可以称为第一过孔G1。
需要说明的是，由于第一栅导电层23、第二栅导电层26及源漏导电层24也基本位于副显示区A2以外的区域内，因此，冗余半导体图案21a在衬底10上的正投影，与第一栅导电层23、第二栅导电层26及源漏导电层24中的任一者在衬底10上的正投影无交叠。冗余半导体图案21a独立设置，未构成晶体管的一部分。
示例性的，如图29所示，副发光器件31b位于冗余半导体图案21a远离衬底10的一侧，且两者相互绝缘设置。另外，至少部分冗余半导体图案21a在衬底10上的正投影，位于副发光器件31b在衬底10上的正投影范围内。
也就是说，全部的冗余半导体图案21a在衬底10上的正投影，位于副发光器件31b在衬底10上的正投影范围内。或者，一部分冗余半导体图案21a在衬底10上的正投影，位于副发光器件31b在衬底10上的正投影范围内，另一部分冗余半导体图案21a在衬底10上的正投影和副发光器件31b在衬底10上的正投影无交叠。此时，与副发光器件31b在衬底10上的正投影无交叠的部分冗余半导体图案21a所对应的第二过孔G2，可以称为第一过孔G1。
在一些示例中，如图25所示，靠近元件设置区A21的边界的部分第一过孔G1的分布密度，大于或等于第二过孔G2的分布密度。
这样，有源层21中与副显示区A2相邻的部分所包含的氢，在脱氢工艺中，还可以通过多个第二过孔G2溢出，从而进一步增加了该部分有源层21的氢溢出途径，有利于增加去氢效率。通过使靠近元件设置区A21的边界的部分第一过孔G1的分布密度，大于或等于第二过孔G2的分布密度，可以改善有源层21中位于与副显示区A2相邻的部分的去氢量和其他部分的去氢量之间的差异，进而有利于改善暗环现象。
可选地，在位于第一单位面积区域a的第一过孔G1的分布密度，小于或等于位于第二单位面积区域b的第一过孔G1的分布密度的情况下，随着与副显示区A2的边界之间的间距的增大，第一过孔G1的分布密续逐渐降低，靠近元件设置区A21的边界的部分第一过孔G1的分布密度，例如降低至或接近第二过孔G2的分布密度。
需要说明的是，通过设置有冗余半导体图案21a，以改善有源层21的不同部分地去氢量差异。
在一些实施例中，如图25所示，像素电路层20还包括多个冗余像素电路C2，该多个冗余像素电路C2位于主显示区A1，且位于多个显示像素电路C11和副显示区A2之间。
示例性的，上述多个冗余像素电路C2与信号线(例如上文中提到的扫描信号线Gate、数据信号线Data、使能信号线EM等)及发光器件31的阳极电绝缘。也即，多个冗余像素电路C2均未与信号线(例如上文中提到的扫描信号线Gate、数据信号线Data、使能信号线EM等)进行耦接，多个冗余像素电路C2均未与发光器件31进行耦接。
采用上述设置方式，设置多个冗余像素电路C2，能够提升显示像素电路C1的显示均一性，避免显示像素电路C1产生阈值电压偏移的问题，从而可以解决发光器件31中，与靠近副显示区A2的边界的显示像素电路C1耦接的发光器件31出现的显示异常的问题。
由上述可知，显示画面所出现的暗环问题主要是由与副显示区A2的边界相邻的部分显示像素电路C1导致的，通过在多个显示像素电路C1和副显示区A2之间设置多个冗余像素电路C2，那么在对有源层21进行去氢处理的过程中，即使该多个冗余像素电路C2所对应的部分有源层21的去氢量和显示像素电路C1所对应的部分有源层21的去氢量之间存在差异，也可以避免影响发光器件31的发光亮度，且显示像素电路C1和副显示区A2的边界之间的距离较远，去氢量相对比较充分且一致，从而可以避免显示像素电路C1所包括的晶体管出现阈值电压的正偏现象，进而可以使得显示像素电路C1提供至与其电连接的发光器件31的驱动电流之间的差异较小，有助于避免显示画面出现暗环。
需要说明的是，如图16和图32所示，像素电路层20还包括平坦层25。该平坦层25可以填充第一过孔G1、第二过孔G2，以提供平坦的表面，确保副发光器件31b的结构稳定性。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种显示基板，具有主显示区和副显示区，所述主显示区至少部分围绕所述副显示区，所述副显示区包括元件设置区和围绕所述元件设置区的过渡区；
    所述显示基板包括：
    衬底，至少位于所述主显示区和所述副显示区；
    位于所述衬底一侧的像素电路层，所述像素电路层包括有源层及设置在所述有源层远离所述衬底一侧的多层无机绝缘层；所述有源层至少位于所述主显示区，且至少部分围绕所述副显示区，所述多层无机绝缘层至少位于所述主显示区和所述副显示区；
    多个第一过孔，至少位于所述过渡区，所述多个第一过孔贯穿所述多层无机绝缘层中的至少一层。
  2. 根据权利要求1所述的显示基板，其中，所述副显示区包括第一单位面积区域和第二单位面积区域，所述第一单位面积区域与所述副显示区的边界之间的间距，大于所述第二单位面积区域与所述副显示区的边界之间的间距；
    位于所述第一单位面积区域的第一过孔的分布密度，小于或等于位于所述第二单位面积区域的第一过孔的分布密度。
  3. 根据权利要求2所述的显示基板，其中，与所述副显示区的边界间距相同的至少两个第一单位面积区域内的第一过孔的分布密度相同；和/或，
    与所述副显示区的边界间距相同的至少两个第二单位面积区域内的第一过孔的分布密度相同。
  4. 根据权利要求1～3中任一项所述的显示基板，其中，位于所述副显示区的第一过孔均匀分布。
  5. 根据权利要求1～4中任一项所述的显示基板，其中，所述多个第一过孔位于所述过渡区；
    所述多个第一过孔中的至少部分第一过孔沿所述元件设置区的边界依次排列、呈环形设置。
  6. 根据权利要求1～4中任一项所述的显示基板，其中，所述像素电路层包括多个像素电路；
    所述多个第一过孔的一部分位于所述过渡区，所述多个第一过孔的另一部分位于所述元件设置区中至少靠近所述过渡区的部分区域；
    位于所述元件设置区中的部分第一过孔所占据的区域的最小尺寸，大于或等于一个像素电路的尺寸。
  7. 根据权利要求6所述的显示基板，其中，位于所述过渡区的部分第一过孔的分布密度，与位于所述元件设置区的部分第一过孔的分布密度相同。
  8. 根据权利要求6或7所述的显示基板，还包括：位于所述像素电路层远离所述衬底一侧的发光器件层；所述发光器件层包括位于所述副显示区的多个副发光器件；
    位于所述元件设置区中的部分第一过孔在所述衬底上的正投影，和所述多个副发光器件在所述衬底上的正投影无交叠。
  9. 根据权利要求1～8中任一项所述的显示基板，其中，所述第一过孔的分布密度的范围为1％～14％。
  10. 根据权利要求1～9中任一项所述的显示基板，其中，沿经过所述元件设置区的中心、且与所述副显示区的边界连线的方向，第一过孔的孔径，及所述第一过孔和所述副显 示区的边界之间的间距，呈负相关。
  11. 根据权利要求1～10中任一项所述的显示基板，其中，所述多层无机绝缘层包括沿远离所述有源层的方向依次层叠的第一栅绝缘层、第二栅绝缘层和层间介质层，至少一个所述第一过孔贯穿所述层间介质层、所述第二栅绝缘层和所述第一栅绝缘层。
  12. 根据权利要求11所述的显示基板，其中，所述像素电路层还包括位于所述副显示区的多个冗余半导体图案，所述多个冗余半导体图案与所述有源层同层设置；
    所述显示基板还包括：位于所述副显示区的多个第二过孔，第二过孔贯穿所述多层无机绝缘层中的至少一层；
    其中，所述多个第二过孔在所述衬底上的正投影，位于所述多个冗余半导体图案在所述衬底上的正投影范围内，所述过渡区的至少一个所述第二过孔为所述第一过孔。
  13. 根据权利要求12所述的显示基板，其中，所述多个第二过孔贯穿所述层间介质层、所述第二栅绝缘层和所述第一栅绝缘层至所述多个冗余半导体图案远离所述衬底一侧的表面。
  14. 根据权利要求12或13所述的显示基板，还包括：位于所述像素电路层远离所述衬底一侧的发光器件层；所述发光器件层包括位于所述副显示区的多个副发光器件；
    其中，所述多个第二过孔中的至少部分在所述衬底上的正投影，位于所述多个副发光器件在所述衬底上的正投影范围内。
  15. 根据权利要求12～14中任一项所述的显示基板，其中，所述多个第二过孔的一部分位于所述元件设置区；
    靠近所述元件设置区的边界的部分第一过孔的分布密度，大于或等于位于所述元件设置区的第二过孔的分布密度。
  16. 根据权利要求1～15中任一项所述的显示基板，还包括：至少位于所述主显示区的多个第三过孔；
    所述多个第三过孔贯穿所述多层无机绝缘层至所述有源层远离所述衬底一侧的表面；
    所述多个第三过孔的分布密度，小于或等于所述多个第一过孔的分布密度。
  17. 根据权利要求1～16中任一项所述的显示基板，其中，所述像素电路层包括多个像素电路，所述多个像素电路的至少一部分位于所述主显示区，位于所述主显示区的至少部分像素电路围绕所述副显示区；
    像素电路包括驱动晶体管，最靠近所述副显示区的边界的各驱动晶体管，与所述副显示区之间的最小间距相同。
  18. 根据权利要求1～16中任一项所述的显示基板，还包括：位于所述像素电路层远离所述衬底一侧的发光器件层，所述发光器件层包括位于所述主显示区的多个主发光器件和位于所述副显示区的多个副发光器件；
    所述像素电路层包括多个显示像素电路，所述多个显示像素电路包括多个第一显示像素电路和多个第二显示像素电路；
    所述多个第一显示像素电路位于所述主显示区，且分别与所述多个主发光器件电连接；
    所述多个第二显示像素电路位于所述主显示区，且分别通过导线与所述多个副发光器件电连接。
  19. 根据权利要求1～16中任一项所述的显示基板，具有显示区和围绕所述显示区的边框区，所述显示区包括所述主显示区和所述副显示区；
    所述显示基板还包括：位于所述像素电路层上的发光器件层，所述发光器件层包括位于所述主显示区的多个主发光器件和位于所述副显示区的多个副发光器件；
    所述像素电路层包括多个显示像素电路，所述多个显示像素电路包括多个第一显示像素电路和多个第二显示像素电路；
    所述多个第一显示像素电路位于所述主显示区，且分别与所述多个主发光器件电连接；
    所述多个第二显示像素电路位于所述所述边框区，且分别通过导线与所述多个副发光器件电连接。
  20. 根据权利要求18或19所述的显示基板，其中，所述像素电路层还包括多个冗余像素电路，所述多个冗余像素电路位于所述主显示区，且位于所述多个显示像素电路和所述副显示区之间。
  21. 一种显示装置，包括：
    如权利要求1～20中任一项所述的显示基板；及，
    光学元件，设置在所述显示基板的非出光侧，所述光学元件在所述显示基板上的正投影与所述显示基板的元件设置区至少部分交叠。
PCT/CN2022/089651 2022-04-27 2022-04-27 显示基板及显示装置 WO2023206164A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2022/089651 WO2023206164A1 (zh) 2022-04-27 2022-04-27 显示基板及显示装置
CN202280000924.4A CN117321767A (zh) 2022-04-27 2022-04-27 显示基板及显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/089651 WO2023206164A1 (zh) 2022-04-27 2022-04-27 显示基板及显示装置

Publications (1)

Publication Number Publication Date
WO2023206164A1 true WO2023206164A1 (zh) 2023-11-02

Family

ID=88516692

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/089651 WO2023206164A1 (zh) 2022-04-27 2022-04-27 显示基板及显示装置

Country Status (2)

Country Link
CN (1) CN117321767A (zh)
WO (1) WO2023206164A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170077188A1 (en) * 2015-09-11 2017-03-16 Samsung Display Co., Ltd. Organic light-emitting display apparatus
CN110874990A (zh) * 2019-12-02 2020-03-10 武汉天马微电子有限公司 一种显示面板和显示装置
CN111554693A (zh) * 2020-04-27 2020-08-18 上海天马有机发光显示技术有限公司 显示面板及其制备方法、显示装置
CN211929490U (zh) * 2020-03-31 2020-11-13 京东方科技集团股份有限公司 显示基板及显示面板
CN113314577A (zh) * 2021-05-26 2021-08-27 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置
CN114094030A (zh) * 2021-11-18 2022-02-25 京东方科技集团股份有限公司 显示基板及其制备方法、显示面板、显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170077188A1 (en) * 2015-09-11 2017-03-16 Samsung Display Co., Ltd. Organic light-emitting display apparatus
CN110874990A (zh) * 2019-12-02 2020-03-10 武汉天马微电子有限公司 一种显示面板和显示装置
CN211929490U (zh) * 2020-03-31 2020-11-13 京东方科技集团股份有限公司 显示基板及显示面板
CN111554693A (zh) * 2020-04-27 2020-08-18 上海天马有机发光显示技术有限公司 显示面板及其制备方法、显示装置
CN113314577A (zh) * 2021-05-26 2021-08-27 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置
CN114094030A (zh) * 2021-11-18 2022-02-25 京东方科技集团股份有限公司 显示基板及其制备方法、显示面板、显示装置

Also Published As

Publication number Publication date
CN117321767A (zh) 2023-12-29

Similar Documents

Publication Publication Date Title
US11812640B2 (en) Display substrate having a projection of the display layer located within a projection of a light shielding layer, display device and transparent display including the same
CN108695370B (zh) Oled基板及制作方法、显示装置
CN110289301B (zh) 显示基板及其制造方法、显示装置
US10665793B2 (en) Pixel definition layer having an incline for an organic light emitting device
US11985840B2 (en) Display substrate, manufacturing method thereof and display device
US20220005890A1 (en) An array substrate, a method for manufacturing the same, and a display device
WO2021093687A1 (zh) 显示基板及其制备方法、显示装置
US9960217B2 (en) Display panel and system for displaying images utilizing the same
WO2020224474A1 (zh) Tft背板及其制备方法、显示面板
US11257868B2 (en) Display substrate, fabricating method thereof and display device
US20220130943A1 (en) Display substrate and display apparatus
TW201809818A (zh) 顯示裝置
US20220262890A1 (en) Display substrate and display apparatus
US20220149137A1 (en) Display substrate, method for manufacturing same, and display apparatus
WO2021175312A1 (zh) 显示基板及其制备方法、显示装置
CN110854175B (zh) 阵列基板及其制备方法、显示面板
CN109599430B (zh) Oled基板及其制备方法、oled显示装置
US20210091155A1 (en) Transparent display panel and method for manufacturing the same, display device
WO2023206164A1 (zh) 显示基板及显示装置
US11930665B2 (en) Display substrate and manufacturing method thereof, and display apparatus
WO2022067551A1 (zh) 显示面板及显示装置
WO2021092752A1 (zh) 显示基板及其制作方法、显示装置
WO2023137766A1 (zh) 显示面板、显示模组及显示装置
WO2023206160A1 (zh) 显示面板及显示装置
US20230337479A1 (en) Display substrate and display device

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 202280000924.4

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22939017

Country of ref document: EP

Kind code of ref document: A1