WO2023206160A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2023206160A1
WO2023206160A1 PCT/CN2022/089643 CN2022089643W WO2023206160A1 WO 2023206160 A1 WO2023206160 A1 WO 2023206160A1 CN 2022089643 W CN2022089643 W CN 2022089643W WO 2023206160 A1 WO2023206160 A1 WO 2023206160A1
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WO
WIPO (PCT)
Prior art keywords
light
display area
pixel circuits
layer
display panel
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Application number
PCT/CN2022/089643
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English (en)
French (fr)
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WO2023206160A9 (zh
Inventor
谢涛峰
徐元杰
李双
黄耀
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/089643 priority Critical patent/WO2023206160A1/zh
Priority to CN202280000992.0A priority patent/CN117337630A/zh
Publication of WO2023206160A1 publication Critical patent/WO2023206160A1/zh
Publication of WO2023206160A9 publication Critical patent/WO2023206160A9/zh

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  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • a display panel having a display area, the display area including a main display area and a auxiliary display area, the main display area surrounding at least a part of the auxiliary display area;
  • the display panel includes : a base substrate, located at least in the display area; a pixel circuit layer, located on one side of the base substrate and at least in the display area, the pixel circuit layer including a plurality of surrounding pixel circuits, the plurality of surrounding pixel circuits
  • the pixel circuit is located in the main display area and at least partially surrounds the secondary display area;
  • the light blocking layer is located in the main display area and between the base substrate and the pixel circuit layer, the light blocking layer
  • the orthographic projection on the base substrate at least partially overlaps the orthographic projection of the plurality of surrounding pixel circuits on the base substrate.
  • the light-blocking layer includes a plurality of light-blocking patterns.
  • An orthographic projection of at least part of a surrounding pixel circuit on the base substrate is located within the orthographic projection range of a light blocking pattern on the base substrate.
  • the surround pixel circuitry includes drive transistors.
  • the orthographic projection of the active layer of the driving transistor on the base substrate is located within the orthographic projection range of the light blocking pattern on the base substrate.
  • the surround pixel circuit further includes a compensation transistor coupled to the drive transistor.
  • the orthographic projection of the active layer of the compensation transistor on the base substrate is located within the range of the orthographic projection of the light blocking pattern on the base substrate.
  • the plurality of surrounding pixel circuits are arranged in multiple columns along the first direction and in multiple rows along the second direction.
  • the light blocking patterns corresponding to at least two surrounding pixel circuits adjacent along the first direction are connected, and/or are connected along the second direction.
  • the light blocking patterns corresponding to at least two adjacent surrounding pixel circuits are connected.
  • the plurality of light-blocking patterns are connected to form an integrated structure.
  • the light blocking layer surrounds the secondary display area.
  • the light-blocking layer includes at least two concentrically arranged light-blocking rings.
  • Each light-blocking ring includes a plurality of connected light-blocking patterns, and the light-blocking ring surrounds at least part of the secondary display area.
  • the light blocking layer further includes at least one connection pattern. Two adjacent light blocking patterns are connected to each other through the connecting pattern.
  • the display panel further includes: a first voltage signal line and a transfer layer provided in the pixel circuit layer; the light blocking layer communicates with the first voltage signal through the transfer layer wire connection.
  • the material of the light blocking layer includes molybdenum or graphite.
  • the plurality of surrounding pixel circuits are arranged in multiple columns along the first direction and in multiple rows along the second direction.
  • first direction at least six columns of surrounding pixel circuits are provided on either side of the auxiliary display area.
  • second direction on either side of the auxiliary display area, at least six columns of surrounding pixel circuits are provided.
  • At least three rows of surrounding pixel circuits are provided on the side.
  • the plurality of pixel circuit layers further include a plurality of redundant pixel circuits.
  • the plurality of redundant pixel circuits are located in the main display area and surround at least a part of the secondary display area; the plurality of redundant pixel circuits are closer to the secondary display area than the surrounding pixel circuits.
  • the plurality of surrounding pixel circuits are arranged in multiple columns along the first direction and in multiple rows along the second direction; the plurality of redundant pixel circuits are arranged in at least one column along the first direction, Arranged in at least one row along the second direction.
  • the sum of the number of columns of surrounding pixel circuits and the number of columns of redundant pixel circuits provided on either side is greater than or equal to six columns.
  • the sum of the number of rows of the surrounding pixel circuits and the number of rows of the redundant pixel circuits provided on either side is greater than or equal to three rows.
  • the display panel further includes a plurality of first light-emitting devices located in the main display area;
  • the pixel circuit layer further includes a plurality of first pixel circuits located in the main display area.
  • the plurality of first pixel circuits are coupled to the plurality of first light-emitting devices; at least some of the plurality of surrounding pixel circuits surrounding the pixel circuits are first pixel circuits.
  • the display panel further includes a plurality of second light-emitting devices located in the secondary display area;
  • the pixel circuit layer further includes a plurality of second pixel circuits located in the main display area.
  • the plurality of second pixel circuits and the plurality of second light-emitting devices are connected through conductive lines; at least part of the plurality of surrounding pixel circuits surrounding the pixel circuits is the second pixel circuit.
  • the display panel further includes a plurality of second light-emitting devices located in the secondary display area; and the pixel circuit layer further includes a plurality of second pixel circuits located in the secondary display area. The plurality of second pixel circuits are coupled to the plurality of second light emitting devices.
  • the display panel also has a frame area located on at least one side of the display area and a plurality of second light-emitting devices located in the secondary display area;
  • the pixel circuit layer also includes a frame area located on the frame A plurality of second pixel circuits are provided in the area, and the plurality of second pixel circuits and the plurality of second light-emitting devices are coupled through conductive lines.
  • a display device including: the display panel according to any of the above embodiments.
  • the display device further includes: an optical element located on a side of the light-blocking layer away from the pixel circuit layer, and an orthographic projection of the optical element on the base substrate is located on the secondary side. within the display area.
  • Figure 1 is a structural diagram of a display device according to some embodiments of the present disclosure.
  • Figure 2 is a structural diagram of a display panel according to some embodiments of the present disclosure.
  • Figure 3a is a structural diagram of another display device according to some embodiments of the present disclosure.
  • Figure 3b is a structural diagram of yet another display device according to some embodiments of the present disclosure.
  • Figure 4a is a structural diagram of a display device in an implementation manner
  • Figure 4b is a schematic diagram of total reflection of light at the interface between the back film and the air in one implementation
  • Figure 4c is a structural diagram of a pixel circuit layer in a display panel in an implementation manner
  • Figure 4d is a schematic diagram of a “progressive dark ring” appearing on the display panel in one implementation
  • Figure 4e is a schematic diagram of the characteristic transfer line of the driving transistor in the display panel at the preset gray level of L64 in one implementation
  • Figure 4f is a schematic diagram of the characteristic transfer line of the driving transistor in the display panel at the preset gray level of L128 in one implementation
  • Figure 5 is a partial structural diagram of a display panel according to some embodiments of the present disclosure.
  • Figure 6a is a partial structural diagram of another display panel according to some embodiments of the present disclosure.
  • Figure 6b is a partial structural diagram of another display panel according to some embodiments of the present disclosure.
  • Figure 7 is a structural diagram of a pixel circuit and a light-emitting device according to some embodiments of the present disclosure.
  • Figure 8a is a top view of some film layers of a display panel according to some embodiments of the present disclosure.
  • Figure 8b is a top view of other film layers of a display panel according to some embodiments of the present disclosure.
  • Figure 9a is a top view of further film layers of a display panel according to some embodiments of the present disclosure.
  • Figure 9b is a top view of further film layers of a display panel according to some embodiments of the present disclosure.
  • Figure 10 is a top view of further film layers of a display panel according to some embodiments of the present disclosure.
  • Figure 11 is a top view of further film layers of a display panel according to some embodiments of the present disclosure.
  • Figure 12a is a top view of further film layers of a display panel according to some embodiments of the present disclosure.
  • Figure 12b is a top view of further film layers of a display panel according to some embodiments of the present disclosure.
  • Figure 13 is a top view of further film layers of a display panel according to some embodiments of the present disclosure.
  • Figure 14 is a top view of further film layers of a display panel according to some embodiments of the present disclosure.
  • Figure 15 is a top view of further film layers of a display panel according to some embodiments of the present disclosure.
  • Figure 16 is a structural diagram of a light blocking layer and substrate according to some embodiments of the present disclosure.
  • Figure 17 is a structural diagram of another light blocking layer and substrate according to some embodiments of the present disclosure.
  • Figure 18 is a structural diagram of a pixel circuit layer and a light blocking layer according to some embodiments of the present disclosure
  • Figure 19 is a top view of further film layers of a display panel according to some embodiments of the present disclosure.
  • Figure 20a is a top view of further film layers of a display panel according to some embodiments of the present disclosure.
  • Figure 20b is a top view of further film layers of a display panel according to some embodiments of the present disclosure.
  • Figure 21 is a top view of further film layers of a display panel according to some embodiments of the present disclosure.
  • Figure 22 is a top view of further film layers of a display panel according to some embodiments of the present disclosure.
  • Figure 23 is a top view of further film layers of a display panel according to some embodiments of the present disclosure.
  • Figure 24 is a top view of further film layers of a display panel according to some embodiments of the present disclosure.
  • Figure 25 is a top view of further film layers of a display panel according to some embodiments of the present disclosure.
  • Figure 26 is a top view of further film layers of a display panel according to some embodiments of the present disclosure.
  • Figure 27 is a top view of further film layers of a display panel according to some embodiments of the present disclosure.
  • Figure 28 is a top view of further film layers of a display panel according to some embodiments of the present disclosure.
  • Figure 29 is a top view of further film layers of a display panel according to some embodiments of the present disclosure.
  • Figure 30 is a cross-sectional view of a light blocking layer connected to a first voltage signal line according to some embodiments of the present disclosure.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • connection and its derivatives may be used.
  • some embodiments may be described using the term “connected” to indicate that two or more components are in direct physical or electrical contact with each other.
  • the embodiments disclosed herein are not necessarily limited by the content herein.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally interpreted to mean “when” or “in response to” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrase “if it is determined" or “if [stated condition or event] is detected” is optionally interpreted to mean “when it is determined" or “in response to the determination" or “on detection of [stated condition or event]” or “in response to detection of [stated condition or event]”.
  • vertical and “equal” include the stated situation and situations that are approximate to the stated situation, and the range of the approximate situation is within an acceptable deviation range, where the acceptable deviation Ranges are as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (ie, the limitations of the measurement system).
  • vertical includes absolute verticality and approximate verticality, wherein the acceptable deviation range of the approximate verticality may also be a deviation within 5°, for example.
  • “Equal” includes absolute equality and approximate equality, wherein the difference between the two that may be equal within the acceptable deviation range of approximately equal is less than or equal to 5% of either one, for example.
  • Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • the transistors used in the circuit structure can be thin film transistors (Thin Film Transistor, TFT for short), field effect transistors (Metal Oxide Semiconductor, MOS for short) or other characteristics.
  • thin film transistors are used as examples in the embodiments of the present disclosure for description.
  • the first electrode of each transistor used is one of the source electrode and the drain electrode
  • the second electrode of each transistor is the other of the source electrode and the drain electrode. Since the source and drain of the transistor may be symmetrical in structure, the source and drain of the transistor may be structurally indistinguishable. That is to say, the first electrode and the third electrode of the transistor in the embodiment of the present disclosure
  • the two poles can be structurally indistinguishable.
  • the transistor is a P-type transistor
  • the first electrode of the transistor is the source electrode
  • the second electrode is the drain electrode
  • the first electrode of the transistor is the drain electrode
  • the second pole is the source.
  • nodes such as the first node and the second node do not represent actual existing components, but represent the meeting points of relevant couplings in the circuit diagram. That is to say, these nodes are formed by the relevant couplings in the circuit diagram.
  • the transistors included in the circuit structure provided in the embodiments of the present disclosure may all be N-type transistors, or may all be P-type transistors, or some may be N-type transistors and the other may be P-type transistors.
  • N-type transistors or may all be P-type transistors, or some may be N-type transistors and the other may be P-type transistors.
  • Effective level refers to the level that enables the transistor to turn on. Among them, P-type transistors can be turned on under the control of low-level signals, and N-type transistors can be turned on under the control of high-level signals.
  • Some embodiments of the present disclosure provide a display panel 100 and a display device 1000.
  • the display panel 100 and the display device 1000 are introduced respectively below.
  • the display device 1000 may be any display device that displays text or images, whether moving (eg, video) or stationary (eg, still images). More specifically, it is contemplated that the display devices of the embodiments may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants, etc.
  • PDA handheld or portable computer
  • GPS receiver/navigator camera
  • MP4 video player video player
  • video camera game console
  • watch clock
  • calculator TV monitor
  • flat panel display computer monitor
  • automotive monitor e.g., odometer display, etc.
  • navigator cockpit controller and/or display
  • display of camera view e.g., display of rear view camera in vehicle
  • electronic photo electronic billboard or sign
  • projector construction Structure
  • packaging and aesthetic structure for example, for the display of an image of a piece of jewelry
  • the display device 1000 includes: a heat dissipation film 40.
  • the heat dissipation film 40 is located on the non-display side of the display device 1000 .
  • the non-display side of the display device 1000 refers to the side opposite to the side on which the display device displays a screen.
  • the heat in the display device 1000 can be dissipated through the heat dissipation film 40 in a timely manner, thereby preventing heat from accumulating inside the display device 1000 and thus affecting the display effect of the display device 1000 .
  • the heat dissipation film 40 may include a protective layer 41 , a heat dissipation layer 42 , a buffer layer 43 , a foam layer 44 , a mesh glue layer 45 , etc., which are stacked in sequence.
  • the material of the protective layer 41 may include release glue.
  • the protective layer 41 can play a certain protective role on the heat dissipation film 40 and the display panel 100 before the display panel 100 is assembled with the optical components mentioned below. During the assembly process of the display device 1000, for example, before assembling the optical elements, the protective layer 41 in the heat dissipation film 40 can be peeled off.
  • the material of the heat dissipation layer 42 may include copper foil.
  • the copper foil can be self-adhesive copper foil, double-conducting copper foil, single-conducting copper foil, etc.
  • the above-mentioned copper foils all have excellent conductivity.
  • the heat in the display panel 100 can be dissipated through the heat dissipation layer 42.
  • the copper foil can be dissipated through the heat dissipation layer 42.
  • the heat dissipation layer 42 can also play the role of electromagnetic shielding and electrostatic discharge for the pixel circuit layer 20 on one side of the base substrate 10 .
  • the material of the buffer layer 43 may include PET (Polyethylene Terephthalate, polyethylene terephthalate) or the like.
  • PET Polyethylene Terephthalate, polyethylene terephthalate
  • the buffer layer can buffer and dissipate external force impacts on the heat dissipation film 40 to avoid damage to the heat dissipation film 40 .
  • the material of the foam layer 44 may include polyurethane foam, conductive foam, aluminum foil foam, etc.
  • the above materials all have good thermal conductivity and can quickly dissipate the heat generated by the display panel 100 to prevent heat accumulation from affecting the display.
  • the panel 100 has adverse effects and causes the display effect to be degraded.
  • the material of the foam layer is relatively soft, it can protect the display panel 100 and absorb and buffer the external force when it impacts the display panel 100 to avoid damage to the display panel 100 .
  • the material of the grid glue layer 45 can be pressure-sensitive glue, which can bond the heat dissipation film 40 and the base substrate 10 to achieve fixation between the heat dissipation film 40 and the base substrate 10 .
  • the above-mentioned heat dissipation film 40 has an opening, and the opening is arranged opposite to the secondary display area A2.
  • the above-mentioned openings of the heat dissipation film 40 refer to the structural through holes of the heat dissipation film 40 formed after the heat dissipation film 40 peels off the protective layer 41 as shown in FIG. 3b.
  • the through hole penetrates the heat dissipation layer 42 , the buffer layer 43 , the foam layer 44 , and the mesh glue layer 45 .
  • the center of the opening of the heat dissipation film 40 may coincide with the center of the sub-display area A2, and the area of the opening of the heat dissipation film 40 may be greater than or equal to the area of the sub-display area A2.
  • the display device 1000 further includes an optical element 50 .
  • the optical element 50 may be a camera, an infrared sensor, a fingerprint sensor, or the like.
  • the optical element 50 is a camera as an example for description.
  • external light can pass through the part of the display device 1000 located in the secondary display area A2 and be incident on the camera, so that the camera can collect the light and realize the function of taking pictures.
  • the orthographic projection of the optical element 50 on the heat dissipation film 40 is located in the opening of the heat dissipation film 40 and the secondary display area A2.
  • the optical element 50 is arranged opposite to the opening of the heat dissipation film 40 , and the area of the orthographic projection of the optical element 50 on the heat dissipation film 40 is less than or equal to the area of the opening of the heat dissipation film 40 .
  • the optical element 50 is arranged opposite to the auxiliary display area A2, and the area of the orthogonal projection of the optical element 50 on the heat dissipation film 40 is less than or equal to the area of the auxiliary display area A2.
  • the heat dissipation film 40 is usually provided as a whole layer and is opaque.
  • an opening in the heat dissipation film 40 and making the orthographic projection of the optical element 50 on the heat dissipation film 40 be located within the opening and the sub-display area A2 external light can be prevented from being emitted by the heat dissipation film while passing through the sub-display area A2.
  • 40 blocks and normally enters the optical element 50, thereby ensuring that the optical element 50 collects enough light and ensuring that the optical element 50 can operate normally.
  • the display device 1000 further includes: a back film 60 located between the base substrate 10 and the heat dissipation film 40 .
  • the back film 60 can cover the surface of the base substrate 10 close to the heat dissipation film 40, thereby protecting the base substrate 10, the pixel circuit layer 20, the light-emitting device 30 and other structures to prevent the above structures from being damaged, ensuring that The display panel 100 displays normally.
  • the material of the back film 60 may be a light-transmitting material.
  • the light incident on one side of the back film 60 can pass through the back film 60 and emerge from the other side of the back film 60 .
  • external light can pass through the secondary display area A2 and the back film 60 of the display panel 100 in order, and be incident on the optical element 50, so that the optical element 50 can collect Sufficient light enables functions such as taking pictures.
  • the display device 1000 also includes a frame, a display driver IC (Integrated Circuit), and other electronic accessories.
  • a display driver IC Integrated Circuit
  • the above-mentioned display device 1000 includes: a display panel 100 .
  • the display panel 100 has a display area A, and a frame area F located on at least one side of the display area A.
  • the frame area F may surround a part of the display area A, that is, the frame area F may be located on one side, two sides, three sides, etc. of the display area A.
  • the frame area F can surround the display area A and surround the display area A.
  • the display area A of the display panel 100 includes a main display area A1 and a auxiliary display area A2, and the main display area A1 surrounds at least a part of the auxiliary display area A2.
  • the main display area A1 may surround a portion of the secondary display area A2.
  • the main display area A1 may surround the auxiliary display area A2 and surround the auxiliary display area A2.
  • the display area A and the sub-display area A2 have various shapes, and can be selected and set according to actual needs.
  • the shape of the display area A may be a rectangle, an approximately rectangle, a circle, an ellipse, etc.
  • the approximate rectangle is a rectangle in a non-strict sense, and its four inner corners may be rounded corners, for example, or a certain side may not be a straight line, for example.
  • the shape of the secondary display area A2 may also be a rectangle, an approximately rectangle, a circle, an ellipse, etc., and may be set according to actual requirements.
  • the shape of the sub-display area A2 is circular as an example.
  • the light transmittance of the portion of the display panel 100 located in the secondary display area A2 is greater than the light transmittance of the portion of the display panel 100 located in the main display area A1.
  • light can pass through the portion of the display panel 100 located in the sub-display area A2 and emit from one side of the display panel 100 to the other side of the display panel 100 .
  • the display panel 100 includes: a base substrate 10 , a pixel circuit layer 20 located on one side of the base substrate 10 , and a light emitting device layer 30 .
  • the substrate substrate 10 may be a flexible substrate.
  • the flexible substrate can be, for example, a PET substrate, a PEN (Polyethylene naphthalate two formic acid glycol ester, polyethylene naphthalate) substrate, or a PI (Polyimide, polyimide) substrate, or the like. Therefore, the above-mentioned display panel 100 is a flexible display panel.
  • the base substrate 10 is at least located in the display area A.
  • the base substrate 10 may be located in the display area A of the display panel 100 .
  • the base substrate 10 may be located in the display area A of the display panel 100 and the frame area F of the display panel 100 .
  • the pixel circuit layer 20 includes a plurality of pixel circuits 21 .
  • the light emitting device layer 30 includes a plurality of light emitting devices 31 .
  • the pixel circuit 21 has a variety of structures, and the configuration can be selected according to actual needs.
  • the structure of the pixel circuit 21 may include a "6T1C", “7T1C”, “6T2C” or “7T2C” structure.
  • T represents a transistor
  • the number in front of “T” represents the number of transistors
  • C represents a storage capacitor
  • the number in front of "C” represents the number of storage capacitors.
  • the structure of the pixel circuit 21 is a “7T1C” structure as an example for description.
  • FIG. 7 illustrates an equivalent circuit diagram of the pixel circuit 21.
  • the pixel circuit 21 includes: a first reset transistor T1, a second reset transistor T2, a switching transistor T3, a driving transistor T4, a compensation transistor T5, a first light emission control transistor T6, and a second light emission control transistor T7. and storage capacitor Cst.
  • the gate electrode of the first reset transistor T1 is coupled to the reset signal line Reset, the first electrode of the first reset transistor T1 is coupled to the first initial signal line Vinit1, and the first electrode of the first reset transistor T1 is coupled to the first initial signal line Vinit1.
  • the second pole is coupled to the fourth node N4, that is, coupled to the second pole of the compensation transistor T5.
  • the first reset transistor T1 is configured to be turned on under the control of the reset signal transmitted by the reset signal line Reset, and transmit the first initial signal received at the first initial signal line Vinit1 to the fourth node N4, to The fourth node N4 is reset.
  • the gate of the second reset transistor T2 is coupled to the first scanning signal line Gate1
  • the first electrode of the second reset transistor T2 is coupled to the second initial signal line Vinit2
  • the second reset transistor T2 The second pole is coupled to the first node N1, that is, coupled to the light-emitting device 31.
  • the second reset transistor T2 is configured to be turned on under the control of the first scanning signal transmitted by the first scanning signal line Gate1, and transmit the second initial signal received at the second initial signal line Vinit2 to the first Node N1 resets the first node N1.
  • the gate of the switching transistor T3 is coupled to the second scanning signal line Gate2, the first pole of the switching transistor T3 is coupled to the data line Data, and the second pole of the switching transistor T3 is coupled to the second node N2 coupled, that is, coupled to the first pole of the driving transistor T4.
  • the switching transistor T3 is configured to be turned on under the control of the second scanning signal transmitted by the second scanning signal line Gate2, and transmit the data signal received at the data line Data to the second node N2.
  • the gate of the driving transistor T4 is coupled to the fourth node N4, the first pole of the driving transistor T4 is coupled to the second node N2, and the second pole of the driving transistor T4 is coupled to the third node N3.
  • the driving transistor T4 is configured to be turned on under the control of the voltage of the fourth node N4, and transmit the signal (for example, a data signal) from the second node N2 to the third node N3.
  • the gate of the compensation transistor T5 is coupled to the second scanning signal line Gate2, and the first pole of the compensation transistor T5 is coupled to the third node N3, that is, coupled to the second pole of the driving transistor T4.
  • the second electrode of the compensation transistor T5 is coupled to the fourth node N4, that is, coupled to the gate of the driving transistor T4.
  • the compensation transistor T5 is configured to be turned on under the control of the second scanning signal transmitted by the second scanning signal line Gate2, and transmit the electrical signal (for example, a data signal) from the third node N3 to the fourth node N4.
  • the gate of the first light-emitting control transistor T6 is coupled to the enable signal line EM
  • the first electrode of the first light-emitting control transistor T6 is coupled to the voltage signal line VDD
  • the first light-emitting control transistor T6 The second pole is coupled to the second node N2.
  • the first light emission control transistor T6 is configured to be turned on under the control of the enable signal transmitted by the enable signal line EM, and transmit the voltage signal received at the first voltage signal line VDD to the second node N2.
  • the gate of the second light-emitting control transistor T7 is coupled to the enable signal line EM
  • the first electrode of the second light-emitting control transistor T7 is coupled to the third node N3
  • the second light-emitting control transistor T7 The second pole is coupled to the first node N1.
  • the second light emitting control transistor T7 is configured to be turned on under the control of the enable signal transmitted by the enable signal line EM, and transmit the electrical signal (eg voltage signal) from the third node N3 to the first node N1 .
  • the first pole of the storage capacitor Cst is coupled to the fourth node N4, and the second pole of the storage capacitor Cst is coupled to the first voltage signal line VDD.
  • the light-emitting device 31 may include an anode layer, a light-emitting functional layer, a cathode layer, etc., which are stacked in sequence.
  • the light-emitting functional layer may include a light-emitting layer.
  • the light-emitting functional layer may further include at least one of a hole injection layer, a hole transport layer, an electron transport layer and an electron injection layer.
  • the pixel driving circuit may be coupled to the anode layer of the light emitting device.
  • an electric field can be formed between the anode layer and the cathode layer of the light-emitting device 31, and the electric field can Different carriers (ie, holes and electrons) are driven to recombine in the light-emitting layer, thereby causing the light-emitting device 31 to emit light.
  • the working process of the pixel circuit 21 includes a reset phase, a data writing and compensation phase, and a light emitting phase in sequence.
  • the first reset transistor T1 under the control of the reset signal, the first reset transistor T1 is turned on, transmits the first initial signal to the fourth node N4, and resets the fourth node N4. Since the fourth node N4 is coupled to the first pole of the storage capacitor Cst, the gate of the driving transistor T4 and the second pole of the compensation transistor T5, when the fourth node N4 is reset, the reset of the storage capacitor Cst can be synchronized.
  • the first electrode, the gate electrode of the driving transistor T4 and the second electrode of the compensation transistor T5 are reset. Wherein, the driving transistor T4 can be turned on under the control of the first initial signal.
  • the second reset transistor T2 is turned on under the control of the first scan signal, and the switching transistor T3 and the compensation transistor T5 are turned on under the control of the second scan signal.
  • the second reset transistor T2 transmits the second start signal to the first node N1 to reset the first node N1. Since the first node N1 is coupled to the anode of the light-emitting device 31, when the first node N1 is reset, the anode of the light-emitting device 31 can be reset simultaneously.
  • the switching transistor T3 transmits the data signal to the second node N2, and the driving transistor T4 transmits the data signal from the second node N2 to the third node N3.
  • the compensation transistor T5 transmits the data signal from the third node N3 to the fourth node N4, and charges the driving transistor T4 until the compensation of the threshold voltage of the driving transistor T4 is completed.
  • the first light-emitting control transistor T6 and the second light-emitting control transistor T7 are turned on at the same time under the control of the enable signal.
  • the first light emission control transistor T6 transmits a voltage signal to the second node N2.
  • the driving transistor T4 transmits the voltage signal from the second node N2 to the third node N3.
  • the second light emission control transistor T7 transmits the voltage signal from the third node N3 to the first node N1.
  • a driving current can be generated, and the light-emitting device 31 emits light under the action of the driving current.
  • each light-emitting device 31 can emit light under the driving action of the corresponding pixel circuit 21.
  • the light emitted by the multiple light-emitting devices 31 cooperates with each other, so that the display panel 100 realizes the display function.
  • the present disclosure schematically illustrates the structure of the display panel 100 by taking the coupling of a pixel circuit 21 and a light-emitting device 31 as an example.
  • Figure 3a and Figure 3b only illustrate the positional relationship between the pixel circuit layer and the light-emitting device layer, and the positional relationship between the pixel circuit and the light-emitting device, and do not illustrate the specific film layer relationship between the pixel circuit and the light-emitting device. Connection relationship, therefore, Figure 3a and Figure 3b do not limit the specific film layer relationship and connection relationship between the pixel circuit and the light-emitting device.
  • the plurality of pixel circuits are located in areas other than the sub-display area A2.
  • the plurality of light-emitting devices 31 are located in the display area A of the display panel 100, where part of the light-emitting devices is located in the main display area and the other part is located in the secondary display area.
  • the light-emitting device 31 located in the main display area A1 is a first light-emitting device 31a
  • the light-emitting device 31 located in the sub-display area A2 is a second light-emitting device 31b.
  • the pixel circuit 21 coupled to the plurality of first light-emitting devices 31a is located in the main display area A1
  • the pixel circuit 21 coupled to the plurality of second light-emitting devices 31b is located in the main display area A1, the frame area F or the auxiliary display area A2.
  • the light-emitting devices 31 in the display area A of the display panel 100 emit light under the driving action of the pixel circuit 21, so that the display panel 100 realizes full-screen display.
  • the FDC area refers to the area opposite to the camera along the thickness direction of the display device. Therefore, the part of the full-screen display device located in the FDC area is configured to be light-transmissive, and the FDC area corresponds to, for example, the above-mentioned sub-display area A2.
  • the external light and the light emitted by the light-emitting device will reach the interface between the back film and the air (ie, the lower surface of the back film) after a series of refraction and/or reflection. Since the refractive index of the back film material is greater than that of air, when the incident angle of the light incident on the interface satisfies the total reflection condition, for example, when the incident angle of the light is greater than the critical angle, the light will be reflected in the above-mentioned Total reflection occurs at the interface and is reflected to the active layer of the transistor in the pixel driving circuit located in the peripheral area of the FDC area, thereby causing the threshold voltage of the transistor in the pixel driving circuit to shift.
  • the above-mentioned light will cause the threshold voltage of the driving transistor to drift, and then during the light-emitting stage of the pixel driving circuit, it is easy to reduce the driving current provided by the driving transistor to the light-emitting device, thereby causing the FDC region to
  • the brightness of the display screen in the surrounding area decreases, and a "progressive dark ring" phenomenon appears as shown in Figure 4d. This phenomenon generally continues to occur 5 minutes after the display device starts displaying the image, and does not gradually disappear until about 6 hours after the display device is turned off.
  • the incident angle of the light incident on the interface between the back film and the air is set to ⁇
  • the refraction angle is ⁇ .
  • the incident angle ⁇ 44°. That is to say, the critical angle is 44°.
  • the peripheral area of the FDC area is an area within a distance of 96 ⁇ m from the boundary line of the FDC area.
  • the active layers of the driving transistors in the peripheral area of the FDC area will be affected by the light, causing the threshold voltage of the above-mentioned driving transistors to drift, and then during the light-emitting stage of the pixel driving circuit, it is easy for the driving transistors to provide light to the light-emitting device.
  • the driving current decreases, which further reduces the brightness of the display screen in the peripheral area of the FDC area, causing a "progressive dark ring" phenomenon as shown in Figure 4d.
  • the preset gray level L64 As an example, refer to Table 1.
  • the threshold voltage Vth of the driving transistor drifts from -2.7 to -2.1, the driving current provided by the driving transistor changes from 2.092 to 1.54.
  • the change percentage of the driving current changes from -4.80% to -5.15%, and the actual display brightness changes from 22.72 to 16.72.
  • the threshold voltage of the driving transistor drifts, which in turn causes the actual display brightness of the light-emitting device to change (that is, the display brightness decreases).
  • There is a brightness difference that can be recognized by the human eye which is the "progressive dark ring" phenomenon mentioned above.
  • the gate voltage Vg of the driving transistor and the driving The current I is simulated and tested, and the simulation results are drawn into its corresponding characteristic curve Vg-I, as shown in Figure 4e.
  • the gate voltage Vg and driving current of the driving transistor I conduct simulation testing, and draw the simulation results into its corresponding characteristic curve Vg-I, as shown in Figure 4f.
  • the drift of the threshold voltage of the driving transistor can significantly change the corresponding driving current, which in turn reduces the actual luminous brightness of the light-emitting device and leads to the phenomenon of "progressive dark ring".
  • the pixel circuit layer 20 is located at least in the display area A, and the multiple pixel circuits 21 in the pixel circuit layer 20 include: multiple surrounding pixels Circuit 21a.
  • pixel circuit layer 20 may be entirely located in display area A.
  • the pixel circuit layer 20 may be entirely located in the main display area A1.
  • the pixel circuit layer 20 may be partially located in the main display area A1 and partially located in the secondary display area A2.
  • the pixel circuit layer 20 may be partially located in the display area A and partially located in other areas of the display panel 100, such as in the frame area F.
  • the plurality of pixel circuits 21 located in the main display area A1 may all be surrounding pixel circuits 21a.
  • the plurality of pixel circuits 21 located in the main display area A1 may also include a plurality of surrounding pixel circuits 21a and a plurality of other pixel circuits. Details of other pixel circuits can be found in the description below, and will not be described again here.
  • the plurality of surrounding pixel circuits 21a are arranged in an array.
  • the plurality of surrounding pixel circuits 21a are arranged in multiple columns along the first direction X, and are arranged in multiple rows along the second direction Y.
  • the angle between the first direction X and the second direction Y may be 80°, 85°, 90°, 95° or 100°.
  • this disclosure takes as an example that the angle between the first direction X and the second direction Y is 90°.
  • a plurality of surrounding pixel circuits 21 a are located in the main display area A1 of the display panel 100 .
  • the plurality of surrounding pixel circuits 21a include, for example, a plurality of first surrounding pixel circuits 212a and a plurality of second surrounding pixel circuits 214a.
  • the first surrounding pixel circuit 212a is coupled to the first light-emitting device 31a located in the main display area A1
  • the second surrounding pixel circuit 214a is coupled to the second light-emitting device 31b located in the secondary display area A2. .
  • FIG. 5 only illustrates part of the connection between the second surrounding pixel circuit 214a and the corresponding second light-emitting device 31b.
  • the plurality of surrounding pixel circuits 21a may all be located in the main display area A1 of the display panel 100 .
  • the first surrounding pixel circuit 212 a and the second surrounding pixel circuit 214 a may be arranged in multiple columns along the first direction X and in multiple rows along the second direction Y. At least one column of first surrounding pixel circuits 212a may be arranged between two adjacent columns of second surrounding pixel circuits 214a. In this way, it is possible to avoid disposing the pixel circuit 21 coupled to the second light-emitting device 31b in the frame area F of the display panel 100, reduce the width of the frame area F in the display panel 100, and thereby increase the screen occupancy of the display panel 100 and the display device 1000. This ratio is beneficial to realizing full-screen display of the display panel 100 and the display device 1000 .
  • the plurality of surrounding pixel circuits 21a may surround part of the sub-display area A2. As another example, the plurality of surrounding pixel circuits 21a may completely surround the sub-display area A2.
  • the display panel 100 further includes: a light-blocking layer 70 located between the base substrate 10 and the pixel circuit layer 20 .
  • the light blocking layer 70 may be located in the main display area A1 of the display panel 100 .
  • the light-blocking layer 70 can reflect or absorb the light incident on its surface, and the light can basically not pass through the light-blocking layer 70 from one side of the light-blocking layer 70 and exit from the other side of the light-blocking layer 70 .
  • the orthographic projection of the light blocking layer 70 on the base substrate 10 at least partially overlaps the orthographic projection of the plurality of surrounding pixel circuits 21 a on the base substrate 10 .
  • a part of the orthographic projection of the surrounding pixel circuit 21 a on the base substrate 10 coincides with a part of the orthographic projection of the light blocking layer 70 on the base substrate 10 . That is to say, a part of the surrounding pixel circuit 21 a is arranged corresponding to the light blocking layer 70 , and a part of the orthographic projection of the surrounding pixel circuit 21 a on the base substrate 10 is at least the same as the orthographic projection of the light blocking layer 70 on the base substrate 10 . Partially overlapped.
  • the part surrounding the orthographic projection of the pixel circuit 21 a on the base substrate 10 includes surrounding the orthographic projection of the active layer of at least one transistor in the pixel circuit 21 a on the base substrate 10 .
  • this part of the light can be prevented from irradiating the part of the surrounding pixel circuit 21a corresponding to the light-blocking layer 70 (
  • the active layer surrounding at least one transistor in the pixel circuit 21a can alleviate the threshold voltage drift problem of the surrounding pixel circuit 21a, thereby slowing down the decrease in the driving current of the surrounding pixel circuit 21a, slowing down the decrease in display brightness, and slowing down the display
  • the panel 100 and the display device 1000 exhibit a “progressive dark ring” phenomenon.
  • the orthographic projection of the surrounding pixel circuit 21 a on the base substrate 10 is located within the range of the orthographic projection of the light blocking layer 70 on the base substrate 10 . That is to say, the entire surrounding pixel circuit 21a is arranged corresponding to the light-blocking layer 70, and at least a part of the orthographic projection of the surrounding pixel circuit 21a on the base substrate 10 is at least the same as the orthographic projection of the light-blocking layer 70 on the base substrate 10. Partially overlapped.
  • the orthographic projection of the surrounding pixel circuit 21 a on the base substrate 10 includes surrounding the orthographic projection of a plurality of transistors included in the pixel circuit 21 a on the base substrate 10 .
  • the light-blocking layer 70 can block the area surrounding all the transistors in the pixel circuit 21a, as shown in FIG. 9a, which can simplify the manufacturing process of the light-blocking layer 70.
  • the orthographic projection of the surrounding pixel circuit 21 a on the base substrate 10 includes the orthographic projection of the active layers of the plurality of transistors included in the surrounding pixel circuit 21 a on the base substrate 10 .
  • the light-blocking layer 70 can be patterned, as shown in FIG. 9b , to block only the active layer surrounding each transistor in the pixel circuit 21a.
  • the threshold voltage drift problem can be slowed down or even eliminated, thereby slowing down or even eliminating the decrease in the driving current of the surrounding pixel circuit 21a, slowing down or even eliminating the decrease in display brightness, and further slowing down or even eliminating the "progressive dark ring" appearing on the display panel 100 and the display device 1000. "Phenomenon.
  • a plurality of pixel circuit layers 20 surrounding the orthographic projection of the pixel circuit 21 a on the base substrate 10 are located within the range of the orthographic projection of the light blocking layer 70 on the base substrate 10 .
  • the light blocking layer 70 can be used to block the part of the light that is totally reflected and emitted to the interior of the display panel 100, preventing it from irradiating the plurality of surrounding pixel circuits 21a, thereby slowing down the threshold of the surrounding pixel circuit 21a.
  • the voltage drift problem slows down or even eliminates the reduction of the driving current surrounding the pixel circuit 21a, thereby slowing down or even eliminating the reduction in display brightness, and further slows down or even eliminates the "progressive dark ring" phenomenon in the display panel 100 and the display device 1000.
  • the light blocking layer 70 includes a plurality of light blocking patterns 71 .
  • An orthographic projection of at least part of the surrounding pixel circuit 21 a on the base substrate 10 is located within the range of an orthographic projection of the light blocking pattern 71 on the base substrate 10 .
  • the orthographic projection of a part or the entire surrounding pixel circuit 21 a on the base substrate 10 is located within the range of the orthographic projection of the light blocking pattern 71 on the base substrate 10 .
  • the orthographic projection of a portion of a transistor in the surrounding pixel circuit 21 a on the base substrate 10 is located within the range of the orthographic projection of a light blocking pattern 71 on the base substrate 10 .
  • the orthographic projection of a transistor in a surrounding pixel circuit 21 a on the base substrate 10 is located within the range of the orthographic projection of a light blocking pattern 71 on the base substrate 10 .
  • the orthographic projection of a portion surrounding multiple transistors in the pixel circuit 21 a on the base substrate 10 is located within the range of the orthographic projection of a light blocking pattern 71 on the base substrate 10 .
  • the orthographic projection of all the transistors in the surrounding pixel circuit 21 a on the base substrate 10 is located within the range of the orthographic projection of the light blocking pattern 71 on the base substrate 10 .
  • the light blocking pattern 71 can have various shapes and can be set according to the actual situation.
  • the shape of the light blocking pattern 71 may be a polygon, a polygonal shape, or the like.
  • each light blocking pattern 71 corresponds to one surrounding pixel circuit 21a.
  • a light blocking pattern 71 is disposed facing at least part of a surrounding pixel circuit 21a.
  • the plurality of surrounding pixel circuits 21a surround the sub-display area A2, and the plurality of light-blocking patterns 71 in the light-blocking layer 70 are arranged corresponding to the plurality of surrounding pixel circuits 21a, therefore, the plurality of light-blocking patterns 71 in the light-blocking layer 70 Set around the secondary display area A2.
  • the surround pixel circuit 21a may include a drive transistor T4.
  • the orthographic projection of the active layer of the driving transistor T4 on the base substrate 10 is located within the range of the orthographic projection of the light blocking pattern 71 on the base substrate 10 .
  • the part surrounding the pixel circuit 21a refers to, for example, the active layer of the driving transistor T4.
  • the boundary line of the orthographic projection of the active layer of the driving transistor T4 on the base substrate 10 is located within the boundary line of the orthographic projection of the light blocking pattern 71 on the base substrate 10 .
  • the boundary line of the orthographic projection of the active layer of the driving transistor T4 on the base substrate 10 at least partially coincides with the boundary line of the orthographic projection of the light blocking pattern 71 on the base substrate 10 .
  • the active layer of the driving transistor T4 of the circuit 21a can slow down the drift of the threshold voltage of the driving transistor T4, slow down the decrease in the driving current of the surrounding pixel circuit 21a, thereby slowing down the decrease in display brightness, and slow down the display panel 100 And the display device 1000 exhibits a “progressive dark ring” phenomenon.
  • the surrounding pixel circuit 21a further includes: a compensation transistor T5 coupled to the driving transistor T4.
  • the orthographic projection of the active layer of the compensation transistor T5 on the base substrate 10 is located within the range of the orthographic projection of the light blocking pattern 71 on the base substrate 10 .
  • the portion surrounding the pixel circuit 21a refers to, for example, the active layer of the driving transistor T4 and the active layer of the compensation transistor T5.
  • the orthographic projection of the active layer of the compensation transistor T5 on the base substrate 10 is located within the boundary line of the orthographic projection of the light blocking pattern on the base substrate 10 .
  • the boundary line of the orthographic projection of the active layer of the compensation transistor T5 on the base substrate 10 at least partially coincides with the boundary line of the orthographic projection of the light blocking pattern on the base substrate 10 .
  • the drift phenomenon of the threshold voltage of the driving transistor T4 and the compensation transistor T5 can be slowed down, thereby slowing down the decrease in the driving current of the surrounding pixel circuit 21a. , slowing down the decrease in display brightness, and further slowing down the "progressive dark ring" phenomenon in the display panel 100 and the display device 1000 .
  • the active layer of the driving transistor T4 and the active layer of the compensation transistor T5 in the same surrounding pixel circuit 21a can be arranged corresponding to the same light-blocking pattern 71. That is to say, the active layer of the driving transistor T4 and the active layer of the compensation transistor T5 in the same surrounding pixel circuit 21 a are located within the range of the orthographic projection of a light blocking pattern 71 on the base substrate 10 .
  • the threshold voltages of the drive transistors and compensation transistors in the pixel drive circuit drift under the influence of light. Then, during the data writing and compensation stages, the data signals transmitted by the compensation transistors will not be able to Complete effective compensation for the threshold voltage of the driving transistor. For example, after compensation, the voltage of the fourth node is too high, resulting in insufficient conduction of the driving transistor, which in turn causes the driving current generated by the driving transistor to be smaller during the light-emitting phase, thus causing the light to emit light. The display brightness of the device decreases, causing a "progressive dark ring" phenomenon in display panels and display devices.
  • the present disclosure adopts the above arrangement method, and sets the orthographic projection of the active layer of the driving transistor T4 and the active layer of the compensation transistor T5 on the base substrate 10 to be within the range of the orthographic projection of the light blocking pattern 71 on the base substrate 10 . Therefore, after the external light and the light emitted by the light-emitting device, after a series of refraction and/or reflection, are incident on the interface between the back film 60 and the air, part of the light is totally reflected at the interface and then directed to the display. Interior of panel 100 .
  • This part of the light after total reflection will be blocked by the light-blocking pattern 71 in the light-blocking layer 70 before being incident on at least one active layer of the driving transistor T4 and the active layer of the compensation transistor T5 in the surrounding pixel circuit 21a. , it can be prevented from irradiating the active layer of the driving transistor T4 and the active layer of the compensation transistor T5 in one or more surrounding pixel circuits 21a, thereby slowing down the drift phenomenon of the threshold voltage of the driving transistor T4 and the compensation transistor T5, and thus The compensation transistor T5 can be made to effectively compensate the threshold voltage of the driving transistor T4, thereby slowing down the decrease in the driving current of the surrounding pixel circuit 21a, thereby slowing down the decrease in display brightness, and further slowing down the occurrence of the problem in the display panel 100 and the display device 1000. "Progressive dark ring" phenomenon.
  • the above-mentioned light-blocking layer 70 has a variety of structures, and the light-blocking pattern 71 in the light-blocking layer 70 has a variety of arrangement methods, and the arrangement can be selected according to actual needs.
  • the multiple light-blocking patterns 71 in the light-blocking layer may be independent of each other and not connected to each other.
  • the multiple light-blocking patterns 71 in the light-blocking layer 70 may all be unconnected light-blocking patterns 71 .
  • the light blocking layer 70 further includes at least one connection pattern 72 .
  • Two adjacent light blocking patterns 71 are connected to each other through the connecting pattern 72 .
  • connection pattern 72 may be a strip pattern extending in a certain direction to connect two adjacent light blocking patterns 71 together.
  • the plurality of light-blocking patterns 71 in the light-blocking layer 70 may all be two adjacent light-blocking patterns 71 connected to each other, or all of the plurality of light-blocking patterns 71 adjacent in sequence may be connected to each other.
  • some of the light-blocking patterns 71 may be unconnected between adjacent light-blocking patterns 71 , while the remaining part of the light-blocking patterns may be between adjacent light-blocking patterns 71 . connected.
  • the light blocking patterns 71 corresponding to at least two surrounding pixel circuits 21a adjacent along the first direction X are connected.
  • the outer contours of the connected light blocking patterns 71 may extend along the first direction X. All connected light blocking patterns 71 may be arranged in multiple rows.
  • the light blocking patterns 71 corresponding to the two surrounding pixel circuits 21a adjacent along the first direction X are not connected. That is to say, in the same row of light-blocking patterns, two adjacent light-blocking patterns 71 located on opposite sides of the sub-display area A2 will not be connected through the sub-display area A2. In this way, light blocking can be avoided.
  • the pattern 71 has a negative impact on the light transmittance of the sub-display area A2 and avoids reducing the light transmittance of the sub-display area A2, so that the optical element 50 located in the sub-display area A2 can collect enough light, thereby allowing the display panel 100 and The display device 1000 achieves better photographing effects.
  • the light blocking patterns 71 corresponding to at least two surrounding pixel circuits 21a adjacent along the second direction Y are connected.
  • the outer contours of the connected light-blocking patterns 71 may extend along the second direction Y. All connected light blocking patterns 71 may be arranged in multiple columns.
  • the light blocking patterns 71 corresponding to the two surrounding pixel circuits 21a adjacent along the second direction Y are not connected. That is to say, in the same column of light-blocking patterns, two adjacent light-blocking patterns 71 located on opposite sides of the sub-display area A2 will not be connected through the sub-display area A2 along the second direction Y.
  • At least four light-blocking patterns 71 among the plurality of light-blocking patterns 71 included in the light-blocking layer 70 can be in the first direction X and the second direction Y. They are all connected to each other through connection patterns 72 .
  • a plurality of light-blocking patterns 71 included in the light-blocking layer 71 are connected to form an integrated structure.
  • the light blocking layer 70 surrounds the secondary display area A2.
  • one-piece structure means that multiple connected patterns are arranged on the same layer, and the two patterns are continuous and not separated.
  • a plurality of light-blocking patterns 71 that are partially connected may be arranged in sequence along the first direction X, and/or the plurality of light-blocking patterns 71 that are partially connected may be arranged along a The second direction Y extends, and/or the remaining connected plurality of light blocking patterns 71 may extend in any direction except the first direction and the second direction.
  • the overall outline formed by all connected light blocking patterns 71 may surround at least a part of the secondary display area A2.
  • the light-blocking pattern 71 in the light-blocking layer 70 may be an overall pattern, which is provided corresponding to the surrounding pixel circuit 21a in the display panel 100.
  • This overall pattern means that, except for the hollow area located in the secondary display area A2, there are no hollow structures in the remaining areas. Therefore, the manufacturing process of the light-blocking layer 70 in the display panel 100 can be simplified, and at the same time, the blocking effect of the light-blocking layer 70 on the light incident on the pixel circuit layer 20 can be improved.
  • the light-blocking pattern 71 in the light-blocking layer 70 may be an overall pattern.
  • the other areas may also have a hollow structure, so that only part of the structure in the pixel circuit 21 such as the area where the active layer is located is blocked. Therefore, the usage amount of material of the light blocking layer 70 can be reduced.
  • the light-blocking layer 70 includes at least two concentrically arranged light-blocking rings.
  • the light-blocking ring includes a plurality of connected light-blocking patterns, and the light-blocking ring surrounds at least part of the secondary display area A2.
  • the centers of the multiple light blocking rings may coincide with the center of the secondary display area A2.
  • the light-blocking ring can be a closed shape, such as a circle, an ellipse, a rectangle, etc.
  • the light-blocking ring may surround the entire sub-display area A2.
  • the light-blocking ring may also be a non-closed shape, such as a part of a circle or a rectangle.
  • the light blocking ring may surround part of the secondary display area A2.
  • the light-blocking ring is a closed circle as an example.
  • the light-blocking layer 70 may include two or more light-blocking rings arranged concentrically.
  • the threshold voltage drift problem of the circuit 21a can further slow down the reduction of the driving current of the surrounding pixel circuit, thereby slowing down the reduction of the display brightness in the area surrounding the sub-display area A2, and further reduce the occurrence of the problem of the display panel 100 and the display device 1000. "Progressive dark ring" phenomenon.
  • the light blocking layer 70 includes two concentrically arranged Among the one or more light-blocking rings, the difference between the outer diameter of the largest light-blocking ring and the inner diameter of the smallest light-blocking ring is at least (96 ⁇ 2) ⁇ m, that is, 192 ⁇ m.
  • the pixel circuit 21 that is illuminated can be Blocking can avoid the impact of light on the threshold voltage of the pixel circuit, thereby slowing down the decrease in the driving current of the pixel circuit, thereby slowing down the decrease in display brightness in the area surrounding the sub-display area A2, and further slowing down the display panel 100 and the display Device 1000 exhibits a "progressive dark ring" phenomenon.
  • At least six columns of surrounding pixel circuits 21 a are provided on either side of the opposite sides of the sub-display area A2 .
  • at least three rows of surrounding pixel circuits 21a are provided on either side of the opposite sides of the sub-display area A2.
  • each column of surrounding pixel circuits 21a is provided on either side of the opposite sides of the sub-display area A2.
  • the refractive index of the material of the back film 60 is 1.45, and the distance from the active layer in the pixel circuit layer 20 to the interface between the back film and the air is 11 ⁇ m, the external light and After a series of refraction and/or reflection, the light emitted by the light-emitting device 31 can be illuminated in an area 96 ⁇ m away from the boundary line of the secondary display area A2. Taking the size of a pixel circuit along the first direction The size in the direction X, and the size along the second direction Y corresponding to the three rows of pixel circuits 21.
  • the present disclosure adopts the above-mentioned arrangement method.
  • the light-blocking layer 70 allows the light-blocking layer 70 to block the corresponding at least six columns of surrounding pixel circuits 21a, preventing the light incident on the interface between the back film 60 and the air from being totally reflected and then incident on the at least six columns of surrounding pixel circuits 21a.
  • the pixel circuit 21a prevents the active layer of the transistors in the at least six columns of surrounding pixel circuit 21a from being exposed to light, prevents the threshold voltage of the transistors in the above-mentioned at least six columns of surrounding pixel circuit 21a from drifting, and avoids coupling with the above-mentioned at least six columns of surrounding pixel circuit 21a.
  • the display brightness of the light-emitting device 31 is reduced.
  • the light-blocking layer 70 is correspondingly provided in the area of the at least three rows of surrounding pixel circuits 21a.
  • the light-blocking layer 70 blocks the corresponding at least three rows of surrounding pixel circuits, preventing the light incident on the interface between the back film 60 and the air from being totally reflected and then incident on the at least three rows of surrounding pixel circuits 21a, thus preventing the at least three rows of surrounding pixel circuits 21a from being completely reflected.
  • the active layer of the transistor in the pixel circuit 21a is exposed to light, thereby preventing the threshold voltage of the transistor in the at least three rows of surrounding pixel circuit 21a from drifting, and preventing the display brightness of the light-emitting device coupled to the at least three rows of surrounding pixel circuit 21a from decreasing, thereby preventing A “progressive dark ring” phenomenon occurs in the display panel 100 and the display device 1000 .
  • the plurality of pixel circuits in the pixel circuit layer 20 further include: a plurality of first pixel circuits 21b located in the main display area A1.
  • the first pixel circuit 21b may be coupled to the first light-emitting device 31a located in the main display area A1, thereby providing a driving signal to the first light-emitting device 31a to drive the first light-emitting device 31a to emit light.
  • the orthographic projections of the plurality of first pixel circuits 21b on the base substrate 10 and the orthographic projections of the plurality of first light-emitting devices 31a on the base substrate 10 at least partially overlap.
  • the first pixel circuit 21b is disposed facing the corresponding first light-emitting device 31a.
  • the first pixel circuit 21b is disposed facing the corresponding part of the first light-emitting device 31a. That is, the first light emitting device 31a is directly above or near the first pixel circuit 21b.
  • At least part of the surrounding pixel circuits 21a among the plurality of surrounding pixel circuits 21a is the first pixel circuit 21b. That is to say, at least part of the surrounding pixel circuit 21a and the light-emitting device 31 driven by it are arranged facing each other or partially facing each other.
  • the plurality of pixel circuits in the pixel circuit layer 20 further include: a plurality of second pixel circuits 21d.
  • a plurality of second pixel circuits 21d are located in the main display area A1.
  • the plurality of second pixel circuits 21d and the plurality of second light emitting devices 31b are coupled through conductive lines.
  • the second pixel circuit 21d may be coupled to the second light-emitting device 31b located in the sub-display area A2, thereby providing a driving signal to the second light-emitting device 31b to drive the second light-emitting device 31b to emit light.
  • At least part of the surrounding pixel circuits 21a among the plurality of surrounding pixel circuits 21a is the second pixel circuit 21d. That is to say, conductive wires are also required to connect the partial surrounding pixel circuit 21a and the corresponding light-emitting device 31.
  • a plurality of second pixel circuits 21d are located in the secondary display area A2.
  • the arrangement density of the plurality of second pixel circuits 21d located in the sub-display area A2 is smaller than the arrangement density of the multiple pixel circuits 21 located in the display area A.
  • the area occupied by the second pixel circuit 21d located in the sub-display area A2 on the display panel 100 is smaller than the area occupied by the pixel circuit 21 located in the display area A on the display panel 100.
  • the light transmittance of the secondary display area A2 in the display panel 100 can be greater than the light transmittance of the main display area A1 in the display panel 100 , thereby enabling the optical element 50 located in the secondary display area A2 to receive Sufficient light is received to achieve normal operation of the optical element 50 .
  • the plurality of second pixel circuits 21d are coupled to the plurality of second light-emitting devices 31b, thereby providing driving signals for the second light-emitting devices 31b to drive the second light-emitting devices 31b to emit light.
  • the plurality of second pixel circuits 21d may be located only in an area close to the boundary of the sub-display area A2, and no second pixel circuit 21d is provided at the center of the sub-display area A2, and the plurality of second light-emitting devices 31b may be uniform. Distributed in the secondary display area A2.
  • the orthographic projection of the plurality of second pixel circuits 21d on the base substrate 10 and the orthographic projection of the plurality of second light-emitting devices 31b on the base substrate 10 at least partially overlap.
  • some of the second pixel circuits 21d are disposed facing the corresponding second light-emitting device 31b, and other second pixel circuits 21d are disposed facing the corresponding part of the second light-emitting device 31b.
  • a plurality of second pixel circuits 21d are located in the frame area F.
  • the plurality of second pixel circuits 21d are coupled to the plurality of second light-emitting devices 31b, thereby providing driving signals for the second light-emitting devices 31b to drive the second light-emitting devices 31b to emit light.
  • the second pixel circuit 21d is located in the frame area F, and the second light-emitting device 31b is located in the sub-display area A2, there is a certain distance between the second pixel circuit 21d and the corresponding second light-emitting device 31b. , the second pixel circuit 21d and the corresponding second light-emitting device 31b are coupled through conductive lines.
  • the pixel circuit layer 20 further includes: a plurality of redundant pixel circuits 21c.
  • the plurality of redundant pixel circuits 21c are connected with signal lines (such as the first scanning signal line Gate1, the second scanning signal line Gate2, the data signal line Data, the enable signal line EM, etc. mentioned above) and the light emitting device.
  • the anode layer of 31 is electrically insulated. That is, none of the plurality of redundant pixel circuits 21c is coupled to the signal lines (such as the first scanning signal line Gate1, the second scanning signal line Gate2, the data signal line Data, the enable signal line EM, etc. mentioned above). Then, none of the plurality of redundant pixel circuits 21 c is coupled to the anode layer of the light-emitting device 31 .
  • Adopting the above arrangement method and arranging multiple redundant pixel circuits 21c can improve the uniformity of the surrounding pixel circuit 21a and avoid the problem of threshold voltage deviation caused by the surrounding pixel circuit 21a, thereby solving the problem of the problem in the light-emitting device close to the sub-display area A2
  • the problem of abnormal display occurs in the light-emitting device 31 coupled to the boundary surrounding the pixel circuit 21a.
  • a plurality of redundant pixel circuits 21c are located in the main display area A1 and surround at least a part of the secondary display area A2.
  • a plurality of redundant pixel circuits 21c may surround a part of the sub-display area A2.
  • a plurality of redundant pixel circuits 21c may surround the entire sub-display area A2.
  • the plurality of redundant pixel circuits 21c are closer to the sub-display area A2 than the surrounding pixel circuits 21a.
  • the redundant pixel circuit 21c which can prevent the light from passing through the pixel circuit layer 20 and emitting from the light exit side of the display panel 100, thus preventing the display panel 100 and the display device 1000 from being damaged.
  • the display screen is abnormal, thereby improving the display effect of the display panel 100 and the display device 1000 .
  • the pixel circuit layer 20 when the pixel circuit layer 20 includes a plurality of surrounding pixel circuits 21 a and a plurality of redundant pixel circuits 21 c , the plurality of surrounding pixel circuits 21 a are arranged along the first direction X as Multiple columns are arranged into multiple rows along the second direction Y.
  • the plurality of redundant pixel circuits 21c are arranged in at least one column along the first direction X and in at least one row along the second direction Y.
  • the plurality of redundant pixel circuits 21c are arranged in one or more columns along the first direction X.
  • the plurality of redundant pixel circuits 21c are arranged in one or more rows along the second direction Y.
  • the redundant pixel circuit 21c can be manufactured together with the surrounding pixel circuit 21a, and the redundant pixel circuit 21c is not coupled to the signal lines and light-emitting devices, thereby simplifying The preparation process of the surrounding pixel circuit 21a and the redundant pixel circuit 21c in the pixel circuit layer 20.
  • the sum of the number of rows of the surrounding pixel circuits 21a and the number of rows of the redundant pixel circuits 21c provided on either side is greater than or equal to three rows. .
  • the number of rows of redundant pixel circuits 21c provided on either side may be less than or equal to 2 rows.
  • the number of rows of the redundant pixel circuits 21c provided on either side of the opposite sides of the sub-display area A2 may be greater than or equal to 1.
  • the above arrangement can ensure the blocking effect of the light-blocking layer on the surrounding pixel circuit 21a and the improvement effect on the "progressive dark ring".
  • the redundant pixel circuit 21c The active layer will be illuminated by part of the light, and the redundant pixel circuit 21c is not connected to the light-emitting device 31 and will not affect the brightness of the light-emitting device. Therefore, there is no need to set a barrier in the area corresponding to the redundant pixel circuit 21c.
  • the light layer 70 is only provided in the area corresponding to the area surrounding the pixel circuit 21a, thereby reducing the amount of material used in the light blocking layer 70.
  • the display panel 100 further includes: a semiconductor layer Poly, a first conductive layer Gate1, a second conductive layer Gate2, an interlayer dielectric layer ILD, and a first conductive layer Gate2, which are sequentially stacked on the side of the light blocking layer 70 away from the base substrate 10.
  • a semiconductor layer Poly a semiconductor layer Poly
  • a first conductive layer Gate1 a second conductive layer Gate2
  • an interlayer dielectric layer ILD an interlayer dielectric layer
  • a first conductive layer Gate2 which are sequentially stacked on the side of the light blocking layer 70 away from the base substrate 10.
  • the pixel circuit layer 20 includes: the above-mentioned semiconductor layer Poly, the first conductive layer Gate1, the second conductive layer Gate2, the interlayer dielectric layer ILD, the third conductive layer SD1, the first planarization layer PLN1, the fourth Conductive layer SD2.
  • FIG. 19 illustrates the top view structure of the light blocking layer 70 .
  • Figure 20a illustrates the top view structure of the semiconductor layer Poly.
  • FIG. 20b illustrates the top view structure of the light-blocking layer 70 and the semiconductor layer ACT which are stacked in sequence.
  • FIG. 21 illustrates the top view structure of the first conductive layer Gate1.
  • Figure 22 illustrates the top view structure of the second conductive layer Gate2.
  • FIG. 23 illustrates a top view structure of the interlayer dielectric layer ILD.
  • FIG. 24 illustrates the top view structure of the third conductive layer SD1.
  • Figure 25 illustrates the top view structure of the first flat layer PLN1.
  • FIG. 26 illustrates the top view structure of the fourth conductive layer SD2.
  • FIG. 27 illustrates the top view structure of the second flat layer PLN2.
  • Figure 28 illustrates the top view structure of the anode layer AND.
  • FIG. 29 illustrates a top view structure of the pixel definition layer PDL.
  • the interlayer dielectric layer ILD, the first planar layer PLN1, and the second planar layer PLN2 are generally made of transparent materials. Therefore, Figure 23 only shows the location of the via holes on the interlayer dielectric layer ILD, and Figure 25 only shows Figure 27 shows the location of the via holes on the first flat layer PLN1, and 27 only shows the location of the via holes on the second flat layer PLN2.
  • a first gate insulating layer may be disposed between the semiconductor layer Poly and the first conductive layer Gate1, and a second gate insulating layer may be disposed between the first conductive layer Gate1 and the second conductive layer Gate2.
  • the interlayer dielectric layer ILD, the first planarization layer PLN1, the second planarization layer PLN2, the first gate insulating layer, and the second gate insulating layer may be made of insulating materials, such as silicon oxide, silicon nitride, oxynitride, etc. Silicon etc.
  • the material of the semiconductor layer Poly may include amorphous silicon, single crystal silicon, polycrystalline silicon or metal oxide semiconductor materials.
  • the materials of the first conductive layer Gate1, the second conductive layer Gate2, the third conductive layer SD1, and the fourth conductive layer SD2 are all conductive materials.
  • the materials of the first conductive layer Gate1 and the second conductive layer Gate2 may be the same, and the materials of the third conductive layer SD1 and the fourth conductive layer SD2 may be the same, for example.
  • the material of the first conductive layer Gate1, the second conductive layer Gate2, the third conductive layer SD1 or the fourth conductive layer SD2 can be a metal material, such as Al (aluminum), Ag (silver), Cu (copper). ), Cr (chromium), etc.
  • the orthographic projection of the semiconductor layer Poly on the substrate overlaps with the orthographic projection of the first conductive layer Gate1 on the substrate.
  • the first conductive layer Gate1 can be used as a mask to perform doping treatment on the semiconductor layer Poly, so that the semiconductor layer Poly is covered by the first conductive layer Gate1
  • the covered portion constitutes the active pattern of each transistor, so that the portion of the semiconductor layer Poly that is not covered by the first conductive layer Gate1 constitutes a conductor, and the conductor can constitute the first pole or the second pole of each transistor.
  • the overlapping portion of the first conductive layer Gate1 and the semiconductor layer Poly constitutes the gate pattern (that is, the gate electrode) of each transistor.
  • the relative positional relationship between each transistor and the storage capacitor included in the pixel circuit 21 is as shown in FIG. 9b.
  • the driving transistor T4 is located between the second light emission control transistor T7 and the first light emission control transistor T6.
  • the driving transistor T4 is also located between the switching transistor T3 and the first light emission control transistor T6.
  • the compensation transistor T5 is located between the second reset transistor T2 and the switching transistor T3.
  • the second reset transistor T2 is also positioned on a side of the second light emission control transistor T7 away from the switching transistor T3.
  • the position of the storage capacitor Cst is the same as the position of the driving transistor T4.
  • the transistors and storage capacitors in the pixel circuit 21 can be arranged more closely, saving the area along the first direction X and the second direction Y on the display panel 100, thereby making it possible to achieve a certain area If more pixel circuits 21 are arranged, the pixel density of the display panel 100 and the display device 1000 can be increased, which is beneficial to the high PPI design of the display panel 100 and the display device 1000 .
  • the display panel 100 further includes: a first voltage signal line VDD and a transfer layer Co disposed in the pixel circuit layer 20 .
  • the first voltage signal line VDD is located on the fourth conductive layer SD2.
  • the transfer layer Co may be disposed on the same layer as the fourth conductive layer SD2.
  • the transfer layer Co may include a transfer pattern.
  • the light blocking layer 70 is connected to the first voltage signal line VDD through a transfer pattern.
  • the transfer pattern can pass through the via holes on the first planar layer PLN1, the interlayer dielectric layer ILD, the second insulating layer GI2, and the first insulating layer GI1 in order to connect to the light blocking layer 70.
  • the transfer pattern may be located in the frame area F, whereby the transfer pattern may be connected to the light-blocking layer 70 in the frame area F.
  • the material of light blocking layer 70 includes molybdenum or graphite.
  • the material of the light-blocking layer 70 can be conductive.
  • the light-blocking layer 70 is connected to the first voltage signal line VDD, since the signal transmitted by the first voltage signal line VDD is a constant voltage signal, the light-blocking layer 70 can be made electrically conductive.
  • There is a constant voltage signal on the layer 70 which can prevent the stability of the voltage signal in the pixel circuit layer 20 (such as the scanning signal line Gate) on the light-blocking layer 70, avoid interference to the signal of the pixel circuit layer, and improve the pixel circuit layer 20 The stability of the transmitted signal.
  • the light blocking layer 70 can also be coupled with other signal lines that transmit constant voltage signals, such as the common voltage signal line VSS, the first initial signal line Vinit1, the second initial signal line Vinit2, etc., so as to avoid blocking.
  • the stability of the voltage signal in the pixel circuit layer 20 (such as the scanning signal line Gate) on the light layer 70 prevents the signal of the pixel circuit layer from being interfered and improves the stability of the signal transmission by the pixel circuit layer 20 .

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Abstract

一种显示面板，具有显示区，所述显示区包括主显示区和副显示区，所述主显示区围绕所述副显示区的至少一部分。所述显示面板包括：衬底基板，至少位于所述显示区；像素电路层，位于所述衬底基板的一侧且至少位于所述显示区，所述像素电路层包括多个环绕像素电路，所述多个环绕像素电路位于所述主显示区且至少部分围绕所述副显示区。挡光层，位于所述主显示区，且位于所述衬底基板和所述像素电路层之间，所述挡光层在所述衬底基板的正投影与所述多个环绕像素电路在所述衬底基板的正投影至少部分交叠。

Description

显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及及显示装置。
背景技术
随着科学技术的不断发展，用户对显示装置的屏占比(显示屏的面积与显示装置的前面板的面积的比例)有着越来越高的追求。
在显示技术领域中，出现了全面屏的概念，也即，将显示装置中的摄像头等光学器件设置在显示屏的下方，以增大显示屏的面积与显示装置的前面板的面积之间的比例，并使得该比例趋近于100％。
发明内容
一方面，提供一种显示面板，所述显示面板具有显示区，所述显示区包括主显示区和副显示区，所述主显示区围绕所述副显示区的至少一部分；所述显示面板包括：衬底基板，至少位于所述显示区；像素电路层，位于所述衬底基板的一侧且至少位于所述显示区，所述像素电路层包括多个环绕像素电路，所述多个环绕像素电路位于所述主显示区且至少部分围绕所述副显示区；挡光层，位于所述主显示区，且位于所述衬底基板和所述像素电路层之间，所述挡光层在所述衬底基板的正投影与所述多个环绕像素电路在所述衬底基板的正投影至少部分交叠。
在一些实施例中，所述挡光层包括多个挡光图案。一个环绕像素电路的至少部分在所述衬底基板上的正投影，位于一个挡光图案在所述衬底基板上的正投影范围内。
在一些实施例中，所述环绕像素电路包括驱动晶体管。所述驱动晶体管的有源层在所述衬底基板上的正投影，位于所述挡光图案在所述衬底基板上的正投影范围内。
在一些实施例中，所述环绕像素电路还包括与所述驱动晶体管耦接的补偿晶体管。所述补偿晶体管的有源层在所述衬底基板上的正投影，位于所述挡光图案在所述衬底基板上的正投影的范围内。
在一些实施例中，所述多个环绕像素电路沿第一方向排列为多列，沿第二方向排列为多行。位于所述副显示区同一侧的部分环绕像素电路中，沿所述第一方向相邻的至少两个环绕像素电路所对应的挡光图案相连接，和/或，沿所述第二方向相邻的至少两个环绕像素电路所对应的挡光图案相连接。
在一些实施例中，所述多个挡光图案相连接，呈一体结构。所述挡光层环绕所述副显示区。
在一些实施例中，所述挡光层包括同心设置的至少两个挡光环。每个挡光环包括相连接的多个挡光图案，所述挡光环环绕所述副显示区的至少部分。
在一些实施例中，所述挡光层还包括至少一个连接图案。相邻两个所述挡光图案通过所述连接图案相互连接。
在一些实施例中，所述显示面板还包括：设置在所述像素电路层中的第一电压信号线和转接层；所述挡光层通过所述转接层与所述第一电压信号线连接。
在一些实施例中，所述挡光层的材料包括钼或石墨。
在一些实施例中，所述多个环绕像素电路沿第一方向排列为多列，沿第二方向排列为多行。沿所述第一方向，所述副显示区的相对两侧中，任一侧设置有至少六列环绕像素电 路，沿所述第二方向，所述副显示区的相对两侧中，任一侧至少设置有至少三行环绕像素电路。
在一些实施例中，所述多个像素电路层还包括多个冗余像素电路。所述多个冗余像素电路位于所述主显示区，且环绕所述副显示区的至少一部分；所述多个冗余像素电路相比于所述环绕像素电路更靠近所述副显示区。
在一些实施例中，所述多个环绕像素电路沿第一方向排列为多列，沿第二方向排列为多行；所述多个冗余像素电路沿所述第一方向排列为至少一列，沿所述第二方向排列为至少一行。沿所述第一方向，所述副显示区的相对两侧中，任一侧所设置的环绕像素电路的列数与冗余像素电路的列数之和大于或等于六列。沿所述第二方向，所述副显示区的相对两侧中，任一侧所设置的环绕像素电路的行数与冗余像素电路的行数之和大于或等于三行。
在一些实施例中，所述显示面板还包括位于所述主显示区的多个第一发光器件；所述像素电路层还包括位于所述主显示区的多个第一像素电路。所述多个第一像素电路与所述多个第一发光器件耦接；所述多个环绕像素电路中的至少部分环绕像素电路为第一像素电路。
在一些实施例中，所述显示面板还包括位于所述副显示区的多个第二发光器件；所述像素电路层还包括位于所述主显示区的多个第二像素电路。所述多个第二像素电路与所述多个第二发光器件通过导电线连接；所述多个环绕像素电路中的至少部分环绕像素电路为第二像素电路。
在一些实施例中，所述显示面板还包括位于所述副显示区的多个第二发光器件；所述像素电路层还包括位于所述副显示区的多个第二像素电路。所述多个第二像素电路与所述多个第二发光器件耦接。
在一些实施例中，所述显示面板还具有位于所述显示区的至少一侧的边框区和位于所述副显示区的多个第二发光器件；所述像素电路层还包括位于所述边框区的多个第二像素电路，所述多个第二像素电路与所述多个第二发光器件通过导电线耦接。
另一方面，提供一种显示装置，包括：上述任一实施例所述的显示面板。
在一些实施例中，所述显示装置还包括：位于所述挡光层远离所述像素电路层一侧的光学元件，所述光学元件在所述衬底基板上的正投影，位于所述副显示区内。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸等的限制。
图1为根据本公开的一些实施例的一种显示装置的结构图；
图2为根据本公开的一些实施例的一种显示面板的结构图；
图3a为根据本公开的一些实施例的另一种显示装置的结构图；
图3b为根据本公开的一些实施例的又一种显示装置的结构图；
图4a为一种实现方式中的一种显示装置的结构图；
图4b为一种实现方式中光线在背膜和空气的界面发生全反射的示意图；
图4c为一种实现方式中显示面板中的一种像素电路层的结构图；
图4d为一种实现方式中显示面板出现“进行性暗环”的示意图；
图4e为一种实现方式中显示面板中的驱动晶体管在预设灰阶为L64的特性转移线的示意图；
图4f为一种实现方式中显示面板中的驱动晶体管在预设灰阶为L128的特性转移线的示意图；
图5为根据本公开的一些实施例的一种显示面板的局部结构图；
图6a为根据本公开的一些实施例的另一种显示面板的局部结构图；
图6b为根据本公开的一些实施例的另一种显示面板的局部结构图；
图7为根据本公开的一些实施例的一种像素电路及发光器件的结构图；
图8a为根据本公开的一些实施例的一种显示面板的一些膜层的俯视图；
图8b为根据本公开的一些实施例的一种显示面板的另一些膜层的俯视图；
图9a为根据本公开的一些实施例的一种显示面板的又一些膜层的俯视图；
图9b为根据本公开的一些实施例的一种显示面板的又一些膜层的俯视图；
图10为根据本公开的一些实施例的一种显示面板的又一些膜层的俯视图；
图11为根据本公开的一些实施例的一种显示面板的又一些膜层的俯视图；
图12a为根据本公开的一些实施例的一种显示面板的又一些膜层的俯视图；
图12b为根据本公开的一些实施例的一种显示面板的又一些膜层的俯视图；
图13为根据本公开的一些实施例的一种显示面板的又一些膜层的俯视图；
图14为根据本公开的一些实施例的一种显示面板的又一些膜层的俯视图；
图15为根据本公开的一些实施例的一种显示面板的又一些膜层的俯视图；
图16为根据本公开的一些实施例的一种挡光层及衬底的结构图；
图17为根据本公开的一些实施例的另一种挡光层及衬底的结构图；
图18为根据本公开的一些实施例的一种像素电路层及挡光层的结构图；
图19为根据本公开的一些实施例的一种显示面板的又一些膜层的俯视图；
图20a为根据本公开的一些实施例的一种显示面板的又一些膜层的俯视图；
图20b为根据本公开的一些实施例的一种显示面板的又一些膜层的俯视图；
图21为根据本公开的一些实施例的一种显示面板的又一些膜层的俯视图；
图22为根据本公开的一些实施例的一种显示面板的又一些膜层的俯视图；
图23为根据本公开的一些实施例的一种显示面板的又一些膜层的俯视图；
图24为根据本公开的一些实施例的一种显示面板的又一些膜层的俯视图；
图25为根据本公开的一些实施例的一种显示面板的又一些膜层的俯视图；
图26为根据本公开的一些实施例的一种显示面板的又一些膜层的俯视图；
图27为根据本公开的一些实施例的一种显示面板的又一些膜层的俯视图；
图28为根据本公开的一些实施例的一种显示面板的又一些膜层的俯视图；
图29为根据本公开的一些实施例的一种显示面板的又一些膜层的俯视图；
图30为根据本公开的一些实施例的一种挡光层与第一电压信号线连接的剖视图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的 形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
在本公开的实施例提供的电路结构(例如像素电路)中，电路结构所采用的晶体管可以为薄膜晶体管(Thin Film Transistor，简称TFT)、场效应晶体管(Metal Oxide Semiconductor，简称MOS)或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。
在本公开的实施例提供的电路结构中，所采用的各晶体管的第一极为源极和漏极中一者，各晶体管的第二极为源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性地，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性地，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
本公开的实施例提供的电路结构中，第一节点、第二节点等节点并非表示实际存在的部件，而是表示电路图中相关耦接的汇合点，也就是说，这些节点是由电路图中相关耦接的汇合点等效而成的节点。
本公开的实施例中提供的电路结构所包括的晶体管，可以均为N型晶体管，或者可以均为P型晶体管，或者一部分为N型晶体管，另一部分为P型晶体管。在本公开中，
“有效电平”指的是，能够使得晶体管导通的电平。其中，P型晶体管可以在低电平信号的控制下导通，N型晶体管可以在高电平信号的控制下导通。
下面，以本公开的实施例中提供的电路结构所包括的晶体管均为P型晶体管为例，
进行示意性说明。本公开的一些实施例提供了一种显示面板100及显示装置1000，以下对显示面板100及显示装置1000分别进行介绍。
本公开的一些实施例提供一种显示装置1000，如图1所示。该显示装置1000可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字的还是图像的任何显示装置中。更明确地说，预期所述实施例的显示装置可实施应用在多种电子中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
在一些实施例中，如图3a所示，显示装置1000包括：散热膜40。
在一些示例中，散热膜40位于显示装置1000的非显示侧。
例如，显示装置1000的非显示侧指的是，与显示装置显示画面的一侧背对的一侧。
采用上述设置方式，可以使得显示装置1000中的热量可以及时通过散热膜40消散，避免使得显示装置1000内部的热量得到积累，进而影响显示装置1000的显示效果。
在一些示例中，散热膜40可以包括依次层叠设置的保护层41、散热层42、缓冲层43、泡棉(Foam)层44、网格胶层45等。
例如，保护层41的材料可以包括剥离胶。保护层41可以在显示面板100未组装下文中提到的光学元件前，对散热膜40及显示面板100起到一定的保护作用。在显示装置 1000的组装过程中，例如在对光学元件进行组装前，可以将散热膜40中的保护层41进行剥离。
例如，散热层42的材料可以包括铜箔。铜箔可以为自粘铜箔、双导铜箔、单导铜箔等，上述铜箔均具有优良的导通性，一方面显示面板100中的热量可以通过散热层42实现热量的消散，另一方面散热层42还可以对衬底基板10一侧的像素电路层20起到电磁屏蔽和静电释放的作用。
例如，缓冲层43的材料可以包括PET(Polyethylene Terephthalate，聚对苯二甲酸乙二醇酯)等。缓冲层可以对散热膜40受到的外力冲击进行缓冲和消散，避免对散热膜40造成损伤。
例如，泡棉层44的材料可以包括聚氨酯泡棉、导电泡棉、铝箔泡棉等，上述材料均具有较佳导热性能，可以迅速地将显示面板100产生的热量散发出去，防止热量累积对显示面板100造成不良影响而导致显示效果下降。此外，由于泡棉层的材料较为柔软，可以对显示面板100进行保护，从而可以在外力对显示面板100造成冲击时，对该外力进行吸收和缓冲，避免对显示面板100造成损伤。
例如，网格胶层45的材料可以为压敏胶，该材料可以使得散热膜40与衬底基板10相粘接，实现散热膜40与衬底基板10之间的固定。
在一些示例中，如图3b所示，上述散热膜40具有开口，该开口与副显示区A2相对设置。
需要说明的是，上述散热膜40的开口指的是，如图3b所示，在散热膜40剥离保护层41后形成的散热膜40的结构上的通孔。该通孔贯穿散热层42、缓冲层43、泡棉(Foam)层44、网格胶层45。
示例性的，散热膜40的开口的中心可以与副显示区A2的中心重合，散热膜40的开口的面积可以大于或等于副显示区A2的面积。
在一些示例中，如图3b所示，显示装置1000还包括：光学元件50。
示例性的，光学元件50例如可以为摄像头、红外传感器或指纹传感器等。
本公开中以光学元件50为摄像头为例进行说明。
在摄像头工作的过程中，外界光线可以穿过显示装置1000位于副显示区A2的部分，入射至摄像头，这样摄像头便可以采集该光线，实现拍照的功能。
示例性的，光学元件50在散热膜40上的正投影，位于散热膜40的开口及副显示区A2内。
例如，光学元件50与散热膜40的开口相对设置，且光学元件50在散热膜40上的正投影的面积，小于或等于散热膜40的开口的面积。光学元件50与副显示区A2相对设置，且光学元件50在散热膜40上的正投影的面积，小于或等于副显示区A2的面积。
可以理解的是，散热膜40通常整层设置且不透光。通过在散热膜40中设置开口，且使得光学元件50在散热膜40上的正投影位于开口及副显示区A2内，可以使得外界光线在穿过副显示区A2的过程中不会被散热膜40阻挡而正常入射至光学元件50，进而可以保证光学元件50采集到足够的光线，保证光学元件50可以正常工作。
示例性的，如图3b所示，显示装置1000还包括：位于衬底基板10和散热膜40之间的背膜60。
示例性的，背膜60可以覆盖衬底基板10靠近散热膜40一侧的表面，进而可以对衬 底基板10、像素电路层20以及发光器件30等结构进行保护，避免上述结构受到损失，保证显示面板100的正常显示。
例如，上述背膜60的材料可以为透光材料。入射至背膜60一侧的光线可以穿透背膜60从背膜60的另一侧出射。这样一来，在显示面板100的光学元件50工作的情况下，外界光线可以依次穿过位于显示面板100的副显示区A2、背膜60，入射至光学元件50，使得光学元件50可以采集到足够的光线，进而可以实现拍照等功能。
示例性的，显示装置1000还包括框架、显示驱动IC(Integrated Circuit，集成电路)以及其他电子配件等。
在一些实施例中，如图1所示，上述显示装置1000包括：显示面板100。
在一些实施例中，如图2所示，显示面板100具有显示区A，以及位于显示区A的至少一侧的边框区F。
例如，边框区F可以围绕一部分显示区A，也即，边框区F可以位于显示区A的一侧、两侧、三侧等。又如，如图2所示，边框区F可以围绕显示区A，将显示区A包围。
在一些示例中，如图2所示，显示面板100的显示区A包括主显示区A1和副显示区A2，主显示区A1围绕副显示区A2的至少一部分。
例如，主显示区A1可以围绕一部分副显示区A2。又如，如图3a所示，主显示区A1可以围绕副显示区A2，将副显示区A2包围。
其中，显示区A及副显示区A2的形状包括多种，可以根据实际需要选择设置。
示例性的，显示区A的形状可以为矩形、近似矩形、圆形或椭圆形等。其中，近似矩形为非严格意义上的矩形，其四个内角例如可以为圆角，或者某条边例如不是直线。
示例性的，副显示区A2的形状也可以为矩形、近似矩形、圆形或椭圆形等，可以根据实际需求进行设置。
为方便描述，本公开中以副显示区A2的形状为圆形为例进行说明。
示例性的，显示面板100中位于副显示区A2的部分的透光率大于显示面板100中位于主显示区A1的部分的透光率。
例如，光线可以透过显示面板100位于副显示区A2的部分，从显示面板100的一侧射向显示面板100的另一侧。
在一些示例中，如图3a和图3b所示，显示面板100包括：衬底基板10、位于衬底基板10的一侧的的像素电路层20、发光器件层30。
示例性的，衬底基板10可以为柔性衬底。该柔性衬底例如可以为PET衬底、PEN(Polyethylene naphthalate two formic acid glycol ester，聚萘二甲酸乙二醇酯)衬底或PI(Polyimide，聚酰亚胺)衬底等。由此，上述显示面板100为柔性显示面板。
示例性的，衬底基板10至少位于显示区A。
例如，衬底基板10可以位于显示面板100的显示区A。
又如，衬底基板10可以位于显示面板100的显示区A和显示面板100的边框区F。
示例性的，像素电路层20包括多个像素电路21。发光器件层30包括多个发光器件31。
示例性的，像素电路21的结构包括多种，可以根据实际需要选择设置。例如，像素电路21的结构可以包括“6T1C”、“7T1C”、“6T2C”或“7T2C”等结构。此处，“T”表示为晶体管，位于“T”前面的数字表示为晶体管的数量，“C”表示为存储电容器，位 于“C”前面的数字表示为存储电容器的数量。
本公开中以像素电路21的结构为“7T1C”结构为例进行说明。其中，图7示意出了像素电路21的等效电路图。
例如，如图7所示，像素电路21包括：第一复位晶体管T1、第二复位晶体管T2、开关晶体管T3、驱动晶体管T4、补偿晶体管T5、第一发光控制晶体管T6、第二发光控制晶体管T7和存储电容器Cst。
例如，如图7所示，第一复位晶体管T1的栅极与复位信号线Reset耦接，第一复位晶体管T1的第一极与第一初始信号线Vinit1耦接，第一复位晶体管T1的第二极与第四节点N4耦接，也即与补偿晶体管T5的第二极耦接。其中，第一复位晶体管T1被配置为，在复位信号线Reset所传输的复位信号的控制下导通，将在第一初始信号线Vinit1处接收的第一初始信号传输至第四节点N4，对第四节点N4进行复位。
例如，如图7所示，第二复位晶体管T2的栅极与第一扫描信号线Gate1耦接，第二复位晶体管T2的第一极与第二初始信号线Vinit2耦接，第二复位晶体管T2的第二极与第一节点N1耦接，也即与发光器件31耦接。其中，第二复位晶体管T2被配置为，在第一扫描信号线Gate1所传输的第一扫描信号的控制下导通，将在第二初始信号线Vinit2处接收的第二初始信号传输至第一节点N1，对第一节点N1进行复位。
例如，如图7所示，开关晶体管T3的栅极与第二扫描信号线Gate2耦接，开关晶体管T3的第一极与数据线Data耦接，开关晶体管T3的第二极与第二节点N2耦接，也即与驱动晶体管T4的第一极耦接。其中，开关晶体管T3被配置为，在第二扫描信号线Gate2所传输的第二扫描信号的控制下导通，将在数据线Data处接收的数据信号传输至第二节点N2。
例如，如图7所示，驱动晶体管T4的栅极与第四节点N4耦接，驱动晶体管T4的第一极与第二节点N2耦接，驱动晶体管T4的第二极与第三节点N3耦接。其中，驱动晶体管T4被配置为，在第四节点N4的电压的控制下导通，将来自第二节点N2的信号(例如为数据信号)传输至第三节点N3。
例如，如图7所示，补偿晶体管T5的栅极与第二扫描信号线Gate2耦接，补偿晶体管T5的第一极与第三节点N3耦接，也即与驱动晶体管T4的第二极耦接，补偿晶体管T5的第二极与第四节点N4耦接，也即与驱动晶体管T4的栅极耦接。其中，补偿晶体管T5被配置为，在第二扫描信号线Gate2所传输的第二扫描信号的控制下导通，将来自第三节点N3的电信号(例如为数据信号)传输至第四节点N4。
例如，如图7所示，第一发光控制晶体管T6的栅极与使能信号线EM耦接，第一发光控制晶体管T6的第一极与电压信号线VDD耦接，第一发光控制晶体管T6的第二极与第二节点N2耦接。其中，第一发光控制晶体管T6被配置为，在使能信号线EM所传输的使能信号的控制下导通，将在第一电压信号线VDD处接收的电压信号传输至第二节点N2。
例如，如图7所示，第二发光控制晶体管T7的栅极与使能信号线EM耦接，第二发光控制晶体管T7的第一极与第三节点N3耦接，第二发光控制晶体管T7的第二极与第一节点N1耦接。其中，第二发光控制晶体管T7被配置为，在使能信号线EM所传输的使能信号的控制下导通，将来自第三节点N3的电信号(例如电压信号)传输至第一节点N1。
例如，如图7所示，存储电容器Cst的第一极与第四节点N4耦接，存储电容器Cst的第二极与第一电压信号线VDD耦接。
示例性的，发光器件31可以包括依次层叠设置的阳极层、发光功能层、阴极层等。其中，发光功能层可以包括发光层。可选地，发光功能层还可以包括空穴注入层、空穴传输层、电子传输层和电子注入层中的至少一者。
例如，像素驱动电路可以和发光器件的阳极层耦接。
通过给发光器件31的阴极层施加公共电压信号，并利用相应的像素电路21给发光器件31的阳极层施加驱动信号，便可以在发光器件31阳极层和阴极层之间形成电场，该电场可以驱动不同的载流子(也即空穴和电子)在发光层中复合，从而使得发光器件31发光。
可选地，像素电路21的工作过程包括依次进行的复位阶段、数据写入及补偿阶段、发光阶段。
例如，在复位阶段，在复位信号的控制下，第一复位晶体管T1导通，将第一初始信号传输至第四节点N4，对第四节点N4进行复位。由于第四节点N4与存储电容器Cst的第一极、驱动晶体管T4的栅极及补偿晶体管T5的第二极耦接，因此，在对第四节点N4复位时，便可以同步对存储电容器Cst的第一极、驱动晶体管T4的栅极及补偿晶体管T5的第二极进行复位。其中，驱动晶体管T4可以在第一初始信号的控制下导通。
例如，在数据写入及补偿阶段，第二复位晶体管T2在第一扫描信号的控制下导通，开关晶体管T3、补偿晶体管T5在第二扫描信号的控制下导通。第二复位晶体管T2将第二始信号传输至第一节点N1，对第一节点N1进行复位。由于第一节点N1与发光器件31的阳极耦接，因此，在对第一节点N1进行复位时，便可以同步对发光器件31的阳极进行复位。开关晶体管T3将数据信号传输至第二节点N2，驱动晶体管T4将来自第二节点N2的数据信号传输至第三节点N3。补偿晶体管T5将来自第三节点N3的数据信号传输至第四节点N4，对驱动晶体管T4进行充电，直至完成对驱动晶体管T4的阈值电压的补偿。
例如，在发光阶段，第一发光控制晶体管T6和第二发光控制晶体管T7在使能信号的控制下同时导通。第一发光控制晶体管T6将电压信号传输至第二节点N2。驱动晶体管T4将来自第二节点N2的电压信号传输至第三节点N3。第二发光控制晶体管T7将来自第三节点N3的电压信号传输至第一节点N1。
例如，在来自第一节点N1的驱动信号(例如上述电压信号)和来自公共电压线VSS的公共电压信号的作用下，可以生成驱动电流，发光器件31在驱动电流的作用下发光。
示例性的，上述多个像素电路21和多个发光器件31可以一一对应耦接。又如，一个像素电路21可以与多个发光器件31耦接，或者，多个像素电路21可以与一个发光器件31耦接。显示面板100中，各发光器件31可以在相应的像素电路21的驱动作用下发出光，多个发光器件31发出的光相互配合，从而使得显示面板100实现显示功能。
下面，本公开以一个像素电路21与一个发光器件31耦接为例，对显示面板100的结构进行示意性说明。
需要说明的是，图3a和图3b仅是示意出了像素电路层和发光器件层的位置关系，及像素电路和发光器件的位置关系，未示意出像素电路和发光器件的具体膜层关系及连接关系，因此，图3a和图3b并不对像素电路和发光器件的具体膜层关系及连接关系形成限定。
示例性的，如图5及图6a所示，上述多个像素电路位于除副显示区A2以外的区域内。上述多个发光器件31位于显示面板100的显示区A，其中，该发光器件的一部分位于主显示区，另一部分位于副显示区。位于主显示区A1的发光器件31为第一发光器件31a， 位于副显示区A2的发光器件31为第二发光器件31b。与多个第一发光器件31a耦接的像素电路21位于主显示区A1，与多个第二发光器件31b耦接的像素电路21位于主显示区A1、边框区F或副显示区A2。由此，在显示面板100的显示区A均有发光器件31在像素电路21的驱动作用下发光，使得显示面板100实现全面屏显示。
在一种实现方式中，如图4a所示，在显示装置中，为了使得摄像头能够正常工作，需要有一定量的外界光线通过FDC(Full Display with Camera)区到达摄像头，从而使得摄像头可以获得足够的光线实现拍照功能(此处，FDC区指的是沿显示装置的厚度方向，与摄像头相对的区域)。因此，全面屏显示装置位于FDC区的部分为可透光设置，FDC区例如对应为上述副显示区A2。
然而，在全面屏显示装置中，外界光线及发光器件发出的光线，经过一系列的折射和/或反射后，会到达背膜与空气的界面(也即背膜的下表面)。由于背膜材料的折射率大于空气的折射率，在入射至该界面的光线的入射角满足全反射条件的情况下，例如在该光线的入射角大于临界角的情况下，该光线会在上述界面发生全反射，并反射至位于FDC区的周边区域的像素驱动电路中的晶体管的有源层，进而使得像素驱动电路中晶体管的阈值电压发生漂移。以像素驱动电路中的驱动晶体管为例，上述光线会使得驱动晶体管的阈值电压发生漂移，进而在像素驱动电路的发光阶段，容易使得驱动晶体管提供给发光器件的驱动电流降低，进而使得该FDC区的周边区域的显示画面的亮度降低，出现如图4d所示的“进行性暗环”现象。该现象一般在显示装置开始显示画面后的5min后持续出现，直至显示装置关机后6h左右才逐渐消失。
需要说明的是，首先，如图4b所示，设定入射至上述背膜与空气的界面的光线的入射角为α，背膜的材料的折射率n 1＝1.45，空气的折射率n 2＝1，折射角为β。根据折射定律，各参数之间满足n 1*sinα＝n 2*sinβ。在折射角β为90°的情况下，即上述光线在上述界面恰好发生全反射的情况下，入射角α＝44°。也就是说，临界角为44°，在入射角α大于或等于44°的情况下，上述光线在该界面发生全反射。在外界光线及发光器件发出的光线，经过一系列的折射和/或反射后，入射至背膜和空气的界面的光线的入射角大于或等于44°的情况下，该光线会经全反射后入射至位于FDC区的周边区域的驱动晶体管的有源层，使得该驱动晶体管的阈值电压发生漂移，进而在发光阶段，容易使得驱动晶体管提供给发光器件的驱动电流降低，进而使得该FDC区的周边区域的显示画面的亮度降低，出现如图4d所示的“进行性暗环”现象。
其次，如图4b及图4c所示，设定像素驱动电路中的晶体管的有源层的下表面与背膜的下表面(即背膜与空气的界面)之间的距离为d，设定入射至背膜和空气的界面的光线的法线NL，位于FDC区的分界线，在背膜和空气的界面发生全反射后的光线所能照射到区域范围中，距离FDC区的边界线的最大间距的尺寸为W。以d＝11μm为例，则根据tanα＝W/d，可得W＝96μm。也就是说，外界光线及发光器件发出的光线，经过一系列的折射和/或反射后，在入射至背膜和空气的界面的光线的入射角大于或等于44°的情况下，该光线会经全反射后入射至围绕FDC区的周边区域，该FDC区的周边区域为距离FDC区边界线的间距为96μm范围内的区域。在该FDC区的周边区域内的驱动晶体管的有源层均会受到该光线的影响，导致上述驱动晶体管的阈值电压发生漂移，进而在像素驱动电路的发光阶段，容易使得驱动晶体管提供给发光器件的驱动电流降低，进而使得该FDC区的周边区域的显示画面的亮度降低，出现如图4d所示的“进行性暗环”现象。
对出现上述“进行性暗环”所对应的像素驱动电路中的驱动晶体管进行仿真测试，得到在同一预设灰阶下，驱动晶体管的不同阈值电压Vth对应的驱动电流I、显示亮度等数据，以及，在不同预设灰阶L64、L128、L255下，驱动晶体管的阈值电压Vth对应的驱动电流I、显示亮度等数据，具体数据如表1所示。
表1
Figure PCTCN2022089643-appb-000001
以预设灰阶为L64为例，参照表1，在驱动晶体管的阈值电压Vth由-2.7漂移至-2.1的过程中，驱动晶体管提供的驱动电流由2.092变化至1.54，该预设灰阶下驱动电流的变化百分比由-4.80％变化至-5.15％，实际显示亮度由22.72变化至16.72。可见，在预设灰阶相同的情况下，由于驱动晶体管的有源层受到光照，使得驱动晶体管的阈值电压发生漂移，进而引起发光器件的实际显示亮度发生变化(也即，显示亮度下降)，出现了人眼可识别的亮度差异，即上文提到的“进行性暗环”现象。
在预设灰阶为L64，驱动晶体管的阈值电压分别为-2.7、-2.6、-2.5、-2.4、-2.3、-2.2、-2.1的情况下，对该驱动晶体管的栅极电压Vg以及驱动电流I进行仿真测试，将仿真结果绘制成其对应的特性曲线Vg—I，如图4e所示。在预设灰阶为L128，驱动晶体管的阈值电压为-2.7、-2.6、-2.5、-2.4、-2.3、-2.2、-2.1的情况下，对该驱动晶体管的栅极电压Vg以及驱动电流I进行仿真测试，将仿真结果绘制成其对应的特性曲线Vg—I，如图4f 所示。可见，在相同的预设灰阶下，在驱动晶体管的阈值电压不同，栅极电压Vg相同的情况下，其对应的驱动电流不同。驱动晶体管的阈值电压漂移越大，其对应的驱动电流越小，发光器件的显示亮度越小，即显示画面越暗。而不同的预设灰阶下，驱动晶体管的阈值电压的漂移，均可使其对应的驱动电流发生明显的变化，进而使得发光器件的实际发光亮度降低，进而出现“进行性暗环”现象。
基于此，如图5所示，本公开的一些实施例中提供的显示面板100中，像素电路层20至少位于显示区A，像素电路层20中的多个像素电路21包括：多个环绕像素电路21a。
在一些示例中，像素电路层20可以全部位于显示区A。例如，像素电路层20可以全部位于主显示区A1。又如，像素电路层20可以部分位于主显示区A1，部分位于副显示区A2。
在另一些示例中，像素电路层20可以部分位于显示区A，部分位于显示面板100的其他区域，如位于边框区F。
例如，位于主显示区A1的多个像素电路21可以全部为环绕像素电路21a。又如，位于主显示区A1的多个像素电路21还可以包括多个环绕像素电路21a及多个其他像素电路，关于其他像素电路可以详见下文中的说明，此处不再赘述。
在一些示例中，上述多个环绕像素电路21a呈阵列状排布。
示例性的，多个环绕像素电路21a沿第一方向X排列为多列，沿第二方向Y排列为多行。
例如，上述第一方向X与第二方向Y的夹角可以为80°、85°、90°、95°或100°等。
为方便说明，本公开以第一方向X与第二方向Y的夹角为90°为例进行描述。
在一些示例中，如图5及图6a所示，多个环绕像素电路21a位于显示面板100的主显示区A1。
以位于主显示区A1的多个像素电路21全部为环绕像素电路21a为例。上述多个环绕像素电路21a例如包括多个第一环绕像素电路212a和多个第二环绕像素电路214a。该多个环绕像素电路21a中，第一环绕像素电路212a与位于主显示区A1的第一发光器件31a耦接，第二环绕像素电路214a与位于副显示区A2的第二发光器件31b耦接。
为清楚地示意出第二环绕像素电路214a与第二发光器件31b的连接关系，图5仅示意出了部分第二环绕像素电路214a与相应的第二发光器件31b的连接情况。
示例性的，上述多个环绕像素电路21a可以全部位于显示面板100的主显示区A1。如图5所示，第一环绕像素电路212a和第二环绕像素电路214a，可以沿第一方向X排列成多列，沿第二方向Y排列为多行。相邻两列第二环绕像素电路214a之间可以排列有至少一列第一环绕像素电路212a。这样，可以避免在显示面板100的边框区F设置与第二发光器件31b耦接的像素电路21，降低显示面板100中边框区F的宽度，进而可以提高显示面板100及显示装置1000的屏占比，有利于实现显示面板100及显示装置1000的全面屏显示。
例如，上述多个环绕像素电路21a可以环绕部分副显示区A2。又如，上述多个环绕像素电路21a可以完全包围副显示区A2。
在一些实施例中，如图3b所示，显示面板100还包括：位于衬底基板10和像素电路层20之间的挡光层70。
示例性的，挡光层70可以位于显示面板100的主显示区A1。
示例性的，挡光层70可以对入射至其表面的光线进行反射或吸收，该光线基本不能从挡光层70的一侧穿过挡光层70并从挡光层70的另一侧出射。
在一些实施例中，挡光层70在衬底基板10的正投影与多个环绕像素电路21a在衬底基板10的正投影至少部分交叠。
示例性的，如图8a及图8b所示，环绕像素电路21a在衬底基板10上的正投影的一部分，与挡光层70在衬底基板10上的正投影的部分重合。也就是说，环绕像素电路21a的一部分与挡光层70对应设置，环绕像素电路21a在衬底基板10上的正投影的一部分，与挡光层70在衬底基板10上的正投影的至少一部分重合。
例如，环绕像素电路21a在衬底基板10上的正投影的一部分，包括环绕像素电路21a中的至少一个晶体管的有源层在衬底基板10上的正投影。
采用上述设置方式，在外界光线及发光器件发出的光线，经过一系列的折射和/或反射，入射至上述背膜60与空气的界面后，部分光线在该界面发生全反射后射向显示面板100的内部。经全反射后射向显示面板100的内部的这部分光线会被挡光层70遮挡，这样一来，可以避免该部分光线照射至上述环绕像素电路21a中与挡光层70对应的部分结构(例如环绕像素电路21a中的至少一个晶体管的有源层)，减缓环绕像素电路21a的阈值电压漂移问题，进而可以减缓环绕像素电路21a的驱动电流降低的现象，减缓显示亮度的降低现象，减缓显示面板100及显示装置1000出现“进行性暗环”现象。
示例性的，如图9a及图9b所示，环绕像素电路21a在衬底基板10上的正投影，位于挡光层70在衬底基板10上的正投影的范围内。也就是说，环绕像素电路21a整体与挡光层70对应设置，环绕像素电路21a在衬底基板10上的正投影的至少一部分，与挡光层70在衬底基板10上的正投影的至少一部分重合。
例如，环绕像素电路21a在衬底基板10上的正投影，包括环绕像素电路21a所包括的多个晶体管在衬底基板10上的正投影。此时，挡光层70可以对环绕像素电路21a中的所有晶体管所在的区域进行遮挡，如图9a所示，这样可以简化挡光层70的制作工艺。
又如，环绕像素电路21a在衬底基板10上的正投影，包括环绕像素电路21a所包括的多个晶体管的有源层在衬底基板10上的正投影。此时，挡光层70可以图案化设置，如图9b所示，仅对环绕像素电路21a中各晶体管的有源层进行遮挡。
采用上述设置方式，在外界光线及发光器件31发出的光线，经过一系列的折射和/或反射，入射至上述背膜60与空气的界面后，部分光线在该界面发生全反射后射向显示面板100的内部。经全反射后射向显示面板100的内部的这部分光线会被挡光层70遮挡，这样一来，可以避免该部分光线照射至上述环绕像素电路21a中的各晶体管，减缓各环绕像素电路21a的阈值电压漂移问题，进而可以减缓甚至消除环绕像素电路21a的驱动电流降低的现象，减缓甚至消除显示亮度的降低现象，进一步地可以减缓甚至消除显示面板100及显示装置1000出现“进行性暗环”现象。
示例性的，如图10所示，像素电路层20中的多个环绕像素电路21a在衬底基板10上的正投影，位于挡光层70在衬底基板10上的正投影的范围内。
采用上述设置方式，可以利用挡光层70遮挡经全反射后射向显示面板100的内部的这部分光线，避免其照射至上述多个环绕像素电路21a，进而可以减缓该环绕像素电路21a的阈值电压漂移问题，减缓甚至消除环绕像素电路21a的驱动电流降低的现象，进而减缓 甚至消除显示亮度的降低现象，进一步地可以减缓甚至消除显示面板100及显示装置1000出现“进行性暗环”现象。
在一些示例中，如图11及图12a所示，挡光层70包括多个挡光图案71。一个环绕像素电路21a的至少部分在衬底基板10上的正投影，位于一个挡光图案71在衬底基板10上的正投影的范围内。
示例性的，一个环绕像素电路21a的一部分或整体在衬底基板10上的正投影，位于一个挡光图案71在衬底基板10上的正投影的范围内。
例如，一个环绕像素电路21a中一个晶体管的部分在衬底基板10上的正投影，位于一个挡光图案71在衬底基板10上的正投影的范围内。又如，一个环绕像素电路21a中一个晶体管在衬底基板10上的正投影，位于一个挡光图案71在衬底基板10上的正投影的范围内。又如，一个环绕像素电路21a中多个晶体管的部分在衬底基板10上的正投影，位于一个挡光图案71在衬底基板10上的正投影的范围内。又如，一个环绕像素电路21a中所有晶体管在衬底基板10上的正投影，位于一个挡光图案71在衬底基板10上的正投影的范围内。
示例性的，挡光图案71的形状可以有多种，可以根据实际情况进行设置。
例如，挡光图案71的形状可以为多边形，也可以为折线形等。
示例性的，多个挡光图案71与多个环绕像素电路21a之间一一对应。也就是说，每个挡光图案71对应一个环绕像素电路21a。一个挡光图案71与一个环绕像素电路21a的至少部分正对设置。
由于多个环绕像素电路21a环绕副显示区A2，且挡光层70中的多个挡光图案71与多个环绕像素电路21a对应设置，因此，挡光层70中的多个挡光图案71环绕副显示区A2设置。
在一些实施例中，环绕像素电路21a可以包括驱动晶体管T4。
在一些示例中，如图8a所示，上述驱动晶体管T4的有源层在衬底基板10上的正投影，位于挡光图案71在衬底基板10上的正投影的范围内。此处，环绕像素电路21a的一部分例如指的是驱动晶体管T4的有源层。
示例性的，驱动晶体管T4的有源层在衬底基板10上的正投影边界线，位于挡光图案71在衬底基板10上的正投影的边界线之内。或者，驱动晶体管T4的有源层在衬底基板10上的正投影边界线，与挡光图案71在衬底基板10上的正投影的边界线至少部分重合。
采用上述设置方式，在外界光线及发光器件31发出的光线，经过一系列的折射和/或反射，入射至上述背膜60与空气的界面后，部分光线在该界面发生全反射后射向显示面板100的内部。经全反射后的这部分光线，在入射至至少一个环绕像素电路21a中驱动晶体管T4有源层之前，会被挡光层70中的挡光图案71遮挡，避免其照射至上述至少一个环绕像素电路21a的驱动晶体管T4的有源层，这样可以减缓该驱动晶体管T4的阈值电压的漂移现象，减缓环绕像素电路21a的驱动电流降低的现象，进而可以减缓显示亮度的降低现象，减缓显示面板100及显示装置1000出现“进行性暗环”现象。
在一些实施例中，如图8b所示，环绕像素电路21a还包括：与驱动晶体管T4耦接的补偿晶体管T5。
在一些示例中，如图8b所示，上述补偿晶体管T5的有源层在衬底基板10上的正投影，位于挡光图案71在衬底基板10上的正投影的范围内。此时，环绕像素电路21a的部 分例如指的是驱动晶体管T4的有源层和补偿晶体管T5的有源层。
示例性的，补偿晶体管T5的有源层在衬底基板10上的正投影，位于挡光图案在衬底基板10上的正投影的边界线之内。或者，补偿晶体管T5的有源层在衬底基板10上的正投影的边界线，与挡光图案在衬底基板10上的正投影的边界线至少部分重合。
采用上述设置方式，在外界光线及发光器件31发出的光线，经过一系列的折射和/或反射，入射至上述背膜60与空气的界面后，部分光线在该界面发生全反射后射向显示面板100的内部。经全反射后的这部分光线，在入射至至少一个环绕像素电路21a中驱动晶体管T4和补偿晶体管T5的有源层之前，会被挡光层70中的挡光图案71遮挡，可以避免其照射至一个或多个环绕像素电路21a的驱动晶体管T4和补偿晶体管T5有源层，减缓该驱动晶体管T4和补偿晶体管T5的阈值电压的漂移现象，进而可以减缓环绕像素电路21a的驱动电流降低的现象，减缓显示亮度的降低现象，进一步地可以减缓显示面板100及显示装置1000出现“进行性暗环”现象。
示例性的，同一个环绕像素电路21a中的驱动晶体管T4的有源层以及补偿晶体管T5的有源层，可以与同一个挡光图案71对应设置。也就是说，同一个环绕像素电路21a中的驱动晶体管T4的有源层和补偿晶体管T5的有源层，位于一个挡光图案71在衬底基板10上的正投影的范围内。
需要说明的是，一种实现方式中，像素驱动电路中的驱动晶体管及补偿晶体管的阈值电压在光照的作用下，发生漂移，那么在数据写入及补偿阶段，补偿晶体管传输的数据信号将无法对驱动晶体管的阈值电压完成有效补偿，例如，补偿后第四节点的电压偏高，进而使得驱动晶体管的导通不充分，进而使得在发光阶段，驱动晶体管生成的驱动电流较小，进而使得发光器件的显示亮度降低，进而使得显示面板及显示装置出现“进行性暗环”现象。
而本公开采用上述设置方式，设置驱动晶体管T4的有源层及补偿晶体管T5的有源层在衬底基板10上的正投影，位于挡光图案71在衬底基板10上的正投影的范围内，由此，在在外界光线及发光器件发出的光线，经过一系列的折射和/或反射，入射至上述背膜60与空气的界面后，部分光线在该界面发生全反射后射向显示面板100的内部。经全反射后后的这部分光线，在入射至至少一个环绕像素电路21a中驱动晶体管T4的有源层和补偿晶体管T5的有源层之前，会被挡光层70中的挡光图案71遮挡，可以避免其照射至一个或多个环绕像素电路21a中驱动晶体管T4的有源层和补偿晶体管T5的有源层，进而可以减缓该驱动晶体管T4和补偿晶体管T5的阈值电压的漂移现象，进而可以使得补偿晶体管T5对驱动晶体管T4的阈值电压完成有效补偿，从而可以减缓环绕像素电路21a的驱动电流降低的现象，进而减缓显示亮度的降低现象，进一步地可以减缓显示面板100及显示装置1000出现“进行性暗环”现象。
可以理解的是，上述挡光层70的结构包括多种，挡光层70中的挡光图案71具有多种设置方式，具体可以根据实际需要选择设置。
在一些实施例中，如图11所示，挡光层中的多个挡光图案71可以是相互独立，互不连接的。
例如，挡光层70中的多个挡光图案71，可以全部为不连接的挡光图案71。
在另一些实施例中，如图13所示，挡光层70还包括至少一个连接图案72。相邻两个挡光图案71通过连接图案72相互连接。
例如，连接图案72可以为沿某一个方向延伸的条状图案，将相邻两个挡光图案71连接在一起。
挡光层70中多个挡光图案71之间的连接方式有多种，可以根据实际情况进行设置。本公开对此不作限制。
例如，挡光层70中的多个挡光图案71，可以全部为相邻两个挡光图案71相互连接，也可以全部为依次相邻的多个挡光图案71相互连接。或者，挡光层70的多个挡光图案71中，一部分挡光图案71可以为相邻的挡光图案71之间未连接，而其余部分挡光图案为相邻的挡光图案71之间相连接。
在一些示例中，位于副显示区A2同一侧的部分环绕像素电路21a中，沿第一方向X相邻的至少两个环绕像素电路21a所对应的挡光图案71相连接。
示例性的，如图13所示，相连接的挡光图案71的外轮廓，可以沿第一方向X延伸。所有相连接的挡光图案71可以呈多行排列。
示例性的，位于副显示区A2相对两侧的部分环绕像素电路21a中，沿第一方向X相邻的两个环绕像素电路21a所对应的挡光图案71未连接。也就是说，同一行挡光图案中，位于副显示区A2的相对两侧、且相邻的两个挡光图案71不会穿过副显示区A2相连接，这样一来，可以避免挡光图案71对副显示区A2的透光率产生不良影响，避免降低副显示区A2的透光率，可以使得位于副显示区A2的光学元件50可以采集足够的光线，进而可以使得显示面板100及显示装置1000实现较好的拍照效果。
在另一些示例中，位于副显示区A2同一侧的部分环绕像素电路21a中，沿第二方向Y相邻的至少两个环绕像素电路21a所对应的挡光图案71相连接。
示例性的，如图12b所示，相连接的挡光图案71的外轮廓，可以沿第二方向Y延伸。所有相连接的挡光图案71可以呈多列排列。
示例性的，位于副显示区A2相对两侧的部分环绕像素电路21a中，沿第二方向Y相邻的两个环绕像素电路21a所对应的挡光图案71未连接。也就是说，同一列挡光图案中，位于副显示区A2的相对两侧、且相邻的两个挡光图案71不会沿第二方向Y穿过副显示区A2相连接，这样一来，可以避免对副显示区A2的透光性的影响，避免使得副显示区A2的透光性下降，进而可以使得位于副显示区A2的光学元件50可以采集足够的光线，进而可以使得显示面板100及显示装置1000可以实现较好的拍照效果。
在又一些示例中，如图14及图15所示，挡光层70所包括的多个挡光图案71中的至少四个挡光图案71，可以在第一方向X和第二方向Y上均通过连接图案72相互连接。
在又一些示例中，如图16所示，挡光层71所包括的多个挡光图案71相连接，呈一体结构。挡光层70环绕副显示区A2。
示例性的，“一体结构”指的是，相连接的多个图案同层设置，且该两个图案是连续的，未分隔开。
示例性的，上述多个挡光图案71中，一部分相连接的多个挡光图案71可以沿第一方向X依次排列，和/或，一部分相连接的多个挡光图案71之间可以沿第二方向Y延伸，和/或，其余连接的多个挡光图案71之间可以沿除第一方向和第二方向以外的任意方向延伸。所有相连接的挡光图案71形成的整体轮廓可以环绕副显示区A2的至少一部分。
可选地，挡光层70中的挡光图案71可以为一整体图形，与显示面板100中的环绕像素电路21a相对应设置。该整体图形指的是，除了位于副显示区A2的区域镂空外，其余 区域内没有镂空结构。由此，可以简化显示面板100中挡光层70的制作工艺，同时提高挡光层70对入射至像素电路层20的光线的遮挡效果。
可选地，挡光层70中的挡光图案71可以为一整体图形。该整体图形中，除了位于副显示区A2的区域镂空外，其余区域内也可以具有镂空结构，仅对像素电路21中的部分结构如有源层所在区域进行遮挡。由此，可以降低挡光层70材料的使用量。
在又一些示例中，如图17所示，挡光层70包括同心设置的至少两个挡光环。挡光环包括相连接的多个挡光图案，挡光环环绕副显示区A2的至少部分。
示例性的，多个挡光环的中心可以与副显示区A2的中心重合。
示例性的，挡光环可以为封闭图形，例如圆形、椭圆、矩形等。在这种情况下，挡光环可以环绕整个副显示区A2的区域。
示例性的，挡光环也可以为非封闭图形，例如为圆形或矩形的一部分。在这种情况下，挡光环可以环绕部分副显示区A2的区域。
为了方便描述，本公开中以挡光环为封闭圆形为例进行说明。
示例性的，挡光层70可以包括同心设置的两个或多个挡光环。
采用上述设置方式，可以在外界光线及发光器件发出的光线，经过一系列的折射和/或反射，入射至上述背膜60与空气的界面后，部分光线在该界面发生全反射后射出。该光线中经全反射后射出的那部分光线被挡光层70中的挡光环遮挡，可以避免其照射至与该挡光环对应设置的环绕像素电路21a的至少部分结构，进而可以减缓该环绕像素电路21a的阈值电压漂移问题，进而可以减缓环绕像素电路的驱动电流降低的现象，进而减缓环绕副显示区A2周边的区域的显示亮度的降低现象，进一步地可以减缓显示面板100及显示装置1000出现“进行性暗环”现象。
此外，如上文中所提到的，在背膜60的材料的折射率为1.45，像素电路层20，到背膜与空气界面的距离为11μm的情况下，挡光层70所包括同心设置的两个或多个挡光环中，最大的挡光环的外直径和最小的挡光环的内直径的差值至少为(96×2)μm，即192μm，由此，可以对受到光照的像素电路21进行遮挡，避免光照对像素电路阈值电压的影响，进而可以减缓像素电路的驱动电流降低的现象，进而减缓环绕副显示区A2周边的区域的显示亮度的降低现象，进一步地可以减缓显示面板100及显示装置1000出现“进行性暗环”现象。
在一些实施例中，如图5及图6a所示，沿第一方向X，副显示区A2的相对两侧中，任一侧设置有至少六列环绕像素电路21a。沿第二方向Y，副显示区A2的相对两侧中，任一侧至少设置有至少三行环绕像素电路21a。
示例性的，沿第一方向X，副显示区A2的相对两侧中，任一侧设置有六列或八列环绕像素电路21a。
示例性的，沿第二方向Y，副显示区A2的相对两侧中，任一侧设置有三行或五行环绕像素电路21a。
需要说明的是，如上文中所提到的，在背膜60的材料的折射率为1.45，像素电路层20中有源层，到背膜与空气界面的距离为11μm的情况下，外界光线及发光器件31发出的光线，经过一系列的折射和/或反射，能够照射到的区域范围为：距离副显示区A2的边界线96μm的区域内。而以一个像素电路沿第一方向X的尺寸为32μm，沿第二方向Y上的尺寸为16μm为例，上述距离副显示区A2的边界线96μm的区域，对应6列像素电路 21沿第一方向X的尺寸，以及对应3行像素电路21沿第二方向Y的尺寸。
而本公开采用上述设置方式，在沿第一方向X，副显示区A2的相对两侧中，任一侧设置有至少六列环绕像素电路21a，并在上述至少六列环绕像素电路21a的区域对应的设置挡光层70，可以使得挡光层70对相应的至少六列环绕像素电路21a进行遮挡，避免入射至背膜60和空气的界面的光线发生全反射后入射至上述至少六列环绕像素电路21a，避免上述至少六列环绕像素电路21a中晶体管的有源层受到光照，避免上述至少六列环绕像素电路21a中晶体管的阈值电压漂移，避免与上述至少六列环绕像素电路21a耦接的发光器件31的显示亮度降低。在沿第二方向Y，副显示区A2的相对两侧中，任一侧至少设置有三行环绕像素电路21a，并在上述至少三行环绕像素电路21a的区域对应的设置挡光层70，可以使得挡光层70对相应的至少三行环绕像素电路进行遮挡，避免入射至背膜60和空气的界面的光线发生全反射后入射至上述至少三行环绕像素电路21a，避免上述至少三行环绕像素电路21a中晶体管的有源层受到光照，避免上述至少三行环绕像素电路21a中晶体管的阈值电压漂移，避免与上述至少三行环绕像素电路21a耦接的发光器件的显示亮度降低，进而避免显示面板100及显示装置1000出现“进行性暗环”现象。
在一些实施例中，如图18所示，像素电路层20中的多个像素电路还包括：位于主显示区A1的多个第一像素电路21b。
示例性的，第一像素电路21b可以与位于主显示区A1的第一发光器件31a耦接，从而为第一发光器件31a提供驱动信号驱动第一发光器件31a发光。
在一些示例中，如图6a所示，多个第一像素电路21b在衬底基板10的正投影和多个第一发光器件31a在衬底基板10的正投影至少部分交叠。
例如，第一像素电路21b与相应的第一发光器件31a正对设置。又如，第一像素电路21b与相应的第一发光器件31a部分正对设置。也就是说，第一发光器件31a在第一像素电路21b的正上方或其附近。
在一些示例中，多个环绕像素电路21a中的至少部分环绕像素电路21a为第一像素电路21b。也就是说，至少部分环绕像素电路21a和其驱动的发光器件31为正对设置或部分正对设置。
在一些实施例中，像素电路层20中的多个像素电路还包括：多个第二像素电路21d。
在一些示例中，如图5所示，多个第二像素电路21d位于主显示区A1。多个第二像素电路21d和多个第二发光器件31b通过导电线耦接。
示例性的，第二像素电路21d可以与位于副显示区A2的第二发光器件31b耦接，从而为第二发光器件31b提供驱动信号，驱动第二发光器件31b发光。
此处，第二像素电路21d与相应的第二发光器件31b之间具有一定的距离，由此，需要通过导电线将第二像素电路21d与相应的第二发光器件31b连接。
示例性的，多个环绕像素电路21a中的至少部分环绕像素电路21a为第二像素电路21d。也就是说，部分环绕像素电路21a与相应的发光器件31之间也需要导电线连接。
在另一些示例中，如图6b所示，多个第二像素电路21d位于副显示区A2。
示例性的，位于副显示区A2的多个第二像素电路21d的排布密度，小于位于显示区A的多个像素电路21的排布密度。
示例性的，位于副显示区A2的第二像素电路21d在显示面板100上所占的面积，小于位于显示区A的像素电路21在显示面板100上所占的面积。
采用上述设置方式，可以使得显示面板100中副显示区A2的透光率，大于显示面板100中主显示区A1的透光率，由此，可以使得位于副显示区A2的光学元件50能够接收到足够的光线，从而实现光学元件50的正常工作。
示例性的，多个第二像素电路21d与多个第二发光器件31b耦接，从而为第二发光器件31b提供驱动信号驱动第二发光器件31b发光。
例如，上述多个第二像素电路21d可以仅位于靠近副显示区A2的边界的区域，在副显示区A2中心的位置未设置第二像素电路21d，而多个第二发光器件31b可以为均匀分布在副显示区A2内。
由此，多个第二像素电路21d在衬底基板10的正投影和多个第二发光器件31b在衬底基板10的正投影至少部分交叠。多个第二像素电路21d中，一些第二像素电路21d与相应的第二发光器件31b正对设置，另一些第二像素电路21d与相应的第二发光器件31b部分正对设置。
在又一些示例中，如图6a所示，多个第二像素电路21d位于边框区F。
示例性的，多个第二像素电路21d与多个第二发光器件31b耦接，从而为第二发光器件31b提供驱动信号驱动第二发光器件31b发光。
示例性的，由于上述第二像素电路21d位于边框区F，而第二发光器件31b位于副显示区A2，由此，第二像素电路21d与相应的第二发光器件31b之间具有一定的距离，第二像素电路21d与相应的第二发光器件31b之间通过导电线耦接。
在一些实施例中，如图18所示，像素电路层20还包括：多个冗余像素电路21c。
示例性的，多个冗余像素电路21c与信号线(例如上文中提到的第一扫描信号线Gate1、第二扫描信号线Gate2、数据信号线Data、使能信号线EM等)及发光器件31的阳极层电绝缘。也即，多个冗余像素电路21c均未与信号线(例如上文中提到的第一扫描信号线Gate1、第二扫描信号线Gate2、数据信号线Data、使能信号线EM等)进行耦接，多个冗余像素电路21c均未与发光器件31的阳极层进行耦接。
采用上述设置方式，设置多个冗余像素电路21c，能够提升环绕像素电路21a的均一性，避免环绕像素电路21a产生阈值电压偏移的问题，从而可以解决发光器件中，与靠近副显示区A2的边界的环绕像素电路21a耦接的发光器件31出现的显示异常的问题。
示例性的，如图18所示，多个冗余像素电路21c位于主显示区A1，且环绕副显示区A2的至少一部分。
例如，多个冗余像素电路21c可以围绕副显示区A2的一部分区域。或者，多个冗余像素电路21c可以围绕整个副显示区A2的区域。
示例性的，多个冗余像素电路21c相比于环绕像素电路21a更靠近副显示区A2。
采用上述设置方式，在外界光线及发光器件发出的光线入射至上述背膜60与空气的界面后，部分光线在该界面发生全反射后射出。该光线中经全反射后射出的那部分光线被冗余像素电路21c遮挡，可以避免该光线穿过像素电路层20从显示面板100的出光侧出射，进而避免使得显示面板100及显示装置1000的显示画面异常，从而可以提高显示面板100及显示装置1000的显示效果。
在一些实施例中，如图18所示，在像素电路层20中包括多个环绕像素电路21a和多个冗余像素电路21c的情况下，多个环绕像素电路21a沿第一方向X排列为多列，沿第二方向Y排列为多行。多个冗余像素电路21c沿第一方向X排列为至少一列，沿第二方向Y 排列为至少一行。
在一些示例中，多个冗余像素电路21c沿第一方向X排列为一列或多列。
在一些示例中，多个冗余像素电路21c沿第二方向Y排列为一行或多行。
采用上述设置方式，在像素电路层20的制作过程中，可以将冗余像素电路21c与环绕像素电路21a一起制作，且使得冗余像素电路21c不与信号线及发光器件耦接，从而可以简化像素电路层20中环绕像素电路21a和冗余像素电路21c的制备工艺。
在一些示例中，沿第一方向X，副显示区A2的相对两侧中，任一侧所设置的环绕像素电路21a的列数与冗余像素电路21c的列数之和大于或等于六列。
示例性的，沿第一方向X，副显示区A2的相对两侧中，任一侧所设置的冗余像素电路21c的列数可以小于或等于5列。
例如，在沿第一方向X，副显示区A2的相对两侧中，任一侧所设置的冗余像素电路21c的列数为2的情况下，环绕像素电路21a的列数可以大于或等于4。
又如，在沿第一方向X，副显示区A2的相对两侧中，任一侧所设置的冗余像素电路21c的列数为5的情况下，环绕像素电路21a的列数可以大于或等于1。
在一些示例中，沿第二方向Y，副显示区A2的相对两侧中，任一侧所设置的环绕像素电路21a的行数与冗余像素电路21c的行数之和大于或等于三行。
示例性的，沿第二方向Y，副显示区A2的相对两侧中，任一侧所设置的冗余像素电路21c的行数可以小于或等于2行。
例如，在第二方向Y，副显示区A2的相对两侧中，任一侧所设置的冗余像素电路21c的行数为2的情况下，环绕像素电路21a的行数可以大于或等于1。
又如，在沿第一方向X，副显示区A2的相对两侧中，任一侧所设置的冗余像素电路21c的行数为1的情况下，环绕像素电路21a的行数可以大于或等于2。
采用上述设置方式，可以确保挡光层对环绕像素电路21a的遮挡效果，及对“进行性暗环”的改善效果。另外，在外界光线及副显示区A2的第二发光器件31b发出的光线，经过一系列的折射和/或反射，投射至显示面板100的像素电路层20的情况下，冗余像素电路21c的有源层会受到部分光线的照射，而冗余像素电路21c不与发光器件31相连接，不会对发光器件的发光亮度造成影响，由此可以不在冗余像素电路21c相对应的区域设置挡光层70，仅在与环绕像素电路21a相对应的区域设置挡光层70，进而可以减少挡光层70的材料的使用量。
在一些实施例中，显示面板100还包括：依次层叠在挡光层70远离衬底基板10一侧的半导体层Poly、第一导电层Gate1、第二导电层Gate2、层间介质层ILD、第三导电层SD1、第一平坦层PLN1、第四导电层SD2、第二平坦层PLN2、阳极层AND、像素界定层PDL等。
示例性的，像素电路层20包括：上述依次层叠设置半导体层Poly、第一导电层Gate1、第二导电层Gate2、层间介质层ILD、第三导电层SD1、第一平坦层PLN1、第四导电层SD2。
其中，图19示意出了挡光层70的俯视结构。图20a示意出了半导体层Poly的俯视结构。图20b示意出了挡光层70、半导体层ACT依次层叠设置后的俯视结构。图21示意出了第一导电层Gate1的俯视结构。图22示意出了第二导电层Gate2的俯视结构。图23示意出了层间介质层ILD的俯视结构。图24示意出了第三导电层SD1的俯视结构。图25示 意出了第一平坦层PLN1的俯视结构。图26示意出了第四导电层SD2的俯视结构。图27示意出了第二平坦层PLN2的俯视结构。图28示意出了阳极层AND的俯视结构。图29示意出了像素界定层PDL的俯视结构。
例如，层间介质层ILD、第一平坦层PLN1、第二平坦层PLN2一般采用透明材料制作而成，因此，图23仅示出了层间介质层ILD上过孔的位置，图25仅示出了第一平坦层PLN1上过孔的位置图，27仅示出了第二平坦层PLN2上过孔的位置。
例如，半导体层Poly和第一导电层Gate1之间可以设置有第一栅绝缘层，第一导电层Gate1和第二导电层Gate2之间可以设置有第二栅绝缘层。
示例性的，层间介质层ILD、第一平坦层PLN1、第二平坦层PLN2、第一栅绝缘层、第二栅绝缘层的材料可以为绝缘材料，例如氧化硅、氮化硅、氮氧化硅等。
示例性的，半导体层Poly的材料可以包括非晶硅、单晶硅、多晶硅或金属氧化物半导体材料。
示例性的，第一导电层Gate1、第二导电层Gate2、第三导电层SD1、第四导电层SD2的材料均为可导电材料。第一导电层Gate1、第二导电层Gate2的材料例如可以相同，第三导电层SD1、第四导电层SD2的材料例如可以相同。
例如，第一导电层Gate1、第二导电层Gate2、第三导电层SD1或第四导电层SD2的材料可以为金属材料，该金属材料例如为Al(铝)、Ag(银)、Cu(铜)、Cr(铬)等。
需要说明的是，半导体层Poly在衬底上的正投影，与第一导电层Gate1在衬底上的正投影具有交叠。其中，在半导体层Poly远离衬底的一侧形成第一导电层Gate1后，可以第一导电层Gate1为掩膜，对半导体层Poly进行掺杂处理，使得半导体层Poly中被第一导电层Gate1覆盖的部分，构成各晶体管的有源图案，使得半导体层Poly中未被第一导电层Gate1覆盖的部分，构成导体，该导体可以构成各晶体管的第一极或第二极。第一导电层Gate1与半导体层Poly交叠的部分，构成各晶体管的栅极图案(也即栅极)。
示例性的，像素电路21所包括的各晶体管及存储电容器之间的相对位置关系如图9b所示。沿第一方向X，补偿晶体管T5和开关晶体管T3同行设置，第一发光控制晶体管T6和第二发光控制晶体管T7同行设置。沿第一方向X，驱动晶体管T4位于第二发光控制晶体管T7和第一发光控制晶体管T6之间。沿第二方向Y，驱动晶体管T4还位于开关晶体管T3和第一发光控制晶体管T6之间。沿第一方向X，补偿晶体管T5位于第二复位晶体管T2和开关晶体管T3之间。沿第二方向Y，第二复位晶体管T2还位第二发光控制晶体管T7远离开关晶体管T3的一侧。其中，存储电容器Cst的位置，与驱动晶体管T4的位置相同。
采用上述设置方式，可以使得像素电路21中的各晶体管和存储电容器的排布较为紧密，节省显示面板100上沿第一方向X及沿第二方向Y上的面积，从而可以使得在一定的面积的情况下排布更多的像素电路21，从而可以提高显示面板100及显示装置1000的像素密度，有利于显示面板100及显示装置1000的高PPI设计。
在一些实施例中，如图30所示，显示面板100还包括：设置在像素电路层20中的第一电压信号线VDD和转接层Co。
示例性的，第一电压信号线VDD位于第四导电层SD2。
示例性的，转接层Co可以与第四导电层SD2同层设置。
示例性的，转接层Co可以包括转接图案。
示例性的，挡光层70通过转接图案与第一电压信号线VDD连接。
示例性的，转接图案可以依次穿过第一平坦层PLN1、层间介质层ILD、第二绝缘层GI2、第一绝缘层GI1上的过孔，与挡光层70连接。
例如，转接图案可以位于边框区F，由此，转接图案可以在边框区F与挡光层70连接。
在一些示例中，挡光层70的材料包括钼或石墨。
采用上述设置方式，挡光层70的材料可以导电，在挡光层70与第一电压信号线VDD连接的情况下，由于第一电压信号线VDD传输的信号为恒压信号，可以使得挡光层70上存在恒压信号，进而可以避免挡光层70上的像素电路层20中(例如扫描信号线Gate)的电压信号的稳定性，避免像素电路层的信号受到干扰，提高像素电路层20传输信号的稳定性。
在另一些示例中，挡光层70也可以与其他传输恒压信号的信号线耦接，例如公共电压信号线VSS、第一初始信号线Vinit1、第二初始信号线Vinit2等，从而可以避免挡光层70上的像素电路层20中(例如扫描信号线Gate)的电压信号的稳定性，避免像素电路层的信号受到干扰，提高像素电路层20传输信号的稳定性。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种显示面板，具有显示区，所述显示区包括主显示区和副显示区，所述主显示区围绕所述副显示区的至少一部分；
    所述显示面板包括：
    衬底基板，至少位于所述显示区；
    像素电路层，位于所述衬底基板的一侧且至少位于所述显示区，所述像素电路层包括多个环绕像素电路，所述多个环绕像素电路位于所述主显示区且至少部分围绕所述副显示区；
    挡光层，位于所述主显示区，且位于所述衬底基板和所述像素电路层之间，所述挡光层在所述衬底基板的正投影与所述多个环绕像素电路在所述衬底基板的正投影至少部分交叠。
  2. 根据权利要求1所述的显示面板，其中，所述挡光层包括多个挡光图案；
    一个环绕像素电路的至少部分在所述衬底基板上的正投影，位于一个挡光图案在所述衬底基板上的正投影范围内。
  3. 根据权利要求2所述的显示面板，其中，所述环绕像素电路包括驱动晶体管；
    所述驱动晶体管的有源层在所述衬底基板上的正投影，位于所述挡光图案在所述衬底基板上的正投影范围内。
  4. 根据权利要求3所述的显示面板，其中，所述环绕像素电路还包括与所述驱动晶体管耦接的补偿晶体管；
    所述补偿晶体管的有源层在所述衬底基板上的正投影，位于所述挡光图案在所述衬底基板上的正投影的范围内。
  5. 根据权利要求2～4中任一项所述的显示面板，其中，所述多个环绕像素电路沿第一方向排列为多列，沿第二方向排列为多行；
    位于所述副显示区同一侧的部分环绕像素电路中，沿所述第一方向相邻的至少两个环绕像素电路所对应的挡光图案相连接，和/或，沿所述第二方向相邻的至少两个环绕像素电路所对应的挡光图案相连接。
  6. 根据权利要求2～4中任一项所述的显示面板，其中，所述多个挡光图案相连接，呈一体结构；
    所述挡光层环绕所述副显示区。
  7. 根据权利要求2～4中任一项所述的显示面板，其中，所述挡光层包括同心设置的至少两个挡光环；
    每个挡光环包括相连接的多个挡光图案，所述挡光环环绕所述副显示区的至少部分。
  8. 根据权利要求2～7中任一项所述的显示面板，其中，所述挡光层还包括至少一个连接图案；
    相邻两个所述挡光图案通过所述连接图案相互连接。
  9. 根据权利要求1～8中任一项所述的显示面板，还包括：设置在所述像素电路层中的第一电压信号线和转接层；
    所述挡光层通过所述转接层与所述第一电压信号线连接。
  10. 根据权利要求1～9中任一项所述的显示面板，其中，所述挡光层的材料包括钼或石墨。
  11. 根据权利要求1～10中任一项所述的显示面板，其中，所述多个环绕像素电路沿第 一方向排列为多列，沿第二方向排列为多行；
    沿所述第一方向，所述副显示区的相对两侧中，任一侧设置有至少六列环绕像素电路，
    沿所述第二方向，所述副显示区的相对两侧中，任一侧至少设置有至少三行环绕像素电路。
  12. 根据权利要求1～10中任一项所述的显示面板，其中，所述像素电路层还包括多个冗余像素电路；
    所述多个冗余像素电路位于所述主显示区，且环绕所述副显示区的至少一部分；
    所述多个冗余像素电路相比于所述环绕像素电路更靠近所述副显示区。
  13. 根据权利要求12所述的显示面板，其中，所述多个环绕像素电路沿第一方向排列为多列，沿第二方向排列为多行；所述多个冗余像素电路沿所述第一方向排列为至少一列，沿所述第二方向排列为至少一行；
    沿所述第一方向，所述副显示区的相对两侧中，任一侧所设置的环绕像素电路的列数与冗余像素电路的列数之和大于或等于六列；
    沿所述第二方向，所述副显示区的相对两侧中，任一侧所设置的环绕像素电路的行数与冗余像素电路的行数之和大于或等于三行。
  14. 根据权利要求1～13中任一项所述的显示面板，还包括位于所述主显示区的多个第一发光器件；
    所述像素电路层还包括位于所述主显示区的多个第一像素电路，所述多个第一像素电路与所述多个第一发光器件耦接；
    所述多个环绕像素电路中的至少部分环绕像素电路为第一像素电路。
  15. 根据权利要求1～14中任一项所述的显示面板，还包括位于所述副显示区的多个第二发光器件；
    所述像素电路层还包括位于所述主显示区的多个第二像素电路，所述多个第二像素电路与所述多个第二发光器件通过导电线耦接；
    所述多个环绕像素电路中的至少部分环绕像素电路为第二像素电路。
  16. 根据权利要求1～14中任一项所述的显示面板，还包括位于所述副显示区的多个第二发光器件；
    所述像素电路层还包括位于所述副显示区的多个第二像素电路，所述多个第二像素电路与所述多个第二发光器件耦接。
  17. 根据权利要求权利要求1～14中任一项中所述的显示面板，其中，所述显示面板还具有位于所述显示区的至少一侧的边框区和位于所述副显示区的多个第二发光器件；
    所述像素电路层还包括位于所述边框区的多个第二像素电路，所述多个第二像素电路与所述多个第二发光器件通过导电线耦接。
  18. 一种显示装置，包括：如权利要求1～17任一项中所述的显示面板。
  19. 根据权利要求18所述的显示装置，还包括：
    位于所述挡光层远离所述像素电路层一侧的光学元件，所述光学元件在所述衬底基板上的正投影，位于所述副显示区内。
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