WO2023199570A1 - 半導体装置とその製造方法 - Google Patents

半導体装置とその製造方法 Download PDF

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Publication number
WO2023199570A1
WO2023199570A1 PCT/JP2023/002514 JP2023002514W WO2023199570A1 WO 2023199570 A1 WO2023199570 A1 WO 2023199570A1 JP 2023002514 W JP2023002514 W JP 2023002514W WO 2023199570 A1 WO2023199570 A1 WO 2023199570A1
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layer
type
type deep
semiconductor device
high concentration
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French (fr)
Japanese (ja)
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秀史 高谷
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Denso Corp
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Denso Corp
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Priority to JP2024514809A priority Critical patent/JP7694816B2/ja
Priority to CN202380033608.1A priority patent/CN119054083A/zh
Priority to EP23787993.7A priority patent/EP4510194A4/en
Publication of WO2023199570A1 publication Critical patent/WO2023199570A1/ja
Priority to US18/912,081 priority patent/US20250040205A1/en
Anticipated expiration legal-status Critical
Priority to JP2025091800A priority patent/JP2025122207A/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/157—Impurity concentrations or distributions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide

Definitions

  • the technology disclosed in this specification relates to a semiconductor device and a manufacturing method thereof.
  • JP 2003-309261A and JP 2017-152488A disclose semiconductor devices in which p-type layers and n-type layers are alternately and repeatedly arranged in the plane direction of a semiconductor substrate. When this semiconductor device is turned off, the plurality of p-type layers and the plurality of n-type layers are depleted, and the voltage between the source and drain is maintained.
  • a semiconductor device disclosed in this specification includes a semiconductor substrate provided with a trench on an upper surface, a gate insulating film that covers the inner surface of the trench, and a semiconductor device disposed within the trench, and is separated from the semiconductor substrate by the gate insulating film. and an insulated gate electrode.
  • the semiconductor substrate includes an n-type source layer in contact with the gate insulating film on a side surface of the trench, and a p-type body layer in contact with the gate insulating film on the side surface of the trench located below the source layer. , a plurality of p-type deep layers, each extending from the body layer to below the bottom surface of the trench, and extending along a first direction when the semiconductor substrate is viewed from above.
  • a plurality of layers are arranged at corresponding intervals among a plurality of intervals defined between the p-type deep layers, and are in contact with the gate insulating film on the side surface of the trench located below the body layer.
  • An n-type high concentration layer that is in contact with at least a part of the lower surface of a corresponding p-type deep layer among the plurality of p-type deep layers and has a higher concentration of n-type impurities than the drift layer.
  • the n-type high concentration layer is provided so as to be in contact with at least a part of the lower surface of the p-type deep layer, the depletion layer spreads from the p-type deep layer toward the drift layer when turned on. can be suppressed. Therefore, in the semiconductor device described above, a wide current path is ensured, so that it can have a characteristic of low on-resistance. Further, the n-type high concentration layer is partially provided so as to be in contact with the lower surface of the p-type deep layer. Therefore, in the semiconductor device described above, a decrease in breakdown voltage is also suppressed. The semiconductor device described above can achieve both low on-resistance and high breakdown voltage.
  • a method for manufacturing a semiconductor device disclosed in this specification includes a deep layer forming step of forming a plurality of p-type deep layers and a plurality of n-type deep layers in an n-type epitaxial layer, the plurality of p-type deep layers each extends along a first direction when the epitaxial layer is viewed from above and is spaced apart from each other in a second direction perpendicular to the first direction, and each of the plurality of a deep layer forming step in which each of the n-type deep layers is arranged at a corresponding interval among a plurality of intervals defined between the adjacent p-type deep layers; and the plurality of p-type deep layers.
  • n-type high concentration layer that is in contact with at least a part of the lower surface of the corresponding p-type deep layer and has a higher concentration of n-type impurity than the epitaxial layer; You can prepare. Note that the chronological order of the deep layer forming step and the n-type high concentration layer forming step is not particularly limited.
  • this semiconductor device manufacturing method a semiconductor device that has both low on-resistance and high breakdown voltage can be manufactured.
  • FIG. 2 is a cross-sectional perspective view of the semiconductor device 10 (a diagram showing an xz cross section that does not include the p-type deep layer 36).
  • FIG. 2 is a cross-sectional perspective view of the semiconductor device 10 with the source electrode 22 and the interlayer insulating film 20 omitted (a diagram showing an xz cross section not including the p-type deep layer 36).
  • This is an enlarged xy section including the p-type trench lower layer 35, the p-type deep layer 36, and the n-type deep layer 37, when the semiconductor substrate 12 is viewed from above.
  • 3 is an enlarged cross-sectional view of the semiconductor device 10 showing the arrangement of a deep layer 37.
  • FIG. 2 is an enlarged cross-sectional view of the semiconductor device 10 shown in FIG.
  • FIG. 2 is a cross-sectional perspective view of the semiconductor device 10 (a diagram showing an xz cross section including a p-type deep layer 36).
  • FIG. 7 is an enlarged yz cross-sectional view of a modification of the semiconductor device 10 including a p-type deep layer 36, an n-type deep layer 37, and an n-type high concentration layer.
  • FIG. 7 is an enlarged yz cross-sectional view of a modification of the semiconductor device 10 including a p-type deep layer 36, an n-type deep layer 37, and an n-type high concentration layer.
  • FIG. 7 is an enlarged yz cross-sectional view of a modification of the semiconductor device 10 including a p-type deep layer 36, an n-type deep layer 37, and an n-type high concentration layer.
  • FIG. 2 is an explanatory diagram of a method for manufacturing the semiconductor device 10.
  • FIG. 2 is an explanatory diagram of a method for manufacturing the semiconductor device 10.
  • FIG. 2 is an explanatory diagram of a method for manufacturing the semiconductor device 10.
  • FIG. 2 is an explanatory diagram of a method for manufacturing the semiconductor device 10.
  • FIG. 1 is an explanatory diagram of a method for manufacturing the semiconductor device 10.
  • FIG. 2 is an explanatory diagram of a method for manufacturing the semiconductor device 10.
  • FIG. 2 is an explanatory diagram of a method for manufacturing the semiconductor device 10.
  • FIG. 2 is an explanatory diagram of a method for manufacturing the semiconductor device 10.
  • the semiconductor device 10 shown in FIGS. 1 to 5 is a type of power device called a MOSFET (metal-oxide-semiconductor field effect transistor), and has a semiconductor substrate 12.
  • MOSFET metal-oxide-semiconductor field effect transistor
  • the thickness direction of the semiconductor substrate 12 is referred to as the z direction
  • one direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x direction, which is a direction perpendicular to the x direction and the z direction.
  • the y direction is made of silicon carbide (SiC).
  • the semiconductor substrate 12 may be made of other semiconductor materials such as silicon and gallium nitride.
  • a plurality of trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12. As shown in FIG. 2, the plurality of trenches 14 extend in the y direction on the upper surface 12a. The plurality of trenches 14 are arranged at intervals in the x direction.
  • each trench 14 is covered with a gate insulating film 16.
  • a gate electrode 18 is arranged within each trench 14 .
  • Each gate electrode 18 is insulated from the semiconductor substrate 12 by a gate insulating film 16.
  • the upper surface of each gate electrode 18 is covered with an interlayer insulating film 20.
  • a source electrode 22 is provided on the top of the semiconductor substrate 12 .
  • the source electrode 22 covers each interlayer insulating film 20.
  • Source electrode 22 is insulated from gate electrode 18 by interlayer insulating film 20 .
  • the source electrode 22 is in contact with the upper surface 12a of the semiconductor substrate 12 at a position where the interlayer insulating film 20 is not present.
  • a drain electrode 24 is provided at the bottom of the semiconductor substrate 12 .
  • the drain electrode 24 is in contact with the entire lower surface 12b of the semiconductor substrate 12.
  • the semiconductor substrate 12 includes a plurality of source layers 30, a plurality of contact layers 32, a body layer 34, a plurality of p-type trench lower layers 35, a plurality of p-type deep layers 36, and a plurality of p-type deep layers 36. It has an n-type deep layer 37, a drift layer 38, a plurality of n-type high concentration layers 39, and a drain layer 40.
  • Each source layer 30 is an n-type layer with a high concentration of n-type impurities. Each source layer 30 is arranged in a range that partially includes the upper surface 12a of the semiconductor substrate 12. Each source layer 30 is in ohmic contact with the source electrode 22. Each source layer 30 is in contact with the gate insulating film 16 at the top of the side surface of the trench 14 . Each source layer 30 faces the gate electrode 18 with the gate insulating film 16 in between. Each source layer 30 extends long in the y direction along the side surface of the trench 14. That is, each source layer 30 extends parallel to the longitudinal direction of the trench 14 when looking at the semiconductor substrate 12 from above, and extends from one end of the trench 14 in the longitudinal direction to the other end. ing.
  • Each contact layer 32 is a p-type layer with a high concentration of p-type impurities. Each contact layer 32 is arranged in a range that partially includes the upper surface 12a of the semiconductor substrate 12. Each contact layer 32 is arranged between two corresponding source layers 30. Each contact layer 32 is in ohmic contact with the source electrode 22. Each contact layer 32 extends long in the y direction. That is, each contact layer 32 extends parallel to the longitudinal direction of the trench 14 when looking at the semiconductor substrate 12 from above, and extends from one end of the trench 14 in the longitudinal direction to the other end. ing.
  • the body layer 34 is a p-type layer with a lower concentration of p-type impurities than the contact layer 32.
  • the body layer 34 is arranged below the plurality of source layers 30 and the plurality of contact layers 32.
  • the body layer 34 is in contact with the plurality of source layers 30 and the plurality of contact layers 32 from below.
  • the body layer 34 is in contact with the gate insulating film 16 on the side surface of the trench 14 located below the source layer 30 .
  • the body layer 34 faces the gate electrode 18 with the gate insulating film 16 interposed therebetween.
  • Each p-type trench lower layer 35 is a p-type layer disposed below the corresponding trench 14. As described later, each p-type trench lower layer 35 may be formed in a common ion implantation process with the body layer 34. In this case, the p-type impurity concentration profiles in the depth direction of each p-type trench lower layer 35 and the body layer 34 are the same, and the depth from the bottom surface of the corresponding trench 14 to the lower surface of each p-type trench lower layer 35 is , corresponds to the depth from the upper surface 12a of the semiconductor substrate 12 to the lower surface of the body layer 34. In this example, each p-type trench lower layer 35 is in contact with the gate insulating film 16 covering the bottom surface of the corresponding trench 14. As shown in FIG. 3, when the semiconductor substrate 12 is viewed from above, each p-type trench lower layer 35 extends long along the longitudinal direction (the y direction in this example) of the corresponding trench 14. It extends continuously from one longitudinal end to the other.
  • Each p-type deep layer 36 is a p-type layer that protrudes downward from the lower surface of the body layer 34.
  • the p-type impurity concentration of each p-type deep layer 36 is higher than the p-type impurity concentration of the body layer 34 and lower than the p-type impurity concentration of the contact layer 32.
  • each p-type deep layer 36 extends long in the x direction, with respect to the longitudinal direction of the trench 14 (in this example, the y direction). Orthogonal.
  • the p-type deep layers 36 are spaced apart from each other in the y direction.
  • the p-type deep layer 36 has a long shape in the z direction in the yz cross section.
  • each p-type deep layer 36 in the z direction i.e., the height of the p-type deep layer 36
  • the dimension of the p-type deep layer 36 in the y direction i.e., the width of the p-type deep layer 36.
  • Each p-type deep layer 36 extends from the lower surface of the body layer 34 to a depth below the bottom surface of each trench 14.
  • Each p-type deep layer 36 is in contact with the gate insulating film 16 on the side surface of the trench 14 located below the body layer 34 . Further, as shown in FIG. 3, each p-type deep layer 36 is in contact with a p-type trench lower layer 35 disposed below the trench 14 so as to intersect therewith.
  • Each n-type deep layer 37 is an n-type layer that protrudes downward from the lower surface of the body layer 34.
  • the n-type impurity concentration in each n-type deep layer 37 is higher than the n-type impurity concentration in the drift layer 38.
  • the n-type impurity concentration of each n-type deep layer 37 is lower than the p-type impurity concentration of each p-type deep layer 36.
  • each n-type deep layer 37 may have the same concentration of n-type impurity as the drift layer 38.
  • each n-type deep layer 37 is arranged at a corresponding interval among a plurality of intervals defined by adjacent p-type deep layers 36. As shown in FIGS.
  • each n-type deep layer 37 extends long in the x direction, and is orthogonal to the longitudinal direction of the trench 14 (in this example, the y direction). are doing.
  • Each n-type deep layer 37 is in contact with the side surfaces of the p-type deep layer 36 on both sides thereof.
  • the n-type deep layer 37 has a long shape in the z direction in the yz cross section. That is, the dimension of the n-type deep layer 37 in the z direction (i.e., the height of the n-type deep layer 37) is larger than the dimension of the n-type deep layer 37 in the y direction (i.e., the width of the n-type deep layer 37).
  • the height of the n-type deep layer 37 is equal to the height of the p-type deep layer 36. Note that in this specification, taking into account variations in the ion implantation process, if the difference in the height of the p-type deep layer 36 with respect to the height of the n-type deep layer 37 is within 3%, the height of the n-type deep layer 37 is It is said that the height of the p-type deep layer 36 is the same as that of the p-type deep layer 36.
  • the width of the n-type deep layer 37 is approximately equal to the width of the p-type deep layer 36. As shown in FIGS. 1, 2, and 5, each n-type deep layer 37 extends from the lower surface of the body layer 34 to below the bottom surface of each trench 14.
  • Each n-type deep layer 37 is in contact with the gate insulating film 16 at the side surface of the trench 14 located below the body layer 34 . Further, as shown in FIG. 3, each n-type deep layer 37 is in contact with a p-type trench lower layer 35 disposed below the trench 14 so as to cross.
  • the drift layer 38 is an n-type layer disposed below the plurality of p-type deep layers 36 and the plurality of n-type deep layers 37.
  • the n-type impurity concentration in the drift layer 38 is lower than the n-type impurity concentration in the n-type deep layer 37 .
  • the drift layer 38 is in contact with the n-type deep layer 37 from below.
  • Each n-type high concentration layer 39 is an n-type layer in contact with the entire lower surface of the corresponding p-type deep layer 36.
  • the n-type impurity concentration in each n-type high concentration layer 39 is higher than the n-type impurity concentration in the drift layer 38.
  • the n-type impurity concentration in each n-type high concentration layer 39 may be lower than the n-type impurity concentration in the n-type deep layer 37.
  • Each n-type high concentration layer 39 is arranged between the drift layer 38 and the p-type deep layer 36, and separates the drift layer 38 and the p-type deep layer 36 from each other.
  • Each n-type high concentration layer 39 is partially provided so as to be in contact with the lower surface of the p-type deep layer 36, and is not provided so as to cover at least a portion of the lower surface of the n-type deep layer 37.
  • each n-type high concentration layer 39 does not extend continuously between adjacent p-type deep layers 36, but is separated below the n-type deep layer 37. Therefore, the n-type deep layer 37 and the drift layer 38 are in contact with each other in the region between the adjacent n-type high concentration layers 39.
  • each n-type high concentration layer 39 extends long along the longitudinal direction (y direction in this example) of the corresponding p-type deep layer 36.
  • each n-type high concentration layer 39 is also in contact with the lower surface of the p-type trench lower layer 35 that intersects with the corresponding p-type deep layer 36, and the drift layer 38 and the p-type trench lower layer 35 are in contact with each other. is located between. Note that adjacent n-type high concentration layers 39 may be connected under the p-type trench lower layer 35. In this example, the n-type high concentration layer 39 extends in the y direction along the lower surface of the p-type trench lower layer 35, and may be formed to separate the drift layer 38 and the p-type trench lower layer 35.
  • the drain layer 40 is an n-type layer that has a higher concentration of n-type impurities than the drift layer 38 and the n-type deep layer 37.
  • the drain layer 40 is in contact with the drift layer 38 from below.
  • the drain layer 40 is arranged in a range that includes the lower surface 12b of the semiconductor substrate 12. Drain layer 40 is in ohmic contact with drain electrode 24 .
  • the semiconductor device 10 is used with a higher potential applied to the drain electrode 24 than to the source electrode 22.
  • a potential equal to or higher than the gate threshold is applied to each gate electrode 18, a channel is formed in the body layer 34 near the gate insulating film 16.
  • the source layer 30 and the n-type deep layer 37 are connected by the channel. Therefore, electrons flow from the source layer 30 to the drain layer 40 via the channel, the n-type deep layer 37, and the drift layer 38. That is, the semiconductor device 10 is turned on.
  • the potential of each gate electrode 18 is lowered from a value above the gate threshold to a value below the gate threshold, the channel disappears and the flow of electrons stops. That is, the semiconductor device 10 is turned off.
  • a depletion layer spreads from the p-type deep layer 36 toward the drift layer 38 when the semiconductor device 10 is turned on.
  • the depletion layer spreads toward the drift layer 38 below the n-type deep layer 37, there is a concern that the current path will become narrower and the on-resistance will increase. This increase in on-resistance is called the JFET effect.
  • the semiconductor device 10 since the n-type high concentration layer 39 is provided in contact with the lower surface of the p-type deep layer 36, the depletion layer is prevented from spreading from the p-type deep layer 36 toward the drift layer 38. It will be done.
  • the semiconductor device 10 can have a characteristic of low on-resistance.
  • the thickness of the n-type high concentration layer 39 may be larger than the thickness of the depletion layer generated by the built-in potential in the pn junction between the p-type deep layer 36 and the n-type high concentration layer 39.
  • the JFET effect can be satisfactorily suppressed.
  • the n-type high concentration layer 39 is partially provided under the p-type deep layer 36, is not provided under at least a portion of the n-type deep layer 37, and is not provided under the semiconductor substrate 12. It is not formed continuously in the plane direction. In this way, since the n-type high concentration layer 39 is partially provided, a decrease in breakdown voltage of the semiconductor device 10 is also suppressed.
  • the semiconductor device 10 can achieve both low on-resistance and high breakdown voltage.
  • the n-type high concentration layer 39 is selectively arranged at both ends in the width direction of the lower surface of the corresponding p-type deep layer 36, and It does not touch the entire area. Even in this modification, when the semiconductor device 10 is turned on, it is possible to suppress the depletion layer from expanding from the p-type deep layer 36 toward the drift layer 38 below the n-type deep layer 37. Furthermore, since a portion of the p-type deep layer 36 is in contact with the drift layer 38, when the semiconductor device 10 is turned off, a depletion layer spreads well from the p-type deep layer 36 to the drift layer 38. Therefore, in this modification, the withstand voltage can be improved.
  • the width of the n-type high concentration layer 39 is larger than the width of the corresponding p-type deep layer 36, so that the n-type high concentration layer 39 is larger than the width of the corresponding p-type deep layer 36.
  • it is in contact with the n-type deep layer 37 adjacent to the corresponding p-type deep layer 36 . According to this example, when the semiconductor device 10 is turned on, the expansion of the depletion layer from the p-type deep layer 36 toward the drift layer 38 can be effectively suppressed.
  • the p-type deep layer 36 extends below the n-type deep layer 37.
  • the n-type high concentration layer 39 is in contact with not only the entire lower surface of the p-type deep layer 36 but also the side surface of the p-type deep layer 36 located below the n-type deep layer 37 .
  • the breakdown voltage of the semiconductor device 10 is improved.
  • the n-type high concentration layer 39 is also arranged on the side surface of the p-type deep layer 36, even if the p-type deep layer 36 extends below the n-type deep layer 37, the semiconductor device 10 is turned on.
  • the trade-off between on-resistance and breakdown voltage can be further improved. Note that in this modification as well, as shown in FIG. 6, the n-type high concentration layer 39 is not provided on a part of the lower surface of the p-type deep layer 36, and the p-type deep layer 36 and the drift layer 38 are in contact with each other. may be formed.
  • the semiconductor device 10 is manufactured from a semiconductor substrate entirely composed of the drain layer 40.
  • an n-type epitaxial layer 50 is formed on the drain layer 40 using an epitaxial growth technique.
  • an n-type layer 60 is formed by introducing n-type impurities into a predetermined depth range away from the surface of the epitaxial layer 50 using ion implantation technology. A portion of the epitaxial layer 50 below the n-type layer 60 becomes the drift layer 38.
  • a mask 52 having an opening is patterned on the epitaxial layer 50.
  • n-type impurities are introduced into the upper part of the drift layer 38 through the opening of the mask 52 to form an n-type heavily doped layer 39.
  • p-type impurities are introduced into a portion of the n-type layer 60 through the opening of the mask 52 using ion implantation technology to form a plurality of p-type deep layers 36. .
  • a portion of the n-type layer 60 on which the plurality of p-type deep layers 36 are not formed becomes the plurality of n-type deep layers 37 .
  • the step of forming a plurality of p-type deep layers 36 and a plurality of n-type deep layers 37 among the steps illustrated in FIGS. 10 to 13 is an example of a deep layer forming step. After forming the plurality of p-type deep layers 36, the mask 52 is removed.
  • the mask 52 serves both as an ion implantation mask for forming the n-type high concentration layer 39 and an ion implantation mask for forming the p-type deep layer 36. Therefore, the number of steps can be reduced and manufacturing costs can be held down.
  • the n-type high concentration layer 39 may be formed after the p-type deep layer 36 is formed.
  • the n-type high concentration layer 39 of the modified example shown in FIG. I can do it.
  • the opening width of the ion implantation mask for forming the n-type high concentration layer 39 is wider than the opening width of the ion implantation mask for forming the p-type deep layer 36 without also using the mask 52. By increasing also the n-type high concentration layer 39 of the modified example shown in FIG. 7 can be formed.
  • the source layer 30 and the contact layer 32 are formed by introducing n-type impurities and p-type impurities into the surface layer of the epitaxial layer 50 using ion implantation technology.
  • trenches 14 extending from the surface of the epitaxial layer 50 to the n-type deep layer 37 and the p-type deep layer 36 are formed using etching technology.
  • the depth of the trench 14 is adjusted so as not to exceed the n-type deep layer 37 and the p-type deep layer 36.
  • the trench 14 intersects the plurality of p-type deep layers 36 and the plurality of n-type deep layers 37 when the epitaxial layer 50 is viewed from above.
  • the body layer 34 and the p-type trench lower layer 35 are formed by introducing p-type impurities into the surface of the epitaxial layer 50 in multiple stages using ion implantation technology.
  • the body layer 34 is formed above the n-type deep layer 37 and the p-type deep layer 36 and below the source layer 30 and the contact layer 32.
  • P-type trench lower layer 35 is formed below the bottom surface of trench 14 .
  • the semiconductor device 10 is completed by forming the trench 14, the gate insulating film 16, the gate electrode 18, the interlayer insulating film 20, the source electrode 22, and the drain electrode 24.

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
PCT/JP2023/002514 2022-04-14 2023-01-26 半導体装置とその製造方法 Ceased WO2023199570A1 (ja)

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EP23787993.7A EP4510194A4 (en) 2022-04-14 2023-01-26 Semiconductor device and method for producing same
US18/912,081 US20250040205A1 (en) 2022-04-14 2024-10-10 Semiconductor device and manufacturing method of semiconductor device
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WO2025258666A1 (ja) * 2024-06-13 2025-12-18 株式会社デンソー 半導体装置
WO2026048876A1 (ja) * 2024-08-29 2026-03-05 株式会社デンソー 半導体装置
EP4734698A1 (en) * 2024-10-22 2026-04-29 Samsung Electronics Co., Ltd. Semiconductor device

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WO2025258666A1 (ja) * 2024-06-13 2025-12-18 株式会社デンソー 半導体装置
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