WO2023193754A1 - 相变存储材料和其制备方法、相变存储芯片及设备 - Google Patents

相变存储材料和其制备方法、相变存储芯片及设备 Download PDF

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Publication number
WO2023193754A1
WO2023193754A1 PCT/CN2023/086543 CN2023086543W WO2023193754A1 WO 2023193754 A1 WO2023193754 A1 WO 2023193754A1 CN 2023086543 W CN2023086543 W CN 2023086543W WO 2023193754 A1 WO2023193754 A1 WO 2023193754A1
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phase change
change memory
layer
atomic number
number percentage
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PCT/CN2023/086543
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English (en)
French (fr)
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陈鑫
李响
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华为技术有限公司
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Publication of WO2023193754A1 publication Critical patent/WO2023193754A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors

Definitions

  • This application relates to the field of data storage technology, specifically to a phase change storage material and its preparation method, phase change memory chips and equipment.
  • Phase change memory as a kind of non-volatile memory, has the capability of high-density data storage and fast erasing and writing speed, and has been applied in embedded memory and other aspects.
  • PCM Phase change memory
  • Embodiments of the present application provide a phase change memory material, a preparation method thereof, a phase change memory chip and equipment, which can reduce the power consumption and operation delay of phase change memory chips and equipment.
  • phase change storage material includes a material shown in formula (1);
  • a represents the atomic number percentage of Ti
  • b represents the atomic number percentage of Sb
  • c represents the atomic number percentage of Te
  • D is a doping element, 0 ⁇ d ⁇ 15%.
  • the phase change memory material provided in the embodiment of the present application is a new type of SbTe-based phase change memory material.
  • SbTe When SbTe is crystallized and in the crystalline state, the phase change memory material is in a low resistance state; when SbTe is amorphous, When in the amorphous state, the phase change memory material is in a high resistance state.
  • different resistance states of phase change storage materials can represent different information, thereby realizing the storage of information. And by measuring the resistance state of the phase change storage material, the information can be read.
  • the phase change memory material contains Ti element, wherein Ti and Te form a TiTe nucleation center. Specifically, the bond strength between TiTe is greater than that between SbTe.
  • the TiTe nucleation center can preserve a stable structure when SbTe transitions between the crystalline (i.e., low-resistance) state and the amorphous (i.e., high-resistance) state. Among them, when SbTe converts from the crystalline state (i.e., low resistance state) to the amorphous state (i.e., high resistance state), TiTe, as a nucleation center, can accelerate the conversion of SbTe from the crystalline state to the amorphous state, thus reducing the operation time. extension. Therefore, when applied to storage-level memory, the storage-level memory can have lower latency.
  • the lattice of TiTe and SbTe has a lattice mismatch of 12%.
  • the phase change memory material contains Ti, which can cause lattice distortion or lattice defects of the phase change memory material, making the phase change memory material It is easier to convert from the crystalline state to the amorphous state, which can reduce the power consumption required when converting from crystal to amorphous.
  • the Ti contained in the phase change memory material can reduce the grain size of the phase change memory material, making the grain size distribution more uniform (it can be understood that the smaller the grain size, the smaller the grain size distribution range, The grain size distribution is more uniform), which can improve the fatigue life of phase change memory materials.
  • the value range of the atomic number percentage a of Ti can be 5% ⁇ a ⁇ 40%, or 10% ⁇ a ⁇ 38%, or 15% ⁇ a ⁇ 30%, or 20% ⁇ a ⁇ 35%, and so on. More specifically, in one example, a may be 5%. In one example, a may specifically be 8%. In one example, a may be specifically 10%. In one example, a may specifically be 13%. In one example, a may be specifically 15%. In one example, a may be specifically 18%. In one example, a may be specifically 20%. In one example, a may be specifically 25%. In one example, a may specifically be 28%. In one example, a can be specifically 30%. In one example, a may be specifically 32%. In one example, a may be specifically 35%. In one example, a can be specifically 37%. In one example, a can be specifically 40%. In one example, a may be specifically 45%.
  • the phase change memory material has better performance such as operation delay, power consumption, thermal stability, fatigue life, etc.
  • the ratio of the atomic number percentage b of Sb to the atomic number percentage c of Te can be: 0.5 ⁇ (b:c) ⁇ 1, or 0.5 ⁇ (b:c) ⁇ 2, or 1 ⁇ (b:c) ⁇ 3, or 2 ⁇ (b:c) ⁇ 3, and so on. More specifically, in an example, (b:c) may be 0.5, or (2:3), or 1, or 2, or 3, and so on.
  • phase change memory material when (b:c) is (2:3), the phase change memory material has better performance such as operation delay, power consumption, thermal stability, and fatigue life.
  • the range of the atomic number percentage a of Ti is 20% ⁇ a ⁇ 35%.
  • the ratio of the atomic number percentage b of Sb to the atomic number percentage c of Te is: 2:3.
  • the phase change memory material has lower operating delay, lower power consumption, higher thermal stability, and higher fatigue life.
  • the atomic number percentage d of the doping element D may be 0% ⁇ d ⁇ 10%, or 0% ⁇ d ⁇ 8%, or 3% ⁇ d ⁇ 10%, or It is 3% ⁇ d ⁇ 8%. More specifically, in one example, the atomic number percentage d of the doping element D is 0, that is, the phase change memory material does not contain the doping element D. In one example, d is 1%. In one example, d is 3%. In one example, d is 5%. In one example, d is 8%. In one example, d is 10%. In one example, d is 15%.
  • phase change memory material has lower operating delay and higher fatigue life.
  • the doping element includes one or a combination of at least two of a first non-metal element, a first metal element, a telluride of a first metal element; wherein the first non-metal element is One or a combination of at least two of C, O, N, Si; the first metal element is one of Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Ga, Sn Or at least a combination of two.
  • the doping element is doped into the phase change memory material, which can improve the thermal temperature resistance and fatigue life of the phase change memory material, and can also speed up the crystallization speed of the phase change memory material (that is, from the high resistance state to the phase change memory material). The speed of low-resistance state transition), thereby reducing operation delay.
  • a method for preparing a phase change memory material is provided.
  • the method can be used to prepare the phase change memory material provided in the first aspect.
  • the method includes: using a first deposition method, according to formula (1) The element ratio is used to prepare the phase change storage material; wherein, the first deposition method is one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD);
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • a represents the atomic number percentage of Ti
  • b represents the atomic number percentage of Sb
  • c represents the atomic number percentage of Te
  • D is a doping element, 0 ⁇ d ⁇ 15%.
  • This method can efficiently prepare phase change storage materials, is simple to operate, and is easy to be implemented industrially.
  • the first deposition method is a sputtering method in physical vapor deposition.
  • preparing the phase change memory material includes: according to formula (1) 1) Prepare the first target material according to the atomic number percentage shown in 1); perform sputtering on the first target material to obtain the phase change storage material.
  • the alloy target material can be prepared first, and then the alloy target material can be sputtered to obtain the phase change memory material. This method is simpler and easier to implement, saves preparation time, and is easy to be implemented industrially.
  • the first deposition method is a sputtering method in physical vapor deposition.
  • preparing the phase change memory material includes: The target material and the SbTe alloy target material are co-sputtering to obtain a phase change memory material; among them, the sputtering power of different elemental target materials during the co-sputtering process is adjusted according to the atomic number percentage shown in formula (1).
  • the elemental target material and the alloy target material can be co-sputtering to obtain the phase change memory material.
  • This method is simple and easy to implement, saves preparation time, and is easy to be implemented industrially.
  • a phase change memory chip including: a plurality of memory cells forming a memory cell array; each memory cell includes: a phase change layer, an electrode located on one side of the phase change layer and an electrode located on one side of the phase change layer. An electrode on the other side of the phase change layer; the phase change layer is made of the phase change memory material provided by the first aspect.
  • This phase change memory chip has the advantages of low operating delay, low power consumption, high thermal stability, and high fatigue life.
  • each memory cell further includes: a buffer layer in contact with the phase change layer; wherein the buffer layer is composed of carbon, a third metal, a nitride of the third metal, and a telluride of the fourth metal. made of one; the third metal is one or a combination of at least two of W, Ta, and Ti; the fourth metal is Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, One or a combination of at least two of Bi, Ti, Ga and Sn.
  • introducing a buffer layer in contact with the phase change layer can further improve the performance of the phase change layer and the memory chip.
  • the buffer layer can improve the thermal insulation effect of the phase change layer, reduce the operating power consumption of the phase change memory chip, and at the same time avoid the diffusion of elements in the phase change layer and increase the phase change rate. Adhesion effect between variable layer and electrode.
  • the buffer layer can be used as a phase change memory material
  • the crystallization template can accelerate the conversion speed of the phase change memory material from the amorphous state to the crystalline state, thereby reducing the operating delay of the phase change memory chip, improving the heating efficiency of the phase change memory chip, and reducing the heat loss of the phase change memory chip.
  • Operating power consumption when the material of the buffer layer is a third metal such as W, Ta, or Ti, the buffer layer can avoid the diffusion of elements in the phase change memory material and can also increase the adhesion effect between the phase change layer and the electrode.
  • the buffer layer can increase the adhesion effect between the phase change layer and the electrode, improve the heating efficiency of the phase change memory material, reduce resistance drift, and repair the phase change memory material. Interface voids will increase the adhesion effect between the phase change layer and the electrode, etc.
  • the buffer layer is located between the phase change layer and the electrode; or the buffer layer is located between the phase change layer and the electrode; or the phase change layer has grooves, and the buffer layer is located on the phase change layer in the grooves; alternatively, the buffer layer has grooves, and the phase change layer is located in the grooves of the buffer layer.
  • the phase change layer and the buffer layer can adopt a variety of contact methods, so that the phase change memory chip can be flexibly implemented and easy to prepare.
  • each memory unit further includes at least one phase change layer and at least one chalcogenide compound layer; wherein at least one phase change layer and at least one chalcogenide compound layer are located on the first electrode and the second Between the electrodes, at least one phase change layer and at least one chalcogenide layer are stacked alternately.
  • phase change layer and the chalcogenide compound layer are staggered and stacked, which can introduce more interfaces to the phase change memory material in the phase change memory chip.
  • the interface can reduce heat conduction, thereby reducing the operating power consumption of the phase change memory chip.
  • sulfur-based compounds have good thermal insulation properties and can reduce the operating power consumption of phase change memory chips. Improve the fatigue life of phase change memory chips.
  • the lattice coefficient of the chalcogenide layer is smaller than the lattice coefficient of SbTe.
  • the material of the chalcogenide layer 115 can be TiTe 2 or other materials with a lattice coefficient smaller than that of SbTe, which can prevent the diffusion of elements in the phase change layer and improve the phase change layer or phase change memory chip. fatigue life.
  • a storage device in a fourth aspect, includes a controller and a phase change memory chip provided in the third aspect.
  • the phase change memory chip is used to store data.
  • the controller is used to write data to the memory chip or Read data from this memory chip.
  • an electronic device including a processor and a storage device provided in the fourth aspect.
  • the storage device is used to store data
  • the processor is used to write data to the storage device or read data from the storage device.
  • phase change storage materials and phase change memory chips provided by the embodiments of the present application have lower operating latency.
  • the storage-level memory has lower latency, which can also reduce the storage device and the Operational latency of electronic equipment.
  • the phase change memory material and the phase change memory chip also have low operating power consumption, thereby reducing the power consumption of the storage devices and electronic devices in which they are located.
  • the phase change memory material and phase change memory chip have a high fatigue life, which can increase the service life of the storage equipment and electronic equipment.
  • Figure 1A is a schematic structural diagram of a phase change memory unit provided by an embodiment of the present application.
  • Figure 1B is a schematic structural diagram of another phase change memory unit provided by an embodiment of the present application.
  • Figure 2 is a schematic structural diagram of a phase change memory cell array provided by an embodiment of the present application.
  • Figure 3A is a schematic diagram of the low resistance state of the germanium antimony tellurium system phase change memory material
  • Figure 3B is a schematic diagram of the high resistance state of the germanium antimony tellurium system phase change memory material
  • Figure 4A is a schematic diagram of the low resistance state of the phase change memory material provided by the embodiment of the present application.
  • Figure 4B is a schematic diagram of the high resistance state of the phase change memory material provided by the embodiment of the present application.
  • Figure 5A is a diagram showing the grain size of the phase change memory material provided by the embodiment of the present application.
  • Figure 5B is a diagram showing the grain size of the phase change memory material provided by the embodiment of the present application.
  • Figure 6 is a diagram showing the resistance-temperature curve of the phase change memory material provided by the embodiment of the present application.
  • Figure 7A is a schematic structural diagram of a phase change memory cell array provided by an embodiment of the present application.
  • Figure 7B is a schematic structural diagram of a phase change memory cell array provided by an embodiment of the present application.
  • Figure 7C is a schematic structural diagram of a phase change memory cell array provided by an embodiment of the present application.
  • Figure 7D is a schematic structural diagram of a phase change memory cell array provided by an embodiment of the present application.
  • Figure 7E is a schematic structural diagram of a phase change memory cell array provided by an embodiment of the present application.
  • Figure 8A is a schematic structural diagram of a phase change memory cell array provided by an embodiment of the present application.
  • Figure 8B is a schematic structural diagram of a phase change memory cell array provided by an embodiment of the present application.
  • Figure 8C is a schematic structural diagram of a phase change memory cell array provided by an embodiment of the present application.
  • Figure 8D is a schematic structural diagram of a phase change memory cell array provided by an embodiment of the present application.
  • Figure 9 is a schematic structural diagram of a storage device provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • the term "and/or" is only an association relationship describing associated objects, indicating that there can be three relationships.
  • a and/or B can mean: A alone exists, and A alone exists. There is B, and there are three situations A and B at the same time.
  • the term "plurality" means two or more.
  • multiple systems refer to two or more systems
  • multiple terminals refer to two or more terminals.
  • Phase-change memory chips are a chip that uses the conductivity difference displayed by phase-change storage materials when they transform between crystalline and amorphous states to store data.
  • the atoms in the phase change memory material are arranged in an orderly manner, so that the phase change memory material has long-distance atomic energy levels and high free electron density, so that the phase change memory material has Lower resistivity, therefore, the crystallized state can be called a low-resistance state.
  • the atoms in the phase change memory material are disorderly arranged, resulting in the short-distance atomic energy level and lower free electron density of the phase change memory material, thus making the phase change memory material have higher resistivity.
  • the amorphous state can be called a high resistance state.
  • the phase change memory material in the low resistance state corresponds to one of "0" and "1”
  • the phase change memory material in the high resistance state corresponds to the other of "0" and "1”.
  • the phase change memory material can switch between a high resistance state and a low resistance state.
  • a high and narrow electrical pulse (called a reset pulse) can be applied to the phase change memory chip to convert the phase change memory material from a low resistance state to a high resistance state.
  • a low and broad electrical pulse (called a set pulse) can be applied to the phase change memory chip to convert the phase change memory material from a high resistance state to a low resistance state.
  • the high-resistance state and low-resistance state of the phase change memory material correspond to different bit values.
  • a lower read voltage a voltage that cannot cause the phase change storage material to convert between a high resistance state and a low resistance state
  • FIG. 1A shows an implementation of a phase change memory cell 110, and a corresponding gate 120.
  • the phase change memory unit refers to the memory unit used to store a bit value ("0" or "1") in the phase change memory chip.
  • the phase change memory unit 110 may include an electrode 111 , an electrode 112 , and a phase change layer 113 located between the electrode 111 and the electrode 112 .
  • the phase change layer 113 is made of phase change storage material. A voltage or current is applied to the phase change layer 113 through the electrode 111 and the electrode 112 to implement a writing operation or a reading operation.
  • a current or voltage is applied to the word line 130 to make the word line 130 at a high potential
  • the transistor 120 is turned on, and then a current or voltage is applied to the bit line 140 to make the phase change layer of the phase change memory cell at a high potential.
  • the column selection circuit adds a small preset potential to the bit line 140 (the preset potential will not cause the resistance state of the phase change memory cell to change).
  • the word line 130 is at a high potential, which will affect the potential on the bit line 140, where the magnitude of the influence is related to the resistance of the phase change memory cell.
  • the influence of the word line 130 on the potential on the bit line 140 is equivalent to the phase change memory cell outputting a signal, and the influence result (the potential on the bit line 140 after being affected by the word line 130) is equivalent to the output signal.
  • the influence result is compared with a reference potential to determine the resistance state of the phase change memory cell, and the data stored in the phase change memory cell is determined based on the resistance state.
  • the column selection circuit will be introduced below and will not be described in detail here.
  • phase change memory cell 110 may include sequentially adjacent electrodes 111, phase change layers 113, electrodes 112, gate layers 116 (also called gate tubes 116), and electrodes 117.
  • the phase change layer 113 may include phase change storage material. Electricity may be applied to the phase change layer 113 between the electrode 111 and the electrode 112 voltage or current to implement write or read operations.
  • the electrode 112 may be connected to the word line 130 through the gate layer 116 and the electrode 117.
  • the gate layer 116 is turned on, and the voltage across the gate layer 116 decreases, causing more voltage to be applied to the phase change layer 113 end, so that write operations or read operations can be realized.
  • the material of the gate layer 116 is an ovonic threshold switching (OTS) material including Ge, Se, and As.
  • OTS ovonic threshold switching
  • the OTS material constituting the gate layer 116 may be doped with at least one of Si, N, and S.
  • the gate layer 116 is made of GeAsSe alloy.
  • the material of the gate layer 116 is a GeAsSe alloy doped with at least one of Si, N, C, As, Se, etc.
  • phase change layer 113 the materials of the phase change layer 113, the electrode 111, the electrode 112, the electrode 116 and the electrode 117 will be introduced below. Among them, in the following description, when no special distinction is made between the electrode 111, the electrode 112, the electrode 116, and the electrode 117, they may be simply called electrodes.
  • Figure 2 shows a phase change memory chip, including a phase change memory cell array and peripheral circuits. Among them, the phase change memory cell array is composed of multiple phase change memory cells arranged in a cross pattern to form a high-density memory array.
  • the phase change memory unit 110 may be a phase change memory unit in the phase change memory cell array.
  • the phase change memory unit 110 may adopt the structure shown in FIG. 1A or the structure shown in FIG. 1B.
  • the phase change memory cell array also includes a gate transistor of the phase change memory cell (not shown in FIG. 2 ).
  • a gate transistor of the phase change memory cell For a phase change memory cell, when the bit line and word line are selected at the same time and the gate is in the on state, the phase change memory cell is in the selected state; otherwise, the phase change memory cell is in the unselected state.
  • the processor (not shown) can select the word line 130 through the row selection circuit, select the bit line 140 through the column selection circuit, and control the gate transistor 120 to turn on, thereby selecting the phase change memory cell 110 .
  • the read/write (R/W) circuit can receive a command from the processor, and according to the command, controls the row selection circuit and the column selection circuit, and applies voltage to the phase change memory unit 110 through the word line 130 and the bit line 140 to perform a read operation. or write operation.
  • the driving circuit VS1 can apply voltage to the phase change memory cell 110 through the word line 130 under the control of the row selection circuit, and the driving circuit VS2 can apply voltage to the phase change memory cell 110 through the bit line 140 under the control of the column selection circuit. Voltage.
  • phase change memory chip and the phase change memory unit provided by the embodiments of the present application.
  • phase change memory materials are introduced.
  • phase change power consumption of phase change memory materials i.e., the energy consumption required to promote the conversion between the high resistance state and the low resistance state
  • fatigue life i.e., the energy consumption required to promote the conversion between the high resistance state and the low resistance state
  • phase change speed the time required to convert between the high resistance state and the low resistance state
  • thermal temperature and other properties have an important impact on the operation delay, life and reliability of phase change memory chips.
  • germanium antimony tellurium (GeSbTe, GST) system phase change memory material has better thermal stability and fatigue life.
  • the conversion between the high-resistance state and the low-resistance state involves the breakage and reorganization of the GeTe bonds, which delays the phase transition process (i.e., the conversion speed between the high-resistance state and the low-resistance state is slow ), resulting in a large operation delay (on the order of 100ns), which cannot fully meet the low-latency requirements of storage-class memory (SCM). Therefore, even if the phase change storage material is applied to storage-level memory, the storage-level memory latency will be large.
  • Embodiments of the present application provide a Ti-doped SbTe phase change memory material.
  • Ti doping will improve the thermal stability of the SbTe phase change system, reduce phase change power consumption, and improve fatigue life.
  • the existence of TiTe nucleation center can accelerate crystallization, thereby reducing operation delay.
  • the general chemical formula of Ti-doped SbTe phase change memory material is: Ti a Sb b Te c D d .
  • a represents the atomic number percentage of the chemical element titanium Ti.
  • a represents the proportion of the chemical element titanium Ti in the total number of atoms in the phase change memory material.
  • b represents the atomic number percentage of the chemical element antimony Sb.
  • b represents the proportion of the chemical element antimony Sb in the total number of atoms in the phase change memory material.
  • c represents the atomic number percentage of the chemical element tellurium Te. In other words, c represents the proportion of the chemical element tellurium Te in the total number of atoms in the phase change memory material.
  • phase change memory material provided in the embodiment of the present application, 3% ⁇ a ⁇ 45%, that is, the proportion of 3% ⁇ Ti in the total number of all atoms in the phase change memory material ⁇ 45%.
  • 0.5 ⁇ (b:c) ⁇ 3 that is, in the phase change memory material, the ratio of the number of Sb atoms to the number of Te atoms is greater than or equal to 0.5 and less than or equal to 3.
  • 0 ⁇ d ⁇ 15% that is, doped
  • the proportion of heteroelement D in the total number of atoms in the phase change memory material is ⁇ 15%. That is to say, the phase change memory material may not include doping elements, or may include doping elements, and the atomic percentage of doping elements does not exceed 15%.
  • the phase change memory material provided in the embodiment of the present application is a new type of SbTe-based phase change memory material.
  • SbTe When SbTe is crystallized and in the crystalline state, the phase change memory material is in a low resistance state; when SbTe is amorphous, When in the amorphous state, the phase change memory material is in a high resistance state.
  • different resistance states of phase change storage materials can represent different information, thereby realizing the storage of information. And by measuring the resistance state of the phase change storage material, the information can be read.
  • Ti and Te form a TiTe nucleation center.
  • TiTe has a stronger bonding strength than SbTe.
  • SbTe changes from the crystalline state (i.e., low resistance state) to the amorphous state (i.e. high resistance state)
  • the TiTe nucleation center can preserve a stable structure. Therefore, TiTe nucleation centers exist in both low-resistance and high-resistance states of phase change memory materials.
  • the TiTe nucleation center serves as a recrystallization nucleation center, which can speed up the crystallization speed of SbTe, thus reducing the operation time. extension.
  • crystallization refers to the process in which the atomic structure in the material changes from disorder to orderly arrangement, that is, the process of transforming from amorphous state to crystalline state.
  • the lattice of TiTe and SbTe has a lattice mismatch of 12%.
  • the introduction of Ti into the phase change memory material provided in the embodiment of the present application can cause lattice distortion or lattice defects of TiSbTe, making the phase change memory Materials can more easily convert from a crystalline to amorphous state, which can reduce the power required to convert from crystalline to amorphous.
  • the Ti included in the phase change memory material provided in the embodiment of the present application can reduce the grain size, thereby improving the fatigue life.
  • the Ti contained in the phase change memory material provided in the embodiments of the present application can improve the thermal stability of the phase change memory material in the low resistance state and the high resistance state.
  • the value range of the atomic number percentage a of Ti may be 5% ⁇ a ⁇ 40%, or 10% ⁇ a ⁇ 38%, or 15% ⁇ a ⁇ 30%, or 20 % ⁇ a ⁇ 35%, etc., which will not be listed one by one here.
  • the atomic number percentage a of Ti when the atomic number percentage a of Ti is in the range of 20% ⁇ a ⁇ 35%, the phase change memory material has better performance such as operation delay, power consumption, thermal stability, fatigue life, etc.
  • a may specifically be 5%. In one example, a may specifically be 8%. In one example, a may be specifically 10%. In one example, a may specifically be 13%. In one example, a may be specifically 15%. In one example, a may be specifically 18%. In one example, a may be specifically 20%. In one example, a may be specifically 25%. In one example, a may specifically be 28%. In one example, a can be specifically 30%. In one example, a may be specifically 32%. In one example, a may be specifically 35%. In one example, a can be specifically 37%. In one example, a can be specifically 40%. In one example, a may be specifically 45%.
  • the ratio of the atomic number percentage b of Sb to the atomic number percentage c of Te may be 0.5 ⁇ (b:c) ⁇ 1, or 0.5 ⁇ (b : c) ⁇ 2, or 1 ⁇ (b: c) ⁇ 3, or 2 ⁇ (b: c) ⁇ 3, etc., which will not be listed here.
  • (b:c) can be specifically 0.5, or (2:3), or 1, or 2, or 3. Wait, I won’t list them all here.
  • (b:c) is (2:3), the phase change memory material has better performance such as operation delay, power consumption, thermal stability, and fatigue life.
  • the value range of the atomic number percentage a of Ti is 20% ⁇ a ⁇ 35%.
  • the ratio of the atomic number percentage b of Sb to the atomic number percentage c of Te is (2: 3). At this time, phase change memory materials have lower operating delays, lower power consumption, higher thermal stability, and higher fatigue life.
  • the doping element D may be one or a combination of at least two non-metallic elements such as C, O, N, Si, etc. In some embodiments, the doping element D may be one or a combination of at least two metal elements such as Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Ga, Sn, etc. In some embodiments, the doping element D may be one or at least two tellurides of metal elements such as Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Ga, Sn, etc. The combination.
  • the doping element D can be non-metallic elements such as C, O, N, Si, etc., and metals such as Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Ga, Sn, etc. elements and one or a combination of at least two of the tellurides of these metallic elements.
  • Adding the doping element D to the phase change memory material can improve the thermal temperature resistance and fatigue life of the phase change memory material, and can also speed up the crystallization speed of the phase change memory material (that is, the speed of transformation from a high resistance state to a low resistance state) , thereby reducing operation latency.
  • the atomic number percentage d of the doping element D may be 0% ⁇ d ⁇ 10%, or 0% ⁇ d ⁇ 8%, or 3% ⁇ d ⁇ 10%, or 3% ⁇ d ⁇ 8%. Among them, when d is 3% ⁇ d ⁇ 8%, the phase change memory material has lower operating delay and higher fatigue life.
  • the atomic number percentage d of the doping element D is 0, that is, the phase change memory material does not contain the doping element D.
  • d is 1%. In one example, d is 3%. In one example, d is 5%. In one example, d is 8%. In one example, d is 10%. In one example, d is 15%.
  • the above example introduces the composition of phase change storage materials.
  • the example introduces the preparation scheme of phase change storage materials.
  • material deposition methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) can be used.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • Ti The phase change memory material is deposited on the substrate with the element ratio shown by Sb b Te c D d .
  • the base material can be an electrode, an electrode, a buffer layer to be introduced below, a chalcogenide compound layer to be introduced below, or other specific base materials, which will not be specified here. Let’s not go into details.
  • phase change memory materials are prepared on the substrate.
  • different deposition rates can be obtained by controlling the power of different targets, thereby obtaining phase change memory materials with corresponding component ratios.
  • the sputtering method in physical vapor deposition can be used to prepare the phase change memory material on the substrate through single target sputtering.
  • the doping element D is not included, or the doping element D1 is not N and/or O, Ti elemental target material, Sb elemental target material, Te elemental target material and the doping element D (when the corresponding When the change material contains a doping element D)
  • the elemental target is sputtered to prepare the phase change memory material on the substrate.
  • the doping element D1 is N
  • titanium nitride alloy targets, Sb elemental targets, and Te elemental targets can be used for sputtering to prepare phase change memory materials on the substrate.
  • titanium oxide alloy targets, Sb elemental targets, and Te elemental targets can be used for sputtering to prepare phase change memory materials on the substrate.
  • different deposition rates can be obtained by controlling the power of different targets, thereby obtaining phase change memory materials with corresponding component ratios.
  • the Ti a Sb b Te c D d alloy may be first prepared (eg, smelted). Then, the Ti a Sb b Te c D d alloy is used for sputtering to prepare the phase change memory material on the substrate.
  • a phase change memory material with an elemental composition of Ti 8 Sb 36.8 Te 55.2 was prepared. details as follows.
  • the Ti elemental target material and the SbTe alloy target material with an atomic percentage purity of not less than 99.99% at different target positions in the sputtering chamber.
  • the ratio of Sb atoms to Te atoms in the SbTe alloy is 2:3.
  • Sputtering power is applied to the Ti elemental target and the SbTe alloy target to generate sputtering glow.
  • the sputtering power applied to the Ti elemental target is 10W
  • the sputtering power applied to the SbTe alloy target is 7W.
  • the argon gas flow rate during the sputtering process was 35 sccm. In this way, a phase change memory material whose elemental composition is Ti 8 Sb 36.8 Te 55.2 can be prepared on the substrate.
  • phase change memory material whose elemental composition is Ti 22 Sb 31.2 Te 46.8 is prepared. details as follows.
  • the Ti elemental target material and the SbTe alloy target material with an atomic percentage purity of not less than 99.99% at different target positions in the sputtering chamber.
  • the ratio of Sb atoms to Te atoms in the SbTe alloy is 2:3.
  • Sputtering power is applied to the Ti elemental target and the SbTe alloy target to generate sputtering glow.
  • the sputtering power applied to the Ti elemental target is 30W
  • the sputtering power applied to the SbTe alloy target is 7W.
  • the argon gas flow rate during the sputtering process was 35 sccm. In this way, a phase change memory material whose elemental composition is Ti 22 Sb 31.2 Te 46.8 can be prepared on the substrate.
  • a phase change memory material with an elemental composition of Ti 28 Sb 28.8 Te 43.2 was prepared. details as follows.
  • the Ti elemental target material and the SbTe alloy target material with an atomic percentage purity of not less than 99.99% at different target positions in the sputtering chamber.
  • the ratio of Sb atoms to Te atoms in the SbTe alloy is 2:3.
  • Sputtering power is applied to the Ti elemental target and the SbTe alloy target to generate sputtering glow.
  • the sputtering power applied to the Ti elemental target is 40W
  • the sputtering power applied to the SbTe alloy target is 7W.
  • the argon gas flow rate during the sputtering process was 35 sccm. In this way, a phase change memory material whose elemental composition is Ti 22 Sb 31.2 Te 46.8 can be prepared on the substrate.
  • a phase change memory material with an elemental composition of Ti 3 Sb 38.8 Te 58.2 was prepared.
  • specific preparation process reference can be made to the description in Embodiment 1, which will not be described again here.
  • a phase change memory material with an elemental composition of Ti 45 Sb 18.8 Te 36.2 was prepared.
  • a phase change memory material with an elemental composition of Ti 40 Sb 23.8 Te 36.2 was prepared.
  • a phase change memory material whose elemental composition is Ti 21 Sb 29.6 Te 44.4 C 5 is prepared.
  • the smelting element composition is Ti 21 Sb 29.6 Te 44.4 C 5 alloy. Place the Ti 21 Sb 29.6 Te 44.4 C 5 alloy at the target position in the sputtering chamber. Place the substrate on the sample stage in the sputtering chamber. Applying sputtering power to Ti 21 Sb 29.6 Te 44.4 C 5 alloy produces sputter glow. Thus, the Ti 21 Sb 29.6 Te 44.4 C 5 alloy is sputtered onto the substrate to prepare a Ti 21 Sb 29.6 Te 44.4 C 5 phase change memory material.
  • a phase change memory material whose elemental composition is Ti 25.7 Sb 27.7 Te 41.6 C 5 is prepared.
  • the smelting element composition is Ti 25.7 Sb 27.7 Te 41.6 C 5 alloy. Place the Ti 25.7 Sb 27.7 Te 41.6 C 5 alloy at the target position in the sputtering chamber. Place the substrate on the sample stage in the sputtering chamber. Applying sputtering power to Ti 25.7 Sb 27.7 Te 41.6 C 5 alloy produces sputter glow. Thus, the Ti 25.7 Sb 27.7 Te 41.6 C 5 alloy is sputtered onto the substrate to prepare a Ti 25.7 Sb 27.7 Te 41.6 C 5 phase change memory material.
  • a phase change memory material whose elemental composition is Ti 17 Sb 31.2 Te 46.8 O 5 is prepared.
  • the smelting element composition is Ti 17 Sb 31.2 Te 46.8 O 5 alloy. Place the Ti 17 Sb 31.2 Te 46.8 O 5 alloy at the target position in the sputtering chamber. Place the substrate on the sample stage in the sputtering chamber. Applying sputtering power to Ti 17 Sb 31.2 Te 46.8 O 5 alloy produces sputtering glow. Thus, the Ti 17 Sb 31.2 Te 46.8 O 5 alloy is sputtered onto the substrate to prepare a Ti 17 Sb 31.2 Te 46.8 O 5 phase change memory material.
  • a phase change memory material whose elemental composition is Ti 14 Sb 31.2 Te 46.8 Si 8 is prepared.
  • the smelting element composition is Ti 14 Sb 31.2 Te 46.8 Si 8. gold.
  • the Ti 14 Sb 31.2 Te 46.8 Si 8 alloy is sputtered onto the substrate to prepare a Ti 14 Sb 31.2 Te 46.8 Si 8 phase change memory material.
  • phase change memory material prepared in Example 1 and the phase change memory material prepared in Example 2 were respectively observed using a transmission electron microscope. The results are shown in Figure 5A and Figure 5B respectively. It can be seen that when the atomic percentage of Ti in the phase change memory material is 8%, some grain sizes are tens of nm. When the atomic percentage of Ti in the phase change memory material is increased to 28%, the grain size can be reduced to within 10 nm. This shows that Ti can reduce the grain size in phase change memory materials, making the grain size distribution more uniform (it can be understood that the smaller the grain size, the smaller the grain size distribution range, making the grain size distribution more uniform) , thereby reducing or avoiding the short fatigue life of phase change memory materials caused by uneven grain sizes. In other words, when the atomic percentage of Ti in the phase change memory material is higher (for example, 28%), the fatigue life of the phase change memory material is higher.
  • curve 601a is a heating curve
  • curve 601b is a cooling curve
  • curve 602a is a heating curve
  • curve 602b is a cooling curve
  • curve 603a is a heating curve
  • curve 603b is a cooling curve
  • the cooling curve represents the change in resistance during the cooling process.
  • the heating curve is used to represent the change in resistance during the heating process.
  • the resistance decreases, indicating that the phase change memory material is crystallizing.
  • the resistance of the phase change storage material remains basically unchanged, indicating that the crystallization has been completed.
  • the initial resistance of the phase change memory material becomes lower and the crystallization temperature increases.
  • the abscissa of the position where the resistance decreases fastest is the crystallization temperature.
  • the crystallization temperature of the phase change material prepared in Example 1 is approximately 210°C
  • the crystallization temperature of the phase change material prepared in Example 2 is approximately 240°C
  • the crystallization temperature of the phase change material prepared in Example 3 is approximately 260°C. about.
  • the initial resistance refers to the resistance corresponding to the minimum temperature on each curve in Figure 6.
  • Ti is added to the phase change memory material, which increases the crystallization temperature of the phase change memory material, that is, improves the thermal stability of the phase change memory material.
  • phase change memory material provided in the embodiments of the present application.
  • phase change memory chip formed by the phase change memory material provided in the embodiment of the present application is introduced.
  • phase change memory chip provided by the embodiment of the present application may include a phase change memory cell memory array and peripheral circuits.
  • phase change memory cell memory array and peripheral circuits.
  • the phase change memory cell array may be composed of multiple phase change memory cells.
  • the structure of the phase change memory cell can be implemented with reference to the structure shown in FIG. 1A.
  • the structure of the phase change memory cell can be implemented with reference to the structure shown in Figure 1B.
  • the phase change layer 113 in the phase change memory unit 110 may be a phase change memory material provided by the embodiment of the present application.
  • the material of the electrode can be metal material, non-metal material, metal nitride, etc.
  • the material of the electrode 1 may be one or a combination of at least two of tungsten (W), carbon (C), tantalum Ta, titanium nitride (TiN), tantalum nitride (TaN), etc.
  • W tungsten
  • C carbon
  • Ta tantalum Ta
  • TiN titanium nitride
  • TaN tantalum nitride
  • the embodiments of this application do not specifically limit the material of the electrode.
  • the phase change memory unit 110 may further include a buffer layer 114.
  • the buffer layer 114 is in contact with the phase change layer 113 and is also located between the electrode 111 and the electrode 112 .
  • the material of buffer layer 114 may be Carbon (C) and other non-metals.
  • the buffer layer 114 may be made of non-metal such as carbon (C).
  • the material of the buffer layer 114 may be metal such as W, Ta, Ti, etc.
  • the buffer layer 114 may be made of metal nitride such as TiN or TaN.
  • the material of the buffer layer 114 may be telluride of metals such as Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Bi, Ti, Ga, Sn, etc.
  • the buffer layer 114 in contact with the phase change layer 113 in the phase change memory unit 110 can further improve the performance of the phase change layer 113.
  • the buffer layer 114 can improve the heat insulation effect of the phase change layer 113, reduce the operating power consumption of the phase change memory unit, and at the same time avoid the phase change layer.
  • the elements in 113 diffuse and will increase the adhesion effect between the phase change layer and the electrode.
  • the buffer layer 114 can be used as a phase change memory material.
  • the crystallization template can accelerate the conversion speed of the phase change storage material from the amorphous state to the crystalline state, thereby reducing the operation delay of the phase change storage operation unit 110, improving the heating efficiency of the phase change storage unit 110, and reducing the phase change.
  • the operating power consumption of the storage unit 110 is not limited to.
  • the buffer layer 114 can avoid the diffusion of elements in the phase change memory material and can also increase the adhesion effect between the phase change layer and the electrode.
  • the buffer layer 114 is made of metal nitride, the buffer layer 114 can increase the adhesion effect between the phase change layer and the electrode, improve the heating efficiency of the phase change memory material, reduce resistance drift, and repair the phase change memory material interface. voids, and will increase the adhesion effect between the phase change layer and the electrode, etc.
  • the materials and functions of the buffer layer 114 are introduced above. Next, an example is provided to introduce the positional relationship between the buffer layer 114 and the phase change layer 113 .
  • the buffer layer 114 is in contact with the phase change layer 113 , and the buffer layer 114 is located between the phase change layer 113 and the electrode 111 .
  • the buffer layer 114 is in contact with the phase change layer 113 , and the buffer layer 114 is located between the phase change layer 113 and the electrode 112 .
  • phase change memory cell 110 includes two buffer layers 114 , each buffer layer 114 being in contact with phase change layer 113 .
  • One buffer layer 114 is located between the phase change layer 113 and the electrode 111
  • the other buffer layer 114 is located between the phase change layer 113 and the electrode 112 .
  • the materials of the two buffer layers 114 may be the same or different.
  • the materials of the two buffer layers 114 are non-metals such as carbon (C), metals such as W and Ta, metal nitrides such as TiN and TaN, or Zr, Cr, Al, Sc, Y, Ta, Tellurides of metals such as Hf, Er, In, Ge, Bi, Ti, Ga, Sn, etc.
  • one of the two buffer layers 114 is made of a non-metal such as carbon (C), and the other is made of a non-metal such as carbon (C); or one of the two buffer layers 114 is made of a metal nitride such as TiN, TaN, etc.
  • the other material is telluride of metals such as carbon (C), such as Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Bi, Ti, Ga, Sn, etc.; etc., which will not be discussed here. List them one by one.
  • C carbon
  • the materials of the two buffer layers 114 are different, so that the phase change memory unit 110 can have the corresponding advantages of the two materials.
  • the phase change layer 113 has a groove, and the buffer layer 114 is located in the groove of the phase change layer 113 and is in contact with the phase change layer 113 . That is, the phase change layer 113 surrounds the buffer layer 114 .
  • the buffer layer 114 has a groove, and the phase change layer 113 is located in the groove of the buffer layer 114 and is in contact with the buffer layer 114 . That is, the buffer layer 114 surrounds the phase change layer 113 .
  • phase change layer 113 and the buffer layer 114 may also have other positional relationships, which are not listed here.
  • the phase change memory unit 110 may further include at least one chalcogenide layer 115 and at least one phase change layer 113. At least one phase change layer 113 and the at least one chalcogenide compound layer 115 are stacked alternately and are located between the electrode 111 and the electrode 112 .
  • the chalcogenide layer 115 may be made of metal sulfide, such as GeS x .
  • the material of the chalcogenide layer 115 may be metal Te compound, such as TiTe 2 , Hf x Te y , Zr x Te y .
  • the material of the chalcogenide layer 115 itself can also be a phase change memory material, such as Sb x Te y , Ge x Sby Tez , Ge x Te y , Bix Te y , In x Te y, etc.
  • phase change memory material such as Sb x Te y , Ge x Sby Tez , Ge x Te y , Bix Te y , In x Te y, etc.
  • the subscripts x, y, and z respectively represent the proportions of the corresponding atoms.
  • the phase change layer 113 and the chalcogenide layer 115 are staggered and stacked. It is not difficult to understand that there is an interface between a phase change layer 113 and an adjacent chalcogenide compound layer 115. In this way, the staggered stacking of the phase change layer 113 and the chalcogenide compound layer 115 can introduce more energy into the phase change memory material.
  • the interface can reduce heat conduction, thereby reducing the operating power consumption of the phase change memory unit 110 and improving the fatigue life of the phase change memory unit 110.
  • the chalcogenide compound has good thermal insulation properties, which can reduce the operating power consumption of the phase change memory unit 110 and improve the fatigue life of the phase change memory unit 110 .
  • the lattice coefficient of the chalcogenide compound layer 115 is smaller than the lattice coefficient of the phase change memory material improved in the embodiment of the present application, thereby preventing elements of the phase change layer 113 from being Diffusion improves the fatigue life of the phase change layer 113 or the phase change memory cell 110.
  • At least one chalcogenide layer 115 and at least one phase change layer 113 are staggered stacks or periodically arranged. , can start from the phase change layer 113 and end at the chalcogenide compound layer 115 to form n periodic repeated superpositions.
  • n is an integer greater than or equal to 1.
  • At least one chalcogenide layer 115 and at least one phase change layer 113 are staggered stacks or periodically arranged. , can start from the chalcogenide compound layer 115 and end at the phase change layer 113, forming n periodic repeated superpositions.
  • n is an integer greater than or equal to 1.
  • n is an integer greater than or equal to 1.
  • At least one chalcogenide layer 115 and at least one phase change layer 113 are staggered stacks or periodically arranged. , may start with the phase change layer 113 and end with the phase change layer 113 . Between the phase change layer 113 at the start position and the phase change layer 113 at the end position, there are n chalcogenide compound layers 115 and phase change layers 113 that are periodically repeatedly superimposed.
  • phase change memory unit 11 at least one chalcogenide compound layer 115 is spaced between the two phase change layers 113, and at least one phase change layer is spaced between the two chalcogenide compound layers 115.
  • n is an integer greater than or equal to 1.
  • n is an integer greater than or equal to 1.
  • At least one chalcogenide layer 115 and at least one phase change layer 113 are staggered or periodically arranged. , may start with the sulfide compound layer 115 and end with the sulfide compound layer 115 . Between the chalcogenide compound layer 115 at the starting position and the chalcogenide compound layer 115 at the end position, n number of phase change layers 113 and chalcogenide compound layers 115 are formed that are repeatedly superimposed periodically.
  • phase change memory unit 11 at least one chalcogenide compound layer 115 is spaced between the two phase change layers 113, and at least one phase change layer is spaced between the two chalcogenide compound layers 115.
  • n is an integer greater than or equal to 1.
  • n is an integer greater than or equal to 1.
  • phase change layer 113 and the chalcogenide compound layer 115 uses the structure shown in FIGS. 8A to 8D as an example to introduce the positional relationship between the phase change layer 113 and the chalcogenide compound layer 115 , but this is not exhaustive. In other embodiments, the phase change layer 113 and the chalcogenide compound layer 115 may also have other positional relationships, which are not listed here.
  • an embodiment of the present application provides a storage device 900 including a phase change memory chip 910 and a controller 920 .
  • the phase change memory chip 910 can be used to store data, and the controller 920 can be used to write data to the phase change memory chip 910 or read data from the phase change memory chip 910 .
  • the phase change memory chip 910 may include multiple phase change memory cells.
  • Cell 110, the plurality of phase change memory cells 110 form a memory cell array in the memory device 900.
  • the phase change memory chip 910 can be implemented with reference to the above introduction to the embodiment shown in FIG. 2 .
  • the controller 920 can be a device with data processing capabilities and is used to control the peripheral circuit of the phase change memory chip 910 to write data to the phase change memory chip 910 or read data from the phase change memory chip 910 .
  • an embodiment of the present application provides an electronic device 1000, which may include a processor 1010 and a storage device 900.
  • the storage device 900 may be used to store data, such as applications, configuration files, etc. of the electronic device 1000 .
  • the storage device 900 can provide data storage space for the processor 1010 so that the processor 1010 can write data into the data storage space.
  • the data stored in the storage device 900 can be read or called by the processor 1010 .
  • the processor 1010 is used to write data to the storage device 900 or read data from the storage device 900 .
  • the processor 1010 can write data to the phase change memory chip 910 or read data from the phase change memory chip 910 through the controller 920 .
  • the processor 1010 can call the data in the storage device 900 to implement the corresponding functions of the electronic device 1000 .
  • the storage device 900 may serve as the memory of the electronic device 1000 . In some embodiments, the storage device 900 may serve as an external memory of the electronic device 1000 . In some embodiments, the processor 1010 may be a neural-network processing unit (NPU). In some embodiments, the storage device 900 may also be other forms of devices with data storage capabilities in the electronic device 1000 . This application does not specifically limit the implementation form of the storage device 900.
  • processor 1010 may be a central processing unit (CPU). In some embodiments, processor 1010 may be a graphics processing unit (GPU). In some embodiments, the processor 1010 may be an application specific integrated circuit (ASIC). In some embodiments, the processor 1010 may be a neural-network processing unit (NPU). In some embodiments, the processor 1010 may also be other forms of devices with data processing capabilities in the electronic device 100 . This application does not specifically limit the implementation form of the processor 1010.
  • the electronic device 1010 may be a server, a mobile terminal (such as a mobile phone, a tablet computer, a notebook computer) or a vehicle-mounted terminal.
  • a mobile terminal such as a mobile phone, a tablet computer, a notebook computer
  • vehicle-mounted terminal such as a vehicle-mounted terminal.

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Abstract

本申请涉及数据存储技术领域，具体涉及一种相变存储材料和其制备方法、相变存储芯片及设备，该相变存储材料包括TiaSbbTecDd所示的材料；其中，a代表Ti的原子个数百分比，b代表Sb的原子个数百分比，c代表Te的原子个数百分比，d代表D元素的原子个数百分比，a+b+c+d＝1；3％≤a≤45％，且0.5≤(b：c)≤3；D为掺杂元素，0≤d≤15％。该相变存储材料具有较低的操作功耗和操作时延。

Description

相变存储材料和其制备方法、相变存储芯片及设备
本申请要求于2022年4月6日提交中国专利局、申请号为202210356787.X、发明名称为“相变存储材料和其制备方法、相变存储芯片及设备”的中国专利申请的优先权，所述专利申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及数据存储技术领域，具体涉及一种相变存储材料和其制备方法、相变存储芯片及设备。
背景技术
信息技术的发展，对存储器提出了低延时、大容量的需求。其中，低延时有助于提高数据处理速度。大容量有助于提高存储密度，以及节省存储器制造成本。
相变存储器(phase change memory，PCM)作为一种非易失存储器，具有高密度数据存储的能力和较快的擦写速度，已应用到在嵌入式存储器等方面。但是，目前的相变存储器难以兼顾低功耗和低操作时延，性能较差。
发明内容
本申请实施例提供了一种相变存储材料和其制备方法、相变存储芯片及设备，可以降低相变存储芯片以及设备的功耗和操作时延。
第一方面，提供了一种相变存储材料，该相变存储材料包括如式(1)所示的材料；
TiaSbbTecDd(1)；
其中，a代表Ti的原子个数百分比，b代表Sb的原子个数百分比，c代表Te的原子个数百分比，d代表D元素的原子个数百分比，a+b+c+d＝1；3％≤a≤45％，且0.5≤(b：c)≤3；D为掺杂元素，0≤d≤15％。
本申请实施例提供的相变存储材料为一种新型的SbTe基相变存储材料，其中，当SbTe晶化，处于晶态时，该相变存储材料处于低阻态；当SbTe非晶化，处于非晶态时，该相变存储材料处于高阻态。其中，相变存储材料不同的阻态可以代表不同信息，从而实现信息的存储。并且可以通过测量相变存储材料的阻态，可以实现信息的读取。
该相变存储材料含有Ti元素，其中，Ti和Te形成TiTe成核中心。具体而言，TiTe之间键强度大于SbTe之间的键强度。在SbTe在晶态(即低阻态)和非晶态(即高阻态)之间转换时，TiTe成核中心能保存稳定的结构。其中，当SbTe从晶态(即低阻态)向非晶态(即高阻态)转换时，TiTe作为成核中心，可以加快SbTe从晶态向非晶态的转换，从而可以降低操作时延。由此，在应用到存储级内存时，可使得存储级内存具有较低的时延。
并且，TiTe与SbTe的晶格有12％的晶格失配度，该相变存储材料中包含Ti，可以导致该相变存储材料的晶格畸变或者说晶格缺陷，使得该相变存储材料更容易从晶态转化为非晶态，从而可以降低由晶体到非晶体转换时所需的功耗。
另外，该相变存储材料中包含的Ti，可以降低该相变存储材料的晶粒尺寸，使得晶粒尺寸分布更为均匀(可以理解，晶粒尺寸越小，晶粒尺寸分布范围越小，晶粒尺寸分布更为均一)，从而可以提高相变存储材料的疲劳寿命。
在一种可能的实施方式中，Ti的原子个数百分比a的取值范围可以为5％≤a≤40％，或 者为10％≤a≤38％，或者为15％≤a≤30％，或者为20％≤a≤35％，等等。更具体地，在一个例子中，a具体可以为5％。在一个例子中，a具体可以为8％。在一个例子中，a具体可以为10％。在一个例子中，a具体可以为13％。在一个例子中，a具体可以为15％。在一个例子中，a具体可以为18％。在一个例子中，a具体可以为20％。在一个例子中，a具体可以为25％。在一个例子中，a具体可以为28％。在一个例子中，a具体可以为30％。在一个例子中，a具体可以为32％。在一个例子中，a具体可以为35％。在一个例子中，a具体可以为37％。在一个例子中，a具体可以为40％。在一个例子中，a具体可以为45％。
其中，当Ti的原子个数百分比a的取值范围为20％≤a≤35％时，相变存储材料的操作时延、功耗、热稳定性、疲劳寿命等性能更佳。
在一种可能的实施方式中，Sb的原子个数百分比b比上Te的原子个数百分比c的比值可以为：0.5≤(b：c)≤1，或者为0.5≤(b：c)≤2，或者为1≤(b：c)≤3，或者为2≤(b：c)≤3，等等。更具体地，在一个例子中，(b：c)具体可以为0.5，或者为(2：3)，或者为1，或者为2，或者为3，等等。
其中，当(b：c)为(2：3)时，相变存储材料的操作时延、功耗、热稳定性、疲劳寿命等性能更佳。
在一种可能的实施方式中，Ti的原子个数百分比a的取值范围为20％≤a≤35％，同时，Sb的原子个数百分比b比上Te的原子个数百分比c的比值为2：3。
在该实施方式中，相变存储材料具有更低的操作时延、更低的功耗、更高热稳定性、更高疲劳寿命。
在一种可能的实施方式中，掺杂元素D的原子个数百分比d可以为0％≤d≤10％，或者为0％≤d≤8％，或者为3％≤d≤10％，或者为3％≤d≤8％。更具体地，在一个例子中，掺杂元素D的原子个数百分比d为0，即相变存储材料不含掺杂元素D。在一个例子中，d为1％。在一个例子中，d为3％。在一个例子中，d为5％。在一个例子中，d为8％。在一个例子中，d为10％。在一个例子中，d为15％。
其中，当d为3％≤d≤8％时，相变存储材料具有更低的操作时延、更高疲劳寿命。
在一种可能的实施方式中，掺杂元素包括第一非金属元素、第一金属元素、第一金属元素的碲化物中的一种或至少两种的组合；其中，第一非金属元素为C、O、N、Si中的一种或至少两种的组合；第一金属元素为Zr、Cr、Al、Sc、Y、Ta、Hf、Er、In、Ge、Ga、Sn中的一种或至少两种的组合。
在该实施方式中，该掺杂元素掺杂到相变存储材料中，可以提升相变存储材料的热温度性和疲劳寿命，还可以加快相变存储材料的结晶速度(即由高阻态向低阻态转化的速度)，从而降低操作时延。
第二方面，提供了一种相变存储材料的制备方法，该方法可以用于制备第一方面提供的相变存储材料，该方法包括：使用第一沉积方式，按照式(1)所示的元素比例，制备相变存储材料；其中，第一沉积方式属于化学气相沉积CVD、物理气相沉积PVD、原子层沉积ALD中的一种；
其中，TiaSbbTecDd   (1)；
其中，a代表Ti的原子个数百分比，b代表Sb的原子个数百分比，c代表Te的原子个数百分比，d代表D元素的原子个数百分比，a+b+c+d＝1；3％≤a≤45％，且0.5≤(b：c)≤3；D为掺杂元素，0≤d≤15％。
该方法可以高效地制备相变存储材料，操作简便，易于工业化实施。
在一种可能的实施方式中，第一沉积方式为物理气相沉积中的溅射方式，使用第一沉积方式，按照式(1)所示的元素比例，制备相变存储材料包括：按照式(1)所示的原子个数百分比，制备第一靶材；对第一靶材进行溅射，得到相变存储材料。
在该实施方式中，可以先制备合金靶材，然后，对合金靶材进行溅射，得到相变存储材料。该方式更为简单易行，且节省制备时间，易于工业化实施。
在一种可能的实施方式中，第一沉积方式为物理气相沉积中的溅射方式，使用第一沉积方式，按照式(1)所示的元素比例，制备相变存储材料包括：对Ti单质靶材和SbTe合金靶材，进行共溅射，得到相变存储材料；其中，按照式(1)所示的原子个数百分比，调节共溅射过程中不同单质靶材的溅射功率。
在该实施方式中，可对单质靶材和合金靶材进行共溅射，得到相变存储材料。该方式简单易行，且节省制备时间，易于工业化实施。
第三方面，提供了一种相变存储芯片，包括：包括多个存储单元，多个存储单元形成存储单元阵列，每个存储单元包括：相变层、位于相变层一侧的电极和位于相变层另一侧的电极；相变层由第一方面提供的相变存储材料制成。
该相变存储芯片具有操作时延低、功耗低、热稳定性高、疲劳寿命高等优势。
在一种可能的实施方式中，每个存储单元还包括：与相变层接触的缓冲层；其中，缓冲层由碳、第三金属、第三金属的氮化物、第四金属的碲化物中的一种制成；第三金属为W、Ta、Ti中的一种或至少两种的组合，第四金属为Zr、Cr、Al、Sc、Y、Ta、Hf、Er、In、Ge、Bi、Ti、Ga、Sn中的一种或至少两种的组合。
在该实施方式中，引入与相变层接触的缓冲层，可以进一步提升相变层以及存储芯片的性能。具体而言，当缓冲层的材质为碳时，缓冲层可以提高相变层的隔热效果，降低相变存储芯片的操作功耗，同时可以避免相变层中的元素扩散，并将增加相变层和电极之间的黏附效果。当缓冲层的材质为Zr、Cr、Al、Sc、Y、Ta、Hf、Er、In、Ge、Bi、Ti、Ga、Sn等第四金属的碲化物时，缓冲层可以作为相变存储材料的结晶模板，可以加速相变存储材料从非晶态向晶态的转换速度，从而可以降低相变存储芯片的操作时延，并且可以提高相变存储芯片的加热效率，降低相变存储芯片的操作功耗。当缓冲层的材质为W、Ta、Ti等第三金属时，缓冲层可以避免相变存储材料中元素扩散，也可以增加相变层和电极之间的黏附效果。当缓冲层的材质为第三金属的氮化物时，缓冲层可以增加相变层和电极之间的粘附效果、提升相变存储材料的加热效率、减小电阻漂移、以及修复相变存储材料界面空洞，并将增加相变层和电极之间的黏附效果等。
在一种可能的实施方式中，缓冲层位于相变层和电极之间；或者，缓冲层位于所述相变层和电极之间；或者，相变层具有凹槽，缓冲层位于相变层的凹槽中；或者，缓冲层具有凹槽，相变层位于缓冲层的凹槽中。
在该实施方式中，相变层和缓冲层可以采用多种接触方式，使得相变存储芯片可以灵活实现，便于制备。
在一种可能的实施方式中，每个存储单元还包括至少一个相变层和至少一个硫系化合物层；其中，至少一个相变层和至少一个硫系化合物层均位于第一电极和第二电极之间，且至少一个相变层和至少一个硫系化合物层交错堆叠。
在该实施方式中，相变层和硫系化合物层交错堆叠，可以为相变存储芯片中的相变存储材料引入更多的界面，界面可以降低热传导，从而减少相变存储芯片的操作功耗、提高相变存储芯片的疲劳寿命。并且，硫系化合物的绝热性能好，可以减少相变存储芯片的操作功耗、 提高相变存储芯片的疲劳寿命。
在一种可能的实施方式中，硫系化合物层的晶格系数小于SbTe的晶格系数。
在该实施方式中，硫系化合物层115的材质可以采用TiTe2等晶格系数小于小于SbTe的晶格系数的材料，可以防止相变层的元素扩散，提高相变层或者说相变存储芯片的疲劳寿命。
第四方面，提供了一种存储设备，该存储设备包括控制器及第三方面提供的相变存储芯片，该相变存储芯片用于存储数据，该控制器用于向该存储芯片写入数据或者从该存储芯片读取数据。
第五方面，提供了一种电子设备，包括处理器及第四方面提供的存储设备，存储设备用于存储数据，处理器用于向存储设备写入数据或者从存储设备读取数据
本申请实施例提供的相变存储材料以及相变存储芯片具有较低的操作时延，在应用到存储级内存时，使得存储级内存具有较低的时延，进而也可以降低所在存储设备以及电子设备的操作时延。并且，该相变存储材料以及相变存储芯片还具有较低的操作功耗，从而可以降低所在存储设备以及电子设备的功耗。另外，该相变存储材料以及相变存储芯片具有较高的疲劳寿命，从而可以提高所在存储设备以及电子设备的使用寿命。
附图说明
图1A为本申请实施例提供的一种相变存储单元的结构示意图；
图1B为本申请实施例提供的另一种相变存储单元的结构示意图；
图2为本申请实施例提供的一种相变存储单元阵列的结构示意图；
图3A为锗锑碲体系相变存储材料的低阻态示意图；
图3B为锗锑碲体系相变存储材料的高阻态示意图；
图4A为本申请实施例提供的相变存储材料的低阻态示意图；
图4B为本申请实施例提供的相变存储材料的高阻态示意图；
图5A为本申请实施例提供的相变存储材料的晶粒尺寸展示图；
图5B为本申请实施例提供的相变存储材料的晶粒尺寸展示图；
图6为本申请实施例提供的相变存储材料的电阻-温度曲线展示图；
图7A为本申请实施例提供的一种相变存储单元阵列的结构示意图；
图7B为本申请实施例提供的一种相变存储单元阵列的结构示意图；
图7C为本申请实施例提供的一种相变存储单元阵列的结构示意图；
图7D为本申请实施例提供的一种相变存储单元阵列的结构示意图；
图7E为本申请实施例提供的一种相变存储单元阵列的结构示意图；
图8A为本申请实施例提供的一种相变存储单元阵列的结构示意图；
图8B为本申请实施例提供的一种相变存储单元阵列的结构示意图；
图8C为本申请实施例提供的一种相变存储单元阵列的结构示意图；
图8D为本申请实施例提供的一种相变存储单元阵列的结构示意图；
图9为本申请实施例提供的一种存储设备的结构示意图；
图10为本申请实施例提供的一种电子设备的结构示意图。
具体实施方式
下面将结合附图，对本申请实施例中的技术方案进行描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以适合的方式结合。
可以理解的是，在本申请实施例的描述中，“示例性的”、“例如”或者“举例来说”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”、“例如”或者“举例来说”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”、“例如”或者“举例来说”等词旨在以具体方式呈现相关概念。
在本申请实施例的描述中，术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，单独存在B，同时存在A和B这三种情况。另外，除非另有说明，术语“多个”的含义是指两个或两个以上。例如，多个系统是指两个或两个以上的系统，多个终端是指两个或两个以上的终端。
相变存储芯片以一种利用相变存储材料在晶态和非晶态之间相互转化时所表现出来的导电性差异来存储数据的芯片。具体而言，在晶体状态下，相变存储材料中的原子有序排列，使得相变存储材料具有相变材料具有长距离的原子能级和较高的自由电子密度，从而使得相变存储材料具有较低的电阻率，因此，可以将晶化态称为低阻态。在非晶化状态下，相变存储材料中的原子无序排列，使得相变存储材料短距离的原子能级和较低的自由电子密度，从而使得相变存储材料具有较高的电阻率，因此，可以将非晶化态称为高阻态。其中，可以设定低阻态的相变存储材料对应“0”和“1”中的一个，高阻态的相变存储材料对应“0”和“1”中的另一个。
当向相变存储材料施加特定的脉冲电压时，相变存储材料可在高阻态与低阻态之间转换。具体而言，可以给相变存储芯片施加一个高而窄的电脉冲(可称之为reset脉冲)，使得相变存储材料从低阻态转化为高阻态。可以给相变存储芯片施加一个低而宽的电脉冲(可称之为set脉冲)，使得相变存储材料从高阻态转化为低阻态。由此，可以实现相变存储材料的写操作。
另外，相变存储材料的高阻态和低阻态分别对应不同的比特值。如此，可以向相变存储材料施加较低的读电压(不能促使相变存储材料在高阻态与低阻态之间转换的电压)，来读取相变存储材料的电阻值，实现读操作。
图1A示出了相变存储单元110的一种实现形式，以及对应的选通器120。其中，相变存储单元是指相变存储芯片中用于存储一个比特值(“0”或“1”)的存储单元。如图1A所示，相变存储单元110可以包括电极111、电极112，以及位于电极111和电极112之间的相变层113。其中，相变层113由相变存储材料制成。通过电极111和电极112向相变层113施加电压或电流，以实现写操作或读操作。
其中，在写入时，给字线130施加电流或电压，使字线130处于高电位，晶体管120导通，然后向位线140施加电流或电压，使相变存储单元的相变层在高阻态与低组态之间转化，以进行写操作。在读出时，列选择电路给位线140加一个小的预设电位(该预设电位不会使相变存储单元的阻态发生变化)。如上所述，字线130处于高电位，会影响位线140上的电位，其中，影响大小与相变存储单元的电阻大小相关。字线130对位线140上的电位的影响相当于相变存储单元输出了信号，影响结果(受字线130影响后，位线140上的电位)相当于输出的信号。将该影响结果与一个参考电位进行比较，从而确定相变存储单元的电阻状态，根据电阻状态确定相变存储单元所存储的数据。其中，列选择电路将在下文进行介绍，此处不再赘述。
图1B示出了相变存储单元110的另一种实现方式。该相变存储单元110可以包括依次相邻的电极111、相变层113、电极112、选通层116(也可以称为选通管116)、电极117。其中，相变层113可包括相变存储材料。可以向电极111和电极112之间的相变层113施加电 压或电流，以实现写操作或读操作。
具体而言，电极112可以通过选通层116、电极117连接到字线130。其中，当选通层116两端的电压差超过选通层116的阈值转变电压Vth时，选通层116导通，选通层116两端电压降低，导致更多电压施加到相变层113两端，从而可以实现写操作或读操作。
在一些实施例中，选通层116的材质为包括Ge、Se及As的阈值转变器件(ovonic threshold switching，OTS)材料。其中，构成选通层116的OTS材料可以掺杂有Si、N、S中的至少一种。在一些实施例中，选通层116的材质为GeAsSe合金。在一些实施例中，选通层116的材质为掺杂有Si、N、C、As、Se等中的至少一种的GeAsSe合金。
另外，相变层113、电极111、电极112、电极116以及电极117的材质将在下文进行介绍。其中，在下文描述中，当对电极111、电极112、电极116以及电极117不做特别区分时，它们可以被简称为电极。图2示出了一种相变存储芯片，包括相变存储单元阵列和外围电路。其中，相变存储单元阵列由多个相变存储单元交叉排布，形成高密度的存储阵列。其中，相变存储单元110可以为该相变存储单元阵列中的一个相变存储单元。相变存储单元110可以采用图1A所示的结构，也可以采用图1B所示的结构。另外，当相变存储单元阵列中相变存储单元具体为图1A所示的结构时，相变存储单元阵列还包括相变存储单元的选通晶体管(图2未示出)。对于相变存储单元而言，当位线和字线被同时选中，且选通器处于导通状态时，该相变存储单元处于选中状态，否则，该相变存储单元处于未选中状态。处理器(未示出)可以通过行选择电路选择字线130，通过列选择电路选择位线140，并控制选通晶体管120导通，从而选中相变存储单元110。读写(R/W)电路可以接收处理器的命令，并根据该命令，控制行选择电路、列选择电路，通过字线130、位线140向相变存储单元110施加电压，以进行读操作或写操作。其中，驱动电路VS1可以在行选择电路的控制下，通过字线130向相变存储单元110施加电压，驱动电路VS2可以在列选择电路的控制下，通过位线140向相变存储单元110施加电压。
上文示例介绍了本申请实施例提供的相变存储芯片以及相变存储单元的结构。接下来，介绍相变存储材料。
相变存储材料的相变功耗(即促使高阻态与低阻态之间转换所需的能耗)、疲劳寿命、相变速度(高阻态与低阻态之间转换所需的时间)、热温度等性能，对相变存储芯片的操作时延、寿命、可靠性具有重要影响。传统的锗锑碲(GeSbTe，GST)体系相变存储材料，虽然具有较佳的热稳定性和疲劳寿命。但是，如图3A和图3B所示，高阻态与低阻态之间的转换，涉及GeTe键的断裂和重组，延缓了相变过程(即高阻态与低阻态之间转换速度慢)，导致操作时延较大(100ns量级)，不能完全满足存储级内存((storage-class memory，SCM))对低时延的要求。因此，即使将该相变存储材料应用到存储级内存，也导致存储级内存时延较大。
本申请实施例提供了一种Ti掺杂SbTe相变存储材料，Ti掺杂会提升SbTe相变体系的热稳定性，降低相变功耗，提升疲劳寿命。同时TiTe成核中心的存在能加速结晶，从而降低操作时延。Ti掺杂SbTe相变存储材料的化学通式为：TiaSbbTecDd。其中，a代表化学元素钛Ti的原子个数百分比。换言之，a代表化学元素钛Ti在相变存储材料中所有原子个数总和中的占比。b代表化学元素锑Sb的原子个数百分比。换言之，b代表化学元素锑Sb在相变存储材料中所有原子个数总和中的占比。c代表化学元素碲Te的原子个数百分比。换言之，c代表化学元素碲Te在相变存储材料中所有原子个数总和中的占比。d代表掺杂元素D的原子个数百分比。换言之，d代表掺杂元素D在相变存储材料中所有原子个数总和中的占比。简而言之，a+b+c+d＝1。
在本申请实施例提供的相变存储材料中，3％≤a≤45％，即3％≤Ti在相变存储材料中所有原子个数总和中的占比≤45％。并且，0.5≤(b：c)≤3，即在相变存储材料中，Sb的原子数量比上Te的原子数量为大于或等于0.5，小于或等于3。0≤d≤15％，即掺杂元素D在相变存储材料中所有原子个数总和中的占比≤15％。也就是说，在相变存储材料可以不包括掺杂元素，也可以包括掺杂元素，且掺杂元素的原子百分比不超过15％。
本申请实施例提供的相变存储材料为一种新型的SbTe基相变存储材料，其中，当SbTe晶化，处于晶态时，该相变存储材料处于低阻态；当SbTe非晶化，处于非晶态时，该相变存储材料处于高阻态。其中，相变存储材料不同的阻态可以代表不同信息，从而实现信息的存储。并且可以通过测量相变存储材料的阻态，可以实现信息的读取。
参阅图4A和图4B，在本申请实施例提供的相变存储材料中，Ti和Te形成的TiTe成核中心，TiTe具有比SbTe更强的成键强度，在SbTe从晶态(即低阻态)向非晶态(即高阻态)转换时，TiTe成核中心能保存稳定的结构。因此，TiTe成核中心在相变存储材料的低阻态和高阻态均存在。在相变存储材料由高阻态(即非晶态)向低阻态(即晶态)转化时，TiTe成核中心作为再结晶的成核中心，可以加快SbTe的结晶速度，从而降低操作时延。其中，结晶是指材料中的原子结构从无序混乱变为有序排列的过程，即从非晶态转化为晶态的过程。
并且，TiTe与SbTe的晶格有12％的晶格失配度，在本申请实施例提供的相变存储材料中引入Ti，可以导致TiSbTe的晶格畸变或者说晶格缺陷，使得相变存储材料更容易从晶态转化为非晶态，从而可以降低由晶体到非晶体转换时所需的功耗。
以及，经过实验测试，本申请实施例提供的相变存储材料所包括的Ti可以降低晶粒尺寸，从而提高疲劳寿命。
此外，经过实验测试，本申请实施例提供的相变存储材料所包含的Ti可以提升相变存储材料在低阻态以及高阻态的热稳定性。
在一些实施例中，Ti的原子个数百分比a的取值范围可以为5％≤a≤40％，或者为10％≤a≤38％，或者为15％≤a≤30％，或者为20％≤a≤35％，等等，此处不再一一列举。其中，当Ti的原子个数百分比a的取值范围为20％≤a≤35％时，相变存储材料的操作时延、功耗、热稳定性、疲劳寿命等性能更佳。
在一个例子中，a具体可以为5％。在一个例子中，a具体可以为8％。在一个例子中，a具体可以为10％。在一个例子中，a具体可以为13％。在一个例子中，a具体可以为15％。在一个例子中，a具体可以为18％。在一个例子中，a具体可以为20％。在一个例子中，a具体可以为25％。在一个例子中，a具体可以为28％。在一个例子中，a具体可以为30％。在一个例子中，a具体可以为32％。在一个例子中，a具体可以为35％。在一个例子中，a具体可以为37％。在一个例子中，a具体可以为40％。在一个例子中，a具体可以为45％。
在一些实施例中，Sb的原子个数百分比b比上Te的原子个数百分比c的比值，即(b：c)，可以为0.5≤(b：c)≤1，或者为0.5≤(b：c)≤2，或者为1≤(b：c)≤3，或者为2≤(b：c)≤3，等等，此处不再一一列举。
在一个例子中，(b：c)具体可以为0.5，或者为(2：3)，或者为1，或者为2，或者为3。等等，此处不再一一列举。其中，当(b：c)为(2：3)时，相变存储材料的操作时延、功耗、热稳定性、疲劳寿命等性能更佳。
在一些实施例中，Ti的原子个数百分比a的取值范围为20％≤a≤35％，同时，Sb的原子个数百分比b比上Te的原子个数百分比c的比值为(2：3)。此时，相变存储材料具有更低的操作时延、更低的功耗、更高热稳定性、更高疲劳寿命。
在一些实施例中，掺杂元素D具体可以为C、O、N、Si等非金属元素中的一种或者至少两种的组合。在一些实施例中，掺杂元素D具体可以为Zr、Cr、Al、Sc、Y、Ta、Hf、Er、In、Ge、Ga、Sn等金属元素中的一种或至少两种的组合。在一些实施例中，掺杂元素D具体可以为Zr、Cr、Al、Sc、Y、Ta、Hf、Er、In、Ge、Ga、Sn等金属元素的碲化物中的一种或至少两种的组合。在一些实施例中，掺杂元素D具体可以为C、O、N、Si等非金属元素，Zr、Cr、Al、Sc、Y、Ta、Hf、Er、In、Ge、Ga、Sn等金属元素以及这些金属元素的碲化物中的一种或至少两种的组合。
在相变存储材料中加入掺杂元素D，可以提升相变存储材料的热温度性和疲劳寿命，还可以加快相变存储材料的结晶速度(即由高阻态向低阻态转化的速度)，从而降低操作时延。
在一些实施例中，掺杂元素D的原子个数百分比d可以为0％≤d≤10％，或者为0％≤d≤8％，或者为3％≤d≤10％，或者为3％≤d≤8％。其中，当d为3％≤d≤8％时，相变存储材料具有更低的操作时延、更高疲劳寿命。
在一个例子中，掺杂元素D的原子个数百分比d为0，即相变存储材料不含掺杂元素D。在一个例子中，d为1％。在一个例子中，d为3％。在一个例子中，d为5％。在一个例子中，d为8％。在一个例子中，d为10％。在一个例子中，d为15％。
上文示例介绍了相变存储材料的成分，接下来，示例介绍相变存储材料的制备方案。
在本申请实施例中，可以采用化学气相沉积(chemical vapor deposition，CVD)、物理气相沉积(physical vapor deposition，PVD)、或者原子层沉积(atomic layer deposition，ALD)等材料沉积方式，按照TiaSbbTecDd所示的元素比例，在基材上沉积相变存储材料。其中，基材可以为电极，也可以为电极，也可以为即将在下文介绍的缓冲层，也可以为即将在下文介绍的硫系化合物层，也可以为其他具体基材，在此不再一一赘述。
在一些实施例中，对Ti单质靶材和SbTe合金靶材，在基材上制备相变存储材料。在溅射过程中，可以通过控制不同靶材的功率来获得不同沉积速率，从而得到相应成分配比的相变存储材料。
在一些实施例中，具体可以采用物理气相沉积中的溅射方式(例如磁控溅射法)，通过单靶材溅射，在基材上制备相变存储材料。具体而言，当不含掺杂元素D，或者掺杂元素D1不为N和/或O时，可以采用Ti单质靶材、Sb单质靶材、Te单质靶材以及掺杂元素D(当相变材料含有掺杂元素D时)单质靶材，进行溅射，以在基材上制备相变存储材料。当掺杂元素D1为N时，可以采用氮化钛合金靶材、Sb单质靶材、Te单质靶材，进行溅射，在基材上制备相变存储材料。当掺杂元素D1为O时，可以采用氧化钛合金靶材、Sb单质靶材、Te单质靶材，进行溅射，在基材上制备相变存储材料。在溅射过程中，可以通过控制不同靶材的功率来获得不同沉积速率，从而得到相应成分配比的相变存储材料。
在一些实施例中，可以先制备(例如冶炼)TiaSbbTecDd合金。然后，采用TiaSbbTecDd合金进行溅射，以在基材上制备相变存储材料。
接下来，在具体的实施例中，介绍相变存储材料的制备过程。
实施例1
制备元素成分为Ti8Sb36.8Te55.2的相变存储材料。具体如下。
将原子百分比纯度不低于99.99％的Ti单质靶材、SbTe合金靶材分别置于溅射腔内的不同靶材位置。其中，SbTe合金中Sb的原子比上Te的原子为2：3。将基材置于溅射腔内的样品台上。向Ti单质靶材、SbTe合金靶材施加溅射功率，产生溅射辉光。向Ti单质靶材施加的溅射功率为10W，向SbTe合金靶材施加的溅射功率为7W。溅射过程中氩气流量为35sccm。 如此，可以在基材上制备得到元素成分为Ti8Sb36.8Te55.2的相变存储材料。
实施例2
制备元素成分为Ti22Sb31.2Te46.8的相变存储材料。具体如下。
将原子百分比纯度不低于99.99％的Ti单质靶材、SbTe合金靶材分别置于溅射腔内的不同靶材位置。其中，SbTe合金中Sb的原子比上Te的原子为2：3。将基材置于溅射腔内的样品台上。向Ti单质靶材、SbTe合金靶材施加溅射功率，产生溅射辉光。向Ti单质靶材施加的溅射功率为30W，向SbTe合金靶材施加的溅射功率为7W。溅射过程中氩气流量为35sccm。如此，可以在基材上制备得到元素成分为Ti22Sb31.2Te46.8的相变存储材料。
实施例3
制备元素成分为Ti28Sb28.8Te43.2的相变存储材料。具体如下。
将原子百分比纯度不低于99.99％的Ti单质靶材、SbTe合金靶材分别置于溅射腔内的不同靶材位置。其中，SbTe合金中Sb的原子比上Te的原子为2：3。将基材置于溅射腔内的样品台上。向Ti单质靶材、SbTe合金靶材施加溅射功率，产生溅射辉光。向Ti单质靶材施加的溅射功率为40W，向SbTe合金靶材施加的溅射功率为7W。溅射过程中氩气流量为35sccm。如此，可以在基材上制备得到元素成分为Ti22Sb31.2Te46.8的相变存储材料。
实施例4
制备元素成分为Ti3Sb38.8Te58.2的相变存储材料。具体制备过程可以参考实施例1的描述，在此不再赘述。
实施例5
制备元素成分为Ti45Sb18.8Te36.2的相变存储材料。具体制备过程可以参考实施例1的描述，在此不再赘述。
实施例6
制备元素成分为Ti40Sb23.8Te36.2的相变存储材料。具体制备过程可以参考实施例1的描述，在此不再赘述。
实施例7
制备元素成分为Ti21Sb29.6Te44.4C5的相变存储材料。冶炼元素成分为Ti21Sb29.6Te44.4C5的合金。将Ti21Sb29.6Te44.4C5合金置于溅射腔内的靶材位置。将基材置于溅射腔内的样品台上。向Ti21Sb29.6Te44.4C5合金施加溅射功率，产生溅射辉光。由此，将Ti21Sb29.6Te44.4C5合金溅射到基材上，制备得到Ti21Sb29.6Te44.4C5相变存储材料。
实施例8
制备元素成分为Ti25.7Sb27.7Te41.6C5的相变存储材料。冶炼元素成分为Ti25.7Sb27.7Te41.6C5的合金。将Ti25.7Sb27.7Te41.6C5合金置于溅射腔内的靶材位置。将基材置于溅射腔内的样品台上。向Ti25.7Sb27.7Te41.6C5合金施加溅射功率，产生溅射辉光。由此，将Ti25.7Sb27.7Te41.6C5合金溅射到基材上，制备得到Ti25.7Sb27.7Te41.6C5相变存储材料。
实施例9
制备元素成分为Ti17Sb31.2Te46.8O5的相变存储材料。冶炼元素成分为Ti17Sb31.2Te46.8O5的合金。将Ti17Sb31.2Te46.8O5合金置于溅射腔内的靶材位置。将基材置于溅射腔内的样品台上。向Ti17Sb31.2Te46.8O5合金施加溅射功率，产生溅射辉光。由此，将Ti17Sb31.2Te46.8O5合金溅射到基材上，制备得到Ti17Sb31.2Te46.8O5相变存储材料。
实施例10
制备元素成分为Ti14Sb31.2Te46.8Si8的相变存储材料。冶炼元素成分为Ti14Sb31.2Te46.8Si8的合 金。将Ti14Sb31.2Te46.8Si8合金置于溅射腔内的靶材位置。将基材置于溅射腔内的样品台上。向Ti14Sb31.2Te46.8Si8合金施加溅射功率，产生溅射辉光。由此，将Ti14Sb31.2Te46.8Si8合金溅射到基材上，制备得到Ti14Sb31.2Te46.8Si8相变存储材料。
上文示例介绍了本申请实施例提供的相变存储材料的制备方案。接下来，介绍本申请实施例提供相变存储材料的疲劳寿命、热稳定性的相关数据。
采用透射电镜分别观察实施例1制备的相变存储材料和实施例2制备的相变存储材料，结果分别如图5A所示和图5B所示。可见，当Ti在相变存储材料中的原子百分比为8％时，有的晶粒尺寸为几十nm。当Ti在相变存储材料中的原子百分比增加到28％时，晶粒尺寸可以降低到10nm以内。这表明，Ti可以降低相变存储材料中的晶粒尺寸，使得晶粒尺寸分布更为均匀(可以理解，晶粒尺寸越小，晶粒尺寸分布范围越小，使得晶粒尺寸分布越均匀)，从而可以减少或者避免因晶粒尺寸不均匀而导致的相变存储材料的疲劳寿命较短。换言之，当Ti在相变存储材料中的原子百分比较高(例如28％)时，相变存储材料的疲劳寿命较高。
测量实施例1制备的相变材料在不同温度下的电阻。结果如图6中曲线601a和曲线601b所示。其中，曲线601a是升温曲线，曲线601b是降温曲线。
测量实施例2制备的相变材料在不同温度下的电阻。结果如图6中曲线602a和曲线602b所示。其中，曲线602a是升温曲线，曲线602b是降温曲线。
测量实施例3制备的相变材料在不同温度下的电阻。结果如图6中曲线603a和曲线603b所示。其中，曲线603a是升温曲线，曲线603b是降温曲线。
其中，降温曲线表示降温过程中，电阻的变化。升温曲线用于表示升温过程中，电阻的变化。其中，如图6所示，在本申请实施例制备的相变存储材料的在升温过程中，电阻降低，表示相变存储材料在进行结晶。在相变存储材料的降温过程中，相变存储材料的电阻基本不变，表示结晶已完成。
并且，从图6中，可以看到随着Ti浓度增加，相变存储材料的初始电阻变低，同时结晶温度升高，其中，电阻下降最快的位置的横坐标为结晶温度。具体而言，实施例1制备的相变材料的结晶温度在210℃左右，实施例2制备的相变材料的结晶温度在240℃左右，实施例3制备的相变材料的结晶温度在260℃左右。另外，初始电阻是指图6中各曲线上最小温度对应的电阻。
从图6可知，本申请实施例在相变存储材料中添加Ti，提高了相变存储材料的结晶温度，即提高了相变存储材料的热稳定性。
上文介绍本申请实施例提供的相变存储材料的元素成分、制备方法以及性能。接下来，介绍本申请实施例提供的相变存储材料所参与形成的相变存储芯片。
本申请实施例提供的相变存储芯片可以包括相变存储单元存储阵列和外围电路。具体可以参考上文对图2所示实施例的介绍，在此不再赘述。
相变存储单元阵列可以由多个相变存储单元组成。在一些实施例中，相变存储单元的结构可以参考图1A所示的结构实现。在一些实施例中，相变存储单元的结构可以参考图1B所示的结构实现。回到图1A或图1B，相变存储单元110中的相变层113可以为本申请实施例提供的相变存储材料。电极的材质可以为金属材料、或非金属材料，或金属氮化物等。更具体地，电极1的材质可以为钨(W)、碳(C)、钽Ta、氮化钛(TiN)、氮化钽(TaN)等中的一种或至少两种的组合。本申请实施例对电极的材质不做具体限定。
在实施例a中，相变存储单元110还可以包括缓冲层114。缓冲层114和相变层113接触，并且也位于电极111和电极112之间。在一个说明性示例中，缓冲层114的材质可以为 碳(C)等非金属。在一个说明性示例中，缓冲层114的材质可以为碳(C)等非金属。在一个说明性示例中，缓冲层114的材质可以为W、Ta、Ti等金属。在一个说明性示例中，缓冲层114的材质可以为TiN、TaN等金属氮化物。在一个说明性示例中，缓冲层114的材质可以为Zr、Cr、Al、Sc、Y、Ta、Hf、Er、In、Ge、Bi、Ti、Ga、Sn等金属的碲化物。
在相变存储单元110中引入与相变层113接触的缓冲层114，可以进一步提升相变层113的性能。具体而言，当缓冲层114的材质为碳(C)等非金属时，缓冲层114可以提高相变层113的隔热效果，降低相变存储单元的操作功耗，同时可以避免相变层113中的元素扩散，并将增加相变层和电极之间的黏附效果。当缓冲层114的材质为Zr、Cr、Al、Sc、Y、Ta、Hf、Er、In、Ge、Bi、Ti、Ga、Sn等金属的碲化物时，缓冲层114可以作为相变存储材料的结晶模板，可以加速相变存储材料从非晶态向晶态的转换速度，从而可以降低相变存储操作单元110的操作时延，并且可以提高相变存储单元110的加热效率，降低相变存储单元110的操作功耗。当缓冲层114的材质为W、Ta等金属时，缓冲层114可以避免相变存储材料中元素扩散，也可以增加相变层和电极之间的黏附效果。当缓冲层114的材质为金属氮化物时，缓冲层114可以增加相变层和电极之间的粘附效果、提升相变存储材料的加热效率、减小电阻漂移、以及修复相变存储材料界面空洞，并将增加相变层和电极之间的黏附效果等。
上文介绍了缓冲层114的材质和功能。接下来，示例介绍缓冲层114和相变层113的之间位置关系。
在实施例a的一个说明性示例中，参阅图7A，缓冲层114与相变层113接触，且缓冲层114位于相变层113和电极111之间。
在实施例a的另一个说明性示例中，参阅图7B，缓冲层114与相变层113接触，且缓冲层114位于相变层113和电极112之间。
在实施例a的又一个说明性示例中，参阅图7C，相变存储单元110包括两个缓冲层114，每个缓冲层114均与相变层113接触。其中一个缓冲层114位于相变层113和电极111之间，另一个缓冲层114位于相变层113和电极112之间。两个缓冲层114的材质可以相同，也可以不同。示例性的，两个缓冲层114的材质均为碳(C)等非金属，或W、Ta等金属，或者TiN、TaN等金属氮化物，或者Zr、Cr、Al、Sc、Y、Ta、Hf、Er、In、Ge、Bi、Ti、Ga、Sn等金属的碲化物。示例性的，两个缓冲层114中的一个的材质为碳(C)等非金属，另一个的材质为碳(C)等非金属；或者，一个的材质为TiN、TaN等金属氮化物，另一个的材质为碳(C)等Zr、Cr、Al、Sc、Y、Ta、Hf、Er、In、Ge、Bi、Ti、Ga、Sn等金属的碲化物；等等，此处不再一一列举。两个缓冲层114的材质不同，从而使得相变存储单元110可以兼具两种材质对应的优势。
在实施例a的又一个说明性示例中，参阅图7D，相变层113具有凹槽，缓冲层114位于相变层113的凹槽中，且和相变层113接触。也就是说，相变层113环绕缓冲层114。
在实施例a的又一个说明性示例中，参阅图7E，缓冲层114具有凹槽，相变层113位于缓冲层114的凹槽中，且和缓冲层114接触。也就是说，缓冲层114环绕相变层113。
上文以图7A-图7E所示的结构为例，举例介绍了相变层113和缓冲层114的位置关系，但并非穷举。在其他实施例中，相变层113和缓冲层114还可以具有其他位置关系，在此不再一一列举。
在实施例b中，相变存储单元110还可以包括至少一个硫系化合物层115和至少一个相变层113。至少一个相变层113和所述至少一个硫系化合物层115交错堆叠，且均位于电极111和电极112之间。
在实施例b的一个说明性示例中，硫系化合物层115的材质可以为金属硫化物，例如GeSx。
在实施例b的另一个说明性示例中，硫系化合物层115的材质可以为金属Te化物，例如TiTe2、HfxTey、ZrxTey。
在实施例b的又一个说明性示例中，硫系化合物层115的材质本身也可以为相变存储材料，例如SbxTey、GexSbyTez、GexTey、BixTey、InxTey等中的一种或至少两种的组合。其中，在前述化学式中，小标x、y、z分别代表对应原子的比例。
相变层113和硫系化合物层115的交错堆叠。不难理解的是，一个相变层113和相邻的一个硫系化合物层115之间具有界面，如此，相变层113和硫系化合物层115的交错堆叠可以为相变存储材料引入更多的界面，界面可以降低热传导，从而减少相变存储单元110的操作功耗、提高相变存储单元110的疲劳寿命。并且，硫系化合物的绝热性能好，可以减少相变存储单元110的操作功耗、提高相变存储单元110的疲劳寿命。以及，当硫系化合物层115的材质为TiTe2等时，硫系化合物层115的晶格系数小于本申请实施例提高的相变存储材料的晶格系数，从而可以防止相变层113的元素扩散，提高相变层113或者说相变存储单元110的疲劳寿命。
在实施例b的又一个说明性示例中，参阅图8A，在从电极111到电极112的方向上，至少一个硫系化合物层115和至少一个相变层113的交错叠堆或者说周期性排列，可以从相变层113开始，到硫系化合物层115结束，形成n个周期性重复叠加。其中，n为大于或等于1的整数。
在实施例b的又一个说明性示例中，参阅图8B，在从电极111到电极112的方向上，至少一个硫系化合物层115和至少一个相变层113的交错叠堆或者说周期性排列，可以从硫系化合物层115开始，到相变层113结束，形成n个周期性重复叠加。其中，n为大于或等于1的整数。其中，n为大于或等于1的整数。
在实施例b的又一个说明性示例中，参阅图8C，在从电极111到电极112的方向上，至少一个硫系化合物层115和至少一个相变层113的交错叠堆或者说周期性排列，可以以相变层113开始，以相变层113结束。在开始位置的相变层113和结束位置的相变层113之间，具有形成n个周期性重复叠加的硫系化合物层115和相变层113。并且，在相变存储单元11中，两个相变层113之间至少间隔一个硫系化合物层115，两个硫系化合物层115之间至少间隔一个相变层。其中，n为大于或等于1的整数。其中，n为大于或等于1的整数。
在实施例b的又一个说明性示例中，参阅图8D，在从电极111到电极112的方向上，至少一个硫系化合物层115和至少一个相变层113的交错叠堆或者说周期性排列，可以以硫系化合物层115开始，以硫系化合物层115结束。在开始位置的硫系化合物层115和结束位置的硫系化合物层115之间，具有形成n个周期性重复叠加的相变层113和硫系化合物层115。并且，在相变存储单元11中，两个相变层113之间至少间隔一个硫系化合物层115，两个硫系化合物层115之间至少间隔一个相变层。其中，n为大于或等于1的整数。其中，n为大于或等于1的整数。
上文以图8A-图8D所示的结构为例，举例介绍了相变层113和硫系化合物层115的位置关系，但并非穷举。在其他实施例中，相变层113和硫系化合物层115还可以具有其他位置关系，在此不再一一列举。
参阅图9，本申请实施例提供了一种存储设备900，包括相变存储芯片910和控制器920。其中，相变存储芯片910可以用于存储数据，控制器920可以用于向相变存储芯片910写入数据或者从相变存储芯片910读取数据。其中，相变存储芯片910可以包括多个相变存储单 元110，该多个相变存储单元110在存储设备900中形成存储单元阵列。
在一些实施例中，相变存储芯片910可以参考上文对图2所示实施例的介绍实现。控制器920可以为具有数据处理能力的器件，用于控制相变存储芯片910的外围电路，实现向相变存储芯片910写入数据或者从相变存储芯片910读取数据。
参阅图10，本申请实施例提供了一种电子设备1000，可以包括处理器1010和存储设备900。其中，存储设备900可以用于存储数据，例如可以存储电子设备1000的应用程序、配置文件等。存储设备900可以为处理器1010提供数据存储空间，使得处理器1010可以向数据存储空间中写入数据。存储设备900存储的数据可供处理器1010读取或者说调用。处理器1010用于向存储设备900写入数据或者从存储设备900读取数据。具体而言，处理器1010可以通过控制器920，实现向相变存储芯片910写入数据或者从相变存储芯片910读取数据。示例性的，处理器1010可以调用存储设备900中的数据，实现电子设备1000的相应功能。
在一些实施例中，存储设备900可以作为电子设备1000的内存(memory)。在一些实施例中，存储设备900可以作为电子设备1000的外存储器。在一些实施例中，处理器1010可以为神经网络处理单元(neural-network processing unit，NPU)。在一些实施例中，存储设备900还可以为电子设备1000中其他形式的具有数据存储能力的装置。本申请不对存储设备900的实现形式做具体限定。
在一些实施例中，处理器1010可以为中央处理单元((central processing unit，CPU))。在一些实施例中，处理器1010可以为图形处理单元(graphics processing unit，GPU)。在一些实施例中，处理器1010可以为专用集成电路(application specific integrated circuit，ASIC)。在一些实施例中，处理器1010可以为神经网络处理单元(neural-network processing unit，NPU)。在一些实施例中，处理器1010还可以为电子设备100中其他形式的具有数据处理能力的装置。本申请不对处理器1010的实现形式做具体限定。
在一些实施例中，电子设备1010可以为服务器、移动终端(例如手机、平板电脑、笔记本电脑)或车载终端等。本申请实施例不对处理器1010和存储设备900所在的电子设备的实现形式做具体限定。
可以理解的是，以上实施例仅用以说明本申请的技术方案，而对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种相变存储材料，其特征在于，所述相变存储材料包括如式(1)所示的材料；
    TiaSbbTecDd    (1)；
    其中，a代表Ti的原子个数百分比，b代表Sb的原子个数百分比，c代表Te的原子个数百分比，d代表D元素的原子个数百分比，a+b+c+d＝1；
    3％≤a≤45％，且0.5≤(b：c)≤3；
    D为掺杂元素，0≤d≤15％。
  2. 根据权利要求1所述的相变存储材料，其特征在于，Ti的原子个数百分比a的取值范围为：20％≤a≤35％。
  3. 根据权利要求1或2所述的相变存储材料，其特征在于，Sb的原子个数百分比b比上Te的原子个数百分比c的比值为2：3。
  4. 根据权利要求1-3任一项所述的相变存储材料，其特征在于，所述掺杂元素D的原子个数百分比d为：3％≤d≤8％。
  5. 根据权利要求1-4任一项所述的相变存储材料，其特征在于，所述掺杂元素包括第一非金属元素、第一金属元素、所述第一金属元素的碲化物中的一种或至少两种的组合；其中，
    所述第一非金属元素为C、O、N、Si中的一种或至少两种的组合；
    所述第一金属元素为Zr、Cr、Al、Sc、Y、Ta、Hf、Er、In、Ge、Ga、Sn中的一种或至少两种的组合。
  6. 一种相变存储材料的制备方法，其特征在于，所述方法用于制备权利要求1-5任一项所述的相变存储材料，所述方法包括：
    使用第一沉积方式，按照式(1)所示的元素比例，制备所述相变存储材料；其中，所述第一沉积方式属于化学气相沉积CVD、物理气相沉积PVD、原子层沉积ALD中的一种；
    其中，TiaSbbTecDd   (1)；
    其中，a代表Ti的原子个数百分比，b代表Sb的原子个数百分比，c代表Te的原子个数百分比，d代表D元素的原子个数百分比，a+b+c+d＝1；
    3％≤a≤45％，且0.5≤(b：c)≤3；
    D为掺杂元素，0≤d≤15％。
  7. 一种相变存储芯片，其特征在于，包括：包括多个存储单元，所述多个存储单元形成存储单元阵列，每个存储单元包括：相变层、位于所述相变层一侧的第一电极和位于所述相变层另一侧的第二电极；所述相变层由权利要求1-5任一项所述的相变存储材料制成。
  8. 根据权利要求7所述的相变存储芯片，其特征在于，每个存储单元还包括：与所述相变层接触的缓冲层；其中，所述缓冲层由碳、第三金属、所述第三金属的氮化物、第四金属的碲化物中的一种制成；所述第三金属为W、Ta、Ti中的一种或至少两种的组合，所述第四金属为Zr、Cr、Al、Sc、Y、Ta、Hf、Er、In、Ge、Bi、Ti、Ga、Sn中的一种或至少两种的 组合。
  9. 根据权利要求7或8所述的相变存储芯片，其特征在于，所述每个存储单元还包括至少一个相变层和至少一个硫系化合物层；其中，所述至少一个相变层和所述至少一个硫系化合物层均位于所述第一电极和所述第二电极之间，且所述至少一个相变层和所述至少一个硫系化合物层交错堆叠。
  10. 根据权利要求9所述的相变存储芯片，其特征在于，所述硫系化合物层的晶格系数小于SbTe的晶格系数。
  11. 一种存储设备，所述存储设备包括控制器及权利要求9-10中任一项所述的相变存储芯片，所述相变存储芯片用于存储数据，所述控制器用于向所述相变存储芯片写入数据或者从所述相变存储芯片读取数据。
  12. 一种电子设备，包括处理器及权利要求11所述的存储设备，所述存储设备用于存储数据，所述处理器用于向所述存储设备写入数据或者从所述存储设备读取数据。
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